From 45110a0fe81ebdc27d3fd797ae8ffdd0e5dfdd79 Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Wed, 3 Apr 2013 18:03:31 +0530 Subject: mmc: sdhci-msm: Fix issue with MSM bus bandwidth voting The driver is using wrong clock rate to calculate the required bandwidth and due to this voting is happening for more bandwidth than it is required. This is ultimately preventing system core voltage from entering into low power mode. The sdhci_host clock indicates the clock rate as requested by MMC core layer and the actual rate that is set is indicated by clk_rate within struct sdhci_msm_host. As of now, sdhci_host clock is being used to calculate the bandwidth whereas bus-bw-vectors-bps indicates only supported bandwidths and hence a mismatch. Fix this by using the right clock rate which is clk_rate within struct sdhci_msm_host. Change-Id: If7d81e44a9b479c4c8e9fbaa7e092af2afb9cb9f Signed-off-by: Sahitya Tummala --- drivers/mmc/host/sdhci-msm.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 6fe66c936e5f..8636a4f12474 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1184,9 +1184,12 @@ out: static unsigned int sdhci_get_bw_required(struct sdhci_host *host, struct mmc_ios *ios) { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_msm_host *msm_host = pltfm_host->priv; + unsigned int bw; - bw = host->clock; + bw = msm_host->clk_rate; /* * For DDR mode, SDCC controller clock will be at * the double rate than the actual clock that goes to card. -- cgit v1.2.3