From 29f6dc4448db2b3316445ea26a96b876b604a33d Mon Sep 17 00:00:00 2001 From: Ryan Wang Date: Sun, 22 Mar 2015 23:09:43 +0800 Subject: qcacld: hif_sdio: force to select driver strength This change is required by HW team to solve the SDIO bus CRC error found in stress test. It forces to select driver strength type D in device initialization function. Change-Id: I1e8f594a4330c4b52a82bc5dafd068ea19961b26 CRs-Fixed: 799171 --- CORE/SERVICES/HIF/common/hif_sdio_common.h | 9 +++- CORE/SERVICES/HIF/sdio/linux/native_sdio/src/hif.c | 50 +++++++++++++++++++++- 2 files changed, 57 insertions(+), 2 deletions(-) diff --git a/CORE/SERVICES/HIF/common/hif_sdio_common.h b/CORE/SERVICES/HIF/common/hif_sdio_common.h index a5796497c40a..6e2e78b619c0 100644 --- a/CORE/SERVICES/HIF/common/hif_sdio_common.h +++ b/CORE/SERVICES/HIF/common/hif_sdio_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -199,4 +199,11 @@ static INLINE void SetExtendedMboxWindowInfo(A_UINT16 Manfid, HIF_DEVICE_MBOX_IN #define CCCR_SDIO_ASYNC_INT_DELAY_LSB 0x06 #define CCCR_SDIO_ASYNC_INT_DELAY_MASK 0xC0 +/* Vendor Specific Driver Strength Settings */ +#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR 0xf2 +#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_MASK 0x0e +#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A 0x02 +#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C 0x04 +#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D 0x08 + #endif /*HIF_SDIO_COMMON_H_*/ diff --git a/CORE/SERVICES/HIF/sdio/linux/native_sdio/src/hif.c b/CORE/SERVICES/HIF/sdio/linux/native_sdio/src/hif.c index 85c5e03449e1..810bae0930ce 100644 --- a/CORE/SERVICES/HIF/sdio/linux/native_sdio/src/hif.c +++ b/CORE/SERVICES/HIF/sdio/linux/native_sdio/src/hif.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -148,6 +148,7 @@ module_param(reset_sdio_on_unload, int, 0644); A_UINT32 nohifscattersupport = 1; +A_UINT32 forcedriverstrength = 1; /* force driver strength to type D */ /* ------ Static Variables ------ */ static const struct sdio_device_id ar6k_id_table[] = { @@ -1300,6 +1301,53 @@ TODO: MMC SDIO3.0 Setting should also be modified in ReInit() function when Powe unsigned char speed = 0; #endif sdio_claim_host(func); + + /* force driver strength to type D */ + if (((id->device & MANUFACTURER_ID_AR6K_BASE_MASK) == + MANUFACTURER_ID_QCA9377_BASE && forcedriverstrength == 1)) { + unsigned int addr = SDIO_CCCR_DRIVE_STRENGTH; + unsigned char value = 0; + A_UINT32 err = Func0_CMD52ReadByte(func->card, addr, &value); + if (err) { + printk("Read CCCR 0x%02X failed: %d\n", + (unsigned int) addr, + (unsigned int) err); + } else { + value = (value & + (~(SDIO_DRIVE_DTSx_MASK << SDIO_DRIVE_DTSx_SHIFT))) | + SDIO_DTSx_SET_TYPE_D; + err = Func0_CMD52WriteByte(func->card, addr, value); + if (err) { + printk("Write CCCR 0x%02X to 0x%02X failed: %d\n", + (unsigned int) addr, + (unsigned int) value, + (unsigned int) err); + } else { + addr = CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR; + value = 0; + err = Func0_CMD52ReadByte(func->card, addr, &value); + if (err) { + printk("Read CCCR 0x%02X failed: %d\n", + (unsigned int) addr, + (unsigned int) err); + } else { + value = (value & + (~CCCR_SDIO_DRIVER_STRENGTH_ENABLE_MASK)) | + CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A | + CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C | + CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D; + err = Func0_CMD52WriteByte(func->card, addr, value); + if (err) { + printk("Write CCCR 0x%02X to 0x%02X failed: %d\n", + (unsigned int) addr, + (unsigned int) value, + (unsigned int) err); + } + } + } + } + } + if (writecccr1) { A_UINT32 err = Func0_CMD52WriteByte(func->card, writecccr1, -- cgit v1.2.3