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2015-03-27CLK: Add binding document for Pistachio clock controllersAndrew Bresticker
Add a device-tree binding document describing the four clock controllers present on the IMG Pistachio SoC. Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: James Hartley <james.hartley@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Damien Horsley <Damien.Horsley@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Patchwork: https://patchwork.linux-mips.org/patch/9319/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-03-06ARM: dts: am43xx: fix SLEWCTRL_FAST pinctrl bindingDave Gerlach
According to AM437x TRM, Document SPRUHL7B, Revised December 2014, Section 7.2.1 Pad Control Registers, setting bit 19 of the pad control registers actually sets the SLEWCTRL value to slow rather than fast as the current macro indicates. Introduce a new macro, SLEWCTRL_SLOW, that sets the bit, and modify SLEWCTRL_FAST to 0 but keep it for completeness. Current users of the macro (i2c, mdio, and uart) are left unmodified as SLEWCTRL_FAST was the macro used and actual desired state. Tested on am437x-gp-evm with no difference in software performance seen. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-03-06ARM: dts: am33xx: fix SLEWCTRL_FAST pinctrl bindingDave Gerlach
According to AM335x TRM, Document spruh73l, Revised February 2015, Section 9.2.2 Pad Control Registers, setting bit 6 of the pad control registers actually sets the SLEWCTRL value to slow rather than fast as the current macro indicates. Introduce a new macro, SLEWCTRL_SLOW, that sets the bit, and modify SLEWCTRL_FAST to 0 but keep it for completeness. Current users of the macro (i2c and mdio) are left unmodified as SLEWCTRL_FAST was the macro used and actual desired state. Tested on am335x-gp-evm with no difference in software performance seen. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-02-02clk: tegra: Define PLLD_DSI and remove dsia(b)_muxMark Zhang
PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock. So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
2015-02-02clk: tegra: split Tegra124 clock header filePaul Walmsley
Split the Tegra124 clock macros into two files: 1. Clock macros common to both Tegra124 and Tegra132 2. Clock macros specific to Tegra124 This was requested by Thierry in Message-ID <20140716072539.GD7978@ulmo>. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com>
2015-01-29clk: exynos5420: Add IDs for clocks used in DISP1 power domainJavier Martinez Canillas
When a power domain is powered off on Exynos5420 SoC, the input clocks of the devices attached to this power domain are re-parented to oscclk and restored to the original parent after powering on the power domain. So a reference to the input and parent clocks for the devices attached to a power domain are needed to be able to do the re-parenting. The DISP1 pd includes modules which uses the following clocks: ACLK_200_DISP1 (MIXER and HDMILINK) ACLK_300_DISP1 (FIMD1) ACLK_400_DISP1 (Internal Buses) Each of these clocks are generated as the output of a clock mux so add an ID for all of these clock muxes and their parents to be referenced in the DISP1 power domain device node. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-01-28DT: iio: vadc: document dt bindingStanimir Varbanov
Document DT binding for Qualcomm SPMI PMIC voltage ADC driver. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
2015-01-28clk: samsung: exynos4: Add divider clock id for memory bus frequencyChanwoo Choi
This patch adds the divider clock id for Exynos4 memory bus frequency. The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling) feature of the exynos memory bus. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-27clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driverStephen Boyd
Add an LCC driver for MSM8960/APQ8064 that supports the i2s, slimbus, and pcm clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27dt-bindings: Add #defines for IPQ806x lpass clock controlRajendra Nayak
Add defines to make more human readable numbers for the lpass clock controller found on IPQ806x SoCs. Also remove the PLL4 define in gcc to avoid #define conflicts because that clock doesn't exist in gcc, instead it lives in lcc. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Split off into separate patch] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-26pinctrl: add driver for Amlogic Meson SoCsBeniamino Galvani
This is a driver for the pinmux and GPIO controller available in Amlogic Meson SoCs. It currently supports only Meson8, however the common code should be generic enough to work also for other SoCs after having defined the proper set of functions and groups. GPIO interrupts are not supported at the moment due to lack of documentation. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-01-24thermal: exynos: Provide thermal_exynos.h file to be included in device tree ↵Lukasz Majewski
files This patch is a preparatory patch to be able to read Exynos thermal configuration from the device tree. It turned out that DTC is not able to interpret enums properly and hence it is necessary to #define those values explicitly. For this reason the ./include/dt-bindings/thermal/thermal_exynos.h file has been introduced. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
2015-01-22mfd: devicetree: bindings: Add Qualcomm RPM DT bindingBjorn Andersson
Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660, 8960 and 8064 based devices. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2015-01-22clk: rockchip: add id for watchdog pclk on rk3288Heiko Stuebner
Adds a new id for the pclk supplying the watchdog on rk3288 socs. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org>
2015-01-21ARM: sunxi: DT: Convert the DTs to use a header for the pinctrl nodesMaxime Ripard
The pinctrl nodes require some extra opaque arguments for the pull up and drive strength values. Introduce a new header file and convert the device trees to replace these opaque numbers by defines. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-21ARM: sunxi: DT: Convert the DTs to use a header for the DMA argumentsMaxime Ripard
The DMA engine for the A10/A20 and derivatives require an opaque extra argument. Add a dt-bindings header, and convert the device trees to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-20ARM: clk: add clk-asm9260 driverOleksij Rempel
Provide CLK support for Alphascale ASM9260 SoC. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-19ARM: dts: Add minimal support for dm8168-evmTony Lindgren
This allows booting the device with basic functionality. Note that at least on my revision c board the DDR3 does not seem to work properly and only some of the memory can be reliably used. Also, the mainline u-boot does not seem to properly initialize the ethernet, so I've been using the old TI u-boot at: http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=summary Cc: Brian Hutchinson <b.hutchman@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-01-16ARM: dts: Add STiH418 SoC supportMaxime COQUELIN
The STiH418 is advanced UHD 60fps AVC processor with 3D graphic acceleration and quad-core ARM Cortex A9 CPU. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-01-15clk: samsung: exynos7: add clocks for audio blockPadmavathi Venna
Add required clk support for I2S, PCM and SPDIF. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-15clk: samsung: exynos7: add clocks for SPI blockPadmavathi Venna
Add clock support for 5 SPI channels. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-15clk: samsung: exynos7: add gate clock for DMA blockPadmavathi Venna
Add support for PDMA0 and PDMA1 gate clks. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-14ASoC: samsung: i2s: Add clk provider DT binding documentationSylwester Nawrocki
The new DT properties required for the I2S device node to be referred as a clock provider and corresponding clock indices definition is added. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-01-13ARM: dt: GIC: Spelling s/specific/specifier/, s/flaggs/flags/Geert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Stephen Warren <swarren@nvidia.com> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
2015-01-13ARM: imx: clk-vf610: Add clock for SNVSSanchayan Maity
Add support for clock gating of the SNVS peripheral. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-12clk: rockchip: add clock IDs for the PVTM clocksHuang Lin
Process-Voltage-Temperature Monitor has two clocks, PVTM_CORE and PVTM_GPU. Signed-off-by: Huang Lin <hl@rock-chips.com> Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-01-12clk: rockchip: add clock ID for usbphy480m_srcKever Yang
There are 3 different parent clock from different usbphy, all of them are fixed 480MHz, it is not able to auto select by clock core to the 2nd and the 3rd parent. For different use case for different board, we may need to select different usbphy clock out as parent manually. Add the clock ID for it so that we can use in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-31GMAC: define clock ID used for GMACRoger Chen
changes since v2: 1. remove SCLK_MAC_PLL Signed-off-by: Roger Chen <roger.chen@rock-chips.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-23clk: samsung: exynos7: Add required clock tree for USBVivek Gautam
Adding required gate clocks for USB3.0 DRD controller present on Exynos7. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-23clk: samsung: exynos7: Add clocks for MSCL blockTony K Nadackal
Add clock support for the MSCL block for Exynos7. Signed-off-by: Tony K Nadackal <tony.kn@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-23ARM: shmobile: r8a7791: add MLB+ clockAndrey Gusakov
Add MLB+ clock to R8A7791 device tree. Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com> [Sergei: rebased, renamed, added changelog] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-12-23ARM: shmobile: r8a7790: add MLB+ clockAndrey Gusakov
Add MLB+ clock to R8A7790 device tree. Signed-off-by: Andrey Gusakov <andrey.gusakov@cogentembedded.com> [Sergei: rebased, renamed, added changelog] Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-12-21ARM: shmobile: r8a7794: Add MMCIF clock to device treeShinobu Uehara
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> [horms: omitted device node; only add clock] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-12-21ARM: shmobile: r8a7794: Add SDHI clocks to device treeShinobu Uehara
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> [horms: omitted device nodes; only add clock] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-12-21ARM: shmobile: r8a7794: Add I2C clocks to device treeKoji Matsuoka
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> [horms: omitted device nodes and aliases; only add clocks] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2014-12-21ARM: shmobile: r8a7794: Add QSPI clock to device treeHisashi Nakamura
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> [horms: omitted device node and alias; only add clock] [horms: use clock-indicies instead of renesas,clock-indicies] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2014-12-21ARM: shmobile: r8a7794: Add SYS-DMAC clocks to device treeHiroyuki Yokoyama
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> [horms: resolved conflicts] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2014-12-21ARM: shmobile: r8a7791: Add IPMMU-SGX clock to device treeRyo Kataoka
Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> [horms: resolved conflicts] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-12-21ARM: shmobile: sh73a0: Add CPG register bits headerUlrich Hecht
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-12-21ARM: shmobile: r8a7794: Add USBDMAC[01] clocks to device treeKazuya Mizuguchi
Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> [horms: merged per-clock patches] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2014-12-21ARM: shmobile: r8a7794: Add USB clocks to device treeShinobu Uehara
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> [horms: resolved conflicts] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2014-12-10thermal: Fix cdev registration with THERMAL_NO_LIMIT on 64bitPunit Agrawal
The size of unsigned long varies between 32 and 64 bit systems while the size of phandle arguments is always 32 bits per parameter. On 64-bit systems, cooling devices registered via of-thermal apis fail to bind when the min/max cooling state is specified as THERMAL_NO_LIMIT (-1UL) as there is a mis-match between the value read from the device tree (32bit) and the pre-processor define (64bit). As we're unlikely to need cooling states larger than 32 bits, and for consistency with the size of phandle arguments, explicitly limit THERMAL_NO_LIMIT to 32 bits. Reported-by: Hyungwoo Yang <hwoo.yang@gmail.com> Acked-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
2014-12-04memory: Add NVIDIA Tegra memory controller supportThierry Reding
The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-28clk: rockchip: add bindings for the mmc clocksAlexandru M Stan
These clocks represent the physical clocks (including phases) and they will later be used for clock phase tuning. Suggested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-28clk: rockchip: rk3288 export i2s0_clkout for use in DTSonny Rao
This exposes the clock that comes out of the i2s block which generally goes to the audio codec. Signed-off-by: Sonny Rao <sonnyrao@chromium.org> [removed CLK_SET_RATE_PARENT from original patch] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-26clk: rockchip: add binding ID for DMC (memory controller) clocks on rk3288Jeff Chen
The DMC clocks need to be turned off at runtime, so we should have IDs so we can export them. Signed-off-by: Jeff Chen <cym@rock-chips.com> [dianders: split into two patches; adjusted commit msg] Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-26clk: tegra: Implement memory-controller clockThierry Reding
The memory controller clock runs either at half or the same frequency as the EMC clock. Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-26phy: add support for USB cluster on the Armada 375 SoCGregory CLEMENT
The Armada 375 SoC comes with an USB2 host and device controller and an USB3 controller. The USB cluster control register allows to manage common features of both USB controllers. This commit adds a driver integrated in the generic PHY framework to control this USB cluster feature. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> [ kishon@ti.com : Made it to use the updated devm_phy_create API and soem cosmentic changes in Kconfig file.] Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Jason Cooper <jason@lakedaemon.net>
2014-11-24of: Add binding document for MIPS GICAndrew Bresticker
The Global Interrupt Controller (GIC) present on certain MIPS systems can be used to route external interrupts to individual VPEs and CPU interrupt vectors. It also supports a timer and software-generated interrupts. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8420/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-23ARM: imx53: clk: add ARM clockLucas Stach
The ARM clock is a virtual clock feeding the ARM partition of the SoC. It controls multiple other clocks to ensure the right sequencing when cpufreq changes the CPU clock rate. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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