summaryrefslogtreecommitdiff
path: root/include/dt-bindings/clock (unfollow)
Commit message (Collapse)Author
2017-05-15clk: msm: Fix dsi clock divider configurationRajkumar Subbiah
The MND values and the PLL output divider configuration does not match the recommended values. When setting DSI pixel clock rate the MND array is ordered in a way that the requested rate goes from highest to lowest. Since the recommendation is to divide the clocks as close to VCO as possible, the request should be from lowest to highest. So reversing the fraction array to match the recommendation. The VCO min max rates are currently forced after pll output divider which is also fixed. Change-Id: I3cb5163f9c8dd3723cdc58bd7e7980719e683f1b Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
2017-03-28clk: msm: gcc-8996: Add pinctrl clk for ln_bb_clkDevesh Jhunjhunwala
Add the pinctrl clock for ln_bb_clk to the GCC driver for MSM8996. CRs-Fixed: 1063062 Change-Id: If85a0dbb26e350588cbd6614c032bf208a205be2 Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
2017-03-22clk: msm: gcc-8996: Add pinctrl clk for ln_bb_clkDevesh Jhunjhunwala
Add the pinctrl clock for ln_bb_clk to the GCC driver for MSM8996. CRs-Fixed: 1063062 Change-Id: If85a0dbb26e350588cbd6614c032bf208a205be2 Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
2017-03-07clk: qcom: Add separate aggre2_noc clock voters for SDM660/630Taniya Das
Separate out the aggre2_noc voters so that individual voters could vote on these clocks and voter clock would aggregate the clock rates before sending a request to RPM. Change-Id: I8ef30af257d2f37ec5af6aa5e3d1b69e5ba8ec8c Signed-off-by: Taniya Das <tdas@codeaurora.org>
2017-02-21clk: qcom: Remove gcc_hmss_ahb_clk for sdm660Amit Nischal
The gcc_hmss_ahb_clk will be controlled by RPM. Remove all control of it from the HLOS clock driver. Change-Id: I26525787352cb0b85937cc005afba7c37a7989ff Signed-off-by: Amit Nischal <anischal@codeaurora.org>
2017-02-13clk: qcom: Clean up the MSM8996 multimedia clock controller (MMCC) driverOdelu Kukatla
Following list of changes have been made 1. Add the missing clocks in multimedia clock controller driver. Also clean up clock flags and parent info for few clocks. 2. Removing clocks which are not controlled by HLOS. 3. MMCC needs to vote for volatge level on rail for the clock frequencies, so add voltage voting in MMCC. 4. Initial rate configuration for MMPLLs. Change-Id: If3d84e52783651b611b624dbc60b18993c0f0b1a Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> Signed-off-by: Amit Nischal <anischal@codeaurora.org>
2017-02-09clk: msm: clock-gcc-8998: Remove control of the hmss_ahb_clk from LinuxDeepak Katragadda
The gcc_hmss_ahb_clk will be controlled by RPM. Remove all control of it from the Linux clock driver. Change-Id: I0a6885e286841eb3f2d31223da3d430dde21d975 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2017-02-07clk: qcom: Remove gcc_rx2_qlink_clkref_clk for sdm660Amit Nischal
The gcc_rx2_qlink_clkref_clk is not required by any client, so remove controlling the clock from HLOS clock driver. Change-Id: I20dbb38f3f0fcbcdb3974923f4a0b540153d3fde Signed-off-by: Amit Nischal <anischal@codeaurora.org>
2017-01-25clk: qcom: mdss: add support for MDSS DP PLL for SDM660Padmanabhan Komanduru
Model and configure MDSS Display Port PLL for SDM660 target. Add changes to define and register DP VCO, divider and mux clocks as per common clock infrastructure. Change-Id: Ice83e21323087e81e2f30998260be85120e41fa8 Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
2017-01-19ASoC: audio-ext-clk: add parent to div and lnbb clksYeleswarapu Nagaradhesh
Add parents to div_clk1 and ln_bbclk. And register both the clocks independently. Change-Id: Ic0435ebad533879e3e0648775956c91cc680644d Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
2017-01-18clk: qcom: Remove few graphics clock for sdm660Taniya Das
The gcc_gpu_bimc_gfx_src_clk and gcc_gpu_snoc_dvm_gfx_clk need to left at their default state of ON. Remove controlling them from the linux clock driver to avoid disabling them during late_init. Change-Id: Iefc033998bf87fcc98dfaa1b7321d9cc33dedd5e Signed-off-by: Taniya Das <tdas@codeaurora.org>
2017-01-17clk: qcom: Add support for GPLL0 active clock for CPUTaniya Das
CPU clocks would require to vote on active only instance of GPLL0, so add the clock and also update the parent names for the CPU clocks. Change-Id: Id8c7f76170a1cc94fe045b8ba975aaa42c4b3819 Signed-off-by: Taniya Das <tdas@codeaurora.org>
2017-01-10clk: qcom: Add support to register GPU rbcpr clocksTaniya Das
GPU RBCPR clocks needs to registered separately, as GFX CPR would require the rbcpr clocks to register the regulator handle. Change-Id: I59def76e7dd69600be8faf47eb867a97ab04739e Signed-off-by: Amit Nischal <anischal@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
2017-01-10clk: qcom: Fix clocks which are required to be always onTaniya Das
Following are the changes made: 1. Add CLK_IGNORE_UNUSED flag for some clocks which are not supposed to be disabled at late_init_level. 2. Fix clock measure debug mux value for mmcc clocks. 3. Add mmss_mdss_byte1_intf_div_clk for mdp. 4. Fix usb ref clocks to branch voted. Change-Id: I06396c73f7855acfac283abe576e0b4cc1a92bd5 Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-12-28msm: Rename msmfalcon/apqfalcon to sdm660/sda660Neeraj Upadhyay
Update the code name from msmfalcon/apqfalcon to sdm660/sda660. As part of this, update the filename containing "falcon" and files content containing "falcon". Change-Id: Iec85862251b9e1b4dcc8bdce8b214ce87c0049bc Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
2016-12-26clk: qcom: Add smd-rpm voter & voter branch clocks for MSM8996Amit Nischal
MSM8996 requires the voter & voter branch clocks to be available for clients to be able to enable/disable and set rate on these clocks. Also add support for keeping active set vote on mmssnoc and pnoc voter clocks. Change-Id: Ie596ddee60aac3e6fc996f9a3e8dc988b0f4aa88 Signed-off-by: Amit Nischal <anischal@codeaurora.org>
2016-12-25clk: qcom: Add voltage voting for MSM8996 GCC driverOdelu Kukatla
Global Clock Controller(GCC) needs to vote for volatge level on rail for the clock frequencies, so add voltage voting in GCC. Also clean up clock flags and parent info for few clocks. Change-Id: Ib4cc69afb32a7654bbdd98f2efff901729c4d3da Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
2016-12-22clk: qcom: Support CPU clock for OSM for common clock frameworkTaniya Das
Following list of changes have been made - Update the clock osm to register to common clock framework - Update clock ops as per common clock framework - cleanup unused function (clk_osm_setup_osm_was) - Fix tabs for macro definitions - Add clocks ids for power and perf clock for clients Change-Id: I389cc9e93a26a434be752cf74444d6c0985ff36d Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-12-20clk: qcom: Add new voter clocks for camss clocksTaniya Das
Add new voter clocks of camss_jpeg0 clocks which are required by camera client. Update the clock indexes for multimedia clocks for the same. Also update the clock ops for hardware control branch clocks. Change-Id: I4bc6608789b8b900e0af007d2ca24ba19f675cb7 Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-12-16clk: qcom: add common clock framework support for MDSS PLLSandeep Panda
Model and configure MDSS DSI PLL using upstream clock framework APIs. Add changes to define and register vco, divider, mux clcoks as per common clock infrastructure. Change-Id: Idc51070e2bb36d1a757d2714d2875a99901321a7 Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
2016-12-12clk: msm: clock-gpu-8998: Program the Droop Detector gfx_pdnDeepak Katragadda
In order to avoid leakage between the graphics and the CX rails, set the GPU_DD_WRAP_CTRL__GFX_PDN bit. Change-Id: I7b2e59606e73c467c2b862f0162a176611d7ae3d Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-12-07include: clock: remove ifdef from header fileMeng Wang
As audio-ext-clk.h is finally included in device tree and and using ifdef results in compilation failure. Delete ifdef from audio-ext-clk.h. CRs-Fixed: 1090500 Change-Id: Ib6f715c3f606770e7e0b1f0f84ab50e442398cd0 Signed-off-by: Meng Wang <mwang@codeaurora.org>
2016-11-22msm: 8998: Replace cobalt with 8998Runmin Wang
Update the code name from msmcobalt to msm8998. As a result, update the filename containing "cobalt" and files content containing "cobalt". CRs-Fixed: 1070840 Change-Id: I2c7b95e3e2a2fec7730724da9eeb86a39a77faf1 Signed-off-by: Runmin Wang <runminw@codeaurora.org> Signed-off-by: Kyle Yan <kyan@codeaurora.org> Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
2016-11-21clk: qcom: Add support for MMCC clock for MSMFalconTaniya Das
Add support for the multimedia clock controller found on MSMFalcon based devices. This should allow most clocks for multimedia peripherals which includes display, video, camera etc. Change-Id: If8aa0b094af5ff82fe66c95e3ef2f13632950d2e Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-11-16include: clock: Add audio external clock of_index extriesMeng Wang
Add clock of_idx entries for audio external clock registered to the qcom clock framework. Change-Id: Ie592d06d2e09c2e263a2e9485a42eafb368e49cc Signed-off-by: Meng Wang <mwang@codeaurora.org>
2016-10-20clk: msm: clock: Remove controlling some graphics clocks in LinuxDeepak Katragadda
The gcc_gpu_bimc_gfx_src_clk and gcc_gpu_snoc_dvm_gfx_clk need to left at their default state of ON. Remove controlling them from the linux clock driver to avoid disabling them during late_init. Change-Id: If3d964840362b6147ba7c9e26c4a3f5d20e5a557 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-10-13clk: qcom: Add support for the turing vote clocksTaniya Das
The turing hlos1 and hlos2 vote clocks is required to be enabled before accessing the turing SMMUs, so add support for the same. Change-Id: I9e4b0d7cc5f164b207a1a0e2c1ae24bdfd8fa063 Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-10-12clk: msm: mdss: fix DSI PLL post vco divider configurationAravind Venkateswaran
The post vco divider clock in the DSI PLL can only be configured to a fixed value of 1 or 4. Current implementation can result in the divider being set to any value between 1 and 4 which can result in failures while enabling the DSI pixel clock. Fix this by replacing the post vco divider with a fixed /1 and /4 dividers followed by a mux clock. CRs-Fixed: 1064277 Change-Id: I01bc7304e446c622849c678c64a3fd6881413e89 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
2016-10-07clk: qcom: Add support for GPU clocks for MSMFalconTaniya Das
Add support for the graphics clock controller found on MSMFalcon based devices. This should allow graphics clocks for GFX clients to be able to do clock functionality. Change-Id: I753b40d574a4afc2104a5c2bfe64b4831fbce8a0 Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-10-07ARM: dts: msm: Add and update the dummy clocks for MSMfalcon/MSMtritonAmit Nischal
For MSMfalcon and MSMtriton, clock consumers requires dummy rpmcc, gcc, mmss and gfx clocks for their operation so add the support for registering dummy clocks as follows: - Add clock-output-names property for the rpmcc, gcc, mmss and gfx clock controller nodes. - Add reset-cells property for clock controller nodes. - Add two fixed clock nodes named as xo_board and sleep_clk. - Remove RPM clock IDs from qcom,gcc-msmfalcon.h. - Modify RPM clock names as per qcom,rpmcc.h file. Change-Id: I06262fe271ab6ba81d4fa5f67315fd1b54edee8c Signed-off-by: Amit Nischal <anischal@codeaurora.org>
2016-09-29clk: qcom: Add support for GCC clock for MSMFalconTaniya Das
Add support for the global clock controller found on MSMFalcon based devices. This should allow most clocks for peripherals other than multimedia clocks. Change-Id: I1ec6309f32c658177580cc0601083d32bcdfad20 Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-09-29clk: qcom: Add support to register rpm-smd clocksAmit Nischal
Update the rpm-smd communication API to send across votes for clock enable/disable to RPM. Use the clk_hw list for the RPM clocks and also update the clock ids and clock names for RPM clocks. Change-Id: I37ae97f22b1b39d040bb78c90b1ff231bc348fe6 Signed-off-by: Amit Nischal <anischal@codeaurora.org>
2016-09-11clk: qcom: Clean up the MSM8996 Global Clock Control (GCC) driverOdelu Kukatla
Remove the RPM controlled clocks and add missing clocks. Also clean up clock flags and parent info for few clocks. Change-Id: I7ae55f992be29a28617070ca7792f912592c3628 Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
2016-09-07clk: msm: clock-osm: Add measurement support for CPU clocksDeepak Katragadda
Add support to measure the perf and power cluster clocks via the debug mux on MSMCOBALT. CRs-Fixed: 1059153 Change-Id: I1682481dfe22deef300ea9bd1db558ae634c9129 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-08-31clk: msm: gcc-cobalt: Add support for gcc_aggre1_ufs_axi_hw_ctl_clkDevesh Jhunjhunwala
Add support for controlling the hw_ctl bit of the gcc_aggre1_ufs_axi_clk CBCR. Change-Id: I856f2c76c3149f3704c47e6f8b0019805a1a0cd4 Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
2016-08-22clk: msm: mdss: update Dp PLL/Phy configurationChandan Uddaraju
Update the Display-Port PHY and PLL configuration with the recommended settings. Remove the support for 9.72Ghz VCO frequency. Update the divider settings to support the new frequency plan. Update the Phy Aux settings and voltage/pre-emphasis settings according to recommended configuration. Change-Id: Ic4d206da3dc6b45214e7601e7556cfb0bef81a7d Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
2016-08-22clk: msm: clock: Add voter clocks for mmss_camss_jpeg0_clkDeepak Katragadda
Add separate voter clocks for controlling the mmss_camss_jpeg0_clk from two clients on MSMCOBALT. CRs-Fixed: 1049594 Change-Id: I530e35054fd512574bca9e5937317099f58d2bb6 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-08-15clk: msm: gcc-cobalt: Remove support for wcss clocksDevesh Jhunjhunwala
The wcss clocks are not owned by APCS, and thus should not be modelled in the clock driver. CRs-Fixed: 1054449 Change-Id: I7677bef6a58c028876b72dbade37c1064b428ee2 Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
2016-08-12clk: msm: Add support for block reset clocks for msmcobaltTaniya Das
Add the block reset clocks which will be used by clients to assert/deassert these clocks using the reset controller framework. Change-Id: I19f4f6e764ffde26ecf3b7cce3fb53a9bf2cc91a Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-08-12clock: qcom: Update the list of clocks supported on MSMFalconTaniya Das
Add the new clocks and update the clock ids for GCC, GPU, MMSS clock controllers. Also add the RPM clocks which are supported and would be used by the clients for all clock operations for RPM controlled clocks. There are separate MMSS and GPU clock controllers, so add the dummy controllers for the same. Change-Id: I5a98b6128f5d54163ab5d03c4c023a748e6a4e95 Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-08-11clk: msm: clock: Control the GPLL0 input sources to MMSSCC and GPUCCDeepak Katragadda
GPLL0 input to the multimedia and graphics clock controllers can be managed by use of voting registers. Enable this usage and turn off the inputs when no clocks within these clock controllers need a GPLL0/GPLL0 divider input. CRs-Fixed: 1009689 Change-Id: Iea17649eb63522510cf7887a630d17a2f64a615b Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-08-10clk: msm: clock: Update clock frequencies on MSMCOBALTDeepak Katragadda
Update the graphics and multimedia clock frequencies and FMAXes to align with the v2 and vq frequency plans. While doing so, remove support for the gpu_pll1 PLL since it is not going to be used to generate any frequencies. CRs-Fixed: 1051170 Change-Id: I4d6547d95bd76d8ca6f4d729009d8b4a78716d5b Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-08-08clk: msm: Add support for block reset clocksTaniya Das
Add the block reset clocks which will be used by clients to assert/deassert these clocks using the reset controller framework. Change-Id: I3e9f7f85bf1faf0e1bb501196ba9d7e197111a03 Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-07-26clk: msm: clock: Remove support for the USB cfg_ahb2phy clock from HLOSDeepak Katragadda
The gcc_usb_phy_cfg_ahb2phy_clk clock will be managed by RPM. There is no need to model it in the linux clock driver or to control it from the USB driver. Change-Id: I05641c2d532ada36623da1e1cc687c90bc4ee906 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-07-16ASoC: aud-ext-clk: enable lnbbclk2 for tavilYeleswarapu Nagaradhesh
Tavil is sourced from lnbbclk2 and hence enable this clock for tavil codec. CRs-Fixed: 1041199 Change-Id: I5409b0f4ed58fefdd25abbe79f144de7e693c1a1 Signed-off-by: Yeleswarapu Nagaradhesh <nagaradh@codeaurora.org>
2016-07-15clk: msm: clock-gcc-cobalt: Remove support for gcc_bimc_hmss_axi_clkDeepak Katragadda
The gcc_bimc_hmss_axi_clk will be configured outside of HLOS. The linux clock driver does not need to manually enable it. CRs-Fixed: 1012646 Change-Id: Ib0b848fb410f4bf266b09cefed0e8bce7292d2ec Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-07-11clk: msm: clock-mmss-cobalt: Add display port clock supportDeepak Katragadda
Add support for the DP link and crypto clocks on MSMCOBALT. CRs-Fixed: 1028725 Change-Id: I6cdb366499f9589dff9a42491c7ff357e98d65c5 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
2016-07-05clock: qcom: Add the clocks supported on MSMFalconTaniya Das
Add all the clocks which are supported on msmfalcon and would be used by the clients for all clock operations for GCC, MMSS, GPU clock controllers. Change-Id: Ie328cb0516644d8a3d66fd0c054575a5cff637dc Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-06-23clk: qcom: rpmcc: Add rpm clock data for msm8996Rajendra Nayak
Add all RPM clock data for msm8996 family of devices ToDo: Adapt to changes needed for RPM over GLINK against RPM over SMD that the driver currently supports Change-Id: Ib095af601a4f03d866cf94c8e277d04630abb42b Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
2016-06-23clk: qcom: Add support for RPM ClocksGeorgi Djakov
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_rpm driver to communicate with RPM. Such platforms are apq8064 and msm8960. Change-Id: I1a73355bc9117c34589a25cf58446cad13ceb6e3 (cherry picked from commit 06d998a24c68be94685af38e8becfda3c8bf757b) Git-commit: 06d998a24c68be94685af38e8becfda3c8bf757b Git-repo: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-27 05:57:59 +0000