| Commit message (Collapse) | Author | Age |
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When resetting the mdp control there is a NULL check for left
mixer before calling pipe reset but the NULL check for right
mixer is missing causes a NULL pointer deferencing. This
change adds the NULL check.
Change-Id: Iebbc68c4016d8b13805187343eb7b657e8b76bcc
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
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Fix the power on/off sequence based on the
hw recommendation, where bimc smmu gdsc is
powered off after mdss gdsc; and for the
power on sequence the bimc smmu gdsc is
enabled before the mdss gdsc.
Change-Id: Iad005082bcdb07f5529cd5eafd6ecd9c250c9665
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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Current Display driver sets to true the ram status variable
shared with the RPM to prevent MMSS GDSC to go OFF only
when we are about to disable the MDSS GDSC regulator for the
Idle Screen scenario; The potential problem with this is that
there is a 4-vsyncs period of time between the end of the
display last transaction (ping pong done) and the release of
the MDSS GDSC regulator (for Idle Screen) where the Display
related clocks are already released and MDSS GDSC regulator
is still on (so rpm variable is still false), causing that Xo
shutdown (and therefore MMSS GDSC off) can happen while the
MDSS GDSC is still active during this period of time.
This change makes sure that any time that the MDSS GDSC
regulator is enabled or when the MDSS GDSC regulator is
disabled but the Display is still active but in Idle Screen,
Display sets the flag to ensure that the MMSS GDSC regulator
is not disabled by the RPM, flag is released once our MDSS
regulator is disabled for Suspend.
Also, re-arrange the sequence to make sure the change of
the flag happens after we disabled the MDSS GDSC regulator,
so we prevent that by any reason the MDSS GDSC could go off
before the MMSS GDSC regulator.
Change-Id: I141cb893c4e2a54f99e65383e69b4ce88ab4c761
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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The Gamut LUT size passed from user space needs to go through
a sanity check to avoid heap overflow. This patch adds the missing
sanity check in the Gamut LUT config write path.
Change-Id: I365938e06dbc6ca01961c9be01db10a5a9c863e4
Signed-off-by: Ping Li <pingli@codeaurora.org>
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Sequence to disable autorefresh when handoff is
done to the kernel is missing to wait for the
previous transaction to finish. This change
makes sure any previous on-going transaction
finishes before disabling autorefresh.
Change-Id: I547aea5cc82989d03963b2153e2561092fd7b36c
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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During secure to non secure transition the commit contains
only non-secure layers and there is no null commit in between.
This change correctly validates such commit and allows non secure layers
only and the driver then performs the functionality to transition to
non-secure state.
CRs-Fixed: 1110585
Change-Id: Ic1d32f0d04d8ee860844f59fd99707dbdb78838f
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
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Fix the HBR2 pattern generation by ensuring that the pattern
selection bit is not overwritten by a subsequent register write
that updates the scrambler reset count.
CRs-Fixed: 1108048
Change-Id: I2d2dcc79de82756eab015a343c24411a735947c9
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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For some use cases like running compliance test, it might
be necessary to disable hdcp. Add a sysfs node to allow
user to take action to enable/disable hdcp for such use
cases.
Change-Id: I8b9ae6d6d4e750be97fece172f635847ad2e05e4
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
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On receiving audio test request from sink, parse audio parameters
and send notifications to audio modules to start audio transmission.
CRs-Fixed: 1109812
Change-Id: Id17d82c5b9e1c4bf453f1f1421d2025b32aa410a
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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Allow each display client to issue multiple requests for audio only,
video only or both to address different use cases for the display
clients.
CRs-Fixed: 1109812
Change-Id: I38518cebb37da0a48ffd817af9246a7c9682b494
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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Fix the electrical compliance test sequence by bypassing
the link training whenever there is a request for a new
PHY test pattern. Link training triggers the sending of
training patterns which might differ from the requested
PHY test pattern. Furthermore, handle the state DP
transitions for power on/off since there is no userspace
interaction for the electrical compliance tests.
CRs-Fixed: 1108048
Change-Id: I9169b7645f7e039c8582993bf88976ff24eb6eca
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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Sink reports the maximum link rate that it supports as part of the
DPCD information. When calculating the link clock rate, ensure that
the calculated rate is always capped at the maximum rate supported
by the sink.
CRs-Fixed: 1109812
Change-Id: I563f3406606128b1bba705e6db33aa8ede8dbb7d
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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A sink uses the HPD IRQ signal to notify the source of for any
link maintenance, link tests and HDCP related messages. Current
implementation tears down the entire display pipeline when this
signal is received. This may not be necessary as it would be
needed to keep the DP interface enabled while any kind of link
maintenance is performed. Fix this and ensure that when handling
of the HPD IRQ is complete, re-establish the display pipeline.
CRs-Fixed: 1109812
Change-Id: Id93c3b147dd206e9718f49e2a053e3ee18162130
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Display Port (DP) controller has the ability to calculate CRC values
for every frame. In addition, most DP sinks also have the capability
to calculate per frame CRC values. Add support to enable/disable
calculation of per-frame CRC values for both the DP controller and
the DP sink. Add support to read the computed CRC values via a new
sysfs node. See below for usage instructions:
To enable/disable per frame CRC calculation:
* echo "ctl_cr_en=[0/1]" > /sys/class/graphics/<fbi>/frame_crc
* echo "sink_cr_en=[0/1]" > /sys/class/graphics/<fbi>/frame_crc
To read computed CRC values:
* cat /sys/class/graphics/<fbi>/frame_crc
CRs-Fixed: 1109812
Change-Id: I41271db64463b26cbbd9baba43d098bc30da33bf
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Add node named 'config' to let the user modules know
about the supported DisplayPort configurations. On
every cable connection, user modules can read this sysfs
node to configure accordingly. This sysfs node can also
be used to force a test pattern on the DP interface using
the following syntax:
echo "bpp=<bpp> pattern_type=<pattern>" > /sys/class/graphics/<fbi>/config
where
* bpp = [0/18/24/30]
* pattern_type = [0/1/2/3]
CRs-Fixed: 1109812
Change-Id: Ia2890e8c8e6214d4a1532f081d7c906484c99a03
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Add support for parsing parameters in the automated CTS mode when
the test type is set to TEST_VIDEO_PATTERN. The parameters parsed
are the color bit depth, colorimetry and the test pattern type.
Configure the source accordingly and transmit the requested
video pattern.
CRs-Fixed: 1109812
Change-Id: I552a50e86dc299b4cf7955992ad82dee19f35cbc
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Add a new API to override the EDID configuration. This will
allow clients to specify a particular resolution to be used
for subsequent connections.
CRs-Fixed: 1109812
Change-Id: Ie08ed509dd563bf265b32a2bfece86352b4e2b68
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Resolutions listed in the Detailed Timing Descriptor (DTD) have
detailed information about all the timings. Current implementation
attempts to match the parsed resolution with the resolution database
based on just the Video Information Code (VIC). This can potentially
overlook mismatches in certain parameters such as refresh rates and
can cause unintended results. Fix this by always adding the resolutions
parsed from the DTDs to the reserved timing list.
CRs-Fixed: 1109812
Change-Id: I8b926f08ce9b44c4a16a32fed26fedd351d77ae8
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Current implementation of the EDID parser always ensures that
VGA resolution (640x480) is added to the list of supported modes.
However, this should really be done by the client of the parser
based on their policies. This will avoid usecases where the EDID
parser would report the VGA resolution as supported even if it
was not listed in the sink's EDID.
CRs-Fixed: 1109812
Change-Id: Ic98314493029586d06a26a2c3a12b275ddaa8a8f
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Populate the required parameters for 640x480p59.94 resolution and
add this to the resolution database.
CRs-Fixed: 1109812
Change-Id: Ic600d81e81d695288abd7638112e2541df5b1197
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Add support to program the vertical sync (VSYNC) and
horizontal sync (HSYNC) polarity based on the sink's EDID.
This enables transmission of these parameters as part of
the Main Stream Attributes.
CRs-Fixed: 1109812
Change-Id: I10a91dd778e51abc8da4d4a8280a57b927cce590
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Current implementation utilizes a simple event queue to handle
some of the tasks when setting up or tearing down a display port
session. This is currently achieved using a workqueue and assumes
that there can be at most one unhandled event outstanding. This
may not be valid and can result certain events being skipped.
Refactor this by handling the events in a new event thread.
CRs-Fixed: 1109812
Change-Id: I2041fd2bbeadbfc7726a6c504ec3e373f34d2aea
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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EDID parser assigns temporary Video Identification Codes (VIC) for
all non-standard resolutions when parsing a sink's EDID. These
VICs can be reused for a subsequent connection for different
resolutions. In the current implementation of the Display Port (DP)
driver, a resolution change is detected whenever a new VIC is used.
However, when switching between two non-standard resolutions spanning
connections to two different sinks, it is possible to have the same
VIC assigned for the two resolutions. This can result in abnormal
behavior. Fix this by resetting the video identification code and panel
information to reset value every time we get an HPD for disconnect.
CRs-Fixed: 1099532
Change-Id: I4bb5a6b4329f67368ebbdc7fe8d92c2ea4605082
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Fix the return value for hpd sysfs write function
to avoid wrong data to propagate to the caller.
Change-Id: Ic2282496598ecba8511f3a0a826e152451394edb
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
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Fix the DTD (Detailed Timing Descriptor) parsing for block
1 (CEA extension block) to properly parse the resolution
details.
Change-Id: I5c1e448d5cdaf771c9e35479fe48067092c964e3
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
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Program the correct number of channels for header byte 3 in
audio stream to avoid issues related to audio channels.
Change-Id: I1de32403efc42d8fde8ac2096ae021e795707aae
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
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During authentication, HDCP may poll hardware for status.
HDCP may be turned off by other thread abruptly depending
on the use-case. Do not poll hardware in case HDCP has been
turned off. Also, wait for authenticating thread to finish
in hdcp off thread to avoid any race condition.
Change-Id: If2e4940310035f08d2077def4fa62620bef19942
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
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Transmit the link pattern first, update the drive settings
and then update the sink about the pattern and drive settings
using aux channel to avoid possible link training failures
with some sinks.
Change-Id: Ia8eccee99f58da94d3f1013f075c07400bde15f9
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
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Interrupts from sinks (cp_irq) may come asynchronously at different
states for HDCP authentications. In case HDCP has failed and an
interrupt is received from sink, do not process it to avoid getting
unnecessary failures.
Change-Id: I00b0d45fdbdc3d43ac49908db66573d6d4b58283
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
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When performing right-only update on a dual LM single display mode with
3D Mux enabled, the right mixer's ping pong buffer should be used.
Change-Id: Ib530d7503ca46a01198cc88de5312635bd84a6fb
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
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IGC length is same for all versions of igc.
Remove the check for igc version in igc read function.
Change-Id: Iaa3cc91db0b2ba6a3e3fb00eb0b1ea5405e0ef9b
CRs-fixed: 1109117
Signed-off-by: Gopikrishnaiah Anand <agopik@codeaurora.org>
Signed-off-by: Ping Li <pingli@codeaurora.org>
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Traffic shaper count for calculating high layer should include
low layer height along with low layer ypos. Fix the high layer end
value by adding height of the low layer.
Change-Id: Icbe1157d9506747d8670f4b7f66c183d98e920fe
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
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Make sure pll regulator is enabled as part of the phy
on sequence. This fixes some corruption observed
when pll is disabled as part of the phy shut-down
sequence.
Change-Id: I1ace97dbf5b8e5ed8fceedddf714758a5f708cfb
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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As per HDMI specification a source should try to re-read the EDID
in case there is error during the EDID buffer read, like checksum
mismatch or EDID header not correct. So retry for maximum allowed
attempts when EDID read fails due to any reason.
Change-Id: I04b222271cf22834dc0ea6355cd78a7492e24f27
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
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Some platforms may use external gpio to enable and disable backlight,
and we may need to invert this gpio according to HW design,
so add support for that.
CRs-Fixed: 1109294
Change-Id: Ib5e895eebcc38d185e8b703c3d895781b43c58c7
Signed-off-by: Yahui Wang <yahuiw@codeaurora.org>
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In the current implementation DSI timing db(Double Buffering)
mode is set as part of DSI controller initialization. This is
causing DSI command transfer failures when sending panel init
commands during device resume for some platforms like SDM660.
Since on these platforms DSI_CMD_OFFSET and DSI_CMD_LENGTH
register has now become double buffered and hence would need a
control flush, for these registers to take effect. But control
flush in driver does not happen until panel init is done properly.
So removing the programing of timing db registers from DSI host
initialization sequence as this is already taken care during dynamic
refresh rate change usecase.
Change-Id: Ia08788127f4d132530e3f3a28efd9d7ee9869483
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
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For split display panels, when panel has 180 flip or HFLIP,
the source layers needs to be swapped instead of the mixers.
SDM will take care of the source swap and rectangle
recalculations.
This change is to remove the mixer swap, and to expose the panel
flip property through sysfs, so that SDM can flip the source
layers to maintain pipe priority.
Change-Id: I47a7dd38dc1e45dd3f7edbd189c9403900b74eea
Signed-off-by: Krishna Chaitanya Devarakonda <kdevarak@codeaurora.org>
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