| Commit message (Collapse) | Author | Age |
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Update the EDID read sequence to first write the offset to
request the appropriate EDID block prior to reading the EDID
block data. In addition, write the correct segment address
when reading more than two extension blocks.
CRs-Fixed: 2006096
Change-Id: Ic4b2bd4d4cf9da5e247c5735b4e768b9e2b87b27
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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Retry AUX read/write transactions that have failed either due
to the AUX controller hardware indicating an error via the ISR,
or due to a software based timeout while waiting for transaction
completion. The transaction retry strategy is as follows: first
repeat the transaction using the same PHY AUX settings, and then
retry the transaction using updated PHY AUX settings if repeating
the transaction has failed.
CRs-Fixed: 2006096
Change-Id: Id9c3c7ae1ab320540545b9c178d947a3cd023079
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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Make the parsing of the AUX controller configurations more
extensible by adding support for multiple settings per configuration,
as well as the parsing of the register offsets. This enables the
extension to support different targets, and combinations of AUX
controller settings depending on the use case.
CRs-Fixed: 2006096
Change-Id: I4e6b623a4d9fafcfcc89477dfa57880eb798c350
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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Increase the AUX controller hardware timeout limits to the
maximum value supported. This increases the AUX controller
hardware's robustness in handling transactions in the face
of differing timing from one DisplayPort sink to another.
CRs-Fixed: 2006096
Change-Id: Ia0da13720526a96f3a88a849043a3ffbb1185cf7
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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Add interrupt handling for PHY AUX errors that might
happen during AUX communication. Read the interrupt
status and clear it before initiating the next AUX
transaction. This will help identify any issues that
result in AUX transaction failures.
CRs-Fixed: 2006096
Change-Id: I0733bfb163c8c3c108002fbe4309e36dc105ccb8
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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A branch device usually notifies a change in downstream connections
using the HPD IRQ pulse. Handle this by checking for a change in
downstream sink count and appropriately handling EDID reads. It is
also possible that the branch device may not have any local EDID.
In such cases, when the downstream sink count is zero, do not read
EDID.
CRs-Fixed: 1112711
Change-Id: I230560c995d7c3b395e37aef5483e5468e1d1dec
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Implement a failsafe mechanism that will prevent the DisplayPort
driver from entering an irrecoverable state in the face of
delayed power off/on events from the display framework. For example,
the driver must indefinitely postpone the handling of other events
from the sink until the power off event is complete, ensuring that
there is no interleaving of events that could lead to a bad state,
or un-clocked register access.
CRs-Fixed: 2006096
Change-Id: I1bfa887ba5ee94cbf44c87aa0d60766cafc854b4
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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EDID utility always lists the default resolution as part of the list
of available modes. If the client does not specify a default resolution
it can result in incorrect behavior. Ensure that the Display Port
driver always initialized with a default resolution.
CRs-Fixed: 2030915
Change-Id: Ib6c75d655e6fcbd5c792ca1aa9da6b08ba2f416e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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There are some cases where MDSS GSDC is not turned off after FB
PM suspend ever after clock ref count is 0 as runtime suspend
is not triggered. Ensure that MDSS GDCC is toggled in these
cases.
Change-Id: I33389ad736960b619b32a9bec4b2b157eed4d20b
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
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Since on some platforms DSI_CMD_OFFSET register has become
double buffered, so dynamic fps update and DSI DMA command
transfer can not happen at the same time. This changes makes
panel status check which in turn does a DSI DMA transfer, and
dfps update mutually exclusive.
Change-Id: If8591c55d31669dbf3f565db041c04bcd6cb616a
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
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In the current implementation DSI driver is masking the
fake ACK and overflow errors that might occur during if
BTA mechanism is used to check ESD. But if register read
mechanism is used to check ESD, then also embedded BTA will
be triggered and fake ACK and overflow errors might be
reported. Mask the same for register based ESD check also.
Change-Id: If1ee0a7cc0171b96a3b7298aa5201372c6eb8139
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
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After the pipes are unstaged during continuous splash
handoff the driver should wait for VSYNC to make sure
the changes are flushed before moving on. Currently it
sleeps for 20ms but this might not be enough especially
on low fps configurations causing pipe hang. Changing
that to wait for VSYNC interrupt instead.
Change-Id: Ic722a7d6c39c36084f35f55e7e899476e34f607f
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
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After cdm has been used, need to reset cdm block,
or the next HDMI device will be affected by the
cdm config.
Change-Id: I4eb879202cc3547d9149b3352377c3395ebfe6b3
Signed-off-by: zhaoyuan <yzhao@codeaurora.org>
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In command mode, the backlight level is set before the first commit
is completed. It shows a snowy screen after suspend resume. Wait for
one ping pong done to ensure commit is completed after suspend
resume before backlight level is set.
Change-Id: I2c6da73f3f84bcdf84e5b90c64f9ca05f0c27198
Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
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Add support to register smmu fault handler for MDSS
context banks to dump necessary debug information.
Change-Id: I955b4a33dbce0e66adee199e0a1272b25aa4392d
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
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Skip the transfer unit setup and the routine to wait for the
video ready interrupt as link training tests do not require
video frames to be sent.
CRs-Fixed: 2006096
Change-Id: Ibf9cda18f8740890f384b1d99f8d00b4692ab74d
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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LP_RX_TIMEOUT/BTA_TIMEOUT"
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The MDP timing generator line count check for DSI error recovery
from LP_RX_TIMEOUT/BTA_TIMEOUT needs to be performed after clearing
the FORCE_TX_STOP bits for DSI data/clock lanes and before enabling
back the DSI video mode engine. Update this sequence to recover the
MDP timing generator from halt state due to back pressure before
the check for line count.
Change-Id: I17ca4ed74e3e11f4e81108a33271f113117ab669
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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In split link panels, the four data lanes are split into
sublinks and the clock lane is shared among the sublink.
Add support for split link panels in mdss.
Change-Id: I40965c274a3591b0a00ca546052e7cb46967844d
Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
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As per HW recommendation, configure the SMART_PANEL_ALIGN_MODE
control to start of frame for command mode split display use
cases. This will avoid any issues related to the skew that can
develop between the 2 interfaces used for sending data to panel.
Change-Id: I067db541bf29a8ca8c6c395fe05b5e159e733476
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
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Do not send a connection notification to clients while processing
link training or electrical compliance requests. This is not
necessary as these tests do not require a video output from the
source device. Furthermore, we need to acknowledge/unblock the external
display module if the core and link clocks are already powered on
and we get an power on event. This will allow the driver to make
progress, for example, to send the test responses and requested
audio/video test patterns.
CRs-Fixed: 2006096
Change-Id: I7956248d8ae665290e770e0fd5b76a79c55cda1d
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
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mdss_mdp_dfps_update_params uses data as operand. Hence the values
are validated against their max values allowed to avoid any overflow
in this change.
Change-Id: I630b9390a18446cd461154e31e08642a8ff06ed8
Signed-off-by: Harsh Sahu <hsahu@codeaurora.org>
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Overfetch params passed by the libscaler are signed 8 bit values.
While calulcating the total fetch pixels decimation calculation should be
applied after adding the fetch values to the src rect. This change corrects
this calculation and typecasts fetch values to signed 8 bit integer.
There is no need to consider repeat values since repeat values are
set to 0 by libscaler.
CRs-Fixed: 2015444
Change-Id: Ia7b9c54385956444e1a88fd0746d8b90f15e5caf
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
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Fix an issue in the configuration of the gpio that controls
the backlight. Toggle the gpio properly during reset.
Change-Id: Ic177b7bbb69211449be386188e1c3154a95708ec
Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>
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Add parameter to indicate backlight level set from
userspace. And get the value by sysfs read function.
Change-Id: Iaecb0076e1f664fe87f3351edeecce40935cbae4
Signed-off-by: Xu Yang <yangxu@codeaurora.org>
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During clock recovery sequence of DP link training, at the end of
first iteration, if the maximum voltage swing or retry count of 5
is reached, the link rate needs to be reduced and the link training
sequence need to be tried again. The current implementation sends
the AUX command to specify the reduced bandwidth but doesn't actually
reduce the link rate. This causes link training failures during
compliance testing. Add change to disable the DP mainlink clocks and
re-enable them with reduced rate in such cases.
Change-Id: I873799a89871dd144434e5692f38434795e686f1
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
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First read the register and then OR it with enable bit
for write gather register in MDP and Rotator.
Change-Id: I2e284c7682055233851a5e69361e2ccfec647ff7
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
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If destination scaler count value is 0, don't parse
destination scaler structure in validate IOCTL.
Change-Id: Ie65b7b0b304108990406e25db55ee841f9316e17
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
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In some cases the hpd call cannot be blocked. For example, in
case of framework restart, both display and audio HALs are not
available, so nobody will notify and unblock hpd call. Another
case is continuous splash in which unblank is delayed till the
first display kickoff, so hpd cannot blocking wait for such a
late notification.
Change-Id: I6ed58c3ac35efdaeac2e73d36d78b7fd64a74f42
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
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For DPCD read failures, set link parameters corresponding to
the fail safe link resolution to conform to the display port
specification.
CRs-Fixed: 2010344
Change-Id: I06f56f508fe7adcb9e76f1a8597fc59cdadd741b
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Detailed Timing Descriptors (DTDs) listed in the EDID data contain
the information about the horizontal addressable video pixels for
each resolution. The maximum value that can be specified for this
field is 4095. In certain instances, a sink may list a resolution
with 4096 horizontal addressable video pixels in the DTD by listing
a value of 4095. If this value is parsed as is, it can lead to
incorrect behavior. Fix this by explicitly updating the value to
4096.
CRs-Fixed: 2020154
Change-Id: I035bbef7d245c7cdd75a5bba8719fcca4592d8b7
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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