| Commit message (Collapse) | Author | Age |
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Micro resolution and 64-bit division is unnecessary; use milli
resolution instead. Measuring the IBATT and VBATT periodically during
sleep is necessary for accuracy. Don't clear the IBATT and VBATT buffers
on suspend to account for the higher charge current during suspend.
Prime the IBATT and VBATT buffers with 10 samples to get a more accurate
first estimate. Introduce a ttf mode to separate the differences in the
QNOVO version of TTF.
Change-Id: Ibc591dd5d38d4bbb712d8906755040d59181f008
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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It supports for temperature (JEITA) based step charging.
The solution samples the battery temperature periodically and
applies the FCC from a static look-up table.
There is a provision for timed hysteresis which is achieved using
a 5 second delayed work.
Change-Id: Ica18f2c812232d6938799dab16fb9f18bc14b48f
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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A median filter is useful for filtering out outliers. Add it.
Change-Id: I21f97a870c262e5fb3d33b8250a2bf074f519b58
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Add support for the CC_STEP and CC_STEP_SEL properties in the BMS power
supply. These properties will be used to communicate the future charge
currents for time to full calculations.
Change-Id: I44087b42b31800d1885bdaf1f38815c8756bc9a8
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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There are several algorithms which modify the charge current in steps
across the charge cycle. CC_STEP is used to notify of all the upcoming
charge currents.
The CC_STEP_SEL property is used to select the index of the CC_STEP to
read or modify using the CC_STEP property.
Change-Id: Ieeb533b758035c1c408cdfd68f001374bf0987a5
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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status7 register will indicate all the charger bits are cleared during
the rest or discharge phase of a Qnovo pulse. Moreover those bits remain
cleared after a pulse train is done and before a new pulse train is
issued.
Hence when Qnovo is active ignore status 7 register bits.
Change-Id: Ice61f8a49625081ffbf1aacaac844b929715e818
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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There are a couple of cases where qnovo charging fails,
1. pulse train enable command register fails to write through, or
2. pulse engine fails to start and pulse train timer PTTIME does
not start counting.
In either case, qnovo charging will stop. Here is the fix,
Write register twice when enabling pulse train, and
restart pulse train if PTTIME does not increase.
Change-Id: Ic235f8f2bc67fe577e42848ef623870c25b68256
Signed-off-by: Harry Yang <harryy@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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The request is to delay ok_to_qnovo for 15 seconds after a charger is
inserted.
To achive that:
Make ok_to_qnovo variable as a votable that can be voted on by
A. HW error conditions
B. Charger is ready after debounce
Moreover since there could be two chargers -usb and dc, create another
votable to track their individual debounce states. The result of this
votable will feed in to ok_to_qnovo votable as branch B above.
Also since we need to stay awake for the debounce time, create an
awake_votable and vote on it while debounce on either usb or dc is in
progress.
Change-Id: I32dc07ba16ef0515a9683f2702d317c39baa2eba
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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At the end of pulse train ESR measurement is forced. It is expected
that when ESR is being measured, which takes about 1.5 seconds, the
next pulse train does not start.
However we see that a uevent is sent to userspace and it enables pulse
train within 100mS.
To prevent that put the pulse train enabling bit under a votable
control. And make QNI_VOTER (the userspace voter) and ESR_VOTER vote
on it.
Moreover, the current pulse train enabling path checks if qnovo was
enabled, make a QNOVO_OVERALL_ENABLE voter to this new voter to reflect
it.
Change-Id: I6d2177250cc47f5aeb6591c532ee18d37e3b02c6
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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When FG IADC measurement period coincides with qnovo discharge pulses
it reads incorrect IADC values. That causes issues with SOC accuracy
and capacity learning amongst others.
The fix to IADC inaccuracy is to set a bit in the FG
peripheral while Qnovo is active.
A side effect of IADC inaccuracy fix is that the ESR
measurement goes haywire. To overcome that, disable ESR when
Qnovo is active and force an esr measurement when its between pulses.
Realize this by disabling ESR and enabling the bit when
Qnovo becomes active. The qnovo driver will set CHARGE_QNOVO_ENABLE
property on the bms psy when its active. Also provide code to
force an ESR measurement via a write to RESISTANCE property in
bms psy.
Change-Id: I7160ad6288362c17d28d67b38ec09332d9a6cbd2
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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When FG IADC measurement period coincides with qnovo discharge pulses
it reads incorrect IADC values. That causes issues with SOC accuracy
and capacity learning amongst others.
The fix to IADC inaccuracy is to set a bit in the FG peripheral while
Qnovo is active.
A side effect of IADC inaccuracy fix is that the ESR measurement goes
haywire. To overcome that, disable ESR when Qnovo is active and force
an esr measurement when its between pulses.
Realize this by setting CHARGE_QNOVO_ENABLE and RESISTANCE property on
the bms psy at appropriate times in the driver.
Change-Id: I5b37083c843ec6bc052c4d344347b9a80554e226
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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In case of quick back-to-back insertion/removal of USB
there is a possibility that VBUS does not fall below the
1V usb-plugout threshold and hence the subsequent insertion
does not generate a plug-in event. This keeps the DPDM
regulator disabled at insertion thus impacting the APSD result.
Fix this by voting to enable the DPDM regulator in the cc-attach
handler.
CRs-Fixed: 2042071
Change-Id: I37a32081f0847965e34eb1c4114602ec61e9a005
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
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The recharge SOC is based off the monotonic SOC (msoc). Hence, use
the msoc to determine if the hold-soc-while-full logic needs
to be applied.
CRs-Fixed: 2080211
Change-Id: I52b02adc4d97cbed42b0c8034a5a48dba1e343d3
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
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An SDP may get detected as a FLOAT charger by PMIC APSD.
To handle this case do the following steps when a FLOAT
charger is detected -
1. Limit the ICL to 100mA and start USB enumeration
2. If enumeration succeeds, USB notifies a valid
ICL and the charger updates ICL and charger-type to SDP.
3. If enumeration fails, USB notifies -ETIMEDOUT and
charger applies ICL based on the Rp value.
CRs-Fixed: 2081457
Change-Id: I2747a42ed9f9531e83c53d781a8ae9baa9aa74d0
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
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Currently the buck frequency is set to 700kHz only when the smb138x is
in master mode. The buck frequency needs to be 700kHz in both master and
slave mode to prevent ADC errors. Do it.
Change-Id: Ib2cea9b38b6b23f9f229ee85c2bde5a5fd6220fd
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
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Remove the HW SOC-based step-charging logic and enable
SW based step-charging.
The SW based step-charging uses the periodic WD bark
IRQ to notify the battery properties. The bark-time
can be changes using the property 'qcom,wd-bark-time-secs'
'qcom,step-charging-enable' enables the feature.
Change-Id: Ib162f3eb3f98a4e7f144bedc8c8cea40fbf6137a
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
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Add a new file which manages the step charging solution.
It supports 2 sources for step-charging - VBATT and SOC.
The solution samples the VBATT/SOC periodically and
applies the FCC from a static look-up table.
Change-Id: I82f560df5a6a8ad0cd46e989f9944d93cb5529d7
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
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In the scenario where the charging is terminated in the
JEITA soft condition, the HW is expected to restart
charging when battery temperature returns back to normal.
However, this does not work as expected and the charging
stays terminated. Fix this by disabling and re-enabling
charging CMD bit to restart charging.
CRs-Fixed: 2071261
Change-Id: I81d2a89c72ede840cc561b736ce1366c65da8c42
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
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There are scenarios where inductive load with higher inrush
current may fail to turn on the OTG. Improve the OTG turn-on
sequence by gradually increasing the current-limit if it
fails to turn-on with a lower current.
CRs-Fixed: 2075050
Change-Id: I41c1e25257a4ee87f00287e07773331b1445b5f2
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
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Temp in trace_temp_notification is not divided with
scaling factor while cpu_node->temp is. Use temp after
scale for better log understanding.
Change-Id: Iadf4a1c39211651fee67cc18f68a65785f28fa58
Signed-off-by: Maria Yu <aiquny@codeaurora.org>
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We observed an interrupt storm on that interrupt
even after the usb path is suspended.
So keep this interrupt disabled as long as the usb
path is suspended.
Note that since the current limit votes can come in
prior to interrupt registration, rerun the election
on the votable after interrupts are registered.
Change-Id: Ib43b071b7b0decf8e50d27d585bea04b727f9475
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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This reverts commit b67bb93f565e ("power: reset: Do not
disable SDI during reset"), to restore the original
behavior of disabling SDI during reset.
Change-Id: I6ad0472dc5d766ffea2a942fc226fb742fe44242
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
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The legacy detection workaround change restricts DCP to 1.5A draw,
regardless of legacy/non-legacy type. This was to prevent a legacy
(non-compliant) cable, incorrectly detected as non-legacy cable from
drawing more than 1.5A.
The issue with legacy bit is that hardware could end up reporting
non-legacy for a legacy cable (not the other way round). We want to
ensure that for non-compliant legacy cable SDP/CDP current limits
are honoured and that for a Rp = 10k legacy cable VBUS shouldn't go
higher than 5V.
This cap of 1.5A on DCP is not necessary. Moreover AICL will limit the
current if needed.
To realize this force the Rp based current whenever DCP or float
is seen via the LEGACY_UNKNOWN_VOTER. LEGACY_UNKNOWN_VOTER is not
removed unless a confirmed hvdcp or pd is seen.
Change-Id: I89505e9db4f045aaf71ab0ee534de783ea4d2df3
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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With Minidump support enabled, user may need to request
to dump both fulldump as well as minidump for debug purpose.
Add support on dload_mode sysfs entry to select both dumps.
Enable both dumps with command:
echo both > /sys/kernel/dload/dload_mode
Change-Id: I2f7c4c6e26dc236c75ab89490990c87b7139880b
Signed-off-by: Lingutla Chandrasekhar <clingutla@codeaurora.org>
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Currently, USB power_supply POWER_SUPPLY_PROP_ONLINE property will be
set if the charger type is POWER_SUPPLY_TYPE_UNKNOWN which is not
expected. Unset ONLINE for UNKNOWN USB charger type.
CRs-Fixed: 2065139
Change-Id: Ibc40ee62b2d95c319a7fe34b17813c2b57518f67
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
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During hardware initialization charger is configured in
DRP mode from force UFP mode and after mode configuration
hardware takes ~300/400 msec for UFP/DFP detection. In case
if the delay between moving to DRP mode and software enabling
interrupts is more than hardware detection delay then software
will miss the detection interrupt. Fix this by moving DRP
configuration after interrupt request this ensures software will
receive interrupt once hardware detection completes.
CRs-Fixed: 2065296
Change-Id: I55c59ed558e8db40a7b1af7638832da1f9547222
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
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Report adapter type as USB_FLOAT if charger hardware detects a
floating charger this will allow USB driver to try/start
communication over Tx/Rx line during compliance testing.
Change-Id: I1d1e91e99806423a3e995876e9db4582ed0f1b08
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
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Add support to register a Floating type charger.
Change-Id: Ib65eff52a42d639a90f162488337a554deab4bfa
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
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A break is missing in a switch statement. Add it.
Change-Id: Ib298194957ff2cc1aaba5bd4335afe9d0f9cf6f5
Signed-off-by: Nicholas Troast <ntroast@codeaurora.org>
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A weak charger might trigger switcher_power_ok interrupt storm
which gets incorrectly detected as a boost_back condition and
input gets suspended. Add a logic to distinguish a weak charger
and the boost_back condition by first reducing the ICL current
to a lower value (500mA by default) on detecting a
switcher_power_ok storm. If the switcher_ok storm disappears
then its indeed a weak charger and if the storm continues its
possibly a boost_back condition.
Change-Id: I46b406e403aa16a502e6da149b180545848fc906
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
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The BOOST_BACK USB-ICL voter needs to be removed in the
following conditions -
1. VBUS falling path during PD hard-reset
2. typeC removal
3. False boost-back detected
For (1) and (2) - remove the boost_back vote in the usbin_handler
and typec_removal path. For (3) add a worker which removes the
boost_back vote after the boost-back condition is detected. The
delay is sufficient to recover from both a valid and an incorrectly
detected boost-back condition.
CRs-Fixed: 2051908
Change-Id: I9d1d04f392bb6040b0565510ff7d1032bb036de2
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
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Workaround to re-enable BMD while getting battery id was required
when driver is probing. This was done to mitigate driver probe
failures because of failed SRAM access. Getting battery_id from
RR_ADC driver itself takes ~200ms and re-enabling BMD takes 200ms
which increases driver probe time.
With the recent changes in reading batt_id channel from RR_ADC
driver, re-enabling BMD is not required anymore when the driver
probes. Hence move getting battery_id and battery profile to
profile_load_work. This way, there won't be any delay when the
driver probes.
CRs-Fixed: 2062261
Change-Id: Ifeb361e0f82fca65f9570fd1f425c7360445d01f
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
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QC_PULSE_COUNT register offset differs between PMI8998 and
PM660. Use common function "smblib_get_pulse_cnt" to read
the pulse count instead of directly reading the register.
While at it, update the "smblib_get_pulse_cnt" function
to return software based pulse count if HW INOV is disabled.
Change-Id: Iab935b352dd75365d1f9862d7a7986cd1c476f66
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
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Currently, capacity learning algorithm is aborted when the
charging status goes to not charging. This can happen with qnovo
enabled charging where stopping the pulsing can lead to charging
status change. Qualify aborting capacity learning based on the
qnovo enable status and input presence.
While at it, abort the capacity learning when the charging status
goes to discharging and charger is removed.
Change-Id: I4546e8880be0658748157cb13f048610eee932a3
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
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Currently, rerun_election() is called on delta_bsoc_irq_en
votable to disable delta_bsoc interrupt during probe. However, it
doesn't set the internal variable for votable to not allow a
similar vote again. When a vote is made later to disable the
interrupt again, it can end up in invoking the callback again.
This leads to an unbalanced interrupt disable warning. Fix it.
CRs-Fixed: 2058754
Change-Id: I30c35be5275b5b310cf9b17ea4660a3e2e89c59a
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
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