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* | | mhi: core: Fix race condition on poll_inboundTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix race condition in mhi_poll_inbound which could leave the bounce buffer list and TRE list out of sync. Change-Id: I76c7de75256b59f8a0dff2a85af733c441761385 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Read the EXEC_ENV from deviceTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Read the EXEC_ENV register from device to determine the MHI base state. Change-Id: Id70a360cfa3775a7186e5059306385a37960df2d Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Enable dynamic event ring allocationTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable dynamic allocation of event rings from the coherent pool to ensure appropriate page alignment with device. Change-Id: Id57ccd889cf96aad73f4ada01405e2d734351c8c Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Set correct DMA mask on deviceTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Set the correct DMA mask on the platform device to avoid bounce buffering from the default 32 bit mask. Change-Id: I7e201e83fd21b0f0a6f57754a3b6f3eded9be58f Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: Use standard kernel return codesTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the MHI defined enum for return codes with kernel standard return codes. This greatly improves readability and parsing of errors by userspace clients. Change-Id: Ica47f8c3a149f23243b5fb6a4aabcdc0a36b1535 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Track number of failed M2 wakeupsTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Failed M2 wakeups may represent a serious hardware problem. The device is refusing to wake up from low power states and all modem functionality is now stalled. Track these wakeup attempts. Change-Id: I3115a4416f85290c5faead0e2d9f280d8cc3b662 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Enable runtime PM on pcie deviceTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable runtime PM on PCIe device to ensure sync with PCIe framework. Change-Id: Ied432440df0dc788642fe1a1a8d9195b6cc1cf7c Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Remove incorrect macro for tre sizesTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unused macros for TRE sizes. This information is now present in device tree. Change-Id: Id3ca59c62d66ce8913e83fcba60e1a912cf146ea Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Add mdmcalifornium as a supported MDM by MHITony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add mdmcalifornium to the list of supported PCIe devices by MHI. Change-Id: I34e846caceb8fd2808594470cccbb7e318011cda Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Support BHI error register readTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case of BHI failure, read the device BHI error registers in the hopes of root causing the failure. Change-Id: I0c695f7afc873d6fd5c0c9d88e9885799b228d46 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Enable SBL logging channelsTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Enable SBL logging channels. Change-Id: I156bc89ca1be0ed966eeb1b2e38b8bfd7bf44de4 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Reorder channel initialization sequenceTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the local bounce buffer list before the device channel initialization sequence. Change-Id: Ia87698dc83807727f6897356bf9b23f123c53851 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Enable correct channel alignmentTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable correct allignment of MHI channels to the ring size rounded up to the next power of two as per device requirement. Change-Id: Ic77c43fdbcde2ec3b6f08e3062eaf778eb13ec5b Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Resolve issue for UL/DLTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resolve issue whereby UL DL properties were being incorrectly set for non HW event rings. CRs-Fixed: 827294 Change-Id: Ie279061e84c0f2498393c5d7bfaef404307c84da Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: Enable logging based on defconfig optionTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable logging based on MHI defconfig option. This avoids excessive logging in secondary boot image. Change-Id: Ie22d56d781feadb2d484e6117c9c25ee29aa5299 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Enable parsing of dev window from dtTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable parsing of device window size from device tree and calculating the appropriate addressing limitations. Change-Id: I252a593a74f0cc00e6295a45d4d13db6c79cdfca Signed-off-by: Andrei Danaila <adanaila@codeaurora.org> Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | mhi: core: Enable queueing of virtual buffersAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Enable clients to queue virtual buffers, thus leaving all the DMA operations to MHI. Change-Id: I824d2f387b1a21d322ca0628963995824227bd76 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | mhi: uci: Enable virtual MHI queueingAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Enable the queueing of virtual buffers to MHI instead of buffers obtained from streaming DMA. Change-Id: I8ba25c1f28cbd1cb302aec184864ed2e25672d4a Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | mhi: core: Enable BB scheme for MHIAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable bounce buffering scheme in MHI for the cases where allocated APQ memory falls outside of the memory range which the device can access. Change-Id: I9f40b0dda2f49111b7deb22973e6399fada90094 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | PFT: moved to a new directoryAndrey Markovytch2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QCOM security components were moved to security folder inside kernel which is more appropriate Change-Id: I4e450a23583ceac929a3980b1b5998f4e0c7cfa9 Signed-off-by: Andrey Markovytch <andreym@codeaurora.org> [gbroner@codeaurora.org: fix merge conflicts and updated ARCH_QCOM] Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
* | | platform: msm: add Per-File-Tagger (PFT) driverAndrey Markovytch2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Integrated from msm-3.14. Additional fixes were made to compile with the new kernel and various new warnings and checkpatch issues were fixed Change-Id: I073db1041e41eac9066e37ee099f1da9e4eed6c0 Signed-off-by: Andrey Markovytch <andreym@codeaurora.org> [gbroner@codeaurora.org: fixed merge conflict and adapted the LSM security hooks] Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
* | | platform: msm: Add snapshot of USB BAM driverMayank Rana2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add USB BAM driver used which allows USB BAM to communicate with other other peripherals (e.g QDSS or IPA) BAM. This snapshot is taken as of msm-3.18 commit d5809484bb1b. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* | | msm: gsi: construct TRE before submitSkylar Chang2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For performance improvement avoid multiple writes to channel ring which is a dma coherent memory. Instead, construct the TRE (Transfer Ring Element) in local memory and then copy it to the ring itself. Change-Id: I36bfae306be2a90c8679d416397a435e638b54eb CRs-Fixed: 977590 Acked-by: Ady Abraham <adya@qti.qualcomm.com> Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
* | | msm: gsi: data path statisticsSkylar Chang2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add capabilities to GSI driver to collect data path statistics in order to help debugging throughput issues. This change also exposes the a debugfs interface to print stats. CRs-Fixed: 975119 Change-Id: If97512af034bd419cf4f679b1c19419605529fa6 Acked by: Ady Abraham <adya@qti.qualcomm.com> Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
* | | SSM: Integrating the SSM driver codeAshay Jaiswal2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for SSM driver which is a framework to which a client can register itself specifying different attributes and defining various permission levels associated with different combination of attribute values and mode of the system. CRs-Fixed: 970190 Change-Id: Ia030ebad56a22ba9103af17f6557c7906b762b76 Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org> Signed-off-by: Manoj Prabhu B <bmanoj@codeaurora.org>
* | | msm: ep_pcie: update PCIe PHY register dumpYan He2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Update the PHY register dump for PCIe Endpoint mode so that more debugging information could be acquired in case of PHY failure. Change-Id: I6b40df668d8a5c912547af701e8a2150db47452f Signed-off-by: Yan He <yanhe@codeaurora.org>
* | | msm: sps: update SPS loggingYan He2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Update the logging in SPS driver to catch additional info for the interaction between SPS driver and BAM client drivers. Change-Id: Icd5955d2d4dd83124f47e60e052ec3b3a2611025 Signed-off-by: Yan He <yanhe@codeaurora.org>
* | | msm: gsi: mask GSI_BREAK_POINTSkylar Chang2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | SW should not be registered for GSI_BREAK_POINT interrupt as this is for debug purpose only Change-Id: I17d152955bb52bccc89ff731eabe05582b7fd14c Acked-by: Ady Abraham <adya@qti.qualcomm.com> Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
* | | msm: ep_pcie: update PCIe PHY sequence to support L1ssYan He2016-03-23
| | | | | | | | | | | | | | | | | | | | | Update the PHY sequence of PCIe Endpoint mode to support L1ss. Change-Id: Ib80a2fab167e232540240183387a441d246463a5 Signed-off-by: Yan He <yanhe@codeaurora.org>
* | | msm: ep_pcie: add the support of MDM2AP GPIOYan He2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Add the support of MDM2AP GPIO so that MDM can notify AP about updated status. Change-Id: Ia5a020898d4d04dcd4fec6b3928aba380663ac56 Signed-off-by: Yan He <yanhe@codeaurora.org>
* | | msm: ep_pcie: support both PARF based MSI and iATU based MSIYan He2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Add the support to generate both PCIe PARF based MSI generation and iATU based address write MSI generation for unit test. Change-Id: I8c5abf8dcae4ebf2c33fee182f6bc147979f74dd Signed-off-by: Yan He <yanhe@codeaurora.org>
* | | msm: ep_pcie: enable BME IRQYan He2016-03-23
| | | | | | | | | | | | | | | | | | | | | Configure PCIe debug register to enable IRQ for BME. Change-Id: I497d86fcdbe862d770b9e7841dabd023cfe6d1f8 Signed-off-by: Yan He <yanhe@codeaurora.org>
* | | msm: ep_pcie: set up execution environment before link upYan He2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Set up the execution environment before PCIe link training to provide better adaptability to various hosts. Change-Id: I72721d3b88a7e5b1a0a1f408da2228391559468e Signed-off-by: Yan He <yanhe@codeaurora.org>
* | | msm: ep_pcie: update MSI address for PCIe clientsYan He2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe clients will utilize the original MSI address instead of mapped local address when active config is enabled. The change here provides the original address to the clients. Change-Id: I0d35fa9508d7c3ec2e97bd7d61754974e798bf8a Signed-off-by: Yan He <yanhe@codeaurora.org>
* | | msm: ipa3: Configure IPA RX HPS resources distributionGhanim Fodi2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IPA RX HPS command queue resources need to be distributed among the different resource groups (e.g. Uplink group). The configuration is the maximum and minimum number of resources that can be used by each group. Change-Id: I02cf831b6ea6da812b67624fbb48bb829e4684d3 Signed-off-by: Ghanim Fodi <gfodi@codeaurora.org>
* | | msm: sps: support using cached write pointer for BAM-to-Sys modeYan He2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Support using the cached write pointer for a BAM-to-Sys mode BAM pipe when check if the desc FIFO of that pipe is full. Change-Id: Ie480ecca9eff76388c504665b496e01bbf3e009f Signed-off-by: Yan He <yanhe@codeaurora.org>
* | | msm: ipa2: add active clients loggingValery Gorohovsky2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add framework for IPAv2 active clients history logging logging is enabled by default cat /sys/kernel/debugfs/ipa/active_clients in order to view logs echo anything to /sys/kernel/debugfs/ipa/active_clients in order to clear the history log buffer Change-Id: I975271798aee56ac9889d34203a32c99a30fc958 Signed-off-by: Valery Gorohovsky <valeryg@codeaurora.org>
* | | msm: ipa3: make ipa3 compile for corbalt rumiSkylar Chang2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the new IPA-interrupt register to get the IPA-HW irq, also change the tag process to be compatible to 64 bits platform. Change-Id: I29a8805cacc8d8df2f0e60ee8e1d2243c718d248 Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
* | | msm: ipa3: fix event ring allocation for PRODSkylar Chang2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not allocate event ring for non interrupts pipes. These pipes receive completion from their status notification pipe. Change-Id: I9ae96440ed479888e2f974f2143ddd275f8afbb2 Acked-by: Ady Abraham <adya@qti.qualcomm.com> Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
* | | msm: ipa3: fix memory leak in __ipa_reap_sys_rt_tblsAmir Levy2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | __ipa_reap_sys_rt_tbls always deletes a routing table from head_rt_tbl_list, but it releases the routing table memory only if it matches the rule type (hashabale\ non hashable). This function was called twice each time with a different rule type, therefore if a DMA memory was allocated for the non hashable type, calling the function for the hashable type first will delete the routing table entry and the next call will not release the memory. This change releases the memory for both rule types and only then deletes the routing table entry. Change-Id: Id7f655b324a20c9681a3c48877d825929bc205aa Signed-off-by: Amir Levy <alevy@codeaurora.org>
* | | msm: sps: add the checking of ZLT in case of an empty pipeYan He2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Check if a ZLT descriptor is the last pending descriptor in the desc FIFO when determine if the desc FIFO of that pipe is empty. Change-Id: Ib8174953d6ad7d886f47f21e243e985b79ef41fb Signed-off-by: Yan He <yanhe@codeaurora.org>
* | | msm: ipa: add support for TX of sk_buff's with paged dataRavi Gummadidala2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | This support is needed to enable GSO (Generic Segmentation Offload). Change-Id: Ib6e7a5a5f3139697e0b6c68782134377a7bb2dc6 Signed-off-by: Ravi Gummadidala <rgummadi@codeaurora.org>
* | | mhi: Enable logging based on defconfig optionsAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | MHI driver stack logging to the private IPC log buffer can be quite expensive from a MIPS perspective. Enable such MHI logging if and only if such logging is desired in defconfig. Change-Id: I4a16eedc2424d250129b1b44a91d1fa32be399f5 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | mhi: core: Fix PM state machine sync issueAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain corner cases have been identified in the MHI core power management state machine whereby the driver state can go out of sync with the device. The cases are as follows: During in MHI resume operation the device is not guaranteed to be fully recovered from LPM as the framework requires. This causes RPM suspend to potentially be invoked on a device which is still going through a resume state. During RPM suspend action, if said action is cancelled a timing window exists where previously cached commands are not played back to the device. This causes a rotting command issue, when said commands are never acknowledged causing a non recoverable timeout error on the client channels. During an RPM suspend operation, a timing window exists where the device may be transitioning to M2 when the M3 is set. This causes a device error which is non recoverable except by a full reset. CRs-Fixed: 856202 Change-Id: I232365ba77b02b9aec87fef4cecc3d991243afe2 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | mhi: core: Flush M3 writeAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Do a read after write for M3 to flush the write to the device. Change-Id: I0cf8c8a9dcf3599614351e1289f4b56a0fe32289 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | mhi: core: Initialize the transaction statusAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize the transaction status return code for the client to a known value. CRs-Fixed: 836433 Change-Id: I8023bd29b6ce36f69dfc3d2844803696eacadeb1 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | mhi: core: Remove race condition on LPMAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Eliminate race condition whereby the device could go into a low power mode before the host has finished initializing. CRs-Fixed: 836441 Change-Id: I9957e87b1bfe956963c1f74f0a02d6714e9afcbe Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | mhi: core: Initialize the client intmod capsAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize the client interrupt moderation capabilities to enable correct marking of TRE moderation flags. CRs-Fixed: 850216 Change-Id: Ic7a51fd1f089a847f225f23202183033352d0761 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | mhi: core: Necessary changes for 64 bitAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | Necessary changes for 64 bit compilation on the 3.18 kernel. Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | mhi: core: Replace dma APIsAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | Replace dma_to_virt and virt_to_dma with mhi_p2v_addr and mhi_v2p_addr Change-Id: Ibda473254040cbd1f5fdf9eb463c14996d5fe12a Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
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