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* | msm: pcie: support PCIe bus driver on msm-4.4Tony Truong2016-03-22
| | | | | | | | | | | | Update PCIe bus driver to be compatible with 4.4 kernel. Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: fix compilation erros if debugfs is disabledTony Truong2016-03-22
| | | | | | | | | | | | This change fixes the compilation erros seen when DEBUG_FS is disabled. Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add QSERDES PHY support for mdmcaliforniumTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | The current PHY sequence is not fully compatible with the QSERDES PHY found on mdmcalifornium. Thus, add the new sequence and other changes to support PCIe QSERDES PHY on mdmcalifornium. Change-Id: I5a5d0b115651a159612e17debf0d25d6f88dbee8 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add ARM32 support for mdmcaliforniumTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | Currently, PCIe bus driver on mdmcalifornium does not have support for ARM32. Thus, add the necessary changes to support ARM32 for PCIe on mdmcalifornium. Change-Id: I6c72debd9ea65b7abb70ce4d5568c972ba786c11 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add support to handle aggregated interruptsTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | Not all targets will have a dedicated line for each PCIe interrupt. On these targets, some PCIe interrupts will be aggregated into one line. Thus, add support to handle aggregated interrupts. Change-Id: I4f5be73718d4a4ae8a3de142579f24a7113fe086 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: update PCIe PHY for MSM8996v3/v4 based on si learningTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | Based on si learning, new PCIe PHY settings improve the overall stability of PCIe PHY on MSM8996 v3 and on v4. Thus, update the PCIe PHY sequence for MSM8996 v3 and v4. Change-Id: Ia1ab0af4c4dcf483d3b3dc05b7b13003de788f40 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add locks to protect PCIe common PHY init and deinitTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | The counter for the number of active root complexes determines when PCIe common PHY should be powered on/off. To avoid conflicts and a stale counter, add locks to protect the access to PCIe common PHY. Change-Id: I18ec54e52e804eb132f9c5c0270455dbc9187151 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: change PCIe WAKE support to be optionalTony Truong2016-03-22
| | | | | | | | | | | | | | | | Not all endpoints require PCIe WAKE support. Therefore make PCIe WAKE GPIO optional. Change-Id: Ifc5a84204cde42881a127b4715727c290ee24450 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: update debugfs messages with new IPC labelTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | In addition to having outputs to kernel log, PCIe debugfs messages should also be captured in IPC logging. Therefore, add a new IPC logging label and update the existing calls to do so. Change-Id: I2ab6a6549575c4e2de2f1ef0756328f4b6f6a178 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add support to distingush between PCIe PHY verTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | PCIe bus driver can now use devicetree to help distingush which PCIe QMP PHY version is being used. This will allow PCIe bus driver to choose the correct PCIe PHY sequence. Change-Id: I74c67431b75292bb1db3e4b97d89d69de9b6f11b Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: remove PCIe CX rail vote when releasing resourcesTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | Current PMIC API call to disable CX rail does not remove PCIe power vote. Add another API call to successfully remove vote when releasing this resource. Change-Id: I5203203e10e8e690745768c241e92d298b87cc4b Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add delay after power down writeTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | To improve PCIe PHY stability, add a delay between the write of power down and sw reset register on MSM8996. Change-Id: If09390bff59e0922cb891c7bac823c11361fca83 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: slow down PCIe PHY RX clock for SVS modeTony Truong2016-03-22
| | | | | | | | | | | | | | | | In order for PCIe to reliabily work in SVS mode, the PCIe PHY RX clock needs to be slowed. Change-Id: Ic6edf487011ef4ac71d486210b1f6176e2142551 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: increase the wakeup delay time for aux clockTony Truong2016-03-22
| | | | | | | | | | | | | | | | Increase the wakeup delay time for PCIe aux clock on MSM8996 to improve PCIe stability when waking up. Change-Id: I2909e80a2c79b4f17ca39c39d899de08b67d4120 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add support for RC to vote for CX railsTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | Each PCIe client requires different CX power levels to maintain functionality. This change gives each PCIe root complex the ability to vote for CX power levels. Change-Id: If027c79220253a60837c3d52202fb5ec4cc3451e Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: update PCIe QMP PHY sequence on MSM8996Tony Truong2016-03-22
| | | | | | | | | | | | | | | | | | New QMP PHY sequence for 1MHz aux clk for PCIe on MSM8996. Therefore, update the PCIe PHY sequence. Change-Id: I2b3746cc9d6ab6b491fa7404ae54fefbf36df905 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: remove unnecessary cleanup code for Synopsys MSITony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | There are unnecessary cleanup code which alters the descriptor of a Synposys MSI IRQ and this causes the IRQ to be unusable afterwards. Remove the unnecessary cleanup code for Synopsys MSI so that the IRQ will remain functional. Change-Id: I87221f9a59d014df21af251277866c511c5375eb Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add PCIe support for 3.18 kernelTony Truong2016-03-22
| | | | | | | | | | | | | | | | Add PCIe support for 3.18 kernel. Added enumeration, interrupts, and hardware configurations support for PCIe. Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: increase the Ipeaks for PCIe LDOsTony Truong2016-03-22
| | | | | | | | | | | | | | | | Increase the Ipeak request for each PCIe LDO based on updated settings. Change-Id: Ie3af6462dac68252b339595e350e393079a89bb9 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add SMMU support to calculate SID for PCIe EPTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | SMMU requires PCIe to provide a SID for each of its endpoint so that the endpoint can successful transaction on the bus. This change adds the support for PCIe bus driver to calculate a SID for its endpoint and give it to the SMMU driver. Change-Id: I52099bbfed0a38c75b0277b0f58f45f6e6559695 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: correct exit code for invalid Root Complex indexesTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | In the case where the Root Complex fails to retrive a valid index, the exit code fails to handle this correctly. This change corrects the way the exit code handles invalid root complex indexes. Change-Id: Ie832fec1be2b05dea05b8917348a1c08cdc1d681 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add support to enable additional GPIO for endpointTony Truong2016-03-22
| | | | | | | | | | | | | | | | Some EP requires additional GPIO to be enabled for link training. Add the support in PCIe Bus Driver to manage this GPIO. Change-Id: I837edae478779fdaf3e94c70a0a031f9d0580a77 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: update PCIe PHY sequence on MSM8996Tony Truong2016-03-22
| | | | | | | | | | | | | | | | | | There are new PCIe PHY settings that have been updated to improve performance and stablilty. Therefore, update the PCIe PHY sequence on MSM8996. Change-Id: If321471c51ff6a91595b68bd2cae08c8c043d6bb Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add entry and exit detail logging for PCIeTony Truong2016-03-22
| | | | | | | | | | | | | | | | To support more accurate benchmarks, add entry and exit logs for PCIe functions. Change-Id: I49f27263722adfaa8ae3973f242faa6a589d3358 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: correct the offset of a PCIe AXI registerTony Truong2016-03-22
| | | | | | | | | | | | | | Correct the offset of a PCIe AXI register. Change-Id: I429c3e42cc8bb6cc7e23b5e461e51ec10435a89d Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add PCIe MSI support on 3.14 kernelTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | To support PCIe MSI on 3.14 kernel, the client's host driver must use the QGIC IRQ number to request/enable the interrupt while the client's firmware must use the SPI number to trigger the interrupt. Therefore, add this logic in PCIe bus driver to support MSI interrupts on 3.14 kernel. Change-Id: I165022281c9e795be8c5e2e4a4faa34d4c004a45 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: correct PCIe PHY dump status register readTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | After writing to a PCIe PHY debug register, the wrong PCIe PHY status register is being read back. This change corrects the PCIe PHY status register that is read back. Change-Id: If360aa6f9b4530e4c07acfcc1af684c6d7ecc234 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add PCIe support for thuliumTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | Add PCIe support for thulium. Added enumeration, interrupts, and hardware configurations support for PCIe. Change-Id: I48b2fc8a51303a6aea7b1b2a97c4de25f19ded4c Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: sanity check when calculating EP CAP offsetTony Truong2016-03-22
| | | | | | | | | | | | | | | | When searching for the endpoint's capabilities register, check that the value from the register read is valid. Change-Id: Ia64de3c75618ca0a51aa4588ac97f2fcb26d8829 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: correct the shadow save for RC L1 registerTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | | | When reading shadow registers, the wrong value is being recovered for root complex L1 register. Currently, the value being recovered is a shadow of the endpoint's L1 register. This change will recover the correct shadow value for RC L1 register. Change-Id: I82b1810ef8761de90b350743cdd9b24a74efb62f Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: remove duplicate call to get aux clk from dtTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | There is an extra identical call made to check if aux clk is supported base from PCIe device tree node. There is no need to do this check twice; therefore, remove the duplicate call. Change-Id: If705e98e637287969d68ea2241e62447aa505eb0 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: only look for EP CAP reg for certain testcasesTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | Not all the testcases for debugfs needs the calculated offset of an endpoint's capability register. Therefore, only calculate the offset of an endpoint's capanility register if that testcase needs it. Change-Id: Iffddcea682d8c9344f51a04b57f60ba906b01dc6 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add support to enable common clock for RCTony Truong2016-03-22
| | | | | | | | | | | | | | | | When the clients want to enable common clock for the endpoint, also enable it for the root complex. Change-Id: I55d5a69be0746a745b073051452d45a38d0a4e65 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add PCIe PHY support for FSM9010Tony Truong2016-03-22
| | | | | | | | | | | | | | | | FSM9010 requires a different PHY sequence. Therefore, this change adds the PCIe PHY support for FSM9010. Change-Id: Ic98860d3ac1f7b644b76064032f399f070fc9b47 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add support to enable clk power management for EPTony Truong2016-03-22
| | | | | | | | | | | | | | | | Add support to enable the clock power management for the endpoint. Change-Id: I02bebfeb5d32eb8e1f75ee5feb4c4fff956ece66 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add support to enable common clk config for EPTony Truong2016-03-22
| | | | | | | | | | | | | | | | Add support to enable the common clock configuration for the endpoint. Change-Id: I9f6c33eb6cfa032837a07e437f349a7c1a60704c Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: calculate EP's capability register offsetsTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | | | The start address of the capability register varies depending on the endpoint. This change calculates the endpoint's capability register offset instead of using a fixed one. Change-Id: I28a97d316aee8c34afe313838b91fcc06af0847f Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add PM support for multiple endpoints on a bridgeTony Truong2016-03-22
| | | | | | | | | | | | | | | | | | In the case of multiple endpoints connected to a bridge, PM logic is not present. Therefore, this change adds PM support for when there are multiple endpoints on a bridge. Change-Id: I5a1876db85d0d161ae537a09a508a93b5099aa56 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | msm: pcie: add PCIe bus driver snapshotTony Truong2016-03-22
|/ | | | | | | | | | | | This PCIe bus driver snapshot is taken as of msm-3.10 commit: 803998b (Merge "ASoC: wcd: don't set autozeroing for conga") This change adds the PCIe bus driver and its dependecies from msm-3.10 to msm-3.14. All the files are as is from msm-3.10. No additional changes were made. Change-Id: Ia1a2d0eea0cc87c16357c95bfcc4df72e910cd34 Signed-off-by: Tony Truong <truong@codeaurora.org>
* Merge tag 'pci-v4.4-fixes-4' of ↵Linus Torvalds2016-01-09
|\ | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixlet from Bjorn Helgaas: "This marks the TI DRA7xx host bridge driver as broken. Apparently it has never worked without some additional out-of-tree code, so I'm going to mark it broken now and remove it completely next cycle unless it's fixed" * tag 'pci-v4.4-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: dra7xx: Mark driver as broken
| * PCI: dra7xx: Mark driver as brokenRichard Cochran2016-01-08
| | | | | | | | | | | | | | | | | | | | Mark the dra7xx PCI host driver as broken. This driver was first merged in v3.17 and has never worked. Although the driver compiles just fine, it is missing an essential device reset. If the driver is included, the kernel locks up hard shortly after booting, before any console output appears. Signed-off-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | Merge tag 'pci-v4.4-fixes-3' of ↵Linus Torvalds2015-12-31
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI bugfix from Bjorn Helgaas: "Here's another fix for v4.4. This fixes 32-bit config reads for the HiSilicon driver. Obviously the driver is completely broken without this fix (apparently it actually was tested internally, but got broken somehow in the process of upstreaming it). Summary: HiSilicon host bridge driver Fix 32-bit config reads (Dongdong Liu)" * tag 'pci-v4.4-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: hisi: Fix hisi_pcie_cfg_read() 32-bit reads
| * PCI: hisi: Fix hisi_pcie_cfg_read() 32-bit readsDongdong Liu2015-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For 32-bit config reads (size == 4), hisi_pcie_cfg_read() returned success but never filled in the data we read. Return the register data for 32-bit config reads. Without this fix, PCI doesn't work at all because enumeration depends on 32-bit config reads. The driver was tested internally, but got broken in the process of upstreaming, so this fixes the breakage. Fixes: 500a1d9a43e0 ("PCI: hisi: Add HiSilicon SoC Hip05 PCIe driver") Signed-off-by: Dongdong Liu <liudongdong3@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com>
* | Merge tag 'pci-v4.4-fixes-2' of ↵Linus Torvalds2015-12-09
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: "These are more fixes I'd like to have in v4.4. Several for the Altera driver added for v4.4, and one for an MSI domain problem that affects several arm64 platforms: MSI: - Only use the generic MSI layer when domain is hierarchical (Marc Zyngier) Altera host bridge driver: - Fix loop in tlp_read_packet() (Dan Carpenter) - Fix Requester ID for config accesses (Ley Foon Tan) - Check TLP completion status (Ley Foon Tan) - Fix error when INTx is 4 (Ley Foon Tan)" * tag 'pci-v4.4-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: altera: Fix error when INTx is 4 PCI: altera: Check TLP completion status PCI: altera: Fix Requester ID for config accesses PCI: altera: Fix loop in tlp_read_packet() PCI/MSI: Only use the generic MSI layer when domain is hierarchical
| * PCI: altera: Fix error when INTx is 4Ley Foon Tan2015-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI interrupt lines start at 1, not at 0. So, creates additional one interrupt when register for irq domain. Error when PCIe devices have 4 INTx: WARNING: CPU: 1 PID: 1 at kernel/irq/irqdomain.c:280 irq_domain_associate+0x17c/0x1cc() error: hwirq 0x4 is too large for dummy Tested on Ethernet adapter card with multi-functions. Signed-off-by: Ley Foon Tan <lftan@altera.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: altera: Check TLP completion statusLey Foon Tan2015-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | Check TLP packet successful completion status. This fix the issue when accessing multi-function devices in enumeration process, TLP will return error when accessing non-exist function number. Returns PCI error code instead of generic errno. Tested on Ethernet adapter card with multi-functions. [bhelgaas: simplify completion status checking code] Signed-off-by: Ley Foon Tan <lftan@altera.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: altera: Fix Requester ID for config accessesLey Foon Tan2015-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Requester ID should use the Root Port devfn and it should be always 0. Previously we constructed the Requester ID using the *Completer* devfn, i.e., the devfn of the Function we expect to respond to the config access. This causes issues when accessing configuration space for devices other than the Root Port. Build the Requester ID using the Root Port devfn. Tested on Ethernet adapter card with multi-functions. Signed-off-by: Ley Foon Tan <lftan@altera.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * PCI: altera: Fix loop in tlp_read_packet()Dan Carpenter2015-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TLP_LOOP is 500 and the "loop" variable was a u8 so "loop < TLP_LOOP" is always true. We only need this condition to work if there is a problem so it would have been easy to miss this in testing. Make it a normal for loop with "int i" instead of over thinking things and making it complicated. Fixes: 6bb4dd154ae8 ("PCI: altera: Add Altera PCIe host controller driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ley Foon Tan <lftan@altera.com>
| * PCI/MSI: Only use the generic MSI layer when domain is hierarchicalMarc Zyngier2015-12-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since d8a1cb757550 ("PCI/MSI: Let pci_msi_get_domain use struct device::msi_domain"), we use the MSI domain associated with the PCI device. But finding an MSI domain doesn't mean that the domain is implemented using the generic MSI domain API, and a number of MSI controllers are still using arch_setup_msi_irq() and arch_teardown_msi_irqs(). Check that the domain we just obtained is hierarchical. If it is, we can use the new generic MSI stuff. Otherwise we have to fall back to the old arch_setup_msi_irq() and arch_teardown_msi_irqs() interfaces. This avoids an oops in msi_domain_alloc_irqs() on systems with R-Car, Tegra, Armada 370, and probably other DesignWare-based host controllers. Fixes: d8a1cb757550 ("PCI/MSI: Let pci_msi_get_domain use struct device::msi_domain") Reported-by: Phil Edworthy <phil.edworthy@renesas.com> Tested-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> CC: stable@vger.kernel.org # v4.3+
* | PCI / PM: Tune down retryable runtime suspend error messagesImre Deak2015-12-02
|/ | | | | | | | | | | | | | | | | | | | | | The runtime PM core doesn't treat EBUSY and EAGAIN retvals from the driver suspend hooks as errors, but they still show up as errors in dmesg. Tune them down. See rpm_suspend() for details of handling these return values. Note that we use dev_dbg() for the retryable retvals, so after this change you'll need either CONFIG_DYNAMIC_DEBUG or CONFIG_PCI_DEBUG for them to show up in the log. One problem caused by this was noticed by Daniel: the i915 driver returns EAGAIN to signal a temporary failure to suspend and as a request towards the RPM core for scheduling a suspend again. This is a normal event, but the resulting error message flags a breakage during the driver's automated testing which parses dmesg and picks up the error. Reported-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://bugs.freedesktop.org/show_bug.cgi?id=92992 Signed-off-by: Imre Deak <imre.deak@intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-30 23:56:16 +0000