| Commit message (Collapse) | Author | Age |
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Limiting the max frequency supported by host controller
to a certain value can be useful for testing power consumption
at various frequencies that are supported by the host.
Note: If the card supports less than desired value then the
frequency of operation would be limited to that frequency.
Usage:
mount -t debugfs none /sys/kernel/debug
echo <desired_frequency> > /sys/kernel/debug/mmcX/max_clock
cat /sys/kernel/debug/mmcX/max_clock
Change-Id: I9e9a7e368f56d8e16548780288211bd8775fd048
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
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Currently, bus frequency is set during the card initialization and
never changed until a new card is inserted. In some low power use
cases, scaling the clock frequencies while the card is in transfer
state would allow power savings. This change allows bus frequency
to be changed after the card initialization.
Change-Id: Iac064221199f69d162d91f5311becd735c15700a
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
[merez@codeaurora.org: remove mmc and sd ops_unsafe settings as they are not in 3.14]
Signed-off-by: Maya Erez <merez@codeaurora.org>
[venkatg@codeaurora.org: Fix refactor of mmc_card_* functions as used
in 3.14 kernel]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed trivial merge conflicts & fixed
compilation error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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In mmc_wait_for_req_done() function, change the call wait_for_completion()
to wait_for_compltion_io(). This change makes the kernel account for
wait time as I/O wait and through another configuration, this io wait
is treated as busy which makes the acpu clock to scale up.
Change-Id: Iebdc7b1b22871bf845f10a55e2272816c72d9964
Signed-off-by: Murali Palnati <palnatim@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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Rate limit sdhci_dumpregs() prints to avoid unnecessary
and exessive logging which can sometimes lead to watchdog
timeouts (especially due to bad cards).
Change-Id: Ib6be6d563e47c2d2e9e1b6b0410c2c45712a9b17
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
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Add a new dts entry to define the CPU affinity in order to maintain
the IRQ pm_qos (Quality of Service) for targets that don't have little
cluster and allow setting the pm_qos to the little cluster,
to improve its performance.
Change-Id: Icf6125066d96331392d98a387974e54c96553306
Signed-off-by: Vince Leung <vincentl@codeaurora.org>
Signed-off-by: Maya Erez <merez@codeaurora.org>
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SDCC AXI master uses 32-bit addressing so there's no need to use
64-bit descriptors. Using 32-bit descriptors instead will reduce
the memory footprint.
This change masks the 64-bit capability to force 32-bit ADMA
descriptors.
CRs-Fixed: 719303
Change-Id: Ifb8095763136bbc795227bdfcb346d1e1fae42c7
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
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SDCC5 controller doesn't advertise 1.8v capability by default.
Dual voltage capability is required for SD3.0 support. Add this
capability for controllers that support this based on
device tree configuration.
Change-Id: Ie4cd6db2e7230bc22cd393c8e37d99f49c777cd0
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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With some devices like QRD SKUK, SD card could not support
hotplug as there is no cd-gpio, and also could not use polling
way due to power comsumption. So add nonhotplug to meet such
requirement and when SD card lost or removed manually, device
will not crash until next reboot process to detect SD card.
Change-Id: I318d3db72fc09248c5dada2fb6d69ade1bbf85cb
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
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With some devices, SD card could not support hotplug as there is
no cd-gpio, and also could not use polling way due to power
comsumption. So add nonhotplug to meet such requirement and when
SD card lost or removed manually, device will not crash until
next reboot process to detect SD card.
Change-Id: Ie8ea8ec57015f36689a119249003eeaa48391393
Signed-off-by: Guoping Yu <guopingy@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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The platform_get_resource API may return NULL, hence check
the return value before using the mapped memory.
Change-Id: I28741554f8e1b5843671ee0d6b08bdcf8e4469c9
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
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8K is the max descriptors supported by the hardware per transfer.
On normal use cases we never use that many descriptors even if
the memory is extremely fragmented. The memory allocated for these
descriptors are never freed hence wasting memory otherwise
available for the system. Reduce the max descriptors to 512 to save
memory (128K with 8K descriptors vs 8K with 512 descriptors) and
still support maximum performance.
CRs-fixed: 684185
Change-Id: Ib57ce03834d741c0fda4195a58d6b287ee9fb0a0
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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Instrument the sdhci driver with tracepoints to aid in
debugging issues and identifying latencies in the following
path:
* CMD completion
* DATA completion
* DMA preparation
* Post DMA cleanup
Change-Id: Ie8cd0c2fb6c1bd6ab13883123be021081f8b8f78
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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The current vote applies to all CPUs and hence may have power
impact, especially when there are more number of CPUs. The new
IRQ specific QoS request shall update the vote only for one
CPU to which the IRQ's smp_affinity attribute is set to.
Change-Id: I55298f729949c39ebfa3eecd4746d77e40cb2e5c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
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Program CORE_CSR_CDC_DELAY_CFG for hardware recommended 1.25ns delay.
We may see data CRC errors if it's programmed for any other delay
value.
CRs-Fixed: 683894
Change-Id: Id7de28b7b9222c35e6b419e416f72bd8f98cbaf8
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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In HS400 mode, command line is still operated in SDR mode and not
DDR mode like data lines. So in order to correctly process command
responses, the hardware needs to be set appropriately or else there
will command crc or similar errors due to incorrect sampling of the
response.
Change-Id: I426ff4fc4798afae254d11a608c800dc0b7bf765
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
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The newer msm sdhci's cores use a different DLL hardware for HS400.
Update the configuration and calibration of the newer DLL block.
The HS400 DLL block used previously is CDC LP 533 and requires
programming multiple registers and waiting for configuration to
complete and then enable it. It has about 18 register writes and
two register reads.
The newer HS400 DLL block is SDC4 DLL and requires two register
writes for configuration and one register read to confirm that it
is initialized. There is an additional register write to enable
the power save mode for SDC4 DLL block.
Change-Id: I20ddeaee9309c43cd51bebdfc02d70553c9d2a87
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
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Set up the card detect GPIO in active configuration before
configuring it as an IRQ. Otherwise, it can be in some
weird/inconsistent state resulting in flood of interrupts.
Change-Id: I8f2344a72acbd48df745cc9b2602fe4ac6f034d4
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
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The intention of sdhci_msm_probe() was to wait up to 1ms for
CORE_SW_RST to be set, but only a 10us timeout was passed to
readl_poll_timeout().
Correct the timeout value to be 1ms, and decrease the sleep
time between read attempts to only 10us so that it's less
than the expected wait time of 40us.
Change-Id: I7007a68232bfba76409e2dbae3060622fa5c1913
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
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On fast path, waiting for 1ms interval to poll registers cause
performance degradation. Also having 1ms delays for polling with
interrupts disabled cause considerable system latencies, hence
poll at 1us interval.
Change-Id: I40113ccf56050b3c46604112846e9b37b254d2be
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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For controllers that doesn't support card insertion/removal i.e.,
when the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION is defined,
card_event() host op must not rely on present state register
to check the card's status.
CRs-fixed: 644221
Change-Id: Icff6db0d8fe17f01cf751896ae09aee215edc548
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
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The commit 'e2598c - mmc: sdhci-msm: improve tuning process'
introduces NULL pointer dereference bug for SD 3.0 cards
when all the tuning phases pass. It uses mmc_card_mmc(card)
for checking the card type but card is initialized after
tuning is done for SD card and thus resulting in NULL
pointer dereference issue.
CRs-fixed: 640424
Change-Id: I59a8d5f017243d8391269bc98998bb37fc44f685
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
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As of now we ignore CRC/INDEX command failures to tuning command
and still wait for data from card but in case the card did not
receive the command, it won't send the data. This is causing
software request timeout for tuning commands. Hence, software
must not ignore such cmd errors for tuning commands but end the
request immediately after resetting the controller for both CMD
and DATA. Also, wait for 146 MCLK cycles for card to send out the
data and thus to move to transfer state. Its corresponding phase must
also be considered as bad phase.
CRs-fixed: 625855
Change-Id: Ic8462dd9c67e4f18a3ce73d972591772be8c6d10
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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In newer hardware, the tuning process is not able to always
find a reliable phase to use for sampling data. This is mostly
due to hardware. This problem manifests itself as all successful
tuning phases, which means that the phase choosen could be a bad
one but is not identified as such at the time of tuning. So in
order to work around this, rely on optional drive types implemented
by the eMMC card, in addition to the mandatory drive type (50 ohm).
By using drive types supported by the card, when all phases are
sucessful in tuning, change drive type to a different value in the
list of supported drive types and retune. This will continue for all
tuning phases until a valid one is found. After that the drive type
is reset to the default one, if changed.
Change-Id: I348fb30daa43d97c58f83f7e4a22019f94ef4954
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[venkatg@codeaurora.org: rename cmd_timeout_ms to busy_timeout as
part of 3.14 kernel upgrade]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict & compilation
error]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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This is needed for supporting 64-bit kernel.
Change-Id: Id4f60dc15688a6f02f31d77705ad1ef0181a1ce9
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
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In the current code, if sdhci_check_state returns true a tasklet is
scheduled which doesn't complete the request if host->mrq is NULL,
which is the case, if sdhci is in bad state. This would make the
mmcqd thread wait for completion infinitely.
Hence, complete the request if sdhci_check_state returns true instead
of scheduling the tasklet.
CRs-Fixed: 615537
Change-Id: I8e2950c3999ac3806f9d631c52d86f0dc13b992f
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
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In some cases, it is possible that the hardware might trigger
an interrupt just about the same time the software tries to
reset the controller. In such case, the hardware interrupt will
be handled after the current thread release spin lock. This leads
to spurious interrupt handling after the completion of reset.
Change-Id: I75211adee1179b0636a918f5ceb68a072ad02a6c
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
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If cpu-dma-latency is not defined in dts files, set it
to 200usec
Change-Id: I27b0357b4d88842a258332250bae66efac3ee5e2
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
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There is a new header file for 64bit platforms.
Change-Id: Iead9ccab1fd0b7249baf670e67872fcffeccf21d
Signed-off-by: Raviv Shvili <rshvili@codeaurora.org>
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Add support for Linux pin control framework while also supporting
the older TLMM configuration for backward compatibility
CRs-Fixed: 568232
Change-Id: Ib6b8f41fd6ced9aa62c980d7e4a73469603cbc5b
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
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With commit 0797e5f145 (mmc: core: Fixup signal voltage switch), voltage
switch sequence for UHS-I cards is broken if used with sdhci driver.
The commit expects the SD clock to be disabled when mmc_set_ios() is
issued but sdhci_do_set_ios() re-enables the SD clock for few cycles
after disabling which is a specification violation during voltage
switch sequence. This failure is observed only for a small group of
cards where they ultimately fall-back into high-speed mode even if
UHS-I modes are supported.
Change-Id: Ie275326627a84bfcd4352637a043296c01c175a6
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
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CLK_PWRSAVE bit in vendor specific register gates the output clock to
card automatically if there are no data/cmd operations.
According the SD3.0 voltage switch sequence the host should provide
clock to the card for atleast one millisecond before DAT[3:0] lines
are pulled high by the card. In this case if power save bit is enabled
it might auto-gate clocks even before the card completes voltage
switch sequence.
Fix this by disabling power save operation when the clocks are turned
off and enable only when clock rate is >400KHz i.e., end of initialization.
CRs-Fixed: 589992
Change-Id: If82d6d2e303b8d1189b76712e514f41fe6e2cf8b
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
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Remove maximum timeout for all cards, since this causes
a long resume time for SD cards. Now only Hynix cards would
have this maximum timeout and this would be decided at the core
layer.
Change-Id: I758f9e5ecf407aba371928a86c313cf69e3cda63
CRs-fixed: 587284
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
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With SDCC5 the capabilities register is not advertising the
8-bit capability feature (except for 8974 and 8084).
So add the software capabilities for 8-bit slot for rest of
the targets with SDCC5.
Change-Id: I288292f37d77507bf5aaa44bf156496b4df87234
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
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With SDCC5 the capabilities register is not advertising the
3.0 voltage features (except for 8974 and 8084).
So add the software capabilities for voltage initialization
for rest of the targets with SDCC5.
CRs-Fixed: 568227
Change-Id: Ida53f5ad7249cd0cd8428b4839dfd932b04e31fa
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
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A callback to turn-on the controller clocks is implemented.
This callback would ensure that the pclk and mclk are enabled
but the output clock to the card is disabled.
CRs-Fixed: 567658
Change-Id: Ic97e600a6388fb64f1267a097b201f31d114a1fb
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
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Currently, the clock to the card is enabled prior to enabling
the power to card. Specification requires that the power be
supplied first and then a delay of 10ms and then clock be
provided to the card.
In this, during MMC_POWER_UP mode, the controller clocks would be
ON and the power would be supplied to the card. In the MMC_POWER_ON
mode, the clocks to the card would be enabled and the rate set.
A callback has been provided to facilitate the enabling of
controller clocks.
CRs-Fixed: 567658
Change-Id: I2d66eae1581b9b136faaba4cafc330aeb6a3f364
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[venkatg@codeaurora.org: Fix sdhci_set_power fn signature
as it changed in 3.14 kernel]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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Several data-timeout issues were seen, most of which were
due to the card taking a longer time to respond. This patch
increases the timeout of the controller to 0xF i.e. max
possible.
Change-Id: I6739de3eb5d9cccf8e39d9dc4730056782334162
CRs-Fixed: 536832
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
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On machines that support more than 32-bit address via lpae or 64-bit buses
set the dma mask as 64-bit.
Change-Id: Ida88f3999fd5e7d09ebe73bb3481d3f1f4cf30c2
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
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MSM SDHCI has CDR mechanism (clock-data recovery) to
automatically adjust the sampling point based on the
voltage/temperature variations. This must be enabled
for only read. Hence, add new host op toggle_cdr to
control CDR.
Change-Id: I75940cfca15fe88de6d46fe58cb33620a3b7ced1
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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Currently, the sdhci host lock is initialized in sdhci_add_host()
but there can be a case where it is required even before that.
Hence, initialize it in sdhci_alloc_host() where sdhci_host
structure is allocated.
Change-Id: If99d82679c07bc2d36e0aad9354757288aa400b8
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
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Some platform drivers support more than 128 adma descriptors
and allows more than 512KB maximum request size per transfer.
Add a callback to get maximum supported adma descriptors from
platform driver instead of limiting host capabilities to
128 descriptors.
Change-Id: I0ac0ffbd0e792a76931e21b321b39c35195ac8d6
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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During probe disable the HC mode since the reset is done in
SDCC mode. HC mode will get set after the reset is complete
before the rest of the initialization is done.
Change-Id: I1fdc633c218447c15c8caad24e2805e7510088f2
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
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The SD3.0 voltage switch sequence to 1.8v would involve stopping the
SDCLK before changing the voltage level and with recent changes in 3.10
kernel, the peripheral clocks are also getting disabled instead of
just stopping the clock to the card. This patch makes sure this doesn't
happen by marking the flag card_clock_off in struct mmc_host before
starting the voltage switch sequence and checking it in host controller
driver.
Change-Id: If62378ba1dd369e69524365a4421d57317c22ca2
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
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The power save bit is currently enabled based on the clock
rate (clk_rate > 400KHz) within struct sdhci_msm_host. But this
clk_rate is updated with the latest value down in this function
sdhci_msm_set_clock(). So during runtime/system resume when the
card is still in initialization phase, the power save bit is
getting enabled when sdhci_msm_set_clock() is called for the
first time based on the previous rate which is wrong.
Change-Id: I05dc8a4a760f658935de3831aaf8dd3b2b996466
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
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Enable power save feature within controller by setting bit 1
in vendor specific register (0x10C). This allows controller to
disable SD clock when bus is idle to save power.
Change-Id: I916a5a414adb3f21dc3a75f3f86c3a81d6956dc8
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
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This patch enables automatic calibration for eMMC devices
in using auto-command21. This feature is disabled by default
and can be enabled using the sysfs attribute
'enable_auto_cmd21'.
CRs-Fixed: 516314
Change-Id: I020c61cb9dee56c0ebe37864e67e4753ddee1adc
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
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This patch adds Programmable Delay Line auto-calibration
support if supported by respective hosts.If the host
supports auto-calibration this change would enable
sending CMD19/CMD21 before any read operation.
CRs-Fixed: 516314
Change-Id: I8a0f51206dc0e174519dd71f0c75267a9e08e7f7
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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As per specification, auto cmd error status register is valid only
when auto cmd error bit is set in Error interrupt status register.
CRs-fixed: 515513
Change-Id: Id1013e1705d8efdba0171dcad14f783607d38ef3
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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In HS400 mode a new RCLK is introduced on the interface for read data
transfers. The eMMC5.0 device transmits the read data to the host with
respect to rising and falling edges of RCLK. In order to ensure correct
operation of read data transfers in HS400 mode, the incoming RX data
needs to be sampled by delayed version of RCLK.
The CDCLP533 delay circuit shifts the RCLK by T/4. It needs to be
initialized, configured and enabled once during HS400 mode switch and
when operational voltage/clock is changed.
Change-Id: Ie7acc50cb932a7b531434ebe72f78e2e7ad27408
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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The following msm platform specific changes are added to support HS400.
- Enable CDC calibration fixed feedback and sleep clock.
- Allow tuning for HS400 mode.
- Add capability to parse and configure pull settings for RCLK pin.
- Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register.
Change-Id: I1304fe0f01df493ead48bf9ff3c7baee5ab040d4
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
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