| Commit message (Collapse) | Author | Age |
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There isn't any need to be in secure mode when executing the GPMU
initalization so swap out to eliminate it as a variable when
GPMU init goes broken.
Change-Id: Ic0dedbad07b8cde80e257f71999002e9cbc47c24
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Enable pm_runtime for the GPU to keep power collapse from hitting
us while we expect the GPU to be powered.
Change-Id: Ic0dedbad693f1d01776a87bc7a145a65510ac3fb
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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If we do not enable the iommu clocks at attach time they might
be shut off automatically by other devices power collapsing which
would affect our ability to switch the pagetable dynamically.
There is little power downside to just leaving them on all the time,
or at least as long as the main device is attached (in other words,
all the time).
Change-Id: Ic0dedbad8f6d2ee2a2cb9516e062af2421d91052
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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The overrun check for the size of submitted commands is off by one.
It should allow the offset plus the size to be equal to the
size of the memory object when the command stream is very tightly
constructed.
Change-Id: Ic0dedbadec41fb8be84d7522b4dc923dbd537ce5
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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When a fault happens on the Adreno GPU we want to collect
a considerable amount of information to diagnose the problem
including registers, caches, and GPU memory structures (ringbuffers,
etc).
The snapshot collects all of this information following a GPU fault
and encodes it into a binary file format that can be pulled from
debugfs or extracted from a memory dump.
This may seem a duplication of other debug methods (the ->show
functions for example) and while that is true for small numbers
of registers the snapshot goes much further - it collects hundreds
(thousands) of registers in addition to memory and other structures
that would be impractical to dump as ascii. The binary format allows
for the snapshot to be easily shared and post-processed in different
ways to extract patterns.
Add the basic snapshot infrastructure and enable ringbuffer, register
and shader bank collection for A5XX targets.
Change-Id: Ic0dedbadcf0513096d05870f522ac73da74ceb31
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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There are some use cases wherein we need to turn off hardware clock
gating before reading certain registers. Modify the A5XX HWCG function
to allow user to enable or disable clock gating at will.
Change-Id: Ic0dedbade1264785b3436099e638a5678a62818f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Update the list of the A5XX register ranges that can be read on a
hang. The new list adds some registers that were previously missed,
and omits registers that are write only.
Change-Id: Ic0dedbadaf6969892c0563d9cfd8fa2869008417
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Instead of using a fixed list of clock names, use the clock-names
list in the device tree to discover and get the list of clocks
that we need.
Change-Id: Ic0dedbad629743ff078177c301ffda3dbce88d3c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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There are reasons for a memory object to outlive the file descriptor
that created it and so the address space that a buffer object is
attached to must also outlive the file descriptor. Reference count
the address space so that it can remain viable until all the objects
have released their addresses.
Change-Id: Ic0dedbad3769801b62152d81b37f2f43f962d308
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Support per-instance pagetables for 5XX targets. Per-instance
pagetables allow each open DRM instance to have its own VM memory
space to prevent accidently or maliciously copying or overwriting
buffers from other instances. It also opens the door for SVM since
any given CPU side address can be more reliably mapped into the
instance's GPU VM space without conflict.
To support this create a new dynamic domain (pagetable) for each open
DRM file and map buffer objects for each instance into that pagetable.
Use the GPU to switch to the pagetable for the instance while doing a
submit.
Change-Id: Ic0dedbad22d157d514ed1628b83e8cded5490dec
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Dynamic IOMMU domains allow multiple pagetables to be attached to the
same IOMMU device. These can be used by smart devices like the GPU
that can switch the pagetable dynamically between DRM instances.
Add support for dynamic IOMMU domains if they are enabled and
supported by your friendly neighborhood IOMMU driver.
Change-Id: Ic0dedbaded3a9e57a7fbb8e745c44c183f6b4655
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path.
Change-Id: Ic0dedbad3761b0f72ad6b1789f69458896214239
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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A5XX GPUs can be run in either 32 or 64 bit mode. The GPU registers
and the microcode use 64 bit virtual addressing by default but the
upper 32 bits are ignored if the GPU is in 32 bit mode. There is no
performance disadvantage to remaining in 64 bit mode even if we are
only generating 32 bit addresses so switch over now to prepare for
possibly using addresses above 4G for those targets that support them.
Change-Id: Ic0dedbad7e527c4b1fe87878e943619c5e0ad869
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.
Change-Id: Ic0dedbad6c62d6859c90764245437c222d61f00d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Implement preemption for A5XX targets - this allows multiple
ringbuffers for different priorities with automatic preemption
of a lower priority ringbuffer if a higher one is ready.
Change-Id: Ic0dedbad428360d23768d52b585021237c6bc3d3
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Remove the IOMMU_WRITE bit from buffer objects that are
marked MSM_BO_GPU_READONLY. Add a new flag (MSM_BO_PRIVILEGED)
to pass through IOMMU_PRIV for those IOMMU targets that support
it.
Change-Id: Ic0dedbad8d9d3f461a47ea093fad3fdd90f46535
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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We use a global ringbuffer size and block size for all targets and
at least for 5XX preemption we need to know the value the RB_CNTL
in several locations so it makes sense to caculate it once and use
it everywhere.
The only monkey wrench is that we need to disable the RPTR shadow
for A430 targets but that only needs to be done once and doesn't
affect A5XX so we can or in the value at init time.
Change-Id: Ic0dedbadca31e835f014037ea3f9741048df3b98
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add a shadow pointer to track the current command being written into
the ring. Don't commit it as 'cur' until the command is submitted.
Because 'cur' is used to construct the software copy of the wptr this
ensures that somebody peeking in on the ring doesn't assume that a
command is inflight while it is being written. This isn't a huge deal
with a single ring (though technically the hangcheck could assume
the system is prematurely busy when it isn't) but it will be rather
important for preemption where the decision to preempt is based
on a non-empty ringbuffer. Without a shadow an aggressive preemption
scheme could assume that the ringbuffer is non empty and switch to it
before the CPU is done writing the command and boom.
Even though preemption won't be supported for all targets because of
the way the code is organized it is simpler to make this generic for
all targets. The extra load for non-preemption targets should be
minimal.
Change-Id: Ic0dedbad83247c3e77de6f4f24bbb97db10e5edd
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add the infrastructure for supporting multiple ringbuffers.
Change-Id: Ic0dedbada90ec5c4c8074ffce33c3fe275b0cda1
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Return the base address of GMEM in virtual address space as
a parameter.
Change-Id: Ic0dedbad3b849052313e4673efcf6c22bc81f21f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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memptrs->wptr seems to be unused. Remove it to avoid
confusing the upcoming preemption code.
Change-Id: Ic0dedbadacef5e866bd37a332019f1133f1def49
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the
user sets 'hint' to non-zero it means that they want a IOVA for the
GEM object instead of a mmap() offset. Return the iova in the 'offset'
member.
Change-Id: Ic0dedbad543df80fdc4b74cd1cd924e9b8534b44
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add support for the A540 GPU which is a revision of the A530 target
with somewhat more complicated power management support.
Change-Id: Ic0dedbadeca628809b6de7c1843f665ecdc427fe
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Bring in a new revision of the rnndb register to fill out some A540
registers.
Change-Id: Ic0dedbad0daf9ad2301479354a83c05bdc301163
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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In the current code the probed configuration is pretty light and it
can be easily probed at boot time and stored in a config struct.
As more features come online the configuration becomes tougher and
more platform specific. It makes sense to do the configuration in
real time so move the majority of the config over to adreno_gpu and
probe at load.
Change-Id: Ic0dedbade871aae2d39e6b036a5e73e4347fc7ca
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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The A5XX GPU powers on in "secure" mode. In secure mode the GPU can
only render to buffers that are marked as secure and inaccessible
to the kernel and user through a series of hardware protections. In
practice secure mode is used to draw things like a UI on a secure
video frame.
In order to switch out of secure mode the GPU executes a special
shader that clears out the GMEM and other sensitve registers and
then writes a register. Because the kernel can't be trusted the
shader binary is signed and verified and programmed by the
trustzone using the PIL loader to upload the binary and access
to the special register is blocked with hardware protection.
So in summary, to do secure mode correctly you need 1) a friendly
trustzone, 2) PIL loader support and 3) a verified zap shader.
For targets without secure support there is an out: if the
trustzone doesn't support secure then there are no hardware
protections and we can freely write the SECVID_TRUST register from
the CPU. Unfortunately we don't have any good way to figure out
at runtime if the trustzone is secure or not so we use a cheat.
If there is a zap shader specified in the device tree for the
target, we assume that the trustzone is secure. No zap shader
definition means that the target is not secure. The downside
of course is that if you guess wrong you trigger a XPU violation
which usually ends up in a system crash but thats a problem
that shows up immediately.
Change-Id: Ic0dedbad8738ad1fac8a7bb8d76e1988aa49f2c8
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Most 5XX targets have GPMU (Graphics Power Management Unit) that
handles a lot of the heavy lifting for power management including
thermal and limits management and dynamic power collapse. While
the GPMU itself is optional, it is usually nessesary to hit
aggressive power targets.
If the GPMU is to be used a filename and minimum version are
defined in the device tree. The GPMU firmware needs to be loaded
into the GPMU at init time via a shared hardware block of registers.
Using the GPU to write the microcode is more efficient than using the
CPU so at first load create an indirect buffer that can be executed
during subsequent initalization sequences.
After loading the GPMU gets initalized through a shared register
interface and then we mostly get out of its way and let it do
its thing.
Change-Id: Ic0dedbad8d899177919b71500f2e944b187e87c0
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add support for the A5XX family of Adreno GPUs.
Change-Id: Ic0dedbad665ef9d0f2cdb32a33eef9fe3fd7aa5c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Verify that the GPU is valid before calling any ioctl functions
that might need the priv->gpu member. Standardize the return
code (-ENXIO).
Change-Id: Ic0dedbad015a531b792e0b94cb61e0570b691de8
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Currently the value written to CP_RB_WPTR is calculated on the fly as
(rb->next - rb->start). But as the code is designed rb->next is wrapped
before writing the commands so if a series of commands happened to
fit perfectly in the ringbuffer, rb->next would end up being equal to
rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR.
The easiest way to fix this is to mask WPTR when writing it to the
hardware; it makes the hardware happy and the rest of the ringbuffer
math appears to work and there isn't any point in messing with things.
Change-Id: Ic0dedbade543a2253b88acf46a8f8e062ae7faf9
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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For every submission buffer object one of MSM_SUBMIT_BO_WRITE
and MSM_SUBMIT_BO_READ must be set (and nothing else). If we
allowed zero then the buffer object would never get queued to
be unreferenced.
Change-Id: Ic0dedbad8a4543428372fe3fef9503cedd1eef6e
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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The upstream DT model presumes that the iommu phandle is in the main
GPU device node. The downstream model defines sub-nodes for the
IOMMU devices. In order to get the right device to attach the IOMMU
domain to we need to do a bit of searching.
First, check in the top level node. If that fails, then start walking
the port list passed in the attached function - hopefully one of those
will have the right device - if found, use that to attach the domain
and breathe normally.
Change-Id: Ic0dedbad4a1852d2ff204031bd360e0b7960805a
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Newer Adreno GPUs are able to support 64 bit virtual addressing. To
prepare for this brave new world switch all IOVA related variables
and members to a uint64_t container. This is harmless for the
display and older targets that do not have 64 bit addressing because
a 32 bit address is just a 64 bit address with lots of zeros. To
avoid ambiguity and compiler oddness make sure to use
lower_32_bits() and upper_32_bits() everywhere the IOVA is used to
ensure that you get what you expect.
Change-Id: Ic0dedbad23322fae32509c1f4d75d9b4e2863081
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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In the future we won't have a fixed set of addresses spaces.
Instead of going through the effort of assigning a ID for each
address space just use the address space itself as a token for
getting / putting an iova.
This forces a few changes in the gem object however: instead
of using a simple index into a list of domains, we need to
maintain a list of them. Luckily the list will be pretty small;
even with dynamic address spaces we wouldn't ever see more than
two or three.
Change-Id: Ic0dedbad4495f02a21135217f3605b93f8b8dfea
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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PM_QOS will put the interrupt where it wants to and we're okay
with that.
Change-Id: Ic0dedbad5294d51a55125a0021f7dcc3b185de02
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Disable the interrupt during the init sequence to avoid having
interrupts fired for errors and other things that we are not
ready to handle while initializing.
Change-Id: Ic0dedbad972f25586e792478f9c96c4af7c31d17
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add some new functions to manipulate GPU registers. gpu_read64 and
gpu_write64 can read/write a 64 bit value to two 32 bit registers.
For 4XX and older these are normally perfcounter registers, but
future targets will use 64 bit addressing so there will be many
more spots where a 64 bit read and write are needed.
gpu_rmw() does a read/modify/write on a 32 bit register given a mask
and bits to OR in.
Change-Id: Ic0dedbadb83d3ac46f7e463c9c901d4f94a7bb58
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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There are very few register accesses in the common code. Cut down
the list of common registers to just those that are used. This
saves const space and saves us the effort of maintaining registers
for A3XX and A4XX that don't exist or are unused.
Change-Id: Ic0dedbadb4dccbba284e9badf2f52f3a72594581
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add helper functions for TYPE4 and TYPE7 ME opcodes that replace
TYPE0 and TYPE3 starting on the A5XX targets.
Change-Id: Ic0dedbad114e28bdbcba55a788c6307b48e14675
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Bring in refreshed register definitions from the rnndb database.
Change-Id: Ic0dedbaddd22f6ac0b8cfb6184073968569de22d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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_get_svm_area can fail to find available address range
from mmap_base which was adjusted by random factor.
By logging mmap_base value will help to identify
any issue with the VA randomization.
Change-Id: Ibdc3fac975adde02c30aa253b53d6533ee558161
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
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Sometimes ringbuffer timer is not getting updated due to
race with the preemption. This can cause dispatcher to
detect false timeout gpu faults. Remove preempt state
check in adreno_dispatch_process_drawqueue(), which will
allow to update ringbuffer timeout value irrespective of
the preemption state.
If the preemption completes successfully, preemption logic
updates timer for new_rb. We don’t need to care if it is
not updated for prev_rb. If preemption in-progress timer
will be updated for cur_rb in adreno_dispatch_process_drawqueue().
In both cases we are taking care to update ringbuffer timer.
Hence we don’t need to check preemption state.
CRs-Fixed: 1095344
Change-Id: I0e0ec655e2262c4f499748ce35a8d710ed15b5e3
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
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When the GPU hardware init function fails (like say, ME_INIT timed
out) return error instead of blindly continuing on. This gives us
a small chance of saving the system before it goes boom.
Change-Id: Ic0dedbad142efbc9bd93e8531b40c391ec15f557
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Make sure to detach the MMU device before destroying the address
space.
Change-Id: Ic0dedbadff27fed017840a61ec5e0d55ce0c71e6
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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SDE and the GPU have different requirements for the SMMU backends - the
SDE generates its own iova addresses and needs special support for DMA
buffers and the GPU does its own IOMMU operations. Add a shim layer to
aspace to break out the address generation and call the appropriate
SMMU functions. There is probably consolidation that can be done, but for
now this is the best way to deal with the two use cases.
Change-Id: Ic0dedbadc6dc03504ef7dffded18ba09fb3ef291
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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We can have various combinations of 64b and 32b address space, ie. 64b
CPU but 32b display and gpu, or 64b CPU and GPU but 32b display. So
best to decouple the device iova's from mmap offset.
Change-Id: Ic0dedbad2b36b535df3e8fb2ddddc20add592cea
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 22877bcbdacd50d076f9b2f829e6a3753aa9821f
Git-repo: https://github.com/freedreno/kernel-msm.git
[jcrouse@codeaurora.org: Fix merge conflicts, remove mdp5 due to large
infrastructure changes, compile fixes]
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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