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| | * | | drm/radeon/kms: add dpm support for KB/KVAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds dpm support for KB/KV asics. This includes: - dynamic engine clock scaling - dynamic voltage scaling - power containment - shader power scaling Set radeon.dpm=1 to enable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/dpm: add helper to fetch the vrefresh of the current modeAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Needed for DPM on CI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/dpm: add a helper to encode pcie lane settingAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | convert from number of lanes to register setting. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/dpm: add vce clocks to radeon_psAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: add r600_get_pcie_lane_support helperAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: parse the acp clock voltage deps tableAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: parse the samu clock voltage deps tableAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/dpm: clean up the extended table error pathesAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: parse the uvd clock voltage deps tableAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: parse the vce clock voltage deps tableAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: add clock voltage dep tables for acp, samuAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: add structs to store vce clock voltage depsAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Used for vce power management. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/dpm: grab mvdd_dependency_on_mclk info from vbiosAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Required for dpm on CI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/dpm: add support for parsing the atom powertune tableAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Needed for DPM on CI. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/dpm: update cac leakage table parsing for CIAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Uses a different table format if the board supports EVV. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: adjust si_dpm function for code sharingAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: add get_temperature() callbacks for CIK (v2)Alex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This added support for the on-chip thermal sensors on CIK asics. v2: fix register offset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: add KB/KV to r600_is_internal_thermal_sensorAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: add CI to r600_is_internal_thermal_sensor()Alex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: add support for thermal controller on KB/KVAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No support for reading temperature back yet. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/cik: add rlc helpers for DPMAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: add structs to store uvd clock voltage depsAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Used for uvd power management. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: switch to pptable.hAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Internally we switched to using a separate header for atombios pplib definitions. Switch over the open source driver. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/sumo add helper to go from vid7 to vid2Alex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Needed for DPM on KB/KV. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: add indirect accessors for dift registers on CIKAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: implement clock and power gating for CIK (v3)Alex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only the APUs support power gating. v2: disable cgcg for now v3: workaround hw issue in mgcg Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: convert SI,CIK to use sumo_rlc functionsAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and remove duplicate si_rlc functions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: clean up sumo_rlc_init() for code sharingAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will eventually be shared with newer asics to reduce code duplication. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/cik: restructure rlc setupAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Restructure rlc setup to handle clock and power gating. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: add support for ASPM on CIK asicsAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enables PCIE ASPM (Active State Power Management) on CIK asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/cik: add support for pcie gen1/2/3 switchingAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: switch CIK to use radeon_ucode.hAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/cik: implement some more atom helpers for DPMAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Required for DPM on CIK. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/kms: fix up dce8 display watermark calc for dpmAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calculate the low and high watermarks based on the low and high clocks for the current power state. The dynamic pm hw will select the appropriate watermark based on the internal dpm state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/dpm: use performance state if no UVD stateAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer asics don't have specific UVD states. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: default to 1024M gart size on rv770+Alex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer asics have a lot of vram so it's less of an issue to waste a little more space for the gart page table. This gives us some additional gart space before having to migrate to non-gart system ram for games, etc. where we use up most of vram. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/dpm: rework thermal state handlingAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Handle the the thermal state directly in the work handler. Remove the state selection function since nothing else uses it now. 2. On some asics there is no thermal state, so we just use a regular state and force the low performance state. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/dpm: use multiple UVD power states (v3)Alex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the UVD handle information to determine which which power states to select when using UVD. For example, decoding a single SD stream requires much lower clocks than multiple HD streams. v2: switch to a cleaner dpm/uvd interface v3: change the uvd power state while streams are active if need be Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: add UVD->DPM helper function (v5)Alex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a helper function for counting the number of open stream handles. v2: fix copy-pasta in comments and whitespace error v3: make function static since it's only used in radeon_uvd.c at the moment v4: make non-static again for future changes v5: make static again for new rework of dpm uvd changes Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon/kms: remove r6xx+ blit copy routinesAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No longer used now that we use the async dma engines or CP DMA for bo copies. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/radeon: switch r6xx+ to using CP DMA for the blit copy callbackAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CP DMA is lighter weight than using the 3D engine. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * | | drm/edid: add quirk for Medion MD30217PGAlex Deucher2013-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This LCD monitor (1280x1024 native) has a completely bogus detailed timing (640x350@70hz). User reports that 1280x1024@60 has waves so prefer 1280x1024@75. Manufacturer: MED Model: 7b8 Serial#: 99188 Year: 2005 Week: 5 EDID Version: 1.3 Analog Display Input, Input Voltage Level: 0.700/0.700 V Sync: Separate Max Image Size [cm]: horiz.: 34 vert.: 27 Gamma: 2.50 DPMS capabilities: Off; RGB/Color Display First detailed timing is preferred mode redX: 0.645 redY: 0.348 greenX: 0.280 greenY: 0.605 blueX: 0.142 blueY: 0.071 whiteX: 0.313 whiteY: 0.329 Supported established timings: 720x400@70Hz 640x480@60Hz 640x480@72Hz 640x480@75Hz 800x600@56Hz 800x600@60Hz 800x600@72Hz 800x600@75Hz 1024x768@60Hz 1024x768@70Hz 1024x768@75Hz 1280x1024@75Hz Manufacturer's mask: 0 Supported standard timings: Supported detailed timing: clock: 25.2 MHz Image Size: 337 x 270 mm h_active: 640 h_sync: 688 h_sync_end 784 h_blank_end 800 h_border: 0 v_active: 350 v_sync: 350 v_sync_end 352 v_blanking: 449 v_border: 0 Monitor name: MD30217PG Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 83 kHz, PixClock max 145 MHz Serial No: 501099188 EDID (in hex): 00ffffffffffff0034a4b80774830100 050f010368221b962a0c55a559479b24 125054afcf00310a0101010101018180 000000000000d60980a0205e63103060 0200510e1100001e000000fc004d4433 3032313750470a202020000000fd0038 4c1e530e000a202020202020000000ff 003530313039393138380a2020200078 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reported-by: friedrich@mailstation.de Cc: stable@vger.kernel.org
| * | | | Merge tag 'drm-intel-next-2013-08-23' of ↵Dave Airlie2013-08-30
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~danvet/drm-intel into drm-next Need to get my stuff out the door ;-) Highlights: - pc8+ support from Paulo - more vma patches from Ben. - Kconfig option to enable preliminary support by default (Josh Triplett) - Optimized cpu cache flush handling and support for write-through caching of display planes on Iris (Chris) - rc6 tuning from Stéphane Marchesin for more stability - VECS seqno wrap/semaphores fix (Ben) - a pile of smaller cleanups and improvements all over Note that I've ditched Ben's execbuf vma conversion for 3.12 since not yet ready. But there's still other vma conversion stuff in here. * tag 'drm-intel-next-2013-08-23' of git://people.freedesktop.org/~danvet/drm-intel: (62 commits) drm/i915: Print seqnos as unsigned in debugfs drm/i915: Fix context size calculation on SNB/IVB/VLV drm/i915: Use POSTING_READ in lcpll code drm/i915: enable Package C8+ by default drm/i915: add i915.pc8_timeout function drm/i915: add i915_pc8_status debugfs file drm/i915: allow package C8+ states on Haswell (disabled) drm/i915: fix SDEIMR assertion when disabling LCPLL drm/i915: grab force_wake when restoring LCPLL drm/i915: drop WaMbcDriverBootEnable workaround drm/i915: Cleaning up the relocate entry function drm/i915: merge HSW and SNB PM irq handlers drm/i915: fix how we mask PMIMR when adding work to the queue drm/i915: don't queue PM events we won't process drm/i915: don't disable/reenable IVB error interrupts when not needed drm/i915: add dev_priv->pm_irq_mask drm/i915: don't update GEN6_PMIMR when it's not needed drm/i915: wrap GEN6_PMIMR changes drm/i915: wrap GTIMR changes drm/i915: add the FCLK case to intel_ddi_get_cdclk_freq ...
| | * | | | drm/i915: Print seqnos as unsigned in debugfsVille Syrjälä2013-08-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I don't like seeing signed seqnos. Make them unsigned. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | * | | | drm/i915: Fix context size calculation on SNB/IVB/VLVVille Syrjälä2013-08-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All the different context sizes reported in the CXT_SIZE register aren't meant to be simply added together. While BSpec is somewhat unclear on the topic of the actual context size, empirical tests have now revealed the truth. So let's add a big fat comment to remind people how it all works. As a result of correctly interpreting CXT_SIZE, the IVB context size is reduced from three pages to two, while SNB context size remains at two pages. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | * | | | drm/i915: Use POSTING_READ in lcpll codeDaniel Vetter2013-08-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we don't use the return value of a mmio read our coding style is to use the POSTING_READ macro. This avoids cluttering the mmio traces. While at it add the missing posting read in the lcpll enable function that Paulo spotted. v2: Drop the _NOTRACE changes, tracing such wait_for loops in the modeset code might actually be rather useful! Cc: Paulo Zanoni <przanoni@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | * | | | drm/i915: enable Package C8+ by defaultPaulo Zanoni2013-08-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should be working, so enable it by default. Also easy to revert. v2: Rebase, s/allow/enable/. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | * | | | drm/i915: add i915.pc8_timeout functionPaulo Zanoni2013-08-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently only enter PC8+ after all its required conditions are met, there's no rendering, and we stay like that for at least 5 seconds. I chose "5 seconds" because this value is conservative and won't make us enter/leave PC8+ thousands of times after the screen is off: some desktop environments have applications that wake up and do rendering every 1-3 seconds, even when the screen is off and the machine is completely idle. But when I was testing my PC8+ patches I set the default value to 100ms so I could use the bad-behaving desktop environments to stress-test my patches. I also thought it would be a good idea to ask our power management team to test different values, but I'm pretty sure they would ask me for an easy way to change the timeout. So to help these 2 cases I decided to create an option that would make it easier to change the default value. I also expect people making specific products that use our driver could try to find the perfect timeout for them. Anyway, fixing the bad-behaving applications will always lead to better power savings than just changing the timeout value: you need to stop waking the Kernel, not quickly put it back to sleep again after you wake it for nothing. Bad sleep leads to bad mood! Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | * | | | drm/i915: add i915_pc8_status debugfs filePaulo Zanoni2013-08-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make it print the value of the variables on the PC8 struct. v2: Update to recent renames and add the new fields. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| | * | | | drm/i915: allow package C8+ states on Haswell (disabled)Paulo Zanoni2013-08-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows PC8+ states on Haswell. These states can only be reached when all the display outputs are disabled, and they allow some more power savings. The fact that the graphics device is allowing PC8+ doesn't mean that the machine will actually enter PC8+: all the other devices also need to allow PC8+. For now this option is disabled by default. You need i915.allow_pc8=1 if you want it. This patch adds a big comment inside i915_drv.h explaining how it works and how it tracks things. Read it. v2: (this is not really v2, many previous versions were already sent, but they had different names) - Use the new functions to enable/disable GTIMR and GEN6_PMIMR - Rename almost all variables and functions to names suggested by Chris - More WARNs on the IRQ handling code - Also disable PC8 when there's GPU work to do (thanks to Ben for the help on this), so apps can run caster - Enable PC8 on a delayed work function that is delayed for 5 seconds. This makes sure we only enable PC8+ if we're really idle - Make sure we're not in PC8+ when suspending v3: - WARN if IRQs are disabled on __wait_seqno - Replace some DRM_ERRORs with WARNs - Fix calls to restore GT and PM interrupts - Use intel_mark_busy instead of intel_ring_advance to disable PC8 v4: - Use the force_wake, Luke! v5: - Remove the "IIR is not zero" WARNs - Move the force_wake chunk to its own patch - Only restore what's missing from RC6, not everything Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
generated by cgit v1.2.3 (git 2.25.1) at 2026-07-17 15:11:27 +0000