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For some optimizations coming on the userspace side, splitting larger
draw or gmem cmds into multiple cmdstream buffers, we need to support
much more than the previous small/arbitrary limit.
Change-Id: Ic0dedbad2f79156f4e6c9f70c8e27cd5fff9acdb
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 6b597ce2f7c7a0f8116d753902db9aba6bc05cb0
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[jcrouse@codeaurora.org: fix some merge conflicts]
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Zero sized buffer objects tend to make various bits of the GEM
infrastructure complain:
WARNING: CPU: 1 PID: 2323 at drivers/gpu/drm/drm_mm.c:389 drm_mm_insert_node_generic+0x258/0x2f0
Zero sized buffers serve no appreciable value to the user so disallow
them at create time.
Change-Id: Ic0dedbada2a0250227d7ee8c45c35dc92a826c67
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Remove deprecated mdss_mdp node entry from msm drm driver.
Change-Id: Ifdfb39259d38cd0bed33585076b33fb15a953fbd
Signed-off-by: Narender Ankam <nankam@codeaurora.org>
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At this point, there is nothing left to fail. And submit already has a
fence assigned and is added to the submit_list. Any problems from here
on out are asynchronous (ie. hangcheck/recovery).
Change-Id: Ib6b6bf00099137972649c97cc6cd8c4fe25ce7c3
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 1193c3bcb581807d58dd7df90528ec744af387a9
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[smasetty@codeaurora.org: fixed merge conflict issues; made corresponding
changes to A5XX submit function.]
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
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Any memory free ioctl doesn't need to be blocked till the
corresponding mementry is destroyed. This change defers
the mementry put to unblock all memory free ioctls immediately.
This is done to reduce the time spent by user applications in
waiting for memory to be freed.
Change-Id: Iaa37ac5dbdedc3d02c41886c2bdf7f3d016176ac
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
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Allow the user to allocate and use secured buffer objects. Secured
buffer objects are suitable for use as a write target while the GPU
is in secure mode. They work exactly like regular buffers except
Secure buffers cannot be mmap()ed.
Change-Id: Ic0dedbadd8135fd8472b38ddf61e2bc70983b12f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Check to see if an imported buffer is an Ion secure buffer and mark
it as such so that it can be used for secure rendering.
Change-Id: Ic0dedbadb414dcbb11d70785d61481a1b7bd4e19
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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A5XX targets support GPU rendering on secured surfaces by going
into a special secure mode to execute the commands. In secure mode
GPU rendering can only write to secure buffers that have been mapped
in an appropriately secured pagetable. In secure mode the GPU can read
both secure and unsecure buffers and the CP engine can only access
unsecured buffers (so commands do not need to be secure).
Secure buffers virtual addresses must fall into a specific range; this
is the clue to the GPU that it should use the secure pagetable
instead of the regular one. For A5XX targets that range will start
at 0xC0000000 and be 256MB in size. All secure buffers in all processes
share the same pagetable.
Add a secure address space for A5XX targets and automatically trigger
into secure mode if any buffer in the submission is marked as secure.
Change-Id: Ic0dedbad8f7168711d10928cd1894b98f908425f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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This patch contains fixes to prevent the CRTC's atomic check
from inadvertently adding extra plane states to the current
state object.
CRs-Fixed: 2037970
Change-Id: Ic0b09ab369f77c2412ba7c3e63fe5032ef9bcd74
Signed-off-by: Clarence Ip <cip@codeaurora.org>
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Simplify the clearing of the topology name by moving it directly
to the release resources call.
Change-Id: If1926372b276f01f64138691b805493d1894951a
Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
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SDE HDMI driver capabilities were capped
to 1080P due to lack of dual pipe support in userspace.
Relax this restriction as full userspace support to
allow dual pipe support is now available.
Change-Id: If8242ea3c65a901ceb3e1004ac40b29ab8554c4b
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
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HDMI connector should wait for audio codec status and notify
HPD status only in case that audio codec has been registered
successfully. Meanwhile move HPD notification to bridge enable
and disable instead of hotplug work. This ensures the correct
video and audio sequence.
Change-Id: I0dac915c8639bb881265a608016e9d37ec9a153c
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
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* refs/heads/tmp-24ac44d
Linux 4.4.66
ftrace/x86: Fix triple fault with graph tracing and suspend-to-ram
ARCv2: save r30 on kernel entry as gcc uses it for code-gen
nfsd: check for oversized NFSv2/v3 arguments
Input: i8042 - add Clevo P650RS to the i8042 reset list
p9_client_readdir() fix
MIPS: Avoid BUG warning in arch_check_elf
MIPS: KGDB: Use kernel context for sleeping threads
ALSA: seq: Don't break snd_use_lock_sync() loop by timeout
ALSA: firewire-lib: fix inappropriate assignment between signed/unsigned type
ipv6: check raw payload size correctly in ioctl
ipv6: check skb->protocol before lookup for nexthop
macvlan: Fix device ref leak when purging bc_queue
ip6mr: fix notification device destruction
netpoll: Check for skb->queue_mapping
net: ipv6: RTF_PCPU should not be settable from userspace
dp83640: don't recieve time stamps twice
tcp: clear saved_syn in tcp_disconnect()
sctp: listen on the sock only when it's state is listening or closed
net: ipv4: fix multipath RTM_GETROUTE behavior when iif is given
l2tp: fix PPP pseudo-wire auto-loading
l2tp: take reference on sessions being dumped
net/packet: fix overflow in check for tp_reserve
net/packet: fix overflow in check for tp_frame_nr
l2tp: purge socket queues in the .destruct() callback
net: phy: handle state correctly in phy_stop_machine
net: neigh: guard against NULL solicit() method
sparc64: Fix kernel panic due to erroneous #ifdef surrounding pmd_write()
sparc64: kern_addr_valid regression
xen/x86: don't lose event interrupts
usb: gadget: f_midi: Fixed a bug when buflen was smaller than wMaxPacketSize
regulator: core: Clear the supply pointer if enabling fails
RDS: Fix the atomicity for congestion map update
net_sched: close another race condition in tcf_mirred_release()
net: cavium: liquidio: Avoid dma_unmap_single on uninitialized ndata
MIPS: Fix crash registers on non-crashing CPUs
md:raid1: fix a dead loop when read from a WriteMostly disk
ext4: check if in-inode xattr is corrupted in ext4_expand_extra_isize_ea()
drm/amdgpu: fix array out of bounds
crypto: testmgr - fix out of bound read in __test_aead()
clk: sunxi: Add apb0 gates for H3
ARM: OMAP2+: timer: add probe for clocksources
xc2028: unlock on error in xc2028_set_config()
f2fs: do more integrity verification for superblock
net: pppolac/pppopns: Add back the msg_flags
Conflicts:
drivers/regulator/core.c
Change-Id: I8e7b279efa442a0338ee735d27ff3ebe866a8dee
Signed-off-by: Blagovest Kolenichev <bkolenichev@codeaurora.org>
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commit 484f689fc9d4eb91c68f53e97dc355b1b06c3edb upstream.
When the initial value of i is greater than zero,
it may cause endless loop, resulting in array out
of bounds, fix it.
This is a port of the radeon fix to amdgpu.
Signed-off-by: tom will <os@iscas.ac.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Julia Lawall <julia.lawall@lip6.fr>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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The "_header" field of the macro was being incorrectly expanded to just
"header". This was only working because all the functions which used this
macro already had "header" defined in scope.
Change-Id: I19e77ae78cfff471ddffd428cb3fd055c6340737
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
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This patch helps dump the full 64k per ring preemption
record to GPU snapshot which is collected during GPU
recovery step. We use the general object snapshot section
type to store these records and we only collect the preemption
records if preemption was going to kick in, which is when
the number of rings is greater than one.
Change-Id: I1872bc14c6b39c8c4963ce9c98e96b03cbfec907
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
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msm-4.4"
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Conflicts:
arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi
drivers/gpu/drm/msm/Makefile
Change-Id: Ief80c28ff1422fd71a0c3d2041531e2ab078ee7a
Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
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DSI display list sequence should be consistent with device tree, so use
list_add_tail instead of list_add to insert dsi devices.
Change-Id: I11d14d663c59c8ee0d1da280f42d9315e12c2a65
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
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Currently both sde_crtc_atomic_begin() and
sde_crtc_atomic_flush() add the CRTC state event
to the cached sde_crtc->event.
This has a potential NULL ptr issue in the
case of vblank event firing in between sde_crtc_atomic_begin() and
sde_crtc_atomic_flush() because the upstream DRM vblank API
send_vblank_event() doesn't consider the case when the VBLANK
interrupt could have already freed any pending vblank events.
Remove the caching from sde_crtc_atomic_begin() to avoid this
condition.
Also make sure that a page_flip event was indeed submitted before
signaling the complete_flip() by setting a PENDING_FLIP flag right
after HW flush.
Change-Id: Ib201d2851e57bf22ec1f00814fc2e4dd2f35bfa1
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
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If the panel is using bridge chips, such as ADV7533, it doesn't
have to set up backlight.
Change-Id: I014d697f81ecf1748ade2c40353ffdf9ff7c3669
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
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Panel pin control is not mandatory for all of the DSI panels.
If the panel is using bridge chips, such as ADV7533, it doesn't
have to configure the panel pin controls.
Change-Id: I48d862a9c67d52c0ed8c3c0309b0ff56d13e97f4
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
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This register is not accessible by CPU for certain TZ, trying to read it
will cause CPU hang.
Change-Id: Ica1b18db2c3cc2c9bacfdbd4c5eb1e2e172ade33
Signed-off-by: Kasin Li <donglil@codeaurora.org>
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GMEM IOVA range is intended to start from 0x100000. But currently
it is initialized with RANGE_MIN_LO:RANGE_MIN_LO. It makes GMEM
IOVA start from 0.
Change-Id: Ib3c9a86d0cd85794881d8708386b18d58bd8e58e
Signed-off-by: Kasin Li <donglil@codeaurora.org>
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vblank event is not enabled and vblank callback function
is not registered. As a result, vblank event could not be
received in user space. Get crtc vblank when start to wait
for commit done to fix this.
Change-Id: I5e348eaf689a0bb7384f8dcee787edcf44772eb6
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
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Conflicts:
arch/arm/boot/dts/qcom/msm8996pro.dtsi
arch/arm64/kernel/Makefile
drivers/leds/leds-qpnp-flash.c
sound/soc/msm/apq8096-auto.c
Change-Id: Idea5d05fec354b8f38ea70643decb03f7b80ddb7
Signed-off-by: Arun KS <arunks@codeaurora.org>
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Adding iommu fault handler callback to iommu driver, which will be
called when memory fault happens.
Change-Id: Ia2486fe167b889633ea4fb4c42601791efda133c
Signed-off-by: Yajun Li <yajunl@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
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Kernel DRM SDE driver doesn't know the alignment requirement from
user space, so it needs to be updated when pitches value when
they are different than fb value.
Change-Id: I392e247330980fcac87b6fbe49a289e0fc473d85
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
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When multiple bridge chips are connected to same interface, the
drm mode in the mode_set has combined timing parameters. For
each individual bridge chip, those timing parameters need to
be divided by panel count.
CRs-Fixed: 1085590
Change-Id: I9af0fa99ab6bcf9e09f4f7b372d53e6f1638e6d0
Signed-off-by: Jin Li <jinl@codeaurora.org>
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Display Bridgechip Abstration layer is a common framework to support
different kind of bridge chips with multi client accessing. This
change is to add a DRM bridge driver and hook it up with DBA
framework.
Change-Id: Ie225a7cdb55a4982199c1735c37986950c5fad05
Signed-off-by: Jin Li <jinl@codeaurora.org>
Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
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With the upcoming secure code the decision tree for configuration
(deciding where virtual addresses start/stop, etc) is going to get
a bit more complex. Head issues off at the pass by moving the
configuration into the GPU specific code. This does result in a
bit more code duplication but it is a lot cleaner.
Change-Id: Ic0dedbad57c11a4bba01825214d0a7853ab537ba
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add support for creating a secure domain in the GPU IOMMU. By default
the secure domain is bound to context bank name "gfx3d_secure".
Change-Id: Ic0dedbad19f69ec4175624dc80f2114bfda2e195
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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None of the existing iommu implementations use the names passed in
at attach time by the API. Save a bit of .data room by removing
the static string definitions and passing NULL to the attach function.
Change-Id: Ic0dedbada9561768b8d9716ea101619e6b549ea4
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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5XX targets that are using per-process pagetables will need to
keep the IOMMU clocks on the entire time because we don't know
exactly when the GPU might touch it. That said there are
occassional depencency issues if the clocks are enabled out
of order. To be certain we should enable the MMU clocks last
and disable them first. Add enable/disable hooks to the MMU
struct to do this cleanly from the GPU pm_resume / pm_suspend
paths.
Change-Id: Ic0dedbad8e2298e55c90b29eed657baa0933ddcf
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Very soon we will be adding support for secure domains and so a bit of
refactoring is needed the GPU IOMMU code:
* Add support for directly probing the context bank device at create
instead of at attach. This makes it a little bit easier to directly
associate a mmu device with a specific context bank.
* Specify the domain type at create time. Add a new domain type
MSM_DOMAIN_USER to associate the user domain with the gfx3d_user
context bank. Also add MSM_DOMAIN_DEFAULT with no context bank
for legacy devices (read MDP4) with only one context bank
to attach to the parent device. Adding a domain type saves us from
having to create N entry points for each domain type.
Note that dynamic domains stay with their own initalization function.
This is because dynamic domains are cloned from the parent domain
so the semantics are too different to try to smash into the generic
functions.
Change-Id: Ic0dedbad41692e776cddc72cda653ae637f9ec77
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Now that the SMMU/IOMMU differences have been resolved the only delta
between the SMMU and the IOMMU address space implementations is the
actual address space allocation which we can work around by assuming
the caller doesn't want address generation if they specify the same
start and end address (i.e. 0).
With that optimization we can get rid of the address space
sub functions and a bunch of otherwise duplicated code.
Change-Id: Ic0dedbaddef0fcd3a8f39e30f95c71245d84f111
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Finish consolidating the MMU map and unmap operations into a single
function. By passing in the meta token to map/unmap the specific
SMMU operations can make a local decision as to which function to
call.
Change-Id: Ic0dedbad52aac6ed1317411b2667755794d1818f
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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For all intents and purposes the mmu ->map function has used a
scatter gather list for some time. Drop the pretense and just
make both the SMMU and IOMMU flavors use the sg flavor of their
respective iommu API functions. As a result we can drop the
map_sg hooks in the SMMU driver and get rid of a considerable
amount of re-invented wheels in the IOMMU driver.
Change-Id: Ic0dedbadc4724c8ae389892fb85610435c5c08cf
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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