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* msm: kgsl: Standardize ringbuffers in the snapshotJordan Crouse2016-03-25
| | | | | | | | | | | | | | | | 'start' and 'stop' in the snapshot ringbuffer header are supposed to be the dword offset that the data starts and stops at respectively. For the current ringbuffer which is parsed 'start' and 'stop' are equal to the CP wptr but all other ringbuffers are just dumped from start to finish so 'start' and stop' should be 0 and KGSL_RB_DWORDS. And having said that, why are we bothering to make the current ringbuffer special anyway? In every case we are dumping the entire ringbuffer so we might as well dump it in order. While messing about in this code go a few more steps to make sure that we don't dump the same ringbuffer more than once. Change-Id: Ic0dedbada33adda660b7f0bf5eb165b0aa159004 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Add pm_qos_cpu_mask_latency to avoid L2PC on mask CPUDivya Ponnusamy2016-03-25
| | | | | | | | | Add a l2pc-cpu-mask-latency in device tree. This latency is used in kgsl_pwrctrl_update_l2pc() API to avoid L2PC on masked CPUs by giving reduced latency value. Change-Id: I0447977bce5ed5c09a863b03bb42b9428686a9f5 Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
* msm: kgsl: Fix VBIF out register settings for A306aHareesh Gundu2016-03-25
| | | | | | | Recommended value for A306a VBIF out registers is 0x10. Change-Id: I5ea3f4203b7649007fa62bdfe70a41c8d86432ef Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* msm: kgsl: Add secure memory flag in process mem fileHarshdeep Dhatt2016-03-25
| | | | | | | | | Secure memory will have 's' flag set in its flag fields. This is needed to track secure memory of a process. CRs-Fixed: 985767 Change-Id: I011dcc951b1db8adf763f85701aa869f6d4744d3 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* msm: kgsl: Unbind the kgsl-event workqueueJonathan Wicks2016-03-25
| | | | | | | | | Allow the kgsl-event workqueue to run on any available core. The other workqueues in KGSL were already unbound. CRs-Fixed: 985082 Change-Id: I7e843b57541b7ddcb53848078f73b05c88238711 Signed-off-by: Jonathan Wicks <jwicks@codeaurora.org>
* msm: kgsl: change ISENSE calibration handshake orderOleg Perelet2016-03-25
| | | | | | | | Force ISENSE calibration to stop before starting new calibration. CRs-Fixed: 973565 Change-Id: I86dcbaa7feaecd630a027c5aca41d62a5855efda Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* msm: kgsl: Invoke AGC handshake on A540Oleg Perelet2016-03-25
| | | | | | | | | Invoke AGC handshake on A540 even when LM is disabled, pass 0 for LM and pass HW patchid. CRs-Fixed: 973565 Change-Id: I62c32b55bf2e3a1ec498b1ec0a8bebf34ac803a9 Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* msm: kgsl: Streamline ringbuffer initializationCarter Cooper2016-03-25
| | | | | | | | Move device specific features to the device rather than trying to do them in the common initialization code. Change-Id: I812db29a2eae90ca532755c265aaa2e52db972d7 Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
* msm: kgsl: Disable guardpage for A5x and suppress pagefaultsSushmita Susheelendra2016-03-25
| | | | | | | | | | | | Disable the guardpage workaround for A5x and instead selectively suppress pagefaults. Suppress read pagefaults that are likely caused due to UCHE overfetches. For this, the fault address must be within the first 64 bytes of a page and the fault page must be preceded by a valid allocation. CRs-Fixed: 975293 Change-Id: I6a0995af3ab4129c6923726043c5f34c747641f9 Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
* msm: kgsl: Change the active context trackerPrakash Kamliya2016-03-25
| | | | | | | | | | | | | | | | | | | The active context tracker that we bolted on the side of the dispatcher was designed mainly to see if there was 1 OR more than 1 active context, not much more than that. Since it is apparent that we'll need to track up to 4 contexts and possibly more later the algorithm needs to change. The new algorithm puts all active contexts on a linked list - every time a context is used it is popped from the list and put on the tip with an updated time. To count the number of active contexts walk the list until you get a context with an active time older than you are looking for. You also can do other magic on the context, like see if it matches up with a given command queue. Change-Id: Ic0dedbad6be9fd1925121ee54e0000c42b089f44 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
* msm: kgsl: Change GPU RAC hardware clockgatingOleg Perelet2016-03-25
| | | | | | | | | On A5xx disable LRZ clockgating, by setting 0x0 for bits 18:16 of RBBM_CLOCK_CNTL2_RAC. CRs-Fixed: 964234 Change-Id: Icf858e3431e1c7f9943762067a74b1ce2af7ca6f Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* sync: oneshot_sync: Add oneshot_sync driverJordan Crouse2016-03-23
| | | | | | | Add the oneshot_sync driver as of msm-3.18 commit 7892968f (sync: oneshot_sync: Update oneshot_sync for new sync APIs). Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Use CONFIG_QCOM_KGSL_IOMMUJordan Crouse2016-03-23
| | | | | | | The rest of the driver started using CONFIG_QCOM_KGSL_IOMMU. The replayed MMU changes didn't get the memo. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Add NULL check for preemption_schedule callHareesh Gundu2016-03-23
| | | | | | | | | | preemption_schedule() is not implemented for A3xx targets. Invoking this function without NULL check result into crash in A3xx target. Fix this by adding a NULL check before invoking the preemption_schedule(). Change-Id: Ic600235f149cade57fedc5454bdc0f6794c67bd9 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* msm: kgsl: Initialize coresight at boot timeJordan Crouse2016-03-23
| | | | | | | | | Initialize coresight at boot time so that it is available to be configured before the first open of /dev/kgsl-3d0 to get GPU scan dumps during initial power up. Change-Id: Ic0dedbadbda251f12855895cc0aa53852f79a8b8 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Add quirk for masking out hang detect signalsShrenuj Bansal2016-03-23
| | | | | | | | | | Add a quirk to mask out the RB 1-3 activity signals in the hang detection logic. Set this quirk in the devicetree for 8996v2 and v3. CRs-Fixed: 978849 Change-Id: I63073b5973644453e775b41a9361de55d7933a07 Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
* msm: kgsl: Submit a set of critical packets right after ME initShrenuj Bansal2016-03-23
| | | | | | | | | | During the initialization sequence, submit a set of important packets to the GPU in order to pre-load the I-cache with the critical ucode instructions. CRs-Fixed: 978777 Change-Id: Ic6a17b24d8c3aa383af8e25cf9ef771459d65796 Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
* msm: kgsl: Enable guard page for GPUOBJ_IMPORT ioctlSushmita Susheelendra2016-03-23
| | | | | | | | | | The guard page should be enabled on the gpuobj import path to ensure allocations that are mapped are safe from the UCHE overfetch bug. CRs-Fixed: 975219 Change-Id: I42b7046ce3d314ec21c8fb03ef4fbbcdb094d8cf Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
* msm: kgsl: Use fault context to retrieve process informationSushmita Susheelendra2016-03-23
| | | | | | | | | | | | | Instead of looking up the process by pagetable base and name, use the fault context to extract the pid and other process specific information. This works for both the per-process and global pagetable configurations and also reduces some locking. This also reports the correct pid and task name in the global pagetable configuration. CRs-Fixed: 971753 Change-Id: I9c869527c3d1b2606f3d12234163935d6f5e43a9 Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org>
* msm: kgsl: Update RBBM_CLOCK_HYST_UCHE idle setting value for A50xHareesh Gundu2016-03-23
| | | | | | | | A50x GPU RBBM_CLOCK_HYST_UCHE idle setting recommended value is 0x00FFFFF4. Update accordingly to reflect the same. Change-Id: I95d79040c645e418ed26ea72ba84af2c2c7efce9 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* msm: kgsl: Specify the initial pwrlevel for each speed binSuman Tatiraju2016-03-23
| | | | | | | | | | Some platforms support multiple GPU clock plans based on the speed bin in the efuse. Specify the wake up frequency of each speed bin individually to wake the gpu at the correct powerlevel. CRs-Fixed: 967494 Change-Id: I9890b8a710d7055c30f9ae7612b092af8fa8a9f5 Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* msm: kgsl: Disable all HW clockgating during snapshotOleg Perelet2016-03-23
| | | | | | | | While producing snapshot disable all HWCG branches, not only top level. CRs-Fixed: 978122 Change-Id: I4b01224a0ba46c276115a284a0da6207c7968f72 Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* msm: kgsl: Add run time hardware clockgating controlOleg Perelet2016-03-23
| | | | | | | | Create sysfs nodes to enable/disable hardware clock gating. CRs-Fixed: 973565 Change-Id: If5f0215e0d7f3d7be1a0cf00fbd8789c6adf2f0f Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* msm: kgsl: Fix race condition in adreno_spin_idle()Suman Tatiraju2016-03-23
| | | | | | | | | | | adreno_spin_idle spins for a timeout checking for gpu to idle. Sometimes due to race conditions the timeout can occur before the loop is executed. Change the logic to a do-while loop and add an extra idle check after the timeout before returning failure. CRs-Fixed: 978122 Change-Id: Idb92a0180dd8cc3e662b1ccf44d69e4bbafb29f1 Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* msm: kgsl: Set the DDR high bank bit if specified in the device treeJordan Crouse2016-03-23
| | | | | | | | | | | | | | | | | | | | | On 5XX targets we need to program the bit of the highest DDR bank into a number of registers, one of which is protected which would cause problems if the user mode driver tried to write to it. Specify the high bank bit in the device tree files, set the problematic register in the kernel and then pass the value up to the user mode driver as a property and let them program the other registers. This makes the device tree the authoratative source of the high bit value which is exactly how it should be. If the value isn't specified by the device tree for whatever reason return an error for the property request - that will give the UMD a clue that the value wasn't specified and they should just set a default. CRs-Fixed: 970272 Change-Id: Ic0dedbad830321329b74da7fa3e172fdaf765c4d Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Add disable-busy-time-burst to disable ceiling thresholdDivya Ponnusamy2016-03-23
| | | | | | | | | | Add a devicetree property disable-busy-time-burst to disable ceiling threshold in the governor. The ceiling threshold cause busy time burst that switch power level for large frames based on busy time. Change-Id: I44f8a51e0aa49bb0b2210703f57874fd5f219c18 Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
* msm: kgsl: Enable GPU clock gating for MSM8996proSuman Tatiraju2016-03-23
| | | | | | | | | The current code enables GPU clock gating only for v2 and v3. Enable it for MSM8996pro also. CRs-Fixed: 974760 Change-Id: I2bcdbf73be080fba836c24616fc7959ad7c4c1e9 Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* msm: kgsl: Enable content protection for A506Rajesh Kemisetti2016-03-23
| | | | | | | | | | | Enable content protection for A506 from gpulist. Also, skip scm call to program CP secure ucode base registers since A506 supports retention for these registers. Change-Id: I48a0f04826430bfb927c755c176255be45199b26 Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
* msm: kgsl: Restrict secure contexts to ringbuffer level preemptionTarun Karra2016-03-23
| | | | | | | | | | | | | | | Preemption from secure to unsecure needs zap shader to be run to clear all secure content. CP does not know during preemption if it is switching between secure and unsecure contexts so restrict secure contexts to be preempted at ringbuffer level. At the end of each secure submission we switch back to unsecure mode and run the zap shader to clear secure contents. Ringbuffer level preemption ensures Zap shader is run before switching back to unsecure mode. CRs-Fixed: 974102 Change-Id: Iff11c1d5732d46fe5a1fbdbc7d162aaa1736741b Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
* msm: kgsl: Read speed bin information from device treeSuman Tatiraju2016-03-23
| | | | | | | | | | | | Speed bin information is sometimes written to efuses to specify a GPU frequency plan available on a platform. The current code only supports reading the efuses for msm8996v3. Hence specify it in the platform device tree node to support multiple platforms. CRs-Fixed: 967494 Change-Id: I5db4d5a35e2700250517ea6cac3d4d736936ce9f Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* msm: kgsl: Update clocks for GPU on MSMCOBALTOleg Perelet2016-03-23
| | | | | | | | | Add new clocks for MSMCOBALT. CRs-Fixed: 973565 Change-Id: I579875f34cff0ff9b714c0378084826aee0f893c Signed-off-by: George Shen <sqiao@codeaurora.org> Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* msm: kgsl: fix some uninitialized variablesHareesh Gundu2016-03-23
| | | | | | | | This change set default value for uninitialized variables, to address errors related to them. Change-Id: Idd306cafa4dfca322945ea8398e0c4d6c18d6ff6 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* msm: kgsl: Update snapshot ringbuffer parser for type7 ibsHarshdeep Dhatt2016-03-23
| | | | | | | | | Fix the wraparound logic when searching for ibs in the ringbuffer. The ibs can either be type3 or type7 packets so handle both cases. CRs-Fixed: 971163 Change-Id: I9bc4b4a72cddfe7f3d3892612c6e28861fdd0324 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* msm: kgsl: Enable GPU-BIMC clocks from kernel driverSunil Khatri2016-03-23
| | | | | | | | | | | | | | | Enable direct programming of GPU-BIMC interface clocks from kernel driver when moving in and out of TURBO. This is done only for targets with a device tree entry defined for GPU-BIMC interface. This is done because some targets do not support B/W requirement of GPU at TURBO, for such targets we need to program the GPU-BIMC interface clocks with TURBO values to meet the B/W goals. Change-Id: Ibe82db8718040513ae0d96366195d41001549189 Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
* msm: kgsl: Add a cmdbatch profiling flag to get time since bootJonathan Wicks2016-03-23
| | | | | | | | | | Add a new cmdbatch profiling flag that populates the seconds and nanosecond fields of the cmdbatch structure with the time since boot instead of the wall time. CRs-Fixed: 968114 Change-Id: I4e752d5237a74192b3ea9cc125c11bae574c1b36 Signed-off-by: Jonathan Wicks <jwicks@codeaurora.org>
* msm: kgsl: Avoid L2PC on masked CPUsPrakash Kamliya2016-03-23
| | | | | | | | | | | | | | | If any of the Graphics rendering threads are running on masked CPUs, avoid L2PC for some duration on that CPU. This reduces latency on CPU (latency mainly because of L2 cache flush) and helps on performance. This change uses pm_qos_update_request_timeout() API. Add l2pc-cpu-mask property in device tree to enable this. CRs-Fixed: 962598 Change-Id: If90090cd2c68ea7c07e269723931fef7201ef136 Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
* msm: kgsl: Use one define for max priority levelsCarter Cooper2016-03-23
| | | | | | | | | Don't redefine the macro since that could result in inconsistent data if one of them changes and the isn't updated. CRs-Fixed: 971159 Change-Id: I57ab3113fbdd82c70cba1c79f4b996cea09a8739 Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
* msm: kgsl: Move A3XX specific ringbuffer init out of common initCarter Cooper2016-03-23
| | | | | | | | | CP_QUEUE_THRESHOLDS is only used in A3XX. Move the register setting out of common ringbuffer initialization and into A3XX specific region. CRs-Fixed: 971153 Change-Id: I05ef504a802534f1582e62085c5b12b20ac57209 Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
* msm: kgsl: Rate limit all logs from the interrupt handlerCarter Cooper2016-03-23
| | | | | | | | | Ensure that all the logs that can be triggered from the interrupt handler are rate limited. CRs-Fixed: 971145 Change-Id: I9fe4a6b28be0dc6299467fb8402bef3694aeac76 Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
* msm: kgsl: Correct protected mode range for 5XX UCHE registersJordan Crouse2016-03-23
| | | | | | | | | | | | | | The start offset for protected mode ranges needs to be aligned with the block size. 0xE87 is not aligned with 16 (1 << 4). The hardware assumes alignment internally so it turns out that 0xE80 - 0xE8F is the range that gets protected. Luckily for us that this is the range we want protected so nothing critical has been left unprotected, but the software should reflect the hardware to prevent incorrect assumptions. CRs-Fixed: 968713 Change-Id: Ic0dedbad6ec7be5cc473afbbc52655663ea65159 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Tweek LLM sleep/wake algorithmJordan Crouse2016-03-23
| | | | | | | | | | | | | | In the LLM sleep sequence, the IDLE_FULL_LM bit (0) needs to be set to force the children to sleep. Also, after the first child is put to sleep, we need to wait for the idle acknowledgment before taking the next child down. In the wake sequence, poll until WAKEUP_ACK is 1 *and* IDLE_FULL_ACK is 0 to ensure that the wake sequence was successful. CRs-Fixed: 970270 Change-Id: Ic0dedbadfca1e0882d84965d634166f921f1e630 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Refactor MMU/IOMMU supportJordan Crouse2016-03-23
| | | | | | | | | | | | | | | | | | | | | The current MMU code assumes a binary state - either there is a IOMMU or there isn't. This precludes other memory models and makes for a lot of inherent IOMMU knowledge in the generic MMU code and the rest of the driver. Reorganize and cleanup the MMU and IOMMU code: * Add a Kconfig boolean dependent on ARM and/or MSM SMMU support. * Make "nommu" mode an actual MMU subtype and figure out available MMU subtypes at probe time. * Move IOMMU device tree parsing to the IOMMU code. * Move the MMU subtype private structures into struct kgsl_mmu. * Move adreno_iommu specific functions out of other generic adreno code. * Move A4XX specific preemption code out of the ringbuffer code. CRs-Fixed: 970264 Change-Id: Ic0dedbad1293a1d129b7c4ed1105d684ca84d97f Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Declare platform_bus_type as secure for ARM driverRajesh Kemisetti2016-03-23
| | | | | | | | | | | | | ARM driver supports only one bus for all context banks. In some cases, hypervisor may not be available and GPU SMMU uses ARM driver. This will make all context banks are on non secure bus and kgsl_mmu_bus_secured() returns -EPERM. Make platform_bus_type as secure for ARM driver. Change-Id: I11a637ca2b1ef29cc42c9811cad009312a2879cd Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
* msm: kgsl: Move all platform drivers to the same module init functionJordan Crouse2016-03-23
| | | | | | | | | There can only be one module_init() function per module. Move all three driver register calls into the same initialization function. The ordering should still work correctly. Change-Id: Ic0dedbadf7c69221a836ba3bbba362d0660f1f0f Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Add and use KGSL_DEVICE macroJordan Crouse2016-03-23
| | | | | | | | | | Add a helper macro to convert an adreno_device pointer to a struct kgsl_device pointer. This is mostly syntatic sugar but it makes the code a bit cleaner and it abstracts a bit of the ugliness away. Change-Id: Ic0dedbadd97bda3316a58514a5a64757bd4154c7 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Add KGSL_RB_DEVICE macroJordan Crouse2016-03-23
| | | | | | | | | | | | | | The ringbuffer structures are static members of struct adreno_device which means that they are permanently associated with a specific adreno device and by extension a struct kgsl_device too. The upshot is that we can use macro math to derive the adreno device from a ringbuffer pointer and get rid of the device shortcut in the ringbuffer struct. This also gives us a chance to clean up how functions use the ringbuffer and adreno_device structs to limit unnessesary dereferencing. Change-Id: Ic0dedbad909ef71e99cd3319713cee38fb1700f0 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* msm: kgsl: Don't overwrite the VBIF XIN offset for A3xxHareesh Gundu2016-03-23
| | | | | | | | | | Currently VBIF XIN register offset is been overwritten by the AXI offset. This will cause VBIF XIN halt time out in VBIF clear transaction path. Fix this by using the proper VBIF XIN offset for A3xx targets. Change-Id: Iac20528cb105904e46e012d67287dd736fa11f70 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
* msm: kgsl: Properly enable bit 5 in CP_INIT maskShrenuj Bansal2016-03-23
| | | | | | | | Use bit 5 in the CP_INIT_MASK to properly enable/disable microcode workarounds. Change-Id: I9f43c8c988c3179b3de2cce071339bc565b4a00d Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
* msm: kgsl: Fix the snapshot mempool size calculationHarshdeep Dhatt2016-03-23
| | | | | | | | | | The snapshot mempool size takes into account the memory required for section headers. It was being calculated based on old header structure. Update that to avoid corruption/ buffer overflow of the mempool memory. Change-Id: I07274934e4c0dced707e03be3e31b2459e00d706 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* msm: kgsl: Add A5x support for CONTEXT_SWITCH_YIELD preemptionJonathan Wicks2016-03-23
| | | | | | | Enable CP to process yield packets placed in the IB2s. Change-Id: I2fadfb108a2dc42f574b3f6ed2e667baddb7889c Signed-off-by: Jonathan Wicks <jwicks@codeaurora.org>
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