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| * | | | | msm: kgsl: Add trace for throttling countersOleg Perelet2016-09-07
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trace active and idle counters and DCVS adjustement. CRs-Fixed: 1055047 Change-Id: I60d30192c55efd8b0d5dc455343464d29648281e Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | | | | Merge "msm: kgsl: Change %p to %pK in debug messages"Linux Build Service Account2016-08-30
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| * | | | msm: kgsl: Change %p to %pK in debug messagesDivya Ponnusamy2016-08-24
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The format specifier %p can leak kernel addresses while not valuing the kptr_restrict system settings. Use %pK instead of %p, which evaluates whether kptr_restrict is set. Change-Id: I0778e43e0a03852ca2944377256a7b401586a747 Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
* | | | Merge "msm: kgsl: Change sequencing for GPU hardware clock gating"Linux Build Service Account2016-08-26
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| * | | | msm: kgsl: Change sequencing for GPU hardware clock gatingOleg Perelet2016-08-24
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable GPU SP clock before programing hardware clock gating registers. CRs-Fixed: 1056488 Change-Id: I2c91e8ae6a30facefd5dd3d4a4e4c33ffc792fe1 Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | | | msm: kgsl: remove un-used GPU power statesGeorge Shen2016-08-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DEEP-NAP and SLEEP states are not used in targets of previous two generations. They are neither saving GPU power, nor saving system power. Remove to reduce maintenance overhead. CRs-Fixed: 1053516 Change-Id: If2fc2701548f90bb7ea9559a87752e13a7b0f736 Signed-off-by: George Shen <sqiao@codeaurora.org>
* | | | msm: kgsl: remove GFX retention supportGeorge Shen2016-08-22
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GFX retention mode does not save GFX rail power. The feature increased MX rail power. Fixing the problem requires more overhead than removing it. The feature has never been enabled in any targets. So remove the feature. CRs-Fixed: 1053516 Change-Id: I5f118138eca307f7cc16405ff9c8897ecd510c12 Signed-off-by: George Shen <sqiao@codeaurora.org>
* | | Merge "msm: kgsl: Fix sequencing for GPMU performace counters allocation"Linux Build Service Account2016-08-18
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| * | | msm: kgsl: Fix sequencing for GPMU performace counters allocationOleg Perelet2016-08-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Operation needs to be read/modify/write. It was write only which zeroed out bits outside of requested region. CRs-Fixed: 1055047 Change-Id: I2e010a99ed5961cd501e1eae913c73b3dbee4789 Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | | | Merge "msm: kgsl: Add sparse memory support"Linux Build Service Account2016-08-16
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| * | | | msm: kgsl: Add sparse memory supportCarter Cooper2016-08-15
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to allocate/reserve a virtual address range without physically backing. Add support to allocate physically backing memory without assigning it a virtual address. Add support to unite the two forementioned allocations together. Add support to divorce them from one another. Add support to let their kids do cache operations as they see fit. Create a 'dummy' page that is used to back virtual allocations that are not yet backed by physical memory. CRs-Fixed: 1046456 Change-Id: Ifaa687b036eeab22ab4cf0238abdfbe7b2311ed3 Signed-off-by: Carter Cooper <ccooper@codeaurora.org> Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
* | | | Merge "msm: kgsl: Fix the ringbuffer wrap around logic"Linux Build Service Account2016-08-16
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| * | | msm: kgsl: Fix the ringbuffer wrap around logicHarshdeep Dhatt2016-08-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, if read pointer is behind write pointer and there is not enough space toward the end of the ringbuffer for new commands, then write pointer is being set to 0. This is problematic, because it leads to the overwriting of unexecuted commands with new commands at the start of the ringbuffer. So, instead of setting the write pointer to 0, look for space from the start of the ringbuffer up till the read pointer and if there is room, update the write pointer accordingly. CRs-Fixed: 1028465 Change-Id: I1cbdbf139b14988513a22030aa2be4a99a221880 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* | | | Merge "msm: kgsl: Disable RB sampler data path optimization"Linux Build Service Account2016-08-16
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| * | | msm: kgsl: Disable RB sampler data path optimizationSunil Khatri2016-08-10
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable RB sampler data path DP2 clock gating optimization for 1-SP A5XX GPU's. Optimization leads to precision difference during interpolation which cause rendering difference between Binning and Direct rendering mode. CRs-Fixed: 1040638 Change-Id: I40d1ce2f5db0ed75453feda5c31152f8201b8697 Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
* | | Merge "msm: kgsl: update GPU busy statistics"Linux Build Service Account2016-08-13
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| * | msm: kgsl: update GPU busy statisticsOleg Perelet2016-08-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case of GPU idle (NAP), schedule DCVS call to obtain updated GPU load for correct GPU frequency scaling. Change-Id: Ifcf05ffde0a054839e51d3f8173b8449fe177aa0 CRs-Fixed: 1050000 Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | | Merge "msm: kgsl: Allow 0 as a valid ion file descriptor"Linux Build Service Account2016-08-07
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| * | | msm: kgsl: Allow 0 as a valid ion file descriptorCarter Cooper2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Treat 0 as a valid fd instead of treating it as an error. CRs-Fixed: 1030098 Change-Id: I4a1b14fcbca617bc2a43b30af7256edc3920f04c Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
| * | | msm: kgsl: Remove event workerJordan Crouse2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Scheduling issues were occurring with the GPU event worker after b7be807 (msm: kgsl: Unbind the kgsl-event workqueue) was merged. In certain conditions, it seems that the kgsl-event workqueue was conflicting with the KGSL worker and slowing it down. It turns out that everywhere we schedule the event worker and the dispatcher worker at the same time. Since the worker is singlethread, the event worker and the dispatcher run synchronously anyway, so it makes sense to run the event processor from within the dispatcher and save the extra schedule. CRs-Fixed: 1043509 Change-Id: Ic0dedbad67eb04d41afb6add4477f146dfff9784 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | Merge "msm: kgsl: Make VBIF register dump more generic"Linux Build Service Account2016-08-07
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| * | msm: kgsl: Make VBIF register dump more genericHareesh Gundu2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make VBIF register dump more generic to avoid adding new entry for every VBIF revision. There will not be any change in register mapping and address for new VBIF revision. AHB reads are permitted throughout entire VBIF range. For all unoccupied registers read values driven to 0 by HW but should not be relied upon. CRs-Fixed: 1021711 Change-Id: I5aada474389e9189abcd38f1bc4854ada91dea87 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
| * | msm: kgsl: Read HLSQ SP/TP registers through debug apertureHarshdeep Dhatt2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use crash dumper to read HLSQ SP/TP registers through debug ahb aperture during device snapshot. CRs-Fixed: 1019957 Change-Id: I3b18fd0d1eab28b6b3e5d314539cfbc15210f675 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
| * | msm: kgsl: Don't read CP_RB_RPTR register without clockHareesh Gundu2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For A3xx we get GPU read pointer from the CP_RB_RPTR register instead of rptr scratch memory address. In retire_cmdbatch() and _retier_maraker() GPU clock will be off, so avoid reading CP_RB_RPTR register. Also hold device mutex in sendcmd() to access GPU registers. CRs-Fixed: 1024730 Change-Id: Ifa5e9d3f892301685cb48a227ce4967d895499b1 Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
| * | msm: kgsl: Correct dma_buf_get function return value checkDeepak Kumar2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check the return value of dma_buf_get function using IS_ERR_OR_NULL as dma_buf_get function can return ERR_PTR(-EINVAL) which won't be caught by simple NULL check. This will avoid kernel panic due to invalid pointer access. CRs-Fixed: 1008517 Change-Id: I11ebf618edd25a251d3fb8bb7fbbb886e10d788f Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
| * | msm: kgsl: Correct the size of SDS in snapshotHarshdeep Dhatt2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | Dump 256 instead of 128 dwords of SDS as DRAW_STATE_ADDR is actually 8 bits wide [7:0] and not 7 bits wide [6:0]. CRs-Fixed: 1023608 Change-Id: I8dcb07bf0a3b9e91b6ec7396d89239fdbd548ac0 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
| * | msm: kgsl: Add vbif version for A540Harshdeep Dhatt2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | A540 has a new vbif version. Add it so that we can dump vbif registers in snapshot for A540. CRs-Fixed: 1024192 Change-Id: Id9323fa98951e2755fcc6903f84a450bc7ab6169 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
| * | msm: kgsl: Add A5XX_UCHE_DBG_ECO_CNTL_2 to snapshotHarshdeep Dhatt2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | Add the register to be dumped in a5xx snapshot. CRs-Fixed: 1024179 Change-Id: I316029caa10047828375ae0eab1f1d35d30fccb6 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
| * | msm: kgsl: Reduce CP preemption record sizeHareesh Gundu2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | A5xx GPUs currently don't need more than 64KB for CP preemption record. CRs-Fixed: 1019529 Change-Id: I3df22b7b282fb8ff3269f01b2b258318fc83cbcb Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
| * | msm: kgsl: Add array of page pointers to memdescHarshdeep Dhatt2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is done to improve the kgsl vmfault routine. Currently, it traverses the sglist to find the faulted page, which takes linear time. By having an array of all the page pointers, this operation will be completed in constant time. Also, allocate sgt only for mapping this memory to the GPU. Since this optimization is not needed for secure/global or imported memory, we will not keep this array but keep the sgt instead. CRs-Fixed: 1006012 Change-Id: I221fce9082da0bdd59842455221b896a33a6ce42 Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
| * | msm: kgsl: Don't allocate memory for microcode if it is already allocatedDeepak Kumar2016-08-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a check to avoid allocating memory for loading microcode in case it is already allocated. This avoids memory allocation failure for microcode during multiple tries by userspace to open the kgsl device in case of errors. CRs-Fixed: 1043490 Change-Id: I018ebdb0dab1fc13af8d85a273c1c8b477fa1e26 Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
| * | msm: kgsl: track GPU active time per frequencyGeorge Shen2016-08-03
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Tracks GPU active time per frequency for GPU workload profiling. The data will be output in /sys/class/kgsl/kgsl-3d0/gpu_clock_stats with one u64 value in microseconds per clock level. For example: cat /sys/class/kgsl/kgsl-3d0/gpu_clock_stats 39392 29292 929292 929292 4040404 CRs-Fixed: 1011462 Change-Id: I5f2caa8b38d99ffd23f03c1dfed1efda273fc2fb Signed-off-by: George Shen <sqiao@codeaurora.org>
* | Merge "msm: kgsl: Allocate global buffers through paged memory"Linux Build Service Account2016-08-04
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| * msm: kgsl: Allocate global buffers through paged memoryHarshdeep Dhatt2016-07-26
| | | | | | | | | | | | | | | | | | | | The global buffers are allocated through cma, which can be very limited on some targets. Add a flag to allocate a global buffer through our page allocator. CRs-Fixed: 1024295 Change-Id: Ie796b03ce152774535f593acdf00e900109d303a Signed-off-by: Harshdeep Dhatt <hdhatt@codeaurora.org>
* | Merge "msm: kgsl: Add 5usec delay for idle check on A540"Linux Build Service Account2016-08-01
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| * | msm: kgsl: Add 5usec delay for idle check on A540Oleg Perelet2016-07-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CRC idle throttling effectively slows down GPU 10x, internal GPU idle hysteresis does not account for this and may take up to 3usec to expire. Make host delay. CRs-Fixed: 1028293 Change-Id: I0a80e49a3fea6e0e8d9e8b82847188b0a4452943 Signed-off-by: Oleg Perelet <operelet@codeaurora.org>
* | | Merge "msm: kgsl: Map GPU QDSS STM through GPU IOMMU"Linux Build Service Account2016-07-27
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| * | msm: kgsl: Map GPU QDSS STM through GPU IOMMUJonathan Wicks2016-07-19
| |/ | | | | | | | | | | | | | | | | | | | | Map the GPU QDSS STM area as a global into the GPU IOMMU so that GPU traces can be routed to QDSS. Enable the gpuaddr and size of the area to be queried from userspace. CRs-Fixed: 1031648 Change-Id: I2e32522a42508a6bee088c95dc56a13935dd691c Signed-off-by: Jonathan Wicks <jwicks@codeaurora.org>
* | msm: kgsl: Keep the active draw context until it is switched outJordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of trying to make a decision to switch out the active draw context for NULL at detach time leave the reference count for it until the next context switch or until the next slumber whichever comes first. This avoids races with the preemption code and ensures a smooth transition. A side effect is that we were depending heavily on the context detach to reset the ringbuffer to the default at power down and we didn't touch it on power up (though we did on soft reset and wake from slumber. Curious). Obviously if we are no longer switching we will need to force the default pagetable during start but it seems to me like this would be the right thing to do even if we were still switching out. CRs-Fixed: 1009124 Change-Id: Ic0dedbadff8df192096292b221130c8ef5b31e12 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Force all command level context switches to the GPUJordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | | | Force any command triggered context switch to the GPU - it should be on the GPU anyway, but we were already passing a flags parameter (unused) so this is a good chance to force the issue and make sure that the cpu path decision isn't in play here. CRs-Fixed: 1009124 Change-Id: Ic0dedbadb277a6498d0840b45c90e1265e2f354a Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Record the ringbuffer start of pipeline timestampJordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | | | | | We are only writing the ringbuffer start of pipeline timestamp for internal commands that do not have a draw context associated which happen rarely (if ever). We should be recording the timestamp for *ALL* commands so when something goes wrong we can get a fuller idea of the timestamp picture for each ringbuffer. CRs-Fixed: 1009134 Change-Id: Ic0dedbad6d99130e31cd8a06dfe025610e9157a8 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Relax timestamp comparisons for processing eventsJordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When processing an event group we check the previously processed timestamp to avoid going through the loop if we don't need to. We use timestamp_cmp() to check the timestamp. In situations where the retired timestamp has advanced by more than 0x80000000 since the last time we checked the timestamp, timestamp_cmp() will return -1 as it thinks that the new timestamp is older than the processed timestamp. This can happen with certain tests and scheduling hiccups. The event processor can be much less restrictive - all we really care about is that the retired timestamp didn't slip backwards by accident (highly unlikely). So just check that the last proccessed timestamp is not equal to the retired timestamp and if the retired timestamp has already rolled, that the delta is outside of the 0x8000000 window. CRs-Fixed: 1009149 Change-Id: Ic0dedbad641bfa3fd6cbc1c91a37fb0e37f72bae Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Remove unneeded error message in kgsl_iommu.cJordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | | | iommu_attach_device() should return a log message for every possible error and we don't need to double up the pain especially for situations when we run out of available domains and start getting a storm of ENOSPC errors back. CRs-Fixed: 1009158 Change-Id: Ic0dedbad7416abb23c769a4d3be9ebd0ca04810c Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Do INIT_WORK() just before queueing a deferred mem entryJordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | | | | | | | gpuobj_free_on_fence() is used infrequently enough that it doesn't make sense to do INIT_WORK() when the memory object is created, especially if debug objects are enabled because INIT_WORK() will go off and do a bunch of accounting that we don't need. Do the INIT_WORK() just before queueing in those rare cases that this actually happens. CRs-Fixed: 1009183 Change-Id: Ic0dedbad1015883788e12815806e3249a1e09b21 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Remove idle wait in kgsl_iommu_set_pf_policy()Jordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | We don't need to wait for idle before changing the pagefault policy on the IOMMU which is a good thing because on a busy system we may never hit idle. CRs-Fixed: 1009187 Change-Id: Ic0dedbadb8f6122e32a0a34a65c54a7bca2a523c Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Allow a draw context to skip snapshotJordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some test applications intentionally generate a GPU fault for various reasons. Because a GPU fault generates a snapshot and snapshots are persistent until they are pulled, running the test application may take up the snapshot slot and prevent a real fault from being captured and debugged. This flag allows the draw context to intentionally avoid generating a snapshot. CRs-Fixed: 1009190 Change-Id: Ic0dedbad8476c308a13572d999540b243d97eabc Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Program the secvid registers in the soft reset pathJordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | The secure buffer registers were not being programmed in the soft reset path which was causing a failure for the critical packets workaround and forcing a hard reset. CRs-Fixed: 1009194 Change-Id: Ic0dedbad998767a1ffdfe265e52fae7baa18d203 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Implement fast preemption for 5XXJordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | | | Allow 5XX targets to preempt quickly from an atomic context. In particular this allows quicker transition from a high priority ringbuffer to a lower one without having to wait for the worker to schedule. CRs-Fixed: 1009124 Change-Id: Ic0dedbad01a31a5da2954b097cb6fa937d45ef5c Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Preemption cleanupsJordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | Remove some unused gpudev hooks and further segment the A4XX and A5XX specific code into their respective areas. Remove some bits that are only applicable to 4XX from the 5XX side. CRs-Fixed: 1009124 Change-Id: Ic0dedbadc324b979583d7a3998195bf15ac537f6 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | msm: kgsl: Leave the MMU clocks on with the rest of the GPUJordan Crouse2016-07-20
| | | | | | | | | | | | | | | | | | | | | | It is no longer power efficient to independently enable and disable the MMU clocks. We can safely enable and disable them with the rest of the GPU clocks and take back the infrastructure needed to handle the clocks. CRs-Fixed: 1009124 Change-Id: Ic0dedbadc48095eada9c5fce6004475a2cb0f0a9 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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