| Commit message (Collapse) | Author | Age |
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Robust context attempts to perform a rendering that takes too long
whether due to an infinite loop in a shader or even just a rendering
operation that takes too long on the given hardware. This type of
attempts can result into GPU faults. Robust context expect driver
to replay IB instead skip IB and if it fails on replay context has
to be invalidated.
KGSL_CONTEXT_INVALIDATE_ON_FAULT flag allows draw context to execute
only replay policy on GPU fault recovery instead of going to default
recovery policy. User space has to set this flag during the context
creation.
Change-Id: If42dc5afc7d5ed1226b73ae5abfa2648d7acf2c3
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
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Hold the context lock before updating the context id in
param->drawctxt_id to avoid race condition between context
creation and context destroy.
Change-Id: Ic26d3e5b68078c02d15c38080b1a262ea4b1f7fe
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
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When allocating userspace memory keep reference to memory
allocation till it is completely initialized and info is sent back
to userspace.
Change-Id: Id72c82bf98c094ecbd4722813c732a998dcbb188
Signed-off-by: Tarun Karra <tkarra@codeaurora.org>
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
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Check for legacy PM4 commands instead of adreno version to calculate
ringbuffer space for PM4 commands that write to memory.
Change-Id: I5d1d4cfbc70bc73ddee9ee752de24aae154a04dc
Signed-off-by: Lynus Vaz <lvaz@codeaurora.org>
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For dual channel DDR, IB vote from client is half of actual
IB vote as IB vote calculation on client side doesn't consider
number of DDR channels. ICB driver takes care of multiplying
the client IB vote with number of DDR channels.
This change removes the AB capping check to avoid the scenarios
where AB vote > actual IB vote/2 but gets capped to actual
IB vote/2 because client side IB vote is half of actual IB vote.
Removal of this check will not impact single channel DDR targets
because of the way AB value is calculated. In case of honest BW
voting, AB will always be less than IB as AB calculation doesn't
consider RAM wait value. In case of unhonest vote, AB value is
always caluclated as some percentage of IB vote and this percentage
value is always <=100%.
Change-Id: Icdca6118f6605665979a1bead35ba3ef631d50e8
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
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Memory retention is needed only for NAP state but not for SLUMBER state.
Disables memory retention for core clock before entering SLUMBER to save
power.
Change-Id: I64a5ecec6fc90d662da8d9d793860e56b0c6473f
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
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Map the GPU QTimer area as a global into the GPU
IOMMU so that the GPU can access the QTimer.
Change-Id: If50bd36681123adde7e3a37644c41316f101154c
Signed-off-by: Jonathan Wicks <jwicks@codeaurora.org>
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Following changes been made to improve soft fault detection,
which will fix un clocked register access in dispatcher_do_fault()
and incorrect declaration of GPU soft fault.
i) Stop fault timer before entering to NAP state
ii) Don’t start fault timer if the dispatcher inflight count is zero
iii) Add ringbuffer empty check in _isidle()
iv) Add device state check in dispatcher_do_fault()
CRs-Fixed: 2012731
Change-Id: I5ce498029f389eeeb428b4ac7fb07afd84d5764c
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
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Disable GPU LRZ clock gating for A512 to avoid HW quirk.
Change-Id: I168d678ab2e08c6e2f16a63d6bc71e7f383f8f1b
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
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To handle Cx peak current limit on SDM660, GPU needs
to call Cx ipeak driver APIs when it switches between
threshold points.
Cx ipeak driver will throttle cDSP frequency if all
the clients are running at their respective threshold
frequencies to limit Cx peak current.
Change-Id: I5ffcf1a42523072d2b8b7bc0022eb3cc067acbb9
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
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Remove the kgsl device-specific debugfs files in the device removal
sequence, and also if probe fails.
Change-Id: I4d5e9ec33a887f29c14bac513c4faf75266e990b
Signed-off-by: Lynus Vaz <lvaz@codeaurora.org>
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A508 GPU has multiple frequency plan, for loading a
specific frequency plan add speed bin read capability
for A508 GPU.
Change-Id: I32a030bec438edc74f1e78bfb2ea86e7a3f60dab
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
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info."
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Using per uts namespace utsname() for kernel build information section
in snapshot dump was causing a kernel panic because it is accessing a
NULL nsproxy pointer. nsproxy was null because corresponding user task
got SIGKILL which triggered call to free_nsproxy. The patch fixes the
issue by using the global init_utsname() which is always valid.
Change-Id: I13b1b07557794a7fcedf0c9e6acfd3406fbb8989
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
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A context may be detached without submitting any commands
to GPU ringbuffer. This may cause us to wait on a timestamp
that will never be retired. So return immediately from
adreno_drawctxt_wait_rb() if context has not submitted any
commands to GPU ringbuffer.
Change-Id: If8b3f8df92ec9b54a1a83d2f6704d4d15eb1b979
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
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_get_svm_area can fail to find available address range
from mmap_base which was adjusted by random factor.
By logging mmap_base value will help to identify
any issue with the VA randomization.
Change-Id: Ibdc3fac975adde02c30aa253b53d6533ee558161
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
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Sometimes ringbuffer timer is not getting updated due to
race with the preemption. This can cause dispatcher to
detect false timeout gpu faults. Remove preempt state
check in adreno_dispatch_process_drawqueue(), which will
allow to update ringbuffer timeout value irrespective of
the preemption state.
If the preemption completes successfully, preemption logic
updates timer for new_rb. We don’t need to care if it is
not updated for prev_rb. If preemption in-progress timer
will be updated for cur_rb in adreno_dispatch_process_drawqueue().
In both cases we are taking care to update ringbuffer timer.
Hence we don’t need to check preemption state.
CRs-Fixed: 1095344
Change-Id: I0e0ec655e2262c4f499748ce35a8d710ed15b5e3
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
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There could be possibility of integer overflow on adding
offset with size and result into a value smaller than
memdesc size.
CRs-Fixed: 1109776
Change-Id: I3746f34c9fb8ada28a9b6ed438ca8c296b69e752
Signed-off-by: Sudeep Yedalapure <sudeepy@codeaurora.org>
Signed-off-by: Abhilash Kumar <krabhi@codeaurora.org>
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Add new GPU ID: A508 and corresponding VBIF and initial
settings on SDM630.
Change-Id: If1cd782beb50098a69a9d05acb083ef4b0465766
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
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in kgsl_pwrscale_init(), add missing NULL check for kgsl_midframe
to avoid further accessing, in case if memory is not available.
Change-Id: If6a4e59d4675fe67aefc63d7f8251f4d28ddeec5
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
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Enable retention of memory and periphery logics for
GPU core clock. If the setting is not done then GPU
might get stale data while switching from NAP to
ACTIVE and which leads to page faults or hangs.
Clock settings need to be handled by client drivers only
and hence do it in KGSL driver.
Change-Id: Iea3fd720e2a0eda9f6ee719177a8898bc2bd75e4
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
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A512 GPU has multiple frequency plan, for loading a
specific frequency plan add speed bin read capability
for A512 GPU.
Change-Id: Iff207c31bc50748a6caaa405608252b78133fd83
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
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During a pagefault we print trace with the fault
information which gets delayed by unacceptable
time. It happens due to the the code that searches the
faulty address in the recently freed addresses for a matching
entry.
Moving it to new position wont have any impact on debugging
instead trace is dumped without any delay.
Change-Id: I11487798b60742096e06605cf3046b4cfc8cc057
Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
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Current irq handler clears the pending interrupt bits in interrupt
status register before serving the interrupts. This leads to a race
condition with the idle check which checks the interrupt status
register to determine whether any interrupt is pending or not. As
the interrupt status register is already cleared, idle check goes
ahead and switch off the GPU clocks even when irq is yet to be served
causing NOC errors.
This change refcounts each irq handler call and uses this reference
count to determine if any irq is still pending or not along with
interrupt status register to avoid this race condition.
Change-Id: I030d52c52055f836ea4c7519ce2d8db94a2a09a0
Signed-off-by: Deepak Kumar <dkumar@codeaurora.org>
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If there is IB2 address overlap with IB object list,
driver is dumping pending dwords size of active IB2
data into snapshot. Fix this by updating IB2 size
while active IB1 parsing instead later point.
Change-Id: Ibb12a876ebf73846424232ef28e00d3dc9f9be59
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
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Some targets do not have GPMU block in GPU and register read
or write into those registers is not valid.
To prevent this, check GPMU presence and then proceed.
Change-Id: I0992125af8cda4b8235aedb64f6ef8868ae95f20
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
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During GPU snapshot dump path, a5xx_snapshot() tries to
capture preemption record without really checking on the
availability of preemption feature.
Add a check for preemption feature and then proceed.
Change-Id: I6ee23a1d8006ba18a25fb341bb88d8944ff054b7
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
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Try to allocate pages from lower order mempools incase
if requested memory size order does not match with the
available mempools.
Change-Id: Idbe4dae3b8bb2a3165199b6959ad4fbf36559964
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
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If power-related initialization fails during device probe, clean up
the kgsl structure members. This is useful if the device probe is
retried later.
Change-Id: I75aeb199da685bb5055ba5a8a0bb552656951674
Signed-off-by: Lynus Vaz <lvaz@codeaurora.org>
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Enable HW clockgating and preemption for A512 GPU to save power
and for better context switching.
Also update proper size for CP MERCIU size.
Change-Id: If3e5101c2695b1f06d650d320bc8d3bebac29f6f
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
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Return error instead of BUG_ON on map global failure.
This will avoid crashing the entire system.
CRs-Fixed: 1106621
Change-Id: I693dc196bb7a2e01f6a033f5fbbf7b454108108d
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>
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This is needed to clear out the internal memories of
GPU while moving from secure to unsecure mode.
Change-Id: I9ef4848212246a2ed45395ef97c7f755784cb635
Signed-off-by: Rajesh Kemisetti <rajeshk@codeaurora.org>
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