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| | * | | | | | | | drm/msm/mdp5: fix for crash in disable pathRob Clark2015-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Seems like disable can race with complete_flip() in process of disabling a crtc, leading to: [ 49.065364] Call trace: [ 49.071441] [<ffffffc00041d5a0>] mdp5_ctl_blend+0x20/0x1c0 [ 49.073788] [<ffffffc00041ebcc>] mdp5_crtc_disable+0x3c/0xa8 [ 49.079348] [<ffffffc0003e7854>] disable_outputs.isra.4+0x11c/0x220 [ 49.085164] [<ffffffc0003e7afc>] drm_atomic_helper_commit_modeset_disables+0x14/0x38 [ 49.091155] [<ffffffc000425c80>] complete_commit+0x40/0xb8 [ 49.099136] [<ffffffc0004260ac>] msm_atomic_commit+0x364/0x398 [ 49.104430] [<ffffffc00040a614>] drm_atomic_commit+0x3c/0x70 [ 49.110249] [<ffffffc0003e67b8>] drm_atomic_helper_set_config+0x1b0/0x3e0 [ 49.116065] [<ffffffc0003f99bc>] drm_mode_set_config_internal+0x64/0xf8 [ 49.122746] [<ffffffc0003fa624>] drm_framebuffer_remove+0xe4/0x128 [ 49.129171] [<ffffffc0003feaf8>] drm_mode_rmfb+0xc0/0x100 [ 49.135420] [<ffffffc0003efba8>] drm_ioctl+0x258/0x4d0 [ 49.140889] [<ffffffc0001b0388>] do_vfs_ioctl+0x338/0x5d0 [ 49.145921] [<ffffffc0001b06a8>] SyS_ioctl+0x88/0xa0 It makes no sense to free the ctl without disabling all stages, so lets just move them together to avoid the crash. Signed-off-by: Rob Clark <robdclark@gmail.com>
| | * | | | | | | | drm/msm: workaround for missing irq on a306/8x16Rob Clark2015-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
| | * | | | | | | | drm/msm: adreno a306 supportRob Clark2015-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As found in apq8016 (used in DragonBoard 410c) and msm8916. Note that numerically a306 is actually 307 (since a305c already claimed 306). Nice and confusing. Signed-off-by: Rob Clark <robdclark@gmail.com>
| | * | | | | | | | drm/msm: clarify downstream bus scalingRob Clark2015-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few spots in the driver have support for downstream android CONFIG_MSM_BUS_SCALING. This is mainly to simplify backporting the driver for various devices which do not have sufficient upstream kernel support. But the intentionally dead code seems to cause some confusion. Rename the #define to make this more clear. Signed-off-by: Rob Clark <robdclark@gmail.com>
| | * | | | | | | | drm/msm/mdp4: Support NV12MT format in mdp4Rob Clark2015-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using fb modifier flag, support NV12MT format in MDP4. v2: - rework the modifier's description [Daniel Vetter's comment] - drop .set_mode_config() callback [Rob Clark's comment] v3: - change VENDOR's name and restrict usage to NV12 [pointed by Daniel] Signed-off-by: Rob Clark <robdclark@gmail.com>
| | * | | | | | | | drm/msm: update generated headersRob Clark2015-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rob Clark <robdclark@gmail.com>
| | * | | | | | | | drm/msm: add missing DRIVER_ATOMIC flagRob Clark2015-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Somehow this got lost when msm atomic support was first merged. Signed-off-by: Rob Clark <robdclark@gmail.com>
| | * | | | | | | | drm/msm/adreno: dump scratch regs and other info on hangRob Clark2015-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dump a bit more info when the GPU hangs, without having hang_debug enabled (which dumps a *lot* of registers). Also dump the scratch registers, as they are useful for determining where in the cmdstream the GPU hung (and they seem always safe to read when GPU has hung). Note that the freedreno gallium driver emits increasing counter values to SCRATCH6 (to identify tile #) and SCRATCH7 (to identify draw #), so these two in particular can be used to "triangulate" where in the cmdstream the GPU hung. Signed-off-by: Rob Clark <robdclark@gmail.com>
| * | | | | | | | | Merge tag 'drm-intel-next-fixes-2015-06-11' of ↵Dave Airlie2015-06-12
| |\ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm-intel into drm-next firmware name fix * tag 'drm-intel-next-fixes-2015-06-11' of git://anongit.freedesktop.org/drm-intel: drm/i915/skl: Fix DMC API version in firmware file name
| | * | | | | | | | drm/i915/skl: Fix DMC API version in firmware file nameRodrigo Vivi2015-06-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 04 is the minor version. API version is ver1. So let's follow same scheme used on published version at 01.org. If really needed the minor version a follow-up updated will be done. But for now we need to move fwd and unblock end users. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| * | | | | | | | | Merge tag 'drm-amdkfd-next-fixes-2015-06-10' of ↵Dave Airlie2015-06-12
| |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~gabbayo/linux into drm-next - Make the reset wavefronts action be per process per device instead of per process, because one device can be stuck but the other one won't be - Add some missing properties to the CZ device_info structure - Rename symbols to not have CONFIG_ prefix - Some more cleanups and debug prints * tag 'drm-amdkfd-next-fixes-2015-06-10' of git://people.freedesktop.org/~gabbayo/linux: drm/amdkfd: remove not used defines from cik_regs.h drm/amdkfd: Add missing properties to CZ device info drm/amdkfd: make reset wavefronts per process per device drm/amdkfd: add debug print to kfd_events.c drm/amdkfd: avoid CONFIG_ prefix for non-Kconfig symbols
| | * | | | | | | | | drm/amdkfd: remove not used defines from cik_regs.hOded Gabbay2015-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| | * | | | | | | | | drm/amdkfd: Add missing properties to CZ device infoOded Gabbay2015-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds two missing properties initializations to the device info structure of CZ. As we don't have CZ support yet, it isn't critical, but its important to fix this now instead of forgetting about it later. Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| | * | | | | | | | | drm/amdkfd: make reset wavefronts per process per deviceBen Goz2015-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit moves the reset wavefront flag to per process per device data structure, so we can support multiple devices. Signed-off-by: Ben Goz <ben.goz@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| | * | | | | | | | | drm/amdkfd: add debug print to kfd_events.cOded Gabbay2015-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| | * | | | | | | | | drm/amdkfd: avoid CONFIG_ prefix for non-Kconfig symbolsValentin Rothberg2015-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_ prefix is reserved for Kconfig options in Make and CPP syntax. Various static analysis tools rely on this naming convention and check if CONFIG_ prefixed symbols are defined Kconfig. Hence add yet another prefix AMD_ to CONFIG_REG_{BASE,END,SISE} to apply to this convention and make static analysis tools happy. Signed-off-by: Valentin Rothberg <valentinrothberg@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
| * | | | | | | | | | Merge branch '2015-06-08-st-drm-next' of ↵Dave Airlie2015-06-12
| |\ \ \ \ \ \ \ \ \ \ | | |_|_|/ / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://git.linaro.org/people/benjamin.gaignard/kernel into drm-next Mainly it is fixing timing on HDMI to be compliant with CEA-861E spec. * '2015-06-08-st-drm-next' of http://git.linaro.org/people/benjamin.gaignard/kernel: drm/sti: vtg fix CEA-861E video format timing error drm/sti: hdmi fix CEA-861E video format timing error drm/sti: VTG interrupt names are badly displayed drm/sti: missing first pixel column on HDMI display drm/sti: correctly test devm_ioremap() return
| | * | | | | | | | | drm/sti: vtg fix CEA-861E video format timing errorVincent Abriou2015-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HDMI analyzer tests showed that Vsync and Hsync signal were not compliant with the HDMI protocol. HDMI_DELAY should be taken into account in the VTG Vsync programming to reflect the 6 pixels shift introduced in the VTG Hsync programming. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
| | * | | | | | | | | drm/sti: hdmi fix CEA-861E video format timing errorVincent Abriou2015-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HDMI analyzer tests showed that Vsync and Hsync signal were not compliant with the HDMI protocol. The first active pixel of a line is defined by HDMI_ACTIVE_VID_XMIN. The last active pixel of a line is defined by HDMI_ACTIVE_VID_XMAX. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
| | * | | | | | | | | drm/sti: VTG interrupt names are badly displayedVincent Abriou2015-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VTG interrupt names are badly displayed using "cat /proc/interrupts". Simply use the VTG device name while registering the VTG interrupts to fix it. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
| | * | | | | | | | | drm/sti: missing first pixel column on HDMI displayVincent Abriou2015-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | VTG programing updated to fix the shift of one column observed on HDMI display. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
| | * | | | | | | | | drm/sti: correctly test devm_ioremap() returnWei Yongjun2015-06-08
| | |/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of error, the function devm_ioremap_nocache() returns NULL not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
| * | | | | | | | | drm/virtio: remove some dead codeDan Carpenter2015-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The goto is correct, and we never reach the return statement so just delete the dead code. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | | | | | | | drm/virtio: checking for NULL instead of IS_ERRDan Carpenter2015-06-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | virtio_gpu_alloc_object() returns an error pointer, it never returns NULL. Fixes: dc5698e80cf7 ('Add virtio gpu driver.') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | | | | | | | | drm/amdgpu: fix a amdgpu_dpm=0 bugSonny Jiang2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: don't enable/disable display twice on suspend/resumeAlex Deucher2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We were doing it in the common code and in the IP specific code. Remove the IP specific code. The common code handles the ordering properly. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: fix UVD/VCE VM emulationChristian König2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: enable vce powergatingSonny Jiang2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable VCE dpm and powergating. VCE dpm dynamically scales the VCE clocks on demand. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
| * | | | | | | | | drm/amdgpu/iceland: don't call smu_init on resumeAlex Deucher2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | smu_init allocates buffers and initializes them. It does not touch the hw. There is no need to do it again on resume. It should really be part of sw_init (and smu_fini should be part of sw_fini), but we need the firmware sizes from the other IPs for firmware loading so we have to wait until sw init is done for all other IPs. Reviewed-by: Sonny Jiang <Sonny.Jiang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu/tonga: don't call smu_init on resumeAlex Deucher2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | smu_init allocates buffers and initializes them. It does not touch the hw. There is no need to do it again on resume. It should really be part of sw_init (and smu_fini should be part of sw_fini), but we need the firmware sizes from the other IPs for firmware loading so we have to wait until sw init is done for all other IPs. Reviewed-by: Sonny Jiang <Sonny.Jiang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu/cz: don't call smu_init on resumeAlex Deucher2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | smu_init allocates buffers and initializes them. It does not touch the hw. There is no need to do it again on resume. It should really be part of sw_init (and smu_fini should be part of sw_fini), but we need the firmware sizes from the other IPs for firmware loading so we have to wait until sw init is done for all other IPs. Reviewed-by: Sonny Jiang <Sonny.Jiang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: update to latest gfx8 golden register settingsAlex Deucher2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: whitespace cleanup in gmc8 golden regsAlex Deucher2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/admgpu: move XDMA golden registers to dce codeAlex Deucher2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Already moved other display registers. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: fix the build on big endianAlex Deucher2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some leftover copy and pastes from radeon that never got updated. Reviewed-by: Christian König <christian.koenig@amd.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: remove the VI hardware semaphore in ring syncDavid Zhang2015-06-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Zhang <david1.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
| * | | | | | | | | drm/amdgpu: set the gfx config properly for all CZ variants (v2)Alex Deucher2015-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Need to adjust the number of CUs and RBs. v2: get proper values Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: also print the pci revision when printing the pci idsAlex Deucher2015-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver makes use of this information so print if to aid in debugging. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Samuel Li <samuel.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: cleanup VA IOCTLChristian König2015-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the unnecessary returned status and make the IOCTL write only. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: fix saddr handling in amdgpu_vm_bo_unmapChristian König2015-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: fix amdgpu_vm_bo_mapChristian König2015-06-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to reset the bo_va address, otherwise new mappings wouldn't be updated in the page table. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: disable user fence interrupt (v2)Chunming Zhou2015-06-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | amdgpu submits both kernel and user fences, but just need one interrupt, disable user fence interrupt and don't effect user fence. v2: fix merge error Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
| * | | | | | | | | drm/amdgpu: fix user ptr race conditionChristian König2015-06-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: monk liu <monk.liu@amd.com>
| * | | | | | | | | drm/amdgpu: add zero timeout check in amdgpu_fence_wait_seq_timeoutJack Xiao2015-06-05
| |/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
| * | | | | | | | Merge branch 'drm-next-4.2-amdgpu' of ↵Dave Airlie2015-06-05
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~agd5f/linux into drm-next This is the big pull request for amdgpu, the new driver for VI+ AMD asics. I currently supports Tonga, Iceland, and Carrizo and also contains a Kconfig option to build support for CI parts for testing. All major functionality is supported (displays, gfx, compute, dma, video decode/encode, etc.). Power management is working on Carrizo, but is still being worked on for Tonga and Iceland. * 'drm-next-4.2-amdgpu' of git://people.freedesktop.org/~agd5f/linux: (106 commits) drm/amdgpu: only support IBs in the buffer list (v2) drm/amdgpu: add vram_type and vram_bit_width for interface query (v2) drm/amdgpu: add ib_size/start_alignment interface query drm/amdgpu: add me/ce/pfp_feature_version interface query drm/amdgpu add ce_ram_size for interface query drm/amdgpu add max_memory_clock for interface query (v2) drm/amdgpu: add hdp flush for gfx8 compute ring drm/amdgpu: fix no hdp flush for compute ring drm/amdgpu: add HEVC/H.265 UVD support drm/amdgpu: stop loading firmware with pm.mutex locked drm/amdgpu: remove mclk_lock drm/amdgpu: fix description of vm_size module parameter (v2) drm/amdgpu: remove all sh mem register modification in vm flush drm/amdgpu: rename GEM_OP_SET_INITIAL_DOMAIN -> GEM_OP_SET_PLACEMENT drm/amdgpu: fence should be added to shared slot drm/amdgpu: sync fence of clear_invalids (v2) drm/amdgpu: max_pde_used usage should be under protect drm/amdgpu: fix bug of vm_bo_map (v2) drm/amdgpu: implement the allocation range (v3) drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2) ...
| | * | | | | | | | drm/amdgpu: only support IBs in the buffer list (v2)Marek Olšák2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | amdgpu_cs_find_mapping doesn't work without all buffers being validated, so the TTM validation must be done first. v2: only use amdgpu_cs_find_mapping for UVD/VCE VM emulation Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
| | * | | | | | | | drm/amdgpu: add vram_type and vram_bit_width for interface query (v2)Ken Wang2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Track the type of vram on the board and provide a query for it. User mode drivers and tools want this information for determining bandwidth information and form informational purposes. v2: fix build when CI support is not enabled Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
| | * | | | | | | | drm/amdgpu: add ib_size/start_alignment interface queryKen Wang2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Query the IB alignment requirements from the kernel rather than hardcoding them in the user mode drivers. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
| | * | | | | | | | drm/amdgpu: add me/ce/pfp_feature_version interface queryKen Wang2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide this information to usermode drivers. We were previously missing this info. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
| | * | | | | | | | drm/amdgpu add ce_ram_size for interface queryKen Wang2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a query for the CE ram size. User mode drivers will want to use this to determine how much size of the cache on the CE. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewd-by: Jammy Zhou <Jammy.Zhou@amd.com>