| Commit message (Collapse) | Author | Age |
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memptrs->wptr seems to be unused. Remove it to avoid
confusing the upcoming preemption code.
Change-Id: Ic0dedbadacef5e866bd37a332019f1133f1def49
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the
user sets 'hint' to non-zero it means that they want a IOVA for the
GEM object instead of a mmap() offset. Return the iova in the 'offset'
member.
Change-Id: Ic0dedbad543df80fdc4b74cd1cd924e9b8534b44
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add support for the A540 GPU which is a revision of the A530 target
with somewhat more complicated power management support.
Change-Id: Ic0dedbadeca628809b6de7c1843f665ecdc427fe
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Bring in a new revision of the rnndb register to fill out some A540
registers.
Change-Id: Ic0dedbad0daf9ad2301479354a83c05bdc301163
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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In the current code the probed configuration is pretty light and it
can be easily probed at boot time and stored in a config struct.
As more features come online the configuration becomes tougher and
more platform specific. It makes sense to do the configuration in
real time so move the majority of the config over to adreno_gpu and
probe at load.
Change-Id: Ic0dedbade871aae2d39e6b036a5e73e4347fc7ca
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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The A5XX GPU powers on in "secure" mode. In secure mode the GPU can
only render to buffers that are marked as secure and inaccessible
to the kernel and user through a series of hardware protections. In
practice secure mode is used to draw things like a UI on a secure
video frame.
In order to switch out of secure mode the GPU executes a special
shader that clears out the GMEM and other sensitve registers and
then writes a register. Because the kernel can't be trusted the
shader binary is signed and verified and programmed by the
trustzone using the PIL loader to upload the binary and access
to the special register is blocked with hardware protection.
So in summary, to do secure mode correctly you need 1) a friendly
trustzone, 2) PIL loader support and 3) a verified zap shader.
For targets without secure support there is an out: if the
trustzone doesn't support secure then there are no hardware
protections and we can freely write the SECVID_TRUST register from
the CPU. Unfortunately we don't have any good way to figure out
at runtime if the trustzone is secure or not so we use a cheat.
If there is a zap shader specified in the device tree for the
target, we assume that the trustzone is secure. No zap shader
definition means that the target is not secure. The downside
of course is that if you guess wrong you trigger a XPU violation
which usually ends up in a system crash but thats a problem
that shows up immediately.
Change-Id: Ic0dedbad8738ad1fac8a7bb8d76e1988aa49f2c8
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Most 5XX targets have GPMU (Graphics Power Management Unit) that
handles a lot of the heavy lifting for power management including
thermal and limits management and dynamic power collapse. While
the GPMU itself is optional, it is usually nessesary to hit
aggressive power targets.
If the GPMU is to be used a filename and minimum version are
defined in the device tree. The GPMU firmware needs to be loaded
into the GPMU at init time via a shared hardware block of registers.
Using the GPU to write the microcode is more efficient than using the
CPU so at first load create an indirect buffer that can be executed
during subsequent initalization sequences.
After loading the GPMU gets initalized through a shared register
interface and then we mostly get out of its way and let it do
its thing.
Change-Id: Ic0dedbad8d899177919b71500f2e944b187e87c0
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add support for the A5XX family of Adreno GPUs.
Change-Id: Ic0dedbad665ef9d0f2cdb32a33eef9fe3fd7aa5c
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Verify that the GPU is valid before calling any ioctl functions
that might need the priv->gpu member. Standardize the return
code (-ENXIO).
Change-Id: Ic0dedbad015a531b792e0b94cb61e0570b691de8
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Currently the value written to CP_RB_WPTR is calculated on the fly as
(rb->next - rb->start). But as the code is designed rb->next is wrapped
before writing the commands so if a series of commands happened to
fit perfectly in the ringbuffer, rb->next would end up being equal to
rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR.
The easiest way to fix this is to mask WPTR when writing it to the
hardware; it makes the hardware happy and the rest of the ringbuffer
math appears to work and there isn't any point in messing with things.
Change-Id: Ic0dedbade543a2253b88acf46a8f8e062ae7faf9
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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For every submission buffer object one of MSM_SUBMIT_BO_WRITE
and MSM_SUBMIT_BO_READ must be set (and nothing else). If we
allowed zero then the buffer object would never get queued to
be unreferenced.
Change-Id: Ic0dedbad8a4543428372fe3fef9503cedd1eef6e
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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The upstream DT model presumes that the iommu phandle is in the main
GPU device node. The downstream model defines sub-nodes for the
IOMMU devices. In order to get the right device to attach the IOMMU
domain to we need to do a bit of searching.
First, check in the top level node. If that fails, then start walking
the port list passed in the attached function - hopefully one of those
will have the right device - if found, use that to attach the domain
and breathe normally.
Change-Id: Ic0dedbad4a1852d2ff204031bd360e0b7960805a
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Newer Adreno GPUs are able to support 64 bit virtual addressing. To
prepare for this brave new world switch all IOVA related variables
and members to a uint64_t container. This is harmless for the
display and older targets that do not have 64 bit addressing because
a 32 bit address is just a 64 bit address with lots of zeros. To
avoid ambiguity and compiler oddness make sure to use
lower_32_bits() and upper_32_bits() everywhere the IOVA is used to
ensure that you get what you expect.
Change-Id: Ic0dedbad23322fae32509c1f4d75d9b4e2863081
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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In the future we won't have a fixed set of addresses spaces.
Instead of going through the effort of assigning a ID for each
address space just use the address space itself as a token for
getting / putting an iova.
This forces a few changes in the gem object however: instead
of using a simple index into a list of domains, we need to
maintain a list of them. Luckily the list will be pretty small;
even with dynamic address spaces we wouldn't ever see more than
two or three.
Change-Id: Ic0dedbad4495f02a21135217f3605b93f8b8dfea
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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PM_QOS will put the interrupt where it wants to and we're okay
with that.
Change-Id: Ic0dedbad5294d51a55125a0021f7dcc3b185de02
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Disable the interrupt during the init sequence to avoid having
interrupts fired for errors and other things that we are not
ready to handle while initializing.
Change-Id: Ic0dedbad972f25586e792478f9c96c4af7c31d17
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add some new functions to manipulate GPU registers. gpu_read64 and
gpu_write64 can read/write a 64 bit value to two 32 bit registers.
For 4XX and older these are normally perfcounter registers, but
future targets will use 64 bit addressing so there will be many
more spots where a 64 bit read and write are needed.
gpu_rmw() does a read/modify/write on a 32 bit register given a mask
and bits to OR in.
Change-Id: Ic0dedbadb83d3ac46f7e463c9c901d4f94a7bb58
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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There are very few register accesses in the common code. Cut down
the list of common registers to just those that are used. This
saves const space and saves us the effort of maintaining registers
for A3XX and A4XX that don't exist or are unused.
Change-Id: Ic0dedbadb4dccbba284e9badf2f52f3a72594581
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Add helper functions for TYPE4 and TYPE7 ME opcodes that replace
TYPE0 and TYPE3 starting on the A5XX targets.
Change-Id: Ic0dedbad114e28bdbcba55a788c6307b48e14675
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Bring in refreshed register definitions from the rnndb database.
Change-Id: Ic0dedbaddd22f6ac0b8cfb6184073968569de22d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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When the GPU hardware init function fails (like say, ME_INIT timed
out) return error instead of blindly continuing on. This gives us
a small chance of saving the system before it goes boom.
Change-Id: Ic0dedbad142efbc9bd93e8531b40c391ec15f557
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Make sure to detach the MMU device before destroying the address
space.
Change-Id: Ic0dedbadff27fed017840a61ec5e0d55ce0c71e6
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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SDE and the GPU have different requirements for the SMMU backends - the
SDE generates its own iova addresses and needs special support for DMA
buffers and the GPU does its own IOMMU operations. Add a shim layer to
aspace to break out the address generation and call the appropriate
SMMU functions. There is probably consolidation that can be done, but for
now this is the best way to deal with the two use cases.
Change-Id: Ic0dedbadc6dc03504ef7dffded18ba09fb3ef291
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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We can have various combinations of 64b and 32b address space, ie. 64b
CPU but 32b display and gpu, or 64b CPU and GPU but 32b display. So
best to decouple the device iova's from mmap offset.
Change-Id: Ic0dedbad2b36b535df3e8fb2ddddc20add592cea
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 22877bcbdacd50d076f9b2f829e6a3753aa9821f
Git-repo: https://github.com/freedreno/kernel-msm.git
[jcrouse@codeaurora.org: Fix merge conflicts, remove mdp5 due to large
infrastructure changes, compile fixes]
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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We'll need this too for shrinker/purging.
Change-Id: Ic0dedbada844d46b608c99cf3eaa3a898a6d5016
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 4fe5f65e66823dcb212a0404af47389b2b1c58f0
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[jcrouse@codeaurora.org: Modified to use different iommu map function
and merge with existing display changes]
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Nobody uses this now that we are entirely scatter/gather enabled.
Remove it to avoid having to calculate the length unnecessarily.
Change-Id: Ic0dedbad020998e1c8fd5d526789f73beb0d5755
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Previous value really only made sense on armv7 without LPAE. Everything
that supports more than 4g of memory also has iommu's that can map
anything.
Change-Id: Ic0dedbad6ca5973f2ac0d2690dec77e40787b8da
Git-commit: 49d24b7a6bf253aeb7cb81672316c83e7b628ea9
Git-repo: https://github.com/freedreno/kernel-msm
Signed-off-by: Rob Clark <robdclark@gmail.com>
[jcrouse@codeaurora.org: Fixed minor merge issues]
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Use phys_addr_t to store physical addresses destined for iommu_map() to
support targets that can have more than 32 bits of physical address space.
Change-Id: Ic0dedbad8d87bf05c602bccdd48338086d76478d
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Remove CONFIG_OF checks in adreno_device.c. The downstream bus scaling
stuff is included only when CONFIG_OF is not set. So, remove that too.
Change-Id: Ic0dedbadbd39970667e7ab745c4b276690a0b0d7
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 66a42f8586897c3a95ac2fef5e2ee1e69da695c8
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Not sure where it came from, but seem unintentional. And also not
needed on a420, so let's just drop it.
Change-Id: Ic0dedbaddb70f0268d4182cc206412b6c69fd472
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 7977f4426c44da95c5dba91a62f099411e029de8
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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As described in the downstream/kgsl driver:
Sometimes the RPTR shadow memory is unreliable causing timeouts
in adreno_idle(). Read it directly from the register instead.
Change-Id: Ic0dedbadf67029a7f8f872daa16d2286efe46267
Signed-off-by: Craig Stout <cstout@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 7d0c5ee9f07779ab29ac291748060a0a6f1d66db
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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We need this for GL_TIMESTAMP queries.
Note: currently only supported on a4xx.. a3xx doesn't have this
always-on counter. I think we could emulate it with the one CP
counter that is available, but for now it is of limited usefulness
on a3xx (since we can't seem to do time-elapsed queries in any sane
way with the existing firmware on a3xx, and if you are trying to do
profiling on a tiler you want time-elapsed). We can add that later
if it becomes useful.
Change-Id: Ic0dedbad46a7cb22391de89ed2341a5a378e1bb0
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 6c77d1abe61797239533918d7a0336fc84f4aef1
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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We need this in userspace for interpreting some of the perf ctrs.
Note possibly not quite sufficient if we had some frequency mgmt
approach other than race-to-idle. Not really sure what the best
thing to do if we did. Although displaying results as a percentage
of max frequence seems sensible(ish) if we did.
Change-Id: Ic0dedbad1d8481cd2609ae0d86d4de6045f0d22e
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Git-commit: 4102a9e5325941223fbfa0a56175e9efb3d4385a
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Change-Id: Ic0dedbadb04269a45b56bc88955977110607b566
Signed-off-by: Craig Stout <cstout@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 38bbc55ef5858301f5da6f6261434033a30058f6
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Change-Id: Ic0dedbad2287ea30f82398e3a8d2e40d15fad95a
Signed-off-by: Craig Stout <cstout@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: 357ff00b08d67cfb489f2e306bda7d3ef45a1306
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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Pull in additional regs needed for a430, etc.
Change-Id: Ic0dedbada256c546268b2a19556a78e8912d06e4
Signed-off-by: Rob Clark <robdclark@gmail.com>
Git-commit: a2272e48eef02869dc3fa031720f36dd4cb05e4f
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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With commit <5aad7456b5a5aeea93a437ae46680a97d089fe51> (<drm/msm/sde:
parse csc type dtsi entry to select valid csc>), support for
CSC is added to 8998 target. However this is an optional property for
some targets. Fix the parsing logic to not fail in case of missing
optional properties.
CRs-Fixed: 2002381
Change-Id: Idfe750d3afbd0d88d89ffa873deae130a24b2827
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Manoj Kumar AVM <manojavm@codeaurora.org>
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Currently any pending PAGE_FLIP events are not signalled
by the drm driver. Userspace blocks on these events
to trigger a redraw. Add support to signal the PAGE_FLIP
complete events after commit is complete.
Change-Id: I887efc48f8890e5e1ed055f7016393a90fc26fa6
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
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If the user-space client doesn't provide the pixel extension and qseed3
configuration, driver should set the default values. Change sets the
default values if user-space client is not configuring the blocks when
VIG pipes are selected.
CRs-Fixed:2002381
Change-Id: I02f0e76fb87587d2eed9e5f4fcca5baa7d605b92
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Signed-off-by: Manoj Kumar AVM <manojavm@codeaurora.org>
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With the conversion of the master device to use the arm iommu
ops we lose the benefit of a cache flush using the dma_map_sg
trick. Plus we end up mapping all the GPU buffers into the master
DMA device which is admittedly sub optimal.
However it did end up mapping all the display buffers which
unintentionally worked. Put the map_sg() functions back into msm_gem.c
to make it intentionally work from now on.
Change-Id: Ic0dedbada1a8723fb47311189a6b7e11969427ee
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
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* quic/dev/msm-4.4-drm_kms:
drm/msm/sde: allow mmus to be optional during kms init
drm/msm/sde: check for null catalog in sde hw destroy
drm/msm: treat data bus dtsi property as optional
drm/msm/sde: add crtc clock & bandwidth capabilities
drm/msm/sde: parse csc type dtsi entry to select valid csc
drm/msm: fix copyright marking in "msm" drm driver
drm/msm: remove smmu coherent hardware table walk attrib
drm/msm/sde: add DMA2 and DMA3 pipe staging support
drm/msm/sde: add event for underruns
drm/msm/sde: fix check for frame event overflow
ARM: dts: msm: add ping pong split definitions for msm8996
ARM: dts: msm: add sde max bus bandwidth setting for msm8996
drm/msm/sde: add dynamic clock and bandwidth commit support
ARM: dts: msm: add sde bus scale settings for msm8996
drm/msm/sde: add bus bandwidth control for crtc
drm/msm/sde: add frame done callback event to crtc
drm/msm/sde: bypass crtc atomic begin/flush if disabled
drm/msm/sde: add debugfs entry for vbif
drm/msm/sde: add debugfs entry for danger and safe status
drm/msm/sde: enable ping pong split support
ARM: dts: msm: enable imgswap on sharp nt35597 dual panel
drm/msm/sde: remove catalog parsing limits
drm/msm/sde: update pixel extension uapi
drm/msm/sde: enable master physical encoder last
drm/msm/sde: reset ctl mixer config at end of use case
drm/msm: Support virtualization of color processing properties
drm/msm/sde: Move DSPP/SSPP color process hw programming to common location
drm/msm/sde: Add support for Memory Color in plane
drm/msm/sde: Add PA global adjustment properties to plane
drm/msm: implement smmu detach and guard freeing of client dev
drm/msm/sde: reset kickoff count atomically before irq enable
ARM: dts: msm: default sde clock rate to max for msm8996
drm/msm/sde: base scaler phase on decimated dimensions
drm/msm/sde: move sde hw init to hw_init callback
drm/msm/sde: check for missed irqs in command encoder
drm/msm: support probe deferral in msm_drv
drm/msm/sde: fix iounmap usage and init callflow
drm/msm/sde: fixup sde_kms shutdown sequence and naming
drm/msm/sde: fix cmd mode vblank irq control
drm/msm/sde: apply correct zpos range for sde clients
drm: Increase max number of DRM object properties
drm/msm/sde: add debug dump and panic facility
drm/msm/sde: match xlog features in evtlog
drm/msm/sde: add debugfs support for misr data
drm/msm/sde: Add device tree subnode parsing capability
drm/msm: create separate commit thread for each display
drm/msm/sde: Add backlight class support for sde drm driver
drm/msm/sde: add common sde debug folder
drm/msm/sde: route evtlog to sde trace log
drm/msm/sde: add systrace compatible trace macro
drm/msm/sde: separate plane/encoder/crtc functions into headers
drm/msm/sde: add default 10 bit csc matrix to source pipe
drm/msm/sde: add 10 bit csc for sde
drm/msm/sde: add qseedv3.x support for sde
drm/msm/sde: add 10-bit formats support
drm/msm/sde: print error only if catalog property is mandatory
drm/msm/sde: remove redundant vblank request in crtc
drm/msm/sde: add vblank reference counting to crtc
drm/msm/sde: handle pingpong blocks from virtual encoder
drm/msm/sde: add support for BGRX and XBGR formats in plane
drm/msm/sde: add multi-client and ref counting for core irq
drm/msm/sde: cache connector list in sde crtc
drm/msm/sde: remove display manager
drm/msm/sde: fix video encoder access in phy encoder
drm/msm/sde: add debugfs node for vsync and underrun status
drm/msm/sde: update vblank and underrun isr handling
drm/msm/sde: fix color component order
drm/msm/dsi-staging: fix issues related to deferral
drm/msm/sde: remove static allocation of mdp_top hw block
drm/msm: initialize local varibles in sde power module
drm/msm/sde: dual pipe use case support
drm/msm/sde: update crtc status debugfs node
ARM: dts: msm: add vbif OT and plane QoS/LUT for msm8996
drm/msm/sde: add clock control parsing to hardware catalog
drm/msm/sde: correct read out of bit offset array
drm/msm/sde: add plane QoS parsing to hardware catalog
drm/msm/sde: add vbif parsing to hardware catalog
drm/msm/sde: add writeback id parsing to hardware catalog
drm/msm/sde: update mixer op mode config bit fields correctly
drm/msm/sde: add sde error prefix for all errors
drm/msm: add capability property for crtc
drm/msm/sde: update ubwc and src split properties for sde
drm/msm/sde: correct to use sync vblank request for commit
drm/msm: execute pending vblank disable upon last close
drm/msm/sde: update crtc to use sde debug macros
drm/msm/sde: remove unused functions in sde crtc
drm/msm/sde: move sde_crtc declarations into sde_crtc header
drm/msm/sde: move sde_crtc away from legacy drm vblank apis
drm/msm: add error logging in msm_atomic
drm/msm/sde: move vbif functions to their own file
defconfig: enable backlight class driver for msm defconfig.
drm/msm/sde: additional event logging for fences
drm/msm/sde: assign relative mixer stages based on zpos
drm/msm/sde: remove redundant vblank request and notification
drm/msm/sde: fixup header markings
drm/msm: fix power handle APIs when clk are not present
drm/msm/sde: don't convert ktime to ns when waiting for fences
DOWNSTREAM: drm/msm/sde: enable sde client customizations
drm/msm: rename kernel module to msm_drm
drm/msm/sde: allow primary planes to be used with all crtcs
drm/msm/sde: limit primary plane count to number of crtcs
drm/msm: teardown all modes in lastclose handler
drm/msm/sde: update proper error message for rm failure
drm/sde: move hardware catalog to dtsi parser
drm/msm/sde: enable proper support for split flush
drm/msm/sde: add mode config mutex lock for connector search
drm/msm/sde: bypass wait for commit done if crtc is not enabled
drm/msm/sde: add proper mode config lock to plane QoS check
drm/msm/sde: correct crtc to use new plane state for update
drm/msm/sde: remove error message from optional settings
drm/msm/sde: remove unused traffic shaper from hw drivers
drm/msm: property read should return success for virtual crtc
drm/msm/sde: avoid programming same plane source address
drm/msm/sde: update plane dmesg logging to use sde macros
drm/msm/sde: update scaler property definition and type
drm/msm/sde: break out plane decimation to separate properties
drm/msm/sde: update register writes to use SDE logging macros
drm/msm/sde: update csc property definition and type
drm/msm: Modularize property install function of color processing
drm/msm: Add support for PA vLut feature
drm/msm: Expose Assertive display capability
drm/msm: Suspend/Resume support for color processing features
drm/msm: Add support for PCC in Crtc
drm/msm/sde: update catalog for post processing
drm/msm/sde: don't duplicate input fence pointer with state
drm/msm/sde: fix color component order for compressed formats
drm/msm/sde: add writeback ROI support for msmskunk
drm/msm/sde: add const alpha support for msmskunk
ARM: dts: msm: add max clock property for sde to msm8996
drm/msm/sde: add max clock property for sde
drm/msm: add support for custom event notification
drm/msm: Initial version post processing header
drm/msm: remove msm clock driver header files
drm/msm/dsi-staging: keep backlight api under LED config
drm/msm/sde: enable sde clocks during debugfs register read
drm/msm/sde: update pipes on dirty plane properties
drm/msm/sde: fix compilation issues in sde driver
drm/msm/sde: update encoder dmesg logging to use sde macros
drm/msm/sde: remove unused header dependency
drm/msm/sde: use const alpha for wb if pipe alpha not supported
drm/msm/sde: remove unused sde functions
drm/msm/sde: add mode change request to cdm resource update
drm/msm/sde: cleanup alpha calc and plane stage in crtc
ARM: dts: msm: send panel off command during pre off state
drm/msm/sde: remove unused writeback function stubs
drm/msm/sde: remove unused vblank control for writeback
drm/msm/sde: remove unused encoder function
drm/msm/sde: always clear topology name when removing rsvp
drm/msm/sde: reorganize top level interrupt handling code
drm/msm/sde: add OT support for source pipe and writeback
drm/msm/sde: add danger/safe/QoS support for source pipe
drm/msm/sde: improve debug log for blend setup
DOWNSTREAM: drm/msm/sde: optionally delay output fence signal
drm/msm/sde: determine output fence timing on create
drm/sde: use power handle api to vote for core clock
ARM: dts: msm: add clk rate and gdsc supply entry for msm8996
drm/msm: add power handle driver for msm
drm/msm/sde: add helper macro for performing ktime comparisons
drm/msm/sde: assign ctls based on capability requirements
drm/msm/sde: clean up crtc ctl tracking
drm/msm/sde: improve resource manager hw block lookup time
drm/msm: internal property updates should update cached value
drm/msm/sde: fix plane stage setup in sde crtc
ARM: dts: msm: add nt35597 panel definition for msm8996
drm/sde: remove warn on from sde encoder
drm/sde: allow base layer plane stagging
drm/msm: update plane, crtc and connector caps blob prop
drm/msm/sde: add api for determining current interface mode
drm/msm/sde: fix uninitialized return code in rm
drm/msm/sde: fix atomic check for crtc driver
drm/msm: validate framebuffer before accessing it
drm/msm: fix atomic mode check for sde plane
drm/msm: use drm helper API for atomic check
ARM: dts: msm: remove hdmi connector for msm8996
drm/msm/sde: enable dynamic hardware resource assignment
drm/msm/sde: dynamic hardware resource manager
drm/msm/sde: move crtc towards multi-encoder support
drm/msm/sde: list block interconnects as bitmasks
drm/msm/sde: add topology management properties
drivers/gpu/drm: disable drm fbdev emulation
drm/msm/sde: use common structure for phys encoder init
drm/msm/sde: list hardwired mixer connections
drm/msm: enable/disable sde during driver open and close
drm/dsi: turn off the wled backlight with panel power off
drm/dsi: fix dsi control power supply turn off sequence
drm/msm/sde: add support for dirty properties
drm/msm: allow flags to be set in property helpers
drm/msm/sde: trigger plane modeset on buffer pitch change
ARM: dts: msm: add SDE writeback display for msm8996
drm/msm/sde: enable writeback enumeration in display manager
drm/msm/sde: add virtual writeback device and connector
drm/msm/sde: add resource management for writeback and cdm
drm/msm/sde: add hardware driver support for chroma down module
drm/msm/sde: add hardware driver support for writeback interface
drm/msm/sde: add smmu domain selection logic to connector
drm/msm/sde: add function to return raw interrupt status
ARM: dts: msm: add SDE smmu node to msm8996
drm/msm/sde: Bypass unused interface during smmu init
drm/msm: add non-realtime and secure smmu domains
drm/msm: cache active displays within display manager
drm/msm/sde: add connector api for querying display info
drm/msm/sde: use msm_display_info for display information
drm/msm/sde: explicitly enumerate supported plane formats
drm/msm/sde: add retire fence support
drm/msm/dsi-staging: use sde connector for dsi
drm/msm/sde: add generic support for drm connectors
drm/msm/sde: add utility functions for kms info
drm/msm/sde: enable output_fence property
drm/msm/sde: add output fence utility functions
drm/msm/sde: support more formats including compression
drm/msm: subdriver hook to validate modified formats
drm/msm/sde: add drm fourcc modifier for qcom compressed format
drm/msm/sde: command mode panel encoder support
drm/msm/dsi-staging: turn gpio off if panel reset fails
drm/msm/sde: single kickoff to flush hardware
drm/msm/dsi-staging: add dsi cmd/vid mode to display info
drm/msm: add subdriver callback for single kickoff
drm/msm/sde: fix reading of the pingpong counters
drm/dsi-staging: update configurations for display related GPIOs
drm/msm/sde: add register name to logging
drm/msm/sde: add logmask area for top registers
drm/msm/sde: define sde specific macros for dmesg logging
drm/msm/sde: enable explicit input fences
drm/msm/sde: add support for crtc properties
drm/dsi-staging: reset drm/dsi data before reconfiguring
ARM: dts: msm: fix compilation errors for msm8996
ARM: dts: msm: add configurations for 1080p panel on msm8996
defconfig: enabled drm/kms driver in msm defconfig
drm/msm/dsi: remove unused tag from dsi API
drm/kms: remove compilation of hdcp_hdmi
ARM: dts: msm: update settings for dsi panels
drm/msm: disable mdp4 driver in drm kms
drm/msm: switch to qti KGSL driver
ARM: dts: msm: add configurations for 720p panel
ARM: dts: msm: add device tree for sde dsi device on msm8996
drm/dsi-staging: add support to get regulator data from device tree
drm/msm/sde: use sde plane csc cfg struct for user settings
drm/msm: add display manager to makefile
drm/msm: rename MSM drm platform driver's name into msm_drm
drm/msm/sde: avoid dereferencing scaler blob if null state
drm/msm: handle null blob property array
drm/msm: enable both dsi drivers together
drm: mipi: change header format to work with msm hardware
drm/dsi-staging: remove interrupt handling
drm/msm: move display manager out from dsi-staging
drm/msm/dsi-staging: fix dynamic fps and seamless updates
drm/msm/dsi-staging: support dynamic frame-rate and validation
drm/msm: defer drm driver probe if backlight isn't ready
drm/msm: common display interface for mdp driver
drm/msm/sde: init private kms pointer before modeset init
drm/msm/dsi-staging: add dsi panel driver
drm/msm/dsi-staging: add debugfs support for dsi driver
drm/msm/dsi-staging: add support for command mode panels
drm/msm/dsi-staging: dsi display tests
drm/msm/dsi-staging: add dsi drm interface
drm/msm/dsi-staging: add dsi display driver
drm/msm/sde: replace plane property/state handling with msm_prop
drm/msm: add generic property/state handling
drm/msm: use sde specific color format throughout
drm/msm: move dynamic fps and seamless updates
drm/msm: update wrapper macros for event logging
drm/msm/sde: init spinlock for lm_lock
drm/msm/sde: clean up debug output
drm/msm: add event log for profiling msm drm driver events
drm/msm/sde: pageflip fixes
drm/msm/sde: remove crtc full modeset based on plane changes
drm/msm/sde: add z-order and plane id to prints
drm/msm/sde: add wrappers for release fence API
drm/msm/sde: update max up/down scale
drm/msm/sde: add planes color fill/fence timeout
drm/msm/sde: updates to planes atomic_check
drm/msm/sde: add cache for released plane states
drm/msm/sde: input fence support for planes
drm/msm/sde: add debugfs for crtc
drm/msm/sde: don't overflow mixer cfg fields
drm/msm: enable seamless dynamic framerates
drm/msm/sde: remove plane decimation properties
drm/msm/sde: change csc matrix coeff in h/w driver to s15.16
drm/msm/sde: enable blending across all planes
drm/msm/sde: remove 'mdp' from sde file names
defconfig: msm: enable SYNC Driver
drm/msm/sde: add valid rotator writeback flag
drm/msm/sde: add properties for planes
msm: sde: sde plane properties user definitions
drm/msm/sde: consolidate SDE error logging on DRM standard calls
drm/msm/sde: set encoder role at display probe time
drm/msm/sde: add preliminary debugfs support
drm/msm/sde: add blending support for more use cases
drm/msm/sde: enable NV12 modetest for planes
drm/msm/sde: fixup mdp top split pipe control
drm/msm/sde: add support for vblank callback
drm/msm/dsi-staging: add dsi phy driver
drm/msm/dsi-staging: add clock and power utilities
drm/msm/dsi-staging: add dsi controller driver
drm/msm/sde: add resource manager to enable dual dsi
drm/msm/sde: adding implementation for mdp_top in hw driver
drm/msm/sde: sde hw interrupt handling
drm/msm/sde: simplify encoder display probe logic
drm/msm/sde: move sde encoder to new display interface
drm/msm/sde: programmable pre-fetch support for video encoders
drm/msm/sde: sde encoder virtualization
drm/msm/sde: add controller instance to INTF block in catalog
drm/msm/sde: add basic sde object enumeration
drm/msm: add smmu handler
drm/msm/sde: add driver for sde support
drm/msm/dsi-staging: add catalog for dsi driver
drm/msm/dsi-staging: add hardware driver for dsi controller
drm/msm/dsi-staging: add hardware driver for dsi phy
drm/msm/dsi-staging: add dsi definitions for new dsi driver
drm/msm: remove clock framework dependency
Change-Id: I20ec5183e730d1033f824f3b33f52d5b1578f740
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
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dev/msm-4.4-drm_kms
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Data bus properties such as number of bus channel and number of
axi ports are optional dtsi properties, and should not cause
data bus parsing function to fail.
Clear error code if the above properties do not exist in dtsi.
Change-Id: I44b9d2b462f95444047c8f9f2a83dffae5596074
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
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dev/msm-4.4-drm_kms
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Add clock and bandwidth properties to capabilities blob for crtc.
These properties are used by user mode client to fine tune use
case power/performance.
Change-Id: I9d2a4a299198bc3ba72d1a76f4cc80ee19df8ae0
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
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