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| * | | | | drm/msm: profile submit_time in nanosecond resolutionSharat Masetty2017-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial version of the patch save the command submit_time and queue_time in seconds, but its desired by the users of this profiling API to return the time in nanoseconds resolution. Change-Id: I3a56e3ffd3ebe86f51a00a12b7c3e7c4b4c9a956 Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
* | | | | | Merge "drm/msm: add irq mapping for cec in hdmi driver"Linux Build Service Account2017-05-26
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| * | | | | | drm/msm: add irq mapping for cec in hdmi driverRay Zhang2017-05-25
| | |/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make HDMI device as the interrupt parent of CEC device, so add the new IRQ domain in HDMI driver dealing with the necessary IRQ mapping. Change-Id: Id935da1d1e488ccee01b831b9f085a83d67268f2 Signed-off-by: Ray Zhang <rayz@codeaurora.org>
* | | | | | Merge "drm/sde: only set split registers for DSI interfaces"Linux Build Service Account2017-05-25
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| * | | | | | drm/sde: only set split registers for DSI interfacesJin Li2017-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPLIT related registers are only for DSI interfaces. Without checking the interface type, they could be overwrote by configurations through HDMI path. CRs-Fixed: 1085586 Change-Id: I7ace9fd8dfe5ee99cb750b2723e8f22701039552 Signed-off-by: Jin Li <jinl@codeaurora.org> Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
| * | | | | | drm/sde: set display h/v polarity according to panel infoJin Li2017-05-15
| | |/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The h/v polarity should always be set from the panel configuration. For HDMI display, it's from the EDID information. For DSI display, it's from the panel settings in the dtsi. CRs-Fixed: 1085021 Change-Id: I3776603d7055e69eb2c8e5003ab83bc0483ab7c8 Signed-off-by: Jin Li <jinl@codeaurora.org> Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
* | | | | | Merge "drm/msm: wait fence complete before flip"Linux Build Service Account2017-05-25
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| * | | | | | drm/msm: wait fence complete before flipJin Li2017-05-16
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In async commit case, driver needs to always wait for input fence before triggering the complete_commit path. Otherwise, there could be tearing since GPU hasn't finished the composition rendering. Change-Id: I73a54f5811fdcf8639618ce3cacf4cbaa00b406c Signed-off-by: Felix Xiong <xayang@codeaurora.org> Signed-off-by: Jin Li <jinl@codeaurora.org> Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
* | | | | | Merge "drm/msm: deal with arbitrary # of cmd buffers"Linux Build Service Account2017-05-25
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| * | | | | drm/msm: deal with arbitrary # of cmd buffersRob Clark2017-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some optimizations coming on the userspace side, splitting larger draw or gmem cmds into multiple cmdstream buffers, we need to support much more than the previous small/arbitrary limit. Change-Id: Ic0dedbad2f79156f4e6c9f70c8e27cd5fff9acdb Signed-off-by: Rob Clark <robdclark@gmail.com> Git-commit: 6b597ce2f7c7a0f8116d753902db9aba6bc05cb0 Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git [jcrouse@codeaurora.org: fix some merge conflicts] Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | | | Merge "drm/msm: Don't allow zero sized buffer objects"Linux Build Service Account2017-05-20
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| * | | | | drm/msm: Don't allow zero sized buffer objectsJordan Crouse2017-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zero sized buffer objects tend to make various bits of the GEM infrastructure complain: WARNING: CPU: 1 PID: 2323 at drivers/gpu/drm/drm_mm.c:389 drm_mm_insert_node_generic+0x258/0x2f0 Zero sized buffers serve no appreciable value to the user so disallow them at create time. Change-Id: Ic0dedbada2a0250227d7ee8c45c35dc92a826c67 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | | | Merge "drm/msm: remove mdp node entry"Linux Build Service Account2017-05-16
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| * | | | | | drm/msm: remove mdp node entryNarender Ankam2017-05-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove deprecated mdss_mdp node entry from msm drm driver. Change-Id: Ifdfb39259d38cd0bed33585076b33fb15a953fbd Signed-off-by: Narender Ankam <nankam@codeaurora.org>
* | | | | | | Merge "drm/msm: drop return from gpu->submit()"Linux Build Service Account2017-05-16
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| * | | | | | drm/msm: drop return from gpu->submit()Rob Clark2017-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At this point, there is nothing left to fail. And submit already has a fence assigned and is added to the submit_list. Any problems from here on out are asynchronous (ie. hangcheck/recovery). Change-Id: Ib6b6bf00099137972649c97cc6cd8c4fe25ce7c3 Signed-off-by: Rob Clark <robdclark@gmail.com> Git-commit: 1193c3bcb581807d58dd7df90528ec744af387a9 Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git [smasetty@codeaurora.org: fixed merge conflict issues; made corresponding changes to A5XX submit function.] Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
* | | | | | | Merge "drm/msm: Allocate secure buffer objects"Linux Build Service Account2017-05-11
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| * | | | | drm/msm: Allocate secure buffer objectsJordan Crouse2017-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the user to allocate and use secured buffer objects. Secured buffer objects are suitable for use as a write target while the GPU is in secure mode. They work exactly like regular buffers except Secure buffers cannot be mmap()ed. Change-Id: Ic0dedbadd8135fd8472b38ddf61e2bc70983b12f Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
| * | | | | drm/msm: Support importing secure buffersJordan Crouse2017-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check to see if an imported buffer is an Ion secure buffer and mark it as such so that it can be used for secure rendering. Change-Id: Ic0dedbadb414dcbb11d70785d61481a1b7bd4e19 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
| * | | | | drm/msm: Support secure rendering for A5XX targetsJordan Crouse2017-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A5XX targets support GPU rendering on secured surfaces by going into a special secure mode to execute the commands. In secure mode GPU rendering can only write to secure buffers that have been mapped in an appropriately secured pagetable. In secure mode the GPU can read both secure and unsecure buffers and the CP engine can only access unsecured buffers (so commands do not need to be secure). Secure buffers virtual addresses must fall into a specific range; this is the clue to the GPU that it should use the secure pagetable instead of the regular one. For A5XX targets that range will start at 0xC0000000 and be 256MB in size. All secure buffers in all processes share the same pagetable. Add a secure address space for A5XX targets and automatically trigger into secure mode if any buffer in the submission is marked as secure. Change-Id: Ic0dedbad8f7168711d10928cd1894b98f908425f Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | | | Merge "drm/msm/sde: avoid adding plane states in crtc atomic check"Linux Build Service Account2017-05-10
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| * | | | | | drm/msm/sde: avoid adding plane states in crtc atomic checkClarence Ip2017-05-10
| | |/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch contains fixes to prevent the CRTC's atomic check from inadvertently adding extra plane states to the current state object. CRs-Fixed: 2037970 Change-Id: Ic0b09ab369f77c2412ba7c3e63fe5032ef9bcd74 Signed-off-by: Clarence Ip <cip@codeaurora.org>
* | | | | | Merge "drm/msm/sde: move topology name reset to release resources"Linux Build Service Account2017-05-10
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| * | | | | | drm/msm/sde: move topology name reset to release resourcesLloyd Atkinson2017-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify the clearing of the topology name by moving it directly to the release resources call. Change-Id: If1926372b276f01f64138691b805493d1894951a Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
| * | | | | | drm/msm: allow SDE HDMI display to support 4KAbhinav Kumar2017-05-09
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDE HDMI driver capabilities were capped to 1080P due to lack of dual pipe support in userspace. Relax this restriction as full userspace support to allow dual pipe support is now available. Change-Id: If8242ea3c65a901ceb3e1004ac40b29ab8554c4b Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
* | | | | | Merge "drm/msm: notify hpd status when audio codec is ready"Linux Build Service Account2017-05-10
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| * | | | | drm/msm: notify hpd status when audio codec is readyRay Zhang2017-05-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HDMI connector should wait for audio codec status and notify HPD status only in case that audio codec has been registered successfully. Meanwhile move HPD notification to bridge enable and disable instead of hotplug work. This ensures the correct video and audio sequence. Change-Id: I0dac915c8639bb881265a608016e9d37ec9a153c Signed-off-by: Ray Zhang <rayz@codeaurora.org>
* | | | | | Merge "drm/msm: Fix the SNAPSHOT_HEADER macro"Linux Build Service Account2017-05-04
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| * | | | | drm/msm: Fix the SNAPSHOT_HEADER macroSharat Masetty2017-05-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "_header" field of the macro was being incorrectly expanded to just "header". This was only working because all the functions which used this macro already had "header" defined in scope. Change-Id: I19e77ae78cfff471ddffd428cb3fd055c6340737 Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
* | | | | | Merge "drm/msm: Add preemption records to QTI GPU snapshot"Linux Build Service Account2017-05-03
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| * | | | | drm/msm: Add preemption records to QTI GPU snapshotSharat Masetty2017-05-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch helps dump the full 64k per ring preemption record to GPU snapshot which is collected during GPU recovery step. We use the general object snapshot section type to store these records and we only collect the preemption records if preemption was going to kick in, which is when the number of rings is greater than one. Change-Id: I1872bc14c6b39c8c4963ce9c98e96b03cbfec907 Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
* | | | | | Merge "Merge remote-tracking branch 'remotes/quic/dev/msm-4.4-8996au' into ↵Linux Build Service Account2017-05-02
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| * \ \ \ \ \ Merge remote-tracking branch 'remotes/quic/dev/msm-4.4-8996au' into msm-4.4Zhiqiang Tu2017-05-02
| |\ \ \ \ \ \ | | |/ / / / / | |/| | | | / | | | |_|_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi drivers/gpu/drm/msm/Makefile Change-Id: Ief80c28ff1422fd71a0c3d2041531e2ab078ee7a Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
| | * | | | drm: msm: dsi: add dsi device to tail of display list insteadYunyun Cao2017-04-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DSI display list sequence should be consistent with device tree, so use list_add_tail instead of list_add to insert dsi devices. Change-Id: I11d14d663c59c8ee0d1da280f42d9315e12c2a65 Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
| | * | | | drm/msm/sde: remove redundant CRTC event cachingAbhinav Kumar2017-04-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently both sde_crtc_atomic_begin() and sde_crtc_atomic_flush() add the CRTC state event to the cached sde_crtc->event. This has a potential NULL ptr issue in the case of vblank event firing in between sde_crtc_atomic_begin() and sde_crtc_atomic_flush() because the upstream DRM vblank API send_vblank_event() doesn't consider the case when the VBLANK interrupt could have already freed any pending vblank events. Remove the caching from sde_crtc_atomic_begin() to avoid this condition. Also make sure that a page_flip event was indeed submitted before signaling the complete_flip() by setting a PENDING_FLIP flag right after HW flush. Change-Id: Ib201d2851e57bf22ec1f00814fc2e4dd2f35bfa1 Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
| | * | | | drm/sde: don't set up backlight for dsi bridge on 8996 auto platformYunyun Cao2017-04-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the panel is using bridge chips, such as ADV7533, it doesn't have to set up backlight. Change-Id: I014d697f81ecf1748ade2c40353ffdf9ff7c3669 Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
| | * | | | drm/sde: don't return error when fail to set panel pin ctrlJin Li2017-04-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Panel pin control is not mandatory for all of the DSI panels. If the panel is using bridge chips, such as ADV7533, it doesn't have to configure the panel pin controls. Change-Id: I48d862a9c67d52c0ed8c3c0309b0ff56d13e97f4 Signed-off-by: Jin Li <jinl@codeaurora.org> Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
| | * | | | drm/msm: Don't dump RBBM_SECVID_TSB_CNTLKasin Li2017-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This register is not accessible by CPU for certain TZ, trying to read it will cause CPU hang. Change-Id: Ica1b18db2c3cc2c9bacfdbd4c5eb1e2e172ade33 Signed-off-by: Kasin Li <donglil@codeaurora.org>
| | * | | | drm/msm: Fix gmem range settingKasin Li2017-04-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GMEM IOVA range is intended to start from 0x100000. But currently it is initialized with RANGE_MIN_LO:RANGE_MIN_LO. It makes GMEM IOVA start from 0. Change-Id: Ib3c9a86d0cd85794881d8708386b18d58bd8e58e Signed-off-by: Kasin Li <donglil@codeaurora.org>
| | * | | | drm: sde: enable vblank event when begin to wait for commit doneYunyun Cao2017-04-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vblank event is not enabled and vblank callback function is not registered. As a result, vblank event could not be received in user space. Get crtc vblank when start to wait for commit done to fix this. Change-Id: I5e348eaf689a0bb7384f8dcee787edcf44772eb6 Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
| | * | | | Merge remote-tracking branch 'remotes/origin/msm-4.4' into dev/msm-4.4-8996auArun KS2017-04-06
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/boot/dts/qcom/msm8996pro.dtsi arch/arm64/kernel/Makefile drivers/leds/leds-qpnp-flash.c sound/soc/msm/apq8096-auto.c Change-Id: Idea5d05fec354b8f38ea70643decb03f7b80ddb7 Signed-off-by: Arun KS <arunks@codeaurora.org>
| | * | | | | drm:msm add iommu fault handler functionYajun Li2017-04-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding iommu fault handler callback to iommu driver, which will be called when memory fault happens. Change-Id: Ia2486fe167b889633ea4fb4c42601791efda133c Signed-off-by: Yajun Li <yajunl@codeaurora.org> Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
| | * | | | | drm/sde: update plane pitches when it's different than fbJin Li2017-04-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kernel DRM SDE driver doesn't know the alignment requirement from user space, so it needs to be updated when pitches value when they are different than fb value. Change-Id: I392e247330980fcac87b6fbe49a289e0fc473d85 Signed-off-by: Jin Li <jinl@codeaurora.org> Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
| | * | | | | drm/sde: add panel count to support multiple bridge chipsJin Li2017-04-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When multiple bridge chips are connected to same interface, the drm mode in the mode_set has combined timing parameters. For each individual bridge chip, those timing parameters need to be divided by panel count. CRs-Fixed: 1085590 Change-Id: I9af0fa99ab6bcf9e09f4f7b372d53e6f1638e6d0 Signed-off-by: Jin Li <jinl@codeaurora.org>
| | * | | | | drm/sde: add bridge chip support for drm driverJin Li2017-03-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Display Bridgechip Abstration layer is a common framework to support different kind of bridge chips with multi client accessing. This change is to add a DRM bridge driver and hook it up with DBA framework. Change-Id: Ie225a7cdb55a4982199c1735c37986950c5fad05 Signed-off-by: Jin Li <jinl@codeaurora.org> Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
* | | | | | | Merge "msm/drm: Move msm_drm_config configuration into the GPUs"Linux Build Service Account2017-05-02
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| * | | | | | | msm/drm: Move msm_drm_config configuration into the GPUsJordan Crouse2017-04-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming secure code the decision tree for configuration (deciding where virtual addresses start/stop, etc) is going to get a bit more complex. Head issues off at the pass by moving the configuration into the GPU specific code. This does result in a bit more code duplication but it is a lot cleaner. Change-Id: Ic0dedbad57c11a4bba01825214d0a7853ab537ba Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
| * | | | | | | msm/drm: Add secure support to GPU IOMMUJordan Crouse2017-04-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for creating a secure domain in the GPU IOMMU. By default the secure domain is bound to context bank name "gfx3d_secure". Change-Id: Ic0dedbad19f69ec4175624dc80f2114bfda2e195 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
| * | | | | | | drm/msm: Remove iommu names during attachJordan Crouse2017-04-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | None of the existing iommu implementations use the names passed in at attach time by the API. Save a bit of .data room by removing the static string definitions and passing NULL to the attach function. Change-Id: Ic0dedbada9561768b8d9716ea101619e6b549ea4 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
| * | | | | | | drm/msm: Add enable/disable hooks for mmuJordan Crouse2017-04-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 5XX targets that are using per-process pagetables will need to keep the IOMMU clocks on the entire time because we don't know exactly when the GPU might touch it. That said there are occassional depencency issues if the clocks are enabled out of order. To be certain we should enable the MMU clocks last and disable them first. Add enable/disable hooks to the MMU struct to do this cleanly from the GPU pm_resume / pm_suspend paths. Change-Id: Ic0dedbad8e2298e55c90b29eed657baa0933ddcf Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-07-18 01:12:09 +0000