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* | | | | | | Merge "drm/msm/sde: disable vblank ref power on crtc disable"Linux Build Service Account2017-07-28
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| * | | | | | | drm/msm/sde: disable vblank ref power on crtc disableClarence Ip2017-07-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update vblank reference counts via the exposed sde_crtc_vblank function, rather than attempting to zero it on the side during CRTC disable operations. This allows the power voting to be updated correctly based on the vblank reference count value. CRs-Fixed: 2037677 Change-Id: I7026a1b239503a2b1d97ad7bb61fbc0a4a38d7ea Signed-off-by: Clarence Ip <cip@codeaurora.org>
* | | | | | | | Merge "drm/msm/sde: output black frame during resume operation"Linux Build Service Account2017-07-28
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| * | | | | | | drm/msm/sde: output black frame during resume operationClarence Ip2017-07-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides a module parameter to control whether each plane outputs the previously configured content or a black frame during the resume operation. The default is set to output a black frame. CRs-Fixed: 2019307 Change-Id: I48c1a8edfa1e85252a070bda51228ef67dea041c Signed-off-by: Clarence Ip <cip@codeaurora.org>
| * | | | | | | drm/msm/sde: dispatch suspend/resume notification to cpClarence Ip2017-07-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change enables the appropriate callbacks to the color processing component on suspend/resume transitions. CRs-Fixed: 2019307 Change-Id: I7b8c9eb2b32da42e36d32e9d88e74e0c0c7b1ecb Signed-off-by: Clarence Ip <cip@codeaurora.org>
| * | | | | | | drm/msm/sde: move power resource handling for vblank to crtcsClarence Ip2017-07-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the power resource request/release from the sde kms layer into the CRTCs so that proper accounting for suspend/resume operations may be done. A single power resource request is made as long while the CRTC's vblank request ref count is not zero and the driver is not in a suspended state. CRs-Fixed: 2019307 Change-Id: I2d47567ec3dded72faed8bd5441d8d4653d5ef25 Signed-off-by: Clarence Ip <cip@codeaurora.org>
| * | | | | | | drm/msm/sde: reset drm state on suspend/resumeClarence Ip2017-07-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Explicitly disable connector DPMS and CRTC active states on system suspend, and restore the previous state during a system resume. This allows the underlying drivers to trigger a DPMS callback for handling any panel related power disables while still preserving the DRM atomic state. CRs-Fixed: 2019307 Change-Id: Ib9933e4bc8b43c64def777b081d4315e5dbb7365 Signed-off-by: Clarence Ip <cip@codeaurora.org>
| * | | | | | | drm/msm/sde: allow forcing of kernel scaler calculationClarence Ip2017-07-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a debugfs entry to the planes to force the driver to ignore any custom scaler configuration from the user space. CRs-Fixed: 2019305 Change-Id: I98596a1aaa0629ca1bfe81ab5c01a0d7854859e3 Signed-off-by: Clarence Ip <cip@codeaurora.org>
| * | | | | | | drm/msm/sde: add null checks to scaler3 lut setupClarence Ip2017-07-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Plane state is set to NULL during color fill operations. This patch adds checks to gracefully handle NULL plane state during the scaler3 setup path. CRs-Fixed: 2019301 Change-Id: I3ac5bd8f26e68afe559bf7c815da904392d3de13 Signed-off-by: Clarence Ip <cip@codeaurora.org>
* | | | | | | | Merge "msm: sde: fix kernel booting failure in sde driver"Linux Build Service Account2017-07-28
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| * | | | | | msm: sde: fix kernel booting failure in sde driverGuchun Chen2017-07-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This issue is caused by change 1974734. With that change, kernel booting will fail in sde driver. [drm:sde_wb_drm_init:601] [sde error]invalid params [drm:_sde_kms_setup_displays:691] [sde error]wb bridge 0 init failed, -22 [drm:_sde_init_phy_plane:2663] [sde error][5]no valid formats for plane [drm:sde_plane_init:2746] [sde error]_sde_init_phy_plane error vp=0 [drm:_sde_kms_drm_obj_init:861] [sde error]sde_plane_init failed [drm:sde_kms_hw_init:1288] [sde error]modeset init failed: -22 msm_drm 900000.qcom,mdss_mdp: kms hw init failed: -22 sblk->format_list should be put back to _sde_sspp_setup_vig, _sde_sspp_setup_rgb, _sde_sspp_setup_cursor,_sde_sspp_setup_dma and sde_wb_parse_dt, otherwise, it will fail when populating the pixel format which pipe supported in sde_plane_init. Change-Id: I479886d7d7e676a10f8a26bd372aad847dd03163 Signed-off-by: Guchun Chen <guchunc@codeaurora.org>
* | | | | | | drm/msm: Turn off hardware clock gating before reading A5XX registersJordan Crouse2017-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On A5XX GPU hardware clock gating needs to be turned off before reading certain GPU registers via AHB. Turn off HWCG before calling adreno_show() to safely dump all the registers without a system hang. Change-Id: Ic0dedbad550ab5d414cea7837672e586a7acd370 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | | | | drm/msm: Remember the state of A5XX hardware clock gatingJordan Crouse2017-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remember if the A5XX hardware clock gating is currently enabled or disabled to avoid inadvertently enabling it. Change-Id: Ic0dedbada3734a257ac966c041d06695f3521ad4 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | | | | drm/msm: Keep the power on throughout the entire ->show() operationJordan Crouse2017-07-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling and disabling the power at various points in the ->show() call flow may have detrimental effects. For all targets make sure power is on before reading any register and leave it on until we are all done. Change-Id: Ic0dedbad4d37a11634174105fc3ee6fe3713a143 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | | | | drm/msm: Check value of active_cnt in a5xx power functionsJordan Crouse2017-07-24
| |_|/ / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic msm_gpu_pm_resume/msm_gpu_pm_suspend functions have built-in reference counting but the a5xx specific functions are doing unconditional a5xx specific setup / teardown that would behave very badly if they were not accompanied by an actual power up / power down. Change-Id: Ic0dedbad549c4ea9a5c68b0ca43eb98e0449d54b Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | | | Merge "drm/msm: add support for HDR playback control sequence"Linux Build Service Account2017-07-21
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| * | | | | drm/msm: add support for HDR playback control sequenceAbhinav Kumar2017-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HDR playback needs metadata to be sent to the sink while the playback is ongoing and needs a proper teardown sequence when the playback has ended with respect to the infoframe being sent to the sink. This needs a state machine to synchronize start/stop of the playback with sending the right metadata along with resetting the infoframe HDMI registers. Add support for this HDR playback control state machine. Change-Id: I229183531f7ccb48579e74d02e0a1dea1cb945ff Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
* | | | | | Merge "drm/msm: fix Y420CMDB EDID block parsing"Linux Build Service Account2017-07-17
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| * | | | | drm/msm: fix Y420CMDB EDID block parsingAbhinav Kumar2017-07-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the Y420CMDB EDID block parsing to handle the case where the block does not include a capability bitmap. This case means that all the short video descriptors support the YUV 420 mode as well. Also fix the incorrect length check in the parser API. The capability bitmap has no minimum length field. Change-Id: I5d9c2d3ac11d5ddad8e36cb7acfebfb41175f4b7 Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
* | | | | | drm/msm: add YUV format support for HDMIYuan Zhao2017-07-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds YUV format support for HDMI. Also, chooses the best mode for turning on the sink based on sink source capabilities. This can be either RGB or YUV. For YUV formats adjust the pixel clock and also configure the relevant hardware blocks in SDE. Change-Id: I48a36a991c194badb3ddca4bbf5bcbc21d838b8f Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
* | | | | | drm/msm: add RGB 30-bit deep color support for HDMIYuan Zhao2017-07-14
|/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check if the TV supports deep color and adjust the pixel clock accordingly before setting the mode. Also make sure that this pixel clock is within the limits of the sink. Change-Id: I3c44c06ea54b6c49e19c8c41d693000f7c3feeb7 Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
* | | | | Merge "drm/msm/sde: Expose the HDR support capability of the chipset"Linux Build Service Account2017-07-11
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| * | | | | drm/msm/sde: Expose the HDR support capability of the chipsetSrikanth Rajagopalan2017-07-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose HDR capability using a property to the userspace. This will help userspace to decide whether to invoke the HDR library and pass the relevant parameters to be sent to the sink. Change-Id: I3c4bf4d6c4e0f0babdf49b3c99baab42dcb2b5c0 Signed-off-by: Srikanth Rajagopalan <rasrik@codeaurora.org>
* | | | | | drm/msm: add input validation before setting HDR infoframeAbhinav Kumar2017-07-09
|/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the input validation for the connector's HDR support before calling the API to set the infoframe rather than within the API itself. This helps to avoid redundant checks and logging. Change-Id: If21562920edb1613a73b5e18ab258a57e46c1d7b Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
* | | | | Merge "drm/msm: add default value for plane enum property"Linux Build Service Account2017-07-06
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| * | | | | drm/msm: add default value for plane enum propertyJin Li2017-06-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add default value support for plane enum property which caller is able to pass in different default value when initialize the enum property list. Change-Id: I57595bf7c42b0e528a18ab0951655a169b00d611 Signed-off-by: Jin Li <jinl@codeaurora.org> Signed-off-by: Yunyun Cao <yunyunc@codeaurora.org>
* | | | | | Merge "drm/msm: Add timestamp counter"Linux Build Service Account2017-07-05
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| * | | | | drm/msm: Add timestamp counterJordan Crouse2017-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the confusion of adding the perfcounter API the timestamp query was broken. Convert the query over to the perfcounter API to avoid confusion. Change-Id: Ic0dedbad590489a643e8aa6d678bf19f732c06dd Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
| * | | | | drm/msm: Remove next_fenceJordan Crouse2017-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The next_fence array is left over from when we started storing per-ring information. Change-Id: Ic0dedbada687f899eca1017ecfd77fbd2aa8e114 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
| * | | | | drm/msm: Move hangcheck fence to ringbufferJordan Crouse2017-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hangcheck_fence was missed when all the ring specific members were moved out of the gpu struct. Change-Id: Ic0dedbad00a86d6657bc2a3e0e5bbdc5eae21ae6 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
| * | | | | drm/msm: Remove adreno_last_fenceJordan Crouse2017-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | adreno_last_fence is no longer very useful since we have a handy per-ring pointer directly to the values we need. Change-Id: Ic0dedbadfb195551afcd016651776965da32fb2d Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
| * | | | | drm/msm: Change the priority order of the ringbuffersJordan Crouse2017-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we first did preemption the priority was set at submission time. In order to be properly backwards compatible we made ring id 0 the lowest priority ring so that when a legacy app made a submission it didn't get itself onto the highest priority ring by accident. Now that we set the priority with submitqueues this is no longer a concern and ordering priorities this way goes against long standing convention in similar GPU drivers. Declare a flag day and invert the priority algorithm so that priority '0' is the highest priority and it descends from there. The lowest prority ring is 'number of rings - 1' where the number of active rings can be acquired through a parameter query of MSM_PARAM_NR_RINGS. This change also ensures that the legacy submitqueue id '0' will use the next-to-lowest ring buffer by default for legacy submissions. Change-Id: Ic0dedbadeea522e4f07babc4395cbf5fb7143fe3 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | | | Merge "drm/msm: add support for parsing YUV 420 deep color"Linux Build Service Account2017-07-04
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| * | | | | | drm/msm: add support for parsing YUV 420 deep colorAbhinav Kumar2017-06-30
| | |/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current upstream parser only handles RGB deep color modes. Add support in the SDE EDID parser module to parse HDMI VSDB block and indicate support for YUV 420 deep color modes in the sink. Change-Id: If6c007263094e7716a29cae503d3e3471ae04306 Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
* | | | | | Merge "drm/msm/sde: remove extra entries from interrupt table"Linux Build Service Account2017-07-04
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| * | | | | drm/msm/sde: remove extra entries from interrupt tableAlan Kwong2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Four extra reserved entries are allocated in 88-91. These entries do not affect lookup logics but are conflicting with index listed in the documentation. Remove these extra reserved entries to match index with documentation. Change-Id: Id9e3a35e9bee9d13b479d7ef65dca1912ea1ff80 Signed-off-by: Alan Kwong <akwong@codeaurora.org>
| * | | | | drm/msm/sde: correct index lookup for interrupt clear registerAlan Kwong2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Interrupt get status function incorrectly uses interrupt index to lookup clear register offset. Correct get status function to use register index instead to lookup up interrupt offset register. CRs-Fixed: 2053107 Change-Id: I0c298e0b2b2cbc19758ff84be35ba2d2ce52aeb3 Signed-off-by: Alan Kwong <akwong@codeaurora.org>
| * | | | | drm/msm/sde: correct out of bound access in catalogAlan Kwong2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct validate function to use proper size clearing property count array. Correct copy format function to check bound before accessing array element. CRs-Fixed: 2037027 Change-Id: Ied3a8e91eb4e6c2c19632b8f83b35d94d1773bb1 Signed-off-by: Alan Kwong <akwong@codeaurora.org>
| * | | | | drm/msm: add proper termination to device match arrayAlan Kwong2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Device match array should be terminated with a null entry. Add this null entry to mdp version check to avoid check past end of array. CRs-Fixed: 2037027 Change-Id: Ib313fad468205e94eace94eee9db56f19f61ab0c Signed-off-by: Alan Kwong <akwong@codeaurora.org>
| * | | | | drm/msm/sde: use current encoders to determine crtc interfaceAlan Kwong2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using the cached interface type, which is updated during fence preparation time, determine interface type by enumerating over all matching encoders and query the interface directly. This avoids pontential stale interface types due to changing connector state. CRs-Fixed: 2009714 Change-Id: I31e1350cc62cafb5f014c0f32514d0692dec42d0 Signed-off-by: Alan Kwong <akwong@codeaurora.org>
| * | | | | drm/msm/sde: add support for a5x tile pixel formatsAlan Kwong2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new modifier for a5x tile and support for a5x tile pixel format layout calculation. CRs-Fixed: 2009714 Change-Id: If0d1d6ba8d8d3e36dd5d5aef4a9b217d8e5779ba Signed-off-by: Alan Kwong <akwong@codeaurora.org>
| * | | | | drm/msm/sde: move cdm csc setup to writeback commitAlan Kwong2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CDM CSC is currently only initialized during power up. But on power collapse, CSC will be reset and produce incorrect YUV writeback output. Correct this by moving CSC setup to writeback commit to ensure CSC is always up-to-date. Change-Id: Iac004316c32040f83ef582aae83b02e1288514b1 Signed-off-by: Alan Kwong <akwong@codeaurora.org>
| * | | | | drm/msm/sde: correct clamp shift for csc 10Alan Kwong2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clamp shift for csc 10 is 16 bit where csc 8 is 8 bit. Correct csc to apply proper clamp shift based on csc version. Change-Id: I34d30127384668f4cb222a6e634e6581c0054805 Signed-off-by: Alan Kwong <akwong@codeaurora.org>
* | | | | | drm/msm: Add a parameter query for the number of ringbuffersJordan Crouse2017-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to manage ringbuffer priority to its fullest userspace should know how many ringbuffers it has to work with. Add a parameter to return the number of active rings. Change-Id: Ic0dedbada6010dd5122e8409141fd23b414d73e4 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | | | drm/msm: Change the profiling structureJordan Crouse2017-07-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the queued time from the profile struct and turn the submit time into a proper timespec (tv_sec + tv_nsec). This should sync up better with what userspace is used to seeing. Change-Id: Ic0dedbad0621fa248e6cffde2d1ee3f9b609e19d Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | | | drm/msm: Add kernel side submit profiling and tracingJordan Crouse2017-07-03
| |/ / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Record the GPU always on timer value at the start and end of a submission on the ringbuffer. Since the timer runs at a constant 19.2 Mhz this is a handy way of tracking how long each submission takes. The timer values are recorded in the memptrs. Each ringbuffer is given a circular list of 128 entries to store the event ticks; this should be enough to avoid running out of room even when the ring is completely full of submissions. Add trace events for the user to track when submissions are queued, submitted to the ringbuffer and retired. The submitted trace point shows the GPU ticks and the current kernel time at submit time (as read by the CPU) and the retired trace event shows the GPU ticks at submission start/end as read by the GPU. Taken together these two events can provide a pretty close match between the current GPU time and the kernel time which is handy for tracing tools that try to match up the various kernel events with one another. Change-Id: Ic0dedbadbcf89f032890820785b9fb49a6362b01 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | | Merge "drm/msm/sde: add kernel traces to measure enable/disable/kickoff times"Linux Build Service Account2017-06-28
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| * | | | | drm/msm/sde: add kernel traces to measure enable/disable/kickoff timesNarendra Muppalla2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add kernel debug traces in drm to measure the performance of the driver during enable/disable/commit/kickoff. Change-Id: I7122e81b2c320f05bb42091971827908b7c6436f Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
* | | | | | Merge "drm/msm: program hdr information to HDMI registers"Linux Build Service Account2017-06-28
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| * | | | | | drm/msm: program hdr information to HDMI registersAbhinav Kumar2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HDR metadata information is passed down from userspace based on the HDR frame. Program these properties to relevant HDMI registers using the pre_kickoff callback registered for the DRM HDMI connector. This ensures that HDR information is updated on a per-frame basis to the sink. Change-Id: I20c4018316329b1b35a11b8ab4b96e923b3abb3a Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-07-18 05:40:42 +0000