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* | clk: mdss: add pll common block register settings for pll 1Huaibin Yang2016-03-23
| | | | | | | | | | | | | | | | One subset of pll common block setting registers need to be programmed for both pll 0 and pll 1 to prevent current leakage. Change-Id: I1ba621f21b49e0e55c3840b281ca9323130465a2 Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
* | clk: mdss: add delay for new pll locking sequenceHuaibin Yang2016-03-23
| | | | | | | | | | | | | | This change is corresponding to the update from h/w documentation. Change-Id: I74ac06ce0cd1b0a8b52be6fa7dab123ebb2fc79e Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
* | clk: mdss: implement new pll re-locking sequenceHuaibin Yang2016-03-23
| | | | | | | | | | | | | | | | | | The new sequence is intended to improve pll locking time. This patch is to implement locking pll using stored codes and bypassing calibration. Change-Id: I1a26843b5d784984dff4fee0e17841cfc1be37cc Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
* | iopoll: unify atomic and non-atomic interfacesMitchel Humpherys2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | readl_poll_timeout and readl_poll_timeout_atomic really accomplish the same thing, just in different contexts. Unify their interfaces to reduce cognitive load on developers and code reviewers. Change-Id: I319db7cb3894c66447b3337c6802b723a38b3544 [veeras@codeaurora.org: As part of 3.18 upgrade, remove all non-display-related code from this commit arch/arm/mach-msm/clock-mdss-8974.c drivers/iommu/arm-smmu.c include/linux/iopoll.h] Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org> Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
* | clk: qcom: mdss: add support for HDMI pll on thuliumVinu Deokaran2016-03-23
| | | | | | | | | | | | | | | | Added support for new HDMI pll present on thulium. Implemented dynamic calculator for pll settings. Change-Id: Ib0b728d9ffb44b753657292e387ee7b44e854122 Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
* | clk: mdss: implement new pll locking sequenceHuaibin Yang2016-03-23
| | | | | | | | | | | | | | | | | | | | The new sequence is intended to improve pll locking time. This patch is part of new sequence in pll driver side. Change-Id: I09760d52db12deda0c0b4bf700db301cde8a05f1 Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org> [imaund@codeaurora.org: Resolved context conflicts] Signed-off-by: Ian Maund <imaund@codeaurora.org>
* | clk: qcom: mdss: add 20nm hdmi pll support for msm8992Casey Piper2016-03-23
| | | | | | | | | | | | | | | | Parse HDMI PLL string for msm8992 to set the PLL interface type to 20nm HDMI PLL. Change-Id: I7fe187148395d530871dd85ccd59f0645f894096 Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | clk: qcom: mdss: Add 8992 to 20nm pll supported devicesJeykumar Sankaran2016-03-23
| | | | | | | | | | | | | | | | | | | | | | Add 8992 to 20nm pll supported devices. Change-Id: Ic5ca0dc72b83da7a559cfbad1c748b25d1542919 [veeras@codeaurora.org: As part of 3.18 upgrade, remove all non-display related code changes from the commit include/dt-bindings/clock/msm-clocks-8992.h] Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
* | clk: qcom: mdss: hdmi: increase delays to fix 20nm PLL lock failuresCasey Piper2016-03-23
| | | | | | | | | | | | | | | | Introduce minor delays in HDMI PHY sequence to ensure that PHY is ready before failing with a timeout. Change-Id: I8e9adf542b60e63c0c28d314afd5ac61fa64d1b2 Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | clk: qcom: mdss: fix device crash on continuous splash disabledVeera Sundaram Sankaran2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | TZ introduced a recent change which mandates the scm call before accessing the pll registers. So, when continuous splash is disabledin bootloader, the scm call is not made and it causes device crash when the pll driver tries to access the registers. This change makes it return with a disabled handoff clk from the pll driver when continuous splash is disabled, thus not accessing the pll registers at this point. Change-Id: Ic487ef733f889d463d149ee347667cd8eb04084f Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
* | clk: qcom: mdss: update PLL VCO frequency range to change clock phaseChandan Uddaraju2016-03-23
| | | | | | | | | | | | | | | | | | Change the VCO frequency range to avoid display fading issues. Add code to change the PLL dividers to match the new VCO frequency range. Change-Id: Iec62f6be26d47cdfd8b2acb895f2e80d57164833 Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* | clk: qcom: mdss: add support for HDMI autopll calculationsCasey Piper2016-03-23
| | | | | | | | | | | | | | | | | | Automatically calculate the register values needed for HDMI PLL based on the pixel clock. Change-Id: I6fbe519e0316c3f9cc12cd0afd5aa08a90deed7d Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | iopoll: remove overly-helpful helper macros, clarify namingMitchel Humpherys2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the macros in iopoll.h might be a tad verbose or redundant. Several of the "verbose" macros are not used anywhere in the kernel. Based on feedback from upstream, rip out the extra "wrapper" macros and convert callers (if any) to the lower-level ones. Also change the `_noirq' suffix to the more idiomatic `_atomic'. The following semantic patch was used to help identify and make the necessary changes: @@ expression addr, val, cond, timeout_us; @@ - readl_tight_poll_timeout(addr, val, cond, timeout_us) + readl_poll_timeout(addr, val, cond, 0, timeout_us) @@ expression addr, val, cond, max_reads, time_between_us; @@ - readl_poll_timeout_noirq(addr, val, cond, max_reads, time_between_us) + readl_poll_timeout_atomic(addr, val, cond, max_reads, time_between_us) Change-Id: Ibdb054ded59d777f38f594a2f09a12c64abdb059 [veeras@codeaurora.org: As part of 3.18 upgrade, removing all non-display related code from this commit. arch/arm/mach-msm/clock-mdss-8974.c drivers/clk/msm/gdsc.c drivers/iommu/msm_iommu-v1.c include/linux/iopoll.h] Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
* | clk: qcom: mdss: add DSI PLL clock driver support for msm8909Shivaraj Shetty2016-03-23
| | | | | | | | | | | | | | | | | | | | Add changes for DSI PLL clock driver support for msm8909. Add the compatibility string of the DSI PLL handle so that the detection and support of DSI PLL driver for 8909 happens dynamically. Change-Id: If1fb96982433f90c5b82dda8686b7284825bcd09 Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
* | clk: qcom: mdss: Reduce delays in HDMI clock enableCasey Piper2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Reducing delays in HDMI clock enable to prevent the thread from being held in the realtime process and hogging the CPU. Updated delays are provided after further hardware testing. With the added microsecond delay in the timout loop, C and PHY ready should occur well before timeout. Change-Id: Ib36a06e5309f3f8ba9e4013d08ca2ed108457beb Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | clk: msm: mdss: Add support for DSI PLL 1 clock registrationSiddhartha Agrawal2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | Setup DSI 1 PLL clock heirarchy. This is needed for instances where we need to turn off the second pll in case of current leak issue. Change-Id: I694af1fa9591b2345709687c9e7b1d69f15b56a9 [veeras@codeaurora.org: As part of 3.18 upgrade, removing changes in include/dt-bindings/clock/msm-clocks-8994.h from this gerrit] Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org> Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
* | clk: mdss: shutdown 20nm PHY pll properly to fix power issueSiddhartha Agrawal2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | The second DSI PLL is consuming power when it is in reset state. Configure the needed registers to shutdown the second DSI PLL properly even though its not been used. Add these register configurations whenever mdss gdsc is toggled. Change-Id: I008bc102795ccb5991bf4b61545c2d672b453392 Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
* | clk: qcom: mdss: init mdss pll driver at subsys levelDhaval Patel2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Boot loader enables resources for continuous splash screen feature and leaves it on when kernel boot up. MDSS PLL driver adds vote for for these resources in kernel. Some other driver can also request same resources and disables it in failure case. This will fade out splash image on screen. Initializing pll driver at subsystem level adds vote for resources at early stage. Change-Id: Icb80c73e185461a49f682a80ab0578883640e803 Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
* | clk: mdss: add software mux for byte and pixel source clocksJeevan Shriram2016-03-23
| | | | | | | | | | | | | | | | | | Implement the software mux to byte clock and pixel source clock with shadow implementation of PLL clock. This is used for configuring the dynamic refresh pll registers. Change-Id: I9c84cb76d040c5df7361291b6e1fc0fe69dc214f Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
* | clk: mdss: parse the dynamic refresh register baseJeevan Shriram2016-03-23
| | | | | | | | | | | | | | | | Add support for parsing dynamic refresh register base for register programming. Change-Id: I0f23f3c6c01e2ef47fec5048ae0c8ebf31566b61 Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
* | clk: mdss-edp-pll: Fix possible null dereferenceVeera Sundaram Sankaran2016-03-23
| | | | | | | | | | | | | | Fixed null dereferencing in mdss clk Change-Id: I786fdc04ca605ccbf2dda5565968bee08ce031e5 Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
* | clk: mdss-dsi-pll: add support for auto PLL calculator for 20nm PHYChandan Uddaraju2016-03-23
| | | | | | | | | | | | | | | | | | | | Add code to support DSI auto PLL calculator for 8994 platform that uses 20nm physical layer. Update the PLL configuration and DSI PHY regulator configurations to the recommended settings. Change-Id: Ia3d7042d537539491317f99d7bcc2c480f850216 Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* | clk: qcom: mdss: add PLL clock support for 20nm HDMI PHYCasey Piper2016-03-23
| | | | | | | | | | | | | | | | | | | | | | Add support for HDMI PLL on msm8994. Support is added to register this new clock driver. Also modify makefile to compile new 20nm PLL source and add support for registering PLL clock driver for 20nm HDMI PHY. Change-Id: I57421ac638075358c46ddd938e441a8e525f3a5a Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* | clk: qcom: mdss: fix debug clock names for DSI PLL on msm8994Chandan Uddaraju2016-03-23
| | | | | | | | | | | | | | | | Fix the debug clock names to match with proper clocks for msm8994. These clocks are part of 20nm PHY PLL configuration. Change-Id: I709d6df80330702304b91d76ec2cad0a7f494c1e Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* | clk: qcom: mdss: add mdss 20nm pll clock driver supportChandan Uddaraju2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for new 20nm PLL clock driver to handle different DSI panel resolutions. Add seperate files to support this new 20nm PHY PLL block. Change-Id: I4ee5309449f317daddba7106cb8e1829fd6e76cf [veeras@codeaurora.org: As part of the 3.18 upgrade, removing all the msm/mdss display related changes from this commit as it was already updated during that msm/mdss folder update] Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org> Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
* | clk: qcom: mdss: add DSI PLL clock driver support for msm8939Padmanabhan Komanduru2016-03-23
| | | | | | | | | | | | | | | | | | | | This change adds the DSI PLL clock driver support for msm8939. Add the compatibility string of the DSI PLL handle so that the detection and support of DSI PLL driver for 8939 happens dynamically. Change-Id: Iaa4be3541ce938816d5b9552b685ce05e7cdab64 Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* | clk: qcom: mdss: update PLL resources based on ref countPadmanabhan Komanduru2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | At present, the PLL resources are updated based on the enable/disable parameter that is passed to the API. Add support to update the PLL resources based on a ref count. This avoids additional delay due to repeated enable/disable of the resources and also maintains proper state of the PLL resources. Change-Id: I39b7ee2b33acb81acdb7dc1f4f387dc71381a464 Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* | clk: qcom: mdss: split the DSI PLL driver based on PLL modePadmanabhan Komanduru2016-03-23
| | | | | | | | | | | | | | | | | | | | Re-organize the DSI PLL driver code and split it based on the DSI PLL HPM/LPM mode. Add a common PLL util file to use the APIs which are common for both PLLs. Update the DSI PLL enable sequence with the recommended settings for LPM mode. Change-Id: I3f86554522e16579d5c2eccab976136c7afb0dd2 Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* | clk: qcom: mdss: Increase both edp pll's PPM and idle time settingKuogee Hsieh2016-03-23
| | | | | | | | | | | | | | | | | | Increase both edp pll's PPM and idle time setting to fix edp pll unlock problem during stress test. CRs-Fixed: 614017 Change-Id: Ic8315fc77dd002e709a9b215b22cbf498edaf30b Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
* | clk: qcom: mdss: update resource management in PLL driverPadmanabhan Komanduru2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Remove mutex and ref count variables that synchronize the resource enable and disable calls since the regulator and clock drivers take care of maintaining the ref count for each resource. Also, remove resource enable and disable calls from mux_set_rate/mux_get_rate/clk_enable context of the DSI branch clocks to avoid warnings. Change-Id: Ieb32141156afcce008b3555af476c20f888f064b Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* | clk: qcom: mdss: add DSI PLL clock driver support for 8916Padmanabhan Komanduru2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | This change adds the DSI PLL clock driver support for 8916. In addition, it adds support of DSI PLL programming of different MDSS revisions using the same DSI PLL driver. Also rename the compatibility string of the DSI PLL handle so that the detection and support of DSI PLL driver for 8974 and 8916 happens dynamically. Change-Id: I169ebeaf23e4be8ff4b533fce1057144edd8b692 Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* | clk: qcom: mdss: Do not include msm_iomap header fileDhaval Patel2016-03-23
| | | | | | | | | | | | | | | | Do not include msm_iomap header file because MDSS pll driver is not using it. Change-Id: Ibe47a7d643bd6c9c5e0a69aad1ff0cc44da09211 Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
* | clk: qcom: mdss: Fix MDSS HDMI pll supportDhaval Patel2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | PHY registers are not updated during MDSS HDMI pll configuration due to wrong memory mapping. It also leads to crash when user connects the HDMI cable with target. This change fixes the memory mapping for PHY and also adds the missing register configuration entry for HDMI pll. Change-Id: Ie81045fed320993fbab6b02bec6b2b82e5b5d495 Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
* | clk: qcom: mdss: Add mdss pll clock driver supportDhaval Patel2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | Each display output interface such as eDP, HDMI and DSI are clocked by different pll clocks to support various displays at different resolution simultaneously. The mdss pll driver handles all these display output interfaces' pll clocks separately. It also handles their resources through dtsi configuration. Change-Id: I1de2ae9a0549de901a6c82ea489199a722344dc4 Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
* | clk: msm: clock: Add support for MSM8996/COBALT clock treeTaniya Das2016-03-01
| | | | | | | | | | | | | | | | Add clock tree support for MSM8996 and MSMCOBALT, and add corresponding dt bindings header files. Change-Id: If0281f96ce5dd29b04f190efa1527888bc240bb5 Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: msm: Add support for MSM clocksTaniya Das2016-03-01
|/ | | | | | | | Support added for MSM clock and modifications in the clk framework to use the MSM clock framework. Change-Id: Ibbcf0ffbf9d30dde2dcb0e943225ad95dd4e857d Signed-off-by: Taniya Das <tdas@codeaurora.org>
* Merge tag 'fixes-for-linus' of ↵Linus Torvalds2015-12-12
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Arnd Bergmann: "Here are a bunch of small bug fixes for various ARM platforms, nothing really sticks out this week, most of either fixes bugs in code that was just added in 4.4, or that has been broken for many years without anyone noticing. at91/sama5d2: - fix sama5de hardware setup of sd/mmc interface - proper selection of pinctrl drivers. PIO4 is necessary for sama5d2 berlin: - fix incorrect clock input for SDIO exynos: - Fix potential NULL pointer dereference in Exynos PMU driver. imx: - Fix vf610 SAI clock configuration bug which is discovered by the newly added master mode support in SAI audio driver. - Fix buggy L2 cache latency values in vf610 device trees, which may cause system hang when cpu runs at a higher frequency. ixp4xx: - fix prototypes for readl/writel functions ls2080a: - use little-endian register access for GPIO and SDHCI omap: - Fix clock source for ARM TWD and global timers on am437x - Always select REGULATOR_FIXED_VOLTAGE for omap2+ instead of when MACH_OMAP3_PANDORA is selected - Fix SPI DMA handles for dm816x as only some were mapped - Fix up mbox cells for dm816x to make mailbox usable pxa: - use PWM lookup table for all ezx machines s3c24xx: - Remove incorrect __init annotation from s3c24xx cpufreq driver structures. versatile: - fix PCI IRQ mapping on Versatile PB" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ls2080a/dts: Add little endian property for GPIO IP block dt-bindings: define little-endian property for QorIQ GPIO ARM64: dts: ls2080a: fix eSDHC endianness ARM: dts: vf610: use reset values for L2 cache latencies ARM: pxa: use PWM lookup table for all machines ARM: dts: berlin: add 2nd clock for BG2Q sdhci0 and sdhci1 ARM: dts: berlin: correct BG2Q's sdhci2 2nd clock ARM: dts: am4372: fix clock source for arm twd and global timers ARM: at91: fix pinctrl driver selection ARM: at91/dt: add always-on to 1.8V regulator ARM: dts: vf610: fix clock definition for SAI2 ARM: imx: clk-vf610: fix SAI clock tree ARM: ixp4xx: fix read{b,w,l} return types irqchip/versatile-fpga: Fix PCI IRQ mapping on Versatile PB ARM: OMAP2+: enable REGULATOR_FIXED_VOLTAGE ARM: dts: add dm816x missing spi DT dma handles ARM: dts: add dm816x missing #mbox-cells cpufreq: s3c24xx: Do not mark s3c2410_plls_add as __init ARM: EXYNOS: Fix potential NULL pointer access in exynos_sys_powerdown_conf
| * ARM: imx: clk-vf610: fix SAI clock treeStefan Agner2015-12-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Synchronous Audio Interface (SAI) instances are clocked by independent clocks: The bus clock and the audio clock (as shown in Figure 51-1 in the Vybrid Reference Manual). The clock gates in CCGR0/CCGR1 for SAI0 through SAI3 are bus clock gates, as access tests to the registers with/without gating those clocks have shown. The audio clock is gated by the SAIx_EN gates in CCM_CSCDR1, followed by a clock divider (SAIx_DIV). Currently, the parent of the bus clock gates has been assigned to SAIx_DIV, which is not involved in the bus clock path for the SAI instances (see chapter 9.10.12, SAI clocking in the Vybrid Reference Manual). Fix this by define the parent clock of VF610_CLK_SAIx to be the bus clock. If the driver needs the audio clock (when used in master mode), a fixed device tree is required which assign the audio clock properly to VF610_CLK_SAIx_DIV. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk: sunxi: pll2: Fix clock running too fastMaxime Ripard2015-12-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Contrary to what the datasheet says, the pre divider doesn't seem to be incremented by one in the PLL2, but just uses the value from the register, with 0 being a bypass. This fixes the audio playing too fast. Since we now have the same pre-divider flags, and the only difference with the A10 is the post-divider offset, also remove the structure to just pass the offset as an argument. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Fixes: eb662f854710 ("clk: sunxi: pll2: Add A13 support") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: scpi: add missing of_node_putJulia Lawall2015-11-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for_each_available_child_of_node performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. The semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ expression root,e; local idexpression child; @@ for_each_available_child_of_node(root, child) { ... when != of_node_put(child) when != e = child ( return child; | + of_node_put(child); ? return ...; ) ... } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qoriq: fix memory leakSudip Mukherjee2015-11-30
| | | | | | | | | | | | | | | | | | If get_pll_div() fails we exited by returning NULL but we missed releasing hwc. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Fixes: 0dfc86b3173f ("clk: qoriq: Move chip-specific knowledge into driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | imx/clk-pllv2: fix wrong do_div() usageNicolas Pitre2015-11-30
| | | | | | | | | | | | | | | | do_div() is meant to be used with an unsigned dividend. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | imx/clk-pllv1: fix wrong do_div() usageNicolas Pitre2015-11-30
| | | | | | | | | | | | | | | | do_div() is meant to be used with an unsigned dividend. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge branch 'for-4.4-rc/ti-clk-fixes' of ↵Stephen Boyd2015-11-30
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/t-kristo/linux-pm into clk-fixes Pull TI clock driver fixes from Tero Kristo: * 'for-4.4-rc/ti-clk-fixes' of https://github.com/t-kristo/linux-pm: clk: ti: drop locking code from mux/divider drivers clk: ti816x: Add missing dmtimer clkdev entries clk: ti: fapll: fix wrong do_div() usage clk: ti: clkt_dpll: fix wrong do_div() usage
| * | clk: ti: drop locking code from mux/divider driversGrygorii Strashko2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TI's mux and divider clock drivers do not require locking and they do not initialize internal spinlocks. This code was occasionally copy-posted from generic mux/divider drivers. So remove it. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * | clk: ti816x: Add missing dmtimer clkdev entriesNeil Armstrong2015-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing clkdev dmtimer related entries for dm816x. 32Khz and ext sources were missing. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Cc: Brian Hutchinson <b.hutchman@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * | clk: ti: fapll: fix wrong do_div() usageNicolas Pitre2015-11-24
| | | | | | | | | | | | | | | | | | | | | do_div() is meant to be used with an unsigned dividend. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * | clk: ti: clkt_dpll: fix wrong do_div() usageNicolas Pitre2015-11-24
| |/ | | | | | | | | | | | | do_div() is meant to be used with an unsigned dividend. Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* | clk: mmp: add linux/clk.h includesArnd Bergmann2015-11-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The common clk implementation for MMP broke without anyone noticing when we stopped including linux/clk.h from the clk-provider header. This did not show up in the defconfig builds because those use the legacy MMP clk drivers, and it did not show up in my randconfig tests either because I was testing with my mmp multiplatform series applied, which at some point gained the fixup. This fixes the three broken files. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 61ae76563ec3 ("clk: Remove clk.h from clk-provider.h") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: gpio: Get parent clk names in of_gpio_clk_setup()Jyri Sarha2015-11-18
|/ | | | | | | | | | | | | | Get parent clk names in of_gpio_clk_setup() and store the names in struct clk_gpio_delayed_register_data instead of doing it from the clk provider's get() callback. of_clk_get_parent_name() can't be called in struct of_clk_provider's get() callback since it may make a call to of_clk_get_from_provider() and this in turn tries to recursively lock of_clk_mutex. Signed-off-by: Jyri Sarha <jsarha@ti.com> Cc: Sergej Sawazki <ce3a@gmx.de> Fixes: 0a4807c2f9a4 ("clk: Make of_clk_get_parent_name() robust with #clock-cells = 1") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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