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* | clk: msm: clock: Add support for programming MDP_LUT_CBCR registerDeepak Katragadda2016-06-20
| | | | | | | | | | | | | | | | | | | | | | Add support for the mdss_mdp_lut_clk clock on MSMCOBALT. In addition, remove toggling the memory retention bits for the mdp core clock during gdsc_enable/disable. The display driver will use the set_flags API to set the core clock memory retention. CRs-Fixed: 1025605 Change-Id: If812473a67a7900c8f7b8b97f32fbf003f0e80a4 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: qcom: Add KPSS ACC/GCC driverStephen Boyd2016-06-17
| | | | | | | | | | | | | | | | | | | | | | | | The ACC and GCC regions present in KPSSv1 contain registers to control clocks and power to each Krait CPU and L2. For CPUfreq purposes probe these devices and expose a mux clock that chooses between PXO and PLL8. Change-Id: Icaa1b68652eb4c836e8aacad80ff6cebe34cad4f Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: Add support for Krait clocksStephen Boyd2016-06-17
| | | | | | | | | | | | | | | | | | | | | | | | The Krait clocks are made up of a series of muxes and a divider that choose between a fixed rate clock and dedicated HFPLLs for each CPU. Instead of using mmio accesses to remux parents, the Krait implementation exposes the remux control via cp15 registers. Support these clocks. Change-Id: Ic720d45d8c78e6c5a901e58ec6fd23fa15302a21 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: Add support for High-Frequency PLLs (HFPLLs)Stephen Boyd2016-06-17
| | | | | | | | | | | | | | | | | | HFPLLs are the main frequency source for Krait CPU clocks. Add support for changing the rate of these PLLs. Change-Id: I53cb4364e84d108f4fc211ca5524ca25d569997c Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: Add HFPLL driverStephen Boyd2016-06-17
| | | | | | | | | | | | | | | | | | | | | | | | On some devices (MSM8974 for example), the HFPLLs are instantiated within the Krait processor subsystem as separate register regions. Add a driver for these PLLs so that we can provide HFPLL clocks for use by the system. Change-Id: If8a3e492e1c227cbf42f4f9907cdcb0dcb3ccc11 Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: gdsc: Add the missing BIMC gdsc for msm8996Rajendra Nayak2016-06-17
| | | | | | | | | | | | | | | | Add BIMC gdsc data found in MMCC part of msm8996 family of devices. Change-Id: Ibeac134f941f402bcad8e803bdb73ba73f55909d Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: gdsc: Add mmcc gdscs for msm8996 familyRajendra Nayak2016-06-17
| | | | | | | | | | | | | | | | | | Add all gdsc data which are part of mmcc on msm8996 family Change-Id: I77caf8f26bf676a7553b6873eb188acb02a9c44d Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driverStephen Boyd2016-06-17
| | | | | | | | | | | | | | | | | | | | Add a driver for the multimedia clock controller found on MSM8996 based devices. This should allow most multimedia device drivers to probe and control their clocks. Change-Id: I0b69b1e78a8b0faeaff3e5c87c73e24b1c19ba55 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
* | clk: qcom: gcc-msm8996: Add missing BCR for USB3 and PCIE clocksAmit Nischal2016-06-16
| | | | | | | | | | | | | | | | The block reset registers for USB3 and PCIE will be required by the clients to reset their subsystem blocks so add them in the reset map. Change-Id: Ie30158592fca057454152f3f46a5d8b89ae36b88 Signed-off-by: Amit Nischal <anischal@codeaurora.org>
* | clk: msm: clock: Include logic to treat votable clocks/GDSCs differentlyDeepak Katragadda2016-06-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On MSMCOBALT, the votable GDSCs might take longer to enable/disable depending on a number of factors including if another entity outside of HLOS tried disabling the GDSC at the same time that HLOS tried to enable it. Add a higher polling timeout to accommodate this. In addition, add flags to branch clocks which might be controlled via the voting registers so that the driver does not print out a warning if these clocks do not turn off even after removing the SW vote. CRs-Fixed: 1027807 Change-Id: I044ca5209c364d4bfb4f3bd504cdcb87021fd010 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: hdmi: add cobalt hdmi pll calculator and clocksAjay Singh Parmar2016-06-09
| | | | | | | | | | | | | | | | | | | | Add PLL and PHY programming for HDMI. Dynamically calculate the register values to be programmed for a given pixel clock. CRs-Fixed: 1022772 Change-Id: Ibf7877eb6edd29baefee57bc12188989d897d47e Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org> Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
* | clk: msm: clock: Add support for programming the GCC_GPU_IREF_EN registerDeepak Katragadda2016-06-07
| | | | | | | | | | | | | | | | | | | | Add a new gcc_gpu_iref_clk that the graphics driver can control as needed. The default state of the clock is ON; so having this control will mean saving current. CRs-Fixed: 1024948 Change-Id: I562bb546f49b1605f20fb7d705f40584d190230b Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: qcom: Remove CLK_IS_ROOTStephen Boyd2016-06-07
| | | | | | | | | | | | | | | | This flag is a no-op now. Remove usage of the flag. Change-Id: I8b44c2b2b5928f3bc9ecd9f67dc014fb3bfb13df Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: gdsc: Add support for hierarchical power domainsRajendra Nayak2016-06-07
| | | | | | | | | | | | | | | | | | | | Some qcom SoCs' can have hierarchical power domains. Let the gdsc structs specify the parents (if any) and the driver add genpd subdomains for them. Change-Id: Id7faa0b6531ec787484ab17204a524858e6375dd Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: common: check for failureSudip Mukherjee2016-06-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We were not checking the return from devm_add_action() which can fail. Start using the helper and devm_add_action_or_reset() and return directly as we know that the cleanup has been done by this helper. Change-Id: Ie0bb9fed36484bc65b09905bda6b248a17ae2964 (cherry picked from commit 66f5ce2538e06dd6d628e37bbd38c79631274c9f) Git-commit: 66f5ce2538e06dd6d628e37bbd38c79631274c9f Git-repo: https://git.linaro.org/landing-teams/working/qualcomm/kernel.git Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: common: Add API to register board clocks backwards compatiblyStephen Boyd2016-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | | We want to put the XO board clocks into the dt files, but we also need to be backwards compatible with an older dtb. Add an API to the common code to do this. This also makes a place for us to handle the case when the RPM clock driver is enabled and we don't want to register the fixed factor clock. Change-Id: Ie06e1bb4e6add624787faf0372bafdf0b1126d1c Cc: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: qcom: gdsc: Add GDSCs in msm8996 GCCRajendra Nayak2016-06-06
| | | | | | | | | | | | | | | | | | Add all data for the GDSCs which are part of msm8996 GCC block Change-Id: I12323575c44b1a3ba4cb2764a498480b3e62dcaa Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: msm: clock-gcc-cobalt: Add the cnoc_periph RPM resource supportDeepak Katragadda2016-06-02
| | | | | | | | | | | | | | | | | | | | Add support for modelling a new cnoc_periph RPM resource on MSM COBALT. In addition, fix the rpm_res_type being used for the mmssnoc_axi_clk and remove the pnoc resource support. CRs-Fixed: 1003213 Change-Id: I9f9845fea425fc4463dae72e8f8ab6e8bda23121 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-mmss-8996: Add graphics clocks support on msm8996 ProDeepak Katragadda2016-06-02
| | | | | | | | | | | | | | | | | | | | The graphics clock frequencies need to be updated for msm8996 Pro. Add support for doing the same using the bin fuse values. CRs-Fixed: 1022663 Change-Id: I60185482ae9b5364e297370593d95cce056b314e Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: osm: increase unstall timer for PC/RET FSM to 5 usOsvaldo Banuelos2016-06-02
| | | | | | | | | | | | | | | | | | | | Increase the power-collapse and retention FSM exit unstall timer to 5 us. This timer is used to wait after a core asserts its request to exit PC or RET. Change-Id: Icb5c5f219a197a158e00f600e68111ff699062b7 CRs-Fixed: 1023187 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* | clk: msm: osm: increase main PLL minimum L_VAL to 825.6 MHzOsvaldo Banuelos2016-06-02
| | | | | | | | | | | | | | | | | | | | Increase miniumum PLL frequency to 825.6 MHz. This is necessary to ensure stable operation when OSM engages the droop path to the PLL. Change-Id: Ide3309d4dc713892703e2eb5ee33c9db7f990156 CRs-Fixed: 1021593 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* | clk: msm: clock: Support graphics clocks on MSMCOBALT v2Deepak Katragadda2016-06-01
| | | | | | | | | | | | | | | | | | Add support for controlling the graphics clocks on MSMCOBALT v2. CRs-Fixed: 1015446 Change-Id: Ia94606113b112a5e363e342a0ad1d977a48b3d72 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock: Support multimedia clocks on MSMCOBALT v2Deepak Katragadda2016-06-01
| | | | | | | | | | | | | | | | | | Add support for controlling the multimedia clocks on MSMCOBALT v2. CRs-Fixed: 1015446 Change-Id: I636001ea91e7be1e2adec2ea7cd3d9aadfcc39a2 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: qcom: Add MSM8996 Global Clock Control (GCC) driverStephen Boyd2016-06-01
| | | | | | | | | | | | | | | | | | | | Add support for the global clock controller found on MSM8996 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Change-Id: I559f5976b56bf8933df2c68fc4e29b2bd0ce1160 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Taniya Das <tdas@codeaurora.org>
* | clk: msm: mdss: fix DP register configurationsChandan Uddaraju2016-05-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change provides the below updates: - Current DP PLL driver uses the pll_base and the base address for the TXn registers instead of phy_base address. Fix this by using the correct base address. - Disable handoff for vco_divided_clk by implementing handoff function for this clock. - Update the PLL settings to fix PLL locking issues. CRs-Fixed: 1009740 Change-Id: Iea46c5b0482bceb841309175ede42ec3be3e20fd Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* | clk: msm: mdss: fix dp_link_2x_clk_mux clock ops for DP PLL on msmcobaltChandan Uddaraju2016-05-27
| | | | | | | | | | | | | | | | | | | | | | | | | | The DP link clock path in the DSI PLL has a mux clock (dp_link_2x_clk_mux) which allows the pixel clock to be either sourced out two divider clocks. In the current code, the ops for this mux clock is overloaded incorrectly which results in the link clock being always sourced out of the first divider clock. Fix this by using the default mux clock ops for this clock. CRs-Fixed: 1009740 Change-Id: Ie12d5ab272dbd79fe97225864c2360fdde7325a7 Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* | clk: msm: clock: Add the non_local_control setting for video clocksDeepak Katragadda2016-05-27
| | | | | | | | | | | | | | | | | | | | The video subcore RCGs should be force enabled during rate scaling to workaround video firmware potentially disabling the branch clock at the same time on MSMCOBALT. CRs-Fixed: 1020896 Change-Id: I45a119591efc36fa05ee7009d938e596b015e70c Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-local2: Enable sources before force turning on RCGDeepak Katragadda2016-05-27
| | | | | | | | | | | | | | | | | | Make sure that the RCG parents are turned on before force enabling it and changing its configuration. CRs-Fixed: 1020896 Change-Id: Ia633c4dcbab62fc6a4407c5896e36a7bbef48579 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: mdss: fix DSI PLL programming for msmcobaltAravind Venkateswaran2016-05-24
| | | | | | | | | | | | | | | | | | | | | | | | VCO configuration should be based on the requested vco clock rate and should not factor in the bit clock source divider. In addition, the bit clock source divider for the slave controller should always be set to 1. This will ensure that the PLL is locked at the correct rate. CRs-Fixed: 1019289 Change-Id: Ie5c171e13dcccc711ba03acb38fcd7876e792cee Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
* | clk: msm: clock-gpu-cobalt: Correct the CRC enable sequenceDeepak Katragadda2016-05-24
| | | | | | | | | | | | | | | | | | Correct the sequence to turn on the GPU_GX gdsc as part of enabling the GFX CRC. CRs-Fixed: 1018785 Change-Id: I64d0abe7091f81f85e83747f09ece4bc524a4057 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock: Support peripheral clocks on MSMCOBALT v2Deepak Katragadda2016-05-24
| | | | | | | | | | | | | | | | | | Add support for controlling the peripheral clocks on MSMCOBALT v2. CRs-Fixed: 1015446 Change-Id: If69f3752c4295f4cc49cf41854edc03aa90dbbc5 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-alpha-pll: Fix incorrect fabia PLL settingsDeepak Katragadda2016-05-23
| | | | | | | | | | | | | | | | | | | | | | For the fabia PLL to be in STANDBY mode, the RESET_N bit should be set so that the PLL comes out of reset. Else, the PLL is at OFF state and changing it's frequencies would not cause the ACK_LATCH to be set. CRs-Fixed: 1018752 Change-Id: I30f1ee0f4fdb8d92a9f6e187c1d8b797a0bdc94d Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-osm: register cycle counter callbacks with schedulerOsvaldo Banuelos2016-05-20
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement clk_osm_get_cpu_cycle_counter() which returns the running cycle counter value. Register these two functions with a scheduler-provided callback to allow the scheduler to estimate CPU frequency without notification. Lastly, setup the cycle counter to be increased on every rising edge of the XO clock for improved accuracy. Change-Id: Ie0f60ca79efc05901a88da13f7a6476f390518a5 CRs-Fixed: 988356 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* | clk: msm: osm: fix cores in retention as inactive selectionOsvaldo Banuelos2016-05-18
| | | | | | | | | | | | | | | | | | | | | | When SPM_CORE_RET_MAPPING is set to 1, cores in retention are treated as inactive by the OSM. However, currently this register is programmed to 0 when the flag to treat cores in retention as inactive is specified. Fix this. Change-Id: Ibc5df71ddd0cfdabf82d3c1e47efca0d88823a2f CRs-Fixed: 1017123 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* | clk: msm: clock-alpha-pll: Program the fabia PLL calibration registerDeepak Katragadda2016-05-18
| | | | | | | | | | | | | | | | | | | | Add programming the PLL_CAL_L_VAL register to the fabia PLL set_rate sequence. This is required on MSMCOBALT v1 as a workaround. CRs-Fixed: 1016938 Change-Id: I298acf633228b2c565736bf7bfd446d96f4e1983 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: mdss: fix pclk_src_mux clock ops for DSI PLL on msmcobaltAravind Venkateswaran2016-05-16
| | | | | | | | | | | | | | | | | | | | | | | | The DSI pixel clock path in the DSI PLL has a mux clock (pclk_src_mux) which allows the pixel clock to be either sourced out of the VCO clock or the bitclock. In the current code, the ops for this mux clock is overloaded incorrectly which results in the pixel clock being always sourced out of the bit clock. Fix this by using the default mux clock ops for this clock. Change-Id: I39c23b52d17994e28bd3b0d93e8e3dabdb687940 Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
* | clk: msm: clock-gcc-cobalt: Add reset capability to PCIE pipe clockDeepak Katragadda2016-05-15
| | | | | | | | | | | | | | | | | | Instead of having a separate reset clock for PCIE 0 reset, tag the BCR register with the gcc_pcie_0_pipe_clk directly. CRs-Fixed: 1014989 Change-Id: Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-gcc-cobalt: Update the pcie_aux_clk_src frequencyDeepak Katragadda2016-05-15
| | | | | | | | | | | | | | | | | | The pcie_aux_clk_src needs to run at XO frequency instead of at 1MHz. Update the clock driver to support that. CRs-Fixed: 1013278 Change-Id: Id8a92b0f36f71ed50726504d1e5b3feab4cfa512 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: osm: initialize PLL test control registerOsvaldo Banuelos2016-05-12
| | | | | | | | | | | | | | | | | | Program the PLL test control register for the power cluster clock in agreement with hardware guidelines. Change-Id: I102fd544ea0571d31d2ef9232195d4adbddda6d7 CRs-Fixed: 1009203 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* | clk: msm: clock-gcc-cobalt: Update the FMAXes for hmss_gpll0_clk_srcDeepak Katragadda2016-05-11
| | | | | | | | | | | | | | | | | | The hmss_gpll0_clk_src RCG only needs an SVS2 vote on CX to run. Update the FMAXes in the linux clock driver. CRs-Fixed: 1013237 Change-Id: I31aaeb7cf965bfbee4aa219936d8e298899b61a8 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-gcc-cobalt: Add new hw_ctl_clk type UFS clocksDeepak Katragadda2016-05-10
| | | | | | | | | | | | | | | | | | Add new UFS clocks to support enabling/disabling the hardware dynamic gating for their corresponding branch clocks. CRs-Fixed: 1012355 Change-Id: I4836ad8a775b0ec0375e37d27fcbe380e661a7b2 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-local2: Add support for enabling clock HW_CTLDeepak Katragadda2016-05-10
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a new hw_ctl_clk type to allow clock clients to enable hardware dynamic gating of the clock branch. Clients should use the clk_enable API on a separate hw_ctl_clk clock structure to set this bit. Vice-versa for clearing it. It is mandatory that the clients call clk_enable on the actual branch clock before enabling the hw_ctl_clk clock. CRs-Fixed: 1012355 Change-Id: I24e78353fa07f537bafc322dba6b1ffac913cd1d Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: osm: support programming LMh SW override values in set_rate()Osvaldo Banuelos2016-05-09
| | | | | | | | | | | | | | | | | | | | | | To ensure stable operation, it is necessary to place LMh SW override votes when setting the new rate of the power and performance CPU clocks. Add support for parsing these values from Device Tree and programming them in clk_set_rate(). Change-Id: I60d90d546f155edb6c13c46e6c59c75e95848d6c CRs-Fixed: 1009097 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* | clk: qcom: mdss: add Display-port pll clock driver supportChandan Uddaraju2016-05-09
| | | | | | | | | | | | | | | | | | | | Add support for new Display-port PLL clock driver to handle different DP panel resolutions in msmcobalt. Add separate files to support this new PHY PLL block. CRs-Fixed: 1009740 Change-Id: Ic282c7e14fc6e23f4d044cb6a58249bdb4c8c2d8 Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
* | msm: clock: clock-gcc-cobalt: Support QSPI clocks on MSMHAMSTERDeepak Katragadda2016-05-06
| | | | | | | | | | | | | | | | | | Add programming support for the qspi_ref and qspi_ahb clocks in the linux clocks driver. CRs-Fixed: 1011840 Change-Id: Ic67b72b1e9341fec33bcdbde67f9e2c7e8045ec1 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: osm: increase timer resolution programming to nanosecondsOsvaldo Banuelos2016-05-06
| | | | | | | | | | | | | | | | | | | | | | OSM clock period is 5 ns. Therefore, the various hysteresis timers used by OSM can be fine tuned with a granularity of 5 ns. Allow specification of timers in units of nanoseconds to prevent losing valid timer setpoints. Change-Id: Ice93347aaf81fe41ea7862752ac0d2d4e82d838c CRs-Fixed: 1009097 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* | clk: msm: clock-osm: increase refcount of CPU clocks at probe timeOsvaldo Banuelos2016-05-06
| | | | | | | | | | | | | | | | | | | | Increase the refcount of CPU clocks proportionally to the number of available CPUs to maintain the assumption that each CPU clock has been prepared and enabled by the time cpufreq takes over. Change-Id: Icccb28bc7a88dc76cf4ed5710623e992ba62f19c CRs-Fixed: 994035 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* | clk: msm: clock-gcc-cobalt: Add SVS2 frequencies for some UFS clocksDeepak Katragadda2016-05-03
| | | | | | | | | | | | | | | | | | Add SVS2 frequencies to the ufs_axi_clk_src and ufs_ice_core_clk_src clock sources on MSMCOBALT. CRs-Fixed: 1010329 Change-Id: I01210f48d32d7d6cb32f4977e52fb46acd33b1ba Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock-gcc-cobalt: Add clock reset support for additional clocksDeepak Katragadda2016-05-03
| | | | | | | | | | | | | | | | | | Add the BCR register for the gcc_ufs_axi_clk and gcc_blsp1/2_ahb_clk clocks. CRs-Fixed: 1005036 Change-Id: I8cd2403bed66141c99ccf8b9c57e59b936c1d90e Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | clk: msm: clock: Support graphics clocks on MSMHAMSTERDeepak Katragadda2016-04-29
| | | | | | | | | | | | | | | | | | Add support for controlling the graphics clocks on MSMHAMSTER. CRs-Fixed: 1004885 Change-Id: If96d8e7e0cd97cf45c48c6c39236d42659e25ea2 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-07-16 18:54:02 +0000