| Commit message (Collapse) | Author | Age |
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Add device tree properties to enable flash current mitigation
and specify the current limits to use for the different thermal
OTST levels.
CRs-Fixed: 1043718
Change-Id: Iaff6bbf6d7c17ebd6937dbfd91cbabcf09dee118
Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
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Enabling Spread Spectrum Clocking (SSC) support in MDSS DSI PLL
device for msmcobalt.
CRs-Fixed: 1036187
Change-Id: I15ee013f42e6d8630ae650350cc4d92dffd01b2e
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
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Add new pcm device node to use in the ultra low latency
path in noirq mode.
Change-Id: Icf2cb24f60558ffcd6d458e56d2ff967e9d33fa7
CRs-Fixed: 1054967, 1035545
Signed-off-by: Haynes Mathew George <hgeorge@codeaurora.org>
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Create new 64-bit kernel defconfig for msmfalcon to have
target specific configs enabled.
While at it, also rename 32-bit defconfig to be consistent.
Change-Id: Ic4cb890a69aa208261c6cecd2db1cfe3275d1fe9
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
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The core and peripheral memory retention bits no longer need to be
set and cleared by the GDSC driver on MSMCOBALT. Instead, the video
and camera client drivers will use the clk_set_flags API to toggle
these bits as needed.
Change-Id: Ia10ff063d8dc7b52a52e0ff22a2b0a46cc171eb5
CRs-Fixed: 1044274
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Use the exclude_idle attribute of the perf events to avoid reading
PMUs of idle CPUs. The counter values are updated when CPU enters
idle and the saved value is returned when the idle CPU is queried
for that event provided the attribute is set in the perf_event.
Change-Id: I61f7a7474856abf67ac6dfd9e531702072e108a5
Signed-off-by: Patrick Fay <pfay@codeaurora.org>
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Add bus bandwidth entry for ICNSS. It will be used to vote for
aggre2_noc_clk for SMMU.
CRs-Fixed: 1053538
Change-Id: Ic7523e68d65634f28babac6d17e0b02311d7ad79
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
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Set CONFIG_MSM_AVTIMER item to enable AVTimer used by camera for VT calls.
Change-Id: I99fdc57e1d0cde48ac5192d83ced96848232eb41
CRs-Fixed: 1051287
Signed-off-by: Siena Richard <sienar@codeaurora.org>
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This reverts commit 2dae58c4af32 ("arm64: fpsimd: Enable
FP(floating-point) settings for msm8996").
Feature is not applicable to msmcobalt and only applicable
to MSM8996.
CRs-Fixed: 1054373
Change-Id: I8f21787f0a45dd9f7be8986b4f332f498add3203
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
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This reverts commit 1f7d497b0ace ("arm64: fpsimd: add support to
enable/disable fpsimd_settings.").
Feature is not applicable to msmcobalt and only applicable
to MSM8996.
CRs-Fixed: 1054373
Change-Id: I8d11c596d61f0435f4ee2d1007f4903843650aed
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
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This reverts commit 8df2feee092a ("defconfig: arm64: Enable
FP settings for msm8996").
Feature is not applicable to msmcobalt and only applicable
to MSM8996.
CRs-Fixed: 1054373
Change-Id: I0d2c9bc8f27c2ac938754ab97b4bdc7feb6325b1
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
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This reverts commit 7ab05c20ad43 ("arm64: Add support
for app specific settings").
Feature is not applicable to msmcobalt and only applicable
to MSM8996.
CRs-Fixed: 1054373
Change-Id: I12d3a22362b965c7d302976c83ab0e757c98d3c6
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
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This reverts commit fa5a089eb6b7 ("defconfig: arm64: Enable app
specific setting on MSM8996").
Feature is not applicable to msmcobalt and only applicable
to MSM8996.
CRs-Fixed: 1054373
Change-Id: I9464305f6cac6aedb3e5763979dba4cba92e050b
Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
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msmcobalt target supports 4 MI2S and 4 PCM ports. Add pin-control
definitions for these ports.
Change-Id: I632c1dc7136a49c07b587a03181b5b4da42bdd4b
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
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qusb2 phy programming sequence on msmcobalt v2 platform requires
one extra register write to initialize the phy.
Change-Id: Id2e764210e3ca9e12a3d8299bf0c585958bbd7c8
Signed-off-by: Hemant Kumar <hemantk@codeaurora.org>
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Renable GIC_V3_ACL on msmcobalt-perf defconfig to disable ITS
support.
CRs-Fixed: 1054447
Change-Id: Ia0bd3026025c1215c595219a19cc164bc3758363
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
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Clients may have additional mappings in an iommu domain which are not
managed by arm_iommu_create_mapping. As such, it is important that
arm_iommu_create_mapping only use the iova region specified by the client.
However, the current implementation rounds the size of the region up to a
256K boundary (on arm64).
Change-Id: I88ddd98a76b39e3e9126d78da8e725491f2a5b32
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
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Rather than defining QoS clock references at the fab
which can create unwanted clock/gdsc toggles, define
QoS clocks at the affected node instead.
Change-Id: I15a01a772198e0383b1b73052e2d0c4160bf389f
Signed-off-by: David Dai <daidavid1@codeaurora.org>
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Add psci node in msmfalcon device tree to have
support for PSCI.
Change-Id: I5d0cb3fcc711d22eada0983b6b660da7be1d9a3e
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
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Update the graphics and multimedia clock frequencies and FMAXes
to align with the v2 and vq frequency plans. While doing so,
remove support for the gpu_pll1 PLL since it is not going to be
used to generate any frequencies.
CRs-Fixed: 1051170
Change-Id: I4d6547d95bd76d8ca6f4d729009d8b4a78716d5b
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Reset clocks are required by clients those require to reset their subsystem
blocks using the reset framework. As clock mmss supports reset clocks, add
support for the same.
Change-Id: Ia8f5e0b9e86b49077f15db8da2dc7a3cda6b1748
Signed-off-by: Taniya Das <tdas@codeaurora.org>
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Enable CONFIG_IRQSOFF_TRACER and CONFIG_PREEMPT_TRACER to be able to
measure the time spent in irqs-off and preemption-off critical sections.
Change-Id: Icd3aedb9efc702d6bec0d4966d87f10c235d83e9
Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
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Define the Silver and Gold cluster OSM look up tables
with the frequencies and data required to support Silver
cluster scaling up to 1.9 GHz and Gold cluster to
2.5 GHz. Also, update the supported frequencies in the msm
and devfreq CPUfreq devices.
CRs-Fixed: 1051857
Change-Id: Id9e9d37c6c0ac5c3ba6f566377bf86dbfe8ccabb
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Define the CPR corner information for the VDD_APC0 and
VDD_APC1 devices of the msmcobalt v2 chipset. This enables
CPRh closed-loop operation to reduce power consumption by
the voltage rails powering the Silver and Gold clusters.
CRs-Fixed: 1051863
Change-Id: I40b24c00d2c8ec767ba67951b16e7a3c7cdeb511
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Add support for per-chip revision open-loop fuse reference
voltages. This allows for the correct calculation of open-loop
voltages across msmcobalt chip revisions where the fused
reference voltages vary. Lastly, update the compatible string for
existing msmcobalt v1 CPR APC devices.
CRs-Fixed: 1051863
Change-Id: Icff31b265b49d087005ac0e58d7783ff2588548c
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Enable clock gating of venus core, when the core is in idle
state. HLOS can do this using the Clock Gate 4.
CRs-Fixed: 1048319
Change-Id: Iaa1ed5c24f07b8e18efc35de4f6ae6edea3b9f55
Signed-off-by: Chinmay Sawarkar <chinmays@codeaurora.org>
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The axi clock is needed while voting for bus bandwidth and needs
to be turned on along with other cpp clocks, Remove cpp rcg clk.
CRs-Fixed: 1044777 1044373
Change-Id: I644cdf84c6cf71bcb8f4ea24c0efb9a3603ca435
Signed-off-by: Gautham Mayyuri <gmayyuri@codeaurora.org>
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