| Commit message (Collapse) | Author | Age |
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Add property to support multiple sensor which are same slave address
and used in the one platform.
Change-Id: Id6e648ecffd07de1fdafb6fc6187dc14e3e6e36e
Signed-off-by: Wei Ding <weiding@codeaurora.org>
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Add actuator src and flash src of camera0 node for
support focus and flash function on msm8998 qrd skuk board.
Change-Id: I92ed864aedfdd38c8670e08fb35a6545e8abb142
Signed-off-by: Pengfei Liu <pengfeiliu@codeaurora.org>
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Add msm-core device to run power and temperature calculation
on the cores.
Change-Id: I3e8300f15757739714579055985e3fff1a4d8f86
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
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Add the demo battery profile to support 6A charging with pmi8998
on msm8998 MTP.
Change-Id: Id76ebe4a2591664d44d8003730f70defcb2899bc
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
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Clone the ascent battery profile to create a demo battery
profile to support 6A charging with pmi8998.
Change-Id: I57d33cadbe26d5298ef7149a004d14102d62f365
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>
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Remove msm_bus bandwidth vote from DT for msm8998
as WLAN FW will take care of it.
CRs-Fixed: 1094917
Change-Id: Ied5dcb9e3283dc2ec7f5fd6f03465b070f989d8b
Signed-off-by: Yuanyuan Liu <yuanliu@codeaurora.org>
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Remove redundant inclusion of mtp dtsi in msm8998-qrd.dtsi file.
CRs-Fixed: 1094871
Change-Id: Ibc9e99fd69cbd30e449d0fec728d71a1fa7f162c
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
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Add bluetooth device tree node for WCN3990 chip in msm8998 QRD
SKUK board. Configure necessary power supply and clocks to enable
bluetooth.
CRs-Fixed: 1080773
Change-Id: I433c349ddfd6d83629080afadc6fbf79c3b8c635
Signed-off-by: zhenchao <zhenchao@codeaurora.org>
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Add bluetooth device tree node for WCN3990 chip in msm8998 QRD
VR1 board. Configure necessary power supply and clocks to enable
bluetooth.
CRs-Fixed: 1080773
Change-Id: I47b042dc79145a13142c02b0ef8da777efff3a8d
Signed-off-by: zhenchao <zhenchao@codeaurora.org>
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Modify ACD_EXTINT_CFG so that ACD calibrates every time OSM toggles
full freq signal. This is recommended by hardware guidelines to
prevent ACD from mitigating when CPU clock frequency is boosted.
CRs-Fixed: 1088429
Change-Id: I07856ea8b332dbf12654fdd0b5d5518355f1c350
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Add mem-acc threshold and crossover voltage properties to the
VDD_APC0/1 CPR devices and a matching mem-acc crossover voltage
to the OSM device. Update the APM threshold voltage
to 800 mV for both clusters.
CRs-Fixed: 1088429
Change-Id: I747fd7665401803998b2824ace6dedbc5797b17f
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Add support for addtional performance cluster speed bins. Speed bin
fuse 2 and 3 devices can run with a quad core CPU fmax of 2.361 GHz and
single core CPU fmax of 2.457 GHz.
CRs-Fixed: 1086294
Change-Id: I08c3b8bc7e4d40c80be588f05b9439b339f46afc
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Update the VDD_APC0 and VDD_APC1 CPR devices to support two additional
speed bins. This allows CPR operation on bin 2 and 3 parts which have
different performance cluster frequency configurations compared to bin
0 and 1.
CRs-Fixed: 1086294
Change-Id: Id0854f1094ee3e4d4b1961f98a77003f7bcca1da
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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The maximum VDD_APC1 voltage has been increased to 1.136 V
for msm8998 v2. Update the AVS limits of L2 SAW and the
CPR aging reference voltage to reflect this.
CRs-Fixed: 1086294
Change-Id: I863bee32e1e66d9656fc70748628b25606b59e47
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Update the VDD_APC0/1 max floor to ceiling range as well
as the open-loop and closed-loop Nominal fuse corner
adjustments to match the latest hardware characterization.
CRs-Fixed: 1086294
Change-Id: I920175ab16d5a3fc5cd3f117bba3fd1d37db3c5d
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Add the necessary configuration to the OSM clock device in
msm8998 v2 to initialize ACD.
Change-Id: Ibdb861a50ad654be34e14e2bcc012fdf5063acaf
CRs-Fixed: 1053383
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
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Add the new perf configuration for msmfalcon and msmtriton.
Update the msmfalcon_defconfig also.
Change-Id: I8c3be2d0235395a338b758e4dc27a4b243bff62d
Signed-off-by: Venkatesh Yadav Abbarapu <vabbar@codeaurora.org>
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The clock nodes require the regulator nodes to be updated for interposer,
so add the same. Also update the gfx rail regulator phandle.
Change-Id: I08580f4eb04660cd1d123065976ba9bfec61b7d8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
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Clients of VADC_HC and BTM include reading voltage phone
power, system thermistors for thermal mitigation such as
msm_therm, case_therm, XO therm. Add the supported VADC
and BTM channels for the msm8998-qrd-vr1 platforms.
CRs-Fixed: 1090542
Change-Id: I4cda24b1be20310f54ceba1297f424ede1c5d889
Signed-off-by: King Li <kjli@codeaurora.org>
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Clients of VADC_HC and BTM include reading voltage phone
power, system thermistors for thermal mitigation such as
msm_therm, case_therm, XO therm. Add the supported VADC
and BTM channels for the msm8998-qrd-skuk platforms.
CRs-Fixed: 1090579
Signed-off-by: King Li <kjli@codeaurora.org>
Change-Id: I7b7c0ec59e9a3ce8a3526bdc8eb7359a0c98ccd7
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It is found that "dc civac" from el0 on a non-COW RO VA results in a
segmentation fault, while as per ARM ARM, for el0 only read access
permission is needed on a VA to perform clean and invalidate. This bug
was introduced by commit 3fbe6bc28a6b ("arm64: Allow cache maintenance
operations to trigger write faults"), which enabled write faults on all
cache maintenance faults.
The original intention of the above commit was to trigger write faults
only for cache maintenance operations performed by EL1 on user VA. But
it introduced this side effect of generating a write fault on EL0 cache
maintenance ops also when a read permission is sufficient for operation
to succeed. This results in a segmentation fault when the VA is part of
region marked as PROT_READ.
So trigger write faults only when the cache maintenance fault is generated
in non-user mode. Still, there can be a case where kernel performs a cache
maintenance op on a PROT_READ mapped VA which will result in a kernel
fault. But that looks invalid since there is no need for a kernel driver
to perform a cache maintenance on a RO buffer and such cases if they exist
need to be fixed.
Change-Id: I001ca0473c37fcf713201386b5ed6a6244f6b37d
Signed-off-by: Vinayak Menon <vinmenon@codeaurora.org>
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arm64 sets non-dirty userspace PTEs as read only by default.
The expectation is that on the first write the fault handler will
properly unmark the PTE as read only. Currently, the fault handler
will not mark a fault coming from a cache maintenance operation as
a write. The result of this is that a write to a user space address
from a cache maintenance operation will not get unmarked as read only
and the access may be retried infinitely. Rather than going through
the hassel and side effects of adding the cache operations to the
exception table and changing arm code to match, just drop the CM
check from the fault handler and let cache maintenance faults be
handled like normal writes.
Change-Id: I4b295b47ebdd24abf94204ad634e91ca5f71ce8a
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Vinayak Menon <vinmenon@codeaurora.org>
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This change adds the UFS_RESET pin ctrl data for UFS controller node.
This will enable UFS driver to issue reset to UFS device.
Change-Id: I61561fb7e395671d2bc52c6a9c0c71e0351114ea
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
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Include RPM regulator dtsi to enable RPM regulator device
nodes for MSM8998 based interposer platform.
CRs-Fixed: 1077493
Change-Id: Ifcfd9f75e817561b17ec26a68f901a31c5a63a9a
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
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interposer"
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In msmfalcon interposer for CDP and MTP, add
audio related dtsi files to support external
codecs tasha and tavil.
CRs-Fixed: 1083537
Change-Id: I867e28101cfa37f9764d547f3b43871a430de6d7
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
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Add required changes for LDOs for msm8998-interposer-msmfalcon
for USB functionality to be working.
Change-Id: I121651a49ef27ba02f1960ed5c95baf93b00d1f5
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
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Add required USBPD PHY device node for msmfalcon for USB PD
functionality to be working.
Change-Id: I8cd2981f176e08c1ea4f8a9b7ff42887b590d941
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>
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PM3FALCON inherits all it's peripheral nodes from PM2FALCON.
Disable WLED which is not supported on pm3falcon.
CRs-Fixed: 1093681
Change-Id: I1eb0583010712286659ec9b726f4ae7a9a2a84e6
Signed-off-by: Kiran Gunda <kgunda@codeaurora.org>
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Add thermal properties to enable kernel thermal monitoring and
mitigations like hotplug, thermal reset, vdd restriction, etc.
for msmfalcon. Add mitigation profiles for each physical CPU which
has information like sensor to monitor and various mitigation types
to enable for msmfalcon.
Change-Id: I36ca125143cf9929fb0bd781990bdd8ab1dbeebf
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
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