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| | * | | UPSTREAM: MIPS: Make flush_threadRalf Baechle2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoids function calls to an empty function. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 04cc89d120f94131de89a6e20da27016db4782ce) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
| | * | | UPSTREAM: MIPS: Properly disable FPU in start_thread()James Hogan2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | start_thread() (called for execve(2)) clears the TIF_USEDFPU flag without atomically disabling the FPU. With a preemptive kernel, an unfortunately timed preemption after this could result in another task (or KVM guest) being scheduled in with the FPU still enabled, since lose_fpu_inatomic() only turns it off if TIF_USEDFPU is set. Use lose_fpu(0) instead of the separate FPU / MSA management, which should do the right thing (drop FPU properly and atomically without saving state) and will be more future proof. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12302/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 76e5846d3bdf59eb1010d5607003da2dc3910bb1) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
| | * | | UPSTREAM: MIPS: Select CONFIG_HANDLE_DOMAIN_IRQ and make it work.David Daney2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Per the subject, always select HANDLE_DOMAIN_IRQ, and implement set_irq_regs() so that it actually works. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12496/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 1d2753a66acbb101a0ec495cd13b9031ac1b171f) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
| | * | | UPSTREAM: MIPS: math-emu: Fix typoAndrea Gelmini2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: macro@imgtec.com Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13333/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit e7e3346cc64fff306694bdc41908283d195339c1) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
| | * | | UPSTREAM: MIPS: math-emu: dsemul: Remove an unused bit in ADDIUPC emulationMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid a reader's confusion, as the calculation is correct either way. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12283/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 036aff91c30a6f15d5bf25f22827abc26b6d06c1) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
| | * | | UPSTREAM: MIPS: math-emu: dsemul: Reduce `get_isa16_mode' clutterMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12178/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 6d7b14151d7510ed434f2e587cdae9eca82fc123) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
| | * | | UPSTREAM: MIPS: math-emu: dsemul: Correct description of the emulation frameMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove irrelevant content from the description of the emulation frame in `mips_dsemul', referring to bare-metal configurations. Update the text, reflecting the change made with commit ba3049ed4086 ("MIPS: Switch FPU emulator trap to BREAK instruction."), where we switched from using an address error exception on an unaligned access to the use of a BREAK 514 instruction causing a breakpoint exception instead. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12176/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 6e1715f7c34d00dc94f3cecb2526ae3ff0b0649f) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
| | * | | UPSTREAM: MIPS: math-emu: Correct the emulation of microMIPS ADDIUPC instructionMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Emulate the microMIPS ADDIUPC instruction directly in `mips_dsemul'. If executed in the emulation frame, this instruction produces an incorrect result, because the value of the PC there is not the same as where the instruction originated. Reshape code so as to handle all microMIPS cases together. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12175/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 69a1e6cbdf1f40d5dcae84c5a538d390b6d2c307) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
| | * | | UPSTREAM: MIPS: math-emu: Make microMIPS branch delay slot emulation workMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Complement commit 102cedc32a6e ("MIPS: microMIPS: Floating point support.") which introduced microMIPS FPU emulation, but did not adjust the encoding of the BREAK instruction used to terminate the branch delay slot emulation frame. Consequently the execution of any such frame is indeterminate and, depending on CPU configuration, will result in random code execution or an offending program being terminated with SIGILL. This is because the regular MIPS BREAK instruction is encoded with the 0 major and the 0xd minor opcode, however in the microMIPS instruction set this major/minor opcode pair denotes an encoding reserved for the DSP ASE. Instead the microMIPS BREAK instruction is encoded with the 0 major and the 0x7 minor opcode. Use the correct BREAK encoding for microMIPS FPU emulation then. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12174/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 733b8bc183f491e8263009edf8ef184fb44a6882) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
| | * | | UPSTREAM: MIPS: math-emu: dsemul: Fix ill formatting of microMIPS partMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct formatting breakage introduced with commit 102cedc32a6e ("MIPS: microMIPS: Floating point support."), so that further changes to this code can be consistent. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12173/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit a87265cfedce49fa362030ae3e6ef047e08bc12c) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
| | * | | UPSTREAM: MIPS: math-emu: Correctly handle NOP emulationMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix an issue introduced with commit 9ab4471c9f1b ("MIPS: math-emu: Correct delay-slot exception propagation") where the emulation of a NOP instruction signals the need to terminate the emulation loop. This in turn, if the PC has not changed from the entry to the loop, will cause the kernel to terminate the program with SIGILL. Consider this program: static double div(double d) { do d /= 2.0; while (d > .5); return d; } int main(int argc, char **argv) { return div(argc); } which gets compiled to the following binary code: 00400490 <main>: 400490: 44840000 mtc1 a0,$f0 400494: 3c020040 lui v0,0x40 400498: d44207f8 ldc1 $f2,2040(v0) 40049c: 46800021 cvt.d.w $f0,$f0 4004a0: 46220002 mul.d $f0,$f0,$f2 4004a4: 4620103c c.lt.d $f2,$f0 4004a8: 4501fffd bc1t 4004a0 <main+0x10> 4004ac: 00000000 nop 4004b0: 4620000d trunc.w.d $f0,$f0 4004b4: 03e00008 jr ra 4004b8: 44020000 mfc1 v0,$f0 4004bc: 00000000 nop Where the FPU emulator is used, depending on the number of command-line arguments this code will either run to completion or terminate with SIGILL. If no arguments are specified, then BC1T will not be taken, NOP will not be emulated and code will complete successfully. If one argument is specified, then BC1T will be taken once and NOP will be emulated. At this point the entry PC value will be 0x400498 and the new PC value, set by `mips_dsemul' will be 0x4004a0, the target of BC1T. The emulation loop will terminate, but SIGILL will not be issued, because the PC has changed. The FPU emulator will be entered again and on the second execution BC1T will not be taken, NOP will not be emulated and code will complete successfully. If two or more arguments are specified, then the first execution of BC1T will proceed as above. Upon reentering the FPU emulator the emulation loop will continue to BC1T, at which point the branch will be taken and NOP emulated again. At this point however the entry PC value will be 0x4004a0, the same as the target of BC1T. This will make the emulator conclude that execution has not advanced and therefore an unsupported FPU instruction has been encountered, and SIGILL will be sent to the process. Fix the problem by extending the internal API of `mips_dsemul', making it return -1 if no delay slot emulation frame has been made, the instruction has been handled and execution of the emulation loop needs to continue as if nothing happened. Remove code from `mips_dsemul' to reproduce steps made by the emulation loop at the conclusion of each iteration, as those will be reached normally now. Adjust call sites accordingly. Document the API. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12172/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit e4553573b37c3f72533683cb5f3a1ad300b18d37) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | | | | Merge "defconfig: arm64: msm: Enable SPMI msm8996 virtual platform"Linux Build Service Account2018-03-06
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| * | | | | defconfig: arm64: msm: Enable SPMI msm8996 virtual platformYimin Peng2018-03-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add virtual SPMI PMIC arbiter support on virtual platform. Change-Id: I3642d41c5474f975f18f5d19136284b632868389 Signed-off-by: Yimin Peng <yiminp@codeaurora.org>
| * | | | | ARM: dts: msm: Add SPMI and PMIC devices for msm8996 vplatformYimin Peng2018-03-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add virtual SPMI Arbiter and PMIC clients which are disabled by default. Change-Id: I39e5d22bff0f796716a34d7d9ff0e2040cf2d61b Signed-off-by: Yimin Peng <yiminp@codeaurora.org>
* | | | | | Merge "ARM: dts: msm: Disable usb phy by default on msm8996 vplatform"Linux Build Service Account2018-03-06
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| * | | | | ARM: dts: msm: Disable usb phy by default on msm8996 vplatformZhiqiang Tu2018-03-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable usb phy by default and only enable them for the targets which require the support for usb phy. Change-Id: I55d5cba5ef06d3269cc9600dfec866c0f88b31ab Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* | | | | | Merge "ARM: dts: msm: Add support for modem test tools on msm8996 vplatform"Linux Build Service Account2018-03-02
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| * | | | | | ARM: dts: msm: Add support for modem test tools on msm8996 vplatformRamachandran Venkataramani2018-03-01
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add smdpkt and glinkpkt devices with the SSR handlers to support PC based tools to test the modem and adsp. Change-Id: I2a77f6d01ad13b9c061eacbf4d08af12d8e183a7 Signed-off-by: Ramachandran Venkataramani <ramavenk@codeaurora.org>
* / / / / / defconfig: msm: Enable FW loader user space helper for GVMFerry Zhou2018-02-28
|/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | WLAN firmware files are located at non-standard firmware path. So, enable user space helper to load firmware from non-standard fs paths like /vendor/firmware and /firmware/image etc. Change-Id: I60bbc89953ad66dabd76badc4f2117a06f5f0cc7 Signed-off-by: Ferry Zhou <tianguiz@codeaurora.org>
* | | | | ARM: dts: qcom: Remove lpm performance index for sdm660Tirupathi Reddy2018-02-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not use a fixed OSM performance index for sdm660 CPU clusters while entering certain low power modes. CRs-Fixed: 2171214 Change-Id: I4cdcd1f950174ce5570d9546590e6d135d42b426 Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
* | | | | Revert "ARM: dts: msm: Enable ACD functionality for SDM660 silver cluster"Tirupathi Reddy2018-02-26
| |/ / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 791e28b55c04a0c786d64dd8e8a2083b9a225a10. Disable ACD functionality for SDM660 silver cluster to address stability issues. CRs-Fixed: 2171214 Change-Id: Id598c7348e656bf01a21510a27d68fb8beb08fbb Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
* | | | defconfig: msm: Enable configs for modem interfacesRamachandran Venkataramani2018-02-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add configs for sysmon, smdpkt and glinkpkt Change-Id: I57494e41388351eebab92a350f46608358943ca2 Signed-off-by: Ramachandran Venkataramani <ramavenk@codeaurora.org>
* | | | ARM: dts: msm: Disable BCL for all msm8996 auto targetsManaf Meethalavalappu Pallikunhi2018-02-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The auto target doesn't require battery current limit (BCL) solution. Disable BCL devicetree node for all msm8996 auto targets. Change-Id: I70f249de2d7d1304287a9f71a7d48f1b90fabee7 Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
* | | | defconfig: msm: Enable battery current limit module for msm8996Manaf Meethalavalappu Pallikunhi2018-02-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable battery current limit module, which can monitor the battery current, voltage, and SoC and mitigate the CPU cluster. Change-Id: I2ba17fe5fe76d42999f71c6197200ac90ff68877 Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
* | | | Merge "ARM: dts: msm: Disable SPI CAN controller on msm8996 CV2X boards"Linux Build Service Account2018-02-14
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| * | | | ARM: dts: msm: Disable SPI CAN controller on msm8996 CV2X boardsGustavo Solaira2018-02-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable the SPI based CAN controller on msm8996 CV2X boards since they are using the USB based CAN controller now. Change-Id: I57cccee0b9ffa59f516747350160907960048a6a Signed-off-by: Gustavo Solaira <gustavos@codeaurora.org>
* | | | | Merge "defconfig: msm: Enable PCAN-USB for msm8996"Linux Build Service Account2018-02-13
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| * | | | defconfig: msm: Enable PCAN-USB for msm8996Gustavo Solaira2018-01-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable PCAN-USB for msm8996 to support USB based CAN controller. Change-Id: I9f31026681e6f281ad08b66e77cff0da1aa1fdf5 Signed-off-by: Gustavo Solaira <gustavos@codeaurora.org>
* | | | | Merge "ARM: dts: msm: Remove rh850 device node from mizar"Linux Build Service Account2018-02-13
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| * | | | | ARM: dts: msm: Remove rh850 device node from mizarAlex Yakavenka2018-02-08
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mizar board doesn't have rh850 can controller Change-Id: Ie3eb224fc4dfa71da7d290bfaf47ae4b9fcaceb4 Signed-off-by: Alex Yakavenka <ayakav@codeaurora.org>
* | / / / ARM: dts: msm: disable wdog wakeup on msm8996 vplatformYimin Peng2018-02-12
| |/ / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | The wdog always bites with the flag when guest virtual machine enters into suspend. Change-Id: Ie239dcb8a48cdaffcddf923a3114210ec5947ff9 Signed-off-by: Yimin Peng <yiminp@codeaurora.org>
* | | | ARM: dts: msm: refine device tree hierarchy for msm8996 vplatformZhiqiang Tu2018-02-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the basic part and audio common part to separated device tree include files for msm8996 virtual platform. Change-Id: Id1847f6bbf083fb82230f6eb67d32fea401baa5d Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
* | | | Merge "ARM: dts: qcom: add wdog to the baseline msm8996 vplatform"Linux Build Service Account2018-02-09
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| * | | | ARM: dts: qcom: add wdog to the baseline msm8996 vplatformYimin Peng2018-02-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ramdump function needs watchdog device support. Change-Id: I04e7e5773096c91fdc592aedf5d295256bd6ca08 Signed-off-by: Yimin Peng <yiminp@codeaurora.org>
* | | | | Merge "arm64: Move BP hardening to check_and_switch_context"Linux Build Service Account2018-02-08
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| * | | | | arm64: Move BP hardening to check_and_switch_contextMarc Zyngier2018-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We call arm64_apply_bp_hardening() from post_ttbr_update_workaround, which has the unexpected consequence of being triggered on every exception return to userspace when ARM64_SW_TTBR0_PAN is selected, even if no context switch actually occured. This is a bit suboptimal, and it would be more logical to only invalidate the branch predictor when we actually switch to a different mm. In order to solve this, move the call to arm64_apply_bp_hardening() into check_and_switch_context(), where we're guaranteed to pick a different mm context. Change-Id: I28f2fb09b77544e5ead095e9dad1ad64b2b3ae36 Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Git-commit: a8e4c0a919ae310944ed2c9ace11cf3ccd8a609b Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
* | | | | | Merge "arm64: Add BTAC/LinkStack sanitizations for Kryo cores"Linux Build Service Account2018-02-08
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| * | | | | arm64: Add BTAC/LinkStack sanitizations for Kryo coresSrinivas Ramana2018-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kryo cores are exposed to two vulnerabilities due to subroutine return (called LINK-STACK) and branch target predictors. These two issues can be mitigated through software workarounds. Kernel: - Apply LINK-STACK mitigation which is to issue 16 nested BL instructions on process context switch 'cpu_do_switch_mm()' where ASID changes. - Apply psci based branch predictor invalidation. use the kryo core detection routine (based on MIDR) from the commit bb48711800e6d ("arm64: cpu_errata: Add Kryo to Falkor 1003 errata") by Stephen Boyd <sboyd@codeaurora.org>. Change-Id: I81e8e72e7fa219f12dfe8ec39836eb8eb3c4c7b0 Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
* | | | | | Merge "arm64: Implement branch predictor hardening for Falkor"Linux Build Service Account2018-02-08
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| * | | | | arm64: Implement branch predictor hardening for FalkorShanker Donthineni2018-02-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Falkor is susceptible to branch predictor aliasing and can theoretically be attacked by malicious code. This patch implements a mitigation for these attacks, preventing any malicious entries from affecting other victim contexts. Change-Id: I535d423c2cefaf93627267b867bf0846e502d4c1 Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org> [will: fix label name when !CONFIG_KVM and remove references to MIDR_FALKOR] Signed-off-by: Will Deacon <will.deacon@arm.com> Git-commit: ec82b567a74fbdffdf418d4bb381d55f6a9096af Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git [sramana@codeaurora.org: Use only the link stack sanitization routines, and leave Falkor related BP hardening code] Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
* | | | | | Merge "arch: arm64: Add midr values for kryo2xx big cores"Linux Build Service Account2018-02-08
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| * | | | | arch: arm64: Add midr values for kryo2xx big coresSrinivas Ramana2018-02-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add midr value for kryo2xx big cores to apply errata workarounds for branch prediction hardening. Change-Id: I7ca9cfa3e6b48d5af78a5297cb76ebe6f52e519e Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
* | | | | | Merge "arm64: Implement branch predictor hardening for affected Cortex-A CPUs"Linux Build Service Account2018-02-08
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| * | | | | arm64: Implement branch predictor hardening for affected Cortex-A CPUsWill Deacon2018-02-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing and can theoretically be attacked by malicious code. This patch implements a PSCI-based mitigation for these CPUs when available. The call into firmware will invalidate the branch predictor state, preventing any malicious entries from affecting other victim contexts. Change-Id: I554536e8e5cb3839e102299da8f5b944415b1880 Co-developed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Git-commit: aa6acde65e03186b5add8151e1ffe36c3c62639b Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
* | | | | | Merge "arm64: Define Cortex-A73 MIDR"Linux Build Service Account2018-02-08
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| * | | | | arm64: Define Cortex-A73 MIDRMarc Zyngier2018-02-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As we're about to introduce a new workaround that is specific to Cortex-A73, let's define the coresponding MIDR. Change-Id: Iabb0e83a0eadddbde458fdafd1224e442b6f3e63 Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Git-commit: 199fd2bff4040985fbd7853cc39b7245fcf54bb9 Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git [sramana@codeaurora.org: Resolve trivial merge conflicts] Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
* | | | | | Merge "arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75"Linux Build Service Account2018-02-08
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| * | | | | arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75Will Deacon2018-02-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they will soon need MIDR matches for hardening the branch predictor. Change-Id: I59af5ea4af17198aa70d2ba4b25f729a562727ee Signed-off-by: Will Deacon <will.deacon@arm.com> Git-commit: a65d219fe5dc7887fd5ca04c2ac3e9a34feb8dfc Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git [sramana@codeaurora.org: Resolve trivial merge conflicts] Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
* | | | | | Merge "arm64: cpu_errata: Allow an erratum to be match for all revisions of ↵Linux Build Service Account2018-02-08
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| * | | | | arm64: cpu_errata: Allow an erratum to be match for all revisions of a coreMarc Zyngier2018-02-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some minor erratum may not be fixed in further revisions of a core, leading to a situation where the workaround needs to be updated each time an updated core is released. Introduce a MIDR_ALL_VERSIONS match helper that will work for all versions of that MIDR, once and for all. Change-Id: Icbb685f79205ba45f9c990d83cf961616b0d96b7 Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Git-commit: 06f1494f837da8997d670a1ba87add7963b08922 Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git [sramana@codeaurora.org: Fix merge conflicts] Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
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