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* linux: Move hdmi audio codec header to common locationCasey Piper2016-03-23
| | | | | | | | | Move contents of msm_hdmi_audio_codec.h directory to msm_hdmi.h in common linux directory to remove platform dependence. Change-Id: I6331073ba1e5e119770c5e8cb50f6ff677807292 Signed-off-by: Casey Piper <cpiper@codeaurora.org>
* msm: mdss: hdmi: HDMI cable connection status and voteAjay Singh Parmar2016-03-23
| | | | | | | | | | Add HDMI cable connection status functionality to be used by audio driver before starting the audio session and vote for hdmi tx core to remain power on until the audio has completed its processing. Change-Id: I35d1bafff472da19e04aa44f4ac91b1c3c0349e1 Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
* mdss: hdmi: Dynamic Audio re-configurationAjay Singh Parmar2016-03-23
| | | | | | | | This change allows audio driver to change the audio configuration dynamically without bother HDCP link and video configurations. Change-Id: I34af3a9070d29a3ea3ebad7196ca24765fcf6152 Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
* msm: mdss: hdmi: Add support for new HDMI-Audio interfaceUjwal Patel2016-03-23
| | | | | | | | | | Using this new interface, HDMI-Audio codec driver can retrieve sink's audio capabilities. Based on this supported capabilities and current playback clip, it will pass appropriate audio setup information to HDMI driver for configuration. Change-Id: Ia52f72d955778859c381a5e6c94aba57e40d13b2 Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
* defconfig: Enable audio driver on msm-perf_defconfigSudheer Papothi2016-03-23
| | | | | | Include config options for audio in msm-perf_defconfig. Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
* ARM: dts: msm: Disable hdmi audio on kernel 4.4Sudheer Papothi2016-03-23
| | | | | | | Disable HDMI audio functionality on kernel 4.4 till the HDMI driver is ready. Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
* defconfig: Add audio drivers for MSM targetsSudheer Papothi2016-03-23
| | | | | | Add audio drivers for MSM targets. Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
* defconfig: arm64: msm: Enable data featuresSubash Abhinov Kasiviswanathan2016-03-23
| | | | | | | | | | Enable configurations needed for the operation of data specific features such as IPv4 and IPv6 tethering and packet filtering using QoS. Enable ESP match target in iptables to provide the ability to match packets based on the SPI (Security Parameters Index) value in the ESP (Encapsulating Security Payload) header. Signed-off-by: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
* msm: ipa3: defconfig change to compile ipa3Skylar Chang2016-03-23
| | | | Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
* defconfig: msmcortex: Enable the stub regulator driverDevesh Jhunjhunwala2016-03-23
| | | | | | | Add configs to enable the stub regulator driver for the debug and perf configs for msmcortex. Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
* defconfig: arm64: msmcortex: Enable sensors SSC driverSatya Durga Srinivasu Prabhala2016-03-23
| | | | | | Enable sensors SSC driver for msmcortex. Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* ARM64: dts: msm: Add sensors SSC node for msmcobaltSatya Durga Srinivasu Prabhala2016-03-23
| | | | | | | | To support Sensors on msmcobalt, Add sensors SSC device tree node with status = "ok". Change-Id: I2a81ea6a5acc1043a6d28f718580d6a4eb1d39ea Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* defconfig: arm64: msm: Enable tz_logZhen Kong2016-03-23
| | | | | | | This is necessary to support tz_log functionality Acked-by: Shabnam Aboughadareh <shabnama@qti.qualcomm.com> Signed-off-by: Zhen Kong <zkong@codeaurora.org>
* defconfig: Enable PM_DEVFREQ related configsRohit Gupta2016-03-23
| | | | | | | Enable devfreq device and governors. Change-Id: Ifbdb959caab5715dd71c366a38250367ae032605 Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
* defconfig: Enable CPU_FREQ related configsJunjie Wu2016-03-23
| | | | | | | | Enable CPU_FREQ related configs, including governors, cpu-boost driver and cpufreq device for MSM. Change-Id: Icd0a0a7962e72706dbbae02ad7898f938391682c Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
* defconfig: msm: enable CONFIG_SCHED_DEBUGJoonwoo Park2016-03-23
| | | | | | | Enable CONFIG_SCHED_DEBUG in order to expose /proc/sched_debug. Change-Id: Id784c80fe6203f007501637c3d17876528329e2b Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
* defconfig: msm: enable HMP schedulerJoonwoo Park2016-03-23
| | | | | | | Enable HMP scheduler along with scheduler guided frequency input. Change-Id: Ia0e7cf6c5c5ff44492836ebb5189574f55cb742e Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
* defconfig: msm: clean up msm_defconfig and msm-perf_defconfigJoonwoo Park2016-03-23
| | | | | | | Clean up msm_defconfig and msm-perf_defconfig with 'make savedefconfig'. Change-Id: I118d9d4ddc1fb89b4301cb7ceffdbccc60699329 Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
* ARM: dts: enable HMP schedulerJoonwoo Park2016-03-23
| | | | | | | Enable HMP scheduler for msm8996. Change-Id: I2ecdf4b2409b3e1d4f176f2b9f63a9c17aec5ead Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
* diag: Add snap shot of diag driverSreelakshmi Gownipalli2016-03-23
| | | | | | Add snap shot of diag driver Signed-off-by: Sreelakshmi Gownipalli <sgownipa@codeaurora.org>
* usb: gadget: cdev: Add USB serial driver functionalityMayank Rana2016-03-23
| | | | | | | | | This change adds below functionality: 1. Add USB serial driver functionality 2. Add configfS support 3. Enable USB character serial driver Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* irqchip: Compile IRQ_MSMRohit Vaswani2016-03-23
| | | | Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
* defconfig: Seemp: add seemp functionalityWilliam Clark2016-03-23
| | | | | | | Needed to add seemp functionality Change-Id: I43b4eee9191adc7777b9cb937bc4cd0e455dc198 Signed-off-by: William Clark <wclark@codeaurora.org>
* defconfig: msm8996: Enable wil driverMaya Erez2016-03-23
| | | | | | | Enable wil driver as module for MSM8996. Wil driver is needed for 11ad wireless card. Signed-off-by: Maya Erez <merez@codeaurora.org>
* defconfig: arm64: msm: Enable qcom msm crypto driverZhen Kong2016-03-23
| | | | | | This is necessary to support qcom msm crypto functionality. Signed-off-by: Zhen Kong <zkong@codeaurora.org>
* defconfig: msm: Enable WLAN related flagsYue Ma2016-03-23
| | | | | | Add the flags which are required to enable WLAN. Signed-off-by: Yue Ma <yuem@codeaurora.org>
* defconfig: enanble esoc on msm debug and perf defconfigsAbhimanyu Kapur2016-03-22
| | | | | | | | Enable support for esoc interface layer with external soc components on the msm debug and perf defconfigs. Change-Id: I33a4b1f8cdda9a287e6715b23da8b3876abc2ab0 Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* defconfig: enable few debug options on msm_defconfigAbhimanyu Kapur2016-03-22
| | | | | | | | Enable triggering wdog on kernel panic and enable panic on data corruption. Change-Id: I4798ff27ef470225607fdccc15e8fa3a6ebdb1eb Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* defconfig: arm64: disable SPI on msmcortex configsAbhimanyu Kapur2016-03-22
| | | | | | | | Disable SPI on msmcortex debug and perf configs since it fails to compile. Change-Id: Ia9e4077428a0760f1428b81597503e92402bad2a Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* arm64: spinlock: Drop the prfm from arch_spin_trylockRohit Vaswani2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per ARM the prefetch for store (prfm pstl1strm) in the arch_spin_trylock routine can lead to some false positives, decreasing the lock performance. On the Cortex-A57 / Cortex-A53, if the memory type is Shareable, then any linefill started by a PST (prefetch for store)/PLDW instruction also causes the data to be invalidated in other cores, so that the line is ready for writing. This will also clear the exclusive marker associated with that cache line (clearing the exclusive monitors). So, in the scenario where we could have multiple cores trying to acquire exclusive access to a cacheline, the removal of prefetch would help with potentially increasing the chances of one of the cores making progress. Example: struct { spinlock_t lock; atomic_t count; } x; We have 2 cores trying to run the below code spin_lock(&x.lock); atomic_inc(&x.count); spin_unlock(&x.lock); lock and count are part of a struct so they fall into the same cacheline. The lock function uses the trylock mechanism as part of debug spinlock. 1. Core1 has acquired the spinlock and is performing the ldxr, add, strx loop in atomic_inc. 2. Core2 are trying to acquire the spinlock. Core1 | Core2 ldxr | | | | prfm pstl1strm add | | | | ldaxr stxr (fails) | | | | Now, the prfm always clears the exclusive marker for the core1 ldxr, so the stxr always fails. This prevents core1 from making progress and releasing the spinlock that core2 is waiting for. This could potentially go on forever and we end up breaking this pattern if the timing changes or if an interrupt triggers. This could happen with more cores trying to acquire the spinlock, cause more prefetches and make the problem worse. By removing the prfm, we allow the stxr @core1 to suceed and atomic_inc completes, allowing core1 to unlock the spinlock and let core2 proceed. Change-Id: I742ab9b6d98aded628e4dcf4a6ec68b8e2a4ec3e Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> [abhimany: resolve minor merge conflicts] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* defconfig: msmcortex: Enable ARM Cortex-A edac supportAbhimanyu Kapur2016-03-22
| | | | | | | | Enable the error detection and correction driver for L1/L2 caches on the ARM Cortex-A cpu clusters. Change-Id: I8dc9e3719ae9868aaee51ef2186e513a3da1a4f7 Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* arm64: Add macro for Cortex A72 primary part numberSrinivas Ramana2016-03-22
| | | | | | | | | | Add a macro containing the MIDR Primary Part Number value needed to identify ARM Cortex A72 processors. Change-Id: I6a0d04930070523c3dba83f3d7869ba75288b531 Signed-off-by: Srinivas Ramana <sramana@codeaurora.org> [abhimany: resolve minor merge conflicts] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* ARM: dts: msm: Move SPSS device specific info for MSMCOBALT.Puja Gupta2016-03-22
| | | | | | | | | Move SCSR register offsets and bit positions specific to SPSS from driver to device tree entry. CRs-Fixed: 972423 Change-Id: I9712cc550b858af54c90ae92c8636e1d37b3f993 Signed-off-by: Puja Gupta <pujag@codeaurora.org>
* arm64: Call EDAC error handler on system errorStepan Moskovchenko2016-03-22
| | | | | | | | | | | | One possible cause of a system error exception is an ECC error in the CPU's caches. Call the ARM64 EDAC error handler from the system error exception handler to print EDAC error syndrome information to the kernel log. Change-Id: If8757eda0c7fc82b0fccee573cf09627a752fdf3 Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> [satyap: replace ESR_EL1_* with ESR_ELx_* to align with kernel 4.4] Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* ARM64: smp: Prevent cluster LPM modes when pending IPIs on cluster CPUsMahesh Sivasubramanian2016-03-22
| | | | | | | | | | | | | LPM modes can fail if there is a pending IPI interrupt at GIC CPU interface. On some usecases frequent failure of LPM modes can cause power and performance degradation. Hence, prevent cluster low power modes when there is a pending IPI on cluster CPUs. Change-Id: Id8a0ac24e4867ef824e0a6f11d989f1e1a2b0e93 Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org> [satyap: trivial merge conflict resolution] Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* arm: Add weak function definition for random pool intializationLaura Abbott2016-03-22
| | | | | | | | | | | | | | The random pool relies on devices and other items in the system to add entropy to the pool. Most of these devices may not be added until later in the bootup process. This leaves a large period of time where the random pool may not actually give random numbers. Add a weak function for devices to override with their own function to setup the random pool. Change-Id: I0de63420b11f1dd363ccd0ef6ac0fa4a617a1152 Signed-off-by: Laura Abbott <lauraa@codeaurora.org> [satyap: trivial merge conflict resolution] Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* arm64: Fix out of bound access to compat_hwcap_strSe Wang (Patrick) Oh2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As compat_hwcap_str[] doesn't end with 'NULL', c_show() tries to read the next element even after the end of the array. So add 'NULL' at the end of compat_hwcap_str[]. Below is the KASan report for referencing. BUG: KASan: out of bounds access in c_show+0x110/0x248 at addr ffffffc0011f6370 Read of size 8 by task pool-1-thread-1/10526 page:ffffffbac14b39c0 count:1 mapcount:0 mapping: (null) index:0x0 flags: 0x400(reserved) page dumped because: kasan: bad access detected Address belongs to variable compat_hwcap_str+0xb0/0xe0 CPU: 0 PID: 10526 Comm: pool-1-thread-1 Tainted: G B W 3.18.18-ga7b28e9-11552-ge4a827f #1 Hardware name: Qualcomm Technologies, Inc. MSM 8996 v2 + PMI8994 MTP (DT) Call trace: [<ffffffc000089ec4>] dump_backtrace+0x0/0x1c4 [<ffffffc00008a098>] show_stack+0x10/0x1c [<ffffffc0011a7c58>] dump_stack+0x74/0xc8 [<ffffffc00020e94c>] kasan_report_error+0x2b0/0x408 [<ffffffc00020eb80>] kasan_report+0x34/0x40 [<ffffffc00020db14>] __asan_load8+0x84/0x90 [<ffffffc000088ae8>] c_show+0x10c/0x248 [<ffffffc000245bb8>] traverse+0x1a8/0x320 [<ffffffc000245dc8>] seq_lseek+0x98/0x148 [<ffffffc00028f4e0>] proc_reg_llseek+0xa0/0xd8 [<ffffffc000217d1c>] vfs_llseek+0x5c/0x70 [<ffffffc000218b0c>] SyS_lseek+0x48/0x80 [<ffffffc000218b50>] compat_SyS_lseek+0xc/0x18 Memory state around the buggy address: ffffffc0011f6200: 00 00 fa fa fa fa fa fa 00 03 fa fa fa fa fa fa ffffffc0011f6280: 04 fa fa fa fa fa fa fa 00 00 00 00 00 00 00 00 >ffffffc0011f6300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa fa ^ ffffffc0011f6380: fa fa fa fa 00 00 00 00 00 00 fa fa fa fa fa fa ffffffc0011f6400: 02 fa fa fa fa fa fa fa 00 00 00 02 fa fa fa fa Change-Id: I5e2098f9a7a676c47a01baf10de3ac1c86265e69 Signed-off-by: Se Wang (Patrick) Oh <sewango@codeaurora.org> [satyap: trivial merge conflict resolution and move changes in arch/arm64/kernel from setup.c to cpuinfo.c to align with kernel 4.4] Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* ARM64: Add snapshot of edac.h from msm-3.10Stepan Moskovchenko2016-03-22
| | | | | | | | | | | Sync the ARM64 edac header to the version found in msm-3.10 as of commit 142c36711024877a2ec1eb13dbbca38503b26ee3 ("edac: cortex_arm64_edac: Use dbe irq only") to bring in external EDAC API definitions that were missed during the msm-3.18 upgrade. Change-Id: If2dc53858d7a30086a95ea5047bd6b18e44f7e09 Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
* ARM64: Enable EDAC support for ARM64 targetsStepan Moskovchenko2016-03-22
| | | | | | | | Select EDAC (Error Detection and Reporting) functionality for ARM64 CPUs to allow EDAC drivers for ARM64. Change-Id: I699cbefdba7afab65bf8b60c0d5df06dd3b57773 Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
* edac: arm64: Check for ECC errors on panicRohit Vaswani2016-03-22
| | | | | | | | | | | Check for ecc errors on panic on all processors Change-Id: I2a68644afb2730a69aca35abb1f10899a11514dd Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> [stepanm@codeaurora.org: update argument to arm64_check_cache_ecc()] Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> [satyap: trivial merge conflict resolution] Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* arm64: Fix conflict resolution in cpuinfo CPU reportingStepan Moskovchenko2016-03-22
| | | | | | | | | | | | | Commit ebc4e05c338bde49382c7c46ce6b8a371713862e ("arm64: show present cpu instead of online cpu in /proc/cpuinfo") did not have its conflicts against msm-3.18 properly resolved. Change-Id: I1f4eb1d8a20b2bc142a7f0b8890d383a9552557c Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> [satyap: trivial merge conflict resolution and move changes in arch/arm64/kernel from setup.c to cpuinfo.c to align with kernel 4.4] Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* ARM/ARM64: Introduce arch_read_hardware_idAbhimanyu Kapur2016-03-22
| | | | | | | | | | | | | | Moving towards device tree and arm single binary refering to machine descriptor name for hardware id information under /proc/cpuinfo is not suitable for certain soc vendors. Add a hook for soc vendors to supply a per-soc hardware read method. Change-Id: Ifcccdffa3c0e1e8b5f96837eb1c023e468d4c287 Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org> [satyap: trivial merge conflict resolution and move changes in arch/arm64/kernel from setup.c to cpuinfo.c to align with kernel 4.4] Signed-off-by: Satya Durga Srinivasu Prabhala <satyap@codeaurora.org>
* arm64: Set CONFIG_QCOM_KGSL in the defconfigJordan Crouse2016-03-22
| | | | | | | Enable the KGSL GPU driver by enabling CONFIG_QCOM_KGSL in the defconfig. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* defconfig: Enable IOMMU debugfs for msmPatrick Daly2016-03-22
| | | | | | | Allow using the iommu debugfs files. Change-Id: I039828bdb2b5c0369a260bd8f06061d35d84bba5 Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
* Revert "scatterlist: use sg_phys()"Dan Williams2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | commit db0fa0cb0157 "scatterlist: use sg_phys()" did replacements of the form: phys_addr_t phys = page_to_phys(sg_page(s)); phys_addr_t phys = sg_phys(s) & PAGE_MASK; However, this breaks platforms where sizeof(phys_addr_t) > sizeof(unsigned long). Revert for 4.3 and 4.4 to make room for a combined helper in 4.5. Cc: <stable@vger.kernel.org> Cc: Jens Axboe <axboe@fb.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Andrew Morton <akpm@linux-foundation.org> Fixes: db0fa0cb0157 ("scatterlist: use sg_phys()") Suggested-by: Joerg Roedel <joro@8bytes.org> Reported-by: Vitaly Lavrov <vel21ripn@gmail.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* scatterlist: use sg_phys()Dan Williams2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Coccinelle cleanup to replace open coded sg to physical address translations. This is in preparation for introducing scatterlists that reference __pfn_t. // sg_phys.cocci: convert usage page_to_phys(sg_page(sg)) to sg_phys(sg) // usage: make coccicheck COCCI=sg_phys.cocci MODE=patch virtual patch @@ struct scatterlist *sg; @@ - page_to_phys(sg_page(sg)) + sg->offset + sg_phys(sg) @@ struct scatterlist *sg; @@ - page_to_phys(sg_page(sg)) + sg_phys(sg) & PAGE_MASK Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Jens Axboe <axboe@fb.com>
* dma-mapping: fix build when !CONFIG_ARM_DMA_USE_IOMMUShiraz Hashim2016-03-22
| | | | | | | | | | | | | Allow compilation when CONFIG_ARM_DMA_USE_IOMMU is not selected by providing necessary stub functions and fix few mismatch in function declarations. Following this, remove the changes introduced by f3d8d1061fb0b146b3f5 ("msm: ipa: add empty implementation for iommu functions") as they are no longer needed. Change-Id: I04e3aa63407064e8d9c9550a5cb0a82ede899f00 Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
* arm: dma-mapping: flush highmem mappingsShiraz Hashim2016-03-22
| | | | | | | | | | | | | DMA allocations with no kernel mapping are likely protected as well. Stale highmem mappings in such cases with cache-able attributes may lead to speculative fetch ,as highmem mappings are not cleared out. Hence flush out unused highmem mappings explicitly when allocation request with no kernel mapping is requested. Change-Id: Ic1de633c6364eaa1b6d5b0932f2cfe17d64d920e Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
* ARM: dma-mapping: Allow highmem pages to not have a mappingLaura Abbott2016-03-22
| | | | | | | | | | The DMA_ATTR_NO_KERNEL_MAPPING is used to make sure that CMA pages have no kernel mapping. Add support to make sure that highmem pages have no mapping. Change-Id: Ife76df126ecfedf0dba81a35e0de8a1787355b3d Signed-off-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
* arm: dma: Allow CMA pages to not have a kernel mapping.Patrick Daly2016-03-22
| | | | | | | | | | | | | | Currently, there are use cases where not having any kernel mapping is required; if the CMA memory needs to be used as a pool which can have both cached and uncached mappings we need to remove the mapping to avoid the multiple mapping problem. Extend the dma APIs to use the DMA_ATTR_NO_KERNEL_MAPPING with CMA. This doesn't end up saving any virtual address space but the mapping will still not be present. Change-Id: I64d21250abbe615c43e2b5b1272ee2b6d106705a Signed-off-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
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