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* Merge 4.4.122 into android-4.4Greg Kroah-Hartman2018-03-18
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes in 4.4.122 RDMA/ucma: Limit possible option size RDMA/ucma: Check that user doesn't overflow QP state RDMA/mlx5: Fix integer overflow while resizing CQ scsi: qla2xxx: Fix NULL pointer crash due to active timer for ABTS workqueue: Allow retrieval of current task's work struct drm: Allow determining if current task is output poll worker drm/nouveau: Fix deadlock on runtime suspend drm/radeon: Fix deadlock on runtime suspend drm/amdgpu: Fix deadlock on runtime suspend drm/amdgpu: Notify sbios device ready before send request drm/radeon: fix KV harvesting drm/amdgpu: fix KV harvesting MIPS: BMIPS: Do not mask IPIs during suspend MIPS: ath25: Check for kzalloc allocation failure MIPS: OCTEON: irq: Check for null return on kzalloc allocation Input: matrix_keypad - fix race when disabling interrupts loop: Fix lost writes caused by missing flag kbuild: Handle builtin dtb file names containing hyphens bcache: don't attach backing with duplicate UUID x86/MCE: Serialize sysfs changes ALSA: hda/realtek - Fix dock line-out volume on Dell Precision 7520 ALSA: seq: Don't allow resizing pool in use ALSA: seq: More protection for concurrent write and ioctl races ALSA: hda: add dock and led support for HP EliteBook 820 G3 ALSA: hda: add dock and led support for HP ProBook 640 G2 nospec: Include <asm/barrier.h> dependency watchdog: hpwdt: SMBIOS check watchdog: hpwdt: Check source of NMI watchdog: hpwdt: fix unused variable warning netfilter: nfnetlink_queue: fix timestamp attribute ARM: omap2: hide omap3_save_secure_ram on non-OMAP3 builds Input: tca8418_keypad - remove double read of key event register tc358743: fix register i2c_rd/wr function fix netfilter: add back stackpointer size checks netfilter: x_tables: fix missing timer initialization in xt_LED netfilter: nat: cope with negative port range netfilter: IDLETIMER: be syzkaller friendly netfilter: ebtables: CONFIG_COMPAT: don't trust userland offsets netfilter: bridge: ebt_among: add missing match size checks netfilter: ipv6: fix use-after-free Write in nf_nat_ipv6_manip_pkt netfilter: use skb_to_full_sk in ip_route_me_harder netfilter: x_tables: pass xt_counters struct instead of packet counter netfilter: x_tables: pass xt_counters struct to counter allocator netfilter: x_tables: pack percpu counter allocations ext4: inplace xattr block update fails to deduplicate blocks ubi: Fix race condition between ubi volume creation and udev scsi: qla2xxx: Replace fcport alloc with qla2x00_alloc_fcport NFS: Fix an incorrect type in struct nfs_direct_req Revert "ARM: dts: LogicPD Torpedo: Fix I2C1 pinmux" x86/module: Detect and skip invalid relocations x86: Treat R_X86_64_PLT32 as R_X86_64_PC32 serial: sh-sci: prevent lockup on full TTY buffers tty/serial: atmel: add new version check for usart uas: fix comparison for error code staging: comedi: fix comedi_nsamples_left. staging: android: ashmem: Fix lockdep issue during llseek USB: storage: Add JMicron bridge 152d:2567 to unusual_devs.h usb: quirks: add control message delay for 1b1c:1b20 USB: usbmon: remove assignment from IS_ERR argument usb: usbmon: Read text within supplied buffer size usb: gadget: f_fs: Fix use-after-free in ffs_fs_kill_sb() serial: 8250_pci: Add Brainboxes UC-260 4 port serial device fixup: sctp: verify size of a new chunk in _sctp_make_chunk() Linux 4.4.122 Change-Id: I0946c4a7c59be33f18bed6498c3cdb748e82bbaf Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
| * MIPS: BMIPS: Do not mask IPIs during suspendJustin Chen2018-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 06a3f0c9f2725f5d7c63c4203839373c9bd00c28 upstream. Commit a3e6c1eff548 ("MIPS: IRQ: Fix disable_irq on CPU IRQs") fixes an issue where disable_irq did not actually disable the irq. The bug caused our IPIs to not be disabled, which actually is the correct behavior. With the addition of commit a3e6c1eff548 ("MIPS: IRQ: Fix disable_irq on CPU IRQs"), the IPIs were getting disabled going into suspend, thus schedule_ipi() was not being called. This caused deadlocks where schedulable task were not being scheduled and other cpus were waiting for them to do something. Add the IRQF_NO_SUSPEND flag so an irq_disable will not be called on the IPIs during suspend. Signed-off-by: Justin Chen <justinpopo6@gmail.com> Fixes: a3e6c1eff548 ("MIPS: IRQ: Fix disabled_irq on CPU IRQs") Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17385/ [jhogan@kernel.org: checkpatch: wrap long lines and fix commit refs] Signed-off-by: James Hogan <jhogan@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | FROMLIST: MIPS: Add noexec=on|off kernel parameterMiodrag Dinic2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new kernel parameter to override the default behavior related to the decision whether to indicate stack as non-executable or executable (regardless of PT_GNU_STACK entry or CPU RIXI support) in function mips_elf_read_implies_exec(). Allowed values: noexec=on: force indicating non-exec stack & heap noexec=off: force indicating executable stack & heap If this parameter is omitted, kernel behavior remains the same as it was before this patch is applied. This functionality is convenient during debugging and is especially useful for Android development where indication of non-executable stack is required. NOTE: Using noexec=on on a system without CPU XI support is not recommended since there is no actual HW support that provide non-executable stack and heap. Use only for debugging purposes and not in a production environment. Signed-off-by: Miodrag Dinic <miodrag.dinic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com> (cherry picked from: https://patchwork.linux-mips.org/patch/18218/) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | FROMLIST: MIPS: CPC: Map registers using DT in mips_cpc_default_phys_base()Paul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reading mips_cpc_base value from the DT allows each platform to define it according to its needs. This is especially convenient for MIPS_GENERIC kernel where this kind of information should be determined in runtime. Use mti,mips-cpc compatible string with just a reg property to specify the register location for your platform. Signed-off-by: Paul Burton <paul.burton@mips.com> Signed-off-by: Miodrag Dinic <miodrag.dinic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com> (cherry picked from: https://patchwork.linux-mips.org/patch/18513/) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: CPS: Handle spurious VP starts more gracefullyPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On pre-r6 systems with the MT ASE the CPS SMP code included checks to halt the VPE running mips_cps_boot_vpes() if its bit in the struct core_boot_config vpe_mask field is clear. This was largely done in order to allow us to start arbitrary VPEs within a core despite the fact that hardware is typically configured to run only VPE0 after powering up a core. VPE0 would start the desired other VPEs, halt itself, and the fact that VPE0 started would be largely hidden & irrelevant. In MIPSr6 multithreading we have control over which VPs start executing when a core powers up via the cores CPC registers accessed remotely through the redirect block. For this reason the MIPSr6 multithreading path in mips_cps_boot_vpes() hasn't bothered up until now to handle halting the VP running it. However it is possible to power up cores entirely in hardware by using a pwr_up pin associated with the core. Unfortunately some systems wire this pin to a logic 1, which means that it is possible for a core to power up at a point that software doesn't expect. The result is that we generally go execute the kernel on a CPU that ought not to be running & the results can be unpredictable. Handle this case by stopping VPs that we don't expect to be running in mips_cps_boot_vpes() - with this change even if a core powers up it will do nothing useful & all VPs within it will stop running before they proceed to run general kernel code & do any damage. Ideally we would produce some sort of warning here, but given the stage of core bringup this happens at that would be non-trivial. We also will only hit this if a core starts up after being offlined via hotplug, and when that happens we will already produce a warning that the CPU didn't power down in cps_cpu_die() which seems sufficient. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16198/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit fa7a3b4a7217b40bf58c4f38e5ee573b43a8aa2f) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: CPS: Handle cores not powering down more gracefullyPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we get into a state where a core that ought to power down isn't doing so then the current result is that another CPU gets stuck inside cps_cpu_die() waiting for CPU that ought to be powering down to do so. The best case scenario is that we then trigger RCU stall messages or lockup messages, but neither makes it particularly clear what's happening. Handle this more gracefully by introducing a timeout beyond which we warn the user that the core didn't power down & stop waiting for it. This at least allows the CPU running cps_cpu_die() to continue normally, and hopefully presuming the CPU that powered back up is doing nothing harmful the system will continue functioning as normal. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16197/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 4ad755c9e39c0eeae16f96b97602f1954f582c66) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: CPS: Prevent multi-core with dcache aliasingPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Systems using the MIPS Coherence Manager (CM) cannot support multi-core SMP with dcache aliasing. This is because CPU caches are VIPT, but interventions in CM-based systems provide only the physical address to remote caches. This means that interventions may behave incorrectly in the presence of an aliasing dcache, since the physical address used when handling an intervention may lead to operation on an aliased cache line rather than the correct line. Prevent us from running into this issue by refusing to boot secondary cores in systems where dcache aliasing may occur. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16196/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 5570ba2ee920de4e7760a2802b842771845b2c32) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: CM: WARN on attempt to lock invalid VP, not BUGPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | Rather than using BUG_ON in the case of an invalid attempt to lock access to a non-zero VP on a pre-CM3 system, use WARN_ON so that we have even the slightest chance of recovery. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16194/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 2f93a60c3d829da07764eafd922beb40e7317aa3) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: CM: Avoid per-core locking with CM3 & higherPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CM3 provides a GCR_CL_OTHER register per VP, rather than only per core. This means that we don't need to prevent other VPs within a core from racing with code that makes use of the core-other register region. Reduce locking overhead by demoting the per-core spinlock providing protection for CM2.5 & lower to a per-CPU/per-VP spinlock for CM3 & higher. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16193/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 516db1c61f3fd4328361699a2c74781ab1dbf84c) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: smp-cps: Avoid BUG() when offlining pre-r6 CPUsMatt Redfearn2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 0d2808f338c7 ("MIPS: smp-cps: Add support for CPU hotplug of MIPSr6 processors") added a call to mips_cm_lock_other in order to lock the CPC in CPUs containing a version 3 or higher Coherence Manager, which use the general CM core other register, where previous CMs had a dedicated core other register for the CPC. A kernel BUG() is triggered, however, if mips_cm_lock_other is called with a VP other than 0 on a CPU with CM < 3, a condition introduced by 0d2808f338c7. Avoid the BUG() by always locking VP0 when locking the CPC, since the required register, cpc_stat_conf, is shared by all vps in a core. Fixes: 0d2808f338c7 ("MIPS: smp-cps: Add support for CPU hotplug...) Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Qais Yousef <qsyousef@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14297/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 6ca8ac773e97e2dfa5734ae435c40e672dd19ac4) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: smp-cps: Add support for CPU hotplug of MIPSr6 processorsMatt Redfearn2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce support for hotplug of Virtual Processors in MIPSr6 systems. The method is simpler than the VPE parallel from the now-deprecated MT ASE, it can now simply write the VP_STOP register with the mask of VPs to halt, and use the VP_RUNNING register to determine when the VP has halted. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13752/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 0d2808f338c7cb0ccf6b087dd7be0e4fa0c865e0) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: pm-cps: Change FSB workaround to CPU blacklistMatt Redfearn2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check for whether a CPU required the FSB flush workaround previously required every CPU not requiring it to be whitelisted. That approach does not scale well as new CPUs are introduced so change the default from a WARN and returning an error to just returning 0. Any CPUs requiring the workaround can then be added to the blacklist. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14218/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit b97d0b9099afcd5c569acaf9b0eb3f6e3b1b1f35) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Fix early CM probingPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit c014d164f21d ("MIPS: Add platform callback before initializing the L2 cache") added a platform_early_l2_init function in order to allow platforms to probe for the CM before L2 initialisation is performed, so that CM GCRs are available to mips_sc_probe. That commit actually fails to do anything useful, since it checks mips_cm_revision to determine whether it should call mips_cm_probe but the result of mips_cm_revision will always be 0 until mips_cm_probe has been called. Thus the "early" mips_cm_probe call never occurs. Fix this & drop the useless weak platform_early_l2_init function by simply calling mips_cm_probe from setup_arch. For platforms that don't select CONFIG_MIPS_CM this will be a no-op, and for those that do it removes the requirement for them to call mips_cm_probe manually (although doing so isn't harmful for now). Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Aaro Koskinen <aaro.koskinen@nokia.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Rob Herring <robh@kernel.org> Cc: Peter Hurley <peter@hurleysoftware.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Jaedon Shin <jaedon.shin@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12475/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 3af5a67c86a30f8cd8bfd6202709be21cedd2756) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: smp-cps: Stop printing EJTAG exceptions to UARTPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_MIPS_CPS_NS16550 is enabled, some register state is dumped to the UART when an exception is taken via the BEV on secondary cores. EJTAG exceptions are architecturally expected to be handled by the BEV even when Status.BEV is 0. This effectively means that if userland executes an sdbbp instruction on a secondary core then the kernel dumps register state to the UART even though the exception is perfectly normal & expected. Prevent this by simply not dumping information to the UART for EJTAG exceptions. Fixes: 609cf6f2291a ("MIPS: CPS: Early debug using an ns16550-compatible UART") Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12341/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 6609ccdc852f7bfbfa54300dd5b3cd89eb4ced6f) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: smp-cps: Add nothreads kernel parameterPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When debugging a new system or core it can be useful to disable the use of multithreading. Introduce a "nothreads" kernel command line parameter that can be set in order to do so. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12340/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 6422a913856716be080dba4c2cb9d083d4e244ed) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: smp-cps: Support MIPSr6 Virtual ProcessorsPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce support for bringing up Virtual Processors in MIPSr6 systems as CPUs, much like their VPE parallel from the now-deprecated MT ASE. The existing mips_cps_boot_vpes function fits the MIPSr6 architecture pretty well - it can now simply write the mask of running VPs to the VC_RUN register, rather than looping through each & starting or stopping as appropriate as is done for VPEs from the MT ASE. Thus the VP support is in general an extension & simplification of the existing MT ASE VPE (aka SMVP) support. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12339/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 5a3e7c02d84fd31e6a2b1b242612363b6131a09e) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: smp-cps: Skip core setup if coherentPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for supporting MIPSr6 multithreading (ie. VPs) which will begin execution from the core reset vector, skip core level setup if the core is already coherent. This is never the case when a core is first started, since boot_core explicitly clears the cores GCR_Cx_COH_EN register, and always the case when secondary VPs start since the first VP to start will have enabled coherence after initialising the core & its caches. One notable side effect of this patch is that eva_init gets called slightly earlier, prior to mips_cps_core_init rather than after it. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12338/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 87a70bcdb41008decfcf7c217e26b0bcd7f52642) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: smp-cps: Pull boot config retrieval out of mips_cps_boot_vpesPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mips_cps_boot_vpes function previously included code to retrieve pointers to the core & VPE boot configuration structs. These structures were used both by mips_cps_boot_vpes and by its mips_cps_core_entry callsite. In preparation for skipping the call to mips_cps_boot_vpes on some invocations of mips_cps_core_entry, pull the calculation of those pointers out into a separate function such that it can continue to be shared. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12337/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit f12401d7219f5a1e361ded834016e5777a10262b) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: smp-cps: Pull cache init into a functionPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for further modifications to mips_cps_core_entry, pull the L1 cache initialisation out into a separate function. This both makes the code in mips_cps_core_entry read more clearly, particularly when modifying it, and shortens it which will become important as code is added that needs to continue to fit within the reset vector. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12336/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 3dbc9971618ba0e88f25f2168aa5731b53af6f0b) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: smp-cps: Ensure our VP ident calculation is correctPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When bringing up a CPU, ensure that its local ID as provided by the GIC matches up with our calculation of it. This is vital, since if the condition doesn't hold then we won't have configured interrupts correctly for the VP. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Niklas Cassel <niklas.cassel@axis.com> Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12335/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit ba1c0a490a1fa61971b1cf9dd89acc7b4424e798) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: pm-cps: Avoid offset overflow on MIPSr6Markos Chandras2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is similar to commit 934c79231c1b ("MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions"). The CACHE instruction has been redefined for MIPSr6 and it reduced its offset field to 8 bits. This leads to micro-assembler field overflow warnings when booting SMP MIPSr6 cores like the following one: Call Trace: [<ffffffff8010af88>] show_stack+0x68/0x88 [<ffffffff8056ddf0>] dump_stack+0x68/0x88 [<ffffffff801305bc>] warn_slowpath_common+0x8c/0xc8 [<ffffffff80130630>] warn_slowpath_fmt+0x38/0x48 [<ffffffff80125814>] build_insn+0x514/0x5c0 [<ffffffff806ee134>] cps_gen_cache_routine.isra.3+0xe0/0x1b8 [<ffffffff806ee570>] cps_pm_init+0x364/0x9ec [<ffffffff80100538>] do_one_initcall+0x90/0x1a8 [<ffffffff806e8c14>] kernel_init_freeable+0x160/0x21c [<ffffffff8056b6a0>] kernel_init+0x10/0xf8 [<ffffffff801059f8>] ret_from_kernel_thread+0x14/0x1c We fix this by incrementing the base register on every loop. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12329/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 0f2a1484487407390196ca5b3c3a07bee6df15ad) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: traps: Make sure secondary cores have a sane ebase registerMarkos Chandras2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We shouldn't trust that the secondary cores will have a sane ebase register (either from the bootloader or during the hardware design phase) so use the ebase address as calculated by the boot CPU. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Petri Gynther <pgynther@google.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12328/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 04d83f948510f17f8f2ab320b2386f4b5fbd0bd4) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Detect MIPSr6 Virtual Processor supportPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPSr6 introduces support for "Virtual Processors", which are conceptually similar to VPEs from the now-deprecated MT ASE. Detect whether the system supports VPs using the VP bit in Config5, adding cpu_has_vp for use by later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Steven J. Hill <sjhill@realitydiluted.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12327/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit f270d881fa552c9c21c37417af2bf95da9a74347) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: unaligned: Add DSP lwx & lhx missaligned access supportMiodrag Dinic2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add handling of missaligned access for DSP load instructions lwx & lhx. Since DSP instructions share SPECIAL3 opcode with other non-DSP instructions, necessary logic was inserted for distinguishing between instructions with SPECIAL3 opcode. For that purpose, the instruction format for DSP instructions is added to arch/mips/include/uapi/asm/inst.h. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtech.com> Cc: James.Hogan@imgtec.com Cc: Paul.Burton@imgtec.com Cc: Raghu.Gandham@imgtec.com Cc: Leonid.Yegoshin@imgtec.com Cc: Douglas.Leung@imgtec.com Cc: Petar.Jovanovic@imgtec.com Cc: Goran.Ferenc@imgtec.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16511/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 3f88ec633362efa454ca4ea289d4ad91cd44a976) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: cmdline: Add support for 'memmap' parameterMiodrag Dinic2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement support for parsing 'memmap' kernel command line parameter. This patch covers parsing of the following two formats for 'memmap' parameter values: - nn[KMG]@ss[KMG] - nn[KMG]$ss[KMG] ([KMG] = K M or G (kilo, mega, giga)) These two allowed formats for parameter value are already documented in file kernel-parameters.txt in Documentation/admin-guide folder. Some architectures already support them, but Mips did not prior to this patch. Excerpt from Documentation/admin-guide/kernel-parameters.txt: memmap=nn[KMG]@ss[KMG] [KNL] Force usage of a specific region of memory. Region of memory to be used is from ss to ss+nn. memmap=nn[KMG]$ss[KMG] Mark specific memory as reserved. Region of memory to be reserved is from ss to ss+nn. Example: Exclude memory from 0x18690000-0x1869ffff memmap=64K$0x18690000 or memmap=0x10000$0x18690000 There is no need to update this documentation file with respect to this patch. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Cc: James.Hogan@imgtec.com Cc: Paul.Burton@imgtec.com Cc: Raghu.Gandham@imgtec.com Cc: Leonid.Yegoshin@imgtec.com Cc: Douglas.Leung@imgtec.com Cc: Petar.Jovanovic@imgtec.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16508/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 296a7624f5b292af610d728e7e347fda341a985e) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: CPC: Provide default mips_cpc_default_phys_base to ignore CPCPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a default implementation of mips_cpc_default_phys_base() which simply returns 0, and adjust mips_cpc_phys_base() to allow for mips_cpc_default_phys_base() returning 0. This allows kernels which include CPC support to be built without platform code & simply ignore the CPC if it wasn't already enabled by the bootloader. This fixes link failures such as the following from generic defconfigs: arch/mips/built-in.o: In function `mips_cpc_phys_base': arch/mips/kernel/mips-cpc.c:47: undefined reference to `mips_cpc_default_phys_base' [ralf@linux-mips.org: changed prototype for coding style compliance.] Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reported-by: kbuild test robot <fengguang.wu@intel.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14401/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 682c1e52215da4a3e89c14aad60bfc0d400b025f) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Allow emulation for unaligned [LS]DXC1 instructionsPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an address error exception occurs for a LDXC1 or SDXC1 instruction, within the cop1x opcode space, allow it to be passed through to the FPU emulator rather than resulting in a SIGILL. This causes LDXC1 & SDXC1 to be handled in a manner consistent with the more common LDC1 & SDC1 instructions. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13143/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit e70ac023f9515c70cf2b291a294f0f250df29847) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: r2-on-r6-emu: Clear BLTZALL and BGEZALL debugfs countersAleksandar Markovic2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing clearing of BLTZALL and BGEZALL emulation counters in function mipsr2_stats_clear_show(). Previously, it was not possible to reset BLTZALL and BGEZALL emulation counters - their value remained the same even after explicit request via debugfs. As far as other related counters are concerned, they all seem to be properly cleared. This change affects debugfs operation only, core R2 emulation functionality is not affected. Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: james.hogan@imgtec.com Cc: leonid.yegoshin@imgtec.com Cc: douglas.leung@imgtec.com Cc: petar.jovanovic@imgtec.com Cc: miodrag.dinic@imgtec.com Cc: goran.ferenc@imgtec.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15517/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 411dac79cc2ed80f7e348ccc23eb4d8b0ba9f6d5) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: r2-on-r6-emu: Fix BLEZL and BGTZL identificationLeonid Yegoshin2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the problem of inaccurate identification of instructions BLEZL and BGTZL in R2 emulation code by making sure all necessary encoding specifications are met. Previously, certain R6 instructions could be identified as BLEZL or BGTZL. R2 emulation routine didn't take into account that both BLEZL and BGTZL instructions require their rt field (bits 20 to 16 of instruction encoding) to be 0, and that, at same time, if the value in that field is not 0, the encoding may represent a legitimate MIPS R6 instruction. This means that a problem could occur after emulation optimization, when emulation routine tried to pipeline emulation, picked up a next candidate, and subsequently misrecognized an R6 instruction as BLEZL or BGTZL. It should be said that for single pass strategy, the problem does not happen because CPU doesn't trap on branch-compacts which share opcode space with BLEZL/BGTZL (but have rt field != 0, of course). Signed-off-by: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtech.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtech.com> Reported-by: Douglas Leung <douglas.leung@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: james.hogan@imgtec.com Cc: petar.jovanovic@imgtec.com Cc: goran.ferenc@imgtec.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15456/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 5bba7aa4958e271c3ffceb70d47d3206524cf489) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | BACKPORT: MIPS: store the appended dtb address in a variableJonas Gorski2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of rewriting the arguments to match the UHI spec, store the address of a appended or UHI supplied dtb in fw_supplied_dtb. That way the original bootloader arugments are kept intact while still making the use of an appended dtb invisible for mach code. Mach code can still find out if it is an appended dtb by comparing fw_arg1 with fw_supplied_dtb. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: John Crispin <john@phrozen.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Alban Bedel <albeu@free.fr> Cc: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13699/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 15f37e1588920e010f20b53f04af94e91b8ee714) Conflicts: arch/mips/ath79/setup.c arch/mips/lantiq/prom.c arch/mips/pic32/pic32mzda/init.c Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Fix FCSR Cause bit handling for correct SIGFPE issueMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 5a1aca4469fdccd5b74ba0b4e490173b2b447895) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: kernel: Audit and remove any unnecessary uses of module.hPaul Gortmaker2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically a lot of these existed because we did not have a distinction between what was modular code and what was providing support to modules via EXPORT_SYMBOL and friends. That changed when we forked out support for the latter into the export.h file. This means we should be able to reduce the usage of module.h in code that is obj-y Makefile or bool Kconfig. The advantage in doing so is that module.h itself sources about 15 other headers; adding significantly to what we feed cpp, and it can obscure what headers we are effectively using. Since module.h was the source for init.h (for __init) and for export.h (for EXPORT_SYMBOL) we consider each obj-y/bool instance for the presence of either and replace as needed. In the case of the n32/o32 files, we have to get rid of a couple no-op MODULE_ tags to facilitate the module.h removal. They piggy back off the fs/ elf binary support, which is also a bool Kconfig. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14032/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit d9d5417755eda87db8e370e4dd2175fbd8814acc) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Spelling fix lets -> let'sRalf Baechle2018-02-05
| | | | | | | | | | | | | | | | | | As noticed by Sergei in the discussion of Andrea Gelmini's patch series. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> (cherry picked from commit 4939788eb8559754a120531c49ffa96bb30fee06) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: R6: Fix typoAndrea Gelmini2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Cc: macro@imgtec.com Cc: paul.burton@imgtec.com Cc: Leonid.Yegoshin@imgtec.com Cc: trivial@kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13329/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit f5be47f5a4b74ca4bc58348a0b2a6aa4c8cba1be) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: traps: Correct the SIGTRAP debug ABI in `do_watch' and ↵Maciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `do_trap_or_bp' Follow our own rules set in <asm/siginfo.h> for SIGTRAP signals issued from `do_watch' and `do_trap_or_bp' by setting the signal code to TRAP_HWBKPT and TRAP_BRKPT respectively, for Watch exceptions and for those Breakpoint exceptions whose originating BREAK instruction's code does not have a special meaning. Keep Trap exceptions unaffected as these are not debug events. No existing user software is expected to examine signal codes for these signals as SI_KERNEL has been always used here. This change makes the MIPS port more like other Linux ports, which reduces the complexity and provides for performance improvement in GDB. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Pedro Alves <palves@redhat.com> Cc: Luis Machado <lgustavo@codesourcery.com> Cc: linux-mips@linux-mips.org Cc: gdb@sourceware.org Patchwork: https://patchwork.linux-mips.org/patch/12758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 3b143cca6e1397188f507a6c727f4108861ceb8b) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: inst.h: Rename cbcond{0,1}_op to pop{1,3}0_opPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The opcodes currently defined in inst.h as cbcond0_op & cbcond1_op are actually defined in the MIPS base instruction set manuals as pop10 & pop30 respectively. Rename them as such, for consistency with the documentation. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> (cherry picked from commit 1b492600068d5fbd033196ce2bdb28735a23747e) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: inst.h: Rename b{eq,ne}zcji[al]c_op to pop{6,7}6_opPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The opcodes currently defined in inst.h as beqzcjic_op & bnezcjialc_op are actually defined in the MIPS base instruction set manuals as pop66 & pop76 respectively. Rename them as such, for consistency with the documentation. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> (cherry picked from commit 1c66b79bb3b11942a98085fd89295cf6cddae41a) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Fix misspellings in comments.Adam Buchbinder2018-02-05
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12617/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 92a76f6d8545efc67f03278009e9a828bdad3419) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: math-emu: Add IEEE Std 754-2008 NaN encoding emulationMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement IEEE Std 754-2008 NaN encoding wired to the state of the FCSR.NAN2008 bit. Make the interpretation of the quiet bit in NaN data as follows: * in the legacy mode originally defined by the MIPS architecture the value of 1 denotes an sNaN whereas the value of 0 denotes a qNaN, * in the 2008 mode introduced with revision 5 of the MIPS architecture the value of 0 denotes an sNaN whereas the value of 1 denotes a qNaN, following the definition of the preferred NaN encoding introduced with IEEE Std 754-2008. In the 2008 mode, following the requirement of the said standard, quiet an sNaN where needed by setting the quiet bit to 1 and leaving all the NaN payload bits unchanged. Update format conversion operations according to the rules set by IEEE Std 754-2008 and the MIPS architecture. Specifically: * propagate NaN payload bits through conversions between floating-point formats such that as much information as possible is preserved and specifically a conversion from a narrower format to a wider format and then back to the original format does not change a qNaN payload in any way, * conversions from a floating-point to an integer format where the source is a NaN, infinity or a value that would convert to an integer outside the range of the result format produce, under the default exception handling, the respective values defined by the MIPS architecture. In full FPU emulation set the FIR.HAS2008 bit to 1, however do not make any further FCSR bits writable. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11477/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 90d53a91fbd0c5a0882c29fa4279a3d2d700c76d) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: non-exec stack & heap when non-exec PT_GNU_STACK is presentPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The stack and heap have both been executable by default on MIPS until now. This patch changes the default to be non-executable, but only for ELF binaries with a non-executable PT_GNU_STACK header present. This does apply to both the heap & the stack, despite the name PT_GNU_STACK, and this matches the behaviour of other architectures like ARM & x86. Current MIPS toolchains do not produce the PT_GNU_STACK header, which means that we can rely upon this patch not changing the behaviour of existing binaries. The new default will only take effect for newly compiled binaries once toolchains are updated to support PT_GNU_STACK, and since those binaries are newly compiled they can be compiled expecting the change in default behaviour. Again this matches the way in which the ARM & x86 architectures handled their implementations of non-executable memory. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: Maciej Rozycki <maciej.rozycki@imgtec.com> Cc: Faraz Shahbazker <faraz.shahbazker@imgtec.com> Cc: Raghu Gandham <raghu.gandham@imgtec.com> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13765/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 1a770b85c1f1c1ee37afd7cef5237ffc4c970f04) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Add IEEE Std 754 conformance mode selectionMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an `ieee754=' kernel parameter to control IEEE Std 754 conformance mode. Use separate flags copied from the respective CPU feature flags, and adjusted according to the conformance mode selected, to make binaries requesting individual NaN encoding modes accepted or rejected as needed. Update the initial setting for FCSR and, in the full FPU emulation mode, its read-only mask accordingly. Accept the mode selection requested for legacy processors as well. As with the EF_MIPS_NAN2008 ELF file header flag adjust both ABS2008 and NAN2008 bits at the same time, to match the choice made for hardware currently implemented. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11481/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 503943e0e52bd3fbf014aa1d838ced37adb43121) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Determine the presence of IEEE Std 754-2008 featuresMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Determine the presence of and the amount of control available over IEEE Std 754-2008 features. In the case of a hardware FPU being used examine the FIR register for the presence of the HAS2008 bit and then the FCSR register for the writability of the ABS2008 and NAN2008 bits and the hardwired state of each of these bits if read-only. Update the initial FCSR contents used for threads and the FCSR writability mask accordingly. For full FPU emulation and MIPS32 or MIPS64 processors make the FCSR ABS2008 and NAN2008 bits writable. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11480/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 93adeaf6dadcaed943a51ad9ea2d77e24e6d70a7) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Define the legacy-NaN and 2008-NaN featuresMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allocate CPU option bits and define macros for the legacy-NaN and 2008-NaN IEEE Std 754 MIPS architecture features. Unconditionally mark the legacy-NaN feature as present across hardware and emulated floating-point configurations. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11475/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 9519ef37a4a4e9c3c2d7d89ecbecfaf3c839208a) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: ELF: Interpret the NAN2008 file header flagMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Handle the EF_MIPS_NAN2008 ELF file header flag and refuse execution where there is no support in the FPU for the NaN encoding mode requested by a binary invoked. Ensure that the setting of the bit in the binary matches one in any intepreter used. Set the thread's initial FCSR contents according to the value of the EF_MIPS_NAN2008. Set the values of the FCSR ABS2008 and NAN2008 bits both to the same value if possible, to take the approach taken with existing FPU hardware into account. As of now all implementations have both bits hardwired to the same value, that is both are fixed at 0 or both are fixed at 1, even though the architecture allows for implementations where the amount of control implemented with each of these two individual bits is independent of each other. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11479/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 2b5e869ecfcb3112f7e1267cb0328f3ff6d49b18) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: ELF: Also pass any interpreter's file header to `arch_check_elf'Maciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also pass any interpreter's file header to `arch_check_elf' so that any architecture handler can have a look at it if needed. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Acked-by: Andrew Morton <akpm@linux-foundation.org> Acked-by: Al Viro <viro@zeniv.linux.org.uk> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11478/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit eb4bc076ff94b82fce04f6db061de597f71bd129) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Use a union to access the ELF file headerMaciej W. Rozycki2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite `arch_elf_pt_proc' and `arch_check_elf' using a union to access the ELF file header. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11474/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 2ed02dd415aee71a8bf4c621a9bd65c256642b96) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Use per-mm page to execute branch delay slot instructionsPaul Burton2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases the kernel needs to execute an instruction from the delay slot of an emulated branch instruction. These cases include: - Emulated floating point branch instructions (bc1[ft]l?) for systems which don't include an FPU, or upon which the kernel is run with the "nofpu" parameter. - MIPSr6 systems running binaries targeting older revisions of the architecture, which may include branch instructions whose encodings are no longer valid in MIPSr6. Executing instructions from such delay slots is done by writing the instruction to memory followed by a trap, as part of an "emuframe", and executing it. This avoids the requirement of an emulator for the entire MIPS instruction set. Prior to this patch such emuframes are written to the user stack and executed from there. This patch moves FP branch delay emuframes off of the user stack and into a per-mm page. Allocating a page per-mm leaves userland with access to only what it had access to previously, and compared to other solutions is relatively simple. When a thread requires a delay slot emulation, it is allocated a frame. A thread may only have one frame allocated at any one time, since it may only ever be executing one instruction at any one time. In order to ensure that we can free up allocated frame later, its index is recorded in struct thread_struct. In the typical case, after executing the delay slot instruction we'll execute a break instruction with the BRK_MEMU code. This traps back to the kernel & leads to a call to do_dsemulret which frees the allocated frame & moves the user PC back to the instruction that would have executed following the emulated branch. In some cases the delay slot instruction may be invalid, such as a branch, or may trigger an exception. In these cases the BRK_MEMU break instruction will not be hit. In order to ensure that frames are freed this patch introduces dsemul_thread_cleanup() and calls it to free any allocated frame upon thread exit. If the instruction generated an exception & leads to a signal being delivered to the thread, or indeed if a signal simply happens to be delivered to the thread whilst it is executing from the struct emuframe, then we need to take care to exit the frame appropriately. This is done by either rolling back the user PC to the branch or advancing it to the continuation PC prior to signal delivery, using dsemul_thread_rollback(). If this were not done then a sigreturn would return to the struct emuframe, and if that frame had meanwhile been used in response to an emulated branch instruction within the signal handler then we would execute the wrong user code. Whilst a user could theoretically place something like a compact branch to self in a delay slot and cause their thread to become stuck in an infinite loop with the frame never being deallocated, this would: - Only affect the users single process. - Be architecturally invalid since there would be a branch in the delay slot, which is forbidden. - Be extremely unlikely to happen by mistake, and provide a program with no more ability to harm the system than a simple infinite loop would. If a thread requires a delay slot emulation & no frame is available to it (ie. the process has enough other threads that all frames are currently in use) then the thread joins a waitqueue. It will sleep until a frame is freed by another thread in the process. Since we now know whether a thread has an allocated frame due to our tracking of its index, the cookie field of struct emuframe is removed as we can be more certain whether we have a valid frame. Since a thread may only ever have a single frame at any given time, the epc field of struct emuframe is also removed & the PC to continue from is instead stored in struct thread_struct. Together these changes simplify & shrink struct emuframe somewhat, allowing twice as many frames to fit into the page allocated for them. The primary benefit of this patch is that we are now free to mark the user stack non-executable where that is possible. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: Maciej Rozycki <maciej.rozycki@imgtec.com> Cc: Faraz Shahbazker <faraz.shahbazker@imgtec.com> Cc: Raghu Gandham <raghu.gandham@imgtec.com> Cc: Matthew Fortune <matthew.fortune@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13764/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 432c6bacbd0c16ec210c43da411ccc3855c4c010) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | BACKPORT: exit_thread: remove empty bodiesJiri Slaby2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define HAVE_EXIT_THREAD for archs which want to do something in exit_thread. For others, let's define exit_thread as an empty inline. This is a cleanup before we change the prototype of exit_thread to accept a task parameter. [akpm@linux-foundation.org: fix mips] Signed-off-by: Jiri Slaby <jslaby@suse.cz> Cc: "David S. Miller" <davem@davemloft.net> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: "James E.J. Bottomley" <jejb@parisc-linux.org> Cc: Aurelien Jacquiot <a-jacquiot@ti.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chen Liqin <liqin.linux@gmail.com> Cc: Chris Metcalf <cmetcalf@mellanox.com> Cc: Chris Zankel <chris@zankel.net> Cc: David Howells <dhowells@redhat.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Haavard Skinnemoen <hskinnemoen@gmail.com> Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Helge Deller <deller@gmx.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jeff Dike <jdike@addtoit.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Jiri Slaby <jslaby@suse.cz> Cc: Jonas Bonn <jonas@southpole.se> Cc: Koichi Yasutake <yasutake.koichi@jp.panasonic.com> Cc: Lennox Wu <lennox.wu@gmail.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Mark Salter <msalter@redhat.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Matt Turner <mattst88@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Mikael Starvik <starvik@axis.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Rich Felker <dalias@libc.org> Cc: Richard Henderson <rth@twiddle.net> Cc: Richard Kuo <rkuo@codeaurora.org> Cc: Richard Weinberger <richard@nod.at> Cc: Russell King <linux@arm.linux.org.uk> Cc: Steven Miao <realmz6@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> (cherry picked from commit 5f56a5dfdb9bcb3bca03df59980d4d2f012cbb53) Conflicts: arch/powerpc/kernel/process.c arch/xtensa/Kconfig Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Make flush_threadRalf Baechle2018-02-05
| | | | | | | | | | | | | | | | Avoids function calls to an empty function. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 04cc89d120f94131de89a6e20da27016db4782ce) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
* | UPSTREAM: MIPS: Properly disable FPU in start_thread()James Hogan2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | start_thread() (called for execve(2)) clears the TIF_USEDFPU flag without atomically disabling the FPU. With a preemptive kernel, an unfortunately timed preemption after this could result in another task (or KVM guest) being scheduled in with the FPU still enabled, since lose_fpu_inatomic() only turns it off if TIF_USEDFPU is set. Use lose_fpu(0) instead of the separate FPU / MSA management, which should do the right thing (drop FPU properly and atomically without saving state) and will be more future proof. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12302/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit 76e5846d3bdf59eb1010d5607003da2dc3910bb1) Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-26 01:32:36 +0000