| Commit message (Collapse) | Author | Age |
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Currently qsee_ipc_irq_bridge driver is using an incorrect clear mask
when it handles an incoming level triggered interrupt. This causes
an interrupt storm.
Update the IRQ clear mask entry to appropriate value.
CRs-Fixed: 1053076
Change-Id: I6bfe7aecd73a13401a218e89874f2225ac91d18f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
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The UFS driver does not need the GDSC driver to set the core
and peripheral memory retention bits for certain UFS clocks
on it's behalf. Remove doing so.
CRs-Fixed: 1052994
Change-Id: I845eb2014056203d203ee6be66de0cc161c2dedb
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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Add jdi 1080p video mode panel config file and necessary configs
to enable it in msmcobalt MTP and CDP.
Change-Id: I51ac777abdf0d95c74535c20afbbd555c31c358a
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
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Add necessary power and panel timings to support sharp 1080p
cmd mode panel in msmcobalt. Add support for it to work with
both CDP and MTP.
Change-Id: I145da5e01bcdb3aa28804e851c97c00fa4d39114
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
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Add all available interrupts to the mpm gic map list such that new
enabled interrupts are automatically added to bypass list and do not
block XO shutdown.
CRs-fixed: 1044164
Change-Id: Ib68da5c234ab270c401fa54adc99d4416a3cb987
Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
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Enable to lower the battery current FCC based on the system thermal
levels. At level
- 0: no mitigation
- 1: reduce FCC to 1500mA
- 2: reduce FCC to 1000mA
- 3: reduce FCC to 500mA
- 4: disable charging
CRs-Fixed: 1041206
Change-Id: Idcffb2d897615dc2ba842b55086d5fd583cb19f6
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Add the new clocks and update the clock ids for GCC, GPU, MMSS clock
controllers. Also add the RPM clocks which are supported and would be
used by the clients for all clock operations for RPM controlled clocks.
There are separate MMSS and GPU clock controllers, so add the dummy
controllers for the same.
Change-Id: I5a98b6128f5d54163ab5d03c4c023a748e6a4e95
Signed-off-by: Taniya Das <tdas@codeaurora.org>
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Set USB core clock frequency to recommended value to allow SVS mode
when cable is connected.
Change-Id: Ia452476bd3bb7316a86efd08fed52c54f3efa34e
Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
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This change adjusts the bandwidth limits for the
mdp core in the v2 of msmcobalt.
Change-Id: I3559ed2b6984ac9cec8e219f59f634410aaf57c9
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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This change adjusts the ot limits in the mdp vbif
for msmcobalt by removing the xin ot limits and
adding the axi ot limits to the mdp vbif.
CRs-Fixed: 1040746
Change-Id: I365976021dcf02fbc3687091371d7d72cb711605
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
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Add the block reset clocks which will be used by clients to
assert/deassert these clocks using the reset controller framework.
Change-Id: I3e9f7f85bf1faf0e1bb501196ba9d7e197111a03
Signed-off-by: Taniya Das <tdas@codeaurora.org>
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There are some implementation defined registers that need to be
programmed to certain values on cobalt. Add them.
CRs-Fixed: 1037191
Change-Id: I6d9d92f7291df2d92f9faf3c4e80b832422b3ddf
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
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Add the QDSS STM property to the device tree so
that data can be logged from the GPU to the debug
bus when available.
CRs-Fixed: 1031648
Change-Id: I754c85a2ed02d0b1e40fd1e27b10ff84c463ac83
Signed-off-by: Jonathan Wicks <jwicks@codeaurora.org>
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Update TLMM base address to match new address.
Change-Id: Ie0c46cbbcbc3edabd5e0f867b4393a27e55db9f5
Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
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Hardware characterization has shown that some parts require
higher voltages in order to operate consistently. Increase
the ceiling voltage for all corners so that they are able to
operate at higher voltages. This applies to all CPR revisions
except 0.
Change-Id: Ie9d4e825e5c6040036642cdaf22d1f67b6129685
CRs-Fixed: 1050071
Signed-off-by: David Collins <collinsd@codeaurora.org>
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G-Link SPI Transport is used to communicate with external audio codec.
Add G-Link SPI Transport device to support that configuration.
CRs-Fixed: 1045916
Change-Id: I97ca857c21d8873574a180d289e2fbca29c8a891
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
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QOS values are programmed wrongly for msmcobalt. This can
affect Venus performance. This change fixes the same.
CRs-Fixed: 1046678
Change-Id: I6d474c2279422abe63ad625f35809fe156e8c465
Signed-off-by: Praneeth Paladugu <ppaladug@codeaurora.org>
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Adding DFPS support for nt35597 dualmipi wqxga video mode panel based on
vertical porch adjustment.
CRs-Fixed: 1047142
Change-Id: Ida3a175d2d1d9d4c2b5bed1e9998dc1af4f626d0
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
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When continuous splash screen feature is enabled, the display
needs to be kept alive during the kernel boot up. Add proxy vote
for MDSS GDSC to prevent it from being turned off until the display
driver hand off can be executed.
CRs-Fixed: 1037857
Change-Id: Ie111c5d4fb401a04620809b84ba6a7c2e7d1ce88
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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Reserve memory for the display framebuffer in HLOS for continuous
splash feature on msmcobalt target. This memory buffer would be
configured by the bootloader and needs to be retained until the
first frame update in kernel.
CRs-Fixed: 1037857
Change-Id: Ifbcc1454a1c85eb0163fed969a0c8ceb21d23245
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
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DMIC clock on ECPP(Echo cancellation Ping-Pong) path can
run at 1.2MHz. Change configures DMIC clock rate for ECPP
path in codec device node.
CRs-fixed: 1022917
Change-Id: Ie7a0a5c57af608cdb42fac9f0f95fe427de8ea1d
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>
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Add MDSS Display-Port device node for msmcobalt which is needed to drive
any external display that supports DP interface. Add the
msmcobalt-CDP/MTP specific GPIO entries needed for display-port.
Change-Id: I61592c167345ebec4cde07f0a72ef059f186b84a
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
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New battery module is used on QRD msmcobalt SKUK device, add the battery
data for it.
Change-Id: I4a1888fb2302572720260ffea200e5fe6d79a7ba
Signed-off-by: Fenglin Wu <fenglinw@codeaurora.org>
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There's currently a placeholder stream ID of "1" in the PCIe RC device
tree node. The PCIe RC doesn't actually attach and doesn't need a
stream ID though, the "1" was put there to get around an error caused by
the fact that #iommu-cells was equal to 1 for the anoc1_smmu, even
though it should have actually been 0.
Fix all this by making #iommu-cells = <0> for the anoc1 SMMU and
removing the bogus placeholder stream ID.
CRs-Fixed: 1036401
Change-Id: I73ff6d6b081b1ee00c8e8ebea42e86160b35aa37
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>
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change to use SW AEAD and HMAC algorithms with ARMv8 crypto
extensions by default on msmcobalt, as they have better performances
than algorithms using HW crypto engines.
Change-Id: If68b68374bfabcdef7ecbf245b72b12c4734f811
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
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Modify the sleep set GPIO bias for UART_3. This will help lower leakage
once the usecase for UART_3 has ended.
Change-Id: I50d918197a4cd0b503dff78e7d4ba89518c1d1c2
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
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