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* | | thermal: tsens: TSENS driver fixupsSiddartha Mohanadoss2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TSENS Thermal driver. Include support to activate a trip type and mode. This snapshot is taken as of msm-3.14 commit 3bc54cf86b (Merge "msm: camera: Add dummy sub module in sensor pipeline") Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org> Conflicts: drivers/thermal/Kconfig drivers/thermal/Makefile include/linux/thermal.h Change-Id: Ie8a089afc0cf9e45ac000dff425a3e6206c1b9b1
* | | uio: Add snapshot of MSM sharedmem driverNikhilesh Reddy2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a snapshot of the MSM sharedmem driver as of msm-3.14 commit: 149717c082aab8168283b7e0c23d8bd5a45b1999 ( uio: msm_sharedmem: Add custom mmap ) The following changes are included: 02d55287 uio: msm_sharedmem: Restrict debugfs write to root. de961fc7 uio: msm_sharedmem: Return ENOMEM if the shared mem addr is zero. b974ce64 uio: msm_sharedmem: Add addtional information to debugfs c46af547 uio: msm_sharedmem: Add support for dynamic shared memory allocation Change-Id: I49902f018bde1d59d41027b7e46268cc17231a3e Signed-off-by: Nikhilesh Reddy <reddyn@codeaurora.org>
* | | soc: qcom: Add snapshot of QMIKarthikeyan Ramasubramanian2016-03-22
| | | | | | | | | | | | | | | | | | | | | This snapshot is taken as of msm-3.18 commit e70ad0cd (Promotion of kernel.lnx.3.18-151201.) Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
* | | net: ipc_router: Add snapshot of IPC RouterKarthikeyan Ramasubramanian2016-03-22
| | | | | | | | | | | | | | | | | | | | | This snapshot is taken as of msm-3.18 commit e70ad0cd (Promotion of kernel.lnx.3.18-151201.) Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
* | | trace: Add snapshot of ipc_logging driverKarthikeyan Ramasubramanian2016-03-22
| | | | | | | | | | | | | | | | | | | | | This snapshot is taken as of msm-3.18 commit e70ad0cd (Promotion of kernel.lnx.3.18-151201.) Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
* | | smp: Allow booting a specific subset of CPUsStepan Moskovchenko2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a heterogenous multiprocessor system, specifying the 'maxcpus' parameter on the kernel command line does not provide sufficient control over which CPUs are brought online at kernel boot time, since CPUs may have nonuniform performance characteristics. Thus, we introduce a 'boot_cpus' command line argument, allowing the user to explicitly specify the list of CPUs that shall be brought online during kernel boot. Change-Id: I5f119e23202660941fa7be8c4e6dd91a82365451 Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> [abhimany: resolve trivial merge conflicts] Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* | | soc: qcom: add snapshot of PIL, SSR and SYSMON drivers/librariesDavid Keitel2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a snapshot of PIL, SSR and SYSMON drivers and libraries as of msm-3.18 commit 5cef33a285e91869cebe40a25e6294ae1e5fc9cc (Merge "ASoC: msm: Update the AFE clock API support") Change-Id: Ibebddee32b15fbcb5b18cceac43769d3309e609c Signed-off-by: David Keitel <dkeitel@codeaurora.org>
* | | usb: dwc3: Allow controller to enter LPM in bus suspendJack Pham2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a DT property that decides whether to allow controller low power mode upon bus suspend, which will be invoked by the OTG state machine. It is also required to take the core out of LPM in case ep_queue is called by the upper layers. In this case, remote wakeup sequence will be initiated once the core is out of LPM. [jackp@codeaurora.org: Squashed with dwc3 changes from "usb: dwc3: Add new OTG state OTG_STATE_B_SUSPENDED"] Signed-off-by: Jack Pham <jackp@codeaurora.org>
* | | usb: dwc3: core: Disable internal clock gating conditionallyMayank Rana2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently USB DWC3 controller's internal clock gating is disabled unconditionally. In few platform, it is possible to enable internal clock gating with controller. Hence this change adds support to disable this functionality conditionally using "snps,disable-clk-gating" device tree property. With this change USB controller's internal clock gating is enabled by default. CRs-Fixed: 851877 Change-Id: I17d43a23d3bff0cb516b952c35c4a13af53f7777 Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* | | USB: dwc3: Add support for fixing superspeed enumeration issueVijayavardhan Vennapusa2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting SSPHY SUSP bit (bit 17) in GUSB3PIPECTL(0) register might cause device enumerating at high speed mode instead of superspeed mode on some platforms. Hence add workaround by clearing the SSPHY SUSP bit during disconnect and setting it after it is configured to fix this enumeration issue on those platforms. Also add support for disabling U1 and U2 low power modes which could also affect this enumeration issue. CRs-Fixed: 637902 Change-Id: I8668ced09a88b77f37265ab15e89fa9e964bfbe9 Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org> [jackp@codeaurora.org: only add u1/u2 disable bits] Signed-off-by: Jack Pham <jackp@codeaurora.org>
* | | usb: dwc3: Set elastic buffer modeJack Pham2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a device tree property to allow setting the GUSB3PIPECTRL Elastic Buffer Mode (bit 0). By default set the buffer to half-full to work around SuperSpeed link errors. If the property is set, set the buffer to be nominally empty. This change is a combination of two previous commits: USB: dwc3: core: Set elastic buffer mode to zero Currently elastic buffer mode in GUSB3PIPE_CTRL(0) register is set to one. This results in high link error rates and superspeed mode transfer failures if VDDCX is at super turbo mode voltage 1.05V. Hence set elastic buffer mode to zero in GUSB3PIP_CTRL register. usb: dwc3: Do not set half-full elastic buffer On some platforms setting of half-full elastic buffer will cause data corruption and hence we need to avoid this setting. Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org> Signed-off-by: Maya Erez <merez@codeaurora.org> Signed-off-by: Jack Pham <jackp@codeaurora.org>
* | | usb: phy: add snapshot of phy-msm driversJack Pham2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a snapshot of phy-msm-{hsusb,ssusb,ssusb-qmp,qusb}.c taken as of msm-3.18 commit 9da4ddc18727 (Merge "clk: msm: clock-gcc: Associate gfx rail voting with gfx3d branch") Also replaced ARCH_MSM dependency with ARCH_QCOM in the Kconfig. Signed-off-by: Jack Pham <jackp@codeaurora.org>
* | | usb: dwc3: msm: Add snapshot of DWC3 MSM driversJack Pham2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dwc3-msm.c and associated driver files. Note these are based on the downstream implementation and will coexist (for the time being) with dwc3-qcom glue driver until they can eventually be merged. This snapshot is taken as of msm-3.18 commit a3883c356869 (Merge "input: touchscreen: correct condition checks in ITE tech touch driver") Signed-off-by: Jack Pham <jackp@codeaurora.org>
* | | drivers: dma-removed: introduce no-map-fixupShiraz Hashim2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some use cases, it is not known beforehand, how much removed (carve-out) region size must be reserved. Hence the reserved region size might need to be adjusted to support varying use cases. In such cases maintaining different device tree configurations to support varying carve-out region size is difficult. Introduce an optional device tree property, to reserved-memory, "no-map-fixup" which works in tandem with "removed-dma-pool" compatibility that tries to shrink and adjust the removed area on very first successful allocation. At end of which it returns the additional (unused) pages from the region back to the system. Point to note is this that this adjustment is done on very first allocation and thereafter the region size is big enough only to support maximum of first allocation request size. This fixup is attempted only once upon first allocation and never after that. Clients can allocate and free from this region as any other dma region. As the description suggests this type of region is specific to certain special needs and is not to be used for common use cases. Change-Id: I31f49d6bd957814bc2ef3a94910425b820ccc739 Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
* | | mm: slub: Panic instead of restoring corrupted bytesDavid Keitel2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Resiliency of slub was added for production systems in an attempt to restore corruptions and allow production environments to continue to run. In debug setups, this may no be desirable. Thus rather than attempting to restore corrupted bytes in poisoned zones, panic to attempt to catch more context of what was going on in the system at the time. Add the CONFIG_SLUB_DEBUG_PANIC_ON defconfig option to allow debug builds to turn on this panic option. Change-Id: I01763e8eea40a4544e9b7e48c4e4d40840b6c82d Signed-off-by: David Keitel <dkeitel@codeaurora.org>
* | | ksm: Provide support to use deferred timers for scanner threadChintan Pandya2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | KSM thread to scan pages is getting schedule on definite timeout. That wakes up CPU from idle state and hence may affect the power consumption. Provide an optional support to use deferred timer which suites low-power use-cases. To enable deferred timers, $ echo 1 > /sys/kernel/mm/ksm/deferred_timer Change-Id: I07fe199f97fe1f72f9a9e1b0b757a3ac533719e8 Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
* | | common: DMA-mapping: Add strongly ordered memory attributeLaura Abbott2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Strongly ordered memory is occasionally needed for some DMA allocations for specialized use cases. Add the corresponding DMA attribute. Change-Id: Idd9e756c242ef57d6fa6700e51cc38d0863b760d Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
* | | usb: gadget: Move diag dload handling to f_diag driverJack Pham2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upon Diag function bind, the DLOAD memory region should be updated with the USB PID and serial number in order to support a persistent connection with the PC if the device reboots into download mode. This functionality need not be handled in the android.c driver. The only reason it is there is to be able to locate the IO address which is specified in device tree. Since this can be done from the Diag function driver directly, move the handling there. The address itself can be specified under the "qcom,msm-imem" parent with its own "qcom,msm-imem-diag-dload" compatible string. For now, allow falling back to retrieving the address from the "android_usb" for backwards compatibility until the device tree files are updated. Change-Id: I0d6d1dac0f12b7890220d857227ae45c9258c1f2 Signed-off-by: Jack Pham <jackp@codeaurora.org>
* | | power: reset: msm: Define reg-names for the qcom,pshold deviceStepan Moskovchenko2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the qcom,pshold device now supports up to two distinct register definitions, add the 'reg-names' property to assign names to the memory resources, rather than relying on resource numbering. Change-Id: Ie0bc5eae0119901239efae05357ae107a112b87a Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
* | | power: reset: msm: Allow configuring reset type via secure I/OStepan Moskovchenko2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some targets require that the Download Mode / EDL configuration be performed by means of a Secure I/O write to the TCSR_BOOT_MISC_DETECT register rather than through a generic SCM operation. Provide a mechanism for specifying the address of this register in the device tree, to use as a fallback method if the generic SCM call to set the download mode configuration is unavailable. This is necessary to comply with atomicity requirements of the secure environment. Change-Id: I5d3fcb48b0b47815d4839a3b722b0462a1bca087 Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
* | | soc: qcom: Add snapshot of SMP2P DriverKarthikeyan Ramasubramanian2016-03-22
| | | | | | | | | | | | | | | | | | | | | This snapshot is taken as of msm-3.18 commit e70ad0cd (Promotion of kernel.lnx.3.18-151201.) Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
* | | block: Add test-iosched schedulerMaya Erez2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | The test scheduler allows testing a block device by dispatching specific requests according to the test case and declare PASS/FAIL according to the requests completion error code Change-Id: Ief91f9fed6e3c3c75627d27264d5252ea14f10ad Signed-off-by: Maya Erez <merez@codeaurora.org>
* | | phy: qcom-ufs: add UFS PHY support for msmcobalt rumi platformYaniv Gardi2016-03-22
| | | | | | | | | | | | | | | | | | | | | Add support for QRBTC V2 UFS PHY that is used in msmcobalt rumi platform. Change-Id: I21ad3f0db23ea16d05ba40593cc7650e1a443702 Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
* | | phy: qcom-ufs: add support in UFS PHY for msmcobalt platformYaniv Gardi2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for new QCOM UFS PHY that is used in future platforms. Change-Id: I53f162738668ae9f24f5edb9c42a17f947e68b40 Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflict] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* | | scsi/phy: Remove orphaned files after renamingVenkat Gopalakrishnan2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | Delete renamed orphan files after rebasing 3.18 ufs driver changes onto 4.4 ufs driver. Change-Id: Id241ad01bbb0fa74e209c66f8a2d97c05088e33b Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* | | scsi: ufs: update pm qos implementationGilad Broner2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current UFS PM QoS design and implementation do not seem to give the desired increase in performance. This change revisits the PM QoS implementation trying to improve performance by making the following changes: * de-couple voting from clock scaling decision so voting occurs from the first request and unvoting on the completion of the last request regardless to clock scaling state. Otherwise, suspending the PM QoS voting during the time it takes to decide on clock up-scaling, seems to degrade random access performance. * vote on a per-cluster basis by inspecting the request object's cpu field. This follows the soft-irq allocation scheme in the block layer, so the cpu to which the block layer schedules the soft-irq will not be put into deep LPM. We should note that PM QoS voting using cpu mask for specific cpus is a feature of the qcom specific PM QoS implementation. Change-Id: I427d202aeb45cd284a3bb128e26e519212614801 Signed-off-by: Gilad Broner <gbroner@codeaurora.org> Signed-off-by: Krishna Konda <kkonda@codeaurora.org> [venkatg@codeaurora.org: resolved merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* | | clk: msm: Add documentation for gdsc regulator driverDevesh Jhunjhunwala2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a snapshot of gdsc-regulator documentation as of msm-3.18 commit: e70ad0cd5efdd9dc91a77dcdac31d6132e1315c1 (Promotion of kernel.lnx.3.18-151201.) Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
* | | scsi: ufs-qcom: change device reference clock controlGilad Broner2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As of HW major version 2, bit 'UFS_DEV_REF_CLK_EN' which is used to gate/ungate the ref_clk to external UFS device, was moved into the UFS register space to UFS_CFG1 register. This change adds support to appropriately control the device reference clock and it also adds the missing documentation for the device reference clock control register address space. Change-Id: I66a6a75dc5a1cf130b1cee90ae20f9f950edfb3a Signed-off-by: Gilad Broner <gbroner@codeaurora.org> [subhashj@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* | | scsi: ufs-qcom: add number of lanes per directionGilad Broner2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Different platform may have different number of lanes for the UFS link. Add parameter to device tree specifying how many lanes should be configured for the UFS link. Change-Id: Ida8b13b916f76b3cc7afd3da3d04219e95627678 Signed-off-by: Gilad Broner <gbroner@codeaurora.org> [subhashj@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* | | scsi: ufs: define cpu affinity mask for PM QoS votingGilad Broner2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PM QoS request type PM_QOS_REQ_AFFINE_CORES specifies for which CPU cores the voting is applied to by the cpu affinity mask. This change defines the cpu mask to be used for the voting in the device tree node so it can be customized for each target. Change-Id: I004dea47b42eaf3cdf0489427b2bb894c9982f22 Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
* | | scsi: ufs: add cpu-dma latency PM QOS requestGilad Broner2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PM QOS cpu-dma latency request to the driver. Latency parameter value is taken from the device tree node using an optional parameter 'qcom,cpu-dma-latency-us'. Unless specified, a default of 200us is used. Change-Id: I3e10da9e65fc7324897c866b0c2a40cc5e6ca070 Signed-off-by: Gilad Broner <gbroner@codeaurora.org> [subhashj@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* | | scsi: ufs-qcom: add support to control the device ref_clkSubhash Jadavani2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Qualcomm platforms, there will be many consumers of the source clock which also supply ref_clk to UFS Device. So even if generic UFS driver (ufshcd) vote to turn off the source ref_clk, it's very likely that device ref_clk is still running. Hence some of the qualcomm chipsets have separate control bit to gate & ungate the UFS ref_clk to device. This control bit is part of the TLMM register adddress space so it can't be simulated at clock control bit which means UFS qcom driver has to manually control this bit to gate or ungate the device ref_clk. This change adds support for the same. Change-Id: I3ee1187292eaadfdb552d33c2bb6f58922c9e501 [subhashj@codeaurora.org: resolved merge conflicts, dropped changes to msm8994.dtsi] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflicts, drop changes to include/linux/phy/phy-qcom-ufs.h] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* | | scsi: ufs: add Inline Crypto Engine (ICE) support to UFSMaya Erez2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In-order to enhance storage encryption performance, an Inline Cryptographic Engine is introduced to UFS. This patch adds in-line encryption capabilities to the UFS driver. Change-Id: Id3cb913498809b32e1f7eba96395b05a9bf3219f Signed-off-by: Noa Rubens <noag@codeaurora.org> Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Signed-off-by: Maya Erez <merez@codeaurora.org> [subhashj@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* | | scsi: ufs: add option to change default UFS power management levelSubhash Jadavani2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UFS device and link can be put in multiple different low power modes hence UFS driver supports multiple different low power modes. By default UFS driver selects the default (optimal) low power mode (which gives moderate power savings and have relatively less enter and exit latencies) but we might have to tune this default power mode for different chipset platforms to meet the low power requirements/goals. Hence this patch adds option to change default UFS low power mode (level). Change-Id: I45aaae9f46beb3b5d38bcc6dcbd728e79677276c Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* | | ARM: dts: msm: rename attributes to more generic namesYaniv Gardi2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this change the "compatible" attribute in dts files of ufsphy node and the "phy-names" attribute in ufs node are changed to a more generic name. This is done for apq8084 and for msm8994 targets. Change-Id: I46176459e9bc877456489e4728b86eecb2c16261 Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> [subhashj@codeaurora.org: resolved merge conflicts & dropped changes to apq8084.dtsi & msm8994.dtsi] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* | | scsi: ufs-msm: re-factoring the ufs phy to support various physYaniv Gardi2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This re-factor is required in order to provide a robust way to support multiple ufs phys. It also creates a better separation between ufs-msm block, ufs-msm-phy block and the specific phy blocks. In this change a generic phy handle is created, using the phy driver framework. Two ufs phys are currently supported: 28nm and 20nm This change also includes the required DT changes as in this case, the driver changes and the DT changes must be placed within the same change. Change-Id: I3aa7ed942ed7b54f3a29c9b9dbdeff1861079066 Signed-off-by: Noa Rubens <noag@codeaurora.org> Signed-off-by: Gilad Broner <gbroner@codeaurora.org> Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> [gbroner@codeaurora.org: fix merge conflicts in apq8084 and msm8994 device tree files] Signed-off-by: Gilad Broner <gbroner@codeaurora.org> [subhashj@codeaurora.org: resolved merge conflicts, dropped changes to msm8994.dtsi and fixed compilation errors] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* | | scsi: ufs-msm: Add bus bandwidth voting supportSujit Reddy Thumma2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The UFS host controller on MSM chipsets transfer data over System NoC to the DDR memory. Add bus bandwidth voting support based on the speed modes the host communicates with the device so as to provide optimum throughput while transferring data over the bus. Change-Id: I1b407975984985fa108aa9373e2eab08b9027df4 Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org> [gbroner@codeaurora.org: fix merge conflicts - apq8084.dtsi file location has been previously changed and is already up to date] Signed-off-by: Gilad Broner <gbroner@codeaurora.org> [subhashj@codeaurora.org: resolved trivial merge conflicts and also fixed compilation error] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* | | scsi: ufs: Add UFS host PHY driver for MSM targetsSujit Reddy Thumma2016-03-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MSM UFS host PHY driver which binds with UFSHCD platform driver exposing vendor specific operations to initialize the PHY. Since the controller and PHY are tightly coupled in the system, some of the MSM specific controller register configuration is also applied inline while initializing PHY. Add a new compatible property "qcom,ufshc" which specifies the UFS host controller on MSM platforms. The UFS controller driver binds with UFS PHY driver using the phandle reference of PHY devicetree node. Change-Id: If695a844d03268151c6c846bdfa6cee8ff84491b Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org> [subhashj@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [venkatg@codeaurora.org: resolved trivial merge conflicts] Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* | | QoS: Enhance framework to support cpu/irq specific QoS requestsPraveen Chidambaram2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QoS request for CPU_DMA_LATENCY can be better optimized if the request can be set only for the required cpus and not all cpus. This helps save power on other cores, while still gauranteeing the quality of service. Enhance the QoS constraints data structures to support target value for each core. Requests specify if the QoS is applicable to all cores (default) or to a selective subset of the cores or to a core(s), that the IRQ is affine to. QoS requests that need to track an IRQ can be set to apply only on the cpus to which the IRQ's smp_affinity attribute is set to. The QoS framework will automatically track IRQ migration between the cores. The QoS is updated to be applied only to the core(s) that the IRQ has been migrated to. Idle and interested drivers can request a PM QoS value for a constraint across all cpus, or a specific cpu or a set of cpus. Separate APIs have been added to request for individual cpu or a cpumask. The default behaviour of PM QoS is maintained i.e, requests that do not specify a type of the request will continue to be effected on all cores. Requests that want to specify an affinity of cpu(s) or an irq, can modify the PM QoS request data structures by specifying the type of the request and either the mask of the cpus or the IRQ number depending on the type. Updating the request does not reset the type of the request. The userspace sysfs interface does not support CPU/IRQ affinity. Change-Id: I09ae85a1e8585d44440e86d63504ad734e8e3e36 Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org> Conflicts: kernel/power/qos.c
* | | spmi: pmic_arb: block access of invalid read and writesAbhijeet Dharmapurikar2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The system crashes due to bad access when reading from an non configured peripheral and when writing to peripheral which is not owned by current ee. This patch verifies ownership to avoid crashing on write. For reads, since the forward mapping table, data_channel->ppid, is towards the end of the block, we use the core size to figure the max number of ppids supported. The table starts at an offset of 0x800 within the block, so size - 0x800 will give us the area used by the table. Since each table is 4 bytes long (core_size - 0x800) / 4 will gives us the number of data_channel supported. This new protection is functional on hw v2. Change-Id: I74e3452963a7dda9a8c8aaef76de3117cabc454b Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
* | | gpio-usbdetect: use gpio instead of irqAbhijeet Dharmapurikar2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current driver uses irq_read_line api which is not standard. Instead use a gpio and register for an interrupt when it changes states. And upon a change in state interrupt is received, read the gpio state to determine whether it is high or low. Change-Id: Ie4b1226cedfb44e65a84349da4b3eef5fe988dff Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
* | | soc: spm: Snapshot of the SPM driver from 3.18 kernelAbhijeet Dharmapurikar2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a snapshot of the SPM driver from 3.18 kernel. The upstream spm.c file is used as a idle driver. So updated spm driver from 3.18 kernel to msm-spm.c on 4.4 kernel. Change-Id: I73b020214fdcc7eb695cf8f5b52cf7885a0a10cd Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
* | | spmi_devices: change to platform_devicesAbhijeet Dharmapurikar2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change to using upstream spmi bus architecture. All the spmi devices, marked by spmi-dev-container, become platform devices. spmi-slave-container devices become spmi_devices each representing a slave. The read/write functions use regmap api's instead of calls to spmi_ext_register_read/write() implemented by the spmi bus. This regmap is instantiated per slave. The spmi bus helper functions like spmi_get_irq get changed to their platform bus equivalents. Change Kconfig files include * Remove dependence on OF_SPMI, MSM_QPNP_INT * There were few places where an earlier commit dcc2aedc80746acee589e4b47d3e6adf5d3ec253 missed adding dependence on SPMI along with MSM_SPMI. Fix them. * Add depends on ARCH_MSM. ARCH_MSM is used for internal builds. Change the nodes in DTSI files to confirm to the modified drivers. Update their binding docs to drop spmi-dev-container and spmi-slave-container; Finally update defconfig to use upstream SPMI. Change-Id: Ic85bff27c09c84b152cb38acbc3cadd05c0ec57a Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
* | | bif: Add snapshot of bif-core framework and qpnp-bsi driverOsvaldo Banuelos2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This snapshot is taken as of msm-3.18 commit bd4743e (Merge "ARM: dts: msm: Add display configuration for msmgold") Change-Id: I6f9c2fb7bcede6196da26a49dbd6aab598a0b5a9 Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org> Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
* | | qpnp: Add snapshot of some qpnp, regulator and charger driversAbhijeet Dharmapurikar2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | This snapshot is taken as of msm-3.18 commit 9da4ddc (Merge "clk: msm: clock-gcc: Associate gfx rail voting with gfx3d branch") Change-Id: Idd2f467f1f1863a156d1757589dfe78158f0e43f Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
* | | soc: qcom: Add snapshot of G-Link driverKarthikeyan Ramasubramanian2016-03-01
| | | | | | | | | | | | | | | | | | | | | This snapshot is taken as of msm-3.18 commit e70ad0cd (Promotion of kernel.lnx.3.18-151201.) Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
* | | pinctrl: add and update new functions as per msm8996v3Sanrio Alvares2016-03-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | Per the new msm8996v3 design add newly added gpio functions and update positions of existing ones. Add gpio bindings documentation. Change-Id: Id2ccd471afe1d8e43ff625c1c24fdbf666342cd8 Signed-off-by: Sanrio Alvares <salvares@codeaurora.org>
* | | Documentation: Snapshot of msm devicetree bindings from msm-3.18Rohit Vaswani2016-03-01
| | | | | | | | | | | | Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
* | | sysctl: add boot_reason and cold_boot sysctl entries for arm64David Collins2016-03-01
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | Define boot_reason and cold_boot variables in the arm64 version of setup.c so that arm64 targets can export the boot_reason and cold_boot sysctl entries. This feature is required by the qpnp-power-on driver. Change-Id: Id2d4ff5b8caa2e6a35d4ac61e338963d602c8b84 Signed-off-by: David Collins <collinsd@codeaurora.org> [osvaldob: resolved trival merge conflicts] Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* | FROMLIST: mm: mmap: Add new /proc tunable for mmap_base ASLR.dcashman2016-02-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (cherry picked from commit https://lkml.org/lkml/2015/12/21/337) ASLR only uses as few as 8 bits to generate the random offset for the mmap base address on 32 bit architectures. This value was chosen to prevent a poorly chosen value from dividing the address space in such a way as to prevent large allocations. This may not be an issue on all platforms. Allow the specification of a minimum number of bits so that platforms desiring greater ASLR protection may determine where to place the trade-off. Bug: 24047224 Signed-off-by: Daniel Cashman <dcashman@android.com> Signed-off-by: Daniel Cashman <dcashman@google.com> Change-Id: Ibf9ed3d4390e9686f5cc34f605d509a20d40e6c2
generated by cgit v1.2.3 (git 2.25.1) at 2026-07-11 22:24:21 +0000