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* | | | usb: Remove DPDM pulsing functionalityMayank Rana2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This change removes DP DM pulsing functionality related support from QUSB PHY driver as it is not required. Signed-off-by: Mayank Rana <mrana@codeaurora.org>
* | | | input: misc: add support for scaling X and Y touch co-ordinatesShantanu Jain2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In certain situations, due to resolution mismatch, we may need to scale up/down the X and Y co-ordinates returned by the touch controller. Add support for the same where we scale up/down the X and Y touch co-ordinates returned from the touch controller before sending it to android. In such cases, we also need to ensure that the display resolution matches the touch resolution. Add support for that as well. Change-Id: Ia2dabf480478e26db1e1f0d92ca9ba5a252f18eb Signed-off-by: Shantanu Jain <shjain@codeaurora.org>
* | | | input: synaptics: defer touch resume to workqueuezhaoyuan2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During device resume, the touch resume function is called after display resume. Touch resume function will take about >200ms. Defer the touch resume function to a workqueue to reduce the total device resume time. An optional DT property is added to enable this on targets that need this feature. Change-Id: Ia9b055144c5a7f29f0f0d57428cccbe15a7d7a87 Signed-off-by: zhaoyuan <yzhao@codeaurora.org>
* | | | leds: qpnp-wled: add support for configuring sc debounce cyclesHimanshu Aggarwal2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for configuring short circuit debounce cycles in both LCD mode and AMOLED mode. Also, when configuring the WLED SHORT_PROTECT register, the bits corresponding to DBNC_SHORT bit fields are incorrectly written, so correct the corresponding bitmask and the associated code logic to avoid this. Add an explicit SPMI write to WLED1_CTRL_SOFTSTART_RAMP_DELAY register as well for LCD mode. Change-Id: Ibae8926262c52c8db3d04ab355651e5df44ec090 Signed-off-by: Himanshu Aggarwal <haggarwa@codeaurora.org> Signed-off-by: Shantanu Jain <shjain@codeaurora.org>
* | | | msm: kgsl: Add quirk for masking out hang detect signalsShrenuj Bansal2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a quirk to mask out the RB 1-3 activity signals in the hang detection logic. Set this quirk in the devicetree for 8996v2 and v3. CRs-Fixed: 978849 Change-Id: I63073b5973644453e775b41a9361de55d7933a07 Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
* | | | msm: kgsl: Submit a set of critical packets right after ME initShrenuj Bansal2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the initialization sequence, submit a set of important packets to the GPU in order to pre-load the I-cache with the critical ucode instructions. CRs-Fixed: 978777 Change-Id: Ic6a17b24d8c3aa383af8e25cf9ef771459d65796 Signed-off-by: Shrenuj Bansal <shrenujb@codeaurora.org>
* | | | misc: Add snapshot of QPNP misc driverAndy Gross2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a snapshot of the QPNP misc driver as of msm-3.14 commit: e016c39467094409c9c872b02ec619164913054a (Merge "msm: thermal: Fix compilation issue when THERMAL_MONITOR is disabled") CRs-Fixed: 972331 Change-Id: I48dc9857379c388ddff86b20320cdfa23bb22af8 Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Devesh Jhunjhunwala <deveshj@codeaurora.org>
* | | | input: maxim_sti: add support for multitouch protocol BJigarkumar Kishorkumar Zala2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for multitouch procotol B, in order to track object based ID touch activities. Change-Id: I9b6941b3fea2f5c28434793073330cd4abe9fa74 Signed-off-by: Jigarkumar Kishorkumar Zala <j_zala@codeaurora.org>
* | | | slim-msm-ngd: Register with specific subsystemDilip Kota2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Slimbus master is present in different subsystem on different tragets. Register with specific subsystem as mentioned in the device tree. Change-Id: I1bee7fdd7578deedca8e4e43af9055b41b96d652 Signed-off-by: Dilip Kota <dkota@codeaurora.org>
* | | | ASoC: msm: Use legacy ASM APIs for older targetsAshish Jain2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With 3.18 kernel, get_session_time command to DSP is updated to new command. This command is not supported on older targets as they have an older DSP version. To have backwards compatibility, based on DSP version choose which command to use. CRs-Fixed: 978676 Change-Id: I76b0cfcd84df90d7a206690cb8aa1eb773fdc53d Signed-off-by: Ashish Jain <ashishj@codeaurora.org>
* | | | clk: msm: clock-osm: add OSM clock driverOsvaldo Banuelos2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Operating State Manager is a hardware block which deals with performing voltage and frequency change operations in the CPUSS. Two instances exist, one for each cluster, in the msmcobalt chip. Introduce the OSM clock driver to perform the required OSM hardware block initialization and support DCVS scale requests. Change-Id: I3e155db5cd580e371ca1791815e4942f442a3d20 CRs-Fixed: 967319 Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org> Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
* | | | drivers: mfd: Move codec reset gpio config to early bootPhani Kumar Uppalapati2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Codec reset gpio configuration needs to be updated before slimbus master component is initialized otherwise codec cannot be enumerated on the bus. Add a new platform device driver to update the codec reset gpio configuration to valid state (output, drive-strength) before slimbus is initialized. CRs-Fixed: 968161 Change-Id: I7227212e6b846d58196718255aa4b0923352d120 Signed-off-by: Phani Kumar Uppalapati <phaniu@codeaurora.org>
* | | | msm: kgsl: Specify the initial pwrlevel for each speed binSuman Tatiraju2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some platforms support multiple GPU clock plans based on the speed bin in the efuse. Specify the wake up frequency of each speed bin individually to wake the gpu at the correct powerlevel. CRs-Fixed: 967494 Change-Id: I9890b8a710d7055c30f9ae7612b092af8fa8a9f5 Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* | | | msm: kgsl: Set the DDR high bank bit if specified in the device treeJordan Crouse2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 5XX targets we need to program the bit of the highest DDR bank into a number of registers, one of which is protected which would cause problems if the user mode driver tried to write to it. Specify the high bank bit in the device tree files, set the problematic register in the kernel and then pass the value up to the user mode driver as a property and let them program the other registers. This makes the device tree the authoratative source of the high bit value which is exactly how it should be. If the value isn't specified by the device tree for whatever reason return an error for the property request - that will give the UMD a clue that the value wasn't specified and they should just set a default. CRs-Fixed: 970272 Change-Id: Ic0dedbad830321329b74da7fa3e172fdaf765c4d Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
* | | | msm: kgsl: Add disable-busy-time-burst to disable ceiling thresholdDivya Ponnusamy2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a devicetree property disable-busy-time-burst to disable ceiling threshold in the governor. The ceiling threshold cause busy time burst that switch power level for large frames based on busy time. Change-Id: I44f8a51e0aa49bb0b2210703f57874fd5f219c18 Signed-off-by: Divya Ponnusamy <pdivya@codeaurora.org>
* | | | msm: kgsl: Read speed bin information from device treeSuman Tatiraju2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Speed bin information is sometimes written to efuses to specify a GPU frequency plan available on a platform. The current code only supports reading the efuses for msm8996v3. Hence specify it in the platform device tree node to support multiple platforms. CRs-Fixed: 967494 Change-Id: I5db4d5a35e2700250517ea6cac3d4d736936ce9f Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* | | | msm: kgsl: Enable GPU-BIMC clocks from kernel driverSunil Khatri2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable direct programming of GPU-BIMC interface clocks from kernel driver when moving in and out of TURBO. This is done only for targets with a device tree entry defined for GPU-BIMC interface. This is done because some targets do not support B/W requirement of GPU at TURBO, for such targets we need to program the GPU-BIMC interface clocks with TURBO values to meet the B/W goals. Change-Id: Ibe82db8718040513ae0d96366195d41001549189 Signed-off-by: Sunil Khatri <sunilkh@codeaurora.org>
* | | | SSM: Integrating the SSM driver codeAshay Jaiswal2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for SSM driver which is a framework to which a client can register itself specifying different attributes and defining various permission levels associated with different combination of attribute values and mode of the system. CRs-Fixed: 970190 Change-Id: Ia030ebad56a22ba9103af17f6557c7906b762b76 Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org> Signed-off-by: Manoj Prabhu B <bmanoj@codeaurora.org>
* | | | msm: kgsl: Avoid L2PC on masked CPUsPrakash Kamliya2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If any of the Graphics rendering threads are running on masked CPUs, avoid L2PC for some duration on that CPU. This reduces latency on CPU (latency mainly because of L2 cache flush) and helps on performance. This change uses pm_qos_update_request_timeout() API. Add l2pc-cpu-mask property in device tree to enable this. CRs-Fixed: 962598 Change-Id: If90090cd2c68ea7c07e269723931fef7201ef136 Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>
* | | | clk: msm: clock: Enable auto-calibration during certain LPM mode pathsDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add settings to switch to always-on clock source during certain LPM mode exit paths on msm8996 Pro. CRs-Fixed: 968587 Change-Id: I6138681e2a85b7d1ad11350718544de6abe38131 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | | | clk: msm: clock: Add the MMSS clock driver support for MSMCOBALTDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to model the multimedia clocks on MSMCOBALT. Change-Id: Iec33fa93e745a65205cf4206759289d7e842fe36 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | | | lpm: Allow cpu to enter FPC from hypervisorArchana Sathyakumar2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FPC using PSCI is entered from PSCI layer that is in Secure EL1. Switching of EL layers incur additional latency, making FPC slower. Issue wfi within hypervisor for cpu only sleep. This makes FPC much faster than entering from PSCI layer. Change-Id: Icf4c5f2484fdda79c991b842cb3a3185b638bfdb Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org>
* | | | clk: msm: clock: Add GPUCC clock driver support for MSMCOBALTDeepak Katragadda2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to model the graphics clocks on MSMCOBALT. Change-Id: I31c3dda59a0bb7e9b6b6cee8176fb46f46767629 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | | | thermal: tsens: Add Cobalt TSENS supportSiddartha Mohanadoss2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MSM Cobalt TSENS supports upto 22 temperature sensors across two TSENS controllers. Thermal clients have the ability to set temperature threshold and receive notification on a threshold crossing. Change-Id: I05d6f7cfceece6c27ef5d03b9ea3b77d409108db Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
* | | | msm: pcie: add support to modify the Cpl timeout for RCTony Truong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to modify the completion timeout range for the root complex. This value/range will inform when the root complex should send out a completion if the endpoint does not respond. Change-Id: Iabca3f637d9abf6c93810c84d81ff6b5c77d4528 Signed-off-by: Tony Truong <truong@codeaurora.org>
* | | | cnss: Vote for the WLAN antenna switch regulatorYue Ma2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some targets, explicitly turning on/off the regulator for WLAN antenna switch is needed to enable/dsiable antenna sharing capacity. Hence add the change to achieve this based on device tree option. Change-Id: Ic04019cbe9c42bc92a65f308f56f307c52346d92 Signed-off-by: Yue Ma <yuem@codeaurora.org>
* | | | mfd: wcd9xxx: Make DMIC clock drive strength platform dependentBhalchandra Gajare2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Digital microphone clock drive strength setting in the codec could be platform dependent based on the type of microphone, etc. Add support to make the DMIC clock drive strength configurable through device tree. CRs-fixed: 938006 Change-Id: I8b17d985052098b56d012081a77b6dfc94553eca Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
* | | | regulator: Add the MSM GFX LDO regulator driverAnirudh Ghayal2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPU core on MSM TITANIUM can be powered by an internal MSM (on-die) LDO or BHS. Typically the lower voltage corners are powered by the LDO and the higher corners by BHS. Add support to configure the LDO and hand-off between LDO and BHS. Change-Id: Id13b6b601c91aa6c2c2f0e6d820a244144b60437 Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
* | | | Net: CNSS_SDIO: Add SSR support for QCA WIFI DevicesLiangwei Dong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Register subsystem device for SSR recovery. Create ramdump device for cnss fw dump collection. Implement cnss SSR API to wlan sdio driver. CRs-Fixed: 944010 Change-Id: If81fd84bb6080df73b12f235a2aa0eff6f717ce1 Signed-off-by: Liangwei Dong <liangwei@codeaurora.org>
* | | | msm: ep_pcie: add the support of MDM2AP GPIOYan He2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the support of MDM2AP GPIO so that MDM can notify AP about updated status. Change-Id: Ia5a020898d4d04dcd4fec6b3928aba380663ac56 Signed-off-by: Yan He <yanhe@codeaurora.org>
* | | | msm: kgsl: Fix direct references to HZSuman Tatiraju2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the various timeout values HZ agnostic by using the proper macros and values instead. Change-Id: I708cd491f593782f0172cd7d2cca058cd41044a5 Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
* | | | can: Add RH850 CAN controller driverAlex Yakavenka2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver creates network device of type CAN and processes tx and rx frames that it sends and receives over SPI. Change-Id: I903927d5bb0025c2ad3e9f1dd7cb51de547fc360 Signed-off-by: Alex Yakavenka <ayakav@codeaurora.org>
* | | | msm: mdss: add multiple register support in ESD checkRay Zhang2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation cannot support multiple registers in ESD check, and it does not work for many cases. For example, some panels need check multiple registers to get its status, and some panels might return several possible values for one register read. To support this kind of behaviors, a new property in dtsi is added as "qcom,mdss-dsi-panel-status-valid-params" which specifies the valid value length we should check in the payload returned by panel, and the payload length panel should return is specified by the property "qcom,mdss-dsi- panel-status-read-length". "qcom,mdss-dsi-panel-status-value" is also extended to an array which specifies all the possible return values from panel. Change-Id: I098d04281b819581f53c7c509778e7b594aa499a Signed-off-by: Ray Zhang <rayz@codeaurora.org>
* | | | msm: mdss: separate out DBA and CEC functionality from DSISandeep Panda2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, DBA (Display Bridge Abstract) related functionality is being used in DSI files. Carve out DBA related functionality into a new file which serves as a utility module and can be used by any MDSS driver. Define CEC on/enable functions in DBA (Display Bridge Abstract) so that clients can enable disable CEC based on other dependent CEC modules. Separate out CEC abstract data with CEC driver data and initialize and release corresponding modules properly. Change-Id: I84f53d99547dcd4ce0b8275401b03ed8e96e14d5 Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org> Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
* | | | clk: msm: mdss: add DT support for SSC frequency and PPM valuesPadmanabhan Komanduru2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSC frequency and PPM values are currently hardcoded in the DSI PLL driver. Add DT properties to specify the SSC frequency and SSC PPM values for DSI SSC feature. Change-Id: I0faed9f48694f7407c6855b067ffa4510d7e3fdd Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
* | | | msm: mdss: read display id from device treeVinu Deokaran2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to read display ID string from device tree. The string could be empty if it's not defined in the device tree. Change-Id: I70584a1e20b7394145e40d83a2af7775f0117506 Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
* | | | msm: mdss: add support to register secondary fb on DSI devicePadmanabhan Komanduru2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current implementation, DSI0/DSI1 device is always mapped to frame buffer-0. For dual DSI configuration, we need to register both the DSI devices to different frame buffers. Add driver and dtsi support to register DSI device on primary/secondary frame buffer at runtime based on the DSI configuration. Change-Id: Iac872723711c5d0264088c4f3b53d1385fd9ffe0 Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org> Signed-off-by: Vinu Deokaran <vinud@codeaurora.org> Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
* | | | msm: mdss: make timing db property DSI controller specificSandeep Panda2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If timing db(Double Buffered) property is enabled, then MDP FLUSH bit needs to be set in order to push the data to video interface. Currently this property is used as a shared property for both DSI interfaces. But in case of chipsets where there is no FLUSH bit defined for the secondary DSI interface, this will cause issue. So moving the property to each controller specific instead of shared. Change-Id: I25913867da41ca2fb2848ab96f5be5d9228a8f63 Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
* | | | ARM: dts: msm: Add the timeout properties to SMMU GDSCs on MSM8996Deepak Katragadda2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The votable SMMU GDSCs might take longer to enable than the default limit of 100usecs depending on the clock WAKE and SLEEP settings and the clock rates. Make this polling timeout limit more configurable. Change-Id: I26cb00cefa5d45ed2a92f306921e2d95938795af Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
* | | | ASoC: msm: add slot and channel config support for TDM devicesHonghao Liu2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for slot and channel configuration in CPU dai driver for TDM devices. Remove the probing of slot and channel info from device tree. Change-Id: I9d65779b7ef70fac741569f0584b15db29093e0c Signed-off-by: Honghao Liu <honghaol@codeaurora.org>
* | | | net: cnss: enable rome_vreg_dsrc regulator for dsrcGovind Singh2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rome_vreg_dsrc regulator is a fixed regulator and this regulator is control by PMIC gpio4. This is being used as vdd supply for the wlan DSRC module based on sdio interface. Enable rome_vreg_dsrc voltage regulators to enable the power up support in CNSS SDIO platform driver. Change-Id: I7c6032b706d468cc57b5304a3627f526935fb3a3 Signed-off-by: Govind Singh <govinds@codeaurora.org>
* | | | soc: qcom: add secure processor communication (spcom) driverAmir Samuelov2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver supports communication with secure processor subsystem over glink transport layer. The communication is based on using shared memory and interrupts. This driver exposes interface to both kernel and user space. Change-Id: Iec5fc78c8370002643b549e43015c06b09d8ab8b Signed-off-by: Amir Samuelov <amirs@codeaurora.org>
* | | | soc: qcom: Add in-rush current mitigation driverArun KS2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On few recent targets APSS L2 memory is moved to APC domain which were earlier on Mx domain. This can cause inrush current while bringing up huge memories like modem and adsp. To mitigate inrush current, bring up comparatively lesser memory in size(for eg MDP memory) before bringing up huge memories like modem or adsp. This way MDP memory introduce an intermediate load on MX rail. During boot, gdsc driver will set MEM and PERIPHERAL bits. This driver makes sure that dependent subsystems are powered up. Once done, call gdsc_allow_clear_retention() API to allow retention of MDP memories. Change-Id: I54011eb1b6cc38b2c33a67b8b9cc5eaadbd42c6a Signed-off-by: Arun KS <arunks@codeaurora.org>
* | | | mhi: core: Parse ring information from DTAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Parse MHI ring information from DT instead of statically allocating data structure. This is necessary as different platforms support different configurations. Change-Id: I59cd660459d627f93479a11257653611070fd3a4 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | | msm: mhi: Add MHI core driverAndrei Danaila2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the MHI core driver for communication between host and device using PCIe as an interconnect and supporting MHI as the communication protocol. The driver exposes several kernel space APIs for use by other kernel entities to interface to the PCIe device over MHI. APIs for read and write and other notifications are supported by this MHI driver. Support for full power management and device reset is also included. CRs-Fixed: 689329 Change-Id: Ibc2fd7c2d5689001485f71b1133ada2c4ca236a9 Signed-off-by: Andrei Danaila <adanaila@codeaurora.org>
* | | | hw_random: add snapshot of msm_rng driverZhen Kong2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This snapshot is taken as of msm-3.18 commit e70ad0cd (Promotion of kernel.lnx.3.18-151201.) Acked-by: Shabnam Aboughadareh <shabnama@qti.qualcomm.com> Signed-off-by: Zhen Kong <zkong@codeaurora.org>
* | | | input: misc: hbtp_input: Add digital regulator supportAlex Sarraf2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the digital regulator in hbtp_input driver. Signed-off-by: Alex Sarraf <asarraf@codeaurora.org> Change-Id: I315d4b4c985917e55823a3c3951f2bffb20b39e6
* | | | input: hbtp_input: Port and add snapshot of changes from msm-3.10Himanshu Aggarwal2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Port the HBTP Input driver and apply the following driver changes taken from msm-3.10 kernel branch as of msm-3.10 commit. 31773451 input: misc: add input driver for HBTP 20bf9c5f input: hbtp_input: bypass alphabetical and numeric key config e424ee72 input: misc: hbtp-input: add event type in uevents Change-Id: I122d22cf738c747bcd43ec7f90c33a239288fd9d Signed-off-by: Jing Lin <jinglin@codeaurora.org> Signed-off-by: Chun Zhang <chunz@codeaurora.org> Signed-off-by: Himanshu Aggarwal <haggarwa@codeaurora.org>
* | | | input: atmel_maxtouch_ts: squash commit from 3.14 kernelAmy Maloche2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Squash and apply the following touchscreen changes taken from the msm-3.14 kernel branch as of msm-3.14 commit 8139d0b (ARM: dts: msm: Set flag to manage clks during suspend for msm8996) 421c2f3 input: touchscreen: atmel_maxtouch_ts: delay init call 48e0a07 input: atmel_maxtouch_ts: recover from bootloader b3ebb61 input: atmel_maxtouch_ts: add support for force cfg update 8467fe3 input: atmel_maxtouch_ts: fix firmware update routines c83ee59 input: atmel: Secure Touch support 1c7d5e2 input: atmel_maxtouch_ts: fix power up sequence d4c1ffc input: atmel_maxtouch_ts: add support to ignore CRC f402790 input: atmel_maxtouch_ts: add support for standard features 9374cef input: atmel_maxtouch_ts: use proper data types 0fbe83e input: atmel_maxtouch_ts: add regulator error conditions e22d100 input: atmel_maxtouch_ts: add gpio support 63d4b74 input: atmel_maxtouch_ts: add device tree support 575c2fc input: atmel_maxtouch_ts: enable compilation on 3.10 kenrel Signed-off-by: Alex Sarraf <asarraf@codeaurora.org>
* | | | input: synaptics_dsx_fw_update: update fw based on config idHimanshu Aggarwal2016-03-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the firmware based on strict config ID versioning, rather than the entire config ID as a 4 byte number. This will also protect against config ID major number mismatches and packrat id mismatches. This is a propagated patch from 3.10 kernel. commit - 458cbab5c53d5141a66590441f9567d67d580c6f, input: synaptics_dsx_fw_update: update fw based on config id Change-Id: I1097585d3bd8b6ab753676dc56f268c7ce52680d Signed-off-by: Himanshu Aggarwal <haggarwa@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-07-11 12:47:58 +0000