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Pull ARM SoC updates for Marvell mvebu/kirkwood from Olof Johansson:
"This is a branch with updates for Marvell's mvebu/kirkwood platforms.
They came in late-ish, and were heavily interdependent such that it
didn't make sense to split them up across the cross-platform topic
branches. So here they are (for the second release in a row) in a
branch on their own."
* tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (88 commits)
arm: l2x0: add aurora related properties to OF binding
arm: mvebu: add Aurora L2 Cache Controller to the DT
arm: mvebu: add L2 cache support
dma: mv_xor: fix error handling path
dma: mv_xor: fix error checking of irq_of_parse_and_map()
dma: mv_xor: use request_irq() instead of devm_request_irq()
dma: mv_xor: clear the window override control registers
arm: mvebu: fix address decoding armada_cfg_base() function
ARM: mvebu: update defconfig with I2C and RTC support
ARM: mvebu: Add SATA support for OpenBlocks AX3-4
ARM: mvebu: Add support for the RTC in OpenBlocks AX3-4
ARM: mvebu: Add support for I2C on OpenBlocks AX3-4
ARM: mvebu: Add support for I2C controllers in Armada 370/XP
arm: mvebu: Add hardware I/O Coherency support
arm: plat-orion: Add coherency attribute when setup mbus target
arm: dma mapping: Export a dma ops function arm_dma_set_mask
arm: mvebu: Add SMP support for Armada XP
arm: mm: Add support for PJ4B cpu and init routines
arm: mvebu: Add IPI support via doorbells
arm: mvebu: Add initial support for power managmement service unit
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git://git.infradead.org/users/jcooper/linux into late/mvebu
From Jason Cooper:
mvebu cache-l2x0 for v3.8
- Add support for l2x0 cache on mvebu boards
- Depends on mvebu/everything
* tag 'mvebu_cache_l2x0_for_3.8' of git://git.infradead.org/users/jcooper/linux:
arm: l2x0: add aurora related properties to OF binding
arm: mvebu: add Aurora L2 Cache Controller to the DT
arm: mvebu: add L2 cache support
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Aurora is a L2 Cache Controller designed to be compatible with the
L2x0 Cache Controller. L2X0 OF bindings are extended to support some
specificity of Aurora (no cache id part number available through
hardware, always write through mode, choice between outer cache and
system cache).
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-and-reviewed-by: Lior Amsalem <alior@marvell.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Barry Song <21cnbao@gmail.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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git://git.infradead.org/users/jcooper/linux into late/mvebu
From Jason Cooper. Unfortunately this is a combined branch with all
mvebu code as one drop, something we normally try to avoid and instead
slice vendor topics across our branches. Hopefully we can avoid doing
this again for 3.9!
mvebu everything for v3.8
- due to the complex interdependencies of the received pull requests
I decided to keep this in one branch the way they recommended merging it
- this was their first attempt at doing pull requests, we'll work on it
with them
- added SMP support for mvebu SoCs
- added coherency fabric
- added mdio and mvneta drivers
- added mirabox board
- added openblocks ax3-4 board
- clock fixes and improvements
- converted mv_xor driver to devicetree (extensive series in itself)
* tag 'mvebu_everything_for_3.8' of git://git.infradead.org/users/jcooper/linux: (85 commits)
dma: mv_xor: fix error handling path
dma: mv_xor: fix error checking of irq_of_parse_and_map()
dma: mv_xor: use request_irq() instead of devm_request_irq()
dma: mv_xor: clear the window override control registers
arm: mvebu: fix address decoding armada_cfg_base() function
ARM: mvebu: update defconfig with I2C and RTC support
ARM: mvebu: Add SATA support for OpenBlocks AX3-4
ARM: mvebu: Add support for the RTC in OpenBlocks AX3-4
ARM: mvebu: Add support for I2C on OpenBlocks AX3-4
ARM: mvebu: Add support for I2C controllers in Armada 370/XP
arm: mvebu: Add hardware I/O Coherency support
arm: plat-orion: Add coherency attribute when setup mbus target
arm: dma mapping: Export a dma ops function arm_dma_set_mask
arm: mvebu: Add SMP support for Armada XP
arm: mm: Add support for PJ4B cpu and init routines
arm: mvebu: Add IPI support via doorbells
arm: mvebu: Add initial support for power managmement service unit
arm: mvebu: Add support for coherency fabric in mach-mvebu
arm: mvebu: update defconfig to include XOR driver
arm: mvebu: update defconfig to include network driver
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Signed-off-by: Olof Johansson <olof@lixom.net>
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git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
Add hardware I/O coherency support for Armada 370/XP
The purpose of this patch set is to add hardware I/O Coherency support
for Armada 370 and Armada XP. Theses SoCs come with an unit called
coherency fabric. A beginning of the support for this unit have been
introduced with the SMP patch set. This series extend this support:
the coherency fabric unit allows to use the Armada XP and the Armada
370 as nearly coherent architectures.
The third patches enables this new feature and register our own set
of DMA ops, to benefit this hardware enhancement.
The first patches exports a dma operation function needed to register
our own set of dma ops.
The second patch introduces a new flag for the address decoding
configuration in order to be able to set the memory windows as
shared memory.
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Armada 370 and XP come with an unit called coherency fabric. This unit
allows to use the Armada 370/XP as a nearly coherent architecture. The
coherency mechanism uses snoop filters to ensure the coherency between
caches, DRAM and devices. This mechanism needs a synchronization
barrier which guarantees that all the memory writes initiated by the
devices have reached their target and do not reside in intermediate
write buffers. That's why the architecture is not totally coherent and
we need to provide our own functions for some DMA operations.
Beside the use of the coherency fabric, the device units will have to
set the attribute flag of the decoding address window to select the
accurate coherency process for the memory transaction. This is done
each device driver programs the DRAM address windows. The value of the
attribute set by the driver is retrieved through the
orion_addr_map_cfg struct filled during the early initialization of
the platform.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Yehuda Yitschak <yehuday@marvell.com>
Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
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git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
SMP support for Armada XP
The purpose of this series is to add the SMP support for the Armada XP
SoCs. Beside the SMP support itself brought by the last 3 commits,
this series also adds the support for the coherency fabric unit and
the power management service unit.
The coherency fabric is responsible for ensuring hardware coherency
between all CPUs and between CPUs and I/O masters. This unit is also
available for Armada 370 and will be used in an incoming patch set
for hardware I/O cache coherency.
The power management service unit is responsible for powering down and
waking up CPUs and other SOC units.
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This patch enhances the IRQ controller driver to add support for
Inter-Processor-Interrupts that are needed to enable SMP support.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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The Armada 370 and Armada XP SOCs have a power management service unit
which is responsible for powering down and waking up CPUs and other
SOC units. This patch adds support for this unit.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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The Armada 370 and Armada XP SOCs have a coherency fabric unit which
is responsible for ensuring hardware coherency between all CPUs and
between CPUs and I/O masters. This patch provides the basic support
needed for SMP.
Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
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git://github.com/MISL-EBU-System-SW/mainline-public into mvebu/everything
Marvell XOR driver cleanup and DT binding for 3.8
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This patch finally adds a Device Tree binding to the mv_xor
driver. Thanks to the previous cleanup patches, the Device Tree
binding is relatively simply: one DT node per XOR engine, with
sub-nodes for each XOR channel of the XOR engine. The binding
obviously comes with the necessary documentation.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree-discuss@lists.ozlabs.org
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Now that the Armada 370/XP platform has gained proper integration with
the clock framework, we add clk support in the Marvell Armada 370/XP
Ethernet driver.
Since the existing Device Tree binding that exposes a
'clock-frequency' property has never been exposed in any stable kernel
release, we take the freedom of removing this property to replace it
with the standard 'clocks' clock pointer property.
The Device Tree binding documentation is updated accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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github.com:MISL-EBU-System-SW/mainline-public into test-the-merge
Marvell mvneta network driver, for 3.8
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This patch contains a new network driver for the network unit of the
ARM Marvell Armada 370 and the Armada XP. Both SoCs use the PJ4B
processor, a Marvell-developed ARM core that implements the ARMv7
instruction set.
Compared to previous ARM Marvell SoCs (Kirkwood, Orion, Discovery),
the network unit in Armada 370 and Armada XP is highly different. This
is the reason why this new 'mvneta' driver is needed, while the older
ARM Marvell SoCs use the 'mv643xx_eth' driver.
Here is an overview of the most important hardware changes that
require a new, specific, driver for the network unit of Armada 370/XP:
- The new network unit has a completely different design and layout
for the RX and TX descriptors. They are now organized as a simple
array (each RX and TX queue has base address and size of this
array) rather than a linked list as in the old SoCs.
- The new network unit has a different RXQ and TXQ management: this
management is done using special read/write counter registers,
while in the Old SocS, it was done using the Ownership bit in RX
and TX descriptors.
- The new network unit has different interrupt registers
- The new network unit way of cleaning of interrupts is not done by
writing to the cause register, but by updating per-queue counters
- The new network unit has different GMAC registers (link, speed,
duplex configuration) and different WRR registers.
- The new network unit has lots of new units like PnC (Parser and
Classifier), PMT, BM (Memory Buffer Management), xPON, and more.
The driver proposed in the current patch only handles the basic
features. Additional hardware features will progressively be supported
as needed.
This code has originally been written by Rami Rosen
<rosenr@marvell.com>, and then reviewed and cleaned up by Thomas
Petazzoni <thomas.petazzoni@free-electrons.com>.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: David S. Miller <davem@davemloft.net>
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This patch adds a separate driver for the MDIO interface of the
Marvell Ethernet controllers. There are two reasons to have a separate
driver rather than including it inside the MAC driver itself:
*) The MDIO interface is shared by all Ethernet ports, so a driver
must guarantee non-concurrent accesses to this MDIO interface. The
most logical way is to have a separate driver that handles this
single MDIO interface, used by all Ethernet ports.
*) The MDIO interface is the same between the existing mv643xx_eth
driver and the new mvneta driver. Even though it is for now only
used by the mvneta driver, it will in the future be used by the
mv643xx_eth driver as well.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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This driver allows to provide DT clocks for clock gates found on
Marvell Dove and Kirkwood SoCs. The clock gates are referenced by
the phandle index of the corresponding bit in the clock gating control
register to ease lookup in the datasheet.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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Add Armada 370/XP specific CPU clocks
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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This driver allows to provide DT clocks for core clocks found on
Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and
ratios are determined by decoding the Sample-At-Reset registers.
Although technically correct, using a divider of 0 will lead to
div_by_zero panic. Let's use a ratio of 0/1 instead to fail later
with a zero clock.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
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Pull ARM SoC device-tree updates, take 2, from Olof Johansson:
"This branch contains device-tree updates for the SPEAr platform. They
had dependencies on earlier branches from this merge window, which is
why they were broken out in a separate branch."
* tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: SPEAr3xx: Shirq: Move shirq controller out of plat/
ARM: SPEAr320: DT: Add SPEAr 320 HMI board support
ARM: SPEAr3xx: DT: add shirq node for interrupt multiplexor
ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT
ARM: SPEAr1310: Fix AUXDATA for compact flash controller
ARM: SPEAr13xx: Remove fields not required for ssp controller
ARM: SPEAr1310: Move 1310 specific misc register into machine specific files
ARM: SPEAr: DT: Update device nodes
ARM: SPEAr: DT: add uart state to fix warning
ARM: SPEAr: DT: Modify DT bindings for STMMAC
ARM: SPEAr: DT: Fix existing DT support
ARM: SPEAr: DT: Update partition info for MTD devices
ARM: SPEAr: DT: Update pinctrl list
ARM: SPEAr13xx: DT: Add spics gpio controller nodes
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SPEAr3xx architecture includes shared/multiplexed irqs for certain set
of devices. The multiplexor provides a single interrupt to parent
interrupt controller (VIC) on behalf of a group of devices.
There can be multiple groups available on SPEAr3xx variants but not
exceeding 4. The number of devices in a group can differ, further they
may share same set of status/mask registers spanning across different
bit masks. Also in some cases the group may not have enable or other
registers. This makes software little complex.
Present implementation was non-DT and had few complex data structures to
decipher banks, number of irqs supported, mask and registers involved.
This patch simplifies the overall design and convert it in to DT. It
also removes all registration from individual SoC files and bring them
in to common shirq.c.
Also updated the corresponding documentation for DT binding of shirq.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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This merges dependency branch gpio-lw/devel for SPEAr DT updates.
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This merges dependency branch pinctrl/devel for SPEAr DT updates.
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Pull ARM Soc updates, take 2, from Olof Johansson:
"This is the second batch of SoC updates for the 3.8 merge window,
containing parts that had dependencies on earlier branches such that
we couldn't include them with the first branch.
These are general updates for Samsung Exynos, Renesas/shmobile and a
topic branch that adds SMP support to Altera's socfpga platform."
Fix up conflicts mostly as per Olof.
* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: EXYNOS: Clock settings for SATA and SATA PHY
ARM: EXYNOS: Add ARM down clock support
ARM: EXYNOS: Fix i2c suspend/resume for legacy controller
ARM: EXYNOS: Add aliases for i2c controller
ARM: EXYNOS: Setup legacy i2c controller interrupts
sh: clkfwk: fixup unsed variable warning
Revert "ARM: shmobile: r8a7779: Replace modify_scu_cpu_psr with scu_power_mode"
Revert "ARM: shmobile: sh73a0: Replace modify_scu_cpu_psr with scu_power_mode"
Revert "ARM: shmobile: emev2: Replace modify_scu_cpu_psr with scu_power_mode"
ARM: highbank: use common debug_ll_io_init
ARM: shmobile: sh7372: sh7372_fsiXck_clk become non-global
ARM: shmobile: sh7372: remove fsidivx clock
ARM: socfpga: mark secondary_trampoline as cpuinit
socfpga: map uart into virtual address space so that early_printk() works
ARM: socfpga: fix build break for allyesconfig
ARM: socfpga: Enable SMP for socfpga
ARM: EXYNOS: Add dp clock support for EXYNOS5
ARM: SAMSUNG: call clk_get_rate for debugfs rate files
ARM: SAMSUNG: add clock_tree debugfs file in clock
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Merging in the smp-on-socfpga branch into soc2 since the topics are similar
and it's a short branch in the first place.
* next/smp:
ARM: socfpga: mark secondary_trampoline as cpuinit
socfpga: map uart into virtual address space so that early_printk() works
ARM: socfpga: fix build break for allyesconfig
ARM: socfpga: Enable SMP for socfpga
Signed-off-by: Olof Johansson <olof@lixom.net>
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Enable SMP for the SOCFPGA platform.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc2
From Kukjin Kim:
This includes supporting legacy i2c controller and ARM down clock
support for exynos5 and small changes.
[olof: It contains a dependency on samsung/hdmi for HDMI DT bindings, for some reason.]
* 'next/devel-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Clock settings for SATA and SATA PHY
ARM: EXYNOS: Add ARM down clock support
ARM: EXYNOS: Fix i2c suspend/resume for legacy controller
ARM: EXYNOS: Add aliases for i2c controller
ARM: EXYNOS: Setup legacy i2c controller interrupts
ARM: EXYNOS: removing exynos-drm device registration from non-dt platforms
ARM: EXYNOS: add clocks for exynos5 hdmi
ARM: dts: add device tree support for exynos5 hdmiddc
ARM: dts: add device tree support for exynos5 hdmiphy
ARM: dts: add device tree support for exynos5 mixer
ARM: dts: add device tree support for exynos5 hdmi
ARM: EXYNOS: Add dp clock support for EXYNOS5
ARM: SAMSUNG: call clk_get_rate for debugfs rate files
ARM: SAMSUNG: add clock_tree debugfs file in clock
Signed-off-by: Olof Johansson <olof@lixom.net>
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Dependencies for highbank debug_ll_init patch
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Dependency for more Renesas soc changes
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Pull battery subsystem updates from Anton Vorontsov:
"Highlights:
- Two new drivers from Pali Rohár and N900 hackers: rx51_battery and
bq2415x_charger. The drivers are a part of a solution to replace
the proprietary Nokia BME stack
- Power supply core now registers devices with a thermal cooling
subsystem, so we can now automatically throttle charging. Thanks
to Ramakrishna Pallala!
- Device tree support for ab8500 and max8925_power drivers
- Random fixups and enhancements for a bunch of drivers."
* tag 'for-v3.8-merged' of git://git.infradead.org/battery-2.6: (22 commits)
max8925_power: Add support for device-tree initialization
ab8500: Add devicetree support for chargalg
ab8500: Add devicetree support for charger
ab8500: Add devicetree support for btemp
ab8500: Add devicetree support for fuelgauge
twl4030_charger: Change TWL4030_MODULE_* ids to TWL_MODULE_*
jz4740-battery: Use devm_request_and_ioremap
jz4740-battery: Use devm_kzalloc
bq27x00_battery: Fixup nominal available capacity reporting
bq2415x_charger: Fix style issues
bq2415x_charger: Add Kconfig/Makefile entries
power_supply: Add bq2415x charger driver
power_supply: Add new Nokia RX-51 (N900) power supply battery driver
max17042_battery: Fix missing verify_model_lock() return value check
ds2782_battery: Fix signedness bug in ds278x_read_reg16()
lp8788-charger: Fix ADC channel names
lp8788-charger: Fix wrong ADC conversion
lp8788-charger: Use consumer device name on setting IIO channels
power_supply: Register power supply for thermal cooling device
power_supply: Add support for CHARGE_CONTROL_* attributes
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The merge is merely to fix conflicts before sending a pull request.
Conflicts:
drivers/power/ab8500_btemp.c
drivers/power/ab8500_charger.c
drivers/power/ab8500_fg.c
drivers/power/abx500_chargalg.c
drivers/power/max8925_power.c
Signed-off-by: Anton Vorontsov <anton.vorontsov@linaro.org>
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This patch adds device tree support for charging algorithm driver
Signed-off-by: Rajanikanth H.V <rajanikanth.hv@stericsson.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov@linaro.org>
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This patch adds device tree support for ab8500-charger driver
Signed-off-by: Rajanikanth H.V <rajanikanth.hv@stericsson.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov@linaro.org>
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This patch adds device tree support for battery-temperature-monitor driver
Signed-off-by: Rajanikanth H.V <rajanikanth.hv@stericsson.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov@linaro.org>
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- This patch adds device tree support for fuelgauge driver
- optimize bm devices platform_data usage and of_probe(...)
Note: of_probe() routine for battery managed devices is made
common across all bm drivers.
- test status:
- interrupt numbers assigned differs between legacy and FDT mode.
Signed-off-by: Rajanikanth H.V <rajanikanth.hv@stericsson.com>
Signed-off-by: Anton Vorontsov <anton.vorontsov@linaro.org>
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Pull SPI updates from Grant Likely:
"Primarily SPI device driver bug fixes, one removal of an old driver,
and some new tegra support. There is some core code change too, but
all in all pretty small stuff.
The new features to note are:
- Common code for describing GPIO CS lines in the device tree
- Remove the SPI_BUFSIZ limitation on spi_write_the_read()
- core spi ensures bits_per_word is set correctly
- SPARC can now use SPI"
* tag 'spi-for-linus' of git://git.secretlab.ca/git/linux-2.6: (36 commits)
spi/sparc: Allow of_register_spi_devices for sparc
spi: Remove HOTPLUG section attributes
spi: Add support for specifying 3-wire mode via device tree
spi: Fix comparison of different integer types
spi/orion: Add SPI_CHPA and SPI_CPOL support to kirkwood driver.
spi/sh: Add SH Mobile series as dependency to MSIOF controller
spi/sh-msiof: Remove unneeded clock name
spi: Remove SPI_BUFSIZ restriction on spi_write_then_read()
spi/stmp: remove obsolete driver
spi/clps711x: New SPI master driver
spi: omap2-mcspi: remove duplicate inclusion of linux/err.h
spi: omap2-mcspi: Fix the redifine warning
spi/sh-hspi: add CS manual control support
of_spi: add generic binding support to specify cs gpio
spi: omap2-mcspi: remove duplicated include from spi-omap2-mcspi.c
spi/bitbang: (cosmetic) simplify list manipulation
spi/bitbang: avoid needless loop flow manipulations
spi/omap: fix D0/D1 direction confusion
spi: tegra: add spi driver for sflash controller
spi: Dont call master->setup if not populated
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Linux 3.7-rc8
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This patch allows to specify that a SPI device is connected in 3-wire mode via
device tree.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc.git
Pull in the changes Mark has queued up for SPI
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0384e90b8 ("spi/mcspi: allow configuration of pin directions") did what
it claimed to do the wrong way around. D0/D1 is configured as output by
*clearing* the bits in the conf registers, hence also breaking the
former default behaviour.
Fix this before that change is merged to mainline.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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NVIDIA's Tegra20 have the SPI (SFLASH) controller to
interface with spi flash device which is used for system
boot. Add the spi driver for this controller.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Tegra20/Tegra30 supports the spi interface through its SLINK
controller. Add spi driver for SLINK controller.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Allow D0 to be an input and D1 to be an output, configurable via
platform data and a new DT property.
Based on a patch from Matus Ujhelyi <matus.ujhelyi@streamunlimited.com>
Signed-off-by: Daniel Mack <zonque@gmail.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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This will allow to use gpio for chip select with no modification in the
driver binding
When use the cs-gpios, the gpio number will be passed via the cs_gpio field
and the number of chip select will automatically increased with max(hw cs, gpio cs).
So if for example the controller has 2 CS lines, and the cs-gpios
property looks like this:
cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
Then it should be configured so that num_chipselect = 4 with the
following mapping:
cs0 : &gpio1 0 0
cs1 : native
cs2 : &gpio1 1 0
cs3 : &gpio1 2 0
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: spi-devel-general@lists.sourceforge.net
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
[grant.likely: fixed up type of cs count so min() can do type checking]
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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