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* | | | Merge tag 'armsoc-drivers' of ↵Linus Torvalds2015-09-01
|\ \ \ \ | | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Some releases this branch is nearly empty, others we have more stuff. It tends to gather drivers that need SoC modification or dependencies such that they have to (also) go in through our tree. For this release, we have merged in part of the reset controller tree (with handshake that the parts we have merged in will remain stable), as well as dependencies on a few clock branches. In general, new items here are: - Qualcomm driver for SMM/SMD, which is how they communicate with the coprocessors on (some) of their platforms - memory controller work for ARM's PL172 memory controller - reset drivers for various platforms - PMU power domain support for Marvell platforms - Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits) ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze() ARM: tegra: Disable cpuidle if PSCI is available soc/tegra: pmc: Use existing pclk reference soc/tegra: pmc: Remove unnecessary return statement soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile memory: tegra: Add Tegra210 support memory: tegra: Add support for a variable-size client ID bitfield clk: shmobile: rz: Add CPG/MSTP Clock Domain support clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support clk: shmobile: Add CPG/MSTP Clock Domain support ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets reset: reset-zynq: Adding support for Xilinx Zynq reset controller. docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. MIPS: ath79: Add the reset controller to the AR9132 dtsi reset: Add a driver for the reset controller on the AR71XX/AR9XXX devicetree: Add bindings for the ATH79 reset controller reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property doc: dt: add documentation for lpc1850-rgu reset driver ...
| * | | clk: shmobile: rz: Add CPG/MSTP Clock Domain supportGeert Uytterhoeven2015-08-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain supportGeert Uytterhoeven2015-08-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain supportGeert Uytterhoeven2015-08-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. Also update the reg property in the DT binding doc example to match the actual dtsi, which uses #address-cells and #size-cells == 1, not 2. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain supportGeert Uytterhoeven2015-08-12
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG) driver using the generic PM Domain. This allows to power-manage the module clocks of SoC devices that are part of the CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume. SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed through an MSTP clock should be tagged in DT with a proper "power-domains" property. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
* | | Merge tag 'tegra-for-4.3-clk' of ↵Stephen Boyd2015-08-25
|\ \ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.3-rc1 This contains the DFLL driver needed to implement CPU frequency scaling on Tegra.
| * | clk: tegra: Add binding for the Tegra124 DFLL clocksourceTuomas Tynkkynen2015-07-16
| |/ | | | | | | | | | | | | | | | | | | | | | | The DFLL is the main clocksource for the fast CPU cluster on Tegra124 and also provides automatic CPU rail voltage scaling as well. The DFLL is a separate IP block from the usual Tegra124 clock-and-reset controller, so it gets its own node in the device tree. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | clk: add bindings for the Ux500 clocksLinus Walleij2015-08-24
| | | | | | | | | | | | | | | | | | | | These Ux500 clocks have been around for years and were never properly documented. Add the proper binding documentation. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | dt-bindings: clk: Hi6220: Document stub clock driverLeo Yan2015-08-24
| | | | | | | | | | | | | | | | Document the new compatible for stub clock driver which is used for CPU and DDR's dynamic frequency scaling. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge branch 'clk-rk3368' into clk-nextStephen Boyd2015-07-07
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-rk3368: clk: rockchip: add rk3368 clock controller clk: rockchip: add missing include guards clk: rockchip: add dt-binding header for rk3368 dt-bindings: add documentation of rk3668 clock controller clk: rockchip: define the inverters of rk3066/rk3188 and rk3288 clk: rockchip: fix issues in the mmc-phase clock clk: rockchip: add support for phase inverters clk: rockchip: add COMPOSITE_NOGATE_DIVTBL variant clk: rockchip: protect register macros against multipart values clk: rockchip: fix faulty vip parent name on rk3288 clk: rockchip: rk3288: add CLK_SET_RATE_PARENT to sclk_mac
| * | dt-bindings: add documentation of rk3668 clock controllerHeiko Stuebner2015-07-06
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Add the devicetree binding for the cru on the rk3368 which quite similar structured as previous clock controllers. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* / clk: add gpio controlled clock multiplexerSergej Sawazki2015-07-06
|/ | | | | | | | | | | | | Add a common clock driver for basic gpio controlled clock multiplexers. This driver can be used for devices like 5V41068A or 831721I from IDT or for discrete multiplexer circuits. The 'select' pin selects one of two parent clocks. Cc: Jyri Sarha <jsarha@ti.com> Signed-off-by: Sergej Sawazki <ce3a@gmx.de> [sboyd@codeaurora.org: Fix error paths to free memory and do it in the correct order] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'clk-for-linus-4.2' of ↵Linus Torvalds2015-07-01
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clock framework updates from Michael Turquette: "The changes to the common clock framework for 4.2 are dominated by new drivers and updates to existing ones, as usual. There are some fixes to the framework itself and several cleanups for sparse warnings, etc" * tag 'clk-for-linus-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits) clk: stm32: Add clock driver for STM32F4[23]xxx devices dt-bindings: Document the STM32F4 clock bindings cpufreq: exynos: remove Exynos4210 specific cpufreq driver support ARM: Exynos: switch to using generic cpufreq driver for Exynos4210 clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock clk: samsung: add infrastructure to register cpu clocks clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support doc: dt: add documentation for lpc1850-ccu clk driver clk: add lpc18xx ccu clk driver doc: dt: add documentation for lpc1850-cgu clk driver clk: add lpc18xx cgu clk driver clk: keystone: add support for post divider register for main pll clk: mvebu: flag the crypto clk as CLK_IGNORE_UNUSED clk: cygnus: remove Cygnus dummy clock binding clk: cygnus: add clock support for Broadcom Cygnus clk: Change bcm clocks build dependency clk: iproc: add initial common clock support clk: iproc: define Broadcom iProc clock binding MAINTAINERS: update email for Michael Turquette clk: meson: add some error handling in meson_clk_register_cpu() ...
| * dt-bindings: Document the STM32F4 clock bindingsDaniel Thompson2015-06-22
| | | | | | | | | | | | | | | | | | This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * Merge tag 'tegra-for-4.2-clk' of ↵Michael Turquette2015-06-20
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.2-rc1 This contains the EMC clock driver that's been exhaustively reviewed and tested. It also includes a change to the clock core that allows a clock provider to perform low-level reparenting of clocks. This is required by the EMC clock driver because the reparenting needs to be done at a very specific point in time during the EMC frequency switch.
| | * of: document external-memory-controller property in tegra124-carTomeu Vizoso2015-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | This property contains a phandle to the EMC driver that is needed by the EMC clock to request the EMC driver to do its part of the clock change sequence. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * of: document new emc-timings subnode in nvidia,tegra124-carTomeu Vizoso2015-05-13
| | | | | | | | | | | | | | | | | | | | | The EMC clock needs some extra information for changing its rate. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | doc: dt: add documentation for lpc1850-ccu clk driverJoachim Eastwood2015-06-18
| | | | | | | | | | | | | | | | | | | | | Add DT binding documentation for lpc1850-ccu clk driver. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | doc: dt: add documentation for lpc1850-cgu clk driverJoachim Eastwood2015-06-18
| | | | | | | | | | | | | | | | | | | | | Add DT binding documentation for lpc1850-cgu driver. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | clk: keystone: add support for post divider register for main pllMurali Karicheri2015-06-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Main PLL controller has post divider bits in a separate register in pll controller. Use the value from this register instead of fixed divider when available. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | Merge tag 'sunxi-clocks-for-4.2' of ↵Michael Turquette2015-06-18
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner clocks additions for 4.2 One error fix, and one patch to add support for the USB clock found on the Allwinner A23 and A33
| | * | clk: sunxi: Add support for the usb-clk on sun8i a23 and a33 SoCsHans de Goede2015-06-02
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic interface which gets enabled by almost the same bits as used on the a31 for the 3rd phy, but not exactly the same bits so we need a new compatible for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
| * | clk: cygnus: remove Cygnus dummy clock bindingRay Jui2015-06-18
| | | | | | | | | | | | | | | | | | | | | | | | Remove old Cygnus dummy clock binding document, as it's replaced by Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | clk: iproc: define Broadcom iProc clock bindingRay Jui2015-06-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Document the device tree binding for Broadcom iProc architecture based clock controller Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
| * | Merge branch 'clk-shmobile-for-4.2' of ↵Michael Turquette2015-06-17
| |\ \ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
| | * | clk: shmobile: rz: Document mandatory compatible fallbackGeert Uytterhoeven2015-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic RZ CPG compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | clk: shmobile: rcar-gen2: Document mandatory compatible fallbackGeert Uytterhoeven2015-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic R-Car Gen2 CPG compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | clk: shmobile: mstp: Document mandatory compatible fallbackGeert Uytterhoeven2015-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic MSTP gate clocks compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Also fix a typo (missing plural "s") in the compatible value. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | clk: shmobile: div6: Document mandatory compatible fallbackGeert Uytterhoeven2015-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic CPG DIV6 clock compatible value is mandatory, as the driver uses only this value for matching. Document that this is a fallback that must be present. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | clk: shmobile: r8a7794: Document DIV6 clock bindingsGeert Uytterhoeven2015-06-01
| | | | | | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | clk: shmobile: r8a7793: Document DIV6 clock bindingsUlrich Hecht2015-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Cc: devicetree@vger.kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | clk: shmobile: Add r8a7793 SoC to MSTP bindingsUlrich Hecht2015-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also replaces "R-Car M2" with "R-Car M2-W" to avoid confusion. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Cc: Michael Turquette <mturquette@linaro.org> Cc: devicetree@vger.kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| | * | clk: shmobile: Add r8a7778 SoC to MSTP bindingsUlrich Hecht2015-06-01
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| * | | Merge branch 'clk-meson8b' into clk-nextStephen Boyd2015-06-05
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-meson8b: clk: meson8b: Add support for Meson8b clocks clk: meson: Document bindings for Meson8b clock controller clk: meson: Add support for Meson clock controller
| | * | | clk: meson: Document bindings for Meson8b clock controllerCarlo Caione2015-06-05
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | Add documentation for the clock controller. Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | Add TI CDCE925 I2C controlled clock synthesizer driverMike Looijmans2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver supports the TI CDCE925 programmable clock synthesizer. The chip contains two PLLs with spread-spectrum clocking support and five output dividers. The driver only supports the following setup, and uses a fixed setting for the output muxes: Y1 is derived from the input clock Y2 and Y3 derive from PLL1 Y4 and Y5 derive from PLL2 Given a target output frequency, the driver will set the PLL and divider to best approximate the desired output. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | | clk: mvebu: add missing CESA gate clkBoris Brezillon2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Even if not documented in the datasheet, the Armada 370 SoC can actually gate the CESA (crypto engine) clock. Add an entry in the gating_desc table to be able to reference the CESA gateclk in the crypto node. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | | clk: sirf: add CSR atlas7 clk and reset supportZhiwu Song2015-05-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the hardware node includes both clock and reset support, so it is named as "car". this patch implements Flexible clocks(mux, divider, gate), Selectable clock(mux, divider, gate), root clock(gate),leaf clock(gate), others. it also implements the reset controller functionality. Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Guo Zeng <Guo.Zeng@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | dt-bindings: Add pxa1928 clock bindingRob Herring2015-05-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the clock binding documentation for the Marvell PXA1928 SOC. The PXA1928 has 3 clock control blocks for different subsystems of the chip. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | clk: bindings: Fix assigned-clock-rates descriptionStephen Boyd2015-05-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The binding uses assigned-clock-parents when it should use assigned-clock-rates. Furthermore, the part that describes how they relate to the assigned-clocks property is not clear about what is related. Correct and clarify this part of the binding. Reported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | Merge branch 'clk-fixes' into clk-nextMichael Turquette2015-05-08
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| * | | clk: emev2: Use generic names for device nodesGeert Uytterhoeven2015-05-07
| | |/ | |/| | | | | | | | | | | | | | | | | | | uart -> serial Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-06-27
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: - Improvements to the tlb_dump code - KVM fixes - Add support for appended DTB - Minor improvements to the R12000 support - Minor improvements to the R12000 support - Various platform improvments for BCM47xx - The usual pile of minor cleanups - A number of BPF fixes and improvments - Some improvments to the support for R3000 and DECstations - Some improvments to the ATH79 platform support - A major patchset for the JZ4740 SOC adding support for the CI20 platform - Add support for the Pistachio SOC - Minor BMIPS/BCM63xx platform support improvments. - Avoid "SYNC 0" as memory barrier when unlocking spinlocks - Add support for the XWR-1750 board. - Paul's __cpuinit/__cpuinitdata cleanups. - New Malta CPU board support large memory so enable ZONE_DMA32. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits) MIPS: spinlock: Adjust arch_spin_lock back-off time MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA MIPS: BCM47xx: Simplify handling SPROM revisions MIPS: Cobalt Don't use module_init in non-modular MTD registration. MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/ MIPS: use for_each_sg() MIPS: BCM47xx: Don't select BCMA_HOST_PCI MIPS: BCM47xx: Add helper variable for storing NVRAM length MIPS: IRQ/IP27: Move IRQ allocation API to platform code. MIPS: Replace smp_mb with release barrier function in unlocks. MIPS: i8259: DT support MIPS: Malta: Basic DT plumbing MIPS: include errno.h for ENODEV in mips-cm.h MIPS: Define GCR_GIC_STATUS register fields MIPS: BPF: Introduce BPF ASM helpers MIPS: BPF: Use BPF register names to describe the ABI MIPS: BPF: Move register definition to the BPF header MIPS: net: BPF: Replace RSIZE with SZREG MIPS: BPF: Free up some callee-saved registers MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers ...
| * | | DEVICETREE: Add bindings for the ATH79 PLL controllersAlban Bedel2015-06-21
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Alban Bedel <albeu@free.fr> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | DEVICETREE: Add Ingenic CGU binding documentationPaul Burton2015-06-21
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document the devicetree binding for Ingenic SoC CGUs, and add headers defining the clock specifiers for clocks provided by the JZ4740 & JZ4780 CGU blocks. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10152/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | Merge tag 'armsoc-dt' of ↵Linus Torvalds2015-06-26
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Kevin Hilman: "As usual, quite a few device-tree updates in ARM land. There was one minor churn in DTs due to relicensing under a dual-license, and lots of little additions of new peripherals, features etc, but nothing really exciting to call to your attention. Some higlights, focsuing on support for new SoCs and boards: - AT91: new boards: Overkiz, Acme Systems' Arietta G25 - tegra: HDA support - bcm: new platforms: Buffalo WXR-1900DHP, SmartRG SR400ac, ASUS RT-AC87U - mvebu: new platforms: Compulab CM-A510, Armada 385-based Linksys boards, DLink DNS-327L - OMAP: new platforms: Baltos IR5221, LogicPD Torpedo, Toby-Churchill SL50 - ARM: added support for Juno r1 board - sunxi: A33 SoC support; new boards: A23 EVB, SinA33, GA10H-A33, Mele A1000G - imx: i.MX7D SoC support; new boards: Armadeus Systems APF6, Gateworks GW5510, and aristainetos2 boards - hisilicon: hi6220 SoC support; new boards: 96boards hikey" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (462 commits) ARM: hisi: revert changes from hisi/hip04-dt branch ARM: nomadik: set proper compatible for accelerometer ARM64: juno: add GPIO keys ARM: at91/dt: sama5d4: fix dma conf for aes, sha and tdes nodes ARM: dts: Introduce STM32F429 MCU ARM: socfpga: dts: enable ethernet for Arria10 devkit ARM: dts: k2l: fix the netcp range size ARM: dts: k2e: fix the netcp range size ARM: dts: k2hk: fix the netcp range size ARM: dts: k2l-evm: Add device bindings for netcp driver ARM: dts: k2e-evm: Add device bindings for netcp driver ARM: dts: k2hk-evm: Add device bindings for netcp driver ARM: BCM5301X: Add DT for Asus RT-AC87U ARM: BCM5301X: add IRQ numbers for PCIe controller ARM: BCM5301X: add NAND flash chip description arm64: dts: Add dts files for Hisilicon Hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC ARM: at91/dt: sama5d4ek: mci0 uses slot 0 ARM: at91/dt: kizbox: fix mismatch LED PWM device ...
| * | | Merge tag 'v4.1-rc6' into next/dtKevin Hilman2015-06-11
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux 4.1-rc6 Conflicts: arch/arm/boot/dts/zynq-7000.dtsi Resolution summary: Mainline had an earlier version of the commit, resolve in favor of the newer patch in next/dt branch.
| * | | Merge tag 'hi6620-dt-for-4.2' of git://github.com/hisilicon/linux-hisi into ↵Kevin Hilman2015-06-10
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/dt ARM64: DT: Hisilicon hi6220 soc and hikey board updates for 4.2 - Added the devicetree bindings document for hi6220 SoC - Added the devicetree bindings document for hi6220 clock - Added dts files for hi6220 SoC and hikey board * tag 'hi6620-dt-for-4.2' of git://github.com/hisilicon/linux-hisi: arm64: dts: Add dts files for Hisilicon Hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC
| | * | | clk: hi6220: Document devicetree bindings for hi6220 clockBintian Wang2015-06-05
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document DT files bindings for Hisilicon hi6220 clock. Signed-off-by: Bintian Wang <bintian.wang@huawei.com> Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org> Suggested-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | | Merge tag 'imx-dt-4.2' of ↵Kevin Hilman2015-06-10
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt The i.MX device tree changes for 4.2: - Add device tree for i.MX7D SoC and imx7d-sdb board - New i.MX6 board support: Armadeus Systems APF6, Gateworks GW5510, and aristainetos2 boards - Change LVDS to use simple-panel for nitrogen6x and sabrelite boards - Add Wifi/Bluetooth devices support for cubox-i board - Remove unused regulators and correct OTG roles setting for imx6sl-warp board - Add I2C support for imx23-olinuxino board - Move imx6qdl HDMI device to a better place - Add power-domain for imx6qdl CODA device * tag 'imx-dt-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (24 commits) ARM: dts: imx6dl: add imx6dl gpt specific compatible string ARM: dts: imx6: add DT for aristainetos2 board ARM: dts: cubox-i/hummingboard: Fix the license text ARM: dts: sabrelite: use simple-panel instead of display-timings for LVDS0 ARM: dts: nitrogen6x: use simple-panel instead of display-timings for LVDS0 ARM: dts: add imx7d-sdb support ARM: dts: add imx7d soc dtsi file ARM: dts: Armadeus Systems APF6 family support (i.MX6) ARM: dts: vf610: Nomenclature fixup for PTC12 pin used in RMII mode. ARM: dts: cubox-i: add support for Broadcom Wifi/Bluetooth devices Document: dt: binding: imx: update document for imx7d support ARM: dts: imx6qdl: Add power-domain phandle to CODA device node ARM: dts: Gateworks GW5510 support (i.MX6) ARM: dts: imx6sl-warp: Fix OTG roles ARM: dts: imx6sl-warp: Remove USB regulators ARM: dts: imx6sl-warp: Remove unused regulator ARM: dts: add pinfunc include file to support imx7d ARM: mxs: fix in tree users of ssd1306 ARM: dts: imx6qdl-hummingboard: Add PCIe support ARM: dts: imx23-olinuxino: Add i2c support ...
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