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Add the MSM 64bit cache and M4M error reporting
driver which is useful to detect correctable/uncorrectable
L1, L2, L3 cache errors as well as cluster interconnect
errors. Currently the driver does not handle restoring
L2, L3 error configuration settings in case of their
respective power collapse scenarios.
This is a snapshot of the m4m/cache_erp driver as of
msm-3.14 commit:
3bc54cf86bdc7affa7cd4bf7faa3c57fe8f8819d (Merge "msm:
camera: Add dummy sub module in sensor pipeline")
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Conflicts:
drivers/soc/qcom/Kconfig
drivers/soc/qcom/Makefile
Change-Id: I8ae894a6450d2caa4f8662e01690f4f5938fc0b9
Signed-off-by: Zhiqiang Tu <ztu@codeaurora.org>
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This is a snapshot from msm-3.18 upto the
commit 262b8c5814ec ("edac: cortex_arm64_edac:
modify sbe detection to use perf events") for the
arm64 cache cpu erp bindings.
Change-Id: I7313a121440bf5a455401cf73bd5ef4d6c1506cb
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
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Add support for gladiator cache inter connect error detection
and reporting for msmcobalt
CRs-Fixed: 1000642
Change-Id: I68c5ce09cc77a19eb334a1d8ccce8d577f964316
Signed-off-by: Runmin Wang <runminw@codeaurora.org>
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Add support for gladiator cache interconnect error
detection and reporting. The Gladiator is the cache
coherent interconnect in between two or more CPU
clusters. This driver helps detect the errors related to
snoop data transfer and Distributed Virtual Memory(DVM)
on READ/WRITE transactions.
Change-Id: Ic1aa2066df239672a8ed3d99a63318ed32a11af2
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
Signed-off-by: Srinivas Ramana <sramana@codeaurora.org>
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