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* mmc: core: support DDR52 bus-speed during eMMC clock scalingAsutosh Das2016-05-31
| | | | | | | | | Add support for DDR52 bus-speed mode during clock scaling. The reason for this change is DDR52 can be supported at SVS mode. Change-Id: I68e5fca57ae5cbc154f5dd7001df368900cb3f57 Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
* mmc: sdhci: delay the QoS vote removalAsutosh Das2016-05-31
| | | | | | | | By delaying the QoS vote removal, there is some improvement in performance in single threaded use cases. Change-Id: I80545486057c55c697b72b56d57e2ea47cff86b9 Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
* crypto: ice: general driver clean-upGilad Broner2016-05-31
| | | | | | | | | | | | | | | | | | | * Removed spinlock as it was not locking against anything * Removed conversion of interrupt status to error number as it is not used by API client, and in case several bits are set only 1 error is ever handled and the rest get lost. Instead pass to the client the complete status. * Removed redundant includes, variables * vops structure is returned after performing a lookup in the DTS. There's no need for that as we already know the structure to return. * Other minor corrections Change-Id: I6d2549ce04c9e4b19fdd8fe3dfee03d83bfd9d77 Signed-off-by: Gilad Broner <gbroner@codeaurora.org> [subhashj@codeaurora.org: fixed merge conflicts, dropped ICE & UFS driver changes as they are already present] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: sdhci-msm: Add wakeup functionality support for sdioRitesh Harjani2016-05-31
| | | | | | | | | This adds external GPIO wakeup support to sdhci-msm driver for sdio cards. Change-Id: Ic3e280b975d293ea8adadadafecfa8115fe5f428 Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
* mmc: core: Remove disabling of clk-gating for sdio cardsRitesh Harjani2016-05-31
| | | | | | | | | | This removes disabling of clock-gating for qca6574 & qca9377. Now since async card interrupt support for sdio card has been added(3c5351c0643a), re-enable clk-gating support for sdio cards. Change-Id: Ib497556f10c9c6576a3e0a3592f6755c8725370c Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
* mmc: sdhci: Add asynchronous interrupt support for sdio cardsRitesh Harjani2016-05-31
| | | | | | | | | | | | | | SD host controller have asynchronous interrupt support capability to detect card(sdio) interrupt even when clocks are gated(to save power). This patch add support and enable this capability/feature to of SD host controllers for sdio cards. Change-Id: Ic1945355a19ebfdb3bd000bf8138d8001cea53f6 Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> [subhashj@codeaurora.org: fixed merge conflicts & compilatione error] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: sdhci-msm: Remove MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE capabilityRitesh Harjani2016-05-31
| | | | | | | | | | This removes direct enabling of MMC_CAP2_ASYNC_SDIO_IRQ_4BIT_MODE capability from sdhci-msm driver. This capablity needs to be enabled based on reading HOST_CAPABILITIES register. Change-Id: I74c2877d5906ee9e2180fdb8d50167af6d03b3af Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
* mmc: sdhci-msm: add support for fourth drive strengthTalel Shenhar2016-05-31
| | | | | | | | | | | | This change adds support for new drive strength. Before this change sdhci-msm supported only 3 types of drive strength, starting from eMMC version 5.0 there is additional drive strength. Change-Id: Ib0bf945560107ec732e7ffeb7653d271d8d91c2f Signed-off-by: Talel Shenhar <tatias@codeaurora.org> [subhashj@codeaurora.org: fixed minor merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: core: Make sure host is active before sending pon commandSahitya Tummala2016-05-31
| | | | | | | | | Add mmc_get_card() to make sure host is resumed before sending pon command. Also, add mmc_put_card() after completing pon command so that it can release the host and also vote for runtime suspend. Signed-off-by: Sahitya Tummala <stummala@codeaurora.org> Change-Id: I52f4d854388a608c6a09e55a693e3b36bd801fd8
* mmc: block: workaround for timeout issue with some vendor devicesSubhash Jadavani2016-05-31
| | | | | | | | | | | | | | | | | | Commit 66a7393a3ba9685d1eddfbce72e3ef8f4848f19f ("mmc: block: ensure CMDQ is empty before queuing cache flush") added a workaround for particular vendor's eMMC devices. Workaround was to wait for all the outstanding requests to finish up before queuing the flush request. Now detailed root cause analysis from vendor shows that original issue can happen only if DCMD command is sent to device too quickly (within less than 6 microseconds) after completion of previous small sector (less than 8 sectors) read operations. Hence with this change, we are fine tuning the previous workaround such that it would almost have no impact on the storage benchmark performance numbers. Change-Id: I1df1c5d7bbcd7b526236651077b7dade2626cb30 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [subhashj@codeaurora.org: fixed trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: core: kick cmdq thread after suspendSubhash Jadavani2016-05-31
| | | | | | | | | | | | | eMMC runtime suspend first puts the CMDQ to halt and then sets the card state to suspended after sending out sleep command. If new requests get queued after halting the CMDQ but before the card state has changed to suspended then command queue thread will not be woken up again until some new requests are queued to request queue. And if new request gets queued, we will remain in this state forever. Fix this issue by kicking the CMDQ thread after the suspend completion. Change-Id: I37a03d9a75acf2ab3ebda57da87e246b449abf18 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: sdhci: Panic after dumping SDHC registersVenkat Gopalakrishnan2016-05-31
| | | | | | | | | | | | | eMMC CMDQ is pretty latest feature and we may continue to see issues due to HW & SW immaturity. To debug these issues, we should have the host controller register dumps along with current SW state from rampdumps. This change adds the BUG_ON to crash the system in case of eMMC related command timeouts. Change-Id: Ib832aef6eb9ef3941fbe9e73852929c835e97847 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org> [subhashj@codeaurora.org: fixed trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: block: ensure CMDQ is empty before queuing cache flushSubhash Jadavani2016-05-31
| | | | | | | | | | | | | | | Some devices might stop responding to new commands if device cache flush is queued to host controller while host controller is still processing outstanding requests. To workaround this issue, we are making the cmdq thread to wait for all the oustanding requests to be finished before queuing cache flush command on host controller. Change-Id: I15387734f51ca4cadfc9e11270f14d8a0806a00f Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> [subhashj@codeaurora.org: fixed trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: sdhci-msm: Kconfig: select devfreq ondemand for sdhci-msmRitesh Harjani2016-05-31
| | | | | | | | SDHCI-MSM platform is using devfreq ondemand governor. Select devfreq governor for SDHCI-MSM platform. Change-Id: I0fefe7eb9a578b5d897e7f4258f7c0221950509e Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
* mmc: sdhci-msm: fix compilation errorsKrishna Konda2016-05-31
| | | | | | | | | The current code has some compilation errors when compiling for single core configurations. This fixes those errors. Change-Id: Idd1d1bab343cf5cf1e35f229d913d16a7854f358 Signed-off-by: Krishna Konda <kkonda@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
* mmc: sdhci-msm: disable runtime pm and clock gating for SDIOPavan Anamula2016-05-31
| | | | | | | | Disable power management features for SDIO as the current code is not ready to enable it. Change-Id: I234ebf6cc46d2a3b70bf9ba3f94b4b1abc1acd44 Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
* mmc: card: fix race with shutdown handlerSubhash Jadavani2016-05-31
| | | | | | | | | | | | | | | | | | | | | | | | There could be 2 different race conditions possible with current shutdown handler: 1. Shutdown handler sees that there is no request in queue but mmc-cmdqd might have fetched the request from queue and about to issue it to driver. 2. Shutdown handler keeps looping in the while(1) loop as it sees request being pending in the request queue. But mmc-cmdqd thread doesn't wake up to fetch the requests from the request queue. mmc-cmdqd thread isn't waking up because shutdown path has stopped queue and request came into the queue after that. Once queue is stopped, block layer won't invoke the queue's ->request_fn() callback to notify driver about pending request. Remedy to fix both these race condition is simple. In shutdown handler, make sure that we drain (& complete) all the outstanding requests from the queue and then don't allow any new requests to be queued. Block layer API blk_cleanup_queue() precisely does what we want and this change basically use the same API in shutdown handler. Change-Id: I761ba6a2e2974d955bb72ff993b1cc2c32c9ec29 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: core: Card specific custom settings for SDIOPavan Anamula2016-05-31
| | | | | | | | | | | Add quirk to modify custom settings for QCA6574 and QCA9377 cards. Change-Id: I05e70efa71a8b8b931dfff758194af6220a8bc46 Signed-off-by: Pavan Anamula <pavana@codeaurora.org> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org> [subhashj@codeaurora.org: fixed trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: sdhci-msm: parse and configure TLMM iomem resourceSahitya Tummala2016-05-31
| | | | | | | | Some host controllers may need additional TLMM registers to be configured to enable the IO lines connected to it. Change-Id: Ic334ce653bf13fef5969f08e19f6202377b8fd2e Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
* crypto: ice: Make ICE init & reset API synchronousDinesh K Garg2016-05-31
| | | | | | | | | | | | | | ICE init & reset can be synchronous now because ICE does not need to go to secure side for any ICE configuration. This would simplify interface and make call more efficient. Change-Id: I7aa4e2d3ba3383d25758b21b8ae261a0220f35f9 Signed-off-by: Dinesh K Garg <dineshg@codeaurora.org> Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Gilad Broner <gbroner@codeaurora.org> [subhashj@codeaurora.org: fixed merge conflicts, dropped changes to ICE and UFS driver as they are already present] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: sdhci-msm: add the ability to fake 3.0v support for SDIO devicesPavan Anamula2016-05-31
| | | | | | | | | | | | | | As SDIO spec doesn't allow advertisement of 1.8v support, some SDIO devices advertise support of only 3.0v even though they support 1.8v as well. sdhc3 host controller only supports 1.8v and rejects the initialization of SDIO devices that advertise 3.0v support. This change adds fake support for 3.0v to sdhc host controller. This will allow initialization of SDIO devices that supports 1.8v but advertise 3.0v support. Change-Id: I5a98c54ad4998e6439f83081628c9c083e95bbf0 Signed-off-by: Pavan Anamula <pavana@codeaurora.org>
* mmc: sdhci-msm: dump ICE registers also on errorVenkat Gopalakrishnan2016-05-31
| | | | | | | | | In addition to dumping all the SDCC vendor specific registers, also dump the ICE registers that helps in debugging crypto related errors. Change-Id: I804b0cfd77dec21d45016aafbbb001dafb050241 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* mmc: core/card: maintain clock gating reference count integritySubhash Jadavani2016-05-31
| | | | | | | | | | | | | | | Clock gating logic maintains the reference count which gets incremented with *hold* API call and get decremented with *release* API call. If we want to make sure that clocks are enabled during some operation, we should call *hold* API before the operation and then call *release* API after the operation is finished. So *hold* and *release* should be in pair and called exactly once per operation, any violation of these rules may put the reference count out of sync and can cause issues (like unclocked register access). This change fixes the places where this can go out of sync. Change-Id: I2d784cc31027a551a466beec63ee8cd0a1f67af7 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: cmdq_hci: Add cyclic buffer to keep history of last 32 tasksVenkat Gopalakrishnan2016-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Keep track of task history for the last 32 tasks and dump it along with registers in case of any error for debugging. The log is of the following format: [index] <DATA|DCMD> Task: <lower 32bits> | Args: <upper 32bits> of the task descriptor structure. The values need to be decoded accordingly depending on the data or dcmd task descriptor. The last entry index denotes the latest entry in this list. ---- Circular Task History ---- cmdq-host: Last entry index: 1 cmdq-host: [00]DATA Task: 0x0400002f | Args: 0x00d37d18 cmdq-host: [01]DATA Task: 0x0400002f | Args: 0x00d38118 cmdq-host: [02]DCMD Task: 0x0186402f | Args: 0x03200101 Add a debugfs entry to enable/disable this dynamically. It is disabled by default. This applies only to eMMC devices. Usage: echo Y > /sys/kernel/debug/mmcX/cmdq_task_history X - denotes the slot id Change-Id: I6abf29aa928d3d8270405cfc104241043dadfe45 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org> [subhashj@codeaurora.org: fixed compilation error] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: core: fix issue with sleep cmd that follows an RPMB accessSahitya Tummala2016-05-31
| | | | | | | | | | | | | | | | | If the last access to eMMC before runtime/system suspend is an RPMB access, the partition type within EXT_CSD[179] will be set to RPMB. As per specification, the deselect CMD7 and sleep CMD5 are ignored by the card and are treated as illegal commands in this state. This causes eMMC sleep command to timeout and thus fails runtime/system suspend. Hence, switch to default partition config before sending deselect CMD7 and sleep CMD5. CRs-fixed: 630894 Change-Id: I40f3fb590aeba787de8ca3356a8eed5f2780bcc1 Signed-off-by: Sahitya Tummala <stummala@codeaurora.org> Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org> [subhashj@codeaurora.org: fixed merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: core: Fix CQ runtime suspendSahitya Tummala2016-05-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the timeout issue with mmc_cmdq_halt() that happens in the below scenario - 1. Let us say an RPMB request is processed just before the runtime suspend. The RPMB request will put the controller in HALT state and will put the card in legacy mode. 2. So during runtime suspend, the SW will check for card's state and since it is in legacy mode, it won't call CQ disable host->op. But CQ HW will get reset due to SW reset that gets issued during suspend. 3. If we get another RPMB request, we try to do the runtime resume. But since SW did not invoke CQ disable host->op, it thinks that CQ is still enabled and returns here without enabling CQ. 4. Now the RPMB request tries to put the controller in HALT state but timesout since CQ is still not enabled. Fix this issue by checking for host->card->cmdq_init to determine if the controller is initialized in CQ mode instead of checking for card's state in runtime suspend. This will ensure CQ will be disabled as part of runtime suspend and will be enabled again during runtime resume. Change-Id: I26bf97962d31522a9cb25009c6a048dfff6e4535 Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
* mmc: card: kick command queue thread on completion of RPMB operationSubhash Jadavani2016-05-31
| | | | | | | | | | | | | | During RPMB operation, command queue mode would be disabled and we don't exlicitly move back to command queue once the RPMB operation is completed. We expect the command queue thread to switch operating mode (or partition) to command queue before issuing the new transfers in command queue but command queue thread isn't getting scheduled if we don't wake it up explicitly or if some other new transfer get submitted to the queue. Fix this issue by explicitly waking up the command queue thread after the completion of RPMB operation. Change-Id: I68b2f7989d68b51b4810346458e1966d45aee5a2 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: cmdq_hci: release runtime PM reference after halt/unhaltSubhash Jadavani2016-05-31
| | | | | | | | | | Currently we are not releasing the runtime PM reference count after halt/unhalt completion which basically keeps the runtime PM state to active forever. Fix this by releasing the PM reference count on completion of halt/unhalt operation. Change-Id: I28a37917b49acde7f5d75bf9a639d0eb67a1c169 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: sdhci-msm: dump cmdq debug ram only for command queue hostSubhash Jadavani2016-05-31
| | | | | | | | | Currently we are printing the cmdq debug ram contents during the error handling but this code path shouldn't be executed for non cmdq hosts. Change-Id: Ic397e4378c290b604037e69b7df58200810e981c Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: sdhci-msm: don't bug on PM QoS request counter going negativeSubhash Jadavani2016-05-31
| | | | | | | | | | | Currently we are crashing the system if PM QoS request counter goes negative but this doesn't seem to be right way to handle. We should instead skip decrementing this counter once it reaches 0 and just print a dump stack to know the callstack. This change fixes this as mentioned above. Change-Id: I36fb03b1ddf8e04ecc9fe449496b656db84e77d2 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: core: prevent calling ->post_req 2 times if request submit failsSubhash Jadavani2016-05-31
| | | | | | | | Currently we might end up calling ->post_req() 2 times if we failed to submit the request to host driver. This change fixes this issue. Change-Id: I10b681ab955e0a9126b22df68d3601b75328c949 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: cmdq_hci: Add retry mechanism for cmdq_haltRitesh Harjani2016-05-31
| | | | | | | | | | | Currently all functions which calls cmdq_halt relies upon HALT to pass other wise considers it as a FATAL error (like clk scaling). So add retry mechanism in halt - retry if halt completion timesout & HALT also did not complete(by doing register read). Change-Id: I59e199681e46085f804636f4c07249e6f21de1d5 Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
* mmc: cmdq_hci: fix race between req completion and clearing CQTCNKonstantin Dorfman2016-05-31
| | | | | | | | | | | | | | | | | | CQ irq handler first calls completion path for every notified tag and then clears CQTCN register for all completed tags. This approach could cause following problem: 1) issue context (unblocked by tag completion) issues next request, CQE successfully completes it and notifies task completion through CQTCN again for the same tag. 2) CQ irq handler proceeds to clear CQTCN for the original request. In the above scenario clear of CQTCN register will mask next request completion and issue context will be never unblocked. Hence clear CQTCN first and then notify the request completion. Change-Id: Ie644e24279ca30de42bbc9f8e1ae4326609d38a5 Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org> Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* mmc: sdhci-msm: enable partial initialization in resumeMaya Erez2016-05-31
| | | | | | | | | | | | | | Enable partial init on eMMC devices for using card Sleep/Awake sequence (CMD5). Card will be sent to Sleep state during runtime/system suspend and will be woken up during runtime/system resume. By using this sequence the card doesn't need full initialization which gives time reduction in system/runtime resume path. Change-Id: Ide2b8050b56e858cda7bb22b4acf43b5bd3db786 Signed-off-by: Talel Shenhar <tatias@codeaurora.org> Signed-off-by: Maya Erez <merez@codeaurora.org>
* mmc: cmdq_hci: verify the doorbell bit for DCMD before settingVenkat Gopalakrishnan2016-05-31
| | | | | | | | | We make sure that the doorbell bit for any regular slot is not set before ringing the doorbell for that slot, make sure of the same for DCMD slot too. Change-Id: Ia96e8d6ae0c28aad21f4a3cf46b27c7a5c878971 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* mmc: sdhci_msm: keep a reference to the sdhc host instanceVenkat Gopalakrishnan2016-05-31
| | | | | | | | Keep a reference to the sdhc host instance to retrieve all the necessary data structures in case of a crash for debugging. Change-Id: Ic8d696d53cf48290dbcc92f1567650989dd45755 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* mmc: queue: fix the cmdq thread wake up handlingSubhash Jadavani2016-05-31
| | | | | | | | | | | | | | | | If request has to be requeued (due to any DCMD commmand pending or cmdq being halted) and if we change the task status to interruptible before going to sleep then thread may not wakeup again. Note that blk_requeue_request() doesn't trigger ->request_fn() again to wakeup the thread. Fix this issue by making cmdq thread wait for the completion of DCMD or until the cmdq is unhalted. This change also simplifies the cmdq thread function. Change-Id: Iebffc993241e5fadb2962fedc44576566dc66e9c Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* mmc: debugfs: add debugfs entry to force raise host errorsVenkat Gopalakrishnan2016-05-31
| | | | | | | | | | | | | | | The SDHC spec allows to force raise errors that is useful for debugging error handler routines. Add debugfs entry force_error to trigger host errors from userspace. Check SDHCI_SET_INT_ERROR register for error bitmask info. Usage: echo 0x1 > /sys/kernel/debug/mmcX/force_error X - denotes the slot id Change-Id: I9f67442a79b2645cbdc3020d1a10c0b32840ce32 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org> [subhashj@codeaurora.org: fixed trivial merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: cmdq_hci: Fix issue with triggering queue status after dcmdSahitya Tummala2016-05-31
| | | | | | | | | To trigger queue status command after sending dcmd, we need to set bit 31 of CQ_VENDOR_CFG register. But the current code incorrectly sets bit 31 of CQCTL register. Change-Id: Ic5b914cf6a5237ac51b2104453caba2c49c1efbc Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
* mmc: sdhci-msm: use max discard size supported for mmc queueKrishna Konda2016-05-31
| | | | | | | | | | | | With newer mmc drivers, max_discard_to has been remvoed from the sdhci driver. So instead of incorrectly using max_busy_timeout for calculating max_discard to be used by mmc queue, use the mmc cap to indicate that the max discard should be used for msm sdhci driver. Change-Id: I424cd0a5ee9ffd7199be58a5a091984c5fcda52f Signed-off-by: Krishna Konda <kkonda@codeaurora.org> [subhashj@codeaurora.org: fixed merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: core: allow hosts to specify a large discard sizeKrishna Konda2016-05-31
| | | | | | | | | | | max_busy_timeout is used to decide whether R1B response should be used or a R1 response should be used. This is also used to decide what the discard size of mmc queue (registered with block layer) can be set to. In order to keep both the features in place, this change will allow for hosts to specify a larger discard size while still specifying max_busy_timeout. Change-Id: I1e607329c4377897a7cb4086db02cbc150bd02b7 Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
* mmc: core: fix downdifferential for clock scalingSubhash Jadavani2016-05-31
| | | | | | | | | | | "downdifferential" parameter of devfreq's simple ondemand governor supposed to report expected difference between upthreshold and downthreshold value. In other words, downdifferential = upthreshold - downthreshold. But currently downdifferential is set to same as downthreshold, this change fixes this issue. Change-Id: Ic2e762d192f1fed8f94d4d2579d6a4b5d4c2c8b5 Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: cmdq_hci: Fix ADMA error issueSahitya Tummala2016-05-31
| | | | | | | | | | | | | | | | | | | | | The controller triggers an ADMA error when ADMA engine is configured and used in 32-bit mode. This is because the current code always writes 64-bit address to 32-bit address field of a transfer descriptor (bits [63:32]). This corrupts the first 32-bit value of the next transfer descriptor. Below scenario describes how ADMA error can happen - 1. Req#1 - uses slot 1, prepares it's descriptors, queues to the controller 2. Req#2 - uses slot 0, prepares max descriptors (cq_host->mmc->max_segs). 3. Req#1 gets ADMA error from the controller. At step 2, when it prepares the last transfer descriptor (max_segs), it overwrites the 32-bit address field with a 64-bit address and thus corrupts the first entry of slot 1 transfer descriptor. Change-Id: I3eb2dbb40c76ec77626f647d6ec24df4a0858fcb Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
* mmc: sdhci-msm: add sysfs entries for PM QoSGilad Broner2016-05-31
| | | | | | | | Add sysfs entries to allow getting the current status of PM QoS voting and enable or disable voting. Change-Id: If5b8e4b155090343112916c9c57a766bb2104e10 Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
* mmc: sdhci-msm: add offset to CMDQ_COMMAND_DEBUG_RAM_x registers accessKonstantin Dorfman2016-05-31
| | | | | | | | | | | | | Starting from MCI_VERSION 4.2.0 use a different offset for the following registers: PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_n PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_WRAPAROUND PERIPH_SS_SDC1_SDCC_HC_CMDQ_COMMAND_DEBUG_RAM_OVERLAP In addition, move dump debug ram functionality to the MSM specific file. Change-Id: I3b0f5101150de9f2c190ce69b306bd151cbb65ae Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
* mmc: block: stop BKOPs before handling RPMB and ioctlMaya Erez2016-05-31
| | | | | | | | | | | IOCTL and RPMB commands can be issued while the device is busy with background Operations handling. Stop the device BKOPs before handling the RPMB / IOCTL command. Change-Id: I088f74c77026ccd901276e1214e4466ac7815bf1 Signed-off-by: Maya Erez <merez@codeaurora.org> [subhashj@codeaurora.org: fixed merge conflicts] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: block: fix DCMD timeout err handlingVenkat Gopalakrishnan2016-05-31
| | | | | | | | | | DCMD requests don't have data, check for the data pointer before accessing it to prevent null pointer dereference in case of DCMD timeout err. Also signal a completion event for non flush requests like discard that wait for the completion of DCMD request. Change-Id: Ia71a5f1e278a039ba22f6ac42614d9ae79dba7e9 Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
* mmc: card: read the firmware version from ext_csdAsutosh Das2016-05-31
| | | | | | | | | | | | Read the firmware version from ext_csd register and print it for debugging purpose. Change-Id: I4c1fefd5bff753915c9858fb35c958335986c778 Signed-off-by: Asutosh Das <asutoshd@codeaurora.org> Signed-off-by: Sahitya Tummala <stummala@codeaurora.org> [subhashj@codeaurora.org: fixed trivial merge conflicts and compilation errors] Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
* mmc: sdhci-msm-ice: add crypto register dump for debugSahitya Tummala2016-05-31
| | | | | | | | Dump crypto related register information during error for debugging purpose. Change-Id: I8976e8c0b5e9bda910634464202578dbacd7666e Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
* mmc: core: check if manual BKOPS is ongoing before scalingMaya Erez2016-05-31
| | | | | | | | | | | Clock scaling commands are not allowed to be sent when the device performs manual BKOPS. In case the device is busy with manual BKOPS, skip the clock scaling and allow the device to continue the BKOPS. Clock scaling will be invoked again later by dev freq. Change-Id: I78b505326d245b1ddcd9d6f1cdd4294850889d45 Signed-off-by: Maya Erez <merez@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-07 03:45:55 +0000