diff options
Diffstat (limited to 'include/uapi/media')
31 files changed, 11837 insertions, 0 deletions
diff --git a/include/uapi/media/Kbuild b/include/uapi/media/Kbuild new file mode 100644 index 000000000000..640002326ace --- /dev/null +++ b/include/uapi/media/Kbuild @@ -0,0 +1,23 @@ +header-y += ais/ +header-y += msm_cam_sensor.h +header-y += msm_camera.h +header-y += msm_camsensor_sdk.h +header-y += msm_fd.h +header-y += msm_gemini.h +header-y += msm_gestures.h +header-y += msm_isp.h +header-y += msm_jpeg.h +header-y += msm_jpeg_dma.h +header-y += msm_media_info.h +header-y += msm_mercury.h +header-y += msm_sde_rotator.h +header-y += msm_vidc.h +header-y += msm_vpu.h +header-y += msmb_camera.h +header-y += msmb_generic_buf_mgr.h +header-y += msmb_isp.h +header-y += msmb_ispif.h +header-y += msmb_pproc.h +header-y += radio-iris.h +header-y += radio-iris-commands.h +header-y += msm_ba.h diff --git a/include/uapi/media/ais/Kbuild b/include/uapi/media/ais/Kbuild new file mode 100644 index 000000000000..c8d50c7d077c --- /dev/null +++ b/include/uapi/media/ais/Kbuild @@ -0,0 +1,7 @@ +header-y += msm_ais.h +header-y += msm_ais_buf_mgr.h +header-y += msm_ais_isp.h +header-y += msm_ais_ispif.h +header-y += msm_ais_sensor.h +header-y += msm_ais_sensor_sdk.h +header-y += msm_ais_mgr.h diff --git a/include/uapi/media/ais/msm_ais.h b/include/uapi/media/ais/msm_ais.h new file mode 100644 index 000000000000..c393a2a7f636 --- /dev/null +++ b/include/uapi/media/ais/msm_ais.h @@ -0,0 +1,231 @@ +#ifndef __UAPI_MSM_AIS__ +#define __UAPI_MSM_AIS__ + +#include <linux/videodev2.h> +#include <linux/types.h> +#include <linux/ioctl.h> + +#define MSM_CAM_LOGSYNC_FILE_NAME "logsync" +#define MSM_CAM_LOGSYNC_FILE_BASEDIR "camera" + +#define MSM_CAM_V4L2_IOCTL_NOTIFY \ + _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_NOTIFY_META \ + _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_CMD_ACK \ + _IOW('V', BASE_VIDIOC_PRIVATE + 32, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR \ + _IOW('V', BASE_VIDIOC_PRIVATE + 33, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_NOTIFY_DEBUG \ + _IOW('V', BASE_VIDIOC_PRIVATE + 34, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_DAEMON_DISABLED \ + _IOW('V', BASE_VIDIOC_PRIVATE + 35, struct msm_v4l2_event_data) + +#define QCAMERA_DEVICE_GROUP_ID 1 +#define QCAMERA_VNODE_GROUP_ID 2 +#define MSM_CAMERA_NAME "msm_camera" +#define MSM_CONFIGURATION_NAME "msm_config" + +#define MSM_CAMERA_SUBDEV_UNKNOWN 0 +#define MSM_CAMERA_SUBDEV_CSIPHY 1 +#define MSM_CAMERA_SUBDEV_CSID 2 +#define MSM_CAMERA_SUBDEV_ISPIF 3 +#define MSM_CAMERA_SUBDEV_VFE 4 +#define MSM_CAMERA_SUBDEV_AXI 5 +#define MSM_CAMERA_SUBDEV_VPE 6 +#define MSM_CAMERA_SUBDEV_SENSOR 7 +#define MSM_CAMERA_SUBDEV_ACTUATOR 8 +#define MSM_CAMERA_SUBDEV_EEPROM 9 +#define MSM_CAMERA_SUBDEV_CPP 10 +#define MSM_CAMERA_SUBDEV_CCI 11 +#define MSM_CAMERA_SUBDEV_LED_FLASH 12 +#define MSM_CAMERA_SUBDEV_STROBE_FLASH 13 +#define MSM_CAMERA_SUBDEV_BUF_MNGR 14 +#define MSM_CAMERA_SUBDEV_SENSOR_INIT 15 +#define MSM_CAMERA_SUBDEV_OIS 16 +#define MSM_CAMERA_SUBDEV_FLASH 17 +#define MSM_CAMERA_SUBDEV_IR_LED 18 +#define MSM_CAMERA_SUBDEV_IR_CUT 19 +#define MSM_CAMERA_SUBDEV_EXT 20 +#define MSM_CAMERA_SUBDEV_AIS_MNGR 21 + +#define MSM_MAX_CAMERA_SENSORS 5 + +/* The below macro is defined to put an upper limit on maximum + * number of buffer requested per stream. In case of extremely + * large value for number of buffer due to data structure corruption + * we return error to avoid integer overflow. Group processing + * can have max of 9 groups of 8 bufs each. This value may be + * configured in future + */ +#define MSM_CAMERA_MAX_STREAM_BUF 72 + +/* Max batch size of processing */ +#define MSM_CAMERA_MAX_USER_BUFF_CNT 16 + +/* featur base */ +#define MSM_CAMERA_FEATURE_BASE 0x00010000 +#define MSM_CAMERA_FEATURE_SHUTDOWN (MSM_CAMERA_FEATURE_BASE + 1) + +#define MSM_CAMERA_STATUS_BASE 0x00020000 +#define MSM_CAMERA_STATUS_FAIL (MSM_CAMERA_STATUS_BASE + 1) +#define MSM_CAMERA_STATUS_SUCCESS (MSM_CAMERA_STATUS_BASE + 2) + +/* event type */ +#define MSM_CAMERA_V4L2_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x00002000) + +/* event id */ +#define MSM_CAMERA_EVENT_MIN 0 +#define MSM_CAMERA_NEW_SESSION (MSM_CAMERA_EVENT_MIN + 1) +#define MSM_CAMERA_DEL_SESSION (MSM_CAMERA_EVENT_MIN + 2) +#define MSM_CAMERA_SET_PARM (MSM_CAMERA_EVENT_MIN + 3) +#define MSM_CAMERA_GET_PARM (MSM_CAMERA_EVENT_MIN + 4) +#define MSM_CAMERA_MAPPING_CFG (MSM_CAMERA_EVENT_MIN + 5) +#define MSM_CAMERA_MAPPING_SES (MSM_CAMERA_EVENT_MIN + 6) +#define MSM_CAMERA_MSM_NOTIFY (MSM_CAMERA_EVENT_MIN + 7) +#define MSM_CAMERA_EVENT_MAX (MSM_CAMERA_EVENT_MIN + 8) + +/* data.command */ +#define MSM_CAMERA_PRIV_S_CROP (V4L2_CID_PRIVATE_BASE + 1) +#define MSM_CAMERA_PRIV_G_CROP (V4L2_CID_PRIVATE_BASE + 2) +#define MSM_CAMERA_PRIV_G_FMT (V4L2_CID_PRIVATE_BASE + 3) +#define MSM_CAMERA_PRIV_S_FMT (V4L2_CID_PRIVATE_BASE + 4) +#define MSM_CAMERA_PRIV_TRY_FMT (V4L2_CID_PRIVATE_BASE + 5) +#define MSM_CAMERA_PRIV_METADATA (V4L2_CID_PRIVATE_BASE + 6) +#define MSM_CAMERA_PRIV_QUERY_CAP (V4L2_CID_PRIVATE_BASE + 7) +#define MSM_CAMERA_PRIV_STREAM_ON (V4L2_CID_PRIVATE_BASE + 8) +#define MSM_CAMERA_PRIV_STREAM_OFF (V4L2_CID_PRIVATE_BASE + 9) +#define MSM_CAMERA_PRIV_NEW_STREAM (V4L2_CID_PRIVATE_BASE + 10) +#define MSM_CAMERA_PRIV_DEL_STREAM (V4L2_CID_PRIVATE_BASE + 11) +#define MSM_CAMERA_PRIV_SHUTDOWN (V4L2_CID_PRIVATE_BASE + 12) +#define MSM_CAMERA_PRIV_STREAM_INFO_SYNC \ + (V4L2_CID_PRIVATE_BASE + 13) +#define MSM_CAMERA_PRIV_G_SESSION_ID (V4L2_CID_PRIVATE_BASE + 14) +#define MSM_CAMERA_PRIV_CMD_MAX 20 + +/* data.status - success */ +#define MSM_CAMERA_CMD_SUCCESS 0x00000001 +#define MSM_CAMERA_BUF_MAP_SUCCESS 0x00000002 + +/* data.status - error */ +#define MSM_CAMERA_ERR_EVT_BASE 0x00010000 +#define MSM_CAMERA_ERR_CMD_FAIL (MSM_CAMERA_ERR_EVT_BASE + 1) +#define MSM_CAMERA_ERR_MAPPING (MSM_CAMERA_ERR_EVT_BASE + 2) +#define MSM_CAMERA_ERR_DEVICE_BUSY (MSM_CAMERA_ERR_EVT_BASE + 3) + +/* The msm_v4l2_event_data structure should match the + * v4l2_event.u.data field. + * should not exceed 16 elements + */ +struct msm_v4l2_event_data { + /*word 0*/ + unsigned int command; + /*word 1*/ + unsigned int status; + /*word 2*/ + unsigned int session_id; + /*word 3*/ + unsigned int stream_id; + /*word 4*/ + unsigned int map_op; + /*word 5*/ + unsigned int map_buf_idx; + /*word 6*/ + unsigned int notify; + /*word 7*/ + unsigned int arg_value; + /*word 8*/ + unsigned int ret_value; + /*word 9*/ + unsigned int v4l2_event_type; + /*word 10*/ + unsigned int v4l2_event_id; + /*word 11*/ + unsigned int handle; + /*word 12*/ + unsigned int nop6; + /*word 13*/ + unsigned int nop7; + /*word 14*/ + unsigned int nop8; + /*word 15*/ + unsigned int nop9; +}; + +/* map to v4l2_format.fmt.raw_data */ +struct msm_v4l2_format_data { + enum v4l2_buf_type type; + unsigned int width; + unsigned int height; + unsigned int pixelformat; /* FOURCC */ + unsigned char num_planes; + unsigned int plane_sizes[VIDEO_MAX_PLANES]; +}; + +/* MSM Four-character-code (FOURCC) */ +#define msm_v4l2_fourcc(a, b, c, d)\ + ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) |\ + ((__u32)(d) << 24)) + +/* Composite stats */ +#define MSM_V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M') +/* AEC stats */ +#define MSM_V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E') +/* AF stats */ +#define MSM_V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F') +/* AWB stats */ +#define MSM_V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B') +/* IHIST stats */ +#define MSM_V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T') +/* Column count stats */ +#define MSM_V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S') +/* Row count stats */ +#define MSM_V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S') +/* Bayer Grid stats */ +#define MSM_V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G') +/* Bayer focus stats */ +#define MSM_V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F') +/* Bayer hist stats */ +#define MSM_V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T') + +enum smmu_attach_mode { + NON_SECURE_MODE = 0x01, + SECURE_MODE = 0x02, + MAX_PROTECTION_MODE = 0x03, +}; + +struct msm_camera_smmu_attach_type { + enum smmu_attach_mode attach; +}; + +struct msm_camera_user_buf_cont_t { + unsigned int buf_cnt; + unsigned int buf_idx[MSM_CAMERA_MAX_USER_BUFF_CNT]; +}; + +struct msm_camera_return_buf { + __u32 index; + __u32 reserved; +}; + +#define MSM_CAMERA_PRIV_IOCTL_ID_BASE 0 +#define MSM_CAMERA_PRIV_IOCTL_ID_RETURN_BUF 1 + +struct msm_camera_private_ioctl_arg { + __u32 id; + __u32 size; + __u32 result; + __u32 reserved; + __u64 ioctl_ptr; +}; + +#define VIDIOC_MSM_CAMERA_PRIVATE_IOCTL_CMD \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_private_ioctl_arg) + +#endif /* __UAPI_MSM_AIS__ */ + diff --git a/include/uapi/media/ais/msm_ais_buf_mgr.h b/include/uapi/media/ais/msm_ais_buf_mgr.h new file mode 100644 index 000000000000..08383b63897c --- /dev/null +++ b/include/uapi/media/ais/msm_ais_buf_mgr.h @@ -0,0 +1,66 @@ +#ifndef __UAPI_MEDIA_MSM_AIS_BUF_MGR_H__ +#define __UAPI_MEDIA_MSM_AIS_BUF_MGR_H__ + +#include <media/ais/msm_ais.h> + +enum msm_camera_buf_mngr_cmd { + MSM_CAMERA_BUF_MNGR_CONT_MAP, + MSM_CAMERA_BUF_MNGR_CONT_UNMAP, + MSM_CAMERA_BUF_MNGR_CONT_MAX, +}; + +enum msm_camera_buf_mngr_buf_type { + MSM_CAMERA_BUF_MNGR_BUF_PLANAR, + MSM_CAMERA_BUF_MNGR_BUF_USER, + MSM_CAMERA_BUF_MNGR_BUF_INVALID, +}; + +struct msm_buf_mngr_info { + uint32_t session_id; + uint32_t stream_id; + uint32_t frame_id; + struct timeval timestamp; + uint32_t index; + uint32_t reserved; + enum msm_camera_buf_mngr_buf_type type; + struct msm_camera_user_buf_cont_t user_buf; +}; + +struct msm_buf_mngr_main_cont_info { + uint32_t session_id; + uint32_t stream_id; + enum msm_camera_buf_mngr_cmd cmd; + uint32_t cnt; + int32_t cont_fd; +}; + +#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_BASE 0 +#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_GET_BUF_BY_IDX 1 + +#define VIDIOC_MSM_BUF_MNGR_GET_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_PUT_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_BUF_DONE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_CONT_CMD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 36, struct msm_buf_mngr_main_cont_info) + +#define VIDIOC_MSM_BUF_MNGR_INIT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 37, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_DEINIT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 38, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_FLUSH \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 39, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_IOCTL_CMD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 40, \ + struct msm_camera_private_ioctl_arg) + +#endif + diff --git a/include/uapi/media/ais/msm_ais_isp.h b/include/uapi/media/ais/msm_ais_isp.h new file mode 100644 index 000000000000..649173dd4404 --- /dev/null +++ b/include/uapi/media/ais/msm_ais_isp.h @@ -0,0 +1,1157 @@ +#ifndef __UAPI_MSM_AIS_ISP__ +#define __UAPI_MSM_AIS_ISP__ + +#include <linux/videodev2.h> + +#define MAX_PLANES_PER_STREAM 3 +#define MAX_NUM_STREAM 7 + +#define ISP_VERSION_48 48 +#define ISP_VERSION_47 47 +#define ISP_VERSION_46 46 +#define ISP_VERSION_44 44 +#define ISP_VERSION_40 40 +#define ISP_VERSION_32 32 +#define ISP_NATIVE_BUF_BIT (0x10000 << 0) +#define ISP0_BIT (0x10000 << 1) +#define ISP1_BIT (0x10000 << 2) +#define ISP_META_CHANNEL_BIT (0x10000 << 3) +#define ISP_SCRATCH_BUF_BIT (0x10000 << 4) +#define ISP_OFFLINE_STATS_BIT (0x10000 << 5) +#define ISP_SVHDR_IN_BIT (0x10000 << 6) /* RDI hw stream for SVHDR */ +#define ISP_SVHDR_OUT_BIT (0x10000 << 7) /* SVHDR output bufq stream*/ + +#define ISP_STATS_STREAM_BIT 0x80000000 + +#define INTERLACE_SUPPORT_OLD_REMOVED + +struct msm_vfe_cfg_cmd_list; + +enum ISP_START_PIXEL_PATTERN { + ISP_BAYER_RGRGRG, + ISP_BAYER_GRGRGR, + ISP_BAYER_BGBGBG, + ISP_BAYER_GBGBGB, + ISP_YUV_YCbYCr, + ISP_YUV_YCrYCb, + ISP_YUV_CbYCrY, + ISP_YUV_CrYCbY, + ISP_PIX_PATTERN_MAX +}; + +enum msm_vfe_plane_fmt { + Y_PLANE, + CB_PLANE, + CR_PLANE, + CRCB_PLANE, + CBCR_PLANE, + RAW_PLANE, + RDI_PLANE, + VFE_PLANE_FMT_MAX +}; + +enum msm_vfe_input_src { + VFE_PIX_0, + VFE_RAW_0, + VFE_RAW_1, + VFE_RAW_2, + VFE_SRC_MAX, +}; + +enum msm_vfe_axi_stream_src { + PIX_ENCODER, + PIX_VIEWFINDER, + PIX_VIDEO, + ARGB_RAW, + CAMIF_RAW, + IDEAL_RAW, + RDI_INTF_0, + RDI_INTF_1, + RDI_INTF_2, + VFE_AXI_SRC_MAX +}; + +enum msm_vfe_frame_skip_pattern { + NO_SKIP, + EVERY_2FRAME, + EVERY_3FRAME, + EVERY_4FRAME, + EVERY_5FRAME, + EVERY_6FRAME, + EVERY_7FRAME, + EVERY_8FRAME, + EVERY_16FRAME, + EVERY_32FRAME, + SKIP_ALL, + SKIP_RANGE, + MAX_SKIP, +}; + +/* + * Define an unused period. When this period is set it means that the stream is + * stopped(i.e the pattern is 0). We don't track the current pattern, just the + * period defines what the pattern is, if period is this then pattern is 0 else + * pattern is 1 + */ +#define MSM_VFE_STREAM_STOP_PERIOD 15 + +enum msm_isp_stats_type { + MSM_ISP_STATS_AEC, /* legacy based AEC */ + MSM_ISP_STATS_AF, /* legacy based AF */ + MSM_ISP_STATS_AWB, /* legacy based AWB */ + MSM_ISP_STATS_RS, /* legacy based RS */ + MSM_ISP_STATS_CS, /* legacy based CS */ + MSM_ISP_STATS_IHIST, /* legacy based HIST */ + MSM_ISP_STATS_SKIN, /* legacy based SKIN */ + MSM_ISP_STATS_BG, /* Bayer Grids */ + MSM_ISP_STATS_BF, /* Bayer Focus */ + MSM_ISP_STATS_BE, /* Bayer Exposure*/ + MSM_ISP_STATS_BHIST, /* Bayer Hist */ + MSM_ISP_STATS_BF_SCALE, /* Bayer Focus scale */ + MSM_ISP_STATS_HDR_BE, /* HDR Bayer Exposure */ + MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */ + MSM_ISP_STATS_AEC_BG, /* AEC BG */ + MSM_ISP_STATS_MAX /* MAX */ +}; + +/* + * @stats_type_mask: Stats type mask (enum msm_isp_stats_type). + * @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src) + * @skip_mode: skip pattern, if skip mode is range only then min/max is used + * @min_frame_id: minimum frame id (valid only if skip_mode = RANGE) + * @max_frame_id: maximum frame id (valid only if skip_mode = RANGE) +*/ +struct msm_isp_sw_framskip { + uint32_t stats_type_mask; + uint32_t stream_src_mask; + enum msm_vfe_frame_skip_pattern skip_mode; + uint32_t min_frame_id; + uint32_t max_frame_id; +}; + +enum msm_vfe_testgen_color_pattern { + COLOR_BAR_8_COLOR, + UNICOLOR_WHITE, + UNICOLOR_YELLOW, + UNICOLOR_CYAN, + UNICOLOR_GREEN, + UNICOLOR_MAGENTA, + UNICOLOR_RED, + UNICOLOR_BLUE, + UNICOLOR_BLACK, + MAX_COLOR, +}; + +enum msm_vfe_camif_input { + CAMIF_DISABLED, + CAMIF_PAD_REG_INPUT, + CAMIF_MIDDI_INPUT, + CAMIF_MIPI_INPUT, +}; + +struct msm_vfe_fetch_engine_cfg { + uint32_t input_format; + uint32_t buf_width; + uint32_t buf_height; + uint32_t fetch_width; + uint32_t fetch_height; + uint32_t x_offset; + uint32_t y_offset; + uint32_t buf_stride; +}; + +enum msm_vfe_camif_output_format { + CAMIF_QCOM_RAW, + CAMIF_MIPI_RAW, + CAMIF_PLAIN_8, + CAMIF_PLAIN_16, + CAMIF_MAX_FORMAT, +}; + +/* + * Camif output general configuration + */ +struct msm_vfe_camif_subsample_cfg { + uint32_t irq_subsample_period; + uint32_t irq_subsample_pattern; + uint32_t sof_counter_step; + uint32_t pixel_skip; + uint32_t line_skip; + uint32_t first_line; + uint32_t last_line; + uint32_t first_pixel; + uint32_t last_pixel; + enum msm_vfe_camif_output_format output_format; +}; + +/* + * Camif frame and window configuration + */ +struct msm_vfe_camif_cfg { + uint32_t lines_per_frame; + uint32_t pixels_per_line; + uint32_t first_pixel; + uint32_t last_pixel; + uint32_t first_line; + uint32_t last_line; + uint32_t epoch_line0; + uint32_t epoch_line1; + uint32_t is_split; + uint32_t vsync_edge; + uint32_t hsync_edge; + uint32_t sync_mode; + uint32_t vfe_subsample_en; + uint32_t bus_subsample_en; + uint32_t vfe_output_en; + uint32_t bus_output_en; + uint32_t binning_enable; + uint32_t irq_subsample_period; + uint32_t misr_en; + uint32_t irq_subsample_pattern; + uint32_t frame_based_en; + uint32_t frame_drop_Period; + uint32_t frame_drop_pattern; + uint32_t frame_drop_irq_en; + enum msm_vfe_camif_input camif_input; + struct msm_vfe_camif_subsample_cfg subsample_cfg; +}; + +struct msm_vfe_testgen_cfg { + uint32_t lines_per_frame; + uint32_t pixels_per_line; + uint32_t v_blank; + uint32_t h_blank; + enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern; + uint32_t rotate_period; + enum msm_vfe_testgen_color_pattern color_bar_pattern; + uint32_t burst_num_frame; +}; + +enum msm_vfe_inputmux { + CAMIF, + TESTGEN, + EXTERNAL_READ, +}; + +enum msm_vfe_stats_composite_group { + STATS_COMPOSITE_GRP_NONE, + STATS_COMPOSITE_GRP_1, + STATS_COMPOSITE_GRP_2, + STATS_COMPOSITE_GRP_MAX, +}; + +enum msm_vfe_hvx_streaming_cmd { + HVX_DISABLE, + HVX_ONE_WAY, + HVX_ROUND_TRIP +}; + +struct msm_vfe_pix_cfg { + struct msm_vfe_camif_cfg camif_cfg; + struct msm_vfe_testgen_cfg testgen_cfg; + struct msm_vfe_fetch_engine_cfg fetch_engine_cfg; + enum msm_vfe_inputmux input_mux; + enum ISP_START_PIXEL_PATTERN pixel_pattern; + uint32_t input_format; + enum msm_vfe_hvx_streaming_cmd hvx_cmd; + uint32_t is_split; +}; + +struct msm_vfe_rdi_cfg { + uint8_t cid; + uint8_t frame_based; +}; + +struct msm_vfe_input_cfg { + union { + struct msm_vfe_pix_cfg pix_cfg; + struct msm_vfe_rdi_cfg rdi_cfg; + } d; + enum msm_vfe_input_src input_src; + uint32_t input_pix_clk; +}; + +struct msm_vfe_fetch_eng_start { + uint32_t session_id; + uint32_t stream_id; + uint32_t buf_idx; + uint8_t offline_mode; + uint32_t fd; + uint32_t buf_addr; + uint32_t frame_id; +}; + +enum msm_vfe_fetch_eng_pass { + OFFLINE_FIRST_PASS, + OFFLINE_SECOND_PASS, + OFFLINE_MAX_PASS, +}; + +struct msm_vfe_fetch_eng_multi_pass_start { + uint32_t session_id; + uint32_t stream_id; + uint32_t buf_idx; + uint8_t offline_mode; + uint32_t fd; + uint32_t buf_addr; + uint32_t frame_id; + uint32_t output_buf_idx; + uint32_t input_buf_offset; + enum msm_vfe_fetch_eng_pass offline_pass; + uint32_t output_stream_id; +}; + +struct msm_vfe_axi_plane_cfg { + uint32_t output_width; /*Include padding*/ + uint32_t output_height; + uint32_t output_stride; + uint32_t output_scan_lines; + uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/ + uint32_t plane_addr_offset; + uint8_t csid_src; /*RDI 0-2*/ + uint8_t rdi_cid;/*CID 1-16*/ +}; + +enum msm_stream_memory_input_t { + MEMORY_INPUT_DISABLED, + MEMORY_INPUT_ENABLED +}; + +struct msm_vfe_axi_stream_request_cmd { + uint32_t session_id; + uint32_t stream_id; + uint32_t vt_enable; + uint32_t output_format;/*Planar/RAW/Misc*/ + enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/ + struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; + + uint32_t burst_count; + uint32_t hfr_mode; + uint8_t frame_base; + + uint32_t init_frame_drop; /*MAX 31 Frames*/ + enum msm_vfe_frame_skip_pattern frame_skip_pattern; + uint8_t buf_divert; /* if TRUE no vb2 buf done. */ + /*Return values*/ + uint32_t axi_stream_handle; + uint32_t controllable_output; + uint32_t burst_len; + /* Flag indicating memory input stream */ + enum msm_stream_memory_input_t memory_input; +}; + +struct msm_vfe_axi_stream_release_cmd { + uint32_t stream_handle; +}; + +enum msm_vfe_axi_stream_cmd { + STOP_STREAM, + START_STREAM, + STOP_IMMEDIATELY, +}; + +enum msm_vfe_hw_state { + HW_STATE_NONE, + HW_STATE_SLEEP, + HW_STATE_AWAKE, +}; + +struct msm_vfe_axi_stream_cfg_cmd { + uint8_t num_streams; + uint32_t stream_handle[VFE_AXI_SRC_MAX]; + enum msm_vfe_axi_stream_cmd cmd; + uint8_t sync_frame_id_src; + enum msm_vfe_hw_state hw_state; +}; + +enum msm_vfe_axi_stream_update_type { + ENABLE_STREAM_BUF_DIVERT, + DISABLE_STREAM_BUF_DIVERT, + UPDATE_STREAM_FRAMEDROP_PATTERN, + UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, + UPDATE_STREAM_AXI_CONFIG, + UPDATE_STREAM_REQUEST_FRAMES, + UPDATE_STREAM_ADD_BUFQ, + UPDATE_STREAM_REMOVE_BUFQ, + UPDATE_STREAM_SW_FRAME_DROP, + UPDATE_STREAM_REQUEST_FRAMES_VER2, + UPDATE_STREAM_OFFLINE_AXI_CONFIG, +}; +#define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2 + +enum msm_vfe_iommu_type { + IOMMU_ATTACH, + IOMMU_DETACH, +}; + +enum msm_vfe_buff_queue_id { + VFE_BUF_QUEUE_DEFAULT, + VFE_BUF_QUEUE_SHARED, + VFE_BUF_QUEUE_MAX, +}; + +struct msm_vfe_axi_stream_cfg_update_info { + uint32_t stream_handle; + uint32_t output_format; + uint32_t user_stream_id; + uint32_t frame_id; + enum msm_vfe_frame_skip_pattern skip_pattern; + struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; + struct msm_isp_sw_framskip sw_skip_info; +}; + +struct msm_vfe_axi_stream_cfg_update_info_req_frm { + uint32_t stream_handle; + uint32_t user_stream_id; + uint32_t frame_id; + uint32_t buf_index; +}; + +struct msm_vfe_axi_halt_cmd { + uint32_t stop_camif; + uint32_t overflow_detected; + uint32_t blocking_halt; +}; + +struct msm_vfe_axi_reset_cmd { + uint32_t blocking; + uint32_t frame_id; +}; + +struct msm_vfe_axi_restart_cmd { + uint32_t enable_camif; +}; + +struct msm_vfe_axi_stream_update_cmd { + uint32_t num_streams; + enum msm_vfe_axi_stream_update_type update_type; + /* + * For backward compatibility, ensure 1st member of any struct + * in union below is uint32_t stream_handle. + */ + union { + struct msm_vfe_axi_stream_cfg_update_info + update_info[MSM_ISP_STATS_MAX]; + struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2; + }; +}; + +struct msm_vfe_smmu_attach_cmd { + uint32_t security_mode; + uint32_t iommu_attach_mode; +}; + +struct msm_vfe_stats_stream_request_cmd { + uint32_t session_id; + uint32_t stream_id; + enum msm_isp_stats_type stats_type; + uint32_t composite_flag; + uint32_t framedrop_pattern; + uint32_t init_frame_drop; /*MAX 31 Frames*/ + uint32_t irq_subsample_pattern; + uint32_t buffer_offset; + uint32_t stream_handle; +}; + +struct msm_vfe_stats_stream_release_cmd { + uint32_t stream_handle; +}; +struct msm_vfe_stats_stream_cfg_cmd { + uint8_t num_streams; + uint32_t stream_handle[MSM_ISP_STATS_MAX]; + uint8_t enable; + uint32_t stats_burst_len; +}; + +enum msm_vfe_reg_cfg_type { + VFE_WRITE, + VFE_WRITE_MB, + VFE_READ, + VFE_CFG_MASK, + VFE_WRITE_DMI_16BIT, + VFE_WRITE_DMI_32BIT, + VFE_WRITE_DMI_64BIT, + VFE_READ_DMI_16BIT, + VFE_READ_DMI_32BIT, + VFE_READ_DMI_64BIT, + GET_MAX_CLK_RATE, + GET_CLK_RATES, + GET_ISP_ID, + VFE_HW_UPDATE_LOCK, + VFE_HW_UPDATE_UNLOCK, + SET_WM_UB_SIZE, + SET_UB_POLICY, +}; + +struct msm_vfe_cfg_cmd2 { + uint16_t num_cfg; + uint16_t cmd_len; + void __user *cfg_data; + void __user *cfg_cmd; +}; + +struct msm_vfe_cfg_cmd_list { + struct msm_vfe_cfg_cmd2 cfg_cmd; + struct msm_vfe_cfg_cmd_list *next; + uint32_t next_size; +}; + +struct msm_vfe_reg_rw_info { + uint32_t reg_offset; + uint32_t cmd_data_offset; + uint32_t len; +}; + +struct msm_vfe_reg_mask_info { + uint32_t reg_offset; + uint32_t mask; + uint32_t val; +}; + +struct msm_vfe_reg_dmi_info { + uint32_t hi_tbl_offset; /*Optional*/ + uint32_t lo_tbl_offset; /*Required*/ + uint32_t len; +}; + +struct msm_vfe_reg_cfg_cmd { + union { + struct msm_vfe_reg_rw_info rw_info; + struct msm_vfe_reg_mask_info mask_info; + struct msm_vfe_reg_dmi_info dmi_info; + } u; + + enum msm_vfe_reg_cfg_type cmd_type; +}; + +enum vfe_sd_type { + VFE_SD_0 = 0, + VFE_SD_1, + VFE_SD_COMMON, + VFE_SD_MAX, +}; + +/* When you change the value below, check for the sof event_data size. + * V4l2 limits payload to 64 bytes + */ +#define MS_NUM_SLAVE_MAX 1 + +/* Usecases when 2 HW need to be related or synced */ +enum msm_vfe_dual_hw_type { + DUAL_NONE = 0, + DUAL_HW_VFE_SPLIT = 1, + DUAL_HW_MASTER_SLAVE = 2, +}; + +/* Type for 2 INTF when used in Master-Slave mode */ +enum msm_vfe_dual_hw_ms_type { + MS_TYPE_NONE, + MS_TYPE_MASTER, + MS_TYPE_SLAVE, +}; + +struct msm_isp_set_dual_hw_ms_cmd { + uint8_t num_src; + /* Each session can be only one type but multiple intf if YUV cam */ + enum msm_vfe_dual_hw_ms_type dual_hw_ms_type; + /* Primary intf is mostly associated with preview. + * This primary intf SOF frame_id and timestamp is tracked + * and used to calculate delta + */ + enum msm_vfe_input_src primary_intf; + /* input_src array indicates other input INTF that may be Master/Slave. + * For these additional intf, frame_id and timestamp are not saved. + * However, if these are slaves then they will still get their + * frame_id from Master + */ + enum msm_vfe_input_src input_src[VFE_SRC_MAX]; + uint32_t sof_delta_threshold; /* In milliseconds. Sent for Master */ +}; + +enum msm_isp_buf_type { + ISP_PRIVATE_BUF, + ISP_SHARE_BUF, + MAX_ISP_BUF_TYPE, +}; + +struct msm_isp_unmap_buf_req { + uint32_t fd; +}; + +struct msm_isp_buf_request { + uint32_t vfe_id; + enum msm_vfe_axi_stream_src output_id; + uint32_t flags; + uint8_t num_buf; + uint32_t handle; + enum msm_isp_buf_type buf_type; +}; + +struct msm_isp_qbuf_plane { + uint32_t addr; + uint32_t offset; + uint32_t length; +}; + +struct msm_isp_qbuf_buffer { + struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; + uint32_t num_planes; +}; + +struct msm_isp_qbuf_info { + uint32_t handle; + int32_t buf_idx; + /*Only used for prepare buffer*/ + struct msm_isp_qbuf_buffer buffer; + /*Only used for diverted buffer*/ + uint32_t dirty_buf; +}; + +struct msm_isp_clk_rates { + uint32_t svs_rate; + uint32_t nominal_rate; + uint32_t high_rate; +}; + +struct msm_vfe_axi_src_state { + enum msm_vfe_input_src input_src; + uint32_t src_active; + uint32_t src_frame_id; +}; + +enum msm_vfe_cmd_ext_type_t { + VFE_GET_BUFQ_STATE, +}; + +enum msm_isp_buffer_state { + MSM_ISP_BUFFER_STATE_UNUSED, /* not used */ + MSM_ISP_BUFFER_STATE_INITIALIZED, /* REQBUF done */ + MSM_ISP_BUFFER_STATE_PREPARED, /* BUF mapped */ + MSM_ISP_BUFFER_STATE_QUEUED, /* buf queued */ + MSM_ISP_BUFFER_STATE_DEQUEUED, /* in use in VFE */ + MSM_ISP_BUFFER_STATE_DIVERTED, /* Sent to other hardware*/ + MSM_ISP_BUFFER_STATE_DISPATCHED, /* Sent to HAL*/ +}; + +struct msm_vfe_bufq_state { + uint32_t handle; + uint32_t nbufs; + int32_t __user *buf_state; +}; + +struct msm_vfe_cmd_ext { + enum msm_vfe_cmd_ext_type_t type; + union { + struct msm_vfe_bufq_state bufq_state; + } data; +}; + +enum msm_isp_event_mask_index { + ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0, + ISP_EVENT_MASK_INDEX_ERROR = 1, + ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2, + ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3, + ISP_EVENT_MASK_INDEX_REG_UPDATE = 4, + ISP_EVENT_MASK_INDEX_SOF = 5, + ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6, + ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7, + ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8, + ISP_EVENT_MASK_INDEX_BUF_DONE = 9, + ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10, + ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11, + ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12, +}; + + +#define ISP_EVENT_SUBS_MASK_NONE 0 + +#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \ + (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY) + +#define ISP_EVENT_SUBS_MASK_ERROR \ + (1 << ISP_EVENT_MASK_INDEX_ERROR) + +#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \ + (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT) + +#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \ + (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE) + +#define ISP_EVENT_SUBS_MASK_REG_UPDATE \ + (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE) + +#define ISP_EVENT_SUBS_MASK_SOF \ + (1 << ISP_EVENT_MASK_INDEX_SOF) + +#define ISP_EVENT_SUBS_MASK_BUF_DIVERT \ + (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT) + +#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \ + (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY) + +#define ISP_EVENT_SUBS_MASK_FE_READ_DONE \ + (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE) + +#define ISP_EVENT_SUBS_MASK_BUF_DONE \ + (1 << ISP_EVENT_MASK_INDEX_BUF_DONE) + +#define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING \ + (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING) + +#define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH \ + (1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH) + +#define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR \ + (1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR) + +enum msm_isp_event_idx { + ISP_REG_UPDATE = 0, + ISP_EPOCH_0 = 1, + ISP_EPOCH_1 = 2, + ISP_START_ACK = 3, + ISP_STOP_ACK = 4, + ISP_IRQ_VIOLATION = 5, + ISP_STATS_OVERFLOW = 6, + ISP_BUF_DONE = 7, + ISP_FE_RD_DONE = 8, + ISP_IOMMU_P_FAULT = 9, + ISP_ERROR = 10, + ISP_HW_FATAL_ERROR = 11, + ISP_PING_PONG_MISMATCH = 12, + ISP_REG_UPDATE_MISSING = 13, + ISP_BUF_FATAL_ERROR = 14, + ISP_EVENT_MAX = 15 +}; + +#define ISP_EVENT_OFFSET 8 +#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) +#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) +#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) +#define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) +#define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) +#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) +#define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0) +#define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1) +#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) +#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) +#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) +#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) +#define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR) +#define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE) +#define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1) +#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) +#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) +#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) +#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) +#define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE) +#define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT) +#define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR) +#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH) +#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING) +#define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR) +#define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE) + +/* The msm_v4l2_event_data structure should match the + * v4l2_event.u.data field. + * should not exceed 64 bytes + */ + +struct msm_isp_buf_event { + uint32_t session_id; + uint32_t stream_id; + uint32_t handle; + uint32_t output_format; + int8_t buf_idx; + uint8_t field_type; +}; +struct msm_isp_fetch_eng_event { + uint32_t session_id; + uint32_t stream_id; + uint32_t handle; + uint32_t fd; + int8_t buf_idx; + int8_t offline_mode; +}; +struct msm_isp_stats_event { + uint32_t stats_mask; /* 4 bytes */ + uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */ +}; + +struct msm_isp_stream_ack { + uint32_t session_id; + uint32_t stream_id; + uint32_t handle; +}; + +enum msm_vfe_error_type { + ISP_ERROR_NONE, + ISP_ERROR_CAMIF, + ISP_ERROR_BUS_OVERFLOW, + ISP_ERROR_RETURN_EMPTY_BUFFER, + ISP_ERROR_FRAME_ID_MISMATCH, + ISP_ERROR_MAX, +}; + +struct msm_isp_error_info { + enum msm_vfe_error_type err_type; + uint32_t session_id; + uint32_t stream_id; + uint32_t stream_id_mask; +}; + +/* This structure reports delta between master and slave */ +struct msm_isp_ms_delta_info { + uint8_t num_delta_info; + uint32_t delta[MS_NUM_SLAVE_MAX]; +}; + +/* This is sent in EPOCH irq */ +struct msm_isp_output_info { + uint8_t regs_not_updated; + /* mask with bufq_handle for regs not updated or return empty */ + uint16_t output_err_mask; + /* mask with stream_idx for get_buf failed */ + uint8_t stream_framedrop_mask; + /* mask with stats stream_idx for get_buf failed */ + uint16_t stats_framedrop_mask; + /* delta between master and slave */ +}; + +/* This structure is piggybacked with SOF event */ +struct msm_isp_sof_info { + uint8_t regs_not_updated; + /* mask with bufq_handle for regs not updated */ + uint16_t reg_update_fail_mask; + /* mask with bufq_handle for get_buf failed */ + uint32_t stream_get_buf_fail_mask; + /* mask with stats stream_idx for get_buf failed */ + uint16_t stats_get_buf_fail_mask; + /* delta between master and slave */ + struct msm_isp_ms_delta_info ms_delta_info; + /* + * mask with AXI_SRC in paused state. In PAUSED + * state there is no Buffer output. So this mask is used + * to report drop. + */ + uint16_t axi_updating_mask; + /* extended mask with bufq_handle for regs not updated */ + uint32_t reg_update_fail_mask_ext; +}; +#define AXI_UPDATING_MASK 1 +#define REG_UPDATE_FAIL_MASK_EXT 1 + +struct msm_isp_event_data { + /*Wall clock except for buffer divert events + *which use monotonic clock + */ + struct timeval timestamp; + /* Monotonic timestamp since bootup */ + struct timeval mono_timestamp; + uint32_t frame_id; + union { + /* Sent for Stats_Done event */ + struct msm_isp_stats_event stats; + /* Sent for Buf_Divert event */ + struct msm_isp_buf_event buf_done; + /* Sent for offline fetch done event */ + struct msm_isp_fetch_eng_event fetch_done; + /* Sent for Error_Event */ + struct msm_isp_error_info error_info; + /* + * This struct needs to be removed once + * userspace switches to sof_info + */ + struct msm_isp_output_info output_info; + /* Sent for SOF event */ + struct msm_isp_sof_info sof_info; + } u; /* union can have max 52 bytes */ +}; + +enum msm_vfe_ahb_clk_vote { + MSM_ISP_CAMERA_AHB_SVS_VOTE = 1, + MSM_ISP_CAMERA_AHB_TURBO_VOTE = 2, + MSM_ISP_CAMERA_AHB_NOMINAL_VOTE = 3, + MSM_ISP_CAMERA_AHB_SUSPEND_VOTE = 4, +}; + +struct msm_isp_ahb_clk_cfg { + uint32_t vote; + uint32_t reserved[2]; +}; + +#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') +#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') +#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') +#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') +#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') +#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') +#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') +#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') +#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') +#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') +#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') +#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') +#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4') +#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4') +#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4') +#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4') +#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0') +#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0') +#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0') +#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0') +#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') +#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') +#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') +#define V4L2_PIX_FMT_META10 v4l2_fourcc('Q', 'M', '1', '0') +#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/ +#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/ +#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/ +#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/ + + +enum msm_vfe_pixel_data_size { + VFE_PIXEL_DATA_SIZE_8BIT, + VFE_PIXEL_DATA_SIZE_10BIT, + VFE_PIXEL_DATA_SIZE_12BIT, + VFE_PIXEL_DATA_SIZE_14BIT, +}; + +struct msm_vfe_operation_cfg { + enum msm_vfe_camif_input camif_input; + enum msm_vfe_pixel_data_size dataSize; + enum msm_vfe_inputmux input_mux; + enum ISP_START_PIXEL_PATTERN pixel_pattern; + enum msm_vfe_hvx_streaming_cmd hvx_cmd; + uint8_t yuv_cosited; +}; + +struct msm_vfe_axi_output_plane_cfg { + uint8_t wmIndex; + enum msm_vfe_plane_fmt plane_fmt; + uint32_t image_qwords_per_line; + uint32_t image_height; + uint32_t output_stride; + uint32_t output_scan_lines; + uint32_t output_plane_format; + uint32_t frame_increment; +}; + +struct msm_vfe_axi_framedrop_update { + enum msm_vfe_axi_stream_src stream_src; + + uint8_t framedrop_period; + uint32_t framedrop_pattern; +}; + +struct msm_vfe_axi_output_path_cfg { + uint8_t enable; + + uint32_t format; + uint8_t raw_data_size; + uint32_t burst_count; + struct msm_vfe_axi_output_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; + + uint8_t frame_based; + uint32_t frame_group; + uint32_t frame_interval; + + uint8_t framedrop_period; + uint32_t framedrop_pattern; + + uint8_t rdi_cid; + uint8_t rdi_frameskip_en; + uint32_t rdi_frameskip_pattern; +}; + +struct msm_vfe_axi_output_cfg { + struct msm_vfe_axi_output_path_cfg output_path_cfg[VFE_AXI_SRC_MAX]; +}; + + +enum msm_isp_ioctl_cmd_code { + MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE, + + MSM_ISP_REQUEST_BUFQ, + MSM_ISP_RELEASE_BUFQ, + MSM_ISP_ENQUEUE_BUF, + MSM_ISP_DEQUEUE_BUF, + + MSM_ISP_REQUEST_STREAM, + MSM_ISP_CFG_STREAM, + MSM_ISP_RELEASE_STREAM, + MSM_ISP_INPUT_CFG, + MSM_ISP_SET_SRC_STATE, + MSM_ISP_REQUEST_STATS_STREAM, + MSM_ISP_CFG_STATS_STREAM, + MSM_ISP_RELEASE_STATS_STREAM, + MSM_ISP_REG_UPDATE_CMD, + MSM_ISP_UPDATE_STREAM, + MSM_VFE_REG_LIST_CFG, + + MSM_ISP_UPDATE_STATS_STREAM, + MSM_ISP_AXI_HALT, + MSM_ISP_AXI_RESET, + MSM_ISP_AXI_RESTART, + MSM_ISP_FETCH_ENG_START, + MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, + MSM_ISP_MAP_BUF_START_FE, + MSM_ISP_FETCH_ENG_MULTI_PASS_START, + MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, + MSM_ISP_CFG_HW_STATE, + + MSM_ISP_SMMU_ATTACH, + MSM_ISP_UNMAP_BUF, + + MSM_ISP_OPERATION_CFG, + MSM_ISP_CAMIF_CFG, + MSM_ISP_AXI_OUTPUT_CFG, + MSM_ISP_START, + MSM_ISP_STOP, + + MSM_ISP_SET_CLK_STATUS, + MSM_ISP_CMD_EXT, + MSM_ISP_FRAMEDROP_UPDATE, +}; + + +#define VIDIOC_MSM_VFE_REG_CFG \ + _IOWR('V', MSM_VFE_REG_CFG, \ + struct msm_vfe_cfg_cmd2) + +#define VIDIOC_MSM_ISP_REQUEST_BUFQ \ + _IOWR('V', MSM_ISP_REQUEST_BUFQ, \ + struct msm_isp_buf_request) + +#define VIDIOC_MSM_ISP_RELEASE_BUFQ \ + _IOWR('V', MSM_ISP_RELEASE_BUFQ, \ + struct msm_isp_buf_request) + +#define VIDIOC_MSM_ISP_ENQUEUE_BUF \ + _IOWR('V', MSM_ISP_ENQUEUE_BUF, \ + struct msm_isp_qbuf_info) + +#define VIDIOC_MSM_ISP_DEQUEUE_BUF \ + _IOWR('V', MSM_ISP_DEQUEUE_BUF, \ + struct msm_isp_qbuf_info) + +#define VIDIOC_MSM_ISP_REQUEST_STREAM \ + _IOWR('V', MSM_ISP_REQUEST_STREAM, \ + struct msm_vfe_axi_stream_request_cmd) + +#define VIDIOC_MSM_ISP_CFG_STREAM \ + _IOWR('V', MSM_ISP_CFG_STREAM, \ + struct msm_vfe_axi_stream_cfg_cmd) + +#define VIDIOC_MSM_ISP_RELEASE_STREAM \ + _IOWR('V', MSM_ISP_RELEASE_STREAM, \ + struct msm_vfe_axi_stream_release_cmd) + +#define VIDIOC_MSM_ISP_INPUT_CFG \ + _IOWR('V', MSM_ISP_INPUT_CFG, \ + struct msm_vfe_input_cfg) + +#define VIDIOC_MSM_ISP_SET_SRC_STATE \ + _IOWR('V', MSM_ISP_SET_SRC_STATE, \ + struct msm_vfe_axi_src_state) + +#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \ + _IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, \ + struct msm_vfe_stats_stream_request_cmd) + +#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \ + _IOWR('V', MSM_ISP_CFG_STATS_STREAM, \ + struct msm_vfe_stats_stream_cfg_cmd) + +#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \ + _IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, \ + struct msm_vfe_stats_stream_release_cmd) + +#define VIDIOC_MSM_ISP_REG_UPDATE_CMD \ + _IOWR('V', MSM_ISP_REG_UPDATE_CMD, \ + enum msm_vfe_input_src) + +#define VIDIOC_MSM_ISP_UPDATE_STREAM \ + _IOWR('V', MSM_ISP_UPDATE_STREAM, \ + struct msm_vfe_axi_stream_update_cmd) + +#define VIDIOC_MSM_VFE_REG_LIST_CFG \ + _IOWR('V', MSM_VFE_REG_LIST_CFG, \ + struct msm_vfe_cfg_cmd_list) + +#define VIDIOC_MSM_ISP_SMMU_ATTACH \ + _IOWR('V', MSM_ISP_SMMU_ATTACH, \ + struct msm_vfe_smmu_attach_cmd) + +#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \ + _IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, \ + struct msm_vfe_axi_stream_update_cmd) + +#define VIDIOC_MSM_ISP_AXI_HALT \ + _IOWR('V', MSM_ISP_AXI_HALT, \ + struct msm_vfe_axi_halt_cmd) + +#define VIDIOC_MSM_ISP_AXI_RESET \ + _IOWR('V', MSM_ISP_AXI_RESET, \ + struct msm_vfe_axi_reset_cmd) + +#define VIDIOC_MSM_ISP_AXI_RESTART \ + _IOWR('V', MSM_ISP_AXI_RESTART, \ + struct msm_vfe_axi_restart_cmd) + +#define VIDIOC_MSM_ISP_FETCH_ENG_START \ + _IOWR('V', MSM_ISP_FETCH_ENG_START, \ + struct msm_vfe_fetch_eng_start) + +#define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE \ + _IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, \ + struct msm_isp_set_dual_hw_ms_cmd) + +#define VIDIOC_MSM_ISP_MAP_BUF_START_FE \ + _IOWR('V', MSM_ISP_MAP_BUF_START_FE, \ + struct msm_vfe_fetch_eng_start) + +#define VIDIOC_MSM_ISP_UNMAP_BUF \ + _IOWR('V', MSM_ISP_UNMAP_BUF, \ + struct msm_isp_unmap_buf_req) + +#define VIDIOC_MSM_ISP_AHB_CLK_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE+25, struct msm_isp_ahb_clk_cfg) + +#define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START \ + _IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, \ + struct msm_vfe_fetch_eng_multi_pass_start) + +#define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE \ + _IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, \ + struct msm_vfe_fetch_eng_multi_pass_start) + +#define VIDIOC_MSM_ISP_CFG_HW_STATE \ + _IOWR('V', MSM_ISP_CFG_HW_STATE, \ + struct msm_vfe_axi_stream_cfg_cmd) + + +#define VIDIOC_MSM_ISP_OPERATION_CFG \ + _IOWR('V', MSM_ISP_OPERATION_CFG, \ + struct msm_vfe_operation_cfg) + +#define VIDIOC_MSM_ISP_AXI_OUTPUT_CFG \ + _IOWR('V', MSM_ISP_AXI_OUTPUT_CFG, \ + struct msm_vfe_axi_output_cfg) + +#define VIDIOC_MSM_ISP_FRAMEDROP_UPDATE \ + _IOWR('V', MSM_ISP_FRAMEDROP_UPDATE, \ + struct msm_vfe_axi_output_cfg) + +#define VIDIOC_MSM_ISP_CAMIF_CFG \ + _IOWR('V', MSM_ISP_CAMIF_CFG, \ + struct msm_vfe_camif_cfg) + +#define VIDIOC_MSM_ISP_SET_CLK_STATUS \ + _IOWR('V', MSM_ISP_SET_CLK_STATUS, \ + unsigned int) + +#define VIDIOC_MSM_ISP_CMD_EXT \ + _IOWR('V', MSM_ISP_CMD_EXT, \ + struct msm_vfe_cmd_ext) + +#endif /* __UAPI_MSM_AIS_ISP__ */ diff --git a/include/uapi/media/ais/msm_ais_ispif.h b/include/uapi/media/ais/msm_ais_ispif.h new file mode 100644 index 000000000000..a184e2983ab6 --- /dev/null +++ b/include/uapi/media/ais/msm_ais_ispif.h @@ -0,0 +1,179 @@ +#ifndef UAPI_MSM_AIS_ISPIF_H +#define UAPI_MSM_AIS_ISPIF_H + +#include <linux/types.h> +#include <linux/ioctl.h> +#include <linux/videodev2.h> +#include <media/ais/msm_ais_mgr.h> + +#define CSID_VERSION_V20 0x02000011 +#define CSID_VERSION_V22 0x02001000 +#define CSID_VERSION_V30 0x30000000 +#define CSID_VERSION_V3 0x30000000 +#define CSID_VERSION_V35 0x30050000 + +enum msm_ispif_vfe_intf { + VFE0, + VFE1, + VFE_MAX +}; +#define VFE0_MASK (1 << VFE0) +#define VFE1_MASK (1 << VFE1) + +enum msm_ispif_intftype { + PIX0, + RDI0, + PIX1, + RDI1, + RDI2, + INTF_MAX +}; +#define MAX_PARAM_ENTRIES (INTF_MAX * 2) +#define MAX_CID_CH 8 +#define MAX_CID_CH_v2 4 + +#define PIX0_MASK (1 << PIX0) +#define PIX1_MASK (1 << PIX1) +#define RDI0_MASK (1 << RDI0) +#define RDI1_MASK (1 << RDI1) +#define RDI2_MASK (1 << RDI2) + + +enum msm_ispif_vc { + VC0, + VC1, + VC2, + VC3, + VC_MAX +}; + +enum msm_ispif_cid { + CID0, + CID1, + CID2, + CID3, + CID4, + CID5, + CID6, + CID7, + CID8, + CID9, + CID10, + CID11, + CID12, + CID13, + CID14, + CID15, + CID_MAX +}; + +enum msm_ispif_csid { + CSID0, + CSID1, + CSID2, + CSID3, + CSID_MAX +}; + +enum msm_ispif_pixel_odd_even { + PIX_EVEN, + PIX_ODD +}; + +enum msm_ispif_pixel_pack_mode { + PACK_BYTE, + PACK_PLAIN_PACK, + PACK_NV_P8, + PACK_NV_P16 +}; + +struct msm_ispif_pack_cfg { + int pixel_swap_en; + enum msm_ispif_pixel_odd_even even_odd_sel; + enum msm_ispif_pixel_pack_mode pack_mode; +}; + +struct msm_ispif_params_entry { + enum msm_ispif_vfe_intf vfe_intf; + enum msm_ispif_intftype intftype; + enum msm_ispif_csid csid; + int num_cids; + enum msm_ispif_cid cids[MAX_CID_CH_v2]; + uint8_t crop_enable; + uint16_t crop_start_pixel; + uint16_t crop_end_pixel; + uint8_t rdi_frameskip_enable; + uint32_t rdi_framedrop_period; + uint32_t rdi_framedrop_pattern; +}; + +struct msm_ispif_param_data_ext { + uint32_t num; + struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES]; + struct msm_ispif_pack_cfg pack_cfg[CID_MAX]; +}; + +struct msm_ispif_param_data { + uint32_t num; + struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES]; +}; + +struct msm_isp_info { + uint32_t max_resolution; + uint32_t id; + uint32_t ver; +}; + +struct msm_ispif_vfe_info { + int num_vfe; + struct msm_isp_info info[VFE_MAX]; +}; + +enum ispif_cfg_type_t { + ISPIF_CLK_ENABLE, + ISPIF_CLK_DISABLE, + ISPIF_INIT, + ISPIF_RELEASE, + ISPIF_RESET, + ISPIF_CFG, + ISPIF_START_FRAME_BOUNDARY, + ISPIF_RESTART_FRAME_BOUNDARY, + ISPIF_STOP_FRAME_BOUNDARY, + ISPIF_STOP, + ISPIF_ENABLE_REG_DUMP, + ISPIF_SET_VFE_INFO, + ISPIF_CFG2, + ISPIF_READ_REG_LIST_CMD, + ISPIF_WRITE_REG_LIST_CMD, +}; + + + +struct ispif_cfg_data_ext { + enum ispif_cfg_type_t cfg_type; + void __user *data; + uint32_t size; +}; + +struct ispif_cfg_data { + enum ispif_cfg_type_t cfg_type; + union { + int reg_dump; /* ISPIF_ENABLE_REG_DUMP */ + uint32_t csid_version; /* ISPIF_INIT */ + struct msm_ispif_vfe_info vfe_info; /* ISPIF_SET_VFE_INFO */ + struct msm_ispif_param_data params; /* CFG, START, STOP */ + struct msm_camera_reg_list_cmd *reg_list; + }; +}; + +#define ISPIF_RDI_PACK_MODE_SUPPORT 1 +#define ISPIF_RW_REG_LIST_SUPPORT + +#define VIDIOC_MSM_ISPIF_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data) + +#define VIDIOC_MSM_ISPIF_CFG_EXT \ + _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct ispif_cfg_data_ext) + +#endif + diff --git a/include/uapi/media/ais/msm_ais_mgr.h b/include/uapi/media/ais/msm_ais_mgr.h new file mode 100644 index 000000000000..bfac1ac8296a --- /dev/null +++ b/include/uapi/media/ais/msm_ais_mgr.h @@ -0,0 +1,99 @@ +#ifndef __UAPI_MEDIA_MSM_AIS_MGR_H__ +#define __UAPI_MEDIA_MSM_AIS_MGR_H__ + +#include <media/ais/msm_ais.h> + +#define VREGNAME_SIZE 32 +#define CLKNAME_SIZE 32 + +enum cam_ahb_clk_vote { + /* need to update the voting requests + * according to dtsi entries. + */ + CAM_AHB_SUSPEND_VOTE = 0x0, + CAM_AHB_SVS_VOTE = 0x01, + CAM_AHB_NOMINAL_VOTE = 0x02, + CAM_AHB_TURBO_VOTE = 0x03, + CAM_AHB_DYNAMIC_VOTE = 0xFF, +}; + +enum clk_mgr_cfg_type_t { + AIS_CLK_ENABLE, + AIS_CLK_DISABLE, + AIS_CLK_ENABLE_ALLCLK, + AIS_CLK_DISABLE_ALLCLK +}; + +enum ais_mgr_cfg_ext_type_t { + AIS_DIAG_GET_REGULATOR_INFO_LIST, + AIS_DIAG_GET_BUS_INFO_STATE, + AIS_DIAG_GET_CLK_INFO_LIST, + AIS_DIAG_GET_GPIO_LIST, + AIS_DIAG_SET_GPIO_LIST, +}; + +#define AIS_CLK_ENABLE AIS_CLK_ENABLE +#define AIS_CLK_DISABLE AIS_CLK_DISABLE + + +struct msm_camera_reg_list_cmd { + void __user *value_list; + void __user *regaddr_list; + uint32_t reg_num; +}; + +struct msm_ais_diag_regulator_info_t { + int enable; + char regulatorname[VREGNAME_SIZE]; +}; + +struct msm_ais_diag_regulator_info_list_t { + struct msm_ais_diag_regulator_info_t *infolist; + uint32_t regulator_num; +}; + +struct msm_ais_diag_bus_info_t { + enum cam_ahb_clk_vote ahb_clk_vote_state; + uint32_t isp_bus_vector_idx; /* 0 - init 1- ping 2 - pong */ + uint64_t isp_ab; + uint64_t isp_ib; +}; + +struct msm_ais_diag_clk_info_t { + char clk_name[CLKNAME_SIZE]; + long clk_rate; + uint8_t enable; +}; + +struct msm_ais_diag_clk_list_t { + void __user *clk_info; + uint32_t clk_num; +}; + +struct msm_ais_diag_gpio_list_t { + uint32_t __user *gpio_idx_list; + int32_t __user *gpio_val_list; + uint32_t gpio_num; +}; + +struct clk_mgr_cfg_data_ext { + enum ais_mgr_cfg_ext_type_t cfg_type; + union { + struct msm_ais_diag_regulator_info_list_t vreg_infolist; + struct msm_ais_diag_bus_info_t bus_info; + struct msm_ais_diag_clk_list_t clk_infolist; + struct msm_ais_diag_gpio_list_t gpio_list; + } data; +}; + +struct clk_mgr_cfg_data { + enum clk_mgr_cfg_type_t cfg_type; +}; + +#define VIDIOC_MSM_AIS_CLK_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct clk_mgr_cfg_data) + +#define VIDIOC_MSM_AIS_CLK_CFG_EXT \ + _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct clk_mgr_cfg_data_ext) + +#endif /* __UAPI_MEDIA_MSM_AIS_MGR_H__ */ diff --git a/include/uapi/media/ais/msm_ais_sensor.h b/include/uapi/media/ais/msm_ais_sensor.h new file mode 100644 index 000000000000..633f3f227174 --- /dev/null +++ b/include/uapi/media/ais/msm_ais_sensor.h @@ -0,0 +1,670 @@ +#ifndef __UAPI_LINUX_MSM_AIS_SENSOR_H +#define __UAPI_LINUX_MSM_AIS_SENSOR_H + +#include <linux/v4l2-mediabus.h> +#include <media/ais/msm_ais_sensor_sdk.h> +#include <media/ais/msm_ais_mgr.h> +#include <linux/types.h> +#include <linux/i2c.h> + +#define I2C_SEQ_REG_SETTING_MAX 5 + +#define MSM_SENSOR_MCLK_8HZ 8000000 +#define MSM_SENSOR_MCLK_16HZ 16000000 +#define MSM_SENSOR_MCLK_24HZ 24000000 + +#define MAX_SENSOR_NAME 32 +#define MAX_ACTUATOR_AF_TOTAL_STEPS 1024 + +#define MAX_OIS_MOD_NAME_SIZE 32 +#define MAX_OIS_NAME_SIZE 32 +#define MAX_OIS_REG_SETTINGS 800 + +#define MOVE_NEAR 0 +#define MOVE_FAR 1 + +#define MSM_ACTUATOR_MOVE_SIGNED_FAR -1 +#define MSM_ACTUATOR_MOVE_SIGNED_NEAR 1 + +#define MAX_ACTUATOR_REGION 5 + +#define MAX_EEPROM_NAME 32 + +#define MAX_AF_ITERATIONS 3 +#define MAX_NUMBER_OF_STEPS 47 +#define MAX_REGULATOR 5 + +#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */ +#define MSM_V4L2_PIX_FMT_META10 v4l2_fourcc('M', 'E', '1', '0') /* META10 */ +#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') + /* 14 BGBG.. GRGR.. */ +#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') + /* 14 GBGB.. RGRG.. */ +#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') + /* 14 GRGR.. BGBG.. */ +#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') + /* 14 RGRG.. GBGB.. */ + +enum flash_type { + LED_FLASH = 1, + STROBE_FLASH, + GPIO_FLASH +}; + +enum msm_sensor_resolution_t { + MSM_SENSOR_RES_FULL, + MSM_SENSOR_RES_QTR, + MSM_SENSOR_RES_2, + MSM_SENSOR_RES_3, + MSM_SENSOR_RES_4, + MSM_SENSOR_RES_5, + MSM_SENSOR_RES_6, + MSM_SENSOR_RES_7, + MSM_SENSOR_INVALID_RES, +}; + +enum msm_camera_stream_type_t { + MSM_CAMERA_STREAM_PREVIEW, + MSM_CAMERA_STREAM_SNAPSHOT, + MSM_CAMERA_STREAM_VIDEO, + MSM_CAMERA_STREAM_INVALID, +}; + +enum sensor_sub_module_t { + SUB_MODULE_SENSOR, + SUB_MODULE_CHROMATIX, + SUB_MODULE_ACTUATOR, + SUB_MODULE_EEPROM, + SUB_MODULE_LED_FLASH, + SUB_MODULE_STROBE_FLASH, + SUB_MODULE_CSID, + SUB_MODULE_CSID_3D, + SUB_MODULE_CSIPHY, + SUB_MODULE_CSIPHY_3D, + SUB_MODULE_OIS, + SUB_MODULE_EXT, + SUB_MODULE_IR_LED, + SUB_MODULE_IR_CUT, + SUB_MODULE_MAX, +}; + +enum { + MSM_CAMERA_EFFECT_MODE_OFF, + MSM_CAMERA_EFFECT_MODE_MONO, + MSM_CAMERA_EFFECT_MODE_NEGATIVE, + MSM_CAMERA_EFFECT_MODE_SOLARIZE, + MSM_CAMERA_EFFECT_MODE_SEPIA, + MSM_CAMERA_EFFECT_MODE_POSTERIZE, + MSM_CAMERA_EFFECT_MODE_WHITEBOARD, + MSM_CAMERA_EFFECT_MODE_BLACKBOARD, + MSM_CAMERA_EFFECT_MODE_AQUA, + MSM_CAMERA_EFFECT_MODE_EMBOSS, + MSM_CAMERA_EFFECT_MODE_SKETCH, + MSM_CAMERA_EFFECT_MODE_NEON, + MSM_CAMERA_EFFECT_MODE_MAX +}; + +enum { + MSM_CAMERA_WB_MODE_AUTO, + MSM_CAMERA_WB_MODE_CUSTOM, + MSM_CAMERA_WB_MODE_INCANDESCENT, + MSM_CAMERA_WB_MODE_FLUORESCENT, + MSM_CAMERA_WB_MODE_WARM_FLUORESCENT, + MSM_CAMERA_WB_MODE_DAYLIGHT, + MSM_CAMERA_WB_MODE_CLOUDY_DAYLIGHT, + MSM_CAMERA_WB_MODE_TWILIGHT, + MSM_CAMERA_WB_MODE_SHADE, + MSM_CAMERA_WB_MODE_OFF, + MSM_CAMERA_WB_MODE_MAX +}; + +enum { + MSM_CAMERA_SCENE_MODE_OFF, + MSM_CAMERA_SCENE_MODE_AUTO, + MSM_CAMERA_SCENE_MODE_LANDSCAPE, + MSM_CAMERA_SCENE_MODE_SNOW, + MSM_CAMERA_SCENE_MODE_BEACH, + MSM_CAMERA_SCENE_MODE_SUNSET, + MSM_CAMERA_SCENE_MODE_NIGHT, + MSM_CAMERA_SCENE_MODE_PORTRAIT, + MSM_CAMERA_SCENE_MODE_BACKLIGHT, + MSM_CAMERA_SCENE_MODE_SPORTS, + MSM_CAMERA_SCENE_MODE_ANTISHAKE, + MSM_CAMERA_SCENE_MODE_FLOWERS, + MSM_CAMERA_SCENE_MODE_CANDLELIGHT, + MSM_CAMERA_SCENE_MODE_FIREWORKS, + MSM_CAMERA_SCENE_MODE_PARTY, + MSM_CAMERA_SCENE_MODE_NIGHT_PORTRAIT, + MSM_CAMERA_SCENE_MODE_THEATRE, + MSM_CAMERA_SCENE_MODE_ACTION, + MSM_CAMERA_SCENE_MODE_AR, + MSM_CAMERA_SCENE_MODE_FACE_PRIORITY, + MSM_CAMERA_SCENE_MODE_BARCODE, + MSM_CAMERA_SCENE_MODE_HDR, + MSM_CAMERA_SCENE_MODE_MAX +}; + +enum csid_cfg_type_t { + CSID_INIT, + CSID_CFG, + CSID_UPDATE_CFG, + CSID_TESTMODE_CFG, + CSID_START, + CSID_STOP, + CSID_RELEASE, + CSID_READ_REG_LIST_CMD, + CSID_WRITE_REG_LIST_CMD, +}; + +enum csiphy_cfg_type_t { + CSIPHY_INIT, + CSIPHY_CFG, + CSIPHY_START, + CSIPHY_STOP, + CSIPHY_RELEASE, + CSIPHY_READ_REG_LIST_CMD, + CSIPHY_WRITE_REG_LIST_CMD, +}; + +enum camera_vreg_type { + VREG_TYPE_DEFAULT, + VREG_TYPE_CUSTOM, +}; + +enum sensor_af_t { + SENSOR_AF_FOCUSSED, + SENSOR_AF_NOT_FOCUSSED, +}; + +enum cci_i2c_master_t { + MASTER_0, + MASTER_1, + MASTER_MAX, +}; + +struct msm_sensor_event_data { + uint16_t sensor_slave_addr; +}; + +enum msm_sensor_event_mask_index { + SENSOR_EVENT_MASK_INDEX_SIGNAL_STATUS = 2, +}; + +#define SENSOR_EVENT_SUBS_MASK_NONE 0 + +#define SENSOR_EVENT_SUBS_MASK_SIGNAL_STATUS \ + (1 << SENSOR_EVENT_MASK_INDEX_SIGNAL_STATUS) + +enum msm_sensor_event_idx { + SENSOR_SIGNAL_STATUS = 2, + SENSOR_EVENT_MAX = 15 +}; + +#define SENSOR_EVENT_BASE (V4L2_EVENT_PRIVATE_START) +#define SENSOR_EVENT_SIGNAL_STATUS (SENSOR_EVENT_BASE + SENSOR_SIGNAL_STATUS) + +struct msm_csid_event_data { + uint8_t csid_id; + uint32_t error_status; +}; + +enum msm_csid_event_mask_index { + CSID_EVENT_MASK_INDEX_SIGNAL_ERROR = 2, +}; + +#define CSID_EVENT_SUBS_MASK_NONE 0 + +#define CSID_EVENT_SUBS_MASK_SIGNAL_ERROR \ + (1 << CSID_EVENT_MASK_INDEX_SIGNAL_ERROR) + +enum msm_csid_event_idx { + CSID_SIGNAL_ERROR = 2, + CSID_EVENT_MAX = 15 +}; + +#define CSID_EVENT_BASE (V4L2_EVENT_PRIVATE_START + SENSOR_EVENT_MAX) +#define CSID_EVENT_SIGNAL_ERROR (CSID_EVENT_BASE + CSID_SIGNAL_ERROR) + +struct msm_camera_i2c_array_write_config { + struct msm_camera_i2c_reg_setting conf_array; + uint16_t slave_addr; +}; + +struct msm_camera_i2c_read_config { + uint16_t slave_addr; + uint16_t reg_addr; + enum msm_camera_i2c_reg_addr_type addr_type; + enum msm_camera_i2c_data_type data_type; + uint16_t data; +}; + +struct msm_camera_csi2_params { + struct msm_camera_csid_params csid_params; + struct msm_camera_csiphy_params csiphy_params; + uint8_t csi_clk_scale_enable; +}; + +struct msm_camera_csi_lane_params { + uint16_t csi_lane_assign; + uint16_t csi_lane_mask; +}; + +struct csi_lane_params_t { + uint16_t csi_lane_assign; + uint8_t csi_lane_mask; + uint8_t csi_if; + int8_t csid_core[2]; + uint8_t csi_phy_sel; +}; + +struct msm_sensor_info_t { + char sensor_name[MAX_SENSOR_NAME]; + uint32_t session_id; + int32_t subdev_id[SUB_MODULE_MAX]; + int32_t subdev_intf[SUB_MODULE_MAX]; + uint8_t is_mount_angle_valid; + uint32_t sensor_mount_angle; + int modes_supported; + enum camb_position_t position; +}; + +struct camera_vreg_t { + const char *reg_name; + int min_voltage; + int max_voltage; + int op_mode; + uint32_t delay; + const char *custom_vreg_name; + enum camera_vreg_type type; +}; + +struct sensorb_cfg_data { + int cfgtype; + union { + struct msm_sensor_info_t sensor_info; + struct msm_sensor_init_params sensor_init_params; + void *setting; + struct msm_sensor_i2c_sync_params sensor_i2c_sync_params; + } cfg; +}; + +struct csid_cfg_data { + enum csid_cfg_type_t cfgtype; + union { + uint32_t csid_version; + struct msm_camera_csid_params *csid_params; + struct msm_camera_csid_testmode_parms *csid_testmode_params; + uint32_t csid_cidmask; + struct msm_camera_reg_list_cmd *csid_reg_list_cmd; + } cfg; +}; + +struct csiphy_cfg_data { + enum csiphy_cfg_type_t cfgtype; + union { + struct msm_camera_csiphy_params *csiphy_params; + struct msm_camera_csi_lane_params *csi_lane_params; + struct msm_camera_reg_list_cmd *csiphy_reg_list_cmd; + } cfg; +}; + +enum eeprom_cfg_type_t { + CFG_EEPROM_GET_INFO, + CFG_EEPROM_GET_CAL_DATA, + CFG_EEPROM_READ_CAL_DATA, + CFG_EEPROM_WRITE_DATA, + CFG_EEPROM_GET_MM_INFO, + CFG_EEPROM_INIT, +}; + +struct eeprom_get_t { + uint32_t num_bytes; +}; + +struct eeprom_read_t { + uint8_t *dbuffer; + uint32_t num_bytes; +}; + +struct eeprom_write_t { + uint8_t *dbuffer; + uint32_t num_bytes; +}; + +struct eeprom_get_cmm_t { + uint32_t cmm_support; + uint32_t cmm_compression; + uint32_t cmm_size; +}; + +struct msm_eeprom_info_t { + struct msm_sensor_power_setting_array *power_setting_array; + enum i2c_freq_mode_t i2c_freq_mode; + struct msm_eeprom_memory_map_array *mem_map_array; +}; + +struct msm_ir_led_cfg_data_t { + enum msm_ir_led_cfg_type_t cfg_type; + int32_t pwm_duty_on_ns; + int32_t pwm_period_ns; +}; + +struct msm_ir_cut_cfg_data_t { + enum msm_ir_cut_cfg_type_t cfg_type; +}; + +struct msm_eeprom_cfg_data { + enum eeprom_cfg_type_t cfgtype; + uint8_t is_supported; + union { + char eeprom_name[MAX_SENSOR_NAME]; + struct eeprom_get_t get_data; + struct eeprom_read_t read_data; + struct eeprom_write_t write_data; + struct eeprom_get_cmm_t get_cmm_data; + struct msm_eeprom_info_t eeprom_info; + } cfg; +}; + +enum msm_sensor_cfg_type_t { + CFG_SET_SLAVE_INFO, + CFG_SLAVE_READ_I2C, + CFG_WRITE_I2C_ARRAY, + CFG_SLAVE_WRITE_I2C_ARRAY, + CFG_WRITE_I2C_SEQ_ARRAY, + CFG_POWER_UP, + CFG_POWER_DOWN, + CFG_SET_STOP_STREAM_SETTING, + CFG_GET_SENSOR_INFO, + CFG_GET_SENSOR_INIT_PARAMS, + CFG_SET_INIT_SETTING, + CFG_SET_RESOLUTION, + CFG_SET_STOP_STREAM, + CFG_SET_START_STREAM, + CFG_SET_SATURATION, + CFG_SET_CONTRAST, + CFG_SET_SHARPNESS, + CFG_SET_ISO, + CFG_SET_EXPOSURE_COMPENSATION, + CFG_SET_ANTIBANDING, + CFG_SET_BESTSHOT_MODE, + CFG_SET_EFFECT, + CFG_SET_WHITE_BALANCE, + CFG_SET_AUTOFOCUS, + CFG_CANCEL_AUTOFOCUS, + CFG_SET_STREAM_TYPE, + CFG_SET_I2C_SYNC_PARAM, + CFG_WRITE_I2C_ARRAY_ASYNC, + CFG_WRITE_I2C_ARRAY_SYNC, + CFG_WRITE_I2C_ARRAY_SYNC_BLOCK, + CFG_CCI_POWER_UP, + CFG_CCI_POWER_DOWN, +}; + +#define CFG_CCI_POWER_UP CFG_CCI_POWER_UP +#define CFG_CCI_POWER_DOWN CFG_CCI_POWER_DOWN + +enum msm_actuator_cfg_type_t { + CFG_GET_ACTUATOR_INFO, + CFG_SET_ACTUATOR_INFO, + CFG_SET_DEFAULT_FOCUS, + CFG_MOVE_FOCUS, + CFG_SET_POSITION, + CFG_ACTUATOR_POWERDOWN, + CFG_ACTUATOR_POWERUP, + CFG_ACTUATOR_INIT, +}; + +struct msm_ois_opcode { + uint32_t prog; + uint32_t coeff; + uint32_t pheripheral; + uint32_t memory; +}; + +enum msm_ois_cfg_type_t { + CFG_OIS_INIT, + CFG_OIS_POWERDOWN, + CFG_OIS_POWERUP, + CFG_OIS_CONTROL, + CFG_OIS_I2C_WRITE_SEQ_TABLE, +}; + +enum msm_ois_cfg_download_type_t { + CFG_OIS_DOWNLOAD, + CFG_OIS_DATA_CONFIG, +}; + +enum msm_ois_i2c_operation { + MSM_OIS_WRITE = 0, + MSM_OIS_POLL, +}; + +struct reg_settings_ois_t { + uint16_t reg_addr; + enum msm_camera_i2c_reg_addr_type addr_type; + uint32_t reg_data; + enum msm_camera_i2c_data_type data_type; + enum msm_ois_i2c_operation i2c_operation; + uint32_t delay; +}; + +struct msm_ois_params_t { + uint16_t data_size; + uint16_t setting_size; + uint32_t i2c_addr; + enum i2c_freq_mode_t i2c_freq_mode; + enum msm_camera_i2c_reg_addr_type i2c_addr_type; + enum msm_camera_i2c_data_type i2c_data_type; + struct reg_settings_ois_t *settings; +}; + +struct msm_ois_set_info_t { + struct msm_ois_params_t ois_params; +}; + +struct msm_actuator_move_params_t { + int8_t dir; + int8_t sign_dir; + int16_t dest_step_pos; + int32_t num_steps; + uint16_t curr_lens_pos; + struct damping_params_t *ringing_params; +}; + +struct msm_actuator_tuning_params_t { + int16_t initial_code; + uint16_t pwd_step; + uint16_t region_size; + uint32_t total_steps; + struct region_params_t *region_params; +}; + +struct park_lens_data_t { + uint32_t damping_step; + uint32_t damping_delay; + uint32_t hw_params; + uint32_t max_step; +}; + +struct msm_actuator_params_t { + enum actuator_type act_type; + uint8_t reg_tbl_size; + uint16_t data_size; + uint16_t init_setting_size; + uint32_t i2c_addr; + enum i2c_freq_mode_t i2c_freq_mode; + enum msm_camera_i2c_reg_addr_type i2c_addr_type; + enum msm_camera_i2c_data_type i2c_data_type; + struct msm_actuator_reg_params_t *reg_tbl_params; + struct reg_settings_t *init_settings; + struct park_lens_data_t park_lens; +}; + +struct msm_actuator_set_info_t { + struct msm_actuator_params_t actuator_params; + struct msm_actuator_tuning_params_t af_tuning_params; +}; + +struct msm_actuator_get_info_t { + uint32_t focal_length_num; + uint32_t focal_length_den; + uint32_t f_number_num; + uint32_t f_number_den; + uint32_t f_pix_num; + uint32_t f_pix_den; + uint32_t total_f_dist_num; + uint32_t total_f_dist_den; + uint32_t hor_view_angle_num; + uint32_t hor_view_angle_den; + uint32_t ver_view_angle_num; + uint32_t ver_view_angle_den; +}; + +enum af_camera_name { + ACTUATOR_MAIN_CAM_0, + ACTUATOR_MAIN_CAM_1, + ACTUATOR_MAIN_CAM_2, + ACTUATOR_MAIN_CAM_3, + ACTUATOR_MAIN_CAM_4, + ACTUATOR_MAIN_CAM_5, + ACTUATOR_WEB_CAM_0, + ACTUATOR_WEB_CAM_1, + ACTUATOR_WEB_CAM_2, +}; + +struct msm_ois_slave_info { + char ois_name[MAX_OIS_NAME_SIZE]; + uint32_t i2c_addr; + struct msm_ois_opcode opcode; +}; +struct msm_ois_cfg_data { + int cfgtype; + union { + struct msm_ois_set_info_t set_info; + struct msm_camera_i2c_seq_reg_setting *settings; + } cfg; +}; + +struct msm_ois_cfg_download_data { + int cfgtype; + struct msm_ois_slave_info slave_info; +}; + +struct msm_actuator_set_position_t { + uint16_t number_of_steps; + uint32_t hw_params; + uint16_t pos[MAX_NUMBER_OF_STEPS]; + uint16_t delay[MAX_NUMBER_OF_STEPS]; +}; + +struct msm_actuator_cfg_data { + int cfgtype; + uint8_t is_af_supported; + union { + struct msm_actuator_move_params_t move; + struct msm_actuator_set_info_t set_info; + struct msm_actuator_get_info_t get_info; + struct msm_actuator_set_position_t setpos; + enum af_camera_name cam_name; + } cfg; +}; + +enum msm_camera_led_config_t { + MSM_CAMERA_LED_OFF, + MSM_CAMERA_LED_LOW, + MSM_CAMERA_LED_HIGH, + MSM_CAMERA_LED_INIT, + MSM_CAMERA_LED_RELEASE, +}; + +struct msm_camera_led_cfg_t { + enum msm_camera_led_config_t cfgtype; + int32_t torch_current[MAX_LED_TRIGGERS]; + int32_t flash_current[MAX_LED_TRIGGERS]; + int32_t flash_duration[MAX_LED_TRIGGERS]; +}; + +struct msm_flash_init_info_t { + enum msm_flash_driver_type flash_driver_type; + uint32_t slave_addr; + enum i2c_freq_mode_t i2c_freq_mode; + struct msm_sensor_power_setting_array *power_setting_array; + struct msm_camera_i2c_reg_setting_array *settings; +}; + +struct msm_flash_cfg_data_t { + enum msm_flash_cfg_type_t cfg_type; + int32_t flash_current[MAX_LED_TRIGGERS]; + int32_t flash_duration[MAX_LED_TRIGGERS]; + union { + struct msm_flash_init_info_t *flash_init_info; + struct msm_camera_i2c_reg_setting_array *settings; + } cfg; +}; + +/* sensor init structures and enums */ +enum msm_sensor_init_cfg_type_t { + CFG_SINIT_PROBE, + CFG_SINIT_PROBE_DONE, + CFG_SINIT_PROBE_WAIT_DONE, +}; + +struct sensor_init_cfg_data { + enum msm_sensor_init_cfg_type_t cfgtype; + struct msm_sensor_info_t probed_info; + char entity_name[MAX_SENSOR_NAME]; + union { + void *setting; + } cfg; +}; + +#define CSI_RW_REG_LIST_SUPPORT + +#define VIDIOC_MSM_SENSOR_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data) + +#define VIDIOC_MSM_SENSOR_RELEASE \ + _IO('V', BASE_VIDIOC_PRIVATE + 2) + +#define VIDIOC_MSM_SENSOR_GET_SUBDEV_ID \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 3, uint32_t) + +#define VIDIOC_MSM_CSIPHY_IO_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data) + +#define VIDIOC_MSM_CSID_IO_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data) + +#define VIDIOC_MSM_ACTUATOR_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data) + +#define VIDIOC_MSM_FLASH_LED_DATA_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_led_cfg_t) + +#define VIDIOC_MSM_EEPROM_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data) + +#define VIDIOC_MSM_SENSOR_GET_AF_STATUS \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 9, uint32_t) + +#define VIDIOC_MSM_SENSOR_INIT_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data) + +#define VIDIOC_MSM_OIS_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data) + +#define VIDIOC_MSM_FLASH_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t) + +#define VIDIOC_MSM_OIS_CFG_DOWNLOAD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_ois_cfg_download_data) + +#define VIDIOC_MSM_IR_LED_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_led_cfg_data_t) + +#define VIDIOC_MSM_IR_CUT_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_cut_cfg_data_t) + +#endif /* __UAPI_LINUX_MSM_AIS_SENSOR_H */ + diff --git a/include/uapi/media/ais/msm_ais_sensor_sdk.h b/include/uapi/media/ais/msm_ais_sensor_sdk.h new file mode 100644 index 000000000000..3f63bde39cf3 --- /dev/null +++ b/include/uapi/media/ais/msm_ais_sensor_sdk.h @@ -0,0 +1,425 @@ +#ifndef __UAPI_LINUX_MSM_AIS_SENSOR_SDK_H +#define __UAPI_LINUX_MSM_AIS_SENSOR_SDK_H + +#include <linux/videodev2.h> + +#define KVERSION 0x1 + +#define MAX_POWER_CONFIG 12 +#define GPIO_OUT_LOW (0 << 1) +#define GPIO_OUT_HIGH (1 << 1) +#define CSI_EMBED_DATA 0x12 +#define CSI_RESERVED_DATA_0 0x13 +#define CSI_YUV422_8 0x1E +#define CSI_RAW8 0x2A +#define CSI_RAW10 0x2B +#define CSI_RAW12 0x2C +#define CSI_DECODE_6BIT 0 +#define CSI_DECODE_8BIT 1 +#define CSI_DECODE_10BIT 2 +#define CSI_DECODE_12BIT 3 +#define CSI_DECODE_DPCM_10_6_10 4 +#define CSI_DECODE_DPCM_10_8_10 5 +#define MAX_CID 16 +#define I2C_SEQ_REG_DATA_MAX 1024 +#define I2C_REG_DATA_MAX (8*1024) + +#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */ +#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') + /* 14 BGBG.. GRGR.. */ +#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') + /* 14 GBGB.. RGRG.. */ +#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') + /* 14 GRGR.. BGBG.. */ +#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') + /* 14 RGRG.. GBGB.. */ + +#define MAX_ACTUATOR_REG_TBL_SIZE 8 +#define MAX_ACTUATOR_REGION 5 +#define NUM_ACTUATOR_DIR 2 +#define MAX_ACTUATOR_SCENARIO 8 +#define MAX_ACT_MOD_NAME_SIZE 32 +#define MAX_ACT_NAME_SIZE 32 +#define MAX_ACTUATOR_INIT_SET 120 +#define MAX_I2C_REG_SET 12 + +#define MAX_LED_TRIGGERS 3 + +#define MSM_EEPROM_MEMORY_MAP_MAX_SIZE 80 +#define MSM_EEPROM_MAX_MEM_MAP_CNT 8 + +enum msm_sensor_camera_id_t { + CAMERA_0, + CAMERA_1, + CAMERA_2, + CAMERA_3, + MAX_CAMERAS, +}; + +enum i2c_freq_mode_t { + I2C_STANDARD_MODE, + I2C_FAST_MODE, + I2C_CUSTOM_MODE, + I2C_FAST_PLUS_MODE, + I2C_MAX_MODES, +}; + +enum camb_position_t { + BACK_CAMERA_B, + FRONT_CAMERA_B, + AUX_CAMERA_B = 0x100, + INVALID_CAMERA_B, +}; + +enum msm_sensor_power_seq_type_t { + SENSOR_CLK, + SENSOR_GPIO, + SENSOR_VREG, + SENSOR_I2C_MUX, + SENSOR_I2C, +}; + +enum msm_camera_i2c_reg_addr_type { + MSM_CAMERA_I2C_BYTE_ADDR = 1, + MSM_CAMERA_I2C_WORD_ADDR, + MSM_CAMERA_I2C_3B_ADDR, + MSM_CAMERA_I2C_ADDR_TYPE_MAX, +}; + +enum msm_camera_i2c_data_type { + MSM_CAMERA_I2C_BYTE_DATA = 1, + MSM_CAMERA_I2C_WORD_DATA, + MSM_CAMERA_I2C_DWORD_DATA, + MSM_CAMERA_I2C_SET_BYTE_MASK, + MSM_CAMERA_I2C_UNSET_BYTE_MASK, + MSM_CAMERA_I2C_SET_WORD_MASK, + MSM_CAMERA_I2C_UNSET_WORD_MASK, + MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA, + MSM_CAMERA_I2C_DATA_TYPE_MAX, +}; + +enum msm_sensor_power_seq_gpio_t { + SENSOR_GPIO_RESET, + SENSOR_GPIO_STANDBY, + SENSOR_GPIO_AF_PWDM, + SENSOR_GPIO_VIO, + SENSOR_GPIO_VANA, + SENSOR_GPIO_VDIG, + SENSOR_GPIO_VAF, + SENSOR_GPIO_FL_EN, + SENSOR_GPIO_FL_NOW, + SENSOR_GPIO_FL_RESET, + SENSOR_GPIO_CUSTOM1, + SENSOR_GPIO_CUSTOM2, + SENSOR_GPIO_MAX, +}; + +enum msm_ir_cut_filter_gpio_t { + IR_CUT_FILTER_GPIO_P = 0, + IR_CUT_FILTER_GPIO_M, + IR_CUT_FILTER_GPIO_MAX, +}; +#define IR_CUT_FILTER_GPIO_P IR_CUT_FILTER_GPIO_P +#define IR_CUT_FILTER_GPIO_M IR_CUT_FILTER_GPIO_M +#define R_CUT_FILTER_GPIO_MAX IR_CUT_FILTER_GPIO_MAX + +enum msm_camera_vreg_name_t { + CAM_VDIG, + CAM_VIO, + CAM_VANA, + CAM_VAF, + CAM_V_CUSTOM1, + CAM_V_CUSTOM2, + CAM_VREG_MAX, +}; + +enum msm_sensor_clk_type_t { + SENSOR_CAM_MCLK, + SENSOR_CAM_CLK, + SENSOR_CAM_CLK_MAX, +}; + +enum camerab_mode_t { + CAMERA_MODE_2D_B = (1<<0), + CAMERA_MODE_3D_B = (1<<1), + CAMERA_MODE_INVALID = (1<<2), +}; + +enum msm_actuator_data_type { + MSM_ACTUATOR_BYTE_DATA = 1, + MSM_ACTUATOR_WORD_DATA, +}; + +enum msm_actuator_addr_type { + MSM_ACTUATOR_BYTE_ADDR = 1, + MSM_ACTUATOR_WORD_ADDR, +}; + +enum msm_actuator_write_type { + MSM_ACTUATOR_WRITE_HW_DAMP, + MSM_ACTUATOR_WRITE_DAC, + MSM_ACTUATOR_WRITE, + MSM_ACTUATOR_WRITE_DIR_REG, + MSM_ACTUATOR_POLL, + MSM_ACTUATOR_READ_WRITE, +}; + +enum msm_actuator_i2c_operation { + MSM_ACT_WRITE = 0, + MSM_ACT_POLL, +}; + +enum actuator_type { + ACTUATOR_VCM, + ACTUATOR_PIEZO, + ACTUATOR_HVCM, + ACTUATOR_BIVCM, +}; + +enum msm_flash_driver_type { + FLASH_DRIVER_PMIC, + FLASH_DRIVER_I2C, + FLASH_DRIVER_GPIO, + FLASH_DRIVER_DEFAULT +}; + +enum msm_flash_cfg_type_t { + CFG_FLASH_INIT, + CFG_FLASH_RELEASE, + CFG_FLASH_OFF, + CFG_FLASH_LOW, + CFG_FLASH_HIGH, +}; + +enum msm_ir_led_cfg_type_t { + CFG_IR_LED_INIT = 0, + CFG_IR_LED_RELEASE, + CFG_IR_LED_OFF, + CFG_IR_LED_ON, +}; +#define CFG_IR_LED_INIT CFG_IR_LED_INIT +#define CFG_IR_LED_RELEASE CFG_IR_LED_RELEASE +#define CFG_IR_LED_OFF CFG_IR_LED_OFF +#define CFG_IR_LED_ON CFG_IR_LED_ON + +enum msm_ir_cut_cfg_type_t { + CFG_IR_CUT_INIT = 0, + CFG_IR_CUT_RELEASE, + CFG_IR_CUT_OFF, + CFG_IR_CUT_ON, +}; +#define CFG_IR_CUT_INIT CFG_IR_CUT_INIT +#define CFG_IR_CUT_RELEASE CFG_IR_CUT_RELEASE +#define CFG_IR_CUT_OFF CFG_IR_CUT_OFF +#define CFG_IR_CUT_ON CFG_IR_CUT_ON + +enum msm_sensor_output_format_t { + MSM_SENSOR_BAYER, + MSM_SENSOR_YCBCR, + MSM_SENSOR_META, +}; + +struct msm_sensor_power_setting { + enum msm_sensor_power_seq_type_t seq_type; + unsigned short seq_val; + long config_val; + unsigned short delay; + void *data[10]; +}; + +struct msm_sensor_power_setting_array { + struct msm_sensor_power_setting power_setting_a[MAX_POWER_CONFIG]; + struct msm_sensor_power_setting *power_setting; + unsigned short size; + struct msm_sensor_power_setting power_down_setting_a[MAX_POWER_CONFIG]; + struct msm_sensor_power_setting *power_down_setting; + unsigned short size_down; +}; + +enum msm_camera_i2c_operation { + MSM_CAM_WRITE = 0, + MSM_CAM_POLL, + MSM_CAM_READ, +}; + +struct msm_sensor_i2c_sync_params { + unsigned int cid; + int csid; + unsigned short line; + unsigned short delay; +}; + +struct msm_camera_reg_settings_t { + uint16_t reg_addr; + enum msm_camera_i2c_reg_addr_type addr_type; + uint16_t reg_data; + enum msm_camera_i2c_data_type data_type; + enum msm_camera_i2c_operation i2c_operation; + uint16_t delay; +}; + +struct msm_eeprom_mem_map_t { + int slave_addr; + struct msm_camera_reg_settings_t + mem_settings[MSM_EEPROM_MEMORY_MAP_MAX_SIZE]; + int memory_map_size; +}; + +struct msm_eeprom_memory_map_array { + struct msm_eeprom_mem_map_t memory_map[MSM_EEPROM_MAX_MEM_MAP_CNT]; + uint32_t msm_size_of_max_mappings; +}; + +struct msm_sensor_init_params { + /* mask of modes supported: 2D, 3D */ + int modes_supported; + /* sensor position: front, back */ + enum camb_position_t position; + /* sensor mount angle */ + unsigned int sensor_mount_angle; +}; + +struct msm_sensor_id_info_t { + unsigned short sensor_id_reg_addr; + unsigned short sensor_id; + unsigned short sensor_id_mask; +}; + +struct msm_camera_sensor_gpio_intr_config { + int gpio_num; + uint32_t gpio_trigger; +}; + +struct msm_camera_sensor_slave_info { + char sensor_name[32]; + char eeprom_name[32]; + char actuator_name[32]; + char ois_name[32]; + char flash_name[32]; + enum msm_sensor_camera_id_t camera_id; + unsigned short slave_addr; + enum i2c_freq_mode_t i2c_freq_mode; + enum msm_camera_i2c_reg_addr_type addr_type; + struct msm_sensor_id_info_t sensor_id_info; + struct msm_sensor_power_setting_array power_setting_array; + unsigned char is_init_params_valid; + struct msm_sensor_init_params sensor_init_params; + enum msm_sensor_output_format_t output_format; + struct msm_camera_sensor_gpio_intr_config + gpio_intr_config; + unsigned int camera_sensor_device_id; +}; + +struct msm_camera_i2c_reg_array { + unsigned short reg_addr; + unsigned short reg_data; + unsigned int delay; +}; + +struct msm_camera_i2c_reg_setting { + struct msm_camera_i2c_reg_array *reg_setting; + unsigned short size; + enum msm_camera_i2c_reg_addr_type addr_type; + enum msm_camera_i2c_data_type data_type; + unsigned short delay; +}; + +struct msm_camera_csid_vc_cfg { + unsigned char cid; + unsigned char dt; + unsigned char decode_format; +}; + +struct msm_camera_csid_lut_params { + unsigned char num_cid; + struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID]; + struct msm_camera_csid_vc_cfg *vc_cfg[MAX_CID]; +}; + +struct msm_camera_csid_params { + unsigned char lane_cnt; + unsigned short lane_assign; + unsigned char phy_sel; + unsigned int csi_clk; + struct msm_camera_csid_lut_params lut_params; + unsigned char csi_3p_sel; +}; + +struct msm_camera_csid_testmode_parms { + unsigned int num_bytes_per_line; + unsigned int num_lines; + unsigned int h_blanking_count; + unsigned int v_blanking_count; + unsigned int payload_mode; +}; + +struct msm_camera_csiphy_params { + unsigned char lane_cnt; + unsigned char settle_cnt; + unsigned short lane_mask; + unsigned char combo_mode; + unsigned char csid_core; + unsigned int csiphy_clk; + unsigned char csi_3phase; +}; + +struct msm_camera_i2c_seq_reg_array { + unsigned short reg_addr; + unsigned char reg_data[I2C_SEQ_REG_DATA_MAX]; + unsigned short reg_data_size; +}; + +struct msm_camera_i2c_seq_reg_setting { + struct msm_camera_i2c_seq_reg_array *reg_setting; + unsigned short size; + enum msm_camera_i2c_reg_addr_type addr_type; + unsigned short delay; +}; + +struct msm_actuator_reg_params_t { + enum msm_actuator_write_type reg_write_type; + unsigned int hw_mask; + unsigned short reg_addr; + unsigned short hw_shift; + unsigned short data_shift; + unsigned short data_type; + unsigned short addr_type; + unsigned short reg_data; + unsigned short delay; +}; + + +struct damping_params_t { + unsigned int damping_step; + unsigned int damping_delay; + unsigned int hw_params; +}; + +struct region_params_t { + /* [0] = ForwardDirection Macro boundary + * [1] = ReverseDirection Inf boundary + */ + unsigned short step_bound[2]; + unsigned short code_per_step; + /* qvalue for converting float type numbers to integer format */ + unsigned int qvalue; +}; + +struct reg_settings_t { + unsigned short reg_addr; + enum msm_camera_i2c_reg_addr_type addr_type; + unsigned short reg_data; + enum msm_camera_i2c_data_type data_type; + enum msm_actuator_i2c_operation i2c_operation; + unsigned int delay; +}; + +struct msm_camera_i2c_reg_setting_array { + struct msm_camera_i2c_reg_array reg_setting_a[MAX_I2C_REG_SET]; + unsigned short size; + enum msm_camera_i2c_reg_addr_type addr_type; + enum msm_camera_i2c_data_type data_type; + unsigned short delay; +}; + +#endif /* __UAPI_LINUX_MSM_AIS_SENSOR_SDK_H */ diff --git a/include/uapi/media/msm_ba.h b/include/uapi/media/msm_ba.h new file mode 100644 index 000000000000..45ddfb4c8cb9 --- /dev/null +++ b/include/uapi/media/msm_ba.h @@ -0,0 +1,77 @@ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __UAPI_MSM_BA_H__ +#define __UAPI_MSM_BA_H__ + +#include <linux/videodev2.h> +#include <linux/types.h> + +/* CSI control params */ +struct csi_ctrl_params { + uint32_t settle_count; + uint32_t lane_count; +}; + +/* AVI Infoframe params */ +enum picture_aspect_ratio { + PICTURE_ASPECT_RATIO_NONE, + PICTURE_ASPECT_RATIO_4_3, + PICTURE_ASPECT_RATIO_16_9, + PICTURE_ASPECT_RATIO_64_27, + PICTURE_ASPECT_RATIO_256_135, + PICTURE_ASPECT_RATIO_RESERVED, +}; + +enum active_format_aspect_ratio { + ACTIVE_ASPECT_RATIO_16_9_TOP = 2, + ACTIVE_ASPECT_RATIO_14_9_TOP = 3, + ACTIVE_ASPECT_RATIO_16_9_CENTER = 4, + ACTIVE_ASPECT_RATIO_PICTURE = 8, + ACTIVE_ASPECT_RATIO_4_3 = 9, + ACTIVE_ASPECT_RATIO_16_9 = 10, + ACTIVE_ASPECT_RATIO_14_9 = 11, + ACTIVE_ASPECT_RATIO_4_3_SP_14_9 = 13, + ACTIVE_ASPECT_RATIO_16_9_SP_14_9 = 14, + ACTIVE_ASPECT_RATIO_16_9_SP_4_3 = 15, +}; + +struct avi_infoframe_params { + enum picture_aspect_ratio picture_aspect; + enum active_format_aspect_ratio active_aspect; + unsigned char video_code; +}; + +/* Field info params */ +struct field_info_params { + bool even_field; + struct timeval field_ts; +}; + +/* private ioctl structure */ +struct msm_ba_v4l2_ioctl_t { + size_t len; + void __user *ptr; +}; + +/* ADV7481 private ioctls for CSI control params */ +#define VIDIOC_G_CSI_PARAMS \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_ba_v4l2_ioctl_t) +/* ADV7481 private ioctls for field info query */ +#define VIDIOC_G_FIELD_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 40, struct msm_ba_v4l2_ioctl_t) +/* ADV7481 private ioctl for AVI Infoframe query */ +#define VIDIOC_G_AVI_INFOFRAME \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 41, struct msm_ba_v4l2_ioctl_t) + +#endif diff --git a/include/uapi/media/msm_cam_sensor.h b/include/uapi/media/msm_cam_sensor.h new file mode 100644 index 000000000000..e4b4554dd690 --- /dev/null +++ b/include/uapi/media/msm_cam_sensor.h @@ -0,0 +1,637 @@ +#ifndef __UAPI_LINUX_MSM_CAM_SENSOR_H +#define __UAPI_LINUX_MSM_CAM_SENSOR_H + +#include <linux/v4l2-mediabus.h> +#include <media/msm_camsensor_sdk.h> + +#include <linux/types.h> +#include <linux/i2c.h> + +#define I2C_SEQ_REG_SETTING_MAX 5 + +#define MSM_SENSOR_MCLK_8HZ 8000000 +#define MSM_SENSOR_MCLK_16HZ 16000000 +#define MSM_SENSOR_MCLK_24HZ 24000000 + +#define MAX_SENSOR_NAME 32 +#define MAX_ACTUATOR_AF_TOTAL_STEPS 1024 + +#define MAX_OIS_MOD_NAME_SIZE 32 +#define MAX_OIS_NAME_SIZE 32 +#define MAX_OIS_REG_SETTINGS 800 + +#define MOVE_NEAR 0 +#define MOVE_FAR 1 + +#define MSM_ACTUATOR_MOVE_SIGNED_FAR -1 +#define MSM_ACTUATOR_MOVE_SIGNED_NEAR 1 + +#define MAX_ACTUATOR_REGION 5 + +#define MAX_EEPROM_NAME 32 + +#define MAX_AF_ITERATIONS 3 +#define MAX_NUMBER_OF_STEPS 47 +#define MAX_REGULATOR 5 + +/*msm_flash_query_data_t query types*/ +#define FLASH_QUERY_CURRENT 1 + +#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */ +#define MSM_V4L2_PIX_FMT_META10 v4l2_fourcc('M', 'E', '1', '0') /* META10 */ +#define MSM_V4L2_PIX_FMT_META12 v4l2_fourcc('M', 'E', '1', '2') /* META12 */ + +#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') + /* 14 BGBG.. GRGR.. */ +#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') + /* 14 GBGB.. RGRG.. */ +#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') + /* 14 GRGR.. BGBG.. */ +#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') + /* 14 RGRG.. GBGB.. */ + +enum flash_type { + LED_FLASH = 1, + STROBE_FLASH, + GPIO_FLASH +}; + +enum msm_sensor_resolution_t { + MSM_SENSOR_RES_FULL, + MSM_SENSOR_RES_QTR, + MSM_SENSOR_RES_2, + MSM_SENSOR_RES_3, + MSM_SENSOR_RES_4, + MSM_SENSOR_RES_5, + MSM_SENSOR_RES_6, + MSM_SENSOR_RES_7, + MSM_SENSOR_INVALID_RES, +}; + +enum msm_camera_stream_type_t { + MSM_CAMERA_STREAM_PREVIEW, + MSM_CAMERA_STREAM_SNAPSHOT, + MSM_CAMERA_STREAM_VIDEO, + MSM_CAMERA_STREAM_INVALID, +}; + +enum sensor_sub_module_t { + SUB_MODULE_SENSOR, + SUB_MODULE_CHROMATIX, + SUB_MODULE_ACTUATOR, + SUB_MODULE_EEPROM, + SUB_MODULE_LED_FLASH, + SUB_MODULE_STROBE_FLASH, + SUB_MODULE_CSID, + SUB_MODULE_CSID_3D, + SUB_MODULE_CSIPHY, + SUB_MODULE_CSIPHY_3D, + SUB_MODULE_OIS, + SUB_MODULE_EXT, + SUB_MODULE_IR_LED, + SUB_MODULE_IR_CUT, + SUB_MODULE_LASER_LED, + SUB_MODULE_MAX, +}; + +enum { + MSM_CAMERA_EFFECT_MODE_OFF, + MSM_CAMERA_EFFECT_MODE_MONO, + MSM_CAMERA_EFFECT_MODE_NEGATIVE, + MSM_CAMERA_EFFECT_MODE_SOLARIZE, + MSM_CAMERA_EFFECT_MODE_SEPIA, + MSM_CAMERA_EFFECT_MODE_POSTERIZE, + MSM_CAMERA_EFFECT_MODE_WHITEBOARD, + MSM_CAMERA_EFFECT_MODE_BLACKBOARD, + MSM_CAMERA_EFFECT_MODE_AQUA, + MSM_CAMERA_EFFECT_MODE_EMBOSS, + MSM_CAMERA_EFFECT_MODE_SKETCH, + MSM_CAMERA_EFFECT_MODE_NEON, + MSM_CAMERA_EFFECT_MODE_MAX +}; + +enum { + MSM_CAMERA_WB_MODE_AUTO, + MSM_CAMERA_WB_MODE_CUSTOM, + MSM_CAMERA_WB_MODE_INCANDESCENT, + MSM_CAMERA_WB_MODE_FLUORESCENT, + MSM_CAMERA_WB_MODE_WARM_FLUORESCENT, + MSM_CAMERA_WB_MODE_DAYLIGHT, + MSM_CAMERA_WB_MODE_CLOUDY_DAYLIGHT, + MSM_CAMERA_WB_MODE_TWILIGHT, + MSM_CAMERA_WB_MODE_SHADE, + MSM_CAMERA_WB_MODE_OFF, + MSM_CAMERA_WB_MODE_MAX +}; + +enum { + MSM_CAMERA_SCENE_MODE_OFF, + MSM_CAMERA_SCENE_MODE_AUTO, + MSM_CAMERA_SCENE_MODE_LANDSCAPE, + MSM_CAMERA_SCENE_MODE_SNOW, + MSM_CAMERA_SCENE_MODE_BEACH, + MSM_CAMERA_SCENE_MODE_SUNSET, + MSM_CAMERA_SCENE_MODE_NIGHT, + MSM_CAMERA_SCENE_MODE_PORTRAIT, + MSM_CAMERA_SCENE_MODE_BACKLIGHT, + MSM_CAMERA_SCENE_MODE_SPORTS, + MSM_CAMERA_SCENE_MODE_ANTISHAKE, + MSM_CAMERA_SCENE_MODE_FLOWERS, + MSM_CAMERA_SCENE_MODE_CANDLELIGHT, + MSM_CAMERA_SCENE_MODE_FIREWORKS, + MSM_CAMERA_SCENE_MODE_PARTY, + MSM_CAMERA_SCENE_MODE_NIGHT_PORTRAIT, + MSM_CAMERA_SCENE_MODE_THEATRE, + MSM_CAMERA_SCENE_MODE_ACTION, + MSM_CAMERA_SCENE_MODE_AR, + MSM_CAMERA_SCENE_MODE_FACE_PRIORITY, + MSM_CAMERA_SCENE_MODE_BARCODE, + MSM_CAMERA_SCENE_MODE_HDR, + MSM_CAMERA_SCENE_MODE_MAX +}; + +enum csid_cfg_type_t { + CSID_INIT, + CSID_CFG, + CSID_TESTMODE_CFG, + CSID_RELEASE, +}; + +enum csiphy_cfg_type_t { + CSIPHY_INIT, + CSIPHY_CFG, + CSIPHY_RELEASE, +}; + +enum camera_vreg_type { + VREG_TYPE_DEFAULT, + VREG_TYPE_CUSTOM, +}; + +enum sensor_af_t { + SENSOR_AF_FOCUSSED, + SENSOR_AF_NOT_FOCUSSED, +}; + +enum cci_i2c_master_t { + MASTER_0, + MASTER_1, + MASTER_MAX, +}; + +struct msm_camera_i2c_array_write_config { + struct msm_camera_i2c_reg_setting conf_array; + uint16_t slave_addr; +}; + +struct msm_camera_i2c_read_config { + uint16_t slave_addr; + uint16_t reg_addr; + enum msm_camera_i2c_reg_addr_type addr_type; + enum msm_camera_i2c_data_type data_type; + uint16_t data; +}; + +struct msm_camera_csi2_params { + struct msm_camera_csid_params csid_params; + struct msm_camera_csiphy_params csiphy_params; + uint8_t csi_clk_scale_enable; +}; + +struct msm_camera_csi_lane_params { + uint16_t csi_lane_assign; + uint16_t csi_lane_mask; +}; + +struct csi_lane_params_t { + uint16_t csi_lane_assign; + uint8_t csi_lane_mask; + uint8_t csi_if; + int8_t csid_core[2]; + uint8_t csi_phy_sel; +}; + +struct msm_sensor_info_t { + char sensor_name[MAX_SENSOR_NAME]; + uint32_t session_id; + int32_t subdev_id[SUB_MODULE_MAX]; + int32_t subdev_intf[SUB_MODULE_MAX]; + uint8_t is_mount_angle_valid; + uint32_t sensor_mount_angle; + int modes_supported; + enum camb_position_t position; +}; + +struct camera_vreg_t { + const char *reg_name; + int min_voltage; + int max_voltage; + int op_mode; + uint32_t delay; + const char *custom_vreg_name; + enum camera_vreg_type type; +}; + +struct sensorb_cfg_data { + int cfgtype; + union { + struct msm_sensor_info_t sensor_info; + struct msm_sensor_init_params sensor_init_params; + void *setting; + struct msm_sensor_i2c_sync_params sensor_i2c_sync_params; + } cfg; +}; + +struct csid_cfg_data { + enum csid_cfg_type_t cfgtype; + union { + uint32_t csid_version; + struct msm_camera_csid_params *csid_params; + struct msm_camera_csid_testmode_parms *csid_testmode_params; + } cfg; +}; + +struct csiphy_cfg_data { + enum csiphy_cfg_type_t cfgtype; + union { + struct msm_camera_csiphy_params *csiphy_params; + struct msm_camera_csi_lane_params *csi_lane_params; + } cfg; +}; + +enum eeprom_cfg_type_t { + CFG_EEPROM_GET_INFO, + CFG_EEPROM_GET_CAL_DATA, + CFG_EEPROM_READ_CAL_DATA, + CFG_EEPROM_WRITE_DATA, + CFG_EEPROM_GET_MM_INFO, + CFG_EEPROM_INIT, +}; + +struct eeprom_get_t { + uint32_t num_bytes; +}; + +struct eeprom_read_t { + uint8_t *dbuffer; + uint32_t num_bytes; +}; + +struct eeprom_write_t { + uint8_t *dbuffer; + uint32_t num_bytes; +}; + +struct eeprom_get_cmm_t { + uint32_t cmm_support; + uint32_t cmm_compression; + uint32_t cmm_size; +}; + +struct msm_eeprom_info_t { + struct msm_sensor_power_setting_array *power_setting_array; + enum i2c_freq_mode_t i2c_freq_mode; + struct msm_eeprom_memory_map_array *mem_map_array; +}; + +struct msm_ir_led_cfg_data_t { + enum msm_ir_led_cfg_type_t cfg_type; + int32_t pwm_duty_on_ns; + int32_t pwm_period_ns; +}; + +struct msm_ir_cut_cfg_data_t { + enum msm_ir_cut_cfg_type_t cfg_type; +}; + +struct msm_laser_led_cfg_data_t { + enum msm_laser_led_cfg_type_t cfg_type; + void __user *setting; + void __user *debug_reg; + uint32_t debug_reg_size; + uint16_t i2c_addr; + enum i2c_freq_mode_t i2c_freq_mode; +}; + +struct msm_eeprom_cfg_data { + enum eeprom_cfg_type_t cfgtype; + uint8_t is_supported; + union { + char eeprom_name[MAX_EEPROM_NAME]; + struct eeprom_get_t get_data; + struct eeprom_read_t read_data; + struct eeprom_write_t write_data; + struct eeprom_get_cmm_t get_cmm_data; + struct msm_eeprom_info_t eeprom_info; + } cfg; +}; + +enum msm_sensor_cfg_type_t { + CFG_SET_SLAVE_INFO, + CFG_SLAVE_READ_I2C, + CFG_WRITE_I2C_ARRAY, + CFG_SLAVE_WRITE_I2C_ARRAY, + CFG_WRITE_I2C_SEQ_ARRAY, + CFG_POWER_UP, + CFG_POWER_DOWN, + CFG_SET_STOP_STREAM_SETTING, + CFG_GET_SENSOR_INFO, + CFG_GET_SENSOR_INIT_PARAMS, + CFG_SET_INIT_SETTING, + CFG_SET_RESOLUTION, + CFG_SET_STOP_STREAM, + CFG_SET_START_STREAM, + CFG_SET_SATURATION, + CFG_SET_CONTRAST, + CFG_SET_SHARPNESS, + CFG_SET_ISO, + CFG_SET_EXPOSURE_COMPENSATION, + CFG_SET_ANTIBANDING, + CFG_SET_BESTSHOT_MODE, + CFG_SET_EFFECT, + CFG_SET_WHITE_BALANCE, + CFG_SET_AUTOFOCUS, + CFG_CANCEL_AUTOFOCUS, + CFG_SET_STREAM_TYPE, + CFG_SET_I2C_SYNC_PARAM, + CFG_WRITE_I2C_ARRAY_ASYNC, + CFG_WRITE_I2C_ARRAY_SYNC, + CFG_WRITE_I2C_ARRAY_SYNC_BLOCK, +}; + +enum msm_actuator_cfg_type_t { + CFG_GET_ACTUATOR_INFO, + CFG_SET_ACTUATOR_INFO, + CFG_SET_DEFAULT_FOCUS, + CFG_MOVE_FOCUS, + CFG_SET_POSITION, + CFG_ACTUATOR_POWERDOWN, + CFG_ACTUATOR_POWERUP, + CFG_ACTUATOR_INIT, +}; + +struct msm_ois_opcode { + uint32_t prog; + uint32_t coeff; + uint32_t pheripheral; + uint32_t memory; +}; + +enum msm_ois_cfg_type_t { + CFG_OIS_INIT, + CFG_OIS_POWERDOWN, + CFG_OIS_POWERUP, + CFG_OIS_CONTROL, + CFG_OIS_I2C_WRITE_SEQ_TABLE, +}; + +enum msm_ois_cfg_download_type_t { + CFG_OIS_DOWNLOAD, + CFG_OIS_DATA_CONFIG, +}; + +enum msm_ois_i2c_operation { + MSM_OIS_WRITE = 0, + MSM_OIS_POLL, + MSM_OIS_READ, +}; +#define MSM_OIS_READ MSM_OIS_READ + +struct reg_settings_ois_t { + uint16_t reg_addr; + enum msm_camera_i2c_reg_addr_type addr_type; + uint32_t reg_data; + enum msm_camera_i2c_data_type data_type; + enum msm_ois_i2c_operation i2c_operation; + uint32_t delay; +}; + +struct msm_ois_params_t { + uint16_t data_size; + uint16_t setting_size; + uint32_t i2c_addr; + enum i2c_freq_mode_t i2c_freq_mode; + enum msm_camera_i2c_reg_addr_type i2c_addr_type; + enum msm_camera_i2c_data_type i2c_data_type; + struct reg_settings_ois_t *settings; +}; + +struct msm_ois_set_info_t { + struct msm_ois_params_t ois_params; +}; + +struct msm_actuator_move_params_t { + int8_t dir; + int8_t sign_dir; + int16_t dest_step_pos; + int32_t num_steps; + uint16_t curr_lens_pos; + struct damping_params_t *ringing_params; +}; + +struct msm_actuator_tuning_params_t { + int16_t initial_code; + uint16_t pwd_step; + uint16_t region_size; + uint32_t total_steps; + struct region_params_t *region_params; +}; + +struct park_lens_data_t { + uint32_t damping_step; + uint32_t damping_delay; + uint32_t hw_params; + uint32_t max_step; +}; + +struct msm_actuator_params_t { + enum actuator_type act_type; + uint8_t reg_tbl_size; + uint16_t data_size; + uint16_t init_setting_size; + uint32_t i2c_addr; + enum i2c_freq_mode_t i2c_freq_mode; + enum msm_camera_i2c_reg_addr_type i2c_addr_type; + enum msm_camera_i2c_data_type i2c_data_type; + struct msm_actuator_reg_params_t *reg_tbl_params; + struct reg_settings_t *init_settings; + struct park_lens_data_t park_lens; +}; + +struct msm_actuator_set_info_t { + struct msm_actuator_params_t actuator_params; + struct msm_actuator_tuning_params_t af_tuning_params; +}; + +struct msm_actuator_get_info_t { + uint32_t focal_length_num; + uint32_t focal_length_den; + uint32_t f_number_num; + uint32_t f_number_den; + uint32_t f_pix_num; + uint32_t f_pix_den; + uint32_t total_f_dist_num; + uint32_t total_f_dist_den; + uint32_t hor_view_angle_num; + uint32_t hor_view_angle_den; + uint32_t ver_view_angle_num; + uint32_t ver_view_angle_den; +}; + +enum af_camera_name { + ACTUATOR_MAIN_CAM_0, + ACTUATOR_MAIN_CAM_1, + ACTUATOR_MAIN_CAM_2, + ACTUATOR_MAIN_CAM_3, + ACTUATOR_MAIN_CAM_4, + ACTUATOR_MAIN_CAM_5, + ACTUATOR_WEB_CAM_0, + ACTUATOR_WEB_CAM_1, + ACTUATOR_WEB_CAM_2, +}; + +struct msm_ois_slave_info { + char ois_name[MAX_OIS_NAME_SIZE]; + uint32_t i2c_addr; + struct msm_ois_opcode opcode; +}; +struct msm_ois_cfg_data { + int cfgtype; + union { + struct msm_ois_set_info_t set_info; + struct msm_camera_i2c_seq_reg_setting *settings; + } cfg; +}; + +struct msm_ois_cfg_download_data { + int cfgtype; + struct msm_ois_slave_info slave_info; +}; + +struct msm_actuator_set_position_t { + uint16_t number_of_steps; + uint32_t hw_params; + uint16_t pos[MAX_NUMBER_OF_STEPS]; + uint16_t delay[MAX_NUMBER_OF_STEPS]; +}; + +struct msm_actuator_cfg_data { + int cfgtype; + uint8_t is_af_supported; + union { + struct msm_actuator_move_params_t move; + struct msm_actuator_set_info_t set_info; + struct msm_actuator_get_info_t get_info; + struct msm_actuator_set_position_t setpos; + enum af_camera_name cam_name; + } cfg; +}; + +enum msm_camera_led_config_t { + MSM_CAMERA_LED_OFF, + MSM_CAMERA_LED_LOW, + MSM_CAMERA_LED_HIGH, + MSM_CAMERA_LED_INIT, + MSM_CAMERA_LED_RELEASE, +}; + +struct msm_camera_led_cfg_t { + enum msm_camera_led_config_t cfgtype; + int32_t torch_current[MAX_LED_TRIGGERS]; + int32_t flash_current[MAX_LED_TRIGGERS]; + int32_t flash_duration[MAX_LED_TRIGGERS]; +}; + +struct msm_flash_init_info_t { + enum msm_flash_driver_type flash_driver_type; + uint32_t slave_addr; + enum i2c_freq_mode_t i2c_freq_mode; + struct msm_sensor_power_setting_array *power_setting_array; + struct msm_camera_i2c_reg_setting_array *settings; +}; + +struct msm_flash_cfg_data_t { + enum msm_flash_cfg_type_t cfg_type; + int32_t flash_current[MAX_LED_TRIGGERS]; + int32_t flash_duration[MAX_LED_TRIGGERS]; + union { + struct msm_flash_init_info_t *flash_init_info; + struct msm_camera_i2c_reg_setting_array *settings; + } cfg; +}; + +struct msm_flash_query_data_t { + int32_t flags; + int32_t query_type; + int32_t max_avail_curr; +}; + +/* sensor init structures and enums */ +enum msm_sensor_init_cfg_type_t { + CFG_SINIT_PROBE, + CFG_SINIT_PROBE_DONE, + CFG_SINIT_PROBE_WAIT_DONE, +}; + +struct sensor_init_cfg_data { + enum msm_sensor_init_cfg_type_t cfgtype; + struct msm_sensor_info_t probed_info; + char entity_name[MAX_SENSOR_NAME]; + union { + void *setting; + } cfg; +}; + +#define VIDIOC_MSM_SENSOR_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data) + +#define VIDIOC_MSM_SENSOR_RELEASE \ + _IO('V', BASE_VIDIOC_PRIVATE + 2) + +#define VIDIOC_MSM_SENSOR_GET_SUBDEV_ID \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 3, uint32_t) + +#define VIDIOC_MSM_CSIPHY_IO_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csiphy_cfg_data) + +#define VIDIOC_MSM_CSID_IO_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csid_cfg_data) + +#define VIDIOC_MSM_ACTUATOR_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data) + +#define VIDIOC_MSM_FLASH_LED_DATA_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_led_cfg_t) + +#define VIDIOC_MSM_EEPROM_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data) + +#define VIDIOC_MSM_SENSOR_GET_AF_STATUS \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 9, uint32_t) + +#define VIDIOC_MSM_SENSOR_INIT_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct sensor_init_cfg_data) + +#define VIDIOC_MSM_OIS_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_ois_cfg_data) + +#define VIDIOC_MSM_FLASH_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_flash_cfg_data_t) + +#define VIDIOC_MSM_OIS_CFG_DOWNLOAD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_ois_cfg_download_data) + +#define VIDIOC_MSM_FLASH_QUERY_DATA \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_flash_query_data_t) + +#define VIDIOC_MSM_IR_LED_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_led_cfg_data_t) + +#define VIDIOC_MSM_IR_CUT_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_ir_cut_cfg_data_t) + +#define VIDIOC_MSM_LASER_LED_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_laser_led_cfg_data_t) + +#endif + diff --git a/include/uapi/media/msm_camera.h b/include/uapi/media/msm_camera.h new file mode 100644 index 000000000000..81e350ede6eb --- /dev/null +++ b/include/uapi/media/msm_camera.h @@ -0,0 +1,2228 @@ +/* Copyright (c) 2009-2012, 2014-2016, 2018 The Linux Foundation. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __UAPI_MSM_CAMERA_H +#define __UAPI_MSM_CAMERA_H + +#include <linux/videodev2.h> +#include <linux/types.h> +#include <linux/ioctl.h> + +#include <linux/msm_ion.h> + +#define BIT(nr) (1UL << (nr)) + +#define MSM_CAM_IOCTL_MAGIC 'm' + +#define MAX_SERVER_PAYLOAD_LENGTH 8192 + +#define MSM_CAM_IOCTL_GET_SENSOR_INFO \ + _IOR(MSM_CAM_IOCTL_MAGIC, 1, struct msm_camsensor_info *) + +#define MSM_CAM_IOCTL_REGISTER_PMEM \ + _IOW(MSM_CAM_IOCTL_MAGIC, 2, struct msm_pmem_info *) + +#define MSM_CAM_IOCTL_UNREGISTER_PMEM \ + _IOW(MSM_CAM_IOCTL_MAGIC, 3, unsigned) + +#define MSM_CAM_IOCTL_CTRL_COMMAND \ + _IOW(MSM_CAM_IOCTL_MAGIC, 4, struct msm_ctrl_cmd *) + +#define MSM_CAM_IOCTL_CONFIG_VFE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 5, struct msm_camera_vfe_cfg_cmd *) + +#define MSM_CAM_IOCTL_GET_STATS \ + _IOR(MSM_CAM_IOCTL_MAGIC, 6, struct msm_camera_stats_event_ctrl *) + +#define MSM_CAM_IOCTL_GETFRAME \ + _IOR(MSM_CAM_IOCTL_MAGIC, 7, struct msm_camera_get_frame *) + +#define MSM_CAM_IOCTL_ENABLE_VFE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 8, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_CTRL_CMD_DONE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 9, struct camera_cmd *) + +#define MSM_CAM_IOCTL_CONFIG_CMD \ + _IOW(MSM_CAM_IOCTL_MAGIC, 10, struct camera_cmd *) + +#define MSM_CAM_IOCTL_DISABLE_VFE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 11, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_PAD_REG_RESET2 \ + _IOW(MSM_CAM_IOCTL_MAGIC, 12, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_VFE_APPS_RESET \ + _IOW(MSM_CAM_IOCTL_MAGIC, 13, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_RELEASE_FRAME_BUFFER \ + _IOW(MSM_CAM_IOCTL_MAGIC, 14, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_RELEASE_STATS_BUFFER \ + _IOW(MSM_CAM_IOCTL_MAGIC, 15, struct msm_stats_buf *) + +#define MSM_CAM_IOCTL_AXI_CONFIG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 16, struct msm_camera_vfe_cfg_cmd *) + +#define MSM_CAM_IOCTL_GET_PICTURE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 17, struct msm_frame *) + +#define MSM_CAM_IOCTL_SET_CROP \ + _IOW(MSM_CAM_IOCTL_MAGIC, 18, struct crop_info *) + +#define MSM_CAM_IOCTL_PICT_PP \ + _IOW(MSM_CAM_IOCTL_MAGIC, 19, uint8_t *) + +#define MSM_CAM_IOCTL_PICT_PP_DONE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 20, struct msm_snapshot_pp_status *) + +#define MSM_CAM_IOCTL_SENSOR_IO_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 21, struct sensor_cfg_data *) + +#define MSM_CAM_IOCTL_FLASH_LED_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 22, unsigned *) + +#define MSM_CAM_IOCTL_UNBLOCK_POLL_FRAME \ + _IO(MSM_CAM_IOCTL_MAGIC, 23) + +#define MSM_CAM_IOCTL_CTRL_COMMAND_2 \ + _IOW(MSM_CAM_IOCTL_MAGIC, 24, struct msm_ctrl_cmd *) + +#define MSM_CAM_IOCTL_AF_CTRL \ + _IOR(MSM_CAM_IOCTL_MAGIC, 25, struct msm_ctrl_cmt_t *) + +#define MSM_CAM_IOCTL_AF_CTRL_DONE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 26, struct msm_ctrl_cmt_t *) + +#define MSM_CAM_IOCTL_CONFIG_VPE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 27, struct msm_camera_vpe_cfg_cmd *) + +#define MSM_CAM_IOCTL_AXI_VPE_CONFIG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 28, struct msm_camera_vpe_cfg_cmd *) + +#define MSM_CAM_IOCTL_STROBE_FLASH_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 29, uint32_t *) + +#define MSM_CAM_IOCTL_STROBE_FLASH_CHARGE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 30, uint32_t *) + +#define MSM_CAM_IOCTL_STROBE_FLASH_RELEASE \ + _IO(MSM_CAM_IOCTL_MAGIC, 31) + +#define MSM_CAM_IOCTL_FLASH_CTRL \ + _IOW(MSM_CAM_IOCTL_MAGIC, 32, struct flash_ctrl_data *) + +#define MSM_CAM_IOCTL_ERROR_CONFIG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 33, uint32_t *) + +#define MSM_CAM_IOCTL_ABORT_CAPTURE \ + _IO(MSM_CAM_IOCTL_MAGIC, 34) + +#define MSM_CAM_IOCTL_SET_FD_ROI \ + _IOW(MSM_CAM_IOCTL_MAGIC, 35, struct fd_roi_info *) + +#define MSM_CAM_IOCTL_GET_CAMERA_INFO \ + _IOR(MSM_CAM_IOCTL_MAGIC, 36, struct msm_camera_info *) + +#define MSM_CAM_IOCTL_UNBLOCK_POLL_PIC_FRAME \ + _IO(MSM_CAM_IOCTL_MAGIC, 37) + +#define MSM_CAM_IOCTL_RELEASE_PIC_BUFFER \ + _IOW(MSM_CAM_IOCTL_MAGIC, 38, struct camera_enable_cmd *) + +#define MSM_CAM_IOCTL_PUT_ST_FRAME \ + _IOW(MSM_CAM_IOCTL_MAGIC, 39, struct msm_camera_st_frame *) + +#define MSM_CAM_IOCTL_V4L2_EVT_NOTIFY \ + _IOW(MSM_CAM_IOCTL_MAGIC, 40, struct v4l2_event_and_payload) + +#define MSM_CAM_IOCTL_SET_MEM_MAP_INFO \ + _IOR(MSM_CAM_IOCTL_MAGIC, 41, struct msm_mem_map_info *) + +#define MSM_CAM_IOCTL_ACTUATOR_IO_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 42, struct msm_actuator_cfg_data *) + +#define MSM_CAM_IOCTL_MCTL_POST_PROC \ + _IOW(MSM_CAM_IOCTL_MAGIC, 43, struct msm_mctl_post_proc_cmd *) + +#define MSM_CAM_IOCTL_RESERVE_FREE_FRAME \ + _IOW(MSM_CAM_IOCTL_MAGIC, 44, struct msm_cam_evt_divert_frame *) + +#define MSM_CAM_IOCTL_RELEASE_FREE_FRAME \ + _IOR(MSM_CAM_IOCTL_MAGIC, 45, struct msm_cam_evt_divert_frame *) + +#define MSM_CAM_IOCTL_PICT_PP_DIVERT_DONE \ + _IOR(MSM_CAM_IOCTL_MAGIC, 46, struct msm_pp_frame *) + +#define MSM_CAM_IOCTL_SENSOR_V4l2_S_CTRL \ + _IOR(MSM_CAM_IOCTL_MAGIC, 47, struct v4l2_control) + +#define MSM_CAM_IOCTL_SENSOR_V4l2_QUERY_CTRL \ + _IOR(MSM_CAM_IOCTL_MAGIC, 48, struct v4l2_queryctrl) + +#define MSM_CAM_IOCTL_GET_KERNEL_SYSTEM_TIME \ + _IOW(MSM_CAM_IOCTL_MAGIC, 49, struct timeval *) + +#define MSM_CAM_IOCTL_SET_VFE_OUTPUT_TYPE \ + _IOW(MSM_CAM_IOCTL_MAGIC, 50, uint32_t *) + +#define MSM_CAM_IOCTL_MCTL_DIVERT_DONE \ + _IOR(MSM_CAM_IOCTL_MAGIC, 51, struct msm_cam_evt_divert_frame *) + +#define MSM_CAM_IOCTL_GET_ACTUATOR_INFO \ + _IOW(MSM_CAM_IOCTL_MAGIC, 52, struct msm_actuator_cfg_data *) + +#define MSM_CAM_IOCTL_EEPROM_IO_CFG \ + _IOW(MSM_CAM_IOCTL_MAGIC, 53, struct msm_eeprom_cfg_data *) + +#define MSM_CAM_IOCTL_ISPIF_IO_CFG \ + _IOR(MSM_CAM_IOCTL_MAGIC, 54, struct ispif_cfg_data *) + +#define MSM_CAM_IOCTL_STATS_REQBUF \ + _IOR(MSM_CAM_IOCTL_MAGIC, 55, struct msm_stats_reqbuf *) + +#define MSM_CAM_IOCTL_STATS_ENQUEUEBUF \ + _IOR(MSM_CAM_IOCTL_MAGIC, 56, struct msm_stats_buf_info *) + +#define MSM_CAM_IOCTL_STATS_FLUSH_BUFQ \ + _IOR(MSM_CAM_IOCTL_MAGIC, 57, struct msm_stats_flush_bufq *) + +#define MSM_CAM_IOCTL_SET_MCTL_SDEV \ + _IOW(MSM_CAM_IOCTL_MAGIC, 58, struct msm_mctl_set_sdev_data *) + +#define MSM_CAM_IOCTL_UNSET_MCTL_SDEV \ + _IOW(MSM_CAM_IOCTL_MAGIC, 59, struct msm_mctl_set_sdev_data *) + +#define MSM_CAM_IOCTL_GET_INST_HANDLE \ + _IOR(MSM_CAM_IOCTL_MAGIC, 60, uint32_t *) + +#define MSM_CAM_IOCTL_STATS_UNREG_BUF \ + _IOR(MSM_CAM_IOCTL_MAGIC, 61, struct msm_stats_flush_bufq *) + +#define MSM_CAM_IOCTL_CSIC_IO_CFG \ + _IOWR(MSM_CAM_IOCTL_MAGIC, 62, struct csic_cfg_data *) + +#define MSM_CAM_IOCTL_CSID_IO_CFG \ + _IOWR(MSM_CAM_IOCTL_MAGIC, 63, struct csid_cfg_data *) + +#define MSM_CAM_IOCTL_CSIPHY_IO_CFG \ + _IOR(MSM_CAM_IOCTL_MAGIC, 64, struct csiphy_cfg_data *) + +#define MSM_CAM_IOCTL_OEM \ + _IOW(MSM_CAM_IOCTL_MAGIC, 65, struct sensor_cfg_data *) + +#define MSM_CAM_IOCTL_AXI_INIT \ + _IOWR(MSM_CAM_IOCTL_MAGIC, 66, uint8_t *) + +#define MSM_CAM_IOCTL_AXI_RELEASE \ + _IO(MSM_CAM_IOCTL_MAGIC, 67) + +struct v4l2_event_and_payload { + struct v4l2_event evt; + uint32_t payload_length; + uint32_t transaction_id; + void *payload; +}; + +struct msm_stats_reqbuf { + int num_buf; /* how many buffers requested */ + int stats_type; /* stats type */ +}; + +struct msm_stats_flush_bufq { + int stats_type; /* enum msm_stats_enum_type */ +}; + +struct msm_mctl_pp_cmd { + int32_t id; + uint16_t length; + void *value; +}; + +struct msm_mctl_post_proc_cmd { + int32_t type; + struct msm_mctl_pp_cmd cmd; +}; + +#define MSM_CAMERA_LED_OFF 0 +#define MSM_CAMERA_LED_LOW 1 +#define MSM_CAMERA_LED_HIGH 2 +#define MSM_CAMERA_LED_INIT 3 +#define MSM_CAMERA_LED_RELEASE 4 + +#define MSM_CAMERA_STROBE_FLASH_NONE 0 +#define MSM_CAMERA_STROBE_FLASH_XENON 1 + +#define MSM_MAX_CAMERA_SENSORS 6 +#define MAX_SENSOR_NAME 32 +#define MAX_CAM_NAME_SIZE 32 +#define MAX_ACT_MOD_NAME_SIZE 32 +#define MAX_ACT_NAME_SIZE 32 +#define NUM_ACTUATOR_DIR 2 +#define MAX_ACTUATOR_SCENARIO 8 +#define MAX_ACTUATOR_REGION 5 +#define MAX_ACTUATOR_INIT_SET 12 +#define MAX_ACTUATOR_TYPE_SIZE 32 +#define MAX_ACTUATOR_REG_TBL_SIZE 8 + + +#define MSM_MAX_CAMERA_CONFIGS 2 + +#define PP_SNAP 0x01 +#define PP_RAW_SNAP ((0x01)<<1) +#define PP_PREV ((0x01)<<2) +#define PP_THUMB ((0x01)<<3) +#define PP_MASK (PP_SNAP|PP_RAW_SNAP|PP_PREV|PP_THUMB) + +#define MSM_CAM_CTRL_CMD_DONE 0 +#define MSM_CAM_SENSOR_VFE_CMD 1 + +/* Should be same as VIDEO_MAX_PLANES in videodev2.h */ +#define MAX_PLANES 8 + +/***************************************************** + * structure + *****************************************************/ + +/* define five type of structures for userspace <==> kernel + * space communication: + * command 1 - 2 are from userspace ==> kernel + * command 3 - 4 are from kernel ==> userspace + * + * 1. control command: control command(from control thread), + * control status (from config thread); + */ +struct msm_ctrl_cmd { + uint16_t type; + uint16_t length; + void *value; + uint16_t status; + uint32_t timeout_ms; + int resp_fd; /* FIXME: to be used by the kernel, pass-through for now */ + int vnode_id; /* video dev id. Can we overload resp_fd? */ + int queue_idx; + uint32_t evt_id; + uint32_t stream_type; /* used to pass value to qcamera server */ + int config_ident; /*used as identifier for config node*/ +}; + +struct msm_cam_evt_msg { + unsigned short type; /* 1 == event (RPC), 0 == message (adsp) */ + unsigned short msg_id; + unsigned int len; /* size in, number of bytes out */ + uint32_t frame_id; + void *data; + struct timespec timestamp; +}; + +struct msm_pp_frame_sp { + /* phy addr of the buffer */ + unsigned long phy_addr; + uint32_t y_off; + uint32_t cbcr_off; + /* buffer length */ + uint32_t length; + int32_t fd; + uint32_t addr_offset; + /* mapped addr */ + unsigned long vaddr; +}; + +struct msm_pp_frame_mp { + /* phy addr of the plane */ + unsigned long phy_addr; + /* offset of plane data */ + uint32_t data_offset; + /* plane length */ + uint32_t length; + int32_t fd; + uint32_t addr_offset; + /* mapped addr */ + unsigned long vaddr; +}; + +struct msm_pp_frame { + uint32_t handle; /* stores vb cookie */ + uint32_t frame_id; + unsigned short buf_idx; + int path; + unsigned short image_type; + unsigned short num_planes; /* 1 for sp */ + struct timeval timestamp; + union { + struct msm_pp_frame_sp sp; + struct msm_pp_frame_mp mp[MAX_PLANES]; + }; + int node_type; + uint32_t inst_handle; +}; + +struct msm_pp_crop { + uint32_t src_x; + uint32_t src_y; + uint32_t src_w; + uint32_t src_h; + uint32_t dst_x; + uint32_t dst_y; + uint32_t dst_w; + uint32_t dst_h; + uint8_t update_flag; +}; + +struct msm_mctl_pp_frame_cmd { + uint32_t cookie; + uint8_t vpe_output_action; + struct msm_pp_frame src_frame; + struct msm_pp_frame dest_frame; + struct msm_pp_crop crop; + int path; +}; + +struct msm_cam_evt_divert_frame { + unsigned short image_mode; + unsigned short op_mode; + unsigned short inst_idx; + unsigned short node_idx; + struct msm_pp_frame frame; + int do_pp; +}; + +struct msm_mctl_pp_cmd_ack_event { + uint32_t cmd; /* VPE_CMD_ZOOM? */ + int status; /* 0 done, < 0 err */ + uint32_t cookie; /* daemon's cookie */ +}; + +struct msm_mctl_pp_event_info { + int32_t event; + union { + struct msm_mctl_pp_cmd_ack_event ack; + }; +}; + +struct msm_isp_event_ctrl { + unsigned short resptype; + union { + struct msm_cam_evt_msg isp_msg; + struct msm_ctrl_cmd ctrl; + struct msm_cam_evt_divert_frame div_frame; + struct msm_mctl_pp_event_info pp_event_info; + } isp_data; +}; + +#define MSM_CAM_RESP_CTRL 0 +#define MSM_CAM_RESP_STAT_EVT_MSG 1 +#define MSM_CAM_RESP_STEREO_OP_1 2 +#define MSM_CAM_RESP_STEREO_OP_2 3 +#define MSM_CAM_RESP_V4L2 4 +#define MSM_CAM_RESP_DIV_FRAME_EVT_MSG 5 +#define MSM_CAM_RESP_DONE_EVENT 6 +#define MSM_CAM_RESP_MCTL_PP_EVENT 7 +#define MSM_CAM_RESP_MAX 8 + +#define MSM_CAM_APP_NOTIFY_EVENT 0 +#define MSM_CAM_APP_NOTIFY_ERROR_EVENT 1 + +/* this one is used to send ctrl/status up to config thread */ + +struct msm_stats_event_ctrl { + /* 0 - ctrl_cmd from control thread, + * 1 - stats/event kernel, + * 2 - V4L control or read request */ + int resptype; + int timeout_ms; + struct msm_ctrl_cmd ctrl_cmd; + /* struct vfe_event_t stats_event; */ + struct msm_cam_evt_msg stats_event; +}; + +/* 2. config command: config command(from config thread); */ +struct msm_camera_cfg_cmd { + /* what to config: + * 1 - sensor config, 2 - vfe config */ + uint16_t cfg_type; + + /* sensor config type */ + uint16_t cmd_type; + uint16_t queue; + uint16_t length; + void *value; +}; + +#define CMD_GENERAL 0 +#define CMD_AXI_CFG_OUT1 1 +#define CMD_AXI_CFG_SNAP_O1_AND_O2 2 +#define CMD_AXI_CFG_OUT2 3 +#define CMD_PICT_T_AXI_CFG 4 +#define CMD_PICT_M_AXI_CFG 5 +#define CMD_RAW_PICT_AXI_CFG 6 + +#define CMD_FRAME_BUF_RELEASE 7 +#define CMD_PREV_BUF_CFG 8 +#define CMD_SNAP_BUF_RELEASE 9 +#define CMD_SNAP_BUF_CFG 10 +#define CMD_STATS_DISABLE 11 +#define CMD_STATS_AEC_AWB_ENABLE 12 +#define CMD_STATS_AF_ENABLE 13 +#define CMD_STATS_AEC_ENABLE 14 +#define CMD_STATS_AWB_ENABLE 15 +#define CMD_STATS_ENABLE 16 + +#define CMD_STATS_AXI_CFG 17 +#define CMD_STATS_AEC_AXI_CFG 18 +#define CMD_STATS_AF_AXI_CFG 19 +#define CMD_STATS_AWB_AXI_CFG 20 +#define CMD_STATS_RS_AXI_CFG 21 +#define CMD_STATS_CS_AXI_CFG 22 +#define CMD_STATS_IHIST_AXI_CFG 23 +#define CMD_STATS_SKIN_AXI_CFG 24 + +#define CMD_STATS_BUF_RELEASE 25 +#define CMD_STATS_AEC_BUF_RELEASE 26 +#define CMD_STATS_AF_BUF_RELEASE 27 +#define CMD_STATS_AWB_BUF_RELEASE 28 +#define CMD_STATS_RS_BUF_RELEASE 29 +#define CMD_STATS_CS_BUF_RELEASE 30 +#define CMD_STATS_IHIST_BUF_RELEASE 31 +#define CMD_STATS_SKIN_BUF_RELEASE 32 + +#define UPDATE_STATS_INVALID 33 +#define CMD_AXI_CFG_SNAP_GEMINI 34 +#define CMD_AXI_CFG_SNAP 35 +#define CMD_AXI_CFG_PREVIEW 36 +#define CMD_AXI_CFG_VIDEO 37 + +#define CMD_STATS_IHIST_ENABLE 38 +#define CMD_STATS_RS_ENABLE 39 +#define CMD_STATS_CS_ENABLE 40 +#define CMD_VPE 41 +#define CMD_AXI_CFG_VPE 42 +#define CMD_AXI_CFG_ZSL 43 +#define CMD_AXI_CFG_SNAP_VPE 44 +#define CMD_AXI_CFG_SNAP_THUMB_VPE 45 + +#define CMD_CONFIG_PING_ADDR 46 +#define CMD_CONFIG_PONG_ADDR 47 +#define CMD_CONFIG_FREE_BUF_ADDR 48 +#define CMD_AXI_CFG_ZSL_ALL_CHNLS 49 +#define CMD_AXI_CFG_VIDEO_ALL_CHNLS 50 +#define CMD_VFE_BUFFER_RELEASE 51 +#define CMD_VFE_PROCESS_IRQ 52 +#define CMD_STATS_BG_ENABLE 53 +#define CMD_STATS_BF_ENABLE 54 +#define CMD_STATS_BHIST_ENABLE 55 +#define CMD_STATS_BG_BUF_RELEASE 56 +#define CMD_STATS_BF_BUF_RELEASE 57 +#define CMD_STATS_BHIST_BUF_RELEASE 58 +#define CMD_VFE_PIX_SOF_COUNT_UPDATE 59 +#define CMD_VFE_COUNT_PIX_SOF_ENABLE 60 +#define CMD_STATS_BE_ENABLE 61 +#define CMD_STATS_BE_BUF_RELEASE 62 + +#define CMD_AXI_CFG_PRIM BIT(8) +#define CMD_AXI_CFG_PRIM_ALL_CHNLS BIT(9) +#define CMD_AXI_CFG_SEC BIT(10) +#define CMD_AXI_CFG_SEC_ALL_CHNLS BIT(11) +#define CMD_AXI_CFG_TERT1 BIT(12) +#define CMD_AXI_CFG_TERT2 BIT(13) + +#define CMD_AXI_START 0xE1 +#define CMD_AXI_STOP 0xE2 +#define CMD_AXI_RESET 0xE3 +#define CMD_AXI_ABORT 0xE4 + + + +#define AXI_CMD_PREVIEW BIT(0) +#define AXI_CMD_CAPTURE BIT(1) +#define AXI_CMD_RECORD BIT(2) +#define AXI_CMD_ZSL BIT(3) +#define AXI_CMD_RAW_CAPTURE BIT(4) +#define AXI_CMD_LIVESHOT BIT(5) + +/* vfe config command: config command(from config thread)*/ +struct msm_vfe_cfg_cmd { + int cmd_type; + uint16_t length; + void *value; +}; + +struct msm_vpe_cfg_cmd { + int cmd_type; + uint16_t length; + void *value; +}; + +#define MAX_CAMERA_ENABLE_NAME_LEN 32 +struct camera_enable_cmd { + char name[MAX_CAMERA_ENABLE_NAME_LEN]; +}; + +#define MSM_PMEM_OUTPUT1 0 +#define MSM_PMEM_OUTPUT2 1 +#define MSM_PMEM_OUTPUT1_OUTPUT2 2 +#define MSM_PMEM_THUMBNAIL 3 +#define MSM_PMEM_MAINIMG 4 +#define MSM_PMEM_RAW_MAINIMG 5 +#define MSM_PMEM_AEC_AWB 6 +#define MSM_PMEM_AF 7 +#define MSM_PMEM_AEC 8 +#define MSM_PMEM_AWB 9 +#define MSM_PMEM_RS 10 +#define MSM_PMEM_CS 11 +#define MSM_PMEM_IHIST 12 +#define MSM_PMEM_SKIN 13 +#define MSM_PMEM_VIDEO 14 +#define MSM_PMEM_PREVIEW 15 +#define MSM_PMEM_VIDEO_VPE 16 +#define MSM_PMEM_C2D 17 +#define MSM_PMEM_MAINIMG_VPE 18 +#define MSM_PMEM_THUMBNAIL_VPE 19 +#define MSM_PMEM_BAYER_GRID 20 +#define MSM_PMEM_BAYER_FOCUS 21 +#define MSM_PMEM_BAYER_HIST 22 +#define MSM_PMEM_BAYER_EXPOSURE 23 +#define MSM_PMEM_MAX 24 + +#define STAT_AEAW 0 +#define STAT_AEC 1 +#define STAT_AF 2 +#define STAT_AWB 3 +#define STAT_RS 4 +#define STAT_CS 5 +#define STAT_IHIST 6 +#define STAT_SKIN 7 +#define STAT_BG 8 +#define STAT_BF 9 +#define STAT_BE 10 +#define STAT_BHIST 11 +#define STAT_MAX 12 + +#define FRAME_PREVIEW_OUTPUT1 0 +#define FRAME_PREVIEW_OUTPUT2 1 +#define FRAME_SNAPSHOT 2 +#define FRAME_THUMBNAIL 3 +#define FRAME_RAW_SNAPSHOT 4 +#define FRAME_MAX 5 + +enum msm_stats_enum_type { + MSM_STATS_TYPE_AEC, /* legacy based AEC */ + MSM_STATS_TYPE_AF, /* legacy based AF */ + MSM_STATS_TYPE_AWB, /* legacy based AWB */ + MSM_STATS_TYPE_RS, /* legacy based RS */ + MSM_STATS_TYPE_CS, /* legacy based CS */ + MSM_STATS_TYPE_IHIST, /* legacy based HIST */ + MSM_STATS_TYPE_SKIN, /* legacy based SKIN */ + MSM_STATS_TYPE_BG, /* Bayer Grids */ + MSM_STATS_TYPE_BF, /* Bayer Focus */ + MSM_STATS_TYPE_BE, /* Bayer Exposure*/ + MSM_STATS_TYPE_BHIST, /* Bayer Hist */ + MSM_STATS_TYPE_AE_AW, /* legacy stats for vfe 2.x*/ + MSM_STATS_TYPE_COMP, /* Composite stats */ + MSM_STATS_TYPE_MAX /* MAX */ +}; + +struct msm_stats_buf_info { + int type; /* msm_stats_enum_type */ + int fd; + void *vaddr; + uint32_t offset; + uint32_t len; + uint32_t y_off; + uint32_t cbcr_off; + uint32_t planar0_off; + uint32_t planar1_off; + uint32_t planar2_off; + uint8_t active; + int buf_idx; +}; + +struct msm_pmem_info { + int type; + int fd; + void *vaddr; + uint32_t offset; + uint32_t len; + uint32_t y_off; + uint32_t cbcr_off; + uint32_t planar0_off; + uint32_t planar1_off; + uint32_t planar2_off; + uint8_t active; +}; + +struct outputCfg { + uint32_t height; + uint32_t width; + + uint32_t window_height_firstline; + uint32_t window_height_lastline; +}; + +#define VIDEO_NODE 0 +#define MCTL_NODE 1 + +#define OUTPUT_1 0 +#define OUTPUT_2 1 +#define OUTPUT_1_AND_2 2 /* snapshot only */ +#define OUTPUT_1_AND_3 3 /* video */ +#define CAMIF_TO_AXI_VIA_OUTPUT_2 4 +#define OUTPUT_1_AND_CAMIF_TO_AXI_VIA_OUTPUT_2 5 +#define OUTPUT_2_AND_CAMIF_TO_AXI_VIA_OUTPUT_1 6 +#define OUTPUT_1_2_AND_3 7 +#define OUTPUT_ALL_CHNLS 8 +#define OUTPUT_VIDEO_ALL_CHNLS 9 +#define OUTPUT_ZSL_ALL_CHNLS 10 +#define LAST_AXI_OUTPUT_MODE_ENUM OUTPUT_ZSL_ALL_CHNLS + +#define OUTPUT_PRIM BIT(8) +#define OUTPUT_PRIM_ALL_CHNLS BIT(9) +#define OUTPUT_SEC BIT(10) +#define OUTPUT_SEC_ALL_CHNLS BIT(11) +#define OUTPUT_TERT1 BIT(12) +#define OUTPUT_TERT2 BIT(13) + + + +#define MSM_FRAME_PREV_1 0 +#define MSM_FRAME_PREV_2 1 +#define MSM_FRAME_ENC 2 + +#define OUTPUT_TYPE_P BIT(0) +#define OUTPUT_TYPE_T BIT(1) +#define OUTPUT_TYPE_S BIT(2) +#define OUTPUT_TYPE_V BIT(3) +#define OUTPUT_TYPE_L BIT(4) +#define OUTPUT_TYPE_ST_L BIT(5) +#define OUTPUT_TYPE_ST_R BIT(6) +#define OUTPUT_TYPE_ST_D BIT(7) +#define OUTPUT_TYPE_R BIT(8) +#define OUTPUT_TYPE_R1 BIT(9) +#define OUTPUT_TYPE_SAEC BIT(10) +#define OUTPUT_TYPE_SAFC BIT(11) +#define OUTPUT_TYPE_SAWB BIT(12) +#define OUTPUT_TYPE_IHST BIT(13) +#define OUTPUT_TYPE_CSTA BIT(14) + +struct fd_roi_info { + void *info; + int info_len; +}; + +struct msm_mem_map_info { + uint32_t cookie; + uint32_t length; + uint32_t mem_type; +}; + +#define MSM_MEM_MMAP 0 +#define MSM_MEM_USERPTR 1 +#define MSM_PLANE_MAX 8 +#define MSM_PLANE_Y 0 +#define MSM_PLANE_UV 1 + +struct msm_frame { + struct timespec ts; + int path; + int type; + unsigned long buffer; + uint32_t phy_offset; + uint32_t y_off; + uint32_t cbcr_off; + uint32_t planar0_off; + uint32_t planar1_off; + uint32_t planar2_off; + int fd; + + void *cropinfo; + int croplen; + uint32_t error_code; + struct fd_roi_info roi_info; + uint32_t frame_id; + int stcam_quality_ind; + uint32_t stcam_conv_value; + + struct ion_allocation_data ion_alloc; + struct ion_fd_data fd_data; + int ion_dev_fd; +}; + +enum msm_st_frame_packing { + SIDE_BY_SIDE_HALF, + SIDE_BY_SIDE_FULL, + TOP_DOWN_HALF, + TOP_DOWN_FULL, +}; + +struct msm_st_crop { + uint32_t in_w; + uint32_t in_h; + uint32_t out_w; + uint32_t out_h; +}; + +struct msm_st_half { + uint32_t buf_p0_off; + uint32_t buf_p1_off; + uint32_t buf_p0_stride; + uint32_t buf_p1_stride; + uint32_t pix_x_off; + uint32_t pix_y_off; + struct msm_st_crop stCropInfo; +}; + +struct msm_st_frame { + struct msm_frame buf_info; + int type; + enum msm_st_frame_packing packing; + struct msm_st_half L; + struct msm_st_half R; + int frame_id; +}; + +#define MSM_CAMERA_ERR_MASK (0xFFFFFFFF & 1) + +struct stats_buff { + unsigned long buff; + int fd; +}; + +struct msm_stats_buf { + uint8_t awb_ymin; + struct stats_buff aec; + struct stats_buff awb; + struct stats_buff af; + struct stats_buff be; + struct stats_buff ihist; + struct stats_buff rs; + struct stats_buff cs; + struct stats_buff skin; + int type; + uint32_t status_bits; + unsigned long buffer; + int fd; + int length; + struct ion_handle *handle; + uint32_t frame_id; + int buf_idx; +}; +#define MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT 0 +/* video capture mode in VIDIOC_S_PARM */ +#define MSM_V4L2_EXT_CAPTURE_MODE_PREVIEW \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+1) +/* extendedmode for video recording in VIDIOC_S_PARM */ +#define MSM_V4L2_EXT_CAPTURE_MODE_VIDEO \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+2) +/* extendedmode for the full size main image in VIDIOC_S_PARM */ +#define MSM_V4L2_EXT_CAPTURE_MODE_MAIN (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+3) +/* extendedmode for the thumb nail image in VIDIOC_S_PARM */ +#define MSM_V4L2_EXT_CAPTURE_MODE_THUMBNAIL \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+4) +/* ISP_PIX_OUTPUT1: no pp, directly send output1 buf to user */ +#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT1 \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+5) +/* ISP_PIX_OUTPUT2: no pp, directly send output2 buf to user */ +#define MSM_V4L2_EXT_CAPTURE_MODE_ISP_PIX_OUTPUT2 \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+6) +/* raw image type */ +#define MSM_V4L2_EXT_CAPTURE_MODE_RAW \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+7) +/* RDI dump */ +#define MSM_V4L2_EXT_CAPTURE_MODE_RDI \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+8) +/* RDI dump 1 */ +#define MSM_V4L2_EXT_CAPTURE_MODE_RDI1 \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+9) +/* RDI dump 2 */ +#define MSM_V4L2_EXT_CAPTURE_MODE_RDI2 \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+10) +#define MSM_V4L2_EXT_CAPTURE_MODE_AEC \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+11) +#define MSM_V4L2_EXT_CAPTURE_MODE_AWB \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+12) +#define MSM_V4L2_EXT_CAPTURE_MODE_AF \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+13) +#define MSM_V4L2_EXT_CAPTURE_MODE_IHIST \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+14) +#define MSM_V4L2_EXT_CAPTURE_MODE_CS \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+15) +#define MSM_V4L2_EXT_CAPTURE_MODE_RS \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+16) +#define MSM_V4L2_EXT_CAPTURE_MODE_CSTA \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+17) +#define MSM_V4L2_EXT_CAPTURE_MODE_V2X_LIVESHOT \ + (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+18) +#define MSM_V4L2_EXT_CAPTURE_MODE_MAX (MSM_V4L2_EXT_CAPTURE_MODE_DEFAULT+19) + + +#define MSM_V4L2_PID_MOTION_ISO V4L2_CID_PRIVATE_BASE +#define MSM_V4L2_PID_EFFECT (V4L2_CID_PRIVATE_BASE+1) +#define MSM_V4L2_PID_HJR (V4L2_CID_PRIVATE_BASE+2) +#define MSM_V4L2_PID_LED_MODE (V4L2_CID_PRIVATE_BASE+3) +#define MSM_V4L2_PID_PREP_SNAPSHOT (V4L2_CID_PRIVATE_BASE+4) +#define MSM_V4L2_PID_EXP_METERING (V4L2_CID_PRIVATE_BASE+5) +#define MSM_V4L2_PID_ISO (V4L2_CID_PRIVATE_BASE+6) +#define MSM_V4L2_PID_CAM_MODE (V4L2_CID_PRIVATE_BASE+7) +#define MSM_V4L2_PID_LUMA_ADAPTATION (V4L2_CID_PRIVATE_BASE+8) +#define MSM_V4L2_PID_BEST_SHOT (V4L2_CID_PRIVATE_BASE+9) +#define MSM_V4L2_PID_FOCUS_MODE (V4L2_CID_PRIVATE_BASE+10) +#define MSM_V4L2_PID_BL_DETECTION (V4L2_CID_PRIVATE_BASE+11) +#define MSM_V4L2_PID_SNOW_DETECTION (V4L2_CID_PRIVATE_BASE+12) +#define MSM_V4L2_PID_CTRL_CMD (V4L2_CID_PRIVATE_BASE+13) +#define MSM_V4L2_PID_EVT_SUB_INFO (V4L2_CID_PRIVATE_BASE+14) +#define MSM_V4L2_PID_STROBE_FLASH (V4L2_CID_PRIVATE_BASE+15) +#define MSM_V4L2_PID_INST_HANDLE (V4L2_CID_PRIVATE_BASE+16) +#define MSM_V4L2_PID_MMAP_INST (V4L2_CID_PRIVATE_BASE+17) +#define MSM_V4L2_PID_PP_PLANE_INFO (V4L2_CID_PRIVATE_BASE+18) +#define MSM_V4L2_PID_MAX MSM_V4L2_PID_PP_PLANE_INFO + +/* camera operation mode for video recording - two frame output queues */ +#define MSM_V4L2_CAM_OP_DEFAULT 0 +/* camera operation mode for video recording - two frame output queues */ +#define MSM_V4L2_CAM_OP_PREVIEW (MSM_V4L2_CAM_OP_DEFAULT+1) +/* camera operation mode for video recording - two frame output queues */ +#define MSM_V4L2_CAM_OP_VIDEO (MSM_V4L2_CAM_OP_DEFAULT+2) +/* camera operation mode for standard shapshot - two frame output queues */ +#define MSM_V4L2_CAM_OP_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+3) +/* camera operation mode for zsl shapshot - three output queues */ +#define MSM_V4L2_CAM_OP_ZSL (MSM_V4L2_CAM_OP_DEFAULT+4) +/* camera operation mode for raw snapshot - one frame output queue */ +#define MSM_V4L2_CAM_OP_RAW (MSM_V4L2_CAM_OP_DEFAULT+5) +/* camera operation mode for jpeg snapshot - one frame output queue */ +#define MSM_V4L2_CAM_OP_JPEG_CAPTURE (MSM_V4L2_CAM_OP_DEFAULT+6) + + +#define MSM_V4L2_VID_CAP_TYPE 0 +#define MSM_V4L2_STREAM_ON 1 +#define MSM_V4L2_STREAM_OFF 2 +#define MSM_V4L2_SNAPSHOT 3 +#define MSM_V4L2_QUERY_CTRL 4 +#define MSM_V4L2_GET_CTRL 5 +#define MSM_V4L2_SET_CTRL 6 +#define MSM_V4L2_QUERY 7 +#define MSM_V4L2_GET_CROP 8 +#define MSM_V4L2_SET_CROP 9 +#define MSM_V4L2_OPEN 10 +#define MSM_V4L2_CLOSE 11 +#define MSM_V4L2_SET_CTRL_CMD 12 +#define MSM_V4L2_EVT_SUB_MASK 13 +#define MSM_V4L2_PRIVATE_CMD 14 +#define MSM_V4L2_MAX 15 +#define V4L2_CAMERA_EXIT 43 + +struct crop_info { + void *info; + int len; +}; + +struct msm_postproc { + int ftnum; + struct msm_frame fthumnail; + int fmnum; + struct msm_frame fmain; +}; + +struct msm_snapshot_pp_status { + void *status; +}; + +#define CFG_SET_MODE 0 +#define CFG_SET_EFFECT 1 +#define CFG_START 2 +#define CFG_PWR_UP 3 +#define CFG_PWR_DOWN 4 +#define CFG_WRITE_EXPOSURE_GAIN 5 +#define CFG_SET_DEFAULT_FOCUS 6 +#define CFG_MOVE_FOCUS 7 +#define CFG_REGISTER_TO_REAL_GAIN 8 +#define CFG_REAL_TO_REGISTER_GAIN 9 +#define CFG_SET_FPS 10 +#define CFG_SET_PICT_FPS 11 +#define CFG_SET_BRIGHTNESS 12 +#define CFG_SET_CONTRAST 13 +#define CFG_SET_ZOOM 14 +#define CFG_SET_EXPOSURE_MODE 15 +#define CFG_SET_WB 16 +#define CFG_SET_ANTIBANDING 17 +#define CFG_SET_EXP_GAIN 18 +#define CFG_SET_PICT_EXP_GAIN 19 +#define CFG_SET_LENS_SHADING 20 +#define CFG_GET_PICT_FPS 21 +#define CFG_GET_PREV_L_PF 22 +#define CFG_GET_PREV_P_PL 23 +#define CFG_GET_PICT_L_PF 24 +#define CFG_GET_PICT_P_PL 25 +#define CFG_GET_AF_MAX_STEPS 26 +#define CFG_GET_PICT_MAX_EXP_LC 27 +#define CFG_SEND_WB_INFO 28 +#define CFG_SENSOR_INIT 29 +#define CFG_GET_3D_CALI_DATA 30 +#define CFG_GET_CALIB_DATA 31 +#define CFG_GET_OUTPUT_INFO 32 +#define CFG_GET_EEPROM_INFO 33 +#define CFG_GET_EEPROM_DATA 34 +#define CFG_SET_ACTUATOR_INFO 35 +#define CFG_GET_ACTUATOR_INFO 36 +/* TBD: QRD */ +#define CFG_SET_SATURATION 37 +#define CFG_SET_SHARPNESS 38 +#define CFG_SET_TOUCHAEC 39 +#define CFG_SET_AUTO_FOCUS 40 +#define CFG_SET_AUTOFLASH 41 +#define CFG_SET_EXPOSURE_COMPENSATION 42 +#define CFG_SET_ISO 43 +#define CFG_START_STREAM 44 +#define CFG_STOP_STREAM 45 +#define CFG_GET_CSI_PARAMS 46 +#define CFG_POWER_UP 47 +#define CFG_POWER_DOWN 48 +#define CFG_WRITE_I2C_ARRAY 49 +#define CFG_READ_I2C_ARRAY 50 +#define CFG_PCLK_CHANGE 51 +#define CFG_CONFIG_VREG_ARRAY 52 +#define CFG_CONFIG_CLK_ARRAY 53 +#define CFG_GPIO_OP 54 +#define CFG_MAX 55 + + +#define MOVE_NEAR 0 +#define MOVE_FAR 1 + +#define SENSOR_PREVIEW_MODE 0 +#define SENSOR_SNAPSHOT_MODE 1 +#define SENSOR_RAW_SNAPSHOT_MODE 2 +#define SENSOR_HFR_60FPS_MODE 3 +#define SENSOR_HFR_90FPS_MODE 4 +#define SENSOR_HFR_120FPS_MODE 5 + +#define SENSOR_QTR_SIZE 0 +#define SENSOR_FULL_SIZE 1 +#define SENSOR_QVGA_SIZE 2 +#define SENSOR_INVALID_SIZE 3 + +#define CAMERA_EFFECT_OFF 0 +#define CAMERA_EFFECT_MONO 1 +#define CAMERA_EFFECT_NEGATIVE 2 +#define CAMERA_EFFECT_SOLARIZE 3 +#define CAMERA_EFFECT_SEPIA 4 +#define CAMERA_EFFECT_POSTERIZE 5 +#define CAMERA_EFFECT_WHITEBOARD 6 +#define CAMERA_EFFECT_BLACKBOARD 7 +#define CAMERA_EFFECT_AQUA 8 +#define CAMERA_EFFECT_EMBOSS 9 +#define CAMERA_EFFECT_SKETCH 10 +#define CAMERA_EFFECT_NEON 11 +#define CAMERA_EFFECT_FADED 12 +#define CAMERA_EFFECT_VINTAGECOOL 13 +#define CAMERA_EFFECT_VINTAGEWARM 14 +#define CAMERA_EFFECT_ACCENT_BLUE 15 +#define CAMERA_EFFECT_ACCENT_GREEN 16 +#define CAMERA_EFFECT_ACCENT_ORANGE 17 +#define CAMERA_EFFECT_MAX 18 + +/* QRD */ +#define CAMERA_EFFECT_BW 10 +#define CAMERA_EFFECT_BLUISH 12 +#define CAMERA_EFFECT_REDDISH 13 +#define CAMERA_EFFECT_GREENISH 14 + +/* QRD */ +#define CAMERA_ANTIBANDING_OFF 0 +#define CAMERA_ANTIBANDING_50HZ 2 +#define CAMERA_ANTIBANDING_60HZ 1 +#define CAMERA_ANTIBANDING_AUTO 3 + +#define CAMERA_CONTRAST_LV0 0 +#define CAMERA_CONTRAST_LV1 1 +#define CAMERA_CONTRAST_LV2 2 +#define CAMERA_CONTRAST_LV3 3 +#define CAMERA_CONTRAST_LV4 4 +#define CAMERA_CONTRAST_LV5 5 +#define CAMERA_CONTRAST_LV6 6 +#define CAMERA_CONTRAST_LV7 7 +#define CAMERA_CONTRAST_LV8 8 +#define CAMERA_CONTRAST_LV9 9 + +#define CAMERA_BRIGHTNESS_LV0 0 +#define CAMERA_BRIGHTNESS_LV1 1 +#define CAMERA_BRIGHTNESS_LV2 2 +#define CAMERA_BRIGHTNESS_LV3 3 +#define CAMERA_BRIGHTNESS_LV4 4 +#define CAMERA_BRIGHTNESS_LV5 5 +#define CAMERA_BRIGHTNESS_LV6 6 +#define CAMERA_BRIGHTNESS_LV7 7 +#define CAMERA_BRIGHTNESS_LV8 8 + + +#define CAMERA_SATURATION_LV0 0 +#define CAMERA_SATURATION_LV1 1 +#define CAMERA_SATURATION_LV2 2 +#define CAMERA_SATURATION_LV3 3 +#define CAMERA_SATURATION_LV4 4 +#define CAMERA_SATURATION_LV5 5 +#define CAMERA_SATURATION_LV6 6 +#define CAMERA_SATURATION_LV7 7 +#define CAMERA_SATURATION_LV8 8 + +#define CAMERA_SHARPNESS_LV0 0 +#define CAMERA_SHARPNESS_LV1 3 +#define CAMERA_SHARPNESS_LV2 6 +#define CAMERA_SHARPNESS_LV3 9 +#define CAMERA_SHARPNESS_LV4 12 +#define CAMERA_SHARPNESS_LV5 15 +#define CAMERA_SHARPNESS_LV6 18 +#define CAMERA_SHARPNESS_LV7 21 +#define CAMERA_SHARPNESS_LV8 24 +#define CAMERA_SHARPNESS_LV9 27 +#define CAMERA_SHARPNESS_LV10 30 + +#define CAMERA_SETAE_AVERAGE 0 +#define CAMERA_SETAE_CENWEIGHT 1 + +#define CAMERA_WB_AUTO 1 /* This list must match aeecamera.h */ +#define CAMERA_WB_CUSTOM 2 +#define CAMERA_WB_INCANDESCENT 3 +#define CAMERA_WB_FLUORESCENT 4 +#define CAMERA_WB_DAYLIGHT 5 +#define CAMERA_WB_CLOUDY_DAYLIGHT 6 +#define CAMERA_WB_TWILIGHT 7 +#define CAMERA_WB_SHADE 8 + +#define CAMERA_EXPOSURE_COMPENSATION_LV0 12 +#define CAMERA_EXPOSURE_COMPENSATION_LV1 6 +#define CAMERA_EXPOSURE_COMPENSATION_LV2 0 +#define CAMERA_EXPOSURE_COMPENSATION_LV3 -6 +#define CAMERA_EXPOSURE_COMPENSATION_LV4 -12 + +enum msm_v4l2_saturation_level { + MSM_V4L2_SATURATION_L0, + MSM_V4L2_SATURATION_L1, + MSM_V4L2_SATURATION_L2, + MSM_V4L2_SATURATION_L3, + MSM_V4L2_SATURATION_L4, + MSM_V4L2_SATURATION_L5, + MSM_V4L2_SATURATION_L6, + MSM_V4L2_SATURATION_L7, + MSM_V4L2_SATURATION_L8, + MSM_V4L2_SATURATION_L9, + MSM_V4L2_SATURATION_L10, +}; + +enum msm_v4l2_contrast_level { + MSM_V4L2_CONTRAST_L0, + MSM_V4L2_CONTRAST_L1, + MSM_V4L2_CONTRAST_L2, + MSM_V4L2_CONTRAST_L3, + MSM_V4L2_CONTRAST_L4, + MSM_V4L2_CONTRAST_L5, + MSM_V4L2_CONTRAST_L6, + MSM_V4L2_CONTRAST_L7, + MSM_V4L2_CONTRAST_L8, + MSM_V4L2_CONTRAST_L9, + MSM_V4L2_CONTRAST_L10, +}; + + +enum msm_v4l2_exposure_level { + MSM_V4L2_EXPOSURE_N2, + MSM_V4L2_EXPOSURE_N1, + MSM_V4L2_EXPOSURE_D, + MSM_V4L2_EXPOSURE_P1, + MSM_V4L2_EXPOSURE_P2, +}; + +enum msm_v4l2_sharpness_level { + MSM_V4L2_SHARPNESS_L0, + MSM_V4L2_SHARPNESS_L1, + MSM_V4L2_SHARPNESS_L2, + MSM_V4L2_SHARPNESS_L3, + MSM_V4L2_SHARPNESS_L4, + MSM_V4L2_SHARPNESS_L5, + MSM_V4L2_SHARPNESS_L6, +}; + +enum msm_v4l2_expo_metering_mode { + MSM_V4L2_EXP_FRAME_AVERAGE, + MSM_V4L2_EXP_CENTER_WEIGHTED, + MSM_V4L2_EXP_SPOT_METERING, +}; + +enum msm_v4l2_iso_mode { + MSM_V4L2_ISO_AUTO = 0, + MSM_V4L2_ISO_DEBLUR, + MSM_V4L2_ISO_100, + MSM_V4L2_ISO_200, + MSM_V4L2_ISO_400, + MSM_V4L2_ISO_800, + MSM_V4L2_ISO_1600, +}; + +enum msm_v4l2_wb_mode { + MSM_V4L2_WB_OFF, + MSM_V4L2_WB_AUTO , + MSM_V4L2_WB_CUSTOM, + MSM_V4L2_WB_INCANDESCENT, + MSM_V4L2_WB_FLUORESCENT, + MSM_V4L2_WB_DAYLIGHT, + MSM_V4L2_WB_CLOUDY_DAYLIGHT, +}; + +enum msm_v4l2_special_effect { + MSM_V4L2_EFFECT_OFF, + MSM_V4L2_EFFECT_MONO, + MSM_V4L2_EFFECT_NEGATIVE, + MSM_V4L2_EFFECT_SOLARIZE, + MSM_V4L2_EFFECT_SEPIA, + MSM_V4L2_EFFECT_POSTERAIZE, + MSM_V4L2_EFFECT_WHITEBOARD, + MSM_V4L2_EFFECT_BLACKBOARD, + MSM_V4L2_EFFECT_AQUA, + MSM_V4L2_EFFECT_EMBOSS, + MSM_V4L2_EFFECT_SKETCH, + MSM_V4L2_EFFECT_NEON, + MSM_V4L2_EFFECT_MAX, +}; + +enum msm_v4l2_power_line_frequency { + MSM_V4L2_POWER_LINE_OFF, + MSM_V4L2_POWER_LINE_60HZ, + MSM_V4L2_POWER_LINE_50HZ, + MSM_V4L2_POWER_LINE_AUTO, +}; + +#define CAMERA_ISO_TYPE_AUTO 0 +#define CAMEAR_ISO_TYPE_HJR 1 +#define CAMEAR_ISO_TYPE_100 2 +#define CAMERA_ISO_TYPE_200 3 +#define CAMERA_ISO_TYPE_400 4 +#define CAMEAR_ISO_TYPE_800 5 +#define CAMERA_ISO_TYPE_1600 6 + +struct sensor_pict_fps { + uint16_t prevfps; + uint16_t pictfps; +}; + +struct exp_gain_cfg { + uint16_t gain; + uint32_t line; +}; + +struct focus_cfg { + int32_t steps; + int dir; +}; + +struct fps_cfg { + uint16_t f_mult; + uint16_t fps_div; + uint32_t pict_fps_div; +}; +struct wb_info_cfg { + uint16_t red_gain; + uint16_t green_gain; + uint16_t blue_gain; +}; +struct sensor_3d_exp_cfg { + uint16_t gain; + uint32_t line; + uint16_t r_gain; + uint16_t b_gain; + uint16_t gr_gain; + uint16_t gb_gain; + uint16_t gain_adjust; +}; +struct sensor_3d_cali_data_t{ + unsigned char left_p_matrix[3][4][8]; + unsigned char right_p_matrix[3][4][8]; + unsigned char square_len[8]; + unsigned char focal_len[8]; + unsigned char pixel_pitch[8]; + uint16_t left_r; + uint16_t left_b; + uint16_t left_gb; + uint16_t left_af_far; + uint16_t left_af_mid; + uint16_t left_af_short; + uint16_t left_af_5um; + uint16_t left_af_50up; + uint16_t left_af_50down; + uint16_t right_r; + uint16_t right_b; + uint16_t right_gb; + uint16_t right_af_far; + uint16_t right_af_mid; + uint16_t right_af_short; + uint16_t right_af_5um; + uint16_t right_af_50up; + uint16_t right_af_50down; +}; +struct sensor_init_cfg { + uint8_t prev_res; + uint8_t pict_res; +}; + +struct sensor_calib_data { + /* Color Related Measurements */ + uint16_t r_over_g; + uint16_t b_over_g; + uint16_t gr_over_gb; + + /* Lens Related Measurements */ + uint16_t macro_2_inf; + uint16_t inf_2_macro; + uint16_t stroke_amt; + uint16_t af_pos_1m; + uint16_t af_pos_inf; +}; + +enum msm_sensor_resolution_t { + MSM_SENSOR_RES_FULL, + MSM_SENSOR_RES_QTR, + MSM_SENSOR_RES_2, + MSM_SENSOR_RES_3, + MSM_SENSOR_RES_4, + MSM_SENSOR_RES_5, + MSM_SENSOR_RES_6, + MSM_SENSOR_RES_7, + MSM_SENSOR_INVALID_RES, +}; + +struct msm_sensor_output_info_t { + uint16_t x_output; + uint16_t y_output; + uint16_t line_length_pclk; + uint16_t frame_length_lines; + uint32_t vt_pixel_clk; + uint32_t op_pixel_clk; + uint16_t binning_factor; +}; + +struct sensor_output_info_t { + struct msm_sensor_output_info_t *output_info; + uint16_t num_info; +}; + +struct msm_sensor_exp_gain_info_t { + uint16_t coarse_int_time_addr; + uint16_t global_gain_addr; + uint16_t vert_offset; +}; + +struct msm_sensor_output_reg_addr_t { + uint16_t x_output; + uint16_t y_output; + uint16_t line_length_pclk; + uint16_t frame_length_lines; +}; + +struct sensor_driver_params_type { + struct msm_camera_i2c_reg_setting *init_settings; + uint16_t init_settings_size; + struct msm_camera_i2c_reg_setting *mode_settings; + uint16_t mode_settings_size; + struct msm_sensor_output_reg_addr_t *sensor_output_reg_addr; + struct msm_camera_i2c_reg_setting *start_settings; + struct msm_camera_i2c_reg_setting *stop_settings; + struct msm_camera_i2c_reg_setting *groupon_settings; + struct msm_camera_i2c_reg_setting *groupoff_settings; + struct msm_sensor_exp_gain_info_t *sensor_exp_gain_info; + struct msm_sensor_output_info_t *output_info; +}; + +struct mirror_flip { + int32_t x_mirror; + int32_t y_flip; +}; + +struct cord { + uint32_t x; + uint32_t y; +}; + +struct msm_eeprom_data_t { + void *eeprom_data; + uint16_t index; +}; + +struct msm_camera_csid_vc_cfg { + uint8_t cid; + uint8_t dt; + uint8_t decode_format; +}; + +struct csi_lane_params_t { + uint16_t csi_lane_assign; + uint8_t csi_lane_mask; + uint8_t csi_if; + uint8_t csid_core[2]; + uint8_t csi_phy_sel; +}; + +struct msm_camera_csid_lut_params { + uint8_t num_cid; + struct msm_camera_csid_vc_cfg *vc_cfg; +}; + +struct msm_camera_csid_params { + uint8_t lane_cnt; + uint16_t lane_assign; + uint8_t phy_sel; + struct msm_camera_csid_lut_params lut_params; +}; + +struct msm_camera_csiphy_params { + uint8_t lane_cnt; + uint8_t settle_cnt; + uint16_t lane_mask; + uint8_t combo_mode; + uint8_t csid_core; + uint64_t data_rate; +}; + +struct msm_camera_csi2_params { + struct msm_camera_csid_params csid_params; + struct msm_camera_csiphy_params csiphy_params; +}; + +enum msm_camera_csi_data_format { + CSI_8BIT, + CSI_10BIT, + CSI_12BIT, +}; + +struct msm_camera_csi_params { + enum msm_camera_csi_data_format data_format; + uint8_t lane_cnt; + uint8_t lane_assign; + uint8_t settle_cnt; + uint8_t dpcm_scheme; +}; + +enum csic_cfg_type_t { + CSIC_INIT, + CSIC_CFG, +}; + +struct csic_cfg_data { + enum csic_cfg_type_t cfgtype; + struct msm_camera_csi_params *csic_params; +}; + +enum csid_cfg_type_t { + CSID_INIT, + CSID_CFG, +}; + +struct csid_cfg_data { + enum csid_cfg_type_t cfgtype; + union { + uint32_t csid_version; + struct msm_camera_csid_params *csid_params; + } cfg; +}; + +enum csiphy_cfg_type_t { + CSIPHY_INIT, + CSIPHY_CFG, +}; + +struct csiphy_cfg_data { + enum csiphy_cfg_type_t cfgtype; + struct msm_camera_csiphy_params *csiphy_params; +}; + +#define CSI_EMBED_DATA 0x12 +#define CSI_RESERVED_DATA_0 0x13 +#define CSI_YUV422_8 0x1E +#define CSI_RAW8 0x2A +#define CSI_RAW10 0x2B +#define CSI_RAW12 0x2C + +#define CSI_DECODE_6BIT 0 +#define CSI_DECODE_8BIT 1 +#define CSI_DECODE_10BIT 2 +#define CSI_DECODE_DPCM_10_8_10 5 + +#define ISPIF_STREAM(intf, action, vfe) (((intf)<<ISPIF_S_STREAM_SHIFT)+\ + (action)+((vfe)<<ISPIF_VFE_INTF_SHIFT)) +#define ISPIF_ON_FRAME_BOUNDARY (0x01 << 0) +#define ISPIF_OFF_FRAME_BOUNDARY (0x01 << 1) +#define ISPIF_OFF_IMMEDIATELY (0x01 << 2) +#define ISPIF_S_STREAM_SHIFT 4 +#define ISPIF_VFE_INTF_SHIFT 12 + +#define PIX_0 (0x01 << 0) +#define RDI_0 (0x01 << 1) +#define PIX_1 (0x01 << 2) +#define RDI_1 (0x01 << 3) +#define RDI_2 (0x01 << 4) + +enum msm_ispif_vfe_intf { + VFE0, + VFE1, + VFE_MAX, +}; + +enum msm_ispif_intftype { + PIX0, + RDI0, + PIX1, + RDI1, + RDI2, + INTF_MAX, +}; + +enum msm_ispif_vc { + VC0, + VC1, + VC2, + VC3, +}; + +enum msm_ispif_cid { + CID0, + CID1, + CID2, + CID3, + CID4, + CID5, + CID6, + CID7, + CID8, + CID9, + CID10, + CID11, + CID12, + CID13, + CID14, + CID15, +}; + +struct msm_ispif_params { + uint8_t intftype; + uint16_t cid_mask; + uint8_t csid; + uint8_t vfe_intf; +}; + +struct msm_ispif_params_list { + uint32_t len; + struct msm_ispif_params params[4]; +}; + +enum ispif_cfg_type_t { + ISPIF_INIT, + ISPIF_SET_CFG, + ISPIF_SET_ON_FRAME_BOUNDARY, + ISPIF_SET_OFF_FRAME_BOUNDARY, + ISPIF_SET_OFF_IMMEDIATELY, + ISPIF_RELEASE, +}; + +struct ispif_cfg_data { + enum ispif_cfg_type_t cfgtype; + union { + uint32_t csid_version; + int cmd; + struct msm_ispif_params_list ispif_params; + } cfg; +}; + +enum msm_camera_i2c_reg_addr_type { + MSM_CAMERA_I2C_BYTE_ADDR = 1, + MSM_CAMERA_I2C_WORD_ADDR, + MSM_CAMERA_I2C_3B_ADDR, + MSM_CAMERA_I2C_DWORD_ADDR, +}; +#define MSM_CAMERA_I2C_DWORD_ADDR MSM_CAMERA_I2C_DWORD_ADDR + +struct msm_camera_i2c_reg_array { + uint16_t reg_addr; + uint16_t reg_data; +}; + +enum msm_camera_i2c_data_type { + MSM_CAMERA_I2C_BYTE_DATA = 1, + MSM_CAMERA_I2C_WORD_DATA, + MSM_CAMERA_I2C_SET_BYTE_MASK, + MSM_CAMERA_I2C_UNSET_BYTE_MASK, + MSM_CAMERA_I2C_SET_WORD_MASK, + MSM_CAMERA_I2C_UNSET_WORD_MASK, + MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA, +}; + +struct msm_camera_i2c_reg_setting { + struct msm_camera_i2c_reg_array *reg_setting; + uint16_t size; + enum msm_camera_i2c_reg_addr_type addr_type; + enum msm_camera_i2c_data_type data_type; + uint16_t delay; +}; + +enum oem_setting_type { + I2C_READ = 1, + I2C_WRITE, + GPIO_OP, + EEPROM_READ, + VREG_SET, + CLK_SET, +}; + +struct sensor_oem_setting { + enum oem_setting_type type; + void *data; +}; + +enum camera_vreg_type { + REG_LDO, + REG_VS, + REG_GPIO, +}; + +enum msm_camera_vreg_name_t { + CAM_VDIG, + CAM_VIO, + CAM_VANA, + CAM_VAF, + CAM_VREG_MAX, +}; + +struct msm_camera_csi_lane_params { + uint16_t csi_lane_assign; + uint16_t csi_lane_mask; +}; + +struct camera_vreg_t { + const char *reg_name; + int min_voltage; + int max_voltage; + int op_mode; + uint32_t delay; +}; + +struct msm_camera_vreg_setting { + struct camera_vreg_t *cam_vreg; + uint16_t num_vreg; + uint8_t enable; +}; + +struct msm_cam_clk_info { + const char *clk_name; + long clk_rate; + uint32_t delay; +}; + +struct msm_cam_clk_setting { + struct msm_cam_clk_info *clk_info; + uint16_t num_clk_info; + uint8_t enable; +}; + +struct sensor_cfg_data { + int cfgtype; + int mode; + int rs; + uint8_t max_steps; + + union { + int8_t effect; + uint8_t lens_shading; + uint16_t prevl_pf; + uint16_t prevp_pl; + uint16_t pictl_pf; + uint16_t pictp_pl; + uint32_t pict_max_exp_lc; + uint16_t p_fps; + uint8_t iso_type; + struct sensor_init_cfg init_info; + struct sensor_pict_fps gfps; + struct exp_gain_cfg exp_gain; + struct focus_cfg focus; + struct fps_cfg fps; + struct wb_info_cfg wb_info; + struct sensor_3d_exp_cfg sensor_3d_exp; + struct sensor_calib_data calib_info; + struct sensor_output_info_t output_info; + struct msm_eeprom_data_t eeprom_data; + struct csi_lane_params_t csi_lane_params; + /* QRD */ + uint16_t antibanding; + uint8_t contrast; + uint8_t saturation; + uint8_t sharpness; + int8_t brightness; + int ae_mode; + uint8_t wb_val; + int8_t exp_compensation; + uint32_t pclk; + struct cord aec_cord; + int is_autoflash; + struct mirror_flip mirror_flip; + void *setting; + } cfg; +}; + +enum gpio_operation_type { + GPIO_REQUEST, + GPIO_FREE, + GPIO_SET_DIRECTION_OUTPUT, + GPIO_SET_DIRECTION_INPUT, + GPIO_GET_VALUE, + GPIO_SET_VALUE, +}; + +struct msm_cam_gpio_operation { + enum gpio_operation_type op_type; + unsigned address; + int value; + const char *tag; +}; + +struct damping_params_t { + uint32_t damping_step; + uint32_t damping_delay; + uint32_t hw_params; +}; + +enum actuator_type { + ACTUATOR_VCM, + ACTUATOR_PIEZO, + ACTUATOR_HVCM, + ACTUATOR_BIVCM, +}; + +enum msm_actuator_data_type { + MSM_ACTUATOR_BYTE_DATA = 1, + MSM_ACTUATOR_WORD_DATA, +}; + +enum msm_actuator_addr_type { + MSM_ACTUATOR_BYTE_ADDR = 1, + MSM_ACTUATOR_WORD_ADDR, +}; + +enum msm_actuator_write_type { + MSM_ACTUATOR_WRITE_HW_DAMP, + MSM_ACTUATOR_WRITE_DAC, + MSM_ACTUATOR_WRITE, + MSM_ACTUATOR_WRITE_DIR_REG, + MSM_ACTUATOR_POLL, + MSM_ACTUATOR_READ_WRITE, +}; + +struct msm_actuator_reg_params_t { + enum msm_actuator_write_type reg_write_type; + uint32_t hw_mask; + uint16_t reg_addr; + uint16_t hw_shift; + uint16_t data_type; + uint16_t addr_type; + uint16_t reg_data; + uint16_t delay; +}; + +struct reg_settings_t { + uint16_t reg_addr; + uint16_t reg_data; +}; + +struct region_params_t { + /* [0] = ForwardDirection Macro boundary + [1] = ReverseDirection Inf boundary + */ + uint16_t step_bound[2]; + uint16_t code_per_step; +}; + +struct msm_actuator_move_params_t { + int8_t dir; + int8_t sign_dir; + int16_t dest_step_pos; + int32_t num_steps; + struct damping_params_t *ringing_params; +}; + +struct msm_actuator_tuning_params_t { + int16_t initial_code; + uint16_t pwd_step; + uint16_t region_size; + uint32_t total_steps; + struct region_params_t *region_params; +}; + +struct msm_actuator_params_t { + enum actuator_type act_type; + uint8_t reg_tbl_size; + uint16_t data_size; + uint16_t init_setting_size; + uint32_t i2c_addr; + enum msm_actuator_addr_type i2c_addr_type; + enum msm_actuator_data_type i2c_data_type; + struct msm_actuator_reg_params_t *reg_tbl_params; + struct reg_settings_t *init_settings; +}; + +struct msm_actuator_set_info_t { + struct msm_actuator_params_t actuator_params; + struct msm_actuator_tuning_params_t af_tuning_params; +}; + +struct msm_actuator_get_info_t { + uint32_t focal_length_num; + uint32_t focal_length_den; + uint32_t f_number_num; + uint32_t f_number_den; + uint32_t f_pix_num; + uint32_t f_pix_den; + uint32_t total_f_dist_num; + uint32_t total_f_dist_den; + uint32_t hor_view_angle_num; + uint32_t hor_view_angle_den; + uint32_t ver_view_angle_num; + uint32_t ver_view_angle_den; +}; + +enum af_camera_name { + ACTUATOR_MAIN_CAM_0, + ACTUATOR_MAIN_CAM_1, + ACTUATOR_MAIN_CAM_2, + ACTUATOR_MAIN_CAM_3, + ACTUATOR_MAIN_CAM_4, + ACTUATOR_MAIN_CAM_5, + ACTUATOR_WEB_CAM_0, + ACTUATOR_WEB_CAM_1, + ACTUATOR_WEB_CAM_2, +}; + +struct msm_actuator_cfg_data { + int cfgtype; + uint8_t is_af_supported; + union { + struct msm_actuator_move_params_t move; + struct msm_actuator_set_info_t set_info; + struct msm_actuator_get_info_t get_info; + enum af_camera_name cam_name; + } cfg; +}; + +struct msm_eeprom_support { + uint16_t is_supported; + uint16_t size; + uint16_t index; + uint16_t qvalue; +}; + +struct msm_calib_wb { + uint16_t r_over_g; + uint16_t b_over_g; + uint16_t gr_over_gb; +}; + +struct msm_calib_af { + uint16_t macro_dac; + uint16_t inf_dac; + uint16_t start_dac; +}; + +struct msm_calib_lsc { + uint16_t r_gain[221]; + uint16_t b_gain[221]; + uint16_t gr_gain[221]; + uint16_t gb_gain[221]; +}; + +struct pixel_t { + int x; + int y; +}; + +struct msm_calib_dpc { + uint16_t validcount; + struct pixel_t snapshot_coord[128]; + struct pixel_t preview_coord[128]; + struct pixel_t video_coord[128]; +}; + +struct msm_calib_raw { + uint8_t *data; + uint32_t size; +}; + +struct msm_camera_eeprom_info_t { + struct msm_eeprom_support af; + struct msm_eeprom_support wb; + struct msm_eeprom_support lsc; + struct msm_eeprom_support dpc; + struct msm_eeprom_support raw; +}; + +struct msm_eeprom_cfg_data { + int cfgtype; + uint8_t is_eeprom_supported; + union { + struct msm_eeprom_data_t get_data; + struct msm_camera_eeprom_info_t get_info; + } cfg; +}; + +struct sensor_large_data { + int cfgtype; + union { + struct sensor_3d_cali_data_t sensor_3d_cali_data; + } data; +}; + +enum sensor_type_t { + BAYER, + YUV, + JPEG_SOC, +}; + +enum flash_type { + LED_FLASH, + STROBE_FLASH, +}; + +enum strobe_flash_ctrl_type { + STROBE_FLASH_CTRL_INIT, + STROBE_FLASH_CTRL_CHARGE, + STROBE_FLASH_CTRL_RELEASE +}; + +struct strobe_flash_ctrl_data { + enum strobe_flash_ctrl_type type; + int charge_en; +}; + +struct msm_camera_info { + int num_cameras; + uint8_t has_3d_support[MSM_MAX_CAMERA_SENSORS]; + uint8_t is_internal_cam[MSM_MAX_CAMERA_SENSORS]; + uint32_t s_mount_angle[MSM_MAX_CAMERA_SENSORS]; + const char *video_dev_name[MSM_MAX_CAMERA_SENSORS]; + enum sensor_type_t sensor_type[MSM_MAX_CAMERA_SENSORS]; +}; + +struct msm_cam_config_dev_info { + int num_config_nodes; + const char *config_dev_name[MSM_MAX_CAMERA_CONFIGS]; + int config_dev_id[MSM_MAX_CAMERA_CONFIGS]; +}; + +struct msm_mctl_node_info { + int num_mctl_nodes; + const char *mctl_node_name[MSM_MAX_CAMERA_SENSORS]; +}; + +struct flash_ctrl_data { + int flashtype; + union { + int led_state; + struct strobe_flash_ctrl_data strobe_ctrl; + } ctrl_data; +}; + +#define GET_NAME 0 +#define GET_PREVIEW_LINE_PER_FRAME 1 +#define GET_PREVIEW_PIXELS_PER_LINE 2 +#define GET_SNAPSHOT_LINE_PER_FRAME 3 +#define GET_SNAPSHOT_PIXELS_PER_LINE 4 +#define GET_SNAPSHOT_FPS 5 +#define GET_SNAPSHOT_MAX_EP_LINE_CNT 6 + +struct msm_camsensor_info { + char name[MAX_SENSOR_NAME]; + uint8_t flash_enabled; + uint8_t strobe_flash_enabled; + uint8_t actuator_enabled; + uint8_t ispif_supported; + int8_t total_steps; + uint8_t support_3d; + enum flash_type flashtype; + enum sensor_type_t sensor_type; + uint32_t pxlcode; /* enum v4l2_mbus_pixelcode */ + uint32_t camera_type; /* msm_camera_type */ + int mount_angle; + uint32_t max_width; + uint32_t max_height; +}; + +#define V4L2_SINGLE_PLANE 0 +#define V4L2_MULTI_PLANE_Y 0 +#define V4L2_MULTI_PLANE_CBCR 1 +#define V4L2_MULTI_PLANE_CB 1 +#define V4L2_MULTI_PLANE_CR 2 + +struct plane_data { + int plane_id; + uint32_t offset; + unsigned long size; +}; + +struct img_plane_info { + uint32_t width; + uint32_t height; + uint32_t pixelformat; + uint8_t buffer_type; /*Single/Multi planar*/ + uint8_t output_port; + uint32_t ext_mode; + uint8_t num_planes; + struct plane_data plane[MAX_PLANES]; + uint32_t sp_y_offset; + uint32_t inst_handle; +}; + +#define QCAMERA_NAME "qcamera" +#define QCAMERA_SERVER_NAME "qcamera_server" +#define QCAMERA_DEVICE_GROUP_ID 1 +#define QCAMERA_VNODE_GROUP_ID 2 + +enum msm_cam_subdev_type { + CSIPHY_DEV, + CSID_DEV, + CSIC_DEV, + ISPIF_DEV, + VFE_DEV, + AXI_DEV, + VPE_DEV, + SENSOR_DEV, + ACTUATOR_DEV, + EEPROM_DEV, + GESTURE_DEV, + IRQ_ROUTER_DEV, + CPP_DEV, + CCI_DEV, + FLASH_DEV, +}; + +struct msm_mctl_set_sdev_data { + uint32_t revision; + enum msm_cam_subdev_type sdev_type; +}; + +#define MSM_CAM_V4L2_IOCTL_GET_CAMERA_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_GET_CONFIG_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_GET_MCTL_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_CTRL_CMD_DONE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_GET_EVENT_PAYLOAD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_IOCTL_SEND_EVENT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct v4l2_event) + +#define MSM_CAM_V4L2_IOCTL_CFG_VPE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_vpe_cfg_cmd) + +#define MSM_CAM_V4L2_IOCTL_PRIVATE_S_CTRL \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_PRIVATE_G_CTRL \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t) + +#define MSM_CAM_V4L2_IOCTL_PRIVATE_GENERAL \ + _IOW('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_INIT \ + _IO('V', BASE_VIDIOC_PRIVATE + 15) + +#define VIDIOC_MSM_VPE_RELEASE \ + _IO('V', BASE_VIDIOC_PRIVATE + 16) + +#define VIDIOC_MSM_VPE_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_mctl_pp_params *) + +#define VIDIOC_MSM_AXI_INIT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 18, uint8_t *) + +#define VIDIOC_MSM_AXI_RELEASE \ + _IO('V', BASE_VIDIOC_PRIVATE + 19) + +#define VIDIOC_MSM_AXI_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 20, void *) + +#define VIDIOC_MSM_AXI_IRQ \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 21, void *) + +#define VIDIOC_MSM_AXI_BUF_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 22, void *) + +#define VIDIOC_MSM_AXI_RDI_COUNT_UPDATE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 23, void *) + +#define VIDIOC_MSM_VFE_INIT \ + _IO('V', BASE_VIDIOC_PRIVATE + 24) + +#define VIDIOC_MSM_VFE_RELEASE \ + _IO('V', BASE_VIDIOC_PRIVATE + 25) + +struct msm_camera_v4l2_ioctl_t { + uint32_t id; + uint32_t len; + uint32_t trans_code; + void __user *ioctl_ptr; +}; + +struct msm_camera_vfe_params_t { + uint32_t operation_mode; + uint32_t capture_count; + uint8_t skip_reset; + uint8_t stop_immediately; + uint16_t port_info; + uint32_t inst_handle; + uint16_t cmd_type; +}; + +enum msm_camss_irq_idx { + CAMERA_SS_IRQ_0, + CAMERA_SS_IRQ_1, + CAMERA_SS_IRQ_2, + CAMERA_SS_IRQ_3, + CAMERA_SS_IRQ_4, + CAMERA_SS_IRQ_5, + CAMERA_SS_IRQ_6, + CAMERA_SS_IRQ_7, + CAMERA_SS_IRQ_8, + CAMERA_SS_IRQ_9, + CAMERA_SS_IRQ_10, + CAMERA_SS_IRQ_11, + CAMERA_SS_IRQ_12, + CAMERA_SS_IRQ_MAX +}; + +enum msm_cam_hw_idx { + MSM_CAM_HW_MICRO, + MSM_CAM_HW_CCI, + MSM_CAM_HW_CSI0, + MSM_CAM_HW_CSI1, + MSM_CAM_HW_CSI2, + MSM_CAM_HW_CSI3, + MSM_CAM_HW_ISPIF, + MSM_CAM_HW_CPP, + MSM_CAM_HW_VFE0, + MSM_CAM_HW_VFE1, + MSM_CAM_HW_JPEG0, + MSM_CAM_HW_JPEG1, + MSM_CAM_HW_JPEG2, + MSM_CAM_HW_MAX +}; + +struct msm_camera_irq_cfg { + /* Bit mask of all the camera hardwares that needs to + * be composited into a single IRQ to the MSM. + * Current usage: (may be updated based on hw changes) + * Bits 31:13 - Reserved. + * Bits 12:0 + * 12 - MSM_CAM_HW_JPEG2 + * 11 - MSM_CAM_HW_JPEG1 + * 10 - MSM_CAM_HW_JPEG0 + * 9 - MSM_CAM_HW_VFE1 + * 8 - MSM_CAM_HW_VFE0 + * 7 - MSM_CAM_HW_CPP + * 6 - MSM_CAM_HW_ISPIF + * 5 - MSM_CAM_HW_CSI3 + * 4 - MSM_CAM_HW_CSI2 + * 3 - MSM_CAM_HW_CSI1 + * 2 - MSM_CAM_HW_CSI0 + * 1 - MSM_CAM_HW_CCI + * 0 - MSM_CAM_HW_MICRO + */ + uint32_t cam_hw_mask; + uint8_t irq_idx; + uint8_t num_hwcore; +}; + +#define MSM_IRQROUTER_CFG_COMPIRQ \ + _IOWR('V', BASE_VIDIOC_PRIVATE, void __user *) + +#define MAX_NUM_CPP_STRIPS 8 + +enum msm_cpp_frame_type { + MSM_CPP_OFFLINE_FRAME, + MSM_CPP_REALTIME_FRAME, +}; + +struct msm_cpp_frame_info_t { + int32_t frame_id; + uint32_t inst_id; + uint32_t client_id; + enum msm_cpp_frame_type frame_type; + uint32_t num_strips; +}; + +struct msm_ver_num_info { + uint32_t main; + uint32_t minor; + uint32_t rev; +}; + +#define VIDIOC_MSM_CPP_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_GET_INST_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) + +#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0) + +/* Instance Handle - inst_handle + * Data bundle containing the information about where + * to get a buffer for a particular camera instance. + * This is a bitmask containing the following data: + * Buffer Handle Bitmask: + * ------------------------------------ + * Bits : Purpose + * ------------------------------------ + * 31 : is Dev ID valid? + * 30 - 24 : Dev ID. + * 23 : is Image mode valid? + * 22 - 16 : Image mode. + * 15 : is MCTL PP inst idx valid? + * 14 - 8 : MCTL PP inst idx. + * 7 : is Video inst idx valid? + * 6 - 0 : Video inst idx. + */ +#define CLR_DEVID_MODE(handle) (handle &= 0x00FFFFFF) +#define SET_DEVID_MODE(handle, data) \ + (handle |= ((0x1 << 31) | ((data & 0x7F) << 24))) +#define GET_DEVID_MODE(handle) \ + ((handle & 0x80000000) ? ((handle & 0x7F000000) >> 24) : 0xFF) + +#define CLR_IMG_MODE(handle) (handle &= 0xFF00FFFF) +#define SET_IMG_MODE(handle, data) \ + (handle |= ((0x1 << 23) | ((data & 0x7F) << 16))) +#define GET_IMG_MODE(handle) \ + ((handle & 0x800000) ? ((handle & 0x7F0000) >> 16) : 0xFF) + +#define CLR_MCTLPP_INST_IDX(handle) (handle &= 0xFFFF00FF) +#define SET_MCTLPP_INST_IDX(handle, data) \ + (handle |= ((0x1 << 15) | ((data & 0x7F) << 8))) +#define GET_MCTLPP_INST_IDX(handle) \ + ((handle & 0x8000) ? ((handle & 0x7F00) >> 8) : 0xFF) + +#define CLR_VIDEO_INST_IDX(handle) (handle &= 0xFFFFFF00) +#define GET_VIDEO_INST_IDX(handle) \ + ((handle & 0x80) ? (handle & 0x7F) : 0xFF) +#define SET_VIDEO_INST_IDX(handle, data) \ + (handle |= (0x1 << 7) | (data & 0x7F)) +#endif diff --git a/include/uapi/media/msm_camsensor_sdk.h b/include/uapi/media/msm_camsensor_sdk.h new file mode 100644 index 000000000000..40731a927ce5 --- /dev/null +++ b/include/uapi/media/msm_camsensor_sdk.h @@ -0,0 +1,435 @@ +#ifndef __UAPI_LINUX_MSM_CAMSENSOR_SDK_H +#define __UAPI_LINUX_MSM_CAMSENSOR_SDK_H + +#include <linux/videodev2.h> + +#define KVERSION 0x1 + +#define MAX_POWER_CONFIG 12 +#define GPIO_OUT_LOW (0 << 1) +#define GPIO_OUT_HIGH (1 << 1) +#define CSI_EMBED_DATA 0x12 +#define CSI_RESERVED_DATA_0 0x13 +#define CSI_YUV422_8 0x1E +#define CSI_RAW8 0x2A +#define CSI_RAW10 0x2B +#define CSI_RAW12 0x2C +#define CSI_DECODE_6BIT 0 +#define CSI_DECODE_8BIT 1 +#define CSI_DECODE_10BIT 2 +#define CSI_DECODE_12BIT 3 +#define CSI_DECODE_DPCM_10_6_10 4 +#define CSI_DECODE_DPCM_10_8_10 5 +#define MAX_CID 16 +#define I2C_SEQ_REG_DATA_MAX 1024 +#define I2C_REG_DATA_MAX (8*1024) + +#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */ +#define MSM_V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') + /* 14 BGBG.. GRGR.. */ +#define MSM_V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') + /* 14 GBGB.. RGRG.. */ +#define MSM_V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') + /* 14 GRGR.. BGBG.. */ +#define MSM_V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') + /* 14 RGRG.. GBGB.. */ + +#define MAX_ACTUATOR_REG_TBL_SIZE 8 +#define MAX_ACTUATOR_REGION 5 +#define NUM_ACTUATOR_DIR 2 +#define MAX_ACTUATOR_SCENARIO 8 +#define MAX_ACT_MOD_NAME_SIZE 32 +#define MAX_ACT_NAME_SIZE 32 +#define MAX_ACTUATOR_INIT_SET 120 +#define MAX_I2C_REG_SET 12 + +#define MAX_LED_TRIGGERS 3 + +#define MSM_EEPROM_MEMORY_MAP_MAX_SIZE 80 +#define MSM_EEPROM_MAX_MEM_MAP_CNT 8 + +#define MSM_SENSOR_BYPASS_VIDEO_NODE 1 + +#define FRONT_AUX_SENSOR_SUPPORT + +enum msm_sensor_camera_id_t { + CAMERA_0, + CAMERA_1, + CAMERA_2, + CAMERA_3, + MAX_CAMERAS, +}; + +enum i2c_freq_mode_t { + I2C_STANDARD_MODE, + I2C_FAST_MODE, + I2C_CUSTOM_MODE, + I2C_FAST_PLUS_MODE, + I2C_MAX_MODES, +}; + +enum camb_position_t { + BACK_CAMERA_B, + FRONT_CAMERA_B, + AUX_CAMERA_B = 0x100, + FRONT_AUX_CAMERA_B, + INVALID_CAMERA_B, +}; + +enum msm_sensor_power_seq_type_t { + SENSOR_CLK, + SENSOR_GPIO, + SENSOR_VREG, + SENSOR_I2C_MUX, + SENSOR_I2C, +}; + +enum msm_camera_i2c_reg_addr_type { + MSM_CAMERA_I2C_BYTE_ADDR = 1, + MSM_CAMERA_I2C_WORD_ADDR, + MSM_CAMERA_I2C_3B_ADDR, + MSM_CAMERA_I2C_DWORD_ADDR, + MSM_CAMERA_I2C_ADDR_TYPE_MAX, +}; +#define MSM_CAMERA_I2C_DWORD_ADDR MSM_CAMERA_I2C_DWORD_ADDR + +enum msm_camera_i2c_data_type { + MSM_CAMERA_I2C_BYTE_DATA = 1, + MSM_CAMERA_I2C_WORD_DATA, + MSM_CAMERA_I2C_DWORD_DATA, + MSM_CAMERA_I2C_SET_BYTE_MASK, + MSM_CAMERA_I2C_UNSET_BYTE_MASK, + MSM_CAMERA_I2C_SET_WORD_MASK, + MSM_CAMERA_I2C_UNSET_WORD_MASK, + MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA, + MSM_CAMERA_I2C_DATA_TYPE_MAX, +}; + +enum msm_sensor_power_seq_gpio_t { + SENSOR_GPIO_RESET, + SENSOR_GPIO_STANDBY, + SENSOR_GPIO_AF_PWDM, + SENSOR_GPIO_VIO, + SENSOR_GPIO_VANA, + SENSOR_GPIO_VDIG, + SENSOR_GPIO_VAF, + SENSOR_GPIO_FL_EN, + SENSOR_GPIO_FL_NOW, + SENSOR_GPIO_FL_RESET, + SENSOR_GPIO_CUSTOM1, + SENSOR_GPIO_CUSTOM2, + SENSOR_GPIO_CUSTOM3, + SENSOR_GPIO_MAX, +}; +#define SENSOR_GPIO_CUSTOM3 SENSOR_GPIO_CUSTOM3 + +enum msm_ir_cut_filter_gpio_t { + IR_CUT_FILTER_GPIO_P = 0, + IR_CUT_FILTER_GPIO_M, + IR_CUT_FILTER_GPIO_MAX, +}; +#define IR_CUT_FILTER_GPIO_P IR_CUT_FILTER_GPIO_P +#define IR_CUT_FILTER_GPIO_M IR_CUT_FILTER_GPIO_M +#define R_CUT_FILTER_GPIO_MAX IR_CUT_FILTER_GPIO_MAX + +enum msm_camera_vreg_name_t { + CAM_VDIG, + CAM_VIO, + CAM_VANA, + CAM_VAF, + CAM_V_CUSTOM1, + CAM_V_CUSTOM2, + CAM_VREG_MAX, +}; + +enum msm_sensor_clk_type_t { + SENSOR_CAM_MCLK, + SENSOR_CAM_CLK, + SENSOR_CAM_CLK_MAX, +}; + +enum camerab_mode_t { + CAMERA_MODE_2D_B = (1<<0), + CAMERA_MODE_3D_B = (1<<1), + CAMERA_MODE_INVALID = (1<<2), +}; + +enum msm_actuator_data_type { + MSM_ACTUATOR_BYTE_DATA = 1, + MSM_ACTUATOR_WORD_DATA, +}; + +enum msm_actuator_addr_type { + MSM_ACTUATOR_BYTE_ADDR = 1, + MSM_ACTUATOR_WORD_ADDR, +}; + +enum msm_actuator_write_type { + MSM_ACTUATOR_WRITE_HW_DAMP, + MSM_ACTUATOR_WRITE_DAC, + MSM_ACTUATOR_WRITE, + MSM_ACTUATOR_WRITE_DIR_REG, + MSM_ACTUATOR_POLL, + MSM_ACTUATOR_READ_WRITE, +}; + +enum msm_actuator_i2c_operation { + MSM_ACT_WRITE = 0, + MSM_ACT_POLL, +}; + +enum actuator_type { + ACTUATOR_VCM, + ACTUATOR_PIEZO, + ACTUATOR_HVCM, + ACTUATOR_BIVCM, +}; + +enum msm_flash_driver_type { + FLASH_DRIVER_PMIC, + FLASH_DRIVER_I2C, + FLASH_DRIVER_GPIO, + FLASH_DRIVER_DEFAULT +}; + +enum msm_flash_cfg_type_t { + CFG_FLASH_INIT, + CFG_FLASH_RELEASE, + CFG_FLASH_OFF, + CFG_FLASH_LOW, + CFG_FLASH_HIGH, +}; + +enum msm_ir_led_cfg_type_t { + CFG_IR_LED_INIT = 0, + CFG_IR_LED_RELEASE, + CFG_IR_LED_OFF, + CFG_IR_LED_ON, +}; +#define CFG_IR_LED_INIT CFG_IR_LED_INIT +#define CFG_IR_LED_RELEASE CFG_IR_LED_RELEASE +#define CFG_IR_LED_OFF CFG_IR_LED_OFF +#define CFG_IR_LED_ON CFG_IR_LED_ON + +enum msm_laser_led_cfg_type_t { + CFG_LASER_LED_INIT, + CFG_LASER_LED_CONTROL, +}; +#define CFG_LASER_LED_INIT CFG_LASER_LED_INIT +#define CFG_LASER_LED_CONTROL CFG_LASER_LED_CONTROL + +enum msm_ir_cut_cfg_type_t { + CFG_IR_CUT_INIT = 0, + CFG_IR_CUT_RELEASE, + CFG_IR_CUT_OFF, + CFG_IR_CUT_ON, +}; +#define CFG_IR_CUT_INIT CFG_IR_CUT_INIT +#define CFG_IR_CUT_RELEASE CFG_IR_CUT_RELEASE +#define CFG_IR_CUT_OFF CFG_IR_CUT_OFF +#define CFG_IR_CUT_ON CFG_IR_CUT_ON + +enum msm_sensor_output_format_t { + MSM_SENSOR_BAYER, + MSM_SENSOR_YCBCR, + MSM_SENSOR_META, +}; + +struct msm_sensor_power_setting { + enum msm_sensor_power_seq_type_t seq_type; + unsigned short seq_val; + long config_val; + unsigned short delay; + void *data[10]; +}; + +struct msm_sensor_power_setting_array { + struct msm_sensor_power_setting power_setting_a[MAX_POWER_CONFIG]; + struct msm_sensor_power_setting *power_setting; + unsigned short size; + struct msm_sensor_power_setting power_down_setting_a[MAX_POWER_CONFIG]; + struct msm_sensor_power_setting *power_down_setting; + unsigned short size_down; +}; + +enum msm_camera_i2c_operation { + MSM_CAM_WRITE = 0, + MSM_CAM_POLL, + MSM_CAM_READ, +}; + +struct msm_sensor_i2c_sync_params { + unsigned int cid; + int csid; + unsigned short line; + unsigned short delay; +}; + +struct msm_camera_reg_settings_t { + uint16_t reg_addr; + enum msm_camera_i2c_reg_addr_type addr_type; + uint16_t reg_data; + enum msm_camera_i2c_data_type data_type; + enum msm_camera_i2c_operation i2c_operation; + uint16_t delay; +}; + +struct msm_eeprom_mem_map_t { + int slave_addr; + struct msm_camera_reg_settings_t + mem_settings[MSM_EEPROM_MEMORY_MAP_MAX_SIZE]; + int memory_map_size; +}; + +struct msm_eeprom_memory_map_array { + struct msm_eeprom_mem_map_t memory_map[MSM_EEPROM_MAX_MEM_MAP_CNT]; + uint32_t msm_size_of_max_mappings; +}; + +struct msm_sensor_init_params { + /* mask of modes supported: 2D, 3D */ + int modes_supported; + /* sensor position: front, back */ + enum camb_position_t position; + /* sensor mount angle */ + unsigned int sensor_mount_angle; +}; + +struct msm_sensor_id_info_t { + unsigned short sensor_id_reg_addr; + unsigned short sensor_id; + unsigned short sensor_id_mask; +}; + +struct msm_camera_sensor_slave_info { + char sensor_name[32]; + char eeprom_name[32]; + char actuator_name[32]; + char ois_name[32]; + char flash_name[32]; + enum msm_sensor_camera_id_t camera_id; + unsigned short slave_addr; + enum i2c_freq_mode_t i2c_freq_mode; + enum msm_camera_i2c_reg_addr_type addr_type; + struct msm_sensor_id_info_t sensor_id_info; + struct msm_sensor_power_setting_array power_setting_array; + unsigned char is_init_params_valid; + struct msm_sensor_init_params sensor_init_params; + enum msm_sensor_output_format_t output_format; + uint8_t bypass_video_node_creation; +}; + +struct msm_camera_i2c_reg_array { + unsigned short reg_addr; + unsigned short reg_data; + unsigned int delay; +}; + +struct msm_camera_i2c_reg_setting { + struct msm_camera_i2c_reg_array *reg_setting; + unsigned short size; + enum msm_camera_i2c_reg_addr_type addr_type; + enum msm_camera_i2c_data_type data_type; + unsigned short delay; +}; + +struct msm_camera_csid_vc_cfg { + unsigned char cid; + unsigned char dt; + unsigned char decode_format; +}; + +struct msm_camera_csid_lut_params { + unsigned char num_cid; + struct msm_camera_csid_vc_cfg vc_cfg_a[MAX_CID]; + struct msm_camera_csid_vc_cfg *vc_cfg[MAX_CID]; +}; + +struct msm_camera_csid_params { + unsigned char lane_cnt; + unsigned short lane_assign; + unsigned char phy_sel; + unsigned int csi_clk; + struct msm_camera_csid_lut_params lut_params; + unsigned char csi_3p_sel; +}; + +struct msm_camera_csid_testmode_parms { + unsigned int num_bytes_per_line; + unsigned int num_lines; + unsigned int h_blanking_count; + unsigned int v_blanking_count; + unsigned int payload_mode; +}; + +struct msm_camera_csiphy_params { + unsigned char lane_cnt; + unsigned char settle_cnt; + unsigned short lane_mask; + unsigned char combo_mode; + unsigned char csid_core; + unsigned int csiphy_clk; + unsigned char csi_3phase; + uint64_t data_rate; +}; + +struct msm_camera_i2c_seq_reg_array { + unsigned short reg_addr; + unsigned char reg_data[I2C_SEQ_REG_DATA_MAX]; + unsigned short reg_data_size; +}; + +struct msm_camera_i2c_seq_reg_setting { + struct msm_camera_i2c_seq_reg_array *reg_setting; + unsigned short size; + enum msm_camera_i2c_reg_addr_type addr_type; + unsigned short delay; +}; + +struct msm_actuator_reg_params_t { + enum msm_actuator_write_type reg_write_type; + unsigned int hw_mask; + unsigned short reg_addr; + unsigned short hw_shift; + unsigned short data_shift; + unsigned short data_type; + unsigned short addr_type; + unsigned short reg_data; + unsigned short delay; +}; + + +struct damping_params_t { + unsigned int damping_step; + unsigned int damping_delay; + unsigned int hw_params; +}; + +struct region_params_t { + /* [0] = ForwardDirection Macro boundary + [1] = ReverseDirection Inf boundary + */ + unsigned short step_bound[2]; + unsigned short code_per_step; + /* qvalue for converting float type numbers to integer format */ + unsigned int qvalue; +}; + +struct reg_settings_t { + unsigned short reg_addr; + enum msm_camera_i2c_reg_addr_type addr_type; + unsigned short reg_data; + enum msm_camera_i2c_data_type data_type; + enum msm_actuator_i2c_operation i2c_operation; + unsigned int delay; +}; + +struct msm_camera_i2c_reg_setting_array { + struct msm_camera_i2c_reg_array reg_setting_a[MAX_I2C_REG_SET]; + unsigned short size; + enum msm_camera_i2c_reg_addr_type addr_type; + enum msm_camera_i2c_data_type data_type; + unsigned short delay; +}; + +#endif diff --git a/include/uapi/media/msm_fd.h b/include/uapi/media/msm_fd.h new file mode 100644 index 000000000000..eb3bd785676b --- /dev/null +++ b/include/uapi/media/msm_fd.h @@ -0,0 +1,76 @@ +#ifndef __UAPI_MSM_FD__ +#define __UAPI_MSM_FD__ + +#include <linux/videodev2.h> +#include <linux/types.h> + +/* + * struct msm_fd_event - Structure contain event info. + * @buf_index: Buffer index. + * @frame_id: Frame id. + * @face_cnt: Detected faces. + */ +struct msm_fd_event { + __u32 buf_index; + __u32 frame_id; + __u32 face_cnt; +}; + +/* + * enum msm_fd_pose - Face pose. + */ +enum msm_fd_pose { + MSM_FD_POSE_FRONT, + MSM_FD_POSE_RIGHT_DIAGONAL, + MSM_FD_POSE_RIGHT, + MSM_FD_POSE_LEFT_DIAGONAL, + MSM_FD_POSE_LEFT, +}; + +/* + * struct msm_fd_face_data - Structure contain detected face data. + * @pose: refer to enum msm_fd_pose. + * @angle: Face angle + * @confidence: Face confidence level. + * @reserved: Reserved data for future use. + * @face: Face rectangle. + */ +struct msm_fd_face_data { + __u32 pose; + __u32 angle; + __u32 confidence; + __u32 reserved; + struct v4l2_rect face; +}; + +/* + * struct msm_fd_result - Structure contain detected faces result. + * @frame_id: Frame id of requested result. + * @face_cnt: Number of result faces, driver can modify this value (to smaller) + * @face_data: Pointer to array of face data structures. + * Array size should not be smaller then face_cnt. + */ +struct msm_fd_result { + __u32 frame_id; + __u32 face_cnt; + struct msm_fd_face_data __user *face_data; +}; + +/* MSM FD private ioctl ID */ +#define VIDIOC_MSM_FD_GET_RESULT \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_fd_result) + +/* MSM FD event ID */ +#define MSM_EVENT_FD (V4L2_EVENT_PRIVATE_START) + +/* MSM FD control ID's */ +#define V4L2_CID_FD_SPEED (V4L2_CID_PRIVATE_BASE) +#define V4L2_CID_FD_FACE_ANGLE (V4L2_CID_PRIVATE_BASE + 1) +#define V4L2_CID_FD_MIN_FACE_SIZE (V4L2_CID_PRIVATE_BASE + 2) +#define V4L2_CID_FD_FACE_DIRECTION (V4L2_CID_PRIVATE_BASE + 3) +#define V4L2_CID_FD_DETECTION_THRESHOLD (V4L2_CID_PRIVATE_BASE + 4) +#define V4L2_CID_FD_WORK_MEMORY_SIZE (V4L2_CID_PRIVATE_BASE + 5) +#define V4L2_CID_FD_WORK_MEMORY_FD (V4L2_CID_PRIVATE_BASE + 6) + +#endif + diff --git a/include/uapi/media/msm_gemini.h b/include/uapi/media/msm_gemini.h new file mode 100644 index 000000000000..0b41b384f6fb --- /dev/null +++ b/include/uapi/media/msm_gemini.h @@ -0,0 +1,123 @@ +#ifndef __UAPI_MSM_GEMINI_H +#define __UAPI_MSM_GEMINI_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +#define MSM_GMN_IOCTL_MAGIC 'g' + +#define MSM_GMN_IOCTL_GET_HW_VERSION \ + _IOW(MSM_GMN_IOCTL_MAGIC, 1, struct msm_gemini_hw_cmd *) + +#define MSM_GMN_IOCTL_RESET \ + _IOW(MSM_GMN_IOCTL_MAGIC, 2, struct msm_gemini_ctrl_cmd *) + +#define MSM_GMN_IOCTL_STOP \ + _IOW(MSM_GMN_IOCTL_MAGIC, 3, struct msm_gemini_hw_cmds *) + +#define MSM_GMN_IOCTL_START \ + _IOW(MSM_GMN_IOCTL_MAGIC, 4, struct msm_gemini_hw_cmds *) + +#define MSM_GMN_IOCTL_INPUT_BUF_ENQUEUE \ + _IOW(MSM_GMN_IOCTL_MAGIC, 5, struct msm_gemini_buf *) + +#define MSM_GMN_IOCTL_INPUT_GET \ + _IOW(MSM_GMN_IOCTL_MAGIC, 6, struct msm_gemini_buf *) + +#define MSM_GMN_IOCTL_INPUT_GET_UNBLOCK \ + _IOW(MSM_GMN_IOCTL_MAGIC, 7, int) + +#define MSM_GMN_IOCTL_OUTPUT_BUF_ENQUEUE \ + _IOW(MSM_GMN_IOCTL_MAGIC, 8, struct msm_gemini_buf *) + +#define MSM_GMN_IOCTL_OUTPUT_GET \ + _IOW(MSM_GMN_IOCTL_MAGIC, 9, struct msm_gemini_buf *) + +#define MSM_GMN_IOCTL_OUTPUT_GET_UNBLOCK \ + _IOW(MSM_GMN_IOCTL_MAGIC, 10, int) + +#define MSM_GMN_IOCTL_EVT_GET \ + _IOW(MSM_GMN_IOCTL_MAGIC, 11, struct msm_gemini_ctrl_cmd *) + +#define MSM_GMN_IOCTL_EVT_GET_UNBLOCK \ + _IOW(MSM_GMN_IOCTL_MAGIC, 12, int) + +#define MSM_GMN_IOCTL_HW_CMD \ + _IOW(MSM_GMN_IOCTL_MAGIC, 13, struct msm_gemini_hw_cmd *) + +#define MSM_GMN_IOCTL_HW_CMDS \ + _IOW(MSM_GMN_IOCTL_MAGIC, 14, struct msm_gemini_hw_cmds *) + +#define MSM_GMN_IOCTL_TEST_DUMP_REGION \ + _IOW(MSM_GMN_IOCTL_MAGIC, 15, unsigned long) + +#define MSM_GMN_IOCTL_SET_MODE \ + _IOW(MSM_GMN_IOCTL_MAGIC, 16, enum msm_gmn_out_mode) + +#define MSM_GEMINI_MODE_REALTIME_ENCODE 0 +#define MSM_GEMINI_MODE_OFFLINE_ENCODE 1 +#define MSM_GEMINI_MODE_REALTIME_ROTATION 2 +#define MSM_GEMINI_MODE_OFFLINE_ROTATION 3 + +enum msm_gmn_out_mode { + MSM_GMN_OUTMODE_FRAGMENTED, + MSM_GMN_OUTMODE_SINGLE +}; + +struct msm_gemini_ctrl_cmd { + uint32_t type; + uint32_t len; + void *value; +}; + +#define MSM_GEMINI_EVT_RESET 0 +#define MSM_GEMINI_EVT_FRAMEDONE 1 +#define MSM_GEMINI_EVT_ERR 2 + +struct msm_gemini_buf { + uint32_t type; + int fd; + + void *vaddr; + + uint32_t y_off; + uint32_t y_len; + uint32_t framedone_len; + + uint32_t cbcr_off; + uint32_t cbcr_len; + + uint32_t num_of_mcu_rows; + uint32_t offset; +}; + +#define MSM_GEMINI_HW_CMD_TYPE_READ 0 +#define MSM_GEMINI_HW_CMD_TYPE_WRITE 1 +#define MSM_GEMINI_HW_CMD_TYPE_WRITE_OR 2 +#define MSM_GEMINI_HW_CMD_TYPE_UWAIT 3 +#define MSM_GEMINI_HW_CMD_TYPE_MWAIT 4 +#define MSM_GEMINI_HW_CMD_TYPE_MDELAY 5 +#define MSM_GEMINI_HW_CMD_TYPE_UDELAY 6 +struct msm_gemini_hw_cmd { + + uint32_t type:4; + + /* n microseconds of timeout for WAIT */ + /* n microseconds of time for DELAY */ + /* repeat n times for READ/WRITE */ + /* max is 0xFFF, 4095 */ + uint32_t n:12; + uint32_t offset:16; + uint32_t mask; + union { + uint32_t data; /* for single READ/WRITE/WAIT, n = 1 */ + uint32_t *pdata; /* for multiple READ/WRITE/WAIT, n > 1 */ + }; +}; + +struct msm_gemini_hw_cmds { + uint32_t m; /* number of elements in the hw_cmd array */ + struct msm_gemini_hw_cmd hw_cmd[1]; +}; + +#endif /* __UAPI_MSM_GEMINI_H */ diff --git a/include/uapi/media/msm_gestures.h b/include/uapi/media/msm_gestures.h new file mode 100644 index 000000000000..2d6d8f2ef58f --- /dev/null +++ b/include/uapi/media/msm_gestures.h @@ -0,0 +1,54 @@ +#ifndef __UAPI_MSM_GESTURES_H +#define __UAPI_MSM_GESTURES_H + +#include <linux/types.h> +#include <linux/ioctl.h> +#include <media/msm_camera.h> + +#define MSM_GES_IOCTL_CTRL_COMMAND \ + _IOW('V', BASE_VIDIOC_PRIVATE + 20, struct v4l2_control) + +#define VIDIOC_MSM_GESTURE_EVT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 21, struct v4l2_event) + +#define MSM_GES_GET_EVT_PAYLOAD \ + _IOW('V', BASE_VIDIOC_PRIVATE + 22, struct msm_ges_evt) + +#define VIDIOC_MSM_GESTURE_CAM_EVT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 23, int) + +#define MSM_GES_RESP_V4L2 MSM_CAM_RESP_MAX +#define MSM_GES_RESP_MAX (MSM_GES_RESP_V4L2 + 1) + +#define MSM_SVR_RESP_MAX MSM_GES_RESP_MAX + + +#define MSM_V4L2_GES_BASE 100 +#define MSM_V4L2_GES_OPEN (MSM_V4L2_GES_BASE + 0) +#define MSM_V4L2_GES_CLOSE (MSM_V4L2_GES_BASE + 1) +#define MSM_V4L2_GES_CAM_OPEN (MSM_V4L2_GES_BASE + 2) +#define MSM_V4L2_GES_CAM_CLOSE (MSM_V4L2_GES_BASE + 3) + +#define MSM_GES_APP_EVT_MIN (V4L2_EVENT_PRIVATE_START + 0x14) +#define MSM_GES_APP_NOTIFY_EVENT (MSM_GES_APP_EVT_MIN + 0) +#define MSM_GES_APP_NOTIFY_ERROR_EVENT (MSM_GES_APP_EVT_MIN + 1) +#define MSM_GES_APP_EVT_MAX (MSM_GES_APP_EVT_MIN + 2) + +#define MSM_GESTURE_CID_CTRL_CMD V4L2_CID_BRIGHTNESS + +#define MAX_GES_EVENTS 25 + +struct msm_ges_ctrl_cmd { + int type; + void *value; + int len; + int fd; + uint32_t cookie; +}; + +struct msm_ges_evt { + void *evt_data; + int evt_len; +}; + +#endif /*__UAPI_MSM_GESTURES_H*/ diff --git a/include/uapi/media/msm_isp.h b/include/uapi/media/msm_isp.h new file mode 100644 index 000000000000..90d87c249dd5 --- /dev/null +++ b/include/uapi/media/msm_isp.h @@ -0,0 +1,344 @@ +#ifndef __UAPI_MSM_ISP_H__ +#define __UAPI_MSM_ISP_H__ + +#define BIT(nr) (1UL << (nr)) + +/* ISP message IDs */ +#define MSG_ID_RESET_ACK 0 +#define MSG_ID_START_ACK 1 +#define MSG_ID_STOP_ACK 2 +#define MSG_ID_UPDATE_ACK 3 +#define MSG_ID_OUTPUT_P 4 +#define MSG_ID_OUTPUT_T 5 +#define MSG_ID_OUTPUT_S 6 +#define MSG_ID_OUTPUT_V 7 +#define MSG_ID_SNAPSHOT_DONE 8 +#define MSG_ID_STATS_AEC 9 +#define MSG_ID_STATS_AF 10 +#define MSG_ID_STATS_AWB 11 +#define MSG_ID_STATS_RS 12 +#define MSG_ID_STATS_CS 13 +#define MSG_ID_STATS_IHIST 14 +#define MSG_ID_STATS_SKIN 15 +#define MSG_ID_EPOCH1 16 +#define MSG_ID_EPOCH2 17 +#define MSG_ID_SYNC_TIMER0_DONE 18 +#define MSG_ID_SYNC_TIMER1_DONE 19 +#define MSG_ID_SYNC_TIMER2_DONE 20 +#define MSG_ID_ASYNC_TIMER0_DONE 21 +#define MSG_ID_ASYNC_TIMER1_DONE 22 +#define MSG_ID_ASYNC_TIMER2_DONE 23 +#define MSG_ID_ASYNC_TIMER3_DONE 24 +#define MSG_ID_AE_OVERFLOW 25 +#define MSG_ID_AF_OVERFLOW 26 +#define MSG_ID_AWB_OVERFLOW 27 +#define MSG_ID_RS_OVERFLOW 28 +#define MSG_ID_CS_OVERFLOW 29 +#define MSG_ID_IHIST_OVERFLOW 30 +#define MSG_ID_SKIN_OVERFLOW 31 +#define MSG_ID_AXI_ERROR 32 +#define MSG_ID_CAMIF_OVERFLOW 33 +#define MSG_ID_VIOLATION 34 +#define MSG_ID_CAMIF_ERROR 35 +#define MSG_ID_BUS_OVERFLOW 36 +#define MSG_ID_SOF_ACK 37 +#define MSG_ID_STOP_REC_ACK 38 +#define MSG_ID_STATS_AWB_AEC 39 +#define MSG_ID_OUTPUT_PRIMARY 40 +#define MSG_ID_OUTPUT_SECONDARY 41 +#define MSG_ID_STATS_COMPOSITE 42 +#define MSG_ID_OUTPUT_TERTIARY1 43 +#define MSG_ID_STOP_LS_ACK 44 +#define MSG_ID_OUTPUT_TERTIARY2 45 +#define MSG_ID_STATS_BG 46 +#define MSG_ID_STATS_BF 47 +#define MSG_ID_STATS_BHIST 48 +#define MSG_ID_RDI0_UPDATE_ACK 49 +#define MSG_ID_RDI1_UPDATE_ACK 50 +#define MSG_ID_RDI2_UPDATE_ACK 51 +#define MSG_ID_PIX0_UPDATE_ACK 52 +#define MSG_ID_PREV_STOP_ACK 53 +#define MSG_ID_STATS_BE 54 + + +/* ISP command IDs */ +#define VFE_CMD_DUMMY_0 0 +#define VFE_CMD_SET_CLK 1 +#define VFE_CMD_RESET 2 +#define VFE_CMD_START 3 +#define VFE_CMD_TEST_GEN_START 4 +#define VFE_CMD_OPERATION_CFG 5 +#define VFE_CMD_AXI_OUT_CFG 6 +#define VFE_CMD_CAMIF_CFG 7 +#define VFE_CMD_AXI_INPUT_CFG 8 +#define VFE_CMD_BLACK_LEVEL_CFG 9 +#define VFE_CMD_MESH_ROLL_OFF_CFG 10 +#define VFE_CMD_DEMUX_CFG 11 +#define VFE_CMD_FOV_CFG 12 +#define VFE_CMD_MAIN_SCALER_CFG 13 +#define VFE_CMD_WB_CFG 14 +#define VFE_CMD_COLOR_COR_CFG 15 +#define VFE_CMD_RGB_G_CFG 16 +#define VFE_CMD_LA_CFG 17 +#define VFE_CMD_CHROMA_EN_CFG 18 +#define VFE_CMD_CHROMA_SUP_CFG 19 +#define VFE_CMD_MCE_CFG 20 +#define VFE_CMD_SK_ENHAN_CFG 21 +#define VFE_CMD_ASF_CFG 22 +#define VFE_CMD_S2Y_CFG 23 +#define VFE_CMD_S2CbCr_CFG 24 +#define VFE_CMD_CHROMA_SUBS_CFG 25 +#define VFE_CMD_OUT_CLAMP_CFG 26 +#define VFE_CMD_FRAME_SKIP_CFG 27 +#define VFE_CMD_DUMMY_1 28 +#define VFE_CMD_DUMMY_2 29 +#define VFE_CMD_DUMMY_3 30 +#define VFE_CMD_UPDATE 31 +#define VFE_CMD_BL_LVL_UPDATE 32 +#define VFE_CMD_DEMUX_UPDATE 33 +#define VFE_CMD_FOV_UPDATE 34 +#define VFE_CMD_MAIN_SCALER_UPDATE 35 +#define VFE_CMD_WB_UPDATE 36 +#define VFE_CMD_COLOR_COR_UPDATE 37 +#define VFE_CMD_RGB_G_UPDATE 38 +#define VFE_CMD_LA_UPDATE 39 +#define VFE_CMD_CHROMA_EN_UPDATE 40 +#define VFE_CMD_CHROMA_SUP_UPDATE 41 +#define VFE_CMD_MCE_UPDATE 42 +#define VFE_CMD_SK_ENHAN_UPDATE 43 +#define VFE_CMD_S2CbCr_UPDATE 44 +#define VFE_CMD_S2Y_UPDATE 45 +#define VFE_CMD_ASF_UPDATE 46 +#define VFE_CMD_FRAME_SKIP_UPDATE 47 +#define VFE_CMD_CAMIF_FRAME_UPDATE 48 +#define VFE_CMD_STATS_AF_UPDATE 49 +#define VFE_CMD_STATS_AE_UPDATE 50 +#define VFE_CMD_STATS_AWB_UPDATE 51 +#define VFE_CMD_STATS_RS_UPDATE 52 +#define VFE_CMD_STATS_CS_UPDATE 53 +#define VFE_CMD_STATS_SKIN_UPDATE 54 +#define VFE_CMD_STATS_IHIST_UPDATE 55 +#define VFE_CMD_DUMMY_4 56 +#define VFE_CMD_EPOCH1_ACK 57 +#define VFE_CMD_EPOCH2_ACK 58 +#define VFE_CMD_START_RECORDING 59 +#define VFE_CMD_STOP_RECORDING 60 +#define VFE_CMD_DUMMY_5 61 +#define VFE_CMD_DUMMY_6 62 +#define VFE_CMD_CAPTURE 63 +#define VFE_CMD_DUMMY_7 64 +#define VFE_CMD_STOP 65 +#define VFE_CMD_GET_HW_VERSION 66 +#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67 +#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68 +#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69 +#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70 +#define VFE_CMD_JPEG_OUT_BUF_ENQ 71 +#define VFE_CMD_RAW_OUT_BUF_ENQ 72 +#define VFE_CMD_RAW_IN_BUF_ENQ 73 +#define VFE_CMD_STATS_AF_ENQ 74 +#define VFE_CMD_STATS_AE_ENQ 75 +#define VFE_CMD_STATS_AWB_ENQ 76 +#define VFE_CMD_STATS_RS_ENQ 77 +#define VFE_CMD_STATS_CS_ENQ 78 +#define VFE_CMD_STATS_SKIN_ENQ 79 +#define VFE_CMD_STATS_IHIST_ENQ 80 +#define VFE_CMD_DUMMY_8 81 +#define VFE_CMD_JPEG_ENC_CFG 82 +#define VFE_CMD_DUMMY_9 83 +#define VFE_CMD_STATS_AF_START 84 +#define VFE_CMD_STATS_AF_STOP 85 +#define VFE_CMD_STATS_AE_START 86 +#define VFE_CMD_STATS_AE_STOP 87 +#define VFE_CMD_STATS_AWB_START 88 +#define VFE_CMD_STATS_AWB_STOP 89 +#define VFE_CMD_STATS_RS_START 90 +#define VFE_CMD_STATS_RS_STOP 91 +#define VFE_CMD_STATS_CS_START 92 +#define VFE_CMD_STATS_CS_STOP 93 +#define VFE_CMD_STATS_SKIN_START 94 +#define VFE_CMD_STATS_SKIN_STOP 95 +#define VFE_CMD_STATS_IHIST_START 96 +#define VFE_CMD_STATS_IHIST_STOP 97 +#define VFE_CMD_DUMMY_10 98 +#define VFE_CMD_SYNC_TIMER_SETTING 99 +#define VFE_CMD_ASYNC_TIMER_SETTING 100 +#define VFE_CMD_LIVESHOT 101 +#define VFE_CMD_LA_SETUP 102 +#define VFE_CMD_LINEARIZATION_CFG 103 +#define VFE_CMD_DEMOSAICV3 104 +#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105 +#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106 +#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107 +#define VFE_CMD_DEMOSAICV3_ABF_CFG 108 +#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109 +#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110 +#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111 +#define VFE_CMD_XBAR_CFG 112 +#define VFE_CMD_MODULE_CFG 113 +#define VFE_CMD_ZSL 114 +#define VFE_CMD_LINEARIZATION_UPDATE 115 +#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116 +#define VFE_CMD_CLF_CFG 117 +#define VFE_CMD_CLF_LUMA_UPDATE 118 +#define VFE_CMD_CLF_CHROMA_UPDATE 119 +#define VFE_CMD_PCA_ROLL_OFF_CFG 120 +#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121 +#define VFE_CMD_GET_REG_DUMP 122 +#define VFE_CMD_GET_LINEARIZATON_TABLE 123 +#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124 +#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125 +#define VFE_CMD_GET_RGB_G_TABLE 126 +#define VFE_CMD_GET_LA_TABLE 127 +#define VFE_CMD_DEMOSAICV3_UPDATE 128 +#define VFE_CMD_ACTIVE_REGION_CFG 129 +#define VFE_CMD_COLOR_PROCESSING_CONFIG 130 +#define VFE_CMD_STATS_WB_AEC_CONFIG 131 +#define VFE_CMD_STATS_WB_AEC_UPDATE 132 +#define VFE_CMD_Y_GAMMA_CONFIG 133 +#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134 +#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135 +#define VFE_CMD_CAPTURE_RAW 136 +#define VFE_CMD_STOP_LIVESHOT 137 +#define VFE_CMD_RECONFIG_VFE 138 +#define VFE_CMD_STATS_REQBUF 139 +#define VFE_CMD_STATS_ENQUEUEBUF 140 +#define VFE_CMD_STATS_FLUSH_BUFQ 141 +#define VFE_CMD_STATS_UNREGBUF 142 +#define VFE_CMD_STATS_BG_START 143 +#define VFE_CMD_STATS_BG_STOP 144 +#define VFE_CMD_STATS_BF_START 145 +#define VFE_CMD_STATS_BF_STOP 146 +#define VFE_CMD_STATS_BHIST_START 147 +#define VFE_CMD_STATS_BHIST_STOP 148 +#define VFE_CMD_RESET_2 149 +#define VFE_CMD_FOV_ENC_CFG 150 +#define VFE_CMD_FOV_VIEW_CFG 151 +#define VFE_CMD_FOV_ENC_UPDATE 152 +#define VFE_CMD_FOV_VIEW_UPDATE 153 +#define VFE_CMD_SCALER_ENC_CFG 154 +#define VFE_CMD_SCALER_VIEW_CFG 155 +#define VFE_CMD_SCALER_ENC_UPDATE 156 +#define VFE_CMD_SCALER_VIEW_UPDATE 157 +#define VFE_CMD_COLORXFORM_ENC_CFG 158 +#define VFE_CMD_COLORXFORM_VIEW_CFG 159 +#define VFE_CMD_COLORXFORM_ENC_UPDATE 160 +#define VFE_CMD_COLORXFORM_VIEW_UPDATE 161 +#define VFE_CMD_TEST_GEN_CFG 162 +#define VFE_CMD_STATS_BE_START 163 +#define VFE_CMD_STATS_BE_STOP 164 +struct msm_isp_cmd { + int32_t id; + uint16_t length; + void *value; +}; + +#define VPE_CMD_DUMMY_0 0 +#define VPE_CMD_INIT 1 +#define VPE_CMD_DEINIT 2 +#define VPE_CMD_ENABLE 3 +#define VPE_CMD_DISABLE 4 +#define VPE_CMD_RESET 5 +#define VPE_CMD_FLUSH 6 +#define VPE_CMD_OPERATION_MODE_CFG 7 +#define VPE_CMD_INPUT_PLANE_CFG 8 +#define VPE_CMD_OUTPUT_PLANE_CFG 9 +#define VPE_CMD_INPUT_PLANE_UPDATE 10 +#define VPE_CMD_SCALE_CFG_TYPE 11 +#define VPE_CMD_ZOOM 13 +#define VPE_CMD_MAX 14 + +#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */ +#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */ +#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */ + +#define MCTL_CMD_DUMMY_0 0 /* not used */ +#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */ +#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */ +#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */ + +/* event typese sending to MCTL PP module */ +#define MCTL_PP_EVENT_NOTUSED 0 +#define MCTL_PP_EVENT_CMD_ACK 1 + +#define VPE_OPERATION_MODE_CFG_LEN 4 +#define VPE_INPUT_PLANE_CFG_LEN 24 +#define VPE_OUTPUT_PLANE_CFG_LEN 20 +#define VPE_INPUT_PLANE_UPDATE_LEN 12 +#define VPE_SCALER_CONFIG_LEN 260 +#define VPE_DIS_OFFSET_CFG_LEN 12 + + +#define CAPTURE_WIDTH 1280 +#define IMEM_Y_SIZE (CAPTURE_WIDTH*16) +#define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8) + +#define IMEM_Y_PING_OFFSET 0x2E000000 +#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE) + +#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE) +#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE) + + +struct msm_vpe_op_mode_cfg { + uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN]; +}; + +struct msm_vpe_input_plane_cfg { + uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN]; +}; + +struct msm_vpe_output_plane_cfg { + uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN]; +}; + +struct msm_vpe_input_plane_update_cfg { + uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN]; +}; + +struct msm_vpe_scaler_cfg { + uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN]; +}; + +struct msm_vpe_flush_frame_buffer { + uint32_t src_buf_handle; + uint32_t dest_buf_handle; + int path; +}; + +struct msm_mctl_pp_frame_buffer { + uint32_t buf_handle; + int path; +}; +struct msm_mctl_pp_divert_pp { + int path; + int enable; +}; +struct msm_vpe_clock_rate { + uint32_t rate; +}; + +#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0) +#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1) + +#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0) +#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1) +#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2) +#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3) +#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4) +#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5) +#define VFE_OUTPUTS_PREVIEW BIT(6) +#define VFE_OUTPUTS_VIDEO BIT(7) +#define VFE_OUTPUTS_RAW BIT(8) +#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9) +#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10) +#define VFE_OUTPUTS_RDI0 BIT(11) +#define VFE_OUTPUTS_RDI1 BIT(12) + +struct msm_frame_info { + uint32_t inst_handle; + uint32_t path; +}; + +#endif /*__UAPI_MSM_ISP_H__*/ + diff --git a/include/uapi/media/msm_jpeg.h b/include/uapi/media/msm_jpeg.h new file mode 100644 index 000000000000..897a18083650 --- /dev/null +++ b/include/uapi/media/msm_jpeg.h @@ -0,0 +1,125 @@ +#ifndef __UAPI_LINUX_MSM_JPEG_H +#define __UAPI_LINUX_MSM_JPEG_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +#define OUTPUT_H2V1 0 +#define OUTPUT_H2V2 1 +#define OUTPUT_BYTE 6 + +#define MSM_JPEG_IOCTL_MAGIC 'g' + +#define MSM_JPEG_IOCTL_GET_HW_VERSION \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 1, struct msm_jpeg_hw_cmd) + +#define MSM_JPEG_IOCTL_RESET \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 2, struct msm_jpeg_ctrl_cmd) + +#define MSM_JPEG_IOCTL_STOP \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 3, struct msm_jpeg_hw_cmds) + +#define MSM_JPEG_IOCTL_START \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 4, struct msm_jpeg_hw_cmds) + +#define MSM_JPEG_IOCTL_INPUT_BUF_ENQUEUE \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 5, struct msm_jpeg_buf) + +#define MSM_JPEG_IOCTL_INPUT_GET \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 6, struct msm_jpeg_buf) + +#define MSM_JPEG_IOCTL_INPUT_GET_UNBLOCK \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 7, int) + +#define MSM_JPEG_IOCTL_OUTPUT_BUF_ENQUEUE \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 8, struct msm_jpeg_buf) + +#define MSM_JPEG_IOCTL_OUTPUT_GET \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 9, struct msm_jpeg_buf) + +#define MSM_JPEG_IOCTL_OUTPUT_GET_UNBLOCK \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 10, int) + +#define MSM_JPEG_IOCTL_EVT_GET \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 11, struct msm_jpeg_ctrl_cmd) + +#define MSM_JPEG_IOCTL_EVT_GET_UNBLOCK \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 12, int) + +#define MSM_JPEG_IOCTL_HW_CMD \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 13, struct msm_jpeg_hw_cmd) + +#define MSM_JPEG_IOCTL_HW_CMDS \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 14, struct msm_jpeg_hw_cmds) + +#define MSM_JPEG_IOCTL_TEST_DUMP_REGION \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 15, unsigned long) + +#define MSM_JPEG_IOCTL_SET_CLK_RATE \ + _IOW(MSM_JPEG_IOCTL_MAGIC, 16, unsigned int) + +#define MSM_JPEG_MODE_REALTIME_ENCODE 0 +#define MSM_JPEG_MODE_OFFLINE_ENCODE 1 +#define MSM_JPEG_MODE_REALTIME_ROTATION 2 +#define MSM_JPEG_MODE_OFFLINE_ROTATION 3 + +struct msm_jpeg_ctrl_cmd { + uint32_t type; + uint32_t len; + void *value; +}; + +#define MSM_JPEG_EVT_RESET 0 +#define MSM_JPEG_EVT_SESSION_DONE 1 +#define MSM_JPEG_EVT_ERR 2 + +struct msm_jpeg_buf { + uint32_t type; + int fd; + + void *vaddr; + + uint32_t y_off; + uint32_t y_len; + uint32_t framedone_len; + + uint32_t cbcr_off; + uint32_t cbcr_len; + + uint32_t num_of_mcu_rows; + uint32_t offset; + uint32_t pln2_off; + uint32_t pln2_len; +}; + +#define MSM_JPEG_HW_CMD_TYPE_READ 0 +#define MSM_JPEG_HW_CMD_TYPE_WRITE 1 +#define MSM_JPEG_HW_CMD_TYPE_WRITE_OR 2 +#define MSM_JPEG_HW_CMD_TYPE_UWAIT 3 +#define MSM_JPEG_HW_CMD_TYPE_MWAIT 4 +#define MSM_JPEG_HW_CMD_TYPE_MDELAY 5 +#define MSM_JPEG_HW_CMD_TYPE_UDELAY 6 +struct msm_jpeg_hw_cmd { + + uint32_t type:4; + + /* n microseconds of timeout for WAIT */ + /* n microseconds of time for DELAY */ + /* repeat n times for READ/WRITE */ + /* max is 0xFFF, 4095 */ + uint32_t n:12; + uint32_t offset:16; + uint32_t mask; + union { + uint32_t data; /* for single READ/WRITE/WAIT, n = 1 */ + uint32_t *pdata; /* for multiple READ/WRITE/WAIT, n > 1 */ + }; +}; + +struct msm_jpeg_hw_cmds { + uint32_t m; /* number of elements in the hw_cmd array */ + struct msm_jpeg_hw_cmd hw_cmd[1]; +}; + +#endif + diff --git a/include/uapi/media/msm_jpeg_dma.h b/include/uapi/media/msm_jpeg_dma.h new file mode 100644 index 000000000000..6b664566cb4c --- /dev/null +++ b/include/uapi/media/msm_jpeg_dma.h @@ -0,0 +1,28 @@ +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __UAPI_MSM_JPEG_DMA__ +#define __UAPI_MSM_JPEG_DMA__ + +#include <linux/videodev2.h> + +/* msm jpeg dma control ID's */ +#define V4L2_CID_JPEG_DMA_SPEED (V4L2_CID_PRIVATE_BASE) +#define V4L2_CID_JPEG_DMA_MAX_DOWN_SCALE (V4L2_CID_PRIVATE_BASE + 1) + +/* msm_jpeg_dma_buf */ +struct msm_jpeg_dma_buff { + int32_t fd; + uint32_t offset; +}; + +#endif /* __UAPI_MSM_JPEG_DMA__ */ diff --git a/include/uapi/media/msm_media_info.h b/include/uapi/media/msm_media_info.h new file mode 100644 index 000000000000..13bee7a56a0e --- /dev/null +++ b/include/uapi/media/msm_media_info.h @@ -0,0 +1,1054 @@ +#ifndef __MEDIA_INFO_H__ +#define __MEDIA_INFO_H__ + +#ifndef MSM_MEDIA_ALIGN +#define MSM_MEDIA_ALIGN(__sz, __align) (((__align) & ((__align) - 1)) ?\ + ((((__sz) + (__align) - 1) / (__align)) * (__align)) :\ + (((__sz) + (__align) - 1) & (~((__align) - 1)))) +#endif + +#ifndef MSM_MEDIA_ROUNDUP +#define MSM_MEDIA_ROUNDUP(__sz, __r) (((__sz) + ((__r) - 1)) / (__r)) +#endif + +#ifndef MSM_MEDIA_MAX +#define MSM_MEDIA_MAX(__a, __b) ((__a) > (__b)?(__a):(__b)) +#endif + +enum color_fmts { + /* Venus NV12: + * YUV 4:2:0 image with a plane of 8 bit Y samples followed + * by an interleaved U/V plane containing 8 bit 2x2 subsampled + * colour difference samples. + * + * <-------- Y/UV_Stride --------> + * <------- Width -------> + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * U V U V U V U V U V U V . . . . ^ + * U V U V U V U V U V U V . . . . | + * U V U V U V U V U V U V . . . . | + * U V U V U V U V U V U V . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . --> Buffer size alignment + * + * Y_Stride : Width aligned to 128 + * UV_Stride : Width aligned to 128 + * Y_Scanlines: Height aligned to 32 + * UV_Scanlines: Height/2 aligned to 16 + * Extradata: Arbitrary (software-imposed) padding + * Total size = align((Y_Stride * Y_Scanlines + * + UV_Stride * UV_Scanlines + * + max(Extradata, Y_Stride * 8), 4096) + */ + COLOR_FMT_NV12, + + /* Venus NV21: + * YUV 4:2:0 image with a plane of 8 bit Y samples followed + * by an interleaved V/U plane containing 8 bit 2x2 subsampled + * colour difference samples. + * + * <-------- Y/UV_Stride --------> + * <------- Width -------> + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * V U V U V U V U V U V U . . . . ^ + * V U V U V U V U V U V U . . . . | + * V U V U V U V U V U V U . . . . | + * V U V U V U V U V U V U . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . --> Padding & Buffer size alignment + * + * Y_Stride : Width aligned to 128 + * UV_Stride : Width aligned to 128 + * Y_Scanlines: Height aligned to 32 + * UV_Scanlines: Height/2 aligned to 16 + * Extradata: Arbitrary (software-imposed) padding + * Total size = align((Y_Stride * Y_Scanlines + * + UV_Stride * UV_Scanlines + * + max(Extradata, Y_Stride * 8), 4096) + */ + COLOR_FMT_NV21, + /* Venus NV12_MVTB: + * Two YUV 4:2:0 images/views one after the other + * in a top-bottom layout, same as NV12 + * with a plane of 8 bit Y samples followed + * by an interleaved U/V plane containing 8 bit 2x2 subsampled + * colour difference samples. + * + * + * <-------- Y/UV_Stride --------> + * <------- Width -------> + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | | + * . . . . . . . . . . . . . . . . | View_1 + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V | + * U V U V U V U V U V U V . . . . ^ | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . UV_Scanlines | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V V + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . ^ ^ ^ + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . Height | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | Y_Scanlines | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . | | | + * Y Y Y Y Y Y Y Y Y Y Y Y . . . . V | | + * . . . . . . . . . . . . . . . . | View_2 + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V | + * U V U V U V U V U V U V . . . . ^ | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . | | + * U V U V U V U V U V U V . . . . UV_Scanlines | + * . . . . . . . . . . . . . . . . | | + * . . . . . . . . . . . . . . . . V V + * . . . . . . . . . . . . . . . . --> Buffer size alignment + * + * Y_Stride : Width aligned to 128 + * UV_Stride : Width aligned to 128 + * Y_Scanlines: Height aligned to 32 + * UV_Scanlines: Height/2 aligned to 16 + * View_1 begin at: 0 (zero) + * View_2 begin at: Y_Stride * Y_Scanlines + UV_Stride * UV_Scanlines + * Extradata: Arbitrary (software-imposed) padding + * Total size = align((2*(Y_Stride * Y_Scanlines) + * + 2*(UV_Stride * UV_Scanlines) + Extradata), 4096) + */ + COLOR_FMT_NV12_MVTB, + /* Venus NV12 UBWC: + * Compressed Macro-tile format for NV12. + * Contains 4 planes in the following order - + * (A) Y_Meta_Plane + * (B) Y_UBWC_Plane + * (C) UV_Meta_Plane + * (D) UV_UBWC_Plane + * + * Y_Meta_Plane consists of meta information to decode compressed + * tile data in Y_UBWC_Plane. + * Y_UBWC_Plane consists of Y data in compressed macro-tile format. + * UBWC decoder block will use the Y_Meta_Plane data together with + * Y_UBWC_Plane data to produce loss-less uncompressed 8 bit Y samples. + * + * UV_Meta_Plane consists of meta information to decode compressed + * tile data in UV_UBWC_Plane. + * UV_UBWC_Plane consists of UV data in compressed macro-tile format. + * UBWC decoder block will use UV_Meta_Plane data together with + * UV_UBWC_Plane data to produce loss-less uncompressed 8 bit 2x2 + * subsampled color difference samples. + * + * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable + * and randomly accessible. There is no dependency between tiles. + * + * <----- Y_Meta_Stride ----> + * <-------- Width ------> + * M M M M M M M M M M M M . . ^ ^ + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . Height | + * M M M M M M M M M M M M . . | Meta_Y_Scanlines + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . V | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . V + * <--Compressed tile Y Stride---> + * <------- Width -------> + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . . . V + * <----- UV_Meta_Stride ----> + * M M M M M M M M M M M M . . ^ + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . M_UV_Scanlines + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * <--Compressed tile UV Stride---> + * U* V* U* V* U* V* U* V* . . . . ^ + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * + * Y_Stride = align(Width, 128) + * UV_Stride = align(Width, 128) + * Y_Scanlines = align(Height, 32) + * UV_Scanlines = align(Height/2, 16) + * Y_UBWC_Plane_size = align(Y_Stride * Y_Scanlines, 4096) + * UV_UBWC_Plane_size = align(UV_Stride * UV_Scanlines, 4096) + * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) + * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) + * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) + * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) + * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) + * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) + * Extradata = 16k + * + * Total size = align( Y_UBWC_Plane_size + UV_UBWC_Plane_size + + * Y_Meta_Plane_size + UV_Meta_Plane_size + * + max(Extradata, Y_Stride * 64), 4096) + */ + COLOR_FMT_NV12_UBWC, + /* Venus NV12 10-bit UBWC: + * Compressed Macro-tile format for NV12. + * Contains 4 planes in the following order - + * (A) Y_Meta_Plane + * (B) Y_UBWC_Plane + * (C) UV_Meta_Plane + * (D) UV_UBWC_Plane + * + * Y_Meta_Plane consists of meta information to decode compressed + * tile data in Y_UBWC_Plane. + * Y_UBWC_Plane consists of Y data in compressed macro-tile format. + * UBWC decoder block will use the Y_Meta_Plane data together with + * Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples. + * + * UV_Meta_Plane consists of meta information to decode compressed + * tile data in UV_UBWC_Plane. + * UV_UBWC_Plane consists of UV data in compressed macro-tile format. + * UBWC decoder block will use UV_Meta_Plane data together with + * UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2 + * subsampled color difference samples. + * + * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable + * and randomly accessible. There is no dependency between tiles. + * + * <----- Y_Meta_Stride -----> + * <-------- Width ------> + * M M M M M M M M M M M M . . ^ ^ + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . Height | + * M M M M M M M M M M M M . . | Meta_Y_Scanlines + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . V | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . V + * <--Compressed tile Y Stride---> + * <------- Width -------> + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . . . V + * <----- UV_Meta_Stride ----> + * M M M M M M M M M M M M . . ^ + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . M_UV_Scanlines + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * <--Compressed tile UV Stride---> + * U* V* U* V* U* V* U* V* . . . . ^ + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * + * + * Y_Stride = align(Width * 4/3, 128) + * UV_Stride = align(Width * 4/3, 128) + * Y_Scanlines = align(Height, 32) + * UV_Scanlines = align(Height/2, 16) + * Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096) + * UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096) + * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) + * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) + * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) + * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) + * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) + * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) + * Extradata = 16k + * + * Total size = align(Y_UBWC_Plane_size + UV_UBWC_Plane_size + + * Y_Meta_Plane_size + UV_Meta_Plane_size + * + max(Extradata, Y_Stride * 64), 4096) + */ + COLOR_FMT_NV12_BPP10_UBWC, + /* Venus RGBA8888 format: + * Contains 1 plane in the following order - + * (A) RGBA plane + * + * <-------- RGB_Stride --------> + * <------- Width -------> + * R R R R R R R R R R R R . . . . ^ ^ + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . Height | + * R R R R R R R R R R R R . . . . | RGB_Scanlines + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * + * RGB_Stride = align(Width * 4, 128) + * RGB_Scanlines = align(Height, 32) + * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) + * Extradata = 8k + * + * Total size = align(RGB_Plane_size + Extradata, 4096) + */ + COLOR_FMT_RGBA8888, + /* Venus RGBA8888 UBWC format: + * Contains 2 planes in the following order - + * (A) Meta plane + * (B) RGBA plane + * + * <--- RGB_Meta_Stride ----> + * <-------- Width ------> + * M M M M M M M M M M M M . . ^ ^ + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . Height | + * M M M M M M M M M M M M . . | Meta_RGB_Scanlines + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . V | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . V + * <-------- RGB_Stride --------> + * <------- Width -------> + * R R R R R R R R R R R R . . . . ^ ^ + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . Height | + * R R R R R R R R R R R R . . . . | RGB_Scanlines + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . . . V + * + * RGB_Stride = align(Width * 4, 128) + * RGB_Scanlines = align(Height, 32) + * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) + * RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64) + * RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16) + * RGB_Meta_Plane_size = align(RGB_Meta_Stride * + * RGB_Meta_Scanlines, 4096) + * Extradata = 8k + * + * Total size = align(RGB_Meta_Plane_size + RGB_Plane_size + + * Extradata, 4096) + */ + COLOR_FMT_RGBA8888_UBWC, + /* Venus RGBA1010102 UBWC format: + * Contains 2 planes in the following order - + * (A) Meta plane + * (B) RGBA plane + * + * <--- RGB_Meta_Stride ----> + * <-------- Width ------> + * M M M M M M M M M M M M . . ^ ^ + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . Height | + * M M M M M M M M M M M M . . | Meta_RGB_Scanlines + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . V | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . V + * <-------- RGB_Stride --------> + * <------- Width -------> + * R R R R R R R R R R R R . . . . ^ ^ + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . Height | + * R R R R R R R R R R R R . . . . | RGB_Scanlines + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . . . V + * + * RGB_Stride = align(Width * 4, 256) + * RGB_Scanlines = align(Height, 16) + * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) + * RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64) + * RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16) + * RGB_Meta_Plane_size = align(RGB_Meta_Stride * + * RGB_Meta_Scanlines, 4096) + * Extradata = 8k + * + * Total size = align(RGB_Meta_Plane_size + RGB_Plane_size + + * Extradata, 4096) + */ + COLOR_FMT_RGBA1010102_UBWC, + /* Venus RGB565 UBWC format: + * Contains 2 planes in the following order - + * (A) Meta plane + * (B) RGB plane + * + * <--- RGB_Meta_Stride ----> + * <-------- Width ------> + * M M M M M M M M M M M M . . ^ ^ + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . Height | + * M M M M M M M M M M M M . . | Meta_RGB_Scanlines + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . V | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . V + * <-------- RGB_Stride --------> + * <------- Width -------> + * R R R R R R R R R R R R . . . . ^ ^ + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . Height | + * R R R R R R R R R R R R . . . . | RGB_Scanlines + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . | | + * R R R R R R R R R R R R . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . . . V + * + * RGB_Stride = align(Width * 2, 128) + * RGB_Scanlines = align(Height, 16) + * RGB_Plane_size = align(RGB_Stride * RGB_Scanlines, 4096) + * RGB_Meta_Stride = align(roundup(Width, RGB_TileWidth), 64) + * RGB_Meta_Scanline = align(roundup(Height, RGB_TileHeight), 16) + * RGB_Meta_Plane_size = align(RGB_Meta_Stride * + * RGB_Meta_Scanlines, 4096) + * Extradata = 8k + * + * Total size = align(RGB_Meta_Plane_size + RGB_Plane_size + + * Extradata, 4096) + */ + COLOR_FMT_RGB565_UBWC, + /* P010 UBWC: + * Compressed Macro-tile format for NV12. + * Contains 4 planes in the following order - + * (A) Y_Meta_Plane + * (B) Y_UBWC_Plane + * (C) UV_Meta_Plane + * (D) UV_UBWC_Plane + * + * Y_Meta_Plane consists of meta information to decode compressed + * tile data in Y_UBWC_Plane. + * Y_UBWC_Plane consists of Y data in compressed macro-tile format. + * UBWC decoder block will use the Y_Meta_Plane data together with + * Y_UBWC_Plane data to produce loss-less uncompressed 10 bit Y samples. + * + * UV_Meta_Plane consists of meta information to decode compressed + * tile data in UV_UBWC_Plane. + * UV_UBWC_Plane consists of UV data in compressed macro-tile format. + * UBWC decoder block will use UV_Meta_Plane data together with + * UV_UBWC_Plane data to produce loss-less uncompressed 10 bit 2x2 + * subsampled color difference samples. + * + * Each tile in Y_UBWC_Plane/UV_UBWC_Plane is independently decodable + * and randomly accessible. There is no dependency between tiles. + * + * <----- Y_Meta_Stride -----> + * <-------- Width ------> + * M M M M M M M M M M M M . . ^ ^ + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . Height | + * M M M M M M M M M M M M . . | Meta_Y_Scanlines + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . | | + * M M M M M M M M M M M M . . V | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . V + * <--Compressed tile Y Stride---> + * <------- Width -------> + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . ^ ^ + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . Height | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | Macro_tile_Y_Scanlines + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . | | + * Y* Y* Y* Y* Y* Y* Y* Y* . . . . V | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * . . . . . . . . . . . . . . . . V + * <----- UV_Meta_Stride ----> + * M M M M M M M M M M M M . . ^ + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . | + * M M M M M M M M M M M M . . M_UV_Scanlines + * . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * <--Compressed tile UV Stride---> + * U* V* U* V* U* V* U* V* . . . . ^ + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . | + * U* V* U* V* U* V* U* V* . . . . UV_Scanlines + * . . . . . . . . . . . . . . . . | + * . . . . . . . . . . . . . . . . V + * . . . . . . . . . . . . . . . . -------> Buffer size aligned to 4k + * + * + * Y_Stride = align(Width * 2, 256) + * UV_Stride = align(Width * 2, 256) + * Y_Scanlines = align(Height, 16) + * UV_Scanlines = align(Height/2, 16) + * Y_UBWC_Plane_Size = align(Y_Stride * Y_Scanlines, 4096) + * UV_UBWC_Plane_Size = align(UV_Stride * UV_Scanlines, 4096) + * Y_Meta_Stride = align(roundup(Width, Y_TileWidth), 64) + * Y_Meta_Scanlines = align(roundup(Height, Y_TileHeight), 16) + * Y_Meta_Plane_size = align(Y_Meta_Stride * Y_Meta_Scanlines, 4096) + * UV_Meta_Stride = align(roundup(Width, UV_TileWidth), 64) + * UV_Meta_Scanlines = align(roundup(Height, UV_TileHeight), 16) + * UV_Meta_Plane_size = align(UV_Meta_Stride * UV_Meta_Scanlines, 4096) + * Extradata = 8k + * + * Total size = align(Y_UBWC_Plane_size + UV_UBWC_Plane_size + + * Y_Meta_Plane_size + UV_Meta_Plane_size + * + max(Extradata, Y_Stride * 48), 4096) + */ + COLOR_FMT_P010_UBWC, +}; + +#define COLOR_FMT_RGBA1010102_UBWC COLOR_FMT_RGBA1010102_UBWC +#define COLOR_FMT_RGB565_UBWC COLOR_FMT_RGB565_UBWC +#define COLOR_FMT_P010_UBWC COLOR_FMT_P010_UBWC + +static inline unsigned int VENUS_EXTRADATA_SIZE(int width, int height) +{ + (void)height; + (void)width; + + /* + * In the future, calculate the size based on the w/h but just + * hardcode it for now since 16K satisfies all current usecases. + */ + return 16 * 1024; +} + +static inline unsigned int VENUS_Y_STRIDE(int color_fmt, int width) +{ + unsigned int alignment, stride = 0; + + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_UBWC: + alignment = 128; + stride = MSM_MEDIA_ALIGN(width, alignment); + break; + case COLOR_FMT_NV12_BPP10_UBWC: + alignment = 256; + stride = MSM_MEDIA_ALIGN(width, 192); + stride = MSM_MEDIA_ALIGN(stride * 4/3, alignment); + break; + case COLOR_FMT_P010_UBWC: + alignment = 256; + stride = MSM_MEDIA_ALIGN(width * 2, alignment); + break; + default: + break; + } +invalid_input: + return stride; +} + +static inline unsigned int VENUS_UV_STRIDE(int color_fmt, int width) +{ + unsigned int alignment, stride = 0; + + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_UBWC: + alignment = 128; + stride = MSM_MEDIA_ALIGN(width, alignment); + break; + case COLOR_FMT_NV12_BPP10_UBWC: + alignment = 256; + stride = MSM_MEDIA_ALIGN(width, 192); + stride = MSM_MEDIA_ALIGN(stride * 4/3, alignment); + break; + case COLOR_FMT_P010_UBWC: + alignment = 256; + stride = MSM_MEDIA_ALIGN(width * 2, alignment); + break; + default: + break; + } +invalid_input: + return stride; +} + +static inline unsigned int VENUS_Y_SCANLINES(int color_fmt, int height) +{ + unsigned int alignment, sclines = 0; + + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_UBWC: + alignment = 32; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + case COLOR_FMT_P010_UBWC: + alignment = 16; + break; + default: + return 0; + } + sclines = MSM_MEDIA_ALIGN(height, alignment); +invalid_input: + return sclines; +} + +static inline unsigned int VENUS_UV_SCANLINES(int color_fmt, int height) +{ + unsigned int alignment, sclines = 0; + + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + case COLOR_FMT_NV12_MVTB: + case COLOR_FMT_NV12_BPP10_UBWC: + case COLOR_FMT_P010_UBWC: + alignment = 16; + break; + case COLOR_FMT_NV12_UBWC: + alignment = 32; + break; + default: + goto invalid_input; + } + + sclines = MSM_MEDIA_ALIGN(height / 2, alignment); + +invalid_input: + return sclines; +} + +static inline unsigned int VENUS_Y_META_STRIDE(int color_fmt, int width) +{ + int y_tile_width = 0, y_meta_stride = 0; + + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + case COLOR_FMT_P010_UBWC: + y_tile_width = 32; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + y_tile_width = 48; + break; + default: + goto invalid_input; + } + + y_meta_stride = MSM_MEDIA_ROUNDUP(width, y_tile_width); + y_meta_stride = MSM_MEDIA_ALIGN(y_meta_stride, 64); + +invalid_input: + return y_meta_stride; +} + +static inline unsigned int VENUS_Y_META_SCANLINES(int color_fmt, int height) +{ + int y_tile_height = 0, y_meta_scanlines = 0; + + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + y_tile_height = 8; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + case COLOR_FMT_P010_UBWC: + y_tile_height = 4; + break; + default: + goto invalid_input; + } + + y_meta_scanlines = MSM_MEDIA_ROUNDUP(height, y_tile_height); + y_meta_scanlines = MSM_MEDIA_ALIGN(y_meta_scanlines, 16); + +invalid_input: + return y_meta_scanlines; +} + +static inline unsigned int VENUS_UV_META_STRIDE(int color_fmt, int width) +{ + int uv_tile_width = 0, uv_meta_stride = 0; + + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + case COLOR_FMT_P010_UBWC: + uv_tile_width = 16; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + uv_tile_width = 24; + break; + default: + goto invalid_input; + } + + uv_meta_stride = MSM_MEDIA_ROUNDUP(width / 2, uv_tile_width); + uv_meta_stride = MSM_MEDIA_ALIGN(uv_meta_stride, 64); + +invalid_input: + return uv_meta_stride; +} + +static inline unsigned int VENUS_UV_META_SCANLINES(int color_fmt, int height) +{ + int uv_tile_height = 0, uv_meta_scanlines = 0; + + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_NV12_UBWC: + uv_tile_height = 8; + break; + case COLOR_FMT_NV12_BPP10_UBWC: + case COLOR_FMT_P010_UBWC: + uv_tile_height = 4; + break; + default: + goto invalid_input; + } + + uv_meta_scanlines = MSM_MEDIA_ROUNDUP(height / 2, uv_tile_height); + uv_meta_scanlines = MSM_MEDIA_ALIGN(uv_meta_scanlines, 16); + +invalid_input: + return uv_meta_scanlines; +} + +static inline unsigned int VENUS_RGB_STRIDE(int color_fmt, int width) +{ + unsigned int alignment = 0, stride = 0, bpp = 4; + + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_RGBA8888: + alignment = 128; + break; + case COLOR_FMT_RGB565_UBWC: + alignment = 128; + bpp = 2; + break; + case COLOR_FMT_RGBA8888_UBWC: + case COLOR_FMT_RGBA1010102_UBWC: + alignment = 256; + break; + default: + goto invalid_input; + } + + stride = MSM_MEDIA_ALIGN(width * bpp, alignment); + +invalid_input: + return stride; +} + +static inline unsigned int VENUS_RGB_SCANLINES(int color_fmt, int height) +{ + unsigned int alignment = 0, scanlines = 0; + + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_RGBA8888: + alignment = 32; + break; + case COLOR_FMT_RGBA8888_UBWC: + case COLOR_FMT_RGBA1010102_UBWC: + case COLOR_FMT_RGB565_UBWC: + alignment = 16; + break; + default: + goto invalid_input; + } + + scanlines = MSM_MEDIA_ALIGN(height, alignment); + +invalid_input: + return scanlines; +} + +static inline unsigned int VENUS_RGB_META_STRIDE(int color_fmt, int width) +{ + int rgb_tile_width = 0, rgb_meta_stride = 0; + + if (!width) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_RGBA8888_UBWC: + case COLOR_FMT_RGBA1010102_UBWC: + case COLOR_FMT_RGB565_UBWC: + rgb_tile_width = 16; + break; + default: + goto invalid_input; + } + + rgb_meta_stride = MSM_MEDIA_ROUNDUP(width, rgb_tile_width); + rgb_meta_stride = MSM_MEDIA_ALIGN(rgb_meta_stride, 64); + +invalid_input: + return rgb_meta_stride; +} + +static inline unsigned int VENUS_RGB_META_SCANLINES(int color_fmt, int height) +{ + int rgb_tile_height = 0, rgb_meta_scanlines = 0; + + if (!height) + goto invalid_input; + + switch (color_fmt) { + case COLOR_FMT_RGBA8888_UBWC: + case COLOR_FMT_RGBA1010102_UBWC: + case COLOR_FMT_RGB565_UBWC: + rgb_tile_height = 4; + break; + default: + goto invalid_input; + } + + rgb_meta_scanlines = MSM_MEDIA_ROUNDUP(height, rgb_tile_height); + rgb_meta_scanlines = MSM_MEDIA_ALIGN(rgb_meta_scanlines, 16); + +invalid_input: + return rgb_meta_scanlines; +} + +static inline unsigned int VENUS_BUFFER_SIZE( + int color_fmt, int width, int height) +{ + const unsigned int extra_size = VENUS_EXTRADATA_SIZE(width, height); + unsigned int uv_alignment = 0, size = 0; + unsigned int y_plane, uv_plane, y_stride, + uv_stride, y_sclines, uv_sclines; + unsigned int y_ubwc_plane = 0, uv_ubwc_plane = 0; + unsigned int y_meta_stride = 0, y_meta_scanlines = 0; + unsigned int uv_meta_stride = 0, uv_meta_scanlines = 0; + unsigned int y_meta_plane = 0, uv_meta_plane = 0; + unsigned int rgb_stride = 0, rgb_scanlines = 0; + unsigned int rgb_plane = 0, rgb_ubwc_plane = 0, rgb_meta_plane = 0; + unsigned int rgb_meta_stride = 0, rgb_meta_scanlines = 0; + + if (!width || !height) + goto invalid_input; + + y_stride = VENUS_Y_STRIDE(color_fmt, width); + uv_stride = VENUS_UV_STRIDE(color_fmt, width); + y_sclines = VENUS_Y_SCANLINES(color_fmt, height); + uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); + rgb_stride = VENUS_RGB_STRIDE(color_fmt, width); + rgb_scanlines = VENUS_RGB_SCANLINES(color_fmt, height); + + switch (color_fmt) { + case COLOR_FMT_NV21: + case COLOR_FMT_NV12: + uv_alignment = 4096; + y_plane = y_stride * y_sclines; + uv_plane = uv_stride * uv_sclines + uv_alignment; + size = y_plane + uv_plane + + MSM_MEDIA_MAX(extra_size, 8 * y_stride); + size = MSM_MEDIA_ALIGN(size, 4096); + break; + case COLOR_FMT_NV12_MVTB: + uv_alignment = 4096; + y_plane = y_stride * y_sclines; + uv_plane = uv_stride * uv_sclines + uv_alignment; + size = y_plane + uv_plane; + size = 2 * size + extra_size; + size = MSM_MEDIA_ALIGN(size, 4096); + break; + case COLOR_FMT_NV12_UBWC: + case COLOR_FMT_NV12_BPP10_UBWC: + y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); + uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); + y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); + y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height); + y_meta_plane = MSM_MEDIA_ALIGN( + y_meta_stride * y_meta_scanlines, 4096); + uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); + uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height); + uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * + uv_meta_scanlines, 4096); + + size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane + + uv_meta_plane + MSM_MEDIA_MAX(extra_size, + 64 * y_stride); + size = MSM_MEDIA_ALIGN(size, 4096); + break; + case COLOR_FMT_P010_UBWC: + y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); + uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); + y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); + y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height); + y_meta_plane = MSM_MEDIA_ALIGN( + y_meta_stride * y_meta_scanlines, 4096); + uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); + uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height); + uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * + uv_meta_scanlines, 4096); + + size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane + + uv_meta_plane; + size = MSM_MEDIA_ALIGN(size, 4096); + break; + case COLOR_FMT_RGBA8888: + rgb_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines, 4096); + size = rgb_plane; + size = MSM_MEDIA_ALIGN(size, 4096); + break; + case COLOR_FMT_RGBA8888_UBWC: + rgb_ubwc_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines, + 4096); + rgb_meta_stride = VENUS_RGB_META_STRIDE(color_fmt, width); + rgb_meta_scanlines = VENUS_RGB_META_SCANLINES(color_fmt, + height); + rgb_meta_plane = MSM_MEDIA_ALIGN(rgb_meta_stride * + rgb_meta_scanlines, 4096); + size = rgb_ubwc_plane + rgb_meta_plane; + size = MSM_MEDIA_ALIGN(size, 4096); + break; + default: + break; + } +invalid_input: + return size; +} + +static inline unsigned int VENUS_VIEW2_OFFSET( + int color_fmt, int width, int height) +{ + unsigned int offset = 0; + unsigned int y_plane, uv_plane, y_stride, + uv_stride, y_sclines, uv_sclines; + if (!width || !height) + goto invalid_input; + + y_stride = VENUS_Y_STRIDE(color_fmt, width); + uv_stride = VENUS_UV_STRIDE(color_fmt, width); + y_sclines = VENUS_Y_SCANLINES(color_fmt, height); + uv_sclines = VENUS_UV_SCANLINES(color_fmt, height); + switch (color_fmt) { + case COLOR_FMT_NV12_MVTB: + y_plane = y_stride * y_sclines; + uv_plane = uv_stride * uv_sclines; + offset = y_plane + uv_plane; + break; + default: + break; + } +invalid_input: + return offset; +} + +#endif diff --git a/include/uapi/media/msm_mercury.h b/include/uapi/media/msm_mercury.h new file mode 100644 index 000000000000..607a8c8d5651 --- /dev/null +++ b/include/uapi/media/msm_mercury.h @@ -0,0 +1,119 @@ +#ifndef __UAPI_MSM_MERCURY_H +#define __UAPI_MSM_MERCURY_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +#define MSM_MERCURY_HW_VERSION_REG 0x0004/* this offset does not exist in HW*/ + +#define OUTPUT_H2V1 0 +#define OUTPUT_H2V2 1 +#define OUTPUT_BYTE 6 + +#define MSM_MERCURY_MODE_REALTIME_ENCODE 0 +#define MSM_MERCURY_MODE_OFFLINE_ENCODE 1 +#define MSM_MERCURY_MODE_REALTIME_ROTATION 2 +#define MSM_MERCURY_MODE_OFFLINE_ROTATION 3 + +#define MSM_MERCURY_EVT_RESET 1 +#define MSM_MERCURY_EVT_FRAMEDONE 2 +#define MSM_MERCURY_EVT_ERR 3 +#define MSM_MERCURY_EVT_UNBLOCK 4 + +#define MSM_MERCURY_HW_CMD_TYPE_READ 0 +#define MSM_MERCURY_HW_CMD_TYPE_WRITE 1 +#define MSM_MERCURY_HW_CMD_TYPE_WRITE_OR 2 +#define MSM_MERCURY_HW_CMD_TYPE_UWAIT 3 +#define MSM_MERCURY_HW_CMD_TYPE_MWAIT 4 +#define MSM_MERCURY_HW_CMD_TYPE_MDELAY 5 +#define MSM_MERCURY_HW_CMD_TYPE_UDELAY 6 + +#define MSM_MCR_IOCTL_MAGIC 'g' + +#define MSM_MCR_IOCTL_GET_HW_VERSION \ + _IOW(MSM_MCR_IOCTL_MAGIC, 1, struct msm_mercury_hw_cmd *) + +#define MSM_MCR_IOCTL_RESET \ + _IOW(MSM_MCR_IOCTL_MAGIC, 2, struct msm_mercury_ctrl_cmd *) + +#define MSM_MCR_IOCTL_STOP \ + _IOW(MSM_MCR_IOCTL_MAGIC, 3, struct msm_mercury_hw_cmds *) + +#define MSM_MCR_IOCTL_START \ + _IOW(MSM_MCR_IOCTL_MAGIC, 4, struct msm_mercury_hw_cmds *) + +#define MSM_MCR_IOCTL_INPUT_BUF_CFG \ + _IOW(MSM_MCR_IOCTL_MAGIC, 5, struct msm_mercury_buf *) + +#define MSM_MCR_IOCTL_INPUT_GET \ + _IOW(MSM_MCR_IOCTL_MAGIC, 6, struct msm_mercury_buf *) + +#define MSM_MCR_IOCTL_INPUT_GET_UNBLOCK \ + _IOW(MSM_MCR_IOCTL_MAGIC, 7, int) + +#define MSM_MCR_IOCTL_OUTPUT_BUF_CFG \ + _IOW(MSM_MCR_IOCTL_MAGIC, 8, struct msm_mercury_buf *) + +#define MSM_MCR_IOCTL_OUTPUT_GET \ + _IOW(MSM_MCR_IOCTL_MAGIC, 9, struct msm_mercury_buf *) + +#define MSM_MCR_IOCTL_OUTPUT_GET_UNBLOCK \ + _IOW(MSM_MCR_IOCTL_MAGIC, 10, int) + +#define MSM_MCR_IOCTL_EVT_GET \ + _IOW(MSM_MCR_IOCTL_MAGIC, 11, struct msm_mercury_ctrl_cmd *) + +#define MSM_MCR_IOCTL_EVT_GET_UNBLOCK \ + _IOW(MSM_MCR_IOCTL_MAGIC, 12, int) + +#define MSM_MCR_IOCTL_HW_CMD \ + _IOW(MSM_MCR_IOCTL_MAGIC, 13, struct msm_mercury_hw_cmd *) + +#define MSM_MCR_IOCTL_HW_CMDS \ + _IOW(MSM_MCR_IOCTL_MAGIC, 14, struct msm_mercury_hw_cmds *) + +#define MSM_MCR_IOCTL_TEST_DUMP_REGION \ + _IOW(MSM_MCR_IOCTL_MAGIC, 15, unsigned long) + +struct msm_mercury_ctrl_cmd { + uint32_t type; + uint32_t len; + void *value; +}; + +struct msm_mercury_buf { + uint32_t type; + int fd; + void *vaddr; + uint32_t y_off; + uint32_t y_len; + uint32_t framedone_len; + uint32_t cbcr_off; + uint32_t cbcr_len; + uint32_t num_of_mcu_rows; + uint32_t offset; +}; + +struct msm_mercury_hw_cmd { + + uint32_t type:4; + /* n microseconds of timeout for WAIT */ + /* n microseconds of time for DELAY */ + /* repeat n times for READ/WRITE */ + /* max is 0xFFF, 4095 */ + uint32_t n:12; + uint32_t offset:16; + uint32_t mask; + union { + /* for single READ/WRITE/WAIT, n = 1 */ + uint32_t data; + uint32_t *pdata;/* for multiple READ/WRITE/WAIT, n > 1 */ + }; +}; + +struct msm_mercury_hw_cmds { + uint32_t m; /* number of elements in the hw_cmd array */ + struct msm_mercury_hw_cmd hw_cmd[1]; +}; + +#endif /* __UAPI_MSM_MERCURY_H */ diff --git a/include/uapi/media/msm_sde_rotator.h b/include/uapi/media/msm_sde_rotator.h new file mode 100644 index 000000000000..6a92e530d59c --- /dev/null +++ b/include/uapi/media/msm_sde_rotator.h @@ -0,0 +1,114 @@ +#ifndef __UAPI_MSM_SDE_ROTATOR_H__ +#define __UAPI_MSM_SDE_ROTATOR_H__ + +#include <linux/videodev2.h> +#include <linux/types.h> +#include <linux/ioctl.h> + +/* SDE Rotator pixel format definitions */ +#define SDE_PIX_FMT_XRGB_8888 V4L2_PIX_FMT_XBGR32 +#define SDE_PIX_FMT_ARGB_8888 V4L2_PIX_FMT_ABGR32 +#define SDE_PIX_FMT_ABGR_8888 V4L2_PIX_FMT_SDE_ABGR_8888 +#define SDE_PIX_FMT_RGBA_8888 V4L2_PIX_FMT_SDE_RGBA_8888 +#define SDE_PIX_FMT_BGRA_8888 V4L2_PIX_FMT_ARGB32 +#define SDE_PIX_FMT_RGBX_8888 V4L2_PIX_FMT_SDE_RGBX_8888 +#define SDE_PIX_FMT_BGRX_8888 V4L2_PIX_FMT_XRGB32 +#define SDE_PIX_FMT_XBGR_8888 V4L2_PIX_FMT_SDE_XBGR_8888 +#define SDE_PIX_FMT_RGBA_5551 V4L2_PIX_FMT_SDE_RGBA_5551 +#define SDE_PIX_FMT_ARGB_1555 V4L2_PIX_FMT_ARGB555 +#define SDE_PIX_FMT_ABGR_1555 V4L2_PIX_FMT_SDE_ABGR_1555 +#define SDE_PIX_FMT_BGRA_5551 V4L2_PIX_FMT_SDE_BGRA_5551 +#define SDE_PIX_FMT_BGRX_5551 V4L2_PIX_FMT_SDE_BGRX_5551 +#define SDE_PIX_FMT_RGBX_5551 V4L2_PIX_FMT_SDE_RGBX_5551 +#define SDE_PIX_FMT_XBGR_1555 V4L2_PIX_FMT_SDE_XBGR_1555 +#define SDE_PIX_FMT_XRGB_1555 V4L2_PIX_FMT_XRGB555 +#define SDE_PIX_FMT_ARGB_4444 V4L2_PIX_FMT_ARGB444 +#define SDE_PIX_FMT_RGBA_4444 V4L2_PIX_FMT_SDE_RGBA_4444 +#define SDE_PIX_FMT_BGRA_4444 V4L2_PIX_FMT_SDE_BGRA_4444 +#define SDE_PIX_FMT_ABGR_4444 V4L2_PIX_FMT_SDE_ABGR_4444 +#define SDE_PIX_FMT_RGBX_4444 V4L2_PIX_FMT_SDE_RGBX_4444 +#define SDE_PIX_FMT_XRGB_4444 V4L2_PIX_FMT_XRGB444 +#define SDE_PIX_FMT_BGRX_4444 V4L2_PIX_FMT_SDE_BGRX_4444 +#define SDE_PIX_FMT_XBGR_4444 V4L2_PIX_FMT_SDE_XBGR_4444 +#define SDE_PIX_FMT_RGB_888 V4L2_PIX_FMT_RGB24 +#define SDE_PIX_FMT_BGR_888 V4L2_PIX_FMT_BGR24 +#define SDE_PIX_FMT_RGB_565 V4L2_PIX_FMT_RGB565 +#define SDE_PIX_FMT_BGR_565 V4L2_PIX_FMT_SDE_BGR_565 +#define SDE_PIX_FMT_Y_CB_CR_H2V2 V4L2_PIX_FMT_YUV420 +#define SDE_PIX_FMT_Y_CR_CB_H2V2 V4L2_PIX_FMT_YVU420 +#define SDE_PIX_FMT_Y_CR_CB_GH2V2 V4L2_PIX_FMT_SDE_Y_CR_CB_GH2V2 +#define SDE_PIX_FMT_Y_CBCR_H2V2 V4L2_PIX_FMT_NV12 +#define SDE_PIX_FMT_Y_CRCB_H2V2 V4L2_PIX_FMT_NV21 +#define SDE_PIX_FMT_Y_CBCR_H1V2 V4L2_PIX_FMT_SDE_Y_CBCR_H1V2 +#define SDE_PIX_FMT_Y_CRCB_H1V2 V4L2_PIX_FMT_SDE_Y_CRCB_H1V2 +#define SDE_PIX_FMT_Y_CBCR_H2V1 V4L2_PIX_FMT_NV16 +#define SDE_PIX_FMT_Y_CRCB_H2V1 V4L2_PIX_FMT_NV61 +#define SDE_PIX_FMT_YCBYCR_H2V1 V4L2_PIX_FMT_YUYV +#define SDE_PIX_FMT_Y_CBCR_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_VENUS +#define SDE_PIX_FMT_Y_CRCB_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CRCB_H2V2_VENUS +#define SDE_PIX_FMT_RGBA_8888_UBWC V4L2_PIX_FMT_RGBA8888_UBWC +#define SDE_PIX_FMT_RGBX_8888_UBWC V4L2_PIX_FMT_SDE_RGBX_8888_UBWC +#define SDE_PIX_FMT_RGB_565_UBWC V4L2_PIX_FMT_SDE_RGB_565_UBWC +#define SDE_PIX_FMT_Y_CBCR_H2V2_UBWC V4L2_PIX_FMT_NV12_UBWC +#define SDE_PIX_FMT_RGBA_1010102 V4L2_PIX_FMT_SDE_RGBA_1010102 +#define SDE_PIX_FMT_RGBX_1010102 V4L2_PIX_FMT_SDE_RGBX_1010102 +#define SDE_PIX_FMT_ARGB_2101010 V4L2_PIX_FMT_SDE_ARGB_2101010 +#define SDE_PIX_FMT_XRGB_2101010 V4L2_PIX_FMT_SDE_XRGB_2101010 +#define SDE_PIX_FMT_BGRA_1010102 V4L2_PIX_FMT_SDE_BGRA_1010102 +#define SDE_PIX_FMT_BGRX_1010102 V4L2_PIX_FMT_SDE_BGRX_1010102 +#define SDE_PIX_FMT_ABGR_2101010 V4L2_PIX_FMT_SDE_ABGR_2101010 +#define SDE_PIX_FMT_XBGR_2101010 V4L2_PIX_FMT_SDE_XBGR_2101010 +#define SDE_PIX_FMT_RGBA_1010102_UBWC V4L2_PIX_FMT_SDE_RGBA_1010102_UBWC +#define SDE_PIX_FMT_RGBX_1010102_UBWC V4L2_PIX_FMT_SDE_RGBX_1010102_UBWC +#define SDE_PIX_FMT_Y_CBCR_H2V2_P010 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010 +#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_TP10 +#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC V4L2_PIX_FMT_NV12_TP10_UBWC + +/** +* struct msm_sde_rotator_fence - v4l2 buffer fence info +* @index: id number of the buffer +* @type: enum v4l2_buf_type; buffer type +* @fd: file descriptor of the fence associated with this buffer +**/ +struct msm_sde_rotator_fence { + __u32 index; + __u32 type; + __s32 fd; + __u32 reserved[5]; +}; + +/** +* struct msm_sde_rotator_comp_ratio - v4l2 buffer compression ratio +* @index: id number of the buffer +* @type: enum v4l2_buf_type; buffer type +* @numer: numerator of the ratio +* @denom: denominator of the ratio +**/ +struct msm_sde_rotator_comp_ratio { + __u32 index; + __u32 type; + __u32 numer; + __u32 denom; + __u32 reserved[4]; +}; + +/* SDE Rotator private ioctl ID */ +#define VIDIOC_G_SDE_ROTATOR_FENCE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_sde_rotator_fence) +#define VIDIOC_S_SDE_ROTATOR_FENCE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_sde_rotator_fence) +#define VIDIOC_G_SDE_ROTATOR_COMP_RATIO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_sde_rotator_comp_ratio) +#define VIDIOC_S_SDE_ROTATOR_COMP_RATIO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_sde_rotator_comp_ratio) + +/* SDE Rotator private control ID's */ +#define V4L2_CID_SDE_ROTATOR_SECURE (V4L2_CID_USER_BASE + 0x1000) + +/* + * This control Id indicates this context is associated with the + * secure camera. + */ +#define V4L2_CID_SDE_ROTATOR_SECURE_CAMERA (V4L2_CID_USER_BASE + 0x2000) + +#endif /* __UAPI_MSM_SDE_ROTATOR_H__ */ diff --git a/include/uapi/media/msm_vidc.h b/include/uapi/media/msm_vidc.h new file mode 100644 index 000000000000..95b6bab382bb --- /dev/null +++ b/include/uapi/media/msm_vidc.h @@ -0,0 +1,385 @@ +#ifndef __MSM_VIDC_H__ +#define __MSM_VIDC_H__ + +#include <linux/types.h> + +#define MSM_VIDC_HAL_INTERLACE_COLOR_FORMAT_NV12 0x2 +#define MSM_VIDC_HAL_INTERLACE_COLOR_FORMAT_NV12_UBWC 0x8002 + +struct msm_vidc_extradata_header { + unsigned int size; + unsigned int:32; /** Keeping binary compatibility */ + unsigned int:32; /* with firmware and OpenMAX IL **/ + unsigned int type; /* msm_vidc_extradata_type */ + unsigned int data_size; + unsigned char data[1]; +}; + +struct msm_vidc_interlace_payload { + unsigned int format; + unsigned int color_format; +}; + +struct msm_vidc_framerate_payload { + unsigned int frame_rate; +}; + +struct msm_vidc_ts_payload { + unsigned int timestamp_lo; + unsigned int timestamp_hi; +}; + +struct msm_vidc_concealmb_payload { + unsigned int num_mbs; +}; + +struct msm_vidc_recoverysei_payload { + unsigned int flags; +}; + +struct msm_vidc_aspect_ratio_payload { + unsigned int size; + unsigned int version; + unsigned int port_index; + unsigned int aspect_width; + unsigned int aspect_height; +}; + +struct msm_vidc_mpeg2_seqdisp_payload { + unsigned int video_format; + unsigned int color_descp; + unsigned int color_primaries; + unsigned int transfer_char; + unsigned int matrix_coeffs; + unsigned int disp_width; + unsigned int disp_height; +}; + +struct msm_vidc_vc1_seqdisp_payload { + unsigned int prog_seg_format; + unsigned int uv_sampl_fmt; + unsigned int color_format; + unsigned int color_primaries; + unsigned int transfer_char; + unsigned int matrix_coeffs; + unsigned int aspect_ratio; + unsigned int aspect_horiz; + unsigned int aspect_vert; +}; + +struct msm_vidc_input_crop_payload { + unsigned int size; + unsigned int version; + unsigned int port_index; + unsigned int left; + unsigned int top; + unsigned int width; + unsigned int height; +}; + +struct msm_vidc_output_crop_payload { + unsigned int size; + unsigned int version; + unsigned int port_index; + unsigned int left; + unsigned int top; + unsigned int display_width; + unsigned int display_height; + unsigned int width; + unsigned int height; +}; + + +struct msm_vidc_digital_zoom_payload { + unsigned int size; + unsigned int version; + unsigned int port_index; + unsigned int zoom_width; + unsigned int zoom_height; +}; + +struct msm_vidc_extradata_index { + unsigned int type; + union { + struct msm_vidc_input_crop_payload input_crop; + struct msm_vidc_digital_zoom_payload digital_zoom; + struct msm_vidc_aspect_ratio_payload aspect_ratio; + }; +}; + +struct msm_vidc_panscan_window { + unsigned int panscan_height_offset; + unsigned int panscan_width_offset; + unsigned int panscan_window_width; + unsigned int panscan_window_height; +}; + +struct msm_vidc_panscan_window_payload { + unsigned int num_panscan_windows; + struct msm_vidc_panscan_window wnd[1]; +}; + +struct msm_vidc_stream_userdata_payload { + unsigned int type; + unsigned int data[1]; +}; + +struct msm_vidc_frame_qp_payload { + unsigned int frame_qp; +}; + +struct msm_vidc_frame_bits_info_payload { + unsigned int frame_bits; + unsigned int header_bits; +}; + +struct msm_vidc_s3d_frame_packing_payload { + unsigned int fpa_id; + unsigned int cancel_flag; + unsigned int fpa_type; + unsigned int quin_cunx_flag; + unsigned int content_interprtation_type; + unsigned int spatial_flipping_flag; + unsigned int frame0_flipped_flag; + unsigned int field_views_flag; + unsigned int current_frame_is_frame0_flag; + unsigned int frame0_self_contained_flag; + unsigned int frame1_self_contained_flag; + unsigned int frame0_graid_pos_x; + unsigned int frame0_graid_pos_y; + unsigned int frame1_graid_pos_x; + unsigned int frame1_graid_pos_y; + unsigned int fpa_reserved_byte; + unsigned int fpa_repetition_period; + unsigned int fpa_extension_flag; +}; + +struct msm_vidc_vqzip_sei_payload { + unsigned int size; + unsigned int data[1]; +}; + +struct msm_vidc_yuv_stats_payload { + unsigned int frame_qp; + unsigned int texture; + unsigned int luma_in_q16; + unsigned int frame_difference; +}; + +struct msm_vidc_vpx_colorspace_payload { + unsigned int color_space; + unsigned int yuv_range_flag; + unsigned int sumsampling_x; + unsigned int sumsampling_y; +}; + +struct msm_vidc_roi_qp_payload { + int upper_qp_offset; + int lower_qp_offset; + unsigned int b_roi_info; + int mbi_info_size; + unsigned int data[1]; +}; + +struct msm_vidc_mastering_display_colour_sei_payload { + unsigned int nDisplayPrimariesX[3]; + unsigned int nDisplayPrimariesY[3]; + unsigned int nWhitePointX; + unsigned int nWhitePointY; + unsigned int nMaxDisplayMasteringLuminance; + unsigned int nMinDisplayMasteringLuminance; +}; + +struct msm_vidc_content_light_level_sei_payload { + unsigned int nMaxContentLight; + unsigned int nMaxPicAverageLight; +}; + +struct msm_vidc_vui_display_info_payload { + unsigned int video_signal_present_flag; + unsigned int video_format; + unsigned int bit_depth_y; + unsigned int bit_depth_c; + unsigned int video_full_range_flag; + unsigned int color_description_present_flag; + unsigned int color_primaries; + unsigned int transfer_characteristics; + unsigned int matrix_coefficients; + unsigned int chroma_location_info_present_flag; + unsigned int chroma_format_idc; + unsigned int separate_color_plane_flag; + unsigned int chroma_sample_loc_type_top_field; + unsigned int chroma_sample_loc_type_bottom_field; +}; + +enum msm_vidc_extradata_type { + MSM_VIDC_EXTRADATA_NONE = 0x00000000, + MSM_VIDC_EXTRADATA_MB_QUANTIZATION = 0x00000001, + MSM_VIDC_EXTRADATA_INTERLACE_VIDEO = 0x00000002, + MSM_VIDC_EXTRADATA_VC1_FRAMEDISP = 0x00000003, + MSM_VIDC_EXTRADATA_VC1_SEQDISP = 0x00000004, + MSM_VIDC_EXTRADATA_TIMESTAMP = 0x00000005, + MSM_VIDC_EXTRADATA_S3D_FRAME_PACKING = 0x00000006, + MSM_VIDC_EXTRADATA_FRAME_RATE = 0x00000007, + MSM_VIDC_EXTRADATA_PANSCAN_WINDOW = 0x00000008, + MSM_VIDC_EXTRADATA_RECOVERY_POINT_SEI = 0x00000009, + MSM_VIDC_EXTRADATA_MPEG2_SEQDISP = 0x0000000D, + MSM_VIDC_EXTRADATA_STREAM_USERDATA = 0x0000000E, + MSM_VIDC_EXTRADATA_FRAME_QP = 0x0000000F, + MSM_VIDC_EXTRADATA_FRAME_BITS_INFO = 0x00000010, + MSM_VIDC_EXTRADATA_VQZIP_SEI = 0x00000011, + MSM_VIDC_EXTRADATA_ROI_QP = 0x00000013, +#define MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI \ + MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI + MSM_VIDC_EXTRADATA_MASTERING_DISPLAY_COLOUR_SEI = 0x00000015, +#define MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI \ + MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI + MSM_VIDC_EXTRADATA_CONTENT_LIGHT_LEVEL_SEI = 0x00000016, +#define MSM_VIDC_EXTRADATA_PQ_INFO \ + MSM_VIDC_EXTRADATA_PQ_INFO + MSM_VIDC_EXTRADATA_PQ_INFO = 0x00000017, + MSM_VIDC_EXTRADATA_INPUT_CROP = 0x0700000E, +#define MSM_VIDC_EXTRADATA_OUTPUT_CROP \ + MSM_VIDC_EXTRADATA_OUTPUT_CROP + MSM_VIDC_EXTRADATA_OUTPUT_CROP = 0x0700000F, + MSM_VIDC_EXTRADATA_DIGITAL_ZOOM = 0x07000010, +#define MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO \ + MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO + MSM_VIDC_EXTRADATA_VPX_COLORSPACE_INFO = 0x00000014, + MSM_VIDC_EXTRADATA_MULTISLICE_INFO = 0x7F100000, + MSM_VIDC_EXTRADATA_NUM_CONCEALED_MB = 0x7F100001, + MSM_VIDC_EXTRADATA_INDEX = 0x7F100002, + MSM_VIDC_EXTRADATA_ASPECT_RATIO = 0x7F100003, + MSM_VIDC_EXTRADATA_METADATA_LTR = 0x7F100004, + MSM_VIDC_EXTRADATA_METADATA_FILLER = 0x7FE00002, + MSM_VIDC_EXTRADATA_METADATA_MBI = 0x7F100005, +#define MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO \ + MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO + MSM_VIDC_EXTRADATA_VUI_DISPLAY_INFO = 0x7F100006, + MSM_VIDC_EXTRADATA_YUVSTATS_INFO = 0x7F100007, +}; +enum msm_vidc_interlace_type { + MSM_VIDC_INTERLACE_FRAME_PROGRESSIVE = 0x01, + MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_TOPFIELDFIRST = 0x02, + MSM_VIDC_INTERLACE_INTERLEAVE_FRAME_BOTTOMFIELDFIRST = 0x04, + MSM_VIDC_INTERLACE_FRAME_TOPFIELDFIRST = 0x08, + MSM_VIDC_INTERLACE_FRAME_BOTTOMFIELDFIRST = 0x10, +}; + +/* enum msm_vidc_framepack_type */ +#define MSM_VIDC_FRAMEPACK_CHECKERBOARD 0x00 +#define MSM_VIDC_FRAMEPACK_COLUMN_INTERLEAVE 0x01 +#define MSM_VIDC_FRAMEPACK_ROW_INTERLEAVE 0x02 +#define MSM_VIDC_FRAMEPACK_SIDE_BY_SIDE 0x03 +#define MSM_VIDC_FRAMEPACK_TOP_BOTTOM 0x04 +#define MSM_VIDC_FRAMEPACK_TEMPORAL_INTERLEAVE 0x05 + +enum msm_vidc_recovery_sei { + MSM_VIDC_FRAME_RECONSTRUCTION_INCORRECT = 0x0, + MSM_VIDC_FRAME_RECONSTRUCTION_CORRECT = 0x01, + MSM_VIDC_FRAME_RECONSTRUCTION_APPROXIMATELY_CORRECT = 0x02, +}; +enum msm_vidc_userdata_type { + MSM_VIDC_USERDATA_TYPE_FRAME = 0x1, + MSM_VIDC_USERDATA_TYPE_TOP_FIELD = 0x2, + MSM_VIDC_USERDATA_TYPE_BOTTOM_FIELD = 0x3, +}; + +/* See colour_primaries of ISO/IEC 14496 for significance */ +enum msm_vidc_h264_color_primaries_values { + MSM_VIDC_RESERVED_1 = 0, + MSM_VIDC_BT709_5 = 1, + MSM_VIDC_UNSPECIFIED = 2, + MSM_VIDC_RESERVED_2 = 3, + MSM_VIDC_BT470_6_M = 4, + MSM_VIDC_BT601_6_625 = 5, + MSM_VIDC_BT470_6_BG = MSM_VIDC_BT601_6_625, + MSM_VIDC_BT601_6_525 = 6, + MSM_VIDC_SMPTE_240M = 7, + MSM_VIDC_GENERIC_FILM = 8, + MSM_VIDC_BT2020 = 9, +}; + +enum msm_vidc_vp9_color_primaries_values { + MSM_VIDC_CS_UNKNOWN, + MSM_VIDC_CS_BT_601, + MSM_VIDC_CS_BT_709, + MSM_VIDC_CS_SMPTE_170, + MSM_VIDC_CS_SMPTE_240, + MSM_VIDC_CS_BT_2020, + MSM_VIDC_CS_RESERVED, + MSM_VIDC_CS_RGB, +}; + +enum msm_vidc_h264_matrix_coeff_values { + MSM_VIDC_MATRIX_RGB = 0, + MSM_VIDC_MATRIX_BT_709_5 = 1, + MSM_VIDC_MATRIX_UNSPECIFIED = 2, + MSM_VIDC_MATRIX_RESERVED = 3, + MSM_VIDC_MATRIX_FCC_47 = 4, + MSM_VIDC_MATRIX_601_6_625 = 5, + MSM_VIDC_MATRIX_BT470_BG = MSM_VIDC_MATRIX_601_6_625, + MSM_VIDC_MATRIX_601_6_525 = 6, + MSM_VIDC_MATRIX_SMPTE_170M = MSM_VIDC_MATRIX_601_6_525, + MSM_VIDC_MATRIX_SMPTE_240M = 7, + MSM_VIDC_MATRIX_Y_CG_CO = 8, + MSM_VIDC_MATRIX_BT_2020 = 9, + MSM_VIDC_MATRIX_BT_2020_CONST = 10, +}; + +enum msm_vidc_h264_transfer_chars_values { + MSM_VIDC_TRANSFER_RESERVED_1 = 0, + MSM_VIDC_TRANSFER_BT709_5 = 1, + MSM_VIDC_TRANSFER_UNSPECIFIED = 2, + MSM_VIDC_TRANSFER_RESERVED_2 = 3, + MSM_VIDC_TRANSFER_BT_470_6_M = 4, + MSM_VIDC_TRANSFER_BT_470_6_BG = 5, + MSM_VIDC_TRANSFER_601_6_625 = 6, + MSM_VIDC_TRANSFER_601_6_525 = MSM_VIDC_TRANSFER_601_6_625, + MSM_VIDC_TRANSFER_SMPTE_240M = 7, + MSM_VIDC_TRANSFER_LINEAR = 8, + MSM_VIDC_TRANSFER_LOG_100_1 = 9, + MSM_VIDC_TRANSFER_LOG_100_SQRT10_1 = 10, + MSM_VIDC_TRANSFER_IEC_61966 = 11, + MSM_VIDC_TRANSFER_BT_1361 = 12, + MSM_VIDC_TRANSFER_SRGB = 13, + MSM_VIDC_TRANSFER_BT_2020_10 = 14, + MSM_VIDC_TRANSFER_BT_2020_12 = 15, +#define MSM_VIDC_TRANSFER_SMPTE_ST2084 \ + MSM_VIDC_TRANSFER_SMPTE_ST2084 + MSM_VIDC_TRANSFER_SMPTE_ST2084 = 16, +#define MSM_VIDC_TRANSFER_SMPTE_ST428_1 \ + MSM_VIDC_TRANSFER_SMPTE_ST428_1 + MSM_VIDC_TRANSFER_SMPTE_ST428_1 = 17, +#define MSM_VIDC_TRANSFER_HLG \ + MSM_VIDC_TRANSFER_HLG + MSM_VIDC_TRANSFER_HLG = 18, +}; + +enum msm_vidc_pixel_depth { + MSM_VIDC_BIT_DEPTH_8, + MSM_VIDC_BIT_DEPTH_10, + MSM_VIDC_BIT_DEPTH_UNSUPPORTED = 0XFFFFFFFF, +}; + +enum msm_vidc_video_format { + MSM_VIDC_COMPONENT, + MSM_VIDC_PAL, + MSM_VIDC_NTSC, + MSM_VIDC_SECAM, + MSM_VIDC_MAC, + MSM_VIDC_UNSPECIFIED_FORMAT, + MSM_VIDC_RESERVED_1_FORMAT, + MSM_VIDC_RESERVED_2_FORMAT, +}; + +enum msm_vidc_color_desc_flag { + MSM_VIDC_COLOR_DESC_NOT_PRESENT, + MSM_VIDC_COLOR_DESC_PRESENT, +}; + +/*enum msm_vidc_pic_struct */ +#define MSM_VIDC_PIC_STRUCT_MAYBE_INTERLACED 0x0 +#define MSM_VIDC_PIC_STRUCT_PROGRESSIVE 0x1 + +#endif diff --git a/include/uapi/media/msm_vpu.h b/include/uapi/media/msm_vpu.h new file mode 100644 index 000000000000..7bcbc4f90872 --- /dev/null +++ b/include/uapi/media/msm_vpu.h @@ -0,0 +1,475 @@ +#ifndef _H_MSM_VPU_H_ +#define _H_MSM_VPU_H_ + +#include <linux/videodev2.h> + +/* + * V 4 L 2 E X T E N S I O N S B Y V P U + */ + +/* + * v4l2_buffer: + * + * VPU uses standard V4L2 buffer flags, and defines some custom + * flags (used in v4l2_buffer.flags field): + * V4L2_QCOM_BUF_FLAG_EOS: buffer flag indicating end of stream + * V4L2_BUF_FLAG_CDS_ENABLE: buffer flag to enable chroma down-sampling + */ +#define V4L2_BUF_FLAG_CDS_ENABLE 0x10000000 + +/* + * VPU uses multi-plane v4l2_buffer in the following manner: + * each plane can be a separate ION buffer, or all planes are from the + * same ION buffer (under this case all planes have the same fd, but different + * offset). + * + * For struct v4l2_plane + * fd: ION fd representing the ION buffer this plane is from + * reserved[0]: offset of this plane from the start of the ION buffer in + * bytes. Needed when all planes are from the same ION buffer. + */ +#define V4L2_PLANE_MEM_OFFSET 0 + +/* + * struct v4l2_format: + * always use v4l2_pix_format_mplane, even when there is only one plane + * + * v4l2_pix_format_mplane: + * + * VPU uses v4l2_pix_format_mplane for pixel format configuration + * The following members of this structure is either extended or changed: + * pixelformat: extended, a few more private formats added + * colorspace: possible values are enum vpu_colorspace + * field: when it is V4L2_FIELD_ALTERNATE, flags from vpu format extension + * specifies which field first. + * reserved[]: VPU format extension. struct v4l2_format_vpu_extension + */ +enum vpu_colorspace { + VPU_CS_MIN = 0, + /* RGB with full range*/ + VPU_CS_RGB_FULL = 1, + /* RGB with limited range*/ + VPU_CS_RGB_LIMITED = 2, + /* REC 601 with full range */ + VPU_CS_REC601_FULL = 3, + /* REC 601 with limited range */ + VPU_CS_REC601_LIMITED = 4, + /* REC 709 with full range */ + VPU_CS_REC709_FULL = 5, + /* REC 709 with limited range */ + VPU_CS_REC709_LIMITED = 6, + /* SMPTE 240 with full range */ + VPU_CS_SMPTE240_FULL = 7, + /* SMPTE 240 with limited range */ + VPU_CS_SMPTE240_LIMITED = 8, + VPU_CS_MAX = 9, +}; + + +#define VPU_FMT_EXT_FLAG_BT 1 /* bottom field first */ +#define VPU_FMT_EXT_FLAG_TB 2 /* top field first */ +#define VPU_FMT_EXT_FLAG_3D 4 /* 3D format */ +struct v4l2_format_vpu_extension { + __u8 flag; + __u8 gap_in_lines; +}; + +/* + * Supported pixel formats: + * + * VPU supported pixel format fourcc codes (use in s_fmt pixelformat field). + * Can be enumerated using VIDIOC_ENUM_FMT + * + * Standard V4L2 formats, defined in videodev2.h : + * + * V4L2_PIX_FMT_RGB24 24 bit RGB-8-8-8 + * V4L2_PIX_FMT_RGB32 32 bit XRGB-8-8-8-8 + * V4L2_PIX_FMT_BGR24 24 bit BGR-8-8-8 + * V4L2_PIX_FMT_BGR32 32 bit BGRX-8-8-8-8 + * + * V4L2_PIX_FMT_NV12 12 bit YUV 4:2:0 semi-planar NV12 + * V4L2_PIX_FMT_NV21 12 bit YUV 4:2:0 semi-planar NV21 + * V4L2_PIX_FMT_YUYV 16 bit YUYV 4:2:2 interleaved + * V4L2_PIX_FMT_YVYU 16 bit YVYU 4:2:2 interleaved + * V4L2_PIX_FMT_UYVY 16 bit UYVY 4:2:2 interleaved + * V4L2_PIX_FMT_VYUY 16 bit VYUY 4:2:2 interleaved + * + * + * Private VPU formats, defined here : + * + * V4L2_PIX_FMT_XRGB2 32 bit XRGB-2-10-10-10 + * V4L2_PIX_FMT_XBGR2 32 bit XBGR-2-10-10-10 + * + * V4L2_PIX_FMT_YUYV10 24 bit YUYV 4:2:2 10 bit per component loose + * V4L2_PIX_FMT_YUV8 24 bit YUV 4:4:4 8 bit per component + * V4L2_PIX_FMT_YUV10 32 bit YUV 4:4:4 10 bit per component loose + * V4L2_PIX_FMT_YUYV10BWC 10 bit YUYV 4:2:2 compressed, for output only + */ +#define V4L2_PIX_FMT_XRGB2 v4l2_fourcc('X', 'R', 'G', '2') +#define V4L2_PIX_FMT_XBGR2 v4l2_fourcc('X', 'B', 'G', '2') +#define V4L2_PIX_FMT_YUYV10 v4l2_fourcc('Y', 'U', 'Y', 'L') +#define V4L2_PIX_FMT_YUV8 v4l2_fourcc('Y', 'U', 'V', '8') +#define V4L2_PIX_FMT_YUV10 v4l2_fourcc('Y', 'U', 'V', 'L') +#define V4L2_PIX_FMT_YUYV10BWC v4l2_fourcc('Y', 'B', 'W', 'C') + +/* + * VIDIOC_S_INPUT/VIDIOC_S_OUTPUT + * + * The single integer passed by these commands specifies port type in the + * lower 16 bits, and pipe bit mask in the higher 16 bits. + */ +/* input / output types */ +#define VPU_INPUT_TYPE_HOST 0 +#define VPU_INPUT_TYPE_VCAP 1 +#define VPU_OUTPUT_TYPE_HOST 0 +#define VPU_OUTPUT_TYPE_DISPLAY 1 + +/* input / output pipe bit fields */ +#define VPU_PIPE_VCAP0 (1 << 16) +#define VPU_PIPE_VCAP1 (1 << 17) +#define VPU_PIPE_DISPLAY0 (1 << 18) +#define VPU_PIPE_DISPLAY1 (1 << 19) +#define VPU_PIPE_DISPLAY2 (1 << 20) +#define VPU_PIPE_DISPLAY3 (1 << 21) + +/* + * V P U E V E N T S : I D s A N D D A T A P A Y L O A D S + */ + +/* + * Event ID: set in type field of struct v4l2_event + * payload: returned in u.data array of struct v4l2_event + * + * + * VPU_EVENT_FLUSH_DONE: Done flushing buffers after VPU_FLUSH_BUFS ioctl + * payload data: enum v4l2_buf_type (buffer type of flushed port) + * + * VPU_EVENT_ACTIVE_REGION_CHANGED: New Active Region Detected + * payload data: struct v4l2_rect (new active region rectangle) + * + * VPU_EVENT_SESSION_TIMESTAMP: New Session timestamp + * payload data: vpu_frame_timestamp_info + * + * VPU_EVENT_SESSION_CREATED: New session has been created + * payload data: int (number of the attached session) + * + * VPU_EVENT_SESSION_FREED: Session is detached and free + * payload data: int (number of the detached session) + * + * VPU_EVENT_SESSION_CLIENT_EXITED: Indicates that clients of current + * session have exited. + * payload data: int (number of all remaining clients for this session) + * + * VPU_EVENT_HW_ERROR: a hardware error occurred in VPU + * payload data: NULL + * + * VPU_EVENT_INVALID_CONFIG: invalid VPU session configuration + * payload data: NULL + * + * VPU_EVENT_FAILED_SESSION_STREAMING: Failed to stream session + * payload data: NULL + */ +#define VPU_PRIVATE_EVENT_BASE (V4L2_EVENT_PRIVATE_START + 6 * 1000) +enum VPU_PRIVATE_EVENT { + VPU_EVENT_START = VPU_PRIVATE_EVENT_BASE, + + VPU_EVENT_FLUSH_DONE = VPU_EVENT_START + 1, + VPU_EVENT_ACTIVE_REGION_CHANGED = VPU_EVENT_START + 2, + VPU_EVENT_SESSION_TIMESTAMP = VPU_EVENT_START + 3, + VPU_EVENT_SESSION_CREATED = VPU_EVENT_START + 4, + VPU_EVENT_SESSION_FREED = VPU_EVENT_START + 5, + VPU_EVENT_SESSION_CLIENT_EXITED = VPU_EVENT_START + 6, + + VPU_EVENT_HW_ERROR = VPU_EVENT_START + 11, + VPU_EVENT_INVALID_CONFIG = VPU_EVENT_START + 12, + VPU_EVENT_FAILED_SESSION_STREAMING = VPU_EVENT_START + 13, + + VPU_EVENT_END +}; + + +/* + * V P U CO N T R O L S : S T R U C T S A N D I D s + * + * Controls are video processing parameters + */ + +/* + * Standard VPU Controls + */ +struct vpu_ctrl_standard { + __u32 enable; /* boolean: 0=disable, else=enable */ + __s32 value; +}; + +struct vpu_ctrl_auto_manual { + __u32 enable; /* boolean: 0=disable, else=enable */ + __u32 auto_mode; /* boolean: 0=manual, else=automatic */ + __s32 value; +}; + +struct vpu_ctrl_range_mapping { + __u32 enable; /* boolean: 0=disable, else=enable */ + __u32 y_range; /* the range mapping set for Y [0, 7] */ + __u32 uv_range; /* the range mapping set for UV [0, 7] */ +}; + +#define VPU_ACTIVE_REGION_N_EXCLUSIONS 1 +struct vpu_ctrl_active_region_param { + __u32 enable; /* boolean: 0=disable, else=enable */ + /* number of exclusion regions */ + __u32 num_exclusions; + /* roi where active region detection is applied */ + struct v4l2_rect detection_region; + /* roi(s) excluded from active region detection*/ + struct v4l2_rect excluded_regions[VPU_ACTIVE_REGION_N_EXCLUSIONS]; +}; + +struct vpu_ctrl_deinterlacing_mode { + __u32 field_polarity; + __u32 mvp_mode; +}; + +struct vpu_ctrl_hqv { + __u32 enable; + /* strength control of all sharpening features [0, 100] */ + __u32 sharpen_strength; + /* strength control of Auto NR feature [0, 100] */ + __u32 auto_nr_strength; +}; + +struct vpu_info_frame_timestamp { + /* presentation timestamp of the frame */ + __u32 pts_low; + __u32 pts_high; + /* qtimer snapshot */ + __u32 qtime_low; + __u32 qtime_high; +}; + +struct vpu_control { + __u32 control_id; + union control_data { + __s32 value; + struct vpu_ctrl_standard standard; + struct vpu_ctrl_auto_manual auto_manual; + struct vpu_ctrl_range_mapping range_mapping; + struct vpu_ctrl_active_region_param active_region_param; + struct v4l2_rect active_region_result; + struct vpu_ctrl_deinterlacing_mode deinterlacing_mode; + struct vpu_ctrl_hqv hqv; + struct vpu_info_frame_timestamp timestamp; + __u8 reserved[124]; + } data; +}; + +/* + * IDs for standard controls (use in control_id field of struct vpu_control) + * + * VPU_CTRL_NOISE_REDUCTION: noise reduction level, data: auto_manual, + * value: [0, 100] (step in increments of 25). + * + * VPU_CTRL_IMAGE_ENHANCEMENT: image enhancement level, data: auto_manual, + * value: [-100, 100] (step in increments of 1). + * + * VPU_CTRL_ANAMORPHIC_SCALING: anamorphic scaling config, data: standard, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_DIRECTIONAL_INTERPOLATION: directional interpolation config + * data: standard, value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_BACKGROUND_COLOR: , data: value, + * value: red[0:7] green[8:15] blue[16:23] alpha[24:31] + * + * VPU_CTRL_RANGE_MAPPING: Y/UV range mapping, data: range_mapping, + * y_range: [0, 7], uv_range: [0, 7] (step in increments of 1). + * + * VPU_CTRL_DEINTERLACING_MODE: deinterlacing mode, data: deinterlacing_mode, + * field_polarity: [0, 2], mvp_mode: [0, 2] (step in increments of 1). + * + * VPU_CTRL_ACTIVE_REGION_PARAM: active region detection parameters (set only) + * data: active_region_param, + * + * VPU_CTRL_ACTIVE_REGION_RESULT: detected active region roi (get only) + * data: active_region_result + * + * VPU_CTRL_PRIORITY: Session priority, data: value, + * value: high 100, normal 50 + * + * VPU_CTRL_CONTENT_PROTECTION: input content protection status, data: value, + * value: secure 1, non-secure 0 + * + * VPU_CTRL_DISPLAY_REFRESH_RATE: display refresh rate (set only) + * data: value (set to __u32 16.16 format) + * + * VPU_CTRL_HQV: hqv block config, data: hqv, + * sharpen_strength: [0, 100] (step in increments of 25), + * auto_nr_strength: [0, 100] (step in increments of 1). + * + * VPU_CTRL_HQV_SHARPEN: , data: value, + * sharpen_strength: [0, 100] (step in increments of 1). + * + * VPU_CTRL_HQV_AUTONR: , data: value, + * auto_nr_strength: [0, 100] (step in increments of 1). + * + * VPU_CTRL_ACE: , data: value + * + * VPU_CTRL_ACE_BRIGHTNESS: , data: value, + * value: [-100, 100] (step in increments of 1). + * + * VPU_CTRL_ACE_CONTRAST: , data: value, + * value: [-100, 100] (step in increments of 1). + * + * VPU_CTRL_2D3D: , data: value, + * value: 1 enabled, 0 disabled + * + * VPU_CTRL_2D3D_DEPTH: , data: value, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_TIMESTAMP_INFO_MODE: timestamp reporting mode, + * data: value specifying how frequent a timestamp reporting info, value + * is in frames + * + * VPU_INFO_TIMESTAMP: timestamp information (get only) + * data: struct vpu_frame_timestamp_info + * + * VPU_CTRL_FRC: enable/disable FRC, data: value, + * value: 1 enable, 0 disable + * + * VPU_CTRL_FRC_MOTION_SMOOTHNESS: , data: value, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_FRC_MOTION_CLEAR: , data: value, + * value: [0, 100] (step in increments of 1). + * + * VPU_CTRL_LATENCY: session latency, data: value in us + * + * VPU_CTRL_LATENCY_MODE: data: value (ultra low, low, etc.) + * + * VPU_INFO_STATISTICS: frames dropped, etc (get only), + * data: reserved + */ +#define VPU_CTRL_ID_MIN 0 + +#define VPU_CTRL_NOISE_REDUCTION 1 +#define VPU_CTRL_IMAGE_ENHANCEMENT 2 +#define VPU_CTRL_ANAMORPHIC_SCALING 3 +#define VPU_CTRL_DIRECTIONAL_INTERPOLATION 4 +#define VPU_CTRL_BACKGROUND_COLOR 5 +#define VPU_CTRL_RANGE_MAPPING 6 +#define VPU_CTRL_DEINTERLACING_MODE 7 +#define VPU_CTRL_ACTIVE_REGION_PARAM 8 +#define VPU_CTRL_ACTIVE_REGION_RESULT 9 +#define VPU_CTRL_PRIORITY 10 +#define VPU_CTRL_CONTENT_PROTECTION 11 +#define VPU_CTRL_DISPLAY_REFRESH_RATE 12 + +#define VPU_CTRL_HQV 20 +#define VPU_CTRL_HQV_SHARPEN 21 +#define VPU_CTRL_HQV_AUTONR 22 +#define VPU_CTRL_ACE 23 +#define VPU_CTRL_ACE_BRIGHTNESS 24 +#define VPU_CTRL_ACE_CONTRAST 25 +#define VPU_CTRL_2D3D 26 +#define VPU_CTRL_2D3D_DEPTH 27 +#define VPU_CTRL_FRC 28 +#define VPU_CTRL_FRC_MOTION_SMOOTHNESS 29 +#define VPU_CTRL_FRC_MOTION_CLEAR 30 + +#define VPU_INFO_TIMESTAMP 35 +#define VPU_CTRL_TIMESTAMP_INFO_MODE 36 +#define VPU_INFO_STATISTICS 37 +#define VPU_CTRL_LATENCY 38 +#define VPU_CTRL_LATENCY_MODE 39 + +#define VPU_CTRL_ID_MAX 40 + + +/* + * Extended VPU Controls (large data payloads) + */ +#define VPU_MAX_EXT_DATA_SIZE 720 +struct vpu_control_extended { + /* + * extended control type + * 0: system + * 1: session + */ + __u32 type; + + /* + * size and ptr of the data to send + * maximum VPU_MAX_EXT_DATA_SIZE bytes + */ + __u32 data_len; + void __user *data_ptr; + + /* + * size and ptr of the buffer to recv data + * maximum VPU_MAX_EXT_DATA_SIZE bytes + */ + __u32 buf_size; + void __user *buf_ptr; +}; + +/* + * Port specific controls + */ +struct vpu_control_port { + __u32 control_id; + __u32 port; /* 0: INPUT, 1: OUTPUT */ + union control_port_data { + __u32 framerate; + } data; +}; + +/* + * IDs for port controls (use in control_id field of struct vpu_control_port) + * + * VPU_CTRL_FPS: set frame rate, data: __u32, 16.16 format + */ +#define VPU_CTRL_FPS 1000 + + +/* + * V P U D E V I C E P R I V A T E I O C T L C O D E S + */ + +/* VPU Session ioctls (deprecated) */ +#define VPU_ATTACH_TO_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 1), int) + +/* VPU Session ioctls */ +#define VPU_QUERY_SESSIONS _IOR('V', (BASE_VIDIOC_PRIVATE + 0), int) +#define VPU_CREATE_SESSION _IOR('V', (BASE_VIDIOC_PRIVATE + 2), int) +#define VPU_JOIN_SESSION _IOW('V', (BASE_VIDIOC_PRIVATE + 3), int) + +/* Enable second VPU output port and use with current client */ +#define VPU_CREATE_OUTPUT2 _IO('V', (BASE_VIDIOC_PRIVATE + 5)) + +/* Explicit commit of session configuration */ +#define VPU_COMMIT_CONFIGURATION _IO('V', (BASE_VIDIOC_PRIVATE + 10)) + +/* Flush all buffers of given type (port) */ +#define VPU_FLUSH_BUFS _IOW('V', (BASE_VIDIOC_PRIVATE + 15), \ + enum v4l2_buf_type) + +/* VPU controls get/set ioctls (for most controls with small data) */ +#define VPU_G_CONTROL _IOWR('V', (BASE_VIDIOC_PRIVATE + 20), \ + struct vpu_control) +#define VPU_S_CONTROL _IOW('V', (BASE_VIDIOC_PRIVATE + 21), \ + struct vpu_control) + +/* extended control set/get ioctls (large data payloads) */ +#define VPU_G_CONTROL_EXTENDED _IOWR('V', (BASE_VIDIOC_PRIVATE + 22), \ + struct vpu_control_extended) +#define VPU_S_CONTROL_EXTENDED _IOW('V', (BASE_VIDIOC_PRIVATE + 23), \ + struct vpu_control_extended) + +/* VPU port (input/output) specific controls get/set ioctls */ +#define VPU_G_CONTROL_PORT _IOWR('V', (BASE_VIDIOC_PRIVATE + 24), \ + struct vpu_control_port) +#define VPU_S_CONTROL_PORT _IOW('V', (BASE_VIDIOC_PRIVATE + 25), \ + struct vpu_control_port) + +#endif /* _H_MSM_VPU_H_ */ + diff --git a/include/uapi/media/msmb_camera.h b/include/uapi/media/msmb_camera.h new file mode 100644 index 000000000000..0a2dd446ccc4 --- /dev/null +++ b/include/uapi/media/msmb_camera.h @@ -0,0 +1,232 @@ +#ifndef __UAPI_LINUX_MSMB_CAMERA_H +#define __UAPI_LINUX_MSMB_CAMERA_H + +#include <linux/videodev2.h> +#include <linux/types.h> +#include <linux/ioctl.h> + +#define MSM_CAM_LOGSYNC_FILE_NAME "logsync" +#define MSM_CAM_LOGSYNC_FILE_BASEDIR "camera" + +#define MSM_CAM_V4L2_IOCTL_NOTIFY \ + _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_NOTIFY_META \ + _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_CMD_ACK \ + _IOW('V', BASE_VIDIOC_PRIVATE + 32, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR \ + _IOW('V', BASE_VIDIOC_PRIVATE + 33, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_NOTIFY_DEBUG \ + _IOW('V', BASE_VIDIOC_PRIVATE + 34, struct msm_v4l2_event_data) + +#define MSM_CAM_V4L2_IOCTL_DAEMON_DISABLED \ + _IOW('V', BASE_VIDIOC_PRIVATE + 35, struct msm_v4l2_event_data) + +#define QCAMERA_DEVICE_GROUP_ID 1 +#define QCAMERA_VNODE_GROUP_ID 2 +#define MSM_CAMERA_NAME "msm_camera" +#define MSM_CONFIGURATION_NAME "msm_config" + +#define MSM_CAMERA_SUBDEV_CSIPHY 0 +#define MSM_CAMERA_SUBDEV_CSID 1 +#define MSM_CAMERA_SUBDEV_ISPIF 2 +#define MSM_CAMERA_SUBDEV_VFE 3 +#define MSM_CAMERA_SUBDEV_AXI 4 +#define MSM_CAMERA_SUBDEV_VPE 5 +#define MSM_CAMERA_SUBDEV_SENSOR 6 +#define MSM_CAMERA_SUBDEV_ACTUATOR 7 +#define MSM_CAMERA_SUBDEV_EEPROM 8 +#define MSM_CAMERA_SUBDEV_CPP 9 +#define MSM_CAMERA_SUBDEV_CCI 10 +#define MSM_CAMERA_SUBDEV_LED_FLASH 11 +#define MSM_CAMERA_SUBDEV_STROBE_FLASH 12 +#define MSM_CAMERA_SUBDEV_BUF_MNGR 13 +#define MSM_CAMERA_SUBDEV_SENSOR_INIT 14 +#define MSM_CAMERA_SUBDEV_OIS 15 +#define MSM_CAMERA_SUBDEV_FLASH 16 +#define MSM_CAMERA_SUBDEV_IR_LED 17 +#define MSM_CAMERA_SUBDEV_IR_CUT 18 +#define MSM_CAMERA_SUBDEV_EXT 19 +#define MSM_CAMERA_SUBDEV_TOF 20 +#define MSM_CAMERA_SUBDEV_LASER_LED 21 +#define MSM_MAX_CAMERA_SENSORS 6 + +/* The below macro is defined to put an upper limit on maximum + * number of buffer requested per stream. In case of extremely + * large value for number of buffer due to data structure corruption + * we return error to avoid integer overflow. Group processing + * can have max of 9 groups of 8 bufs each. This value may be + * configured in future*/ +#define MSM_CAMERA_MAX_STREAM_BUF 72 + +/* Max batch size of processing */ +#define MSM_CAMERA_MAX_USER_BUFF_CNT 16 + +/* featur base */ +#define MSM_CAMERA_FEATURE_BASE 0x00010000 +#define MSM_CAMERA_FEATURE_SHUTDOWN (MSM_CAMERA_FEATURE_BASE + 1) + +#define MSM_CAMERA_STATUS_BASE 0x00020000 +#define MSM_CAMERA_STATUS_FAIL (MSM_CAMERA_STATUS_BASE + 1) +#define MSM_CAMERA_STATUS_SUCCESS (MSM_CAMERA_STATUS_BASE + 2) + +/* event type */ +#define MSM_CAMERA_V4L2_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x00002000) + +/* event id */ +#define MSM_CAMERA_EVENT_MIN 0 +#define MSM_CAMERA_NEW_SESSION (MSM_CAMERA_EVENT_MIN + 1) +#define MSM_CAMERA_DEL_SESSION (MSM_CAMERA_EVENT_MIN + 2) +#define MSM_CAMERA_SET_PARM (MSM_CAMERA_EVENT_MIN + 3) +#define MSM_CAMERA_GET_PARM (MSM_CAMERA_EVENT_MIN + 4) +#define MSM_CAMERA_MAPPING_CFG (MSM_CAMERA_EVENT_MIN + 5) +#define MSM_CAMERA_MAPPING_SES (MSM_CAMERA_EVENT_MIN + 6) +#define MSM_CAMERA_MSM_NOTIFY (MSM_CAMERA_EVENT_MIN + 7) +#define MSM_CAMERA_EVENT_MAX (MSM_CAMERA_EVENT_MIN + 8) + +/* data.command */ +#define MSM_CAMERA_PRIV_S_CROP (V4L2_CID_PRIVATE_BASE + 1) +#define MSM_CAMERA_PRIV_G_CROP (V4L2_CID_PRIVATE_BASE + 2) +#define MSM_CAMERA_PRIV_G_FMT (V4L2_CID_PRIVATE_BASE + 3) +#define MSM_CAMERA_PRIV_S_FMT (V4L2_CID_PRIVATE_BASE + 4) +#define MSM_CAMERA_PRIV_TRY_FMT (V4L2_CID_PRIVATE_BASE + 5) +#define MSM_CAMERA_PRIV_METADATA (V4L2_CID_PRIVATE_BASE + 6) +#define MSM_CAMERA_PRIV_QUERY_CAP (V4L2_CID_PRIVATE_BASE + 7) +#define MSM_CAMERA_PRIV_STREAM_ON (V4L2_CID_PRIVATE_BASE + 8) +#define MSM_CAMERA_PRIV_STREAM_OFF (V4L2_CID_PRIVATE_BASE + 9) +#define MSM_CAMERA_PRIV_NEW_STREAM (V4L2_CID_PRIVATE_BASE + 10) +#define MSM_CAMERA_PRIV_DEL_STREAM (V4L2_CID_PRIVATE_BASE + 11) +#define MSM_CAMERA_PRIV_SHUTDOWN (V4L2_CID_PRIVATE_BASE + 12) +#define MSM_CAMERA_PRIV_STREAM_INFO_SYNC \ + (V4L2_CID_PRIVATE_BASE + 13) +#define MSM_CAMERA_PRIV_G_SESSION_ID (V4L2_CID_PRIVATE_BASE + 14) +#define MSM_CAMERA_PRIV_CMD_MAX 20 + +/* data.status - success */ +#define MSM_CAMERA_CMD_SUCESS 0x00000001 +#define MSM_CAMERA_BUF_MAP_SUCESS 0x00000002 + +/* data.status - error */ +#define MSM_CAMERA_ERR_EVT_BASE 0x00010000 +#define MSM_CAMERA_ERR_CMD_FAIL (MSM_CAMERA_ERR_EVT_BASE + 1) +#define MSM_CAMERA_ERR_MAPPING (MSM_CAMERA_ERR_EVT_BASE + 2) +#define MSM_CAMERA_ERR_DEVICE_BUSY (MSM_CAMERA_ERR_EVT_BASE + 3) + +/* data.status - success values should be same as above*/ +#define MSM_CAMERA_CMD_SUCCESS 0x00000001 +#define MSM_CAMERA_BUF_MAP_SUCCESS 0x00000002 + +/* The msm_v4l2_event_data structure should match the + * v4l2_event.u.data field. + * should not exceed 16 elements */ +struct msm_v4l2_event_data { + /*word 0*/ + unsigned int command; + /*word 1*/ + unsigned int status; + /*word 2*/ + unsigned int session_id; + /*word 3*/ + unsigned int stream_id; + /*word 4*/ + unsigned int map_op; + /*word 5*/ + unsigned int map_buf_idx; + /*word 6*/ + unsigned int notify; + /*word 7*/ + unsigned int arg_value; + /*word 8*/ + unsigned int ret_value; + /*word 9*/ + unsigned int v4l2_event_type; + /*word 10*/ + unsigned int v4l2_event_id; + /*word 11*/ + unsigned int handle; + /*word 12*/ + unsigned int nop6; + /*word 13*/ + unsigned int nop7; + /*word 14*/ + unsigned int nop8; + /*word 15*/ + unsigned int nop9; +}; + +/* map to v4l2_format.fmt.raw_data */ +struct msm_v4l2_format_data { + enum v4l2_buf_type type; + unsigned int width; + unsigned int height; + unsigned int pixelformat; /* FOURCC */ + unsigned char num_planes; + unsigned int plane_sizes[VIDEO_MAX_PLANES]; +}; + +/* MSM Four-character-code (FOURCC) */ +#define msm_v4l2_fourcc(a, b, c, d)\ + ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) |\ + ((__u32)(d) << 24)) + +/* Composite stats */ +#define MSM_V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M') +/* AEC stats */ +#define MSM_V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E') +/* AF stats */ +#define MSM_V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F') +/* AWB stats */ +#define MSM_V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B') +/* IHIST stats */ +#define MSM_V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T') +/* Column count stats */ +#define MSM_V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S') +/* Row count stats */ +#define MSM_V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S') +/* Bayer Grid stats */ +#define MSM_V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G') +/* Bayer focus stats */ +#define MSM_V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F') +/* Bayer hist stats */ +#define MSM_V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T') + +enum smmu_attach_mode { + NON_SECURE_MODE = 0x01, + SECURE_MODE = 0x02, + MAX_PROTECTION_MODE = 0x03, +}; + +struct msm_camera_smmu_attach_type { + enum smmu_attach_mode attach; +}; + +struct msm_camera_user_buf_cont_t { + unsigned int buf_cnt; + unsigned int buf_idx[MSM_CAMERA_MAX_USER_BUFF_CNT]; +}; + +struct msm_camera_return_buf { + __u32 index; + __u32 reserved; +}; + +#define MSM_CAMERA_PRIV_IOCTL_ID_BASE 0 +#define MSM_CAMERA_PRIV_IOCTL_ID_RETURN_BUF 1 + +struct msm_camera_private_ioctl_arg { + __u32 id; + __u32 size; + __u32 result; + __u32 reserved; + __user __u64 ioctl_ptr; +}; + +#define VIDIOC_MSM_CAMERA_PRIVATE_IOCTL_CMD \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_private_ioctl_arg) + +#endif + diff --git a/include/uapi/media/msmb_generic_buf_mgr.h b/include/uapi/media/msmb_generic_buf_mgr.h new file mode 100644 index 000000000000..8dad9ae92cf8 --- /dev/null +++ b/include/uapi/media/msmb_generic_buf_mgr.h @@ -0,0 +1,68 @@ +#ifndef __UAPI_MEDIA_MSMB_GENERIC_BUF_MGR_H__ +#define __UAPI_MEDIA_MSMB_GENERIC_BUF_MGR_H__ + +#include <media/msmb_camera.h> + +enum msm_camera_buf_mngr_cmd { + MSM_CAMERA_BUF_MNGR_CONT_MAP, + MSM_CAMERA_BUF_MNGR_CONT_UNMAP, + MSM_CAMERA_BUF_MNGR_CONT_MAX, +}; + +enum msm_camera_buf_mngr_buf_type { + MSM_CAMERA_BUF_MNGR_BUF_PLANAR, + MSM_CAMERA_BUF_MNGR_BUF_USER, + MSM_CAMERA_BUF_MNGR_BUF_INVALID, +}; + +struct msm_buf_mngr_info { + uint32_t session_id; + uint32_t stream_id; + uint32_t frame_id; + struct timeval timestamp; + uint32_t index; + uint32_t reserved; + enum msm_camera_buf_mngr_buf_type type; + struct msm_camera_user_buf_cont_t user_buf; +}; + +struct msm_buf_mngr_main_cont_info { + uint32_t session_id; + uint32_t stream_id; + enum msm_camera_buf_mngr_cmd cmd; + uint32_t cnt; + int32_t cont_fd; +}; + +#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_BASE 0 +#define MSM_CAMERA_BUF_MNGR_IOCTL_ID_GET_BUF_BY_IDX 1 + +#define VIDIOC_MSM_BUF_MNGR_GET_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_PUT_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_BUF_DONE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_CONT_CMD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 36, struct msm_buf_mngr_main_cont_info) + +#define VIDIOC_MSM_BUF_MNGR_INIT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 37, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_DEINIT \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 38, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_FLUSH \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 39, struct msm_buf_mngr_info) + +#define VIDIOC_MSM_BUF_MNGR_IOCTL_CMD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 40, \ + struct msm_camera_private_ioctl_arg) + +#define VIDIOC_MSM_BUF_MNGR_BUF_ERROR \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 41, struct msm_buf_mngr_info) +#endif + diff --git a/include/uapi/media/msmb_isp.h b/include/uapi/media/msmb_isp.h new file mode 100644 index 000000000000..273388c657c5 --- /dev/null +++ b/include/uapi/media/msmb_isp.h @@ -0,0 +1,1051 @@ +#ifndef __UAPI_MSMB_ISP__ +#define __UAPI_MSMB_ISP__ + +#include <linux/videodev2.h> +#include <media/msmb_camera.h> + +#define MAX_PLANES_PER_STREAM 3 +#define MAX_NUM_STREAM 7 + +#define ISP_VERSION_48 48 +#define ISP_VERSION_47 47 +#define ISP_VERSION_46 46 +#define ISP_VERSION_44 44 +#define ISP_VERSION_40 40 +#define ISP_VERSION_32 32 +#define ISP_NATIVE_BUF_BIT (0x10000 << 0) +#define ISP0_BIT (0x10000 << 1) +#define ISP1_BIT (0x10000 << 2) +#define ISP_META_CHANNEL_BIT (0x10000 << 3) +#define ISP_SCRATCH_BUF_BIT (0x10000 << 4) +#define ISP_OFFLINE_STATS_BIT (0x10000 << 5) +#define ISP_SVHDR_IN_BIT (0x10000 << 6) /* RDI hw stream for SVHDR */ +#define ISP_SVHDR_OUT_BIT (0x10000 << 7) /* SVHDR output bufq stream*/ + +#define ISP_STATS_STREAM_BIT 0x80000000 + +#define VFE_HW_LIMIT 1 +#define ISP_KERNEL_STATE 1 + +struct msm_vfe_cfg_cmd_list; + +struct isp_kstate { + uint32_t kernel_sofid; + uint32_t drop_reconfig; + uint32_t vfeid; + uint32_t dual_cam_drop_detected; + uint32_t dual_cam_drop; +}; + +enum ISP_START_PIXEL_PATTERN { + ISP_BAYER_RGRGRG, + ISP_BAYER_GRGRGR, + ISP_BAYER_BGBGBG, + ISP_BAYER_GBGBGB, + ISP_YUV_YCbYCr, + ISP_YUV_YCrYCb, + ISP_YUV_CbYCrY, + ISP_YUV_CrYCbY, + ISP_PIX_PATTERN_MAX +}; + +enum msm_vfe_plane_fmt { + Y_PLANE, + CB_PLANE, + CR_PLANE, + CRCB_PLANE, + CBCR_PLANE, + VFE_PLANE_FMT_MAX +}; + +enum msm_vfe_input_src { + VFE_PIX_0, + VFE_RAW_0, + VFE_RAW_1, + VFE_RAW_2, + VFE_SRC_MAX, +}; + +enum msm_vfe_axi_stream_src { + PIX_ENCODER, + PIX_VIEWFINDER, + PIX_VIDEO, + CAMIF_RAW, + IDEAL_RAW, + RDI_INTF_0, + RDI_INTF_1, + RDI_INTF_2, + VFE_AXI_SRC_MAX +}; + +enum msm_vfe_frame_skip_pattern { + NO_SKIP, + EVERY_2FRAME, + EVERY_3FRAME, + EVERY_4FRAME, + EVERY_5FRAME, + EVERY_6FRAME, + EVERY_7FRAME, + EVERY_8FRAME, + EVERY_16FRAME, + EVERY_32FRAME, + SKIP_ALL, + SKIP_RANGE, + MAX_SKIP, +}; + +/* + * Define an unused period. When this period is set it means that the stream is + * stopped(i.e the pattern is 0). We don't track the current pattern, just the + * period defines what the pattern is, if period is this then pattern is 0 else + * pattern is 1 + */ +#define MSM_VFE_STREAM_STOP_PERIOD 15 + +enum msm_isp_stats_type { + MSM_ISP_STATS_AEC, /* legacy based AEC */ + MSM_ISP_STATS_AF, /* legacy based AF */ + MSM_ISP_STATS_AWB, /* legacy based AWB */ + MSM_ISP_STATS_RS, /* legacy based RS */ + MSM_ISP_STATS_CS, /* legacy based CS */ + MSM_ISP_STATS_IHIST, /* legacy based HIST */ + MSM_ISP_STATS_SKIN, /* legacy based SKIN */ + MSM_ISP_STATS_BG, /* Bayer Grids */ + MSM_ISP_STATS_BF, /* Bayer Focus */ + MSM_ISP_STATS_BE, /* Bayer Exposure*/ + MSM_ISP_STATS_BHIST, /* Bayer Hist */ + MSM_ISP_STATS_BF_SCALE, /* Bayer Focus scale */ + MSM_ISP_STATS_HDR_BE, /* HDR Bayer Exposure */ + MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */ + MSM_ISP_STATS_AEC_BG, /* AEC BG */ + MSM_ISP_STATS_MAX /* MAX */ +}; + +/* + * @stats_type_mask: Stats type mask (enum msm_isp_stats_type). + * @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src) + * @skip_mode: skip pattern, if skip mode is range only then min/max is used + * @min_frame_id: minimum frame id (valid only if skip_mode = RANGE) + * @max_frame_id: maximum frame id (valid only if skip_mode = RANGE) +*/ +struct msm_isp_sw_framskip { + uint32_t stats_type_mask; + uint32_t stream_src_mask; + enum msm_vfe_frame_skip_pattern skip_mode; + uint32_t min_frame_id; + uint32_t max_frame_id; +}; + +enum msm_vfe_testgen_color_pattern { + COLOR_BAR_8_COLOR, + UNICOLOR_WHITE, + UNICOLOR_YELLOW, + UNICOLOR_CYAN, + UNICOLOR_GREEN, + UNICOLOR_MAGENTA, + UNICOLOR_RED, + UNICOLOR_BLUE, + UNICOLOR_BLACK, + MAX_COLOR, +}; + +enum msm_vfe_camif_input { + CAMIF_DISABLED, + CAMIF_PAD_REG_INPUT, + CAMIF_MIDDI_INPUT, + CAMIF_MIPI_INPUT, +}; + +struct msm_vfe_fetch_engine_cfg { + uint32_t input_format; + uint32_t buf_width; + uint32_t buf_height; + uint32_t fetch_width; + uint32_t fetch_height; + uint32_t x_offset; + uint32_t y_offset; + uint32_t buf_stride; +}; + +enum msm_vfe_camif_output_format { + CAMIF_QCOM_RAW, + CAMIF_MIPI_RAW, + CAMIF_PLAIN_8, + CAMIF_PLAIN_16, + CAMIF_MAX_FORMAT, +}; + +/* + * Camif output general configuration + */ +struct msm_vfe_camif_subsample_cfg { + uint32_t irq_subsample_period; + uint32_t irq_subsample_pattern; + uint32_t sof_counter_step; + uint32_t pixel_skip; + uint32_t line_skip; + uint32_t first_line; + uint32_t last_line; + uint32_t first_pixel; + uint32_t last_pixel; + enum msm_vfe_camif_output_format output_format; +}; + +/* + * Camif frame and window configuration + */ +struct msm_vfe_camif_cfg { + uint32_t lines_per_frame; + uint32_t pixels_per_line; + uint32_t first_pixel; + uint32_t last_pixel; + uint32_t first_line; + uint32_t last_line; + uint32_t epoch_line0; + uint32_t epoch_line1; + uint32_t is_split; + enum msm_vfe_camif_input camif_input; + struct msm_vfe_camif_subsample_cfg subsample_cfg; +}; + +struct msm_vfe_testgen_cfg { + uint32_t lines_per_frame; + uint32_t pixels_per_line; + uint32_t v_blank; + uint32_t h_blank; + enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern; + uint32_t rotate_period; + enum msm_vfe_testgen_color_pattern color_bar_pattern; + uint32_t burst_num_frame; +}; + +enum msm_vfe_inputmux { + CAMIF, + TESTGEN, + EXTERNAL_READ, +}; + +enum msm_vfe_stats_composite_group { + STATS_COMPOSITE_GRP_NONE, + STATS_COMPOSITE_GRP_1, + STATS_COMPOSITE_GRP_2, + STATS_COMPOSITE_GRP_MAX, +}; + +enum msm_vfe_hvx_streaming_cmd { + HVX_DISABLE, + HVX_ONE_WAY, + HVX_ROUND_TRIP +}; + +struct msm_vfe_pix_cfg { + struct msm_vfe_camif_cfg camif_cfg; + struct msm_vfe_testgen_cfg testgen_cfg; + struct msm_vfe_fetch_engine_cfg fetch_engine_cfg; + enum msm_vfe_inputmux input_mux; + enum ISP_START_PIXEL_PATTERN pixel_pattern; + uint32_t input_format; + enum msm_vfe_hvx_streaming_cmd hvx_cmd; + uint32_t is_split; +}; + +struct msm_vfe_rdi_cfg { + uint8_t cid; + uint8_t frame_based; +}; + +struct msm_vfe_input_cfg { + union { + struct msm_vfe_pix_cfg pix_cfg; + struct msm_vfe_rdi_cfg rdi_cfg; + } d; + enum msm_vfe_input_src input_src; + uint32_t input_pix_clk; +}; + +struct msm_vfe_fetch_eng_start { + uint32_t session_id; + uint32_t stream_id; + uint32_t buf_idx; + uint8_t offline_mode; + uint32_t fd; + uint32_t buf_addr; + uint32_t frame_id; +}; + +enum msm_vfe_fetch_eng_pass { + OFFLINE_FIRST_PASS, + OFFLINE_SECOND_PASS, + OFFLINE_MAX_PASS, +}; + +struct msm_vfe_fetch_eng_multi_pass_start { + uint32_t session_id; + uint32_t stream_id; + uint32_t buf_idx; + uint8_t offline_mode; + uint32_t fd; + uint32_t buf_addr; + uint32_t frame_id; + uint32_t output_buf_idx; + uint32_t input_buf_offset; + enum msm_vfe_fetch_eng_pass offline_pass; + uint32_t output_stream_id; +}; + +struct msm_vfe_axi_plane_cfg { + uint32_t output_width; /*Include padding*/ + uint32_t output_height; + uint32_t output_stride; + uint32_t output_scan_lines; + uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/ + uint32_t plane_addr_offset; + uint8_t csid_src; /*RDI 0-2*/ + uint8_t rdi_cid;/*CID 1-16*/ +}; + +enum msm_stream_rdi_input_type { + MSM_CAMERA_RDI_MIN, + MSM_CAMERA_RDI_PDAF, + MSM_CAMERA_RDI_MAX, +}; + +struct msm_vfe_axi_stream_request_cmd { + uint32_t session_id; + uint32_t stream_id; + uint32_t vt_enable; + uint32_t output_format;/*Planar/RAW/Misc*/ + enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/ + struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; + + uint32_t burst_count; + uint32_t hfr_mode; + uint8_t frame_base; + + uint32_t init_frame_drop; /*MAX 31 Frames*/ + enum msm_vfe_frame_skip_pattern frame_skip_pattern; + uint8_t buf_divert; /* if TRUE no vb2 buf done. */ + /*Return values*/ + uint32_t axi_stream_handle; + uint32_t controllable_output; + uint32_t burst_len; + /* Flag indicating memory input stream */ + enum msm_stream_rdi_input_type rdi_input_type; +}; + +struct msm_vfe_axi_stream_release_cmd { + uint32_t stream_handle; +}; + +enum msm_vfe_axi_stream_cmd { + STOP_STREAM, + START_STREAM, + STOP_IMMEDIATELY, +}; + +struct msm_vfe_axi_stream_cfg_cmd { + uint8_t num_streams; + uint32_t stream_handle[VFE_AXI_SRC_MAX]; + enum msm_vfe_axi_stream_cmd cmd; + uint8_t sync_frame_id_src; +}; + +enum msm_vfe_axi_stream_update_type { + ENABLE_STREAM_BUF_DIVERT, + DISABLE_STREAM_BUF_DIVERT, + UPDATE_STREAM_FRAMEDROP_PATTERN, + UPDATE_STREAM_STATS_FRAMEDROP_PATTERN, + UPDATE_STREAM_AXI_CONFIG, + UPDATE_STREAM_REQUEST_FRAMES, + UPDATE_STREAM_ADD_BUFQ, + UPDATE_STREAM_REMOVE_BUFQ, + UPDATE_STREAM_SW_FRAME_DROP, + UPDATE_STREAM_REQUEST_FRAMES_VER2, + UPDATE_STREAM_OFFLINE_AXI_CONFIG, +}; +#define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2 + +enum msm_vfe_iommu_type { + IOMMU_ATTACH, + IOMMU_DETACH, +}; + +enum msm_vfe_buff_queue_id { + VFE_BUF_QUEUE_DEFAULT, + VFE_BUF_QUEUE_SHARED, + VFE_BUF_QUEUE_MAX, +}; + +struct msm_vfe_axi_stream_cfg_update_info { + uint32_t stream_handle; + uint32_t output_format; + uint32_t user_stream_id; + uint32_t frame_id; + enum msm_vfe_frame_skip_pattern skip_pattern; + struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM]; + struct msm_isp_sw_framskip sw_skip_info; +}; + +struct msm_vfe_axi_stream_cfg_update_info_req_frm { + uint32_t stream_handle; + uint32_t user_stream_id; + uint32_t frame_id; + uint32_t buf_index; +}; + +struct msm_vfe_axi_halt_cmd { + uint32_t stop_camif; + uint32_t overflow_detected; + uint32_t blocking_halt; +}; + +struct msm_vfe_axi_reset_cmd { + uint32_t blocking; + uint32_t frame_id; +}; + +struct msm_vfe_axi_restart_cmd { + uint32_t enable_camif; +}; + +struct msm_vfe_axi_stream_update_cmd { + uint32_t num_streams; + enum msm_vfe_axi_stream_update_type update_type; + /* + * For backward compatibility, ensure 1st member of any struct + * in union below is uint32_t stream_handle. + */ + union { + struct msm_vfe_axi_stream_cfg_update_info + update_info[MSM_ISP_STATS_MAX]; + struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2; + }; +}; + +struct msm_vfe_smmu_attach_cmd { + uint32_t security_mode; + uint32_t iommu_attach_mode; +}; + +struct msm_vfe_stats_stream_request_cmd { + uint32_t session_id; + uint32_t stream_id; + enum msm_isp_stats_type stats_type; + uint32_t composite_flag; + uint32_t framedrop_pattern; + uint32_t init_frame_drop; /*MAX 31 Frames*/ + uint32_t irq_subsample_pattern; + uint32_t buffer_offset; + uint32_t stream_handle; +}; + +struct msm_vfe_stats_stream_release_cmd { + uint32_t stream_handle; +}; +struct msm_vfe_stats_stream_cfg_cmd { + uint8_t num_streams; + uint32_t stream_handle[MSM_ISP_STATS_MAX]; + uint8_t enable; + uint32_t stats_burst_len; +}; + +enum msm_vfe_reg_cfg_type { + VFE_WRITE, + VFE_WRITE_MB, + VFE_READ, + VFE_CFG_MASK, + VFE_WRITE_DMI_16BIT, + VFE_WRITE_DMI_32BIT, + VFE_WRITE_DMI_64BIT, + VFE_READ_DMI_16BIT, + VFE_READ_DMI_32BIT, + VFE_READ_DMI_64BIT, + GET_MAX_CLK_RATE, + GET_CLK_RATES, + GET_ISP_ID, + VFE_HW_UPDATE_LOCK, + VFE_HW_UPDATE_UNLOCK, + SET_WM_UB_SIZE, + SET_UB_POLICY, + GET_VFE_HW_LIMIT, +}; + +struct msm_vfe_cfg_cmd2 { + uint16_t num_cfg; + uint16_t cmd_len; + void __user *cfg_data; + void __user *cfg_cmd; +}; + +struct msm_vfe_cfg_cmd_list { + struct msm_vfe_cfg_cmd2 cfg_cmd; + struct msm_vfe_cfg_cmd_list *next; + uint32_t next_size; +}; + +struct msm_vfe_reg_rw_info { + uint32_t reg_offset; + uint32_t cmd_data_offset; + uint32_t len; +}; + +struct msm_vfe_reg_mask_info { + uint32_t reg_offset; + uint32_t mask; + uint32_t val; +}; + +struct msm_vfe_reg_dmi_info { + uint32_t hi_tbl_offset; /*Optional*/ + uint32_t lo_tbl_offset; /*Required*/ + uint32_t len; +}; + +struct msm_vfe_reg_cfg_cmd { + union { + struct msm_vfe_reg_rw_info rw_info; + struct msm_vfe_reg_mask_info mask_info; + struct msm_vfe_reg_dmi_info dmi_info; + } u; + + enum msm_vfe_reg_cfg_type cmd_type; +}; + +enum vfe_sd_type { + VFE_SD_0 = 0, + VFE_SD_1, + VFE_SD_COMMON, + VFE_SD_MAX, +}; + +/* When you change the value below, check for the sof event_data size. + * V4l2 limits payload to 64 bytes */ +#define MS_NUM_SLAVE_MAX 1 + +/* Usecases when 2 HW need to be related or synced */ +enum msm_vfe_dual_hw_type { + DUAL_NONE = 0, + DUAL_HW_VFE_SPLIT = 1, + DUAL_HW_MASTER_SLAVE = 2, +}; + +/* Type for 2 INTF when used in Master-Slave mode */ +enum msm_vfe_dual_hw_ms_type { + MS_TYPE_NONE, + MS_TYPE_MASTER, + MS_TYPE_SLAVE, +}; + +struct msm_isp_set_dual_hw_ms_cmd { + uint8_t num_src; + /* Each session can be only one type but multiple intf if YUV cam */ + enum msm_vfe_dual_hw_ms_type dual_hw_ms_type; + /* Primary intf is mostly associated with preview. + * This primary intf SOF frame_id and timestamp is tracked + * and used to calculate delta */ + enum msm_vfe_input_src primary_intf; + /* input_src array indicates other input INTF that may be Master/Slave. + * For these additional intf, frame_id and timestamp are not saved. + * However, if these are slaves then they will still get their + * frame_id from Master */ + enum msm_vfe_input_src input_src[VFE_SRC_MAX]; + uint32_t sof_delta_threshold; /* In milliseconds. Sent for Master */ +}; + +enum msm_isp_buf_type { + ISP_PRIVATE_BUF, + ISP_SHARE_BUF, + MAX_ISP_BUF_TYPE, +}; + +struct msm_isp_unmap_buf_req { + uint32_t fd; +}; + +struct msm_isp_buf_request { + uint32_t session_id; + uint32_t stream_id; + uint8_t num_buf; + uint32_t handle; + enum msm_isp_buf_type buf_type; +}; + +struct msm_isp_buf_request_ver2 { + uint32_t session_id; + uint32_t stream_id; + uint8_t num_buf; + uint32_t handle; + enum msm_isp_buf_type buf_type; + enum smmu_attach_mode security_mode; + uint32_t reserved[4]; +}; + +struct msm_isp_qbuf_plane { + uint32_t addr; + uint32_t offset; + uint32_t length; +}; + +struct msm_isp_qbuf_buffer { + struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM]; + uint32_t num_planes; +}; + +struct msm_isp_qbuf_info { + uint32_t handle; + int32_t buf_idx; + /*Only used for prepare buffer*/ + struct msm_isp_qbuf_buffer buffer; + /*Only used for diverted buffer*/ + uint32_t dirty_buf; +}; + +struct msm_isp_clk_rates { + uint32_t svs_rate; + uint32_t nominal_rate; + uint32_t high_rate; +}; + +struct msm_vfe_axi_src_state { + enum msm_vfe_input_src input_src; + uint32_t src_active; + uint32_t src_frame_id; +}; + +enum msm_isp_event_mask_index { + ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0, + ISP_EVENT_MASK_INDEX_ERROR = 1, + ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2, + ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3, + ISP_EVENT_MASK_INDEX_REG_UPDATE = 4, + ISP_EVENT_MASK_INDEX_SOF = 5, + ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6, + ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7, + ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8, + ISP_EVENT_MASK_INDEX_BUF_DONE = 9, + ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING = 10, + ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH = 11, + ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR = 12, +}; + + +#define ISP_EVENT_SUBS_MASK_NONE 0 + +#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \ + (1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY) + +#define ISP_EVENT_SUBS_MASK_ERROR \ + (1 << ISP_EVENT_MASK_INDEX_ERROR) + +#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \ + (1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT) + +#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \ + (1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE) + +#define ISP_EVENT_SUBS_MASK_REG_UPDATE \ + (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE) + +#define ISP_EVENT_SUBS_MASK_SOF \ + (1 << ISP_EVENT_MASK_INDEX_SOF) + +#define ISP_EVENT_SUBS_MASK_BUF_DIVERT \ + (1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT) + +#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \ + (1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY) + +#define ISP_EVENT_SUBS_MASK_FE_READ_DONE \ + (1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE) + +#define ISP_EVENT_SUBS_MASK_BUF_DONE \ + (1 << ISP_EVENT_MASK_INDEX_BUF_DONE) + +#define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING \ + (1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING) + +#define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH \ + (1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH) + +#define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR \ + (1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR) + +enum msm_isp_event_idx { + ISP_REG_UPDATE = 0, + ISP_EPOCH_0 = 1, + ISP_EPOCH_1 = 2, + ISP_START_ACK = 3, + ISP_STOP_ACK = 4, + ISP_IRQ_VIOLATION = 5, + ISP_STATS_OVERFLOW = 6, + ISP_BUF_DONE = 7, + ISP_FE_RD_DONE = 8, + ISP_IOMMU_P_FAULT = 9, + ISP_ERROR = 10, + ISP_HW_FATAL_ERROR = 11, + ISP_PING_PONG_MISMATCH = 12, + ISP_REG_UPDATE_MISSING = 13, + ISP_BUF_FATAL_ERROR = 14, + ISP_EVENT_MAX = 15 +}; + +#define ISP_EVENT_OFFSET 8 +#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START) +#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET)) +#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET)) +#define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET)) +#define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET)) +#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE) +#define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0) +#define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1) +#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK) +#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK) +#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION) +#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW) +#define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR) +#define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE) +#define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1) +#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE) +#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE) +#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE) +#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX) +#define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE) +#define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT) +#define ISP_EVENT_HW_FATAL_ERROR (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR) +#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH) +#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING) +#define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR) +#define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE) + +/* The msm_v4l2_event_data structure should match the + * v4l2_event.u.data field. + * should not exceed 64 bytes */ + +struct msm_isp_buf_event { + uint32_t session_id; + uint32_t stream_id; + uint32_t handle; + uint32_t output_format; + int8_t buf_idx; +}; +struct msm_isp_fetch_eng_event { + uint32_t session_id; + uint32_t stream_id; + uint32_t handle; + uint32_t fd; + int8_t buf_idx; + int8_t offline_mode; +}; +struct msm_isp_stats_event { + uint32_t stats_mask; /* 4 bytes */ + uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */ + uint8_t pd_stats_idx; +}; + +struct msm_isp_stream_ack { + uint32_t session_id; + uint32_t stream_id; + uint32_t handle; +}; + +enum msm_vfe_error_type { + ISP_ERROR_NONE, + ISP_ERROR_CAMIF, + ISP_ERROR_BUS_OVERFLOW, + ISP_ERROR_RETURN_EMPTY_BUFFER, + ISP_ERROR_FRAME_ID_MISMATCH, + ISP_ERROR_MAX, +}; + +struct msm_isp_error_info { + enum msm_vfe_error_type err_type; + uint32_t session_id; + uint32_t stream_id; + uint32_t stream_id_mask; +}; + +/* This structure reports delta between master and slave */ +struct msm_isp_ms_delta_info { + uint8_t num_delta_info; + uint32_t delta[MS_NUM_SLAVE_MAX]; +}; + +/* This is sent in EPOCH irq */ +struct msm_isp_output_info { + uint8_t regs_not_updated; + /* mask with bufq_handle for regs not updated or return empty */ + uint16_t output_err_mask; + /* mask with stream_idx for get_buf failed */ + uint8_t stream_framedrop_mask; + /* mask with stats stream_idx for get_buf failed */ + uint16_t stats_framedrop_mask; + /* delta between master and slave */ +}; + +/* This structure is piggybacked with SOF event */ +struct msm_isp_sof_info { + uint8_t regs_not_updated; + /* mask with bufq_handle for regs not updated */ + uint16_t reg_update_fail_mask; + /* mask with bufq_handle for get_buf failed */ + uint32_t stream_get_buf_fail_mask; + /* mask with stats stream_idx for get_buf failed */ + uint16_t stats_get_buf_fail_mask; + /* delta between master and slave */ + struct msm_isp_ms_delta_info ms_delta_info; + /* + * mask with AXI_SRC in paused state. In PAUSED + * state there is no Buffer output. So this mask is used + * to report drop. + */ + uint16_t axi_updating_mask; + /* extended mask with bufq_handle for regs not updated */ + uint32_t reg_update_fail_mask_ext; +}; +#define AXI_UPDATING_MASK 1 +#define REG_UPDATE_FAIL_MASK_EXT 1 + +struct msm_isp_event_data { + /*Wall clock except for buffer divert events + *which use monotonic clock + */ + struct timeval timestamp; + /* Monotonic timestamp since bootup */ + struct timeval mono_timestamp; + uint32_t frame_id; + union { + /* Sent for Stats_Done event */ + struct msm_isp_stats_event stats; + /* Sent for Buf_Divert event */ + struct msm_isp_buf_event buf_done; + /* Sent for offline fetch done event */ + struct msm_isp_fetch_eng_event fetch_done; + /* Sent for Error_Event */ + struct msm_isp_error_info error_info; + /* + * This struct needs to be removed once + * userspace switches to sof_info + */ + struct msm_isp_output_info output_info; + /* Sent for SOF event */ + struct msm_isp_sof_info sof_info; + } u; /* union can have max 52 bytes */ +}; + +enum msm_vfe_ahb_clk_vote { + MSM_ISP_CAMERA_AHB_SVS_VOTE = 1, + MSM_ISP_CAMERA_AHB_TURBO_VOTE = 2, + MSM_ISP_CAMERA_AHB_NOMINAL_VOTE = 3, + MSM_ISP_CAMERA_AHB_SUSPEND_VOTE = 4, +}; + +struct msm_isp_ahb_clk_cfg { + uint32_t vote; + uint32_t reserved[2]; +}; + +enum msm_vfe_dual_cam_sync_mode { + MSM_ISP_DUAL_CAM_ASYNC, + MSM_ISP_DUAL_CAM_SYNC, +}; + +struct msm_isp_dual_hw_master_slave_sync { + uint32_t sync_mode; + uint32_t reserved[2]; +}; + +struct msm_vfe_dual_lpm_mode { + enum msm_vfe_axi_stream_src stream_src[VFE_AXI_SRC_MAX]; + uint32_t num_src; + uint32_t lpm_mode; +}; +#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8') +#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8') +#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8') +#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8') +#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0') +#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0') +#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0') +#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0') +#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2') +#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2') +#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2') +#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2') +#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4') +#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4') +#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4') +#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4') +#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0') +#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0') +#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0') +#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0') +#define V4L2_PIX_FMT_P16BGGR12 v4l2_fourcc('P', 'B', 'G', '2') +#define V4L2_PIX_FMT_P16GBRG12 v4l2_fourcc('P', 'G', 'B', '2') +#define V4L2_PIX_FMT_P16GRBG12 v4l2_fourcc('P', 'G', 'R', '2') +#define V4L2_PIX_FMT_P16RGGB12 v4l2_fourcc('P', 'R', 'G', '2') +#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4') +#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1') +#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T') +#define V4L2_PIX_FMT_META10 v4l2_fourcc('Q', 'M', '1', '0') +#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/ +#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/ +#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/ +#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/ + +enum msm_isp_ioctl_cmd_code { + MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE, + MSM_ISP_REQUEST_BUF, + MSM_ISP_ENQUEUE_BUF, + MSM_ISP_RELEASE_BUF, + MSM_ISP_REQUEST_STREAM, + MSM_ISP_CFG_STREAM, + MSM_ISP_RELEASE_STREAM, + MSM_ISP_INPUT_CFG, + MSM_ISP_SET_SRC_STATE, + MSM_ISP_REQUEST_STATS_STREAM, + MSM_ISP_CFG_STATS_STREAM, + MSM_ISP_RELEASE_STATS_STREAM, + MSM_ISP_REG_UPDATE_CMD, + MSM_ISP_UPDATE_STREAM, + MSM_VFE_REG_LIST_CFG, + MSM_ISP_SMMU_ATTACH, + MSM_ISP_UPDATE_STATS_STREAM, + MSM_ISP_AXI_HALT, + MSM_ISP_AXI_RESET, + MSM_ISP_AXI_RESTART, + MSM_ISP_FETCH_ENG_START, + MSM_ISP_DEQUEUE_BUF, + MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, + MSM_ISP_MAP_BUF_START_FE, + MSM_ISP_UNMAP_BUF, + MSM_ISP_AHB_CLK_CFG, + MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, + MSM_ISP_FETCH_ENG_MULTI_PASS_START, + MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, + MSM_ISP_REQUEST_BUF_VER2, + MSM_ISP_DUAL_HW_LPM_MODE, +}; + +#define VIDIOC_MSM_VFE_REG_CFG \ + _IOWR('V', MSM_VFE_REG_CFG, \ + struct msm_vfe_cfg_cmd2) + +#define VIDIOC_MSM_ISP_REQUEST_BUF \ + _IOWR('V', MSM_ISP_REQUEST_BUF, \ + struct msm_isp_buf_request) + +#define VIDIOC_MSM_ISP_ENQUEUE_BUF \ + _IOWR('V', MSM_ISP_ENQUEUE_BUF, \ + struct msm_isp_qbuf_info) + +#define VIDIOC_MSM_ISP_RELEASE_BUF \ + _IOWR('V', MSM_ISP_RELEASE_BUF, \ + struct msm_isp_buf_request) + +#define VIDIOC_MSM_ISP_REQUEST_STREAM \ + _IOWR('V', MSM_ISP_REQUEST_STREAM, \ + struct msm_vfe_axi_stream_request_cmd) + +#define VIDIOC_MSM_ISP_CFG_STREAM \ + _IOWR('V', MSM_ISP_CFG_STREAM, \ + struct msm_vfe_axi_stream_cfg_cmd) + +#define VIDIOC_MSM_ISP_RELEASE_STREAM \ + _IOWR('V', MSM_ISP_RELEASE_STREAM, \ + struct msm_vfe_axi_stream_release_cmd) + +#define VIDIOC_MSM_ISP_INPUT_CFG \ + _IOWR('V', MSM_ISP_INPUT_CFG, \ + struct msm_vfe_input_cfg) + +#define VIDIOC_MSM_ISP_SET_SRC_STATE \ + _IOWR('V', MSM_ISP_SET_SRC_STATE, \ + struct msm_vfe_axi_src_state) + +#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \ + _IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, \ + struct msm_vfe_stats_stream_request_cmd) + +#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \ + _IOWR('V', MSM_ISP_CFG_STATS_STREAM, \ + struct msm_vfe_stats_stream_cfg_cmd) + +#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \ + _IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, \ + struct msm_vfe_stats_stream_release_cmd) + +#define VIDIOC_MSM_ISP_REG_UPDATE_CMD \ + _IOWR('V', MSM_ISP_REG_UPDATE_CMD, \ + enum msm_vfe_input_src) + +#define VIDIOC_MSM_ISP_UPDATE_STREAM \ + _IOWR('V', MSM_ISP_UPDATE_STREAM, \ + struct msm_vfe_axi_stream_update_cmd) + +#define VIDIOC_MSM_VFE_REG_LIST_CFG \ + _IOWR('V', MSM_VFE_REG_LIST_CFG, \ + struct msm_vfe_cfg_cmd_list) + +#define VIDIOC_MSM_ISP_SMMU_ATTACH \ + _IOWR('V', MSM_ISP_SMMU_ATTACH, \ + struct msm_vfe_smmu_attach_cmd) + +#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \ + _IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, \ + struct msm_vfe_axi_stream_update_cmd) + +#define VIDIOC_MSM_ISP_AXI_HALT \ + _IOWR('V', MSM_ISP_AXI_HALT, \ + struct msm_vfe_axi_halt_cmd) + +#define VIDIOC_MSM_ISP_AXI_RESET \ + _IOWR('V', MSM_ISP_AXI_RESET, \ + struct msm_vfe_axi_reset_cmd) + +#define VIDIOC_MSM_ISP_AXI_RESTART \ + _IOWR('V', MSM_ISP_AXI_RESTART, \ + struct msm_vfe_axi_restart_cmd) + +#define VIDIOC_MSM_ISP_FETCH_ENG_START \ + _IOWR('V', MSM_ISP_FETCH_ENG_START, \ + struct msm_vfe_fetch_eng_start) + +#define VIDIOC_MSM_ISP_DEQUEUE_BUF \ + _IOWR('V', MSM_ISP_DEQUEUE_BUF, \ + struct msm_isp_qbuf_info) + +#define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE \ + _IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, \ + struct msm_isp_set_dual_hw_ms_cmd) + +#define VIDIOC_MSM_ISP_MAP_BUF_START_FE \ + _IOWR('V', MSM_ISP_MAP_BUF_START_FE, \ + struct msm_vfe_fetch_eng_start) + +#define VIDIOC_MSM_ISP_UNMAP_BUF \ + _IOWR('V', MSM_ISP_UNMAP_BUF, \ + struct msm_isp_unmap_buf_req) + +#define VIDIOC_MSM_ISP_AHB_CLK_CFG \ + _IOWR('V', MSM_ISP_AHB_CLK_CFG, struct msm_isp_ahb_clk_cfg) + +#define VIDIOC_MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC \ + _IOWR('V', MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, \ + struct msm_isp_dual_hw_master_slave_sync) + +#define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START \ + _IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, \ + struct msm_vfe_fetch_eng_multi_pass_start) + +#define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE \ + _IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, \ + struct msm_vfe_fetch_eng_multi_pass_start) + +#define VIDIOC_MSM_ISP_REQUEST_BUF_VER2 \ + _IOWR('V', MSM_ISP_REQUEST_BUF_VER2, struct msm_isp_buf_request_ver2) + +#define VIDIOC_MSM_ISP_DUAL_HW_LPM_MODE \ + _IOWR('V', MSM_ISP_DUAL_HW_LPM_MODE, \ + struct msm_vfe_dual_lpm_mode) + +#endif /* __MSMB_ISP__ */ diff --git a/include/uapi/media/msmb_ispif.h b/include/uapi/media/msmb_ispif.h new file mode 100644 index 000000000000..d532037427cc --- /dev/null +++ b/include/uapi/media/msmb_ispif.h @@ -0,0 +1,179 @@ +#ifndef UAPI_MSMB_ISPIF_H +#define UAPI_MSMB_ISPIF_H + +#include <linux/types.h> +#include <linux/ioctl.h> +#include <linux/videodev2.h> + +#define CSID_VERSION_V20 0x02000011 +#define CSID_VERSION_V22 0x02001000 +#define CSID_VERSION_V30 0x30000000 +#define CSID_VERSION_V3 0x30000000 + +enum msm_ispif_vfe_intf { + VFE0, + VFE1, + VFE_MAX +}; +#define VFE0_MASK (1 << VFE0) +#define VFE1_MASK (1 << VFE1) + +enum msm_ispif_intftype { + PIX0, + RDI0, + PIX1, + RDI1, + RDI2, + INTF_MAX +}; +#define MAX_PARAM_ENTRIES (INTF_MAX * 2) +#define MAX_CID_CH 8 +#define MAX_CID_CH_PARAM_ENTRY 3 + +#define PIX0_MASK (1 << PIX0) +#define PIX1_MASK (1 << PIX1) +#define RDI0_MASK (1 << RDI0) +#define RDI1_MASK (1 << RDI1) +#define RDI2_MASK (1 << RDI2) + +enum msm_ispif_vc { + VC0, + VC1, + VC2, + VC3, + VC_MAX +}; + +enum msm_ispif_cid { + CID0, + CID1, + CID2, + CID3, + CID4, + CID5, + CID6, + CID7, + CID8, + CID9, + CID10, + CID11, + CID12, + CID13, + CID14, + CID15, + CID_MAX +}; + +enum msm_ispif_csid { + CSID0, + CSID1, + CSID2, + CSID3, + CSID_MAX +}; + +enum msm_ispif_pixel_odd_even { + PIX_EVEN, + PIX_ODD +}; + +enum msm_ispif_pixel_pack_mode { + PACK_BYTE, + PACK_PLAIN_PACK, + PACK_NV_P8, + PACK_NV_P16 +}; + +struct msm_ispif_pack_cfg { + int pixel_swap_en; + enum msm_ispif_pixel_odd_even even_odd_sel; + enum msm_ispif_pixel_pack_mode pack_mode; +}; + +struct msm_ispif_params_entry { + enum msm_ispif_vfe_intf vfe_intf; + enum msm_ispif_intftype intftype; + int num_cids; + enum msm_ispif_cid cids[MAX_CID_CH_PARAM_ENTRY]; + enum msm_ispif_csid csid; + int crop_enable; + uint16_t crop_start_pixel; + uint16_t crop_end_pixel; +}; + +struct msm_ispif_right_param_entry { + enum msm_ispif_cid cids[MAX_CID_CH_PARAM_ENTRY]; + enum msm_ispif_csid csid; +}; + +struct msm_ispif_param_data_ext { + uint32_t num; + struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES]; + struct msm_ispif_pack_cfg pack_cfg[CID_MAX]; + struct msm_ispif_right_param_entry right_entries[MAX_PARAM_ENTRIES]; + uint32_t stereo_enable; + uint16_t line_width[VFE_MAX]; +}; + +struct msm_ispif_param_data { + uint32_t num; + struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES]; +}; + +struct msm_isp_info { + uint32_t max_resolution; + uint32_t id; + uint32_t ver; +}; + +struct msm_ispif_vfe_info { + int num_vfe; + struct msm_isp_info info[VFE_MAX]; +}; + +enum ispif_cfg_type_t { + ISPIF_CLK_ENABLE, + ISPIF_CLK_DISABLE, + ISPIF_INIT, + ISPIF_CFG, + ISPIF_START_FRAME_BOUNDARY, + ISPIF_RESTART_FRAME_BOUNDARY, + ISPIF_STOP_FRAME_BOUNDARY, + ISPIF_STOP_IMMEDIATELY, + ISPIF_RELEASE, + ISPIF_ENABLE_REG_DUMP, + ISPIF_SET_VFE_INFO, + ISPIF_CFG2, + ISPIF_CFG_STEREO, +}; + +struct ispif_cfg_data { + enum ispif_cfg_type_t cfg_type; + union { + int reg_dump; /* ISPIF_ENABLE_REG_DUMP */ + uint32_t csid_version; /* ISPIF_INIT */ + struct msm_ispif_vfe_info vfe_info; /* ISPIF_SET_VFE_INFO */ + struct msm_ispif_param_data params; /* CFG, START, STOP */ + }; +}; + +struct ispif_cfg_data_ext { + enum ispif_cfg_type_t cfg_type; + void __user *data; + uint32_t size; +}; + +#define ISPIF_RDI_PACK_MODE_SUPPORT 1 + +#define ISPIF_3D_SUPPORT 1 + +#define ISPIF_LINE_WIDTH_SUPPORT 1 + +#define VIDIOC_MSM_ISPIF_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data) + +#define VIDIOC_MSM_ISPIF_CFG_EXT \ + _IOWR('V', BASE_VIDIOC_PRIVATE+1, struct ispif_cfg_data_ext) + +#endif + diff --git a/include/uapi/media/msmb_pproc.h b/include/uapi/media/msmb_pproc.h new file mode 100644 index 000000000000..8f454571e69d --- /dev/null +++ b/include/uapi/media/msmb_pproc.h @@ -0,0 +1,255 @@ +#ifndef __UAPI_MSMB_PPROC_H +#define __UAPI_MSMB_PPROC_H + +#include <linux/videodev2.h> +#include <linux/types.h> +#include <media/msmb_generic_buf_mgr.h> + +/* Should be same as VIDEO_MAX_PLANES in videodev2.h */ +#define MAX_PLANES VIDEO_MAX_PLANES +/* PARTIAL_FRAME_STRIPE_COUNT must be even */ +#define PARTIAL_FRAME_STRIPE_COUNT 4 + +#define MAX_NUM_CPP_STRIPS 8 +#define MSM_CPP_MAX_NUM_PLANES 3 +#define MSM_CPP_MIN_FRAME_LENGTH 13 +#define MSM_CPP_MAX_FRAME_LENGTH 4096 +#define MSM_CPP_MAX_FW_NAME_LEN 32 +#define MAX_FREQ_TBL 10 +#define MSM_OUTPUT_BUF_CNT 8 + +enum msm_cpp_frame_type { + MSM_CPP_OFFLINE_FRAME, + MSM_CPP_REALTIME_FRAME, +}; + +enum msm_vpe_frame_type { + MSM_VPE_OFFLINE_FRAME, + MSM_VPE_REALTIME_FRAME, +}; + +struct msm_cpp_buffer_info_t { + int32_t fd; + uint32_t index; + uint32_t offset; + uint8_t native_buff; + uint8_t processed_divert; + uint32_t identity; +}; + +struct msm_cpp_stream_buff_info_t { + uint32_t identity; + uint32_t num_buffs; + struct msm_cpp_buffer_info_t *buffer_info; +}; + +enum msm_cpp_batch_mode_t { + BATCH_MODE_NONE, + BATCH_MODE_VIDEO, + BATCH_MODE_PREVIEW +}; + +struct msm_cpp_batch_info_t { + enum msm_cpp_batch_mode_t batch_mode; + uint32_t batch_size; + uint32_t intra_plane_offset[MAX_PLANES]; + uint32_t pick_preview_idx; + uint32_t cont_idx; +}; + +struct msm_cpp_frame_info_t { + int32_t frame_id; + struct timeval timestamp; + uint32_t inst_id; + uint32_t identity; + uint32_t client_id; + enum msm_cpp_frame_type frame_type; + uint32_t num_strips; + uint32_t msg_len; + uint32_t *cpp_cmd_msg; + int src_fd; + int dst_fd; + struct timeval in_time, out_time; + void __user *cookie; + int32_t *status; + int32_t duplicate_output; + uint32_t duplicate_identity; + uint32_t feature_mask; + uint8_t we_disable; + struct msm_cpp_buffer_info_t input_buffer_info; + struct msm_cpp_buffer_info_t output_buffer_info[MSM_OUTPUT_BUF_CNT]; + struct msm_cpp_buffer_info_t duplicate_buffer_info; + struct msm_cpp_buffer_info_t tnr_scratch_buffer_info[2]; + uint32_t reserved; + uint8_t partial_frame_indicator; + /* the followings are used only for partial_frame type + * and is only used for offline frame processing and + * only if payload big enough and need to be split into partial_frame + * if first_payload, kernel acquires output buffer + * first payload must have the last stripe + * buffer addresses from 0 to last_stripe_index are updated. + * kernel updates payload with msg_len and stripe_info + * kernel sends top level, plane level, then only stripes + * starting with first_stripe_index and + * ends with last_stripe_index + * kernel then sends trailing flag at frame done, + * if last payload, kernel queues the output buffer to HAL + */ + uint8_t first_payload; + uint8_t last_payload; + uint32_t first_stripe_index; + uint32_t last_stripe_index; + uint32_t stripe_info_offset; + uint32_t stripe_info; + struct msm_cpp_batch_info_t batch_info; +}; + +struct msm_cpp_pop_stream_info_t { + int32_t frame_id; + uint32_t identity; +}; + +struct cpp_hw_info { + uint32_t cpp_hw_version; + uint32_t cpp_hw_caps; + unsigned long freq_tbl[MAX_FREQ_TBL]; + uint32_t freq_tbl_count; +}; + +struct msm_vpe_frame_strip_info { + uint32_t src_w; + uint32_t src_h; + uint32_t dst_w; + uint32_t dst_h; + uint32_t src_x; + uint32_t src_y; + uint32_t phase_step_x; + uint32_t phase_step_y; + uint32_t phase_init_x; + uint32_t phase_init_y; +}; + +struct msm_vpe_buffer_info_t { + int32_t fd; + uint32_t index; + uint32_t offset; + uint8_t native_buff; + uint8_t processed_divert; +}; + +struct msm_vpe_stream_buff_info_t { + uint32_t identity; + uint32_t num_buffs; + struct msm_vpe_buffer_info_t *buffer_info; +}; + +struct msm_vpe_frame_info_t { + int32_t frame_id; + struct timeval timestamp; + uint32_t inst_id; + uint32_t identity; + uint32_t client_id; + enum msm_vpe_frame_type frame_type; + struct msm_vpe_frame_strip_info strip_info; + unsigned long src_fd; + unsigned long dst_fd; + struct ion_handle *src_ion_handle; + struct ion_handle *dest_ion_handle; + unsigned long src_phyaddr; + unsigned long dest_phyaddr; + unsigned long src_chroma_plane_offset; + unsigned long dest_chroma_plane_offset; + struct timeval in_time, out_time; + void *cookie; + + struct msm_vpe_buffer_info_t input_buffer_info; + struct msm_vpe_buffer_info_t output_buffer_info; +}; + +struct msm_pproc_queue_buf_info { + struct msm_buf_mngr_info buff_mgr_info; + uint8_t is_buf_dirty; +}; + +struct msm_cpp_clock_settings_t { + unsigned long clock_rate; + uint64_t avg; + uint64_t inst; +}; + +#define VIDIOC_MSM_CPP_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_GET_INST_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_LOAD_FIRMWARE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_GET_HW_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_FLUSH_QUEUE \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_ENQUEUE_STREAM_BUFF_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_DEQUEUE_STREAM_BUFF_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_CFG \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_TRANSACTION_SETUP \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_GET_EVENTPAYLOAD \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_GET_INST_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_ENQUEUE_STREAM_BUFF_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_VPE_DEQUEUE_STREAM_BUFF_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_QUEUE_BUF \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 14, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_APPEND_STREAM_BUFF_INFO \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 15, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_SET_CLOCK \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 16, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_POP_STREAM_BUFFER \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 17, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_IOMMU_ATTACH \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 18, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_IOMMU_DETACH \ + _IOWR('V', BASE_VIDIOC_PRIVATE + 19, struct msm_camera_v4l2_ioctl_t) + +#define VIDIOC_MSM_CPP_DELETE_STREAM_BUFF\ + _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct msm_camera_v4l2_ioctl_t) + + +#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0) +#define V4L2_EVENT_VPE_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 1) + +struct msm_camera_v4l2_ioctl_t { + uint32_t id; + size_t len; + int32_t trans_code; + void __user *ioctl_ptr; +}; + +#endif + diff --git a/include/uapi/media/radio-iris-commands.h b/include/uapi/media/radio-iris-commands.h new file mode 100644 index 000000000000..b9dce3dc6872 --- /dev/null +++ b/include/uapi/media/radio-iris-commands.h @@ -0,0 +1,108 @@ +#ifndef __UAPI_RADIO_IRIS_COMMANDS_H +#define __UAPI_RADIO_IRIS_COMMANDS_H + +enum v4l2_cid_private_iris_t { + V4L2_CID_PRIVATE_IRIS_SRCHMODE = (0x08000000 + 1), + V4L2_CID_PRIVATE_IRIS_SCANDWELL, + V4L2_CID_PRIVATE_IRIS_SRCHON, + V4L2_CID_PRIVATE_IRIS_STATE, + V4L2_CID_PRIVATE_IRIS_TRANSMIT_MODE, + V4L2_CID_PRIVATE_IRIS_RDSGROUP_MASK, + V4L2_CID_PRIVATE_IRIS_REGION, + V4L2_CID_PRIVATE_IRIS_SIGNAL_TH, + V4L2_CID_PRIVATE_IRIS_SRCH_PTY, + V4L2_CID_PRIVATE_IRIS_SRCH_PI, + V4L2_CID_PRIVATE_IRIS_SRCH_CNT, + V4L2_CID_PRIVATE_IRIS_EMPHASIS, + V4L2_CID_PRIVATE_IRIS_RDS_STD, + V4L2_CID_PRIVATE_IRIS_SPACING, + V4L2_CID_PRIVATE_IRIS_RDSON, + V4L2_CID_PRIVATE_IRIS_RDSGROUP_PROC, + V4L2_CID_PRIVATE_IRIS_LP_MODE, + V4L2_CID_PRIVATE_IRIS_ANTENNA, + V4L2_CID_PRIVATE_IRIS_RDSD_BUF, + V4L2_CID_PRIVATE_IRIS_PSALL, /*0x8000014*/ + + /*v4l2 Tx controls*/ + V4L2_CID_PRIVATE_IRIS_TX_SETPSREPEATCOUNT, + V4L2_CID_PRIVATE_IRIS_STOP_RDS_TX_PS_NAME, + V4L2_CID_PRIVATE_IRIS_STOP_RDS_TX_RT, + V4L2_CID_PRIVATE_IRIS_IOVERC, + V4L2_CID_PRIVATE_IRIS_INTDET, + V4L2_CID_PRIVATE_IRIS_MPX_DCC, + V4L2_CID_PRIVATE_IRIS_AF_JUMP, + V4L2_CID_PRIVATE_IRIS_RSSI_DELTA, + V4L2_CID_PRIVATE_IRIS_HLSI, /*0x800001d*/ + + /*Diagnostic commands*/ + V4L2_CID_PRIVATE_IRIS_SOFT_MUTE, + V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_ADDR, + V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_LEN, + V4L2_CID_PRIVATE_IRIS_RIVA_PEEK, + V4L2_CID_PRIVATE_IRIS_RIVA_POKE, + V4L2_CID_PRIVATE_IRIS_SSBI_ACCS_ADDR, + V4L2_CID_PRIVATE_IRIS_SSBI_PEEK, + V4L2_CID_PRIVATE_IRIS_SSBI_POKE, + V4L2_CID_PRIVATE_IRIS_TX_TONE, + V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS, + V4L2_CID_PRIVATE_IRIS_SET_NOTCH_FILTER, /* 0x8000028 */ + V4L2_CID_PRIVATE_IRIS_SET_AUDIO_PATH, /* TAVARUA specific command */ + V4L2_CID_PRIVATE_IRIS_DO_CALIBRATION, + V4L2_CID_PRIVATE_IRIS_SRCH_ALGORITHM, /* TAVARUA specific command */ + V4L2_CID_PRIVATE_IRIS_GET_SINR, + V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD, + V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD, + V4L2_CID_PRIVATE_SINR_THRESHOLD, + V4L2_CID_PRIVATE_SINR_SAMPLES, + V4L2_CID_PRIVATE_SPUR_FREQ, + V4L2_CID_PRIVATE_SPUR_FREQ_RMSSI, + V4L2_CID_PRIVATE_SPUR_SELECTION, + V4L2_CID_PRIVATE_UPDATE_SPUR_TABLE, + V4L2_CID_PRIVATE_VALID_CHANNEL, + V4L2_CID_PRIVATE_AF_RMSSI_TH, + V4L2_CID_PRIVATE_AF_RMSSI_SAMPLES, + V4L2_CID_PRIVATE_GOOD_CH_RMSSI_TH, + V4L2_CID_PRIVATE_SRCHALGOTYPE, + V4L2_CID_PRIVATE_CF0TH12, + V4L2_CID_PRIVATE_SINRFIRSTSTAGE, + V4L2_CID_PRIVATE_RMSSIFIRSTSTAGE, + V4L2_CID_PRIVATE_RXREPEATCOUNT, + V4L2_CID_PRIVATE_IRIS_RSSI_TH, + V4L2_CID_PRIVATE_IRIS_AF_JUMP_RSSI_TH, + V4L2_CID_PRIVATE_BLEND_SINRHI, + V4L2_CID_PRIVATE_BLEND_RMSSIHI, + + /*using private CIDs under userclass*/ + V4L2_CID_PRIVATE_IRIS_READ_DEFAULT = 0x00980928, + V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT, + V4L2_CID_PRIVATE_IRIS_SET_CALIBRATION, + V4L2_CID_PRIVATE_IRIS_SET_SPURTABLE = 0x0098092D, + V4L2_CID_PRIVATE_IRIS_GET_SPUR_TBL = 0x0098092E, +}; + +enum iris_evt_t { + IRIS_EVT_RADIO_READY, + IRIS_EVT_TUNE_SUCC, + IRIS_EVT_SEEK_COMPLETE, + IRIS_EVT_SCAN_NEXT, + IRIS_EVT_NEW_RAW_RDS, + IRIS_EVT_NEW_RT_RDS, + IRIS_EVT_NEW_PS_RDS, + IRIS_EVT_ERROR, + IRIS_EVT_BELOW_TH, + IRIS_EVT_ABOVE_TH, + IRIS_EVT_STEREO, + IRIS_EVT_MONO, + IRIS_EVT_RDS_AVAIL, + IRIS_EVT_RDS_NOT_AVAIL, + IRIS_EVT_NEW_SRCH_LIST, + IRIS_EVT_NEW_AF_LIST, + IRIS_EVT_TXRDSDAT, + IRIS_EVT_TXRDSDONE, + IRIS_EVT_RADIO_DISABLED, + IRIS_EVT_NEW_ODA, + IRIS_EVT_NEW_RT_PLUS, + IRIS_EVT_NEW_ERT, + IRIS_EVT_SPUR_TBL, +}; +#endif diff --git a/include/uapi/media/radio-iris.h b/include/uapi/media/radio-iris.h new file mode 100644 index 000000000000..015016ccfbbc --- /dev/null +++ b/include/uapi/media/radio-iris.h @@ -0,0 +1,813 @@ +#ifndef __UAPI_RADIO_IRIS_H +#define __UAPI_RADIO_IRIS_H + +#include <linux/types.h> +#include <media/radio-iris-commands.h> + +#define MIN_TX_TONE_VAL 0x00 +#define MAX_TX_TONE_VAL 0x07 +#define MIN_HARD_MUTE_VAL 0x00 +#define MAX_HARD_MUTE_VAL 0x03 +#define MIN_SRCH_MODE 0x00 +#define MAX_SRCH_MODE 0x09 +#define MIN_SCAN_DWELL 0x00 +#define MAX_SCAN_DWELL 0x0F +#define MIN_SIG_TH 0x00 +#define MAX_SIG_TH 0x03 +#define MIN_PTY 0X00 +#define MAX_PTY 0x1F +#define MIN_PI 0x0000 +#define MAX_PI 0xFFFF +#define MIN_SRCH_STATIONS_CNT 0x00 +#define MAX_SRCH_STATIONS_CNT 0x14 +#define MIN_CHAN_SPACING 0x00 +#define MAX_CHAN_SPACING 0x02 +#define MIN_EMPHASIS 0x00 +#define MAX_EMPHASIS 0x01 +#define MIN_RDS_STD 0x00 +#define MAX_RDS_STD 0x02 +#define MIN_ANTENNA_VAL 0x00 +#define MAX_ANTENNA_VAL 0x01 +#define MIN_TX_PS_REPEAT_CNT 0x01 +#define MAX_TX_PS_REPEAT_CNT 0x0F +#define MIN_SOFT_MUTE 0x00 +#define MAX_SOFT_MUTE 0x01 +#define MIN_PEEK_ACCESS_LEN 0x01 +#define MAX_PEEK_ACCESS_LEN 0xF9 +#define MIN_RESET_CNTR 0x00 +#define MAX_RESET_CNTR 0x01 +#define MIN_HLSI 0x00 +#define MAX_HLSI 0x02 +#define MIN_NOTCH_FILTER 0x00 +#define MAX_NOTCH_FILTER 0x02 +#define MIN_INTF_DET_OUT_LW_TH 0x00 +#define MAX_INTF_DET_OUT_LW_TH 0xFF +#define MIN_INTF_DET_OUT_HG_TH 0x00 +#define MAX_INTF_DET_OUT_HG_TH 0xFF +#define MIN_SINR_TH -128 +#define MAX_SINR_TH 127 +#define MIN_SINR_SAMPLES 0x01 +#define MAX_SINR_SAMPLES 0xFF +#define MIN_BLEND_HI -128 +#define MAX_BLEND_HI 127 + + +/* ---- HCI Packet structures ---- */ +#define RADIO_HCI_COMMAND_HDR_SIZE sizeof(struct radio_hci_command_hdr) +#define RADIO_HCI_EVENT_HDR_SIZE sizeof(struct radio_hci_event_hdr) + +/* HCI data types */ +#define RADIO_HCI_COMMAND_PKT 0x11 +#define RADIO_HCI_EVENT_PKT 0x14 +/*HCI reponce packets*/ +#define MAX_RIVA_PEEK_RSP_SIZE 251 +/* default data access */ +#define DEFAULT_DATA_OFFSET 2 +#define DEFAULT_DATA_SIZE 249 +/* Power levels are 0-7, but SOC will expect values from 0-255 + * So the each level step size will be 255/7 = 36 + */ +#define FM_TX_PWR_LVL_STEP_SIZE 36 +#define FM_TX_PWR_LVL_0 0 /* Lowest power lvl that can be set for Tx */ +#define FM_TX_PWR_LVL_MAX 7 /* Max power lvl for Tx */ +#define FM_TX_PHY_CFG_MODE 0x3c +#define FM_TX_PHY_CFG_LEN 0x10 +#define FM_TX_PWR_GAIN_OFFSET 14 +/**RDS CONFIG MODE**/ +#define FM_RDS_CNFG_MODE 0x0f +#define FM_RDS_CNFG_LEN 0x10 +#define AF_RMSSI_TH_LSB_OFFSET 10 +#define AF_RMSSI_TH_MSB_OFFSET 11 +#define AF_RMSSI_SAMPLES_OFFSET 15 +/**RX CONFIG MODE**/ +#define FM_RX_CONFG_MODE 0x15 +#define FM_RX_CNFG_LEN 0x20 +#define GD_CH_RMSSI_TH_OFFSET 12 +#define MAX_GD_CH_RMSSI_TH 127 +#define SRCH_ALGO_TYPE_OFFSET 25 +#define SINRFIRSTSTAGE_OFFSET 26 +#define RMSSIFIRSTSTAGE_OFFSET 27 +#define CF0TH12_BYTE1_OFFSET 8 +#define CF0TH12_BYTE2_OFFSET 9 +#define CF0TH12_BYTE3_OFFSET 10 +#define CF0TH12_BYTE4_OFFSET 11 +#define MAX_SINR_FIRSTSTAGE 127 +#define MAX_RMSSI_FIRSTSTAGE 127 +#define RDS_PS0_XFR_MODE 0x01 +#define RDS_PS0_LEN 6 +#define RX_REPEATE_BYTE_OFFSET 5 +#define FM_SPUR_TBL_SIZE 240 +#define SPUR_DATA_LEN 16 +#define ENTRIES_EACH_CMD 15 +#define SPUR_DATA_INDEX 2 +#define FM_AF_LIST_MAX_SIZE 200 +/* Each AF frequency consist of sizeof(int) bytes */ +#define AF_LIST_MAX (FM_AF_LIST_MAX_SIZE / 4) + +#define MAX_BLEND_INDEX 49 + +#define TUNE_PARAM 16 +#define FM_RDS_3A_GRP (0x40) +struct radio_hci_command_hdr { + __le16 opcode; /* OCF & OGF */ + __u8 plen; +} __packed; + +struct radio_hci_event_hdr { + __u8 evt; + __u8 plen; +} __packed; + +/* Opcode OCF */ +/* HCI recv control commands opcode */ +#define HCI_OCF_FM_ENABLE_RECV_REQ 0x0001 +#define HCI_OCF_FM_DISABLE_RECV_REQ 0x0002 +#define HCI_OCF_FM_GET_RECV_CONF_REQ 0x0003 +#define HCI_OCF_FM_SET_RECV_CONF_REQ 0x0004 +#define HCI_OCF_FM_SET_MUTE_MODE_REQ 0x0005 +#define HCI_OCF_FM_SET_STEREO_MODE_REQ 0x0006 +#define HCI_OCF_FM_SET_ANTENNA 0x0007 +#define HCI_OCF_FM_SET_SIGNAL_THRESHOLD 0x0008 +#define HCI_OCF_FM_GET_SIGNAL_THRESHOLD 0x0009 +#define HCI_OCF_FM_GET_STATION_PARAM_REQ 0x000A +#define HCI_OCF_FM_GET_PROGRAM_SERVICE_REQ 0x000B +#define HCI_OCF_FM_GET_RADIO_TEXT_REQ 0x000C +#define HCI_OCF_FM_GET_AF_LIST_REQ 0x000D +#define HCI_OCF_FM_SEARCH_STATIONS 0x000E +#define HCI_OCF_FM_SEARCH_RDS_STATIONS 0x000F +#define HCI_OCF_FM_SEARCH_STATIONS_LIST 0x0010 +#define HCI_OCF_FM_CANCEL_SEARCH 0x0011 +#define HCI_OCF_FM_RDS_GRP 0x0012 +#define HCI_OCF_FM_RDS_GRP_PROCESS 0x0013 +#define HCI_OCF_FM_EN_WAN_AVD_CTRL 0x0014 +#define HCI_OCF_FM_EN_NOTCH_CTRL 0x0015 +#define HCI_OCF_FM_SET_EVENT_MASK 0x0016 +#define HCI_OCF_FM_SET_CH_DET_THRESHOLD 0x0017 +#define HCI_OCF_FM_GET_CH_DET_THRESHOLD 0x0018 +#define HCI_OCF_FM_SET_BLND_TBL 0x001B +#define HCI_OCF_FM_GET_BLND_TBL 0x001C +/* HCI trans control commans opcode*/ +#define HCI_OCF_FM_ENABLE_TRANS_REQ 0x0001 +#define HCI_OCF_FM_DISABLE_TRANS_REQ 0x0002 +#define HCI_OCF_FM_GET_TRANS_CONF_REQ 0x0003 +#define HCI_OCF_FM_SET_TRANS_CONF_REQ 0x0004 +#define HCI_OCF_FM_RDS_RT_REQ 0x0008 +#define HCI_OCF_FM_RDS_PS_REQ 0x0009 + + +/* HCI common control commands opcode */ +#define HCI_OCF_FM_TUNE_STATION_REQ 0x0001 +#define HCI_OCF_FM_DEFAULT_DATA_READ 0x0002 +#define HCI_OCF_FM_DEFAULT_DATA_WRITE 0x0003 +#define HCI_OCF_FM_RESET 0x0004 +#define HCI_OCF_FM_GET_FEATURE_LIST 0x0005 +#define HCI_OCF_FM_DO_CALIBRATION 0x0006 +#define HCI_OCF_FM_SET_CALIBRATION 0x0007 +#define HCI_OCF_FM_SET_SPUR_TABLE 0x0008 +#define HCI_OCF_FM_GET_SPUR_TABLE 0x0009 + +/*HCI Status parameters commands*/ +#define HCI_OCF_FM_READ_GRP_COUNTERS 0x0001 + +/*HCI Diagnostic commands*/ +#define HCI_OCF_FM_PEEK_DATA 0x0002 +#define HCI_OCF_FM_POKE_DATA 0x0003 +#define HCI_OCF_FM_SSBI_PEEK_REG 0x0004 +#define HCI_OCF_FM_SSBI_POKE_REG 0x0005 +#define HCI_OCF_FM_STATION_DBG_PARAM 0x0007 +#define HCI_FM_SET_INTERNAL_TONE_GENRATOR 0x0008 + +/* Opcode OGF */ +#define HCI_OGF_FM_RECV_CTRL_CMD_REQ 0x0013 +#define HCI_OGF_FM_TRANS_CTRL_CMD_REQ 0x0014 +#define HCI_OGF_FM_COMMON_CTRL_CMD_REQ 0x0015 +#define HCI_OGF_FM_STATUS_PARAMETERS_CMD_REQ 0x0016 +#define HCI_OGF_FM_TEST_CMD_REQ 0x0017 +#define HCI_OGF_FM_DIAGNOSTIC_CMD_REQ 0x003F + +/* Command opcode pack/unpack */ +#define hci_opcode_pack(ogf, ocf) ((__u16) ((ocf & 0x03ff)|(ogf << 10))) +#define hci_opcode_ogf(op) (op >> 10) +#define hci_opcode_ocf(op) (op & 0x03ff) +#define hci_recv_ctrl_cmd_op_pack(ocf) \ + ((__u16) hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ, ocf)) +#define hci_trans_ctrl_cmd_op_pack(ocf) \ + ((__u16) hci_opcode_pack(HCI_OGF_FM_TRANS_CTRL_CMD_REQ, ocf)) +#define hci_common_cmd_op_pack(ocf) \ + ((__u16) hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ, ocf)) +#define hci_status_param_op_pack(ocf) \ + ((__u16) hci_opcode_pack(HCI_OGF_FM_STATUS_PARAMETERS_CMD_REQ, ocf)) +#define hci_diagnostic_cmd_op_pack(ocf) \ + ((__u16) hci_opcode_pack(HCI_OGF_FM_DIAGNOSTIC_CMD_REQ, ocf)) + + +/* HCI commands with no arguments*/ +#define HCI_FM_ENABLE_RECV_CMD 1 +#define HCI_FM_DISABLE_RECV_CMD 2 +#define HCI_FM_GET_RECV_CONF_CMD 3 +#define HCI_FM_GET_STATION_PARAM_CMD 4 +#define HCI_FM_GET_SIGNAL_TH_CMD 5 +#define HCI_FM_GET_PROGRAM_SERVICE_CMD 6 +#define HCI_FM_GET_RADIO_TEXT_CMD 7 +#define HCI_FM_GET_AF_LIST_CMD 8 +#define HCI_FM_CANCEL_SEARCH_CMD 9 +#define HCI_FM_RESET_CMD 10 +#define HCI_FM_GET_FEATURES_CMD 11 +#define HCI_FM_STATION_DBG_PARAM_CMD 12 +#define HCI_FM_ENABLE_TRANS_CMD 13 +#define HCI_FM_DISABLE_TRANS_CMD 14 +#define HCI_FM_GET_TX_CONFIG 15 +#define HCI_FM_GET_DET_CH_TH_CMD 16 +#define HCI_FM_GET_BLND_TBL_CMD 17 + +/* Defines for FM TX*/ +#define TX_PS_DATA_LENGTH 108 +#define TX_RT_DATA_LENGTH 64 +#define PS_STRING_LEN 9 + +/* ----- HCI Command request ----- */ +struct hci_fm_recv_conf_req { + __u8 emphasis; + __u8 ch_spacing; + __u8 rds_std; + __u8 hlsi; + __u32 band_low_limit; + __u32 band_high_limit; +} __packed; + +/* ----- HCI Command request ----- */ +struct hci_fm_trans_conf_req_struct { + __u8 emphasis; + __u8 rds_std; + __u32 band_low_limit; + __u32 band_high_limit; +} __packed; + + +/* ----- HCI Command request ----- */ +struct hci_fm_tx_ps { + __u8 ps_control; + __u16 pi; + __u8 pty; + __u8 ps_repeatcount; + __u8 ps_num; + __u8 ps_data[TX_PS_DATA_LENGTH]; +} __packed; + +struct hci_fm_tx_rt { + __u8 rt_control; + __u16 pi; + __u8 pty; + __u8 rt_len; + __u8 rt_data[TX_RT_DATA_LENGTH]; +} __packed; + +struct hci_fm_mute_mode_req { + __u8 hard_mute; + __u8 soft_mute; +} __packed; + +struct hci_fm_stereo_mode_req { + __u8 stereo_mode; + __u8 sig_blend; + __u8 intf_blend; + __u8 most_switch; +} __packed; + +struct hci_fm_search_station_req { + __u8 srch_mode; + __u8 scan_time; + __u8 srch_dir; +} __packed; + +struct hci_fm_search_rds_station_req { + struct hci_fm_search_station_req srch_station; + __u8 srch_pty; + __u16 srch_pi; +} __packed; + +struct hci_fm_search_station_list_req { + __u8 srch_list_mode; + __u8 srch_list_dir; + __u32 srch_list_max; + __u8 srch_pty; +} __packed; + +struct hci_fm_rds_grp_req { + __u32 rds_grp_enable_mask; + __u32 rds_buf_size; + __u8 en_rds_change_filter; +} __packed; + +struct hci_fm_en_avd_ctrl_req { + __u8 no_freqs; + __u8 freq_index; + __u8 lo_shft; + __u16 freq_min; + __u16 freq_max; +} __packed; + +struct hci_fm_def_data_rd_req { + __u8 mode; + __u8 length; + __u8 param_len; + __u8 param; +} __packed; + +struct hci_fm_def_data_wr_req { + __u8 mode; + __u8 length; + __u8 data[DEFAULT_DATA_SIZE]; +} __packed; + +struct hci_fm_riva_data { + __u8 subopcode; + __u32 start_addr; + __u8 length; +} __packed; + +struct hci_fm_riva_poke { + struct hci_fm_riva_data cmd_params; + __u8 data[MAX_RIVA_PEEK_RSP_SIZE]; +} __packed; + +struct hci_fm_ssbi_req { + __u16 start_addr; + __u8 data; +} __packed; +struct hci_fm_ssbi_peek { + __u16 start_address; +} __packed; + +struct hci_fm_ch_det_threshold { + char sinr; + __u8 sinr_samples; + __u8 low_th; + __u8 high_th; + +} __packed; + +struct hci_fm_blend_table { + __u8 ucBlendType; + __u8 ucBlendRampRateUp; + __u8 ucBlendDebounceNumSampleUp; + __u8 ucBlendDebounceIdxUp; + __u8 ucBlendSinrIdxSkipStep; + __u8 scBlendSinrHi; + __u8 scBlendRmssiHi; + __u8 ucBlendIndexHi; + __u8 ucBlendIndex[MAX_BLEND_INDEX]; +} __packed; + +/*HCI events*/ +#define HCI_EV_TUNE_STATUS 0x01 +#define HCI_EV_RDS_LOCK_STATUS 0x02 +#define HCI_EV_STEREO_STATUS 0x03 +#define HCI_EV_SERVICE_AVAILABLE 0x04 +#define HCI_EV_SEARCH_PROGRESS 0x05 +#define HCI_EV_SEARCH_RDS_PROGRESS 0x06 +#define HCI_EV_SEARCH_LIST_PROGRESS 0x07 +#define HCI_EV_RDS_RX_DATA 0x08 +#define HCI_EV_PROGRAM_SERVICE 0x09 +#define HCI_EV_RADIO_TEXT 0x0A +#define HCI_EV_FM_AF_LIST 0x0B +#define HCI_EV_TX_RDS_GRP_AVBLE 0x0C +#define HCI_EV_TX_RDS_GRP_COMPL 0x0D +#define HCI_EV_TX_RDS_CONT_GRP_COMPL 0x0E +#define HCI_EV_CMD_COMPLETE 0x0F +#define HCI_EV_CMD_STATUS 0x10 +#define HCI_EV_TUNE_COMPLETE 0x11 +#define HCI_EV_SEARCH_COMPLETE 0x12 +#define HCI_EV_SEARCH_RDS_COMPLETE 0x13 +#define HCI_EV_SEARCH_LIST_COMPLETE 0x14 + +#define HCI_REQ_DONE 0 +#define HCI_REQ_PEND 1 +#define HCI_REQ_CANCELED 2 +#define HCI_REQ_STATUS 3 + +#define MAX_RAW_RDS_GRPS 21 + +#define RDSGRP_DATA_OFFSET 0x1 + +/*RT PLUS*/ +#define DUMMY_CLASS 0 +#define RT_PLUS_LEN_1_TAG 3 +#define RT_ERT_FLAG_BIT 5 + +/*TAG1*/ +#define TAG1_MSB_OFFSET 3 +#define TAG1_MSB_MASK 7 +#define TAG1_LSB_OFFSET 5 +#define TAG1_POS_MSB_MASK 31 +#define TAG1_POS_MSB_OFFSET 1 +#define TAG1_POS_LSB_OFFSET 7 +#define TAG1_LEN_OFFSET 1 +#define TAG1_LEN_MASK 63 + +/*TAG2*/ +#define TAG2_MSB_OFFSET 5 +#define TAG2_MSB_MASK 1 +#define TAG2_LSB_OFFSET 3 +#define TAG2_POS_MSB_MASK 7 +#define TAG2_POS_MSB_OFFSET 3 +#define TAG2_POS_LSB_OFFSET 5 +#define TAG2_LEN_MASK 31 + +#define AGT_MASK 31 +/*Extract 5 left most bits of lsb of 2nd block*/ +#define AGT(x) (x & AGT_MASK) +/*16 bits of 4th block*/ +#define AID(lsb, msb) ((msb << 8) | (lsb)) +/*Extract 5 right most bits of msb of 2nd block*/ +#define GTC(blk2msb) (blk2msb >> 3) + +#define GRP_3A 0x6 +#define RT_PLUS_AID 0x4bd7 + +/*ERT*/ +#define ERT_AID 0x6552 +#define CARRIAGE_RETURN 0x000D +#define MAX_ERT_SEGMENT 31 +#define ERT_FORMAT_DIR_BIT 1 + +#define EXTRACT_BIT(data, bit_pos) ((data & (1 << bit_pos)) >> bit_pos) + +struct hci_ev_tune_status { + __u8 sub_event; + __le32 station_freq; + __u8 serv_avble; + char rssi; + __u8 stereo_prg; + __u8 rds_sync_status; + __u8 mute_mode; + char sinr; + __u8 intf_det_th; +} __packed; + +struct rds_blk_data { + __u8 rdsMsb; + __u8 rdsLsb; + __u8 blockStatus; +} __packed; + +struct rds_grp_data { + struct rds_blk_data rdsBlk[4]; +} __packed; + +struct hci_ev_rds_rx_data { + __u8 num_rds_grps; + struct rds_grp_data rds_grp_data[MAX_RAW_RDS_GRPS]; +} __packed; + +struct hci_ev_prg_service { + __le16 pi_prg_id; + __u8 pty_prg_type; + __u8 ta_prg_code_type; + __u8 ta_ann_code_flag; + __u8 ms_switch_code_flag; + __u8 dec_id_ctrl_code_flag; + __u8 ps_num; + __u8 prg_service_name[119]; +} __packed; + +struct hci_ev_radio_text { + __le16 pi_prg_id; + __u8 pty_prg_type; + __u8 ta_prg_code_type; + __u8 txt_ab_flag; + __u8 radio_txt[64]; +} __packed; + +struct hci_ev_af_list { + __le32 tune_freq; + __le16 pi_code; + __u8 af_size; + __u8 af_list[FM_AF_LIST_MAX_SIZE]; +} __packed; + +struct hci_ev_cmd_complete { + __u8 num_hci_cmd_pkts; + __le16 cmd_opcode; +} __packed; + +struct hci_ev_cmd_status { + __u8 status; + __u8 num_hci_cmd_pkts; + __le16 status_opcode; +} __packed; + +struct hci_ev_srch_st { + __le32 station_freq; + __u8 rds_cap; + __u8 pty; + __le16 status_opcode; +} __packed; + +struct hci_ev_rel_freq { + __u8 rel_freq_msb; + __u8 rel_freq_lsb; + +} __packed; +struct hci_ev_srch_list_compl { + __u8 num_stations_found; + struct hci_ev_rel_freq rel_freq[20]; +} __packed; + +/* ----- HCI Event Response ----- */ +struct hci_fm_conf_rsp { + __u8 status; + struct hci_fm_recv_conf_req recv_conf_rsp; +} __packed; + +struct hci_fm_get_trans_conf_rsp { + __u8 status; + struct hci_fm_trans_conf_req_struct trans_conf_rsp; +} __packed; +struct hci_fm_sig_threshold_rsp { + __u8 status; + __u8 sig_threshold; +} __packed; + +struct hci_fm_station_rsp { + struct hci_ev_tune_status station_rsp; +} __packed; + +struct hci_fm_prgm_srv_rsp { + __u8 status; + struct hci_ev_prg_service prg_srv; +} __packed; + +struct hci_fm_radio_txt_rsp { + __u8 status; + struct hci_ev_radio_text rd_txt; +} __packed; + +struct hci_fm_af_list_rsp { + __u8 status; + struct hci_ev_af_list rd_txt; +} __packed; + +struct hci_fm_data_rd_rsp { + __u8 status; + __u8 ret_data_len; + __u8 data[DEFAULT_DATA_SIZE]; +} __packed; + +struct hci_fm_feature_list_rsp { + __u8 status; + __u8 feature_mask; +} __packed; + +struct hci_fm_dbg_param_rsp { + __u8 status; + __u8 blend; + __u8 soft_mute; + __u8 inf_blend; + __u8 inf_soft_mute; + __u8 pilot_pil; + __u8 io_verc; + __u8 in_det_out; +} __packed; + +#define CLKSPURID_INDEX0 0 +#define CLKSPURID_INDEX1 5 +#define CLKSPURID_INDEX2 10 +#define CLKSPURID_INDEX3 15 +#define CLKSPURID_INDEX4 20 +#define CLKSPURID_INDEX5 25 + +#define MAX_SPUR_FREQ_LIMIT 30 +#define CKK_SPUR 0x3B +#define SPUR_DATA_SIZE 0x4 +#define SPUR_ENTRIES_PER_ID 0x5 + +#define COMPUTE_SPUR(val) ((((val) - (76000)) / (50))) +#define GET_FREQ(val, bit) ((bit == 1) ? ((val) >> 8) : ((val) & 0xFF)) +#define GET_SPUR_ENTRY_LEVEL(val) ((val) / (5)) + +struct hci_fm_spur_data { + __u32 freq[MAX_SPUR_FREQ_LIMIT]; + __s8 rmssi[MAX_SPUR_FREQ_LIMIT]; + __u8 enable[MAX_SPUR_FREQ_LIMIT]; +} __packed; + + +/* HCI dev events */ +#define RADIO_HCI_DEV_REG 1 +#define RADIO_HCI_DEV_WRITE 2 + +/* FM RDS */ +#define RDS_PTYPE 2 +#define RDS_PID_LOWER 1 +#define RDS_PID_HIGHER 0 +#define RDS_OFFSET 5 +#define RDS_PS_LENGTH_OFFSET 7 +#define RDS_STRING 8 +#define RDS_PS_DATA_OFFSET 8 +#define RDS_CONFIG_OFFSET 3 +#define RDS_AF_JUMP_OFFSET 4 +#define PI_CODE_OFFSET 4 +#define AF_SIZE_OFFSET 6 +#define AF_LIST_OFFSET 7 +#define RT_A_B_FLAG_OFFSET 4 +/*FM states*/ + +enum radio_state_t { + FM_OFF, + FM_RECV, + FM_TRANS, + FM_RESET, + FM_CALIB, + FM_TURNING_OFF, + FM_RECV_TURNING_ON, + FM_TRANS_TURNING_ON, + FM_MAX_NO_STATES, +}; + +enum emphasis_type { + FM_RX_EMP75 = 0x0, + FM_RX_EMP50 = 0x1 +}; + +enum channel_space_type { + FM_RX_SPACE_200KHZ = 0x0, + FM_RX_SPACE_100KHZ = 0x1, + FM_RX_SPACE_50KHZ = 0x2 +}; + +enum high_low_injection { + AUTO_HI_LO_INJECTION = 0x0, + LOW_SIDE_INJECTION = 0x1, + HIGH_SIDE_INJECTION = 0x2 +}; + +enum fm_rds_type { + FM_RX_RDBS_SYSTEM = 0x0, + FM_RX_RDS_SYSTEM = 0x1 +}; + +enum iris_region_t { + IRIS_REGION_US, + IRIS_REGION_EU, + IRIS_REGION_JAPAN, + IRIS_REGION_JAPAN_WIDE, + IRIS_REGION_OTHER +}; + +#define STD_BUF_SIZE (256) + +enum iris_buf_t { + IRIS_BUF_SRCH_LIST, + IRIS_BUF_EVENTS, + IRIS_BUF_RT_RDS, + IRIS_BUF_PS_RDS, + IRIS_BUF_RAW_RDS, + IRIS_BUF_AF_LIST, + IRIS_BUF_PEEK, + IRIS_BUF_SSBI_PEEK, + IRIS_BUF_RDS_CNTRS, + IRIS_BUF_RD_DEFAULT, + IRIS_BUF_CAL_DATA, + IRIS_BUF_RT_PLUS, + IRIS_BUF_ERT, + IRIS_BUF_SPUR, + IRIS_BUF_MAX, +}; + +enum iris_xfr_t { + IRIS_XFR_SYNC, + IRIS_XFR_ERROR, + IRIS_XFR_SRCH_LIST, + IRIS_XFR_RT_RDS, + IRIS_XFR_PS_RDS, + IRIS_XFR_AF_LIST, + IRIS_XFR_MAX +}; + +/* Search options */ +enum search_t { + SEEK, + SCAN, + SCAN_FOR_STRONG, + SCAN_FOR_WEAK, + RDS_SEEK_PTY, + RDS_SCAN_PTY, + RDS_SEEK_PI, + RDS_AF_JUMP, +}; + +enum spur_entry_levels { + ENTRY_0, + ENTRY_1, + ENTRY_2, + ENTRY_3, + ENTRY_4, + ENTRY_5, +}; + +/* Band limits */ +#define REGION_US_EU_BAND_LOW 87500 +#define REGION_US_EU_BAND_HIGH 108000 +#define REGION_JAPAN_STANDARD_BAND_LOW 76000 +#define REGION_JAPAN_STANDARD_BAND_HIGH 90000 +#define REGION_JAPAN_WIDE_BAND_LOW 90000 +#define REGION_JAPAN_WIDE_BAND_HIGH 108000 + +#define SRCH_MODE 0x07 +#define SRCH_DIR 0x08 /* 0-up 1-down */ +#define SCAN_DWELL 0x70 +#define SRCH_ON 0x80 + +/* I/O Control */ +#define IOC_HRD_MUTE 0x03 +#define IOC_SFT_MUTE 0x01 +#define IOC_MON_STR 0x01 +#define IOC_SIG_BLND 0x01 +#define IOC_INTF_BLND 0x01 +#define IOC_ANTENNA 0x01 + +/* RDS Control */ +#define RDS_ON 0x01 +#define RDS_BUF_SZ 100 + +/* constants */ +#define RDS_BLOCKS_NUM (4) +#define BYTES_PER_BLOCK (3) +#define MAX_PS_LENGTH (108) +#define MAX_RT_LENGTH (64) +#define RDS_GRP_CNTR_LEN (36) +#define RX_RT_DATA_LENGTH (63) +/* Search direction */ +#define SRCH_DIR_UP (0) +#define SRCH_DIR_DOWN (1) + +/*Search RDS stations*/ +#define SEARCH_RDS_STNS_MODE_OFFSET 4 + +/*Search Station list */ +#define PARAMS_PER_STATION 0x08 +#define STN_NUM_OFFSET 0x01 +#define STN_FREQ_OFFSET 0x02 +#define KHZ_TO_MHZ 1000 +#define GET_MSB(x)((x >> 8) & 0xFF) +#define GET_LSB(x)((x) & 0xFF) + +/* control options */ +#define CTRL_ON (1) +#define CTRL_OFF (0) + +/*Diagnostic commands*/ + +#define RIVA_PEEK_OPCODE 0x0D +#define RIVA_POKE_OPCODE 0x0C + +#define PEEK_DATA_OFSET 0x1 +#define RIVA_PEEK_PARAM 0x6 +#define RIVA_PEEK_LEN_OFSET 0x6 +#define SSBI_PEEK_LEN 0x01 +/*Calibration data*/ +#define PROCS_CALIB_MODE 1 +#define PROCS_CALIB_SIZE 23 +#define DC_CALIB_MODE 2 +#define DC_CALIB_SIZE 48 +#define RSB_CALIB_MODE 3 +#define RSB_CALIB_SIZE 4 +#define CALIB_DATA_OFSET 2 +#define CALIB_MODE_OFSET 1 +#define MAX_CALIB_SIZE 75 + +/* Channel validity */ +#define INVALID_CHANNEL (0) +#define VALID_CHANNEL (1) + +struct hci_fm_set_cal_req_proc { + __u8 mode; + /*Max process calibration data size*/ + __u8 data[PROCS_CALIB_SIZE]; +} __packed; + +struct hci_fm_set_cal_req_dc { + __u8 mode; + /*Max DC calibration data size*/ + __u8 data[DC_CALIB_SIZE]; +} __packed; + +struct hci_cc_do_calibration_rsp { + __u8 status; + __u8 mode; + __u8 data[MAX_CALIB_SIZE]; +} __packed; + +struct hci_fm_set_spur_table_req { + __u8 mode; + __u8 no_of_freqs_entries; + __u8 spur_data[FM_SPUR_TBL_SIZE]; +} __packed; +/* Low Power mode*/ +#define SIG_LEVEL_INTR (1 << 0) +#define RDS_SYNC_INTR (1 << 1) +#define AUDIO_CTRL_INTR (1 << 2) +#define AF_JUMP_ENABLE (1 << 4) + +#endif |