diff options
Diffstat (limited to 'include/uapi/drm')
| -rw-r--r-- | include/uapi/drm/Kbuild | 22 | ||||
| -rw-r--r-- | include/uapi/drm/drm.h | 25 | ||||
| -rw-r--r-- | include/uapi/drm/drm_fourcc.h | 39 | ||||
| -rw-r--r-- | include/uapi/drm/drm_mode.h | 36 | ||||
| -rw-r--r-- | include/uapi/drm/drm_sarea.h | 8 | ||||
| -rw-r--r-- | include/uapi/drm/msm_drm.h | 332 | ||||
| -rw-r--r-- | include/uapi/drm/msm_drm_pp.h | 200 | ||||
| -rw-r--r-- | include/uapi/drm/sde_drm.h | 351 |
8 files changed, 976 insertions, 37 deletions
diff --git a/include/uapi/drm/Kbuild b/include/uapi/drm/Kbuild index 38d437096c35..bafc163da5b8 100644 --- a/include/uapi/drm/Kbuild +++ b/include/uapi/drm/Kbuild @@ -1,20 +1,4 @@ # UAPI Header export list -header-y += drm.h -header-y += drm_fourcc.h -header-y += drm_mode.h -header-y += drm_sarea.h -header-y += exynos_drm.h -header-y += i810_drm.h -header-y += i915_drm.h -header-y += mga_drm.h -header-y += nouveau_drm.h -header-y += qxl_drm.h -header-y += r128_drm.h -header-y += radeon_drm.h -header-y += savage_drm.h -header-y += sis_drm.h -header-y += tegra_drm.h -header-y += via_drm.h -header-y += vmwgfx_drm.h -header-y += msm_drm.h -header-y += virtgpu_drm.h +no-export-headers += amdgpu_drm.h +no-export-headers += armada_drm.h +no-export-headers += omap_drm.h diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index 3801584a0c53..e127ac05cdb0 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -58,6 +58,10 @@ typedef unsigned long drm_handle_t; #endif +#if defined(__cplusplus) +extern "C" { +#endif + #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ @@ -372,7 +376,11 @@ struct drm_buf_pub { */ struct drm_buf_map { int count; /**< Length of the buffer list */ +#ifdef __cplusplus + void __user *virt; +#else void __user *virtual; /**< Mmap'd area in user-virtual */ +#endif struct drm_buf_pub __user *list; /**< Buffer information */ }; @@ -631,6 +639,7 @@ struct drm_gem_open { #define DRM_CAP_CURSOR_WIDTH 0x8 #define DRM_CAP_CURSOR_HEIGHT 0x9 #define DRM_CAP_ADDFB2_MODIFIERS 0x10 +#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 /** DRM_IOCTL_GET_CAP ioctl argument type */ struct drm_get_cap { @@ -679,7 +688,15 @@ struct drm_prime_handle { __s32 fd; }; -#include <drm/drm_mode.h> +#if defined(__cplusplus) +} +#endif + +#include "drm_mode.h" + +#if defined(__cplusplus) +extern "C" { +#endif #define DRM_IOCTL_BASE 'd' #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) @@ -826,7 +843,7 @@ struct drm_event_vblank { __u32 tv_sec; __u32 tv_usec; __u32 sequence; - __u32 reserved; + __u32 crtc_id; /* 0 on older kernels that do not support this */ }; /* typedef area */ @@ -874,4 +891,8 @@ typedef struct drm_scatter_gather drm_scatter_gather_t; typedef struct drm_set_version drm_set_version_t; #endif +#if defined(__cplusplus) +} +#endif + #endif diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index f28f79966e9e..ad810d443ace 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -26,6 +26,10 @@ #include <linux/types.h> +#if defined(__cplusplus) +extern "C" { +#endif + #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ ((__u32)(c) << 16) | ((__u32)(d) << 24)) @@ -230,4 +234,39 @@ */ #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) +/* + * Qualcomm Compressed Format + * + * Refers to a compressed variant of the base format that is compressed. + * Implementation may be platform and base-format specific. + */ +#define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1) + +/* + * QTI DX Format + * + * Refers to a DX variant of the base format. + * Implementation may be platform and base-format specific. + */ +#define DRM_FORMAT_MOD_QCOM_DX fourcc_mod_code(QCOM, 0x2) + +/* + * QTI Tight Format + * + * Refers to a tightly packed variant of the base format. + * Implementation may be platform and base-format specific. + */ +#define DRM_FORMAT_MOD_QCOM_TIGHT fourcc_mod_code(QCOM, 0x4) + +/* + * QTI Tile Format + * + * Refers to a tile variant of the base format. + * Implementation may be platform and base-format specific. + */ +#define DRM_FORMAT_MOD_QCOM_TILE fourcc_mod_code(QCOM, 0x8) + +#if defined(__cplusplus) +} +#endif #endif /* DRM_FOURCC_H */ diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 6c11ca401de8..a73de08c6584 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -29,6 +29,10 @@ #include <linux/types.h> +#if defined(__cplusplus) +extern "C" { +#endif + #define DRM_DISPLAY_INFO_LEN 32 #define DRM_CONNECTOR_NAME_LEN 32 #define DRM_DISPLAY_MODE_LEN 32 @@ -72,7 +76,29 @@ #define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14) #define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) +#define DRM_MODE_FLAG_SEAMLESS (1<<19) +#define DRM_MODE_FLAG_SUPPORTS_RGB (1<<20) +#define DRM_MODE_FLAG_SUPPORTS_YUV (1<<21) +/* Picture aspect ratio options */ +#define DRM_MODE_PICTURE_ASPECT_NONE 0 +#define DRM_MODE_PICTURE_ASPECT_4_3 1 +#define DRM_MODE_PICTURE_ASPECT_16_9 2 +#define DRM_MODE_PICTURE_ASPECT_64_27 3 +#define DRM_MODE_PICTURE_ASPECT_256_135 4 + +/* Aspect ratio flag bitmask (4 bits 27:24) */ +#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<24) +#define DRM_MODE_FLAG_PIC_AR_NONE \ + (DRM_MODE_PICTURE_ASPECT_NONE<<24) +#define DRM_MODE_FLAG_PIC_AR_4_3 \ + (DRM_MODE_PICTURE_ASPECT_4_3<<24) +#define DRM_MODE_FLAG_PIC_AR_16_9 \ + (DRM_MODE_PICTURE_ASPECT_16_9<<24) +#define DRM_MODE_FLAG_PIC_AR_64_27 \ + (DRM_MODE_PICTURE_ASPECT_64_27<<24) +#define DRM_MODE_FLAG_PIC_AR_256_135 \ + (DRM_MODE_PICTURE_ASPECT_256_135<<24) /* DPMS flags */ /* bit compatible with the xorg definitions. */ @@ -88,11 +114,6 @@ #define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ #define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ -/* Picture aspect ratio options */ -#define DRM_MODE_PICTURE_ASPECT_NONE 0 -#define DRM_MODE_PICTURE_ASPECT_4_3 1 -#define DRM_MODE_PICTURE_ASPECT_16_9 2 - /* Dithering mode options */ #define DRM_MODE_DITHERING_OFF 0 #define DRM_MODE_DITHERING_ON 1 @@ -354,6 +375,7 @@ struct drm_mode_fb_cmd { #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ #define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */ +#define DRM_MODE_FB_SECURE (1<<2) /* for secure framebuffers */ struct drm_mode_fb_cmd2 { __u32 fb_id; @@ -596,4 +618,8 @@ struct drm_mode_destroy_blob { __u32 blob_id; }; +#if defined(__cplusplus) +} +#endif + #endif diff --git a/include/uapi/drm/drm_sarea.h b/include/uapi/drm/drm_sarea.h index 413a5642d49f..12285bc929a1 100644 --- a/include/uapi/drm/drm_sarea.h +++ b/include/uapi/drm/drm_sarea.h @@ -34,6 +34,10 @@ #include <drm/drm.h> +#if defined(__cplusplus) +extern "C" { +#endif + /* SAREA area needs to be at least a page */ #if defined(__alpha__) #define SAREA_MAX 0x2000U @@ -83,4 +87,8 @@ typedef struct drm_sarea_frame drm_sarea_frame_t; typedef struct drm_sarea drm_sarea_t; #endif +#if defined(__cplusplus) +} +#endif + #endif /* _DRM_SAREA_H_ */ diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index 75a232b9a970..583ebc4616e9 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -20,6 +20,11 @@ #include <stddef.h> #include <drm/drm.h> +#include <drm/sde_drm.h> + +#if defined(__cplusplus) +extern "C" { +#endif /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints: @@ -39,6 +44,15 @@ #define MSM_PIPE_2D1 0x02 #define MSM_PIPE_3D0 0x10 +/* The pipe-id just uses the lower bits, so can be OR'd with flags in + * the upper 16 bits (which could be extended further, if needed, maybe + * we extend/overload the pipe-id some day to deal with multiple rings, + * but even then I don't think we need the full lower 16 bits). + */ +#define MSM_PIPE_ID_MASK 0xffff +#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) +#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) + /* timeouts are specified in clock-monotonic absolute times (to simplify * restarting interrupted ioctls). The following struct is logically the * same as 'struct timespec' but 32/64b ABI safe. @@ -48,9 +62,73 @@ struct drm_msm_timespec { __s64 tv_nsec; /* nanoseconds */ }; -#define MSM_PARAM_GPU_ID 0x01 -#define MSM_PARAM_GMEM_SIZE 0x02 -#define MSM_PARAM_CHIP_ID 0x03 +/* From CEA.861.3 */ +#define HDR_EOTF_SMTPE_ST2084 0x2 +#define HDR_EOTF_HLG 0x3 + +/* hdr hdmi state takes possible values of 0, 1 and 2 respectively */ +#define DRM_MSM_HDR_DISABLE 0 +#define DRM_MSM_HDR_ENABLE 1 +#define DRM_MSM_HDR_RESET 2 + +/* + * HDR Metadata + * These are defined as per EDID spec and shall be used by the sink + * to set the HDR metadata for playback from userspace. + */ + +#define HDR_PRIMARIES_COUNT 3 + +struct drm_msm_ext_panel_hdr_metadata { + __u32 eotf; /* electro optical transfer function */ + __u32 hdr_supported; /* HDR supported */ + __u32 display_primaries_x[HDR_PRIMARIES_COUNT]; /* Primaries x */ + __u32 display_primaries_y[HDR_PRIMARIES_COUNT]; /* Primaries y */ + __u32 white_point_x; /* white_point_x */ + __u32 white_point_y; /* white_point_y */ + __u32 max_luminance; /* Max luminance */ + __u32 min_luminance; /* Min Luminance */ + __u32 max_content_light_level; /* max content light level */ + __u32 max_average_light_level; /* max average light level */ +}; + +/** + * HDR Control + * This encapsulates the HDR metadata as well as a state control + * for the HDR metadata as required by the HDMI spec to send the + * relevant metadata depending on the state of the HDR playback. + * hdr_state: Controls HDR state, takes values ENABLE(1)/DISABLE(0) + * hdr_meta: Metadata sent by the userspace for the HDR clip + */ + +#define DRM_MSM_EXT_PANEL_HDR_CTRL +struct drm_msm_ext_panel_hdr_ctrl { + __u8 hdr_state; /* HDR state */ + struct drm_msm_ext_panel_hdr_metadata hdr_meta; /* HDR metadata */ +}; + +/** + * HDR sink properties + * These are defined as per EDID spec and shall be used by the userspace + * to determine the HDR properties to be set to the sink. + */ +struct drm_msm_ext_panel_hdr_properties { + __u8 hdr_metadata_type_one; /* static metadata type one */ + __u32 hdr_supported; /* HDR supported */ + __u32 hdr_eotf; /* electro optical transfer function */ + __u32 hdr_max_luminance; /* Max luminance */ + __u32 hdr_avg_luminance; /* Avg luminance */ + __u32 hdr_min_luminance; /* Min Luminance */ +}; + +#define MSM_PARAM_GPU_ID 0x01 +#define MSM_PARAM_GMEM_SIZE 0x02 +#define MSM_PARAM_CHIP_ID 0x03 +#define MSM_PARAM_MAX_FREQ 0x04 +#define MSM_PARAM_TIMESTAMP 0x05 +#define MSM_PARAM_GMEM_BASE 0x06 +#define MSM_PARAM_NR_RINGS 0x07 +#define MSM_PARAM_GPU_HANG_TIMEOUT 0xa0 /* timeout in ms */ struct drm_msm_param { __u32 pipe; /* in, MSM_PIPE_x */ @@ -64,6 +142,8 @@ struct drm_msm_param { #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */ #define MSM_BO_GPU_READONLY 0x00000002 +#define MSM_BO_PRIVILEGED 0x00000004 +#define MSM_BO_SECURE 0x00000008 /* Allocate and map as secure */ #define MSM_BO_CACHE_MASK 0x000f0000 /* cache modes */ #define MSM_BO_CACHED 0x00010000 @@ -72,6 +152,7 @@ struct drm_msm_param { #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ MSM_BO_GPU_READONLY | \ + MSM_BO_SECURE | \ MSM_BO_CACHED | \ MSM_BO_WC | \ MSM_BO_UNCACHED) @@ -82,10 +163,21 @@ struct drm_msm_gem_new { __u32 handle; /* out */ }; +struct drm_msm_gem_svm_new { + __u64 hostptr; /* in, must be page-aligned */ + __u64 size; /* in, must be page-aligned */ + __u32 flags; /* in, mask of MSM_BO_x */ + __u32 handle; /* out */ +}; + +#define MSM_INFO_IOVA 0x01 + +#define MSM_INFO_FLAGS (MSM_INFO_IOVA) + struct drm_msm_gem_info { __u32 handle; /* in */ - __u32 pad; - __u64 offset; /* out, offset to pass to mmap() */ + __u32 flags; /* in - combination of MSM_INFO_* flags */ + __u64 offset; /* out, mmap() offset or iova */ }; #define MSM_PREP_READ 0x01 @@ -121,7 +213,11 @@ struct drm_msm_gem_cpu_fini { */ struct drm_msm_gem_submit_reloc { __u32 submit_offset; /* in, offset from submit_bo */ - __u32 or; /* in, value OR'd with result */ +#ifdef __cplusplus + __u32 or_val; +#else + __u32 or; /* in, value OR'd with result */ +#endif __s32 shift; /* in, amount of left shift (can be negative) */ __u32 reloc_idx; /* in, index of reloc_bo buffer */ __u64 reloc_offset; /* in, offset from start of reloc_bo */ @@ -134,10 +230,13 @@ struct drm_msm_gem_submit_reloc { * this buffer in the first-level ringbuffer * CTX_RESTORE_BUF - only executed if there has been a GPU context * switch since the last SUBMIT ioctl + * PROFILE_BUF - A profiling buffer written to by both GPU and CPU. */ #define MSM_SUBMIT_CMD_BUF 0x0001 #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003 +#define MSM_SUBMIT_CMD_PROFILE_BUF 0x0004 + struct drm_msm_gem_submit_cmd { __u32 type; /* in, one of MSM_SUBMIT_CMD_x */ __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */ @@ -145,7 +244,7 @@ struct drm_msm_gem_submit_cmd { __u32 size; /* in, cmdstream size */ __u32 pad; __u32 nr_relocs; /* in, number of submit_reloc's */ - __u64 __user relocs; /* in, ptr to array of submit_reloc's */ + __u64 relocs; /* in, ptr to array of submit_reloc's */ }; /* Each buffer referenced elsewhere in the cmdstream submit (ie. the @@ -170,17 +269,39 @@ struct drm_msm_gem_submit_bo { __u64 presumed; /* in/out, presumed buffer address */ }; +/* Valid submit ioctl flags: */ +#define MSM_SUBMIT_RING_MASK 0x000F0000 +#define MSM_SUBMIT_RING_SHIFT 16 + +#define MSM_SUBMIT_FLAGS (MSM_SUBMIT_RING_MASK) + /* Each cmdstream submit consists of a table of buffers involved, and * one or more cmdstream buffers. This allows for conditional execution * (context-restore), and IB buffers needed for per tile/bin draw cmds. */ struct drm_msm_gem_submit { - __u32 pipe; /* in, MSM_PIPE_x */ + __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ __u32 fence; /* out */ __u32 nr_bos; /* in, number of submit_bo's */ __u32 nr_cmds; /* in, number of submit_cmd's */ - __u64 __user bos; /* in, ptr to array of submit_bo's */ - __u64 __user cmds; /* in, ptr to array of submit_cmd's */ + __u64 bos; /* in, ptr to array of submit_bo's */ + __u64 cmds; /* in, ptr to array of submit_cmd's */ + __s32 fence_fd; /* gap for the fence_fd which is upstream */ + __u32 queueid; /* in, submitqueue id */ +}; + +/* + * Define a preprocessor variable to let the userspace know that + * drm_msm_gem_submit_profile_buffer switched to only support a kernel timestamp + * for submit time + */ +#define MSM_PROFILE_BUFFER_SUBMIT_TIME 1 + +struct drm_msm_gem_submit_profile_buffer { + struct drm_msm_timespec time; /* out, submission time */ + __u64 ticks_queued; /* out, GPU ticks at ringbuffer submission */ + __u64 ticks_submitted; /* out, GPU ticks before cmdstream execution*/ + __u64 ticks_retired; /* out, GPU ticks after cmdstream execution */ }; /* The normal way to synchronize with the GPU is just to CPU_PREP on @@ -196,6 +317,141 @@ struct drm_msm_wait_fence { struct drm_msm_timespec timeout; /* in */ }; +/** + * struct drm_msm_event_req - Payload to event enable/disable ioctls. + * @object_id: DRM object id. Ex: for crtc pass crtc id. + * @object_type: DRM object type. Ex: for crtc set it to DRM_MODE_OBJECT_CRTC. + * @event: Event for which notification is being enabled/disabled. + * Ex: for Histogram set - DRM_EVENT_HISTOGRAM. + * @client_context: Opaque pointer that will be returned during event response + * notification. + * @index: Object index(ex: crtc index), optional for user-space to set. + * Driver will override value based on object_id and object_type. + */ +struct drm_msm_event_req { + __u32 object_id; + __u32 object_type; + __u32 event; + __u64 client_context; + __u32 index; +}; + +/** + * struct drm_msm_event_resp - payload returned when read is called for + * custom notifications. + * @base: Event type and length of complete notification payload. + * @info: Contains information about DRM that which raised this event. + * @data: Custom payload that driver returns for event type. + * size of data = base.length - (sizeof(base) + sizeof(info)) + */ +struct drm_msm_event_resp { + struct drm_event base; + struct drm_msm_event_req info; + __u8 data[]; +}; + +#define MSM_COUNTER_GROUP_CP 0 +#define MSM_COUNTER_GROUP_RBBM 1 +#define MSM_COUNTER_GROUP_PC 2 +#define MSM_COUNTER_GROUP_VFD 3 +#define MSM_COUNTER_GROUP_HLSQ 4 +#define MSM_COUNTER_GROUP_VPC 5 +#define MSM_COUNTER_GROUP_TSE 6 +#define MSM_COUNTER_GROUP_RAS 7 +#define MSM_COUNTER_GROUP_UCHE 8 +#define MSM_COUNTER_GROUP_TP 9 +#define MSM_COUNTER_GROUP_SP 10 +#define MSM_COUNTER_GROUP_RB 11 +#define MSM_COUNTER_GROUP_VBIF 12 +#define MSM_COUNTER_GROUP_VBIF_PWR 13 +#define MSM_COUNTER_GROUP_VSC 23 +#define MSM_COUNTER_GROUP_CCU 24 +#define MSM_COUNTER_GROUP_LRZ 25 +#define MSM_COUNTER_GROUP_CMP 26 +#define MSM_COUNTER_GROUP_ALWAYSON 27 +#define MSM_COUNTER_GROUP_SP_PWR 28 +#define MSM_COUNTER_GROUP_TP_PWR 29 +#define MSM_COUNTER_GROUP_RB_PWR 30 +#define MSM_COUNTER_GROUP_CCU_PWR 31 +#define MSM_COUNTER_GROUP_UCHE_PWR 32 +#define MSM_COUNTER_GROUP_CP_PWR 33 +#define MSM_COUNTER_GROUP_GPMU_PWR 34 +#define MSM_COUNTER_GROUP_ALWAYSON_PWR 35 + +/** + * struct drm_msm_counter - allocate or release a GPU performance counter + * @groupid: The group ID of the counter to get/put + * @counterid: For GET returns the counterid that was assigned. For PUT + * release the counter identified by groupid/counterid + * @countable: For GET the countable for the counter + */ +struct drm_msm_counter { + __u32 groupid; + int counterid; + __u32 countable; + __u32 counter_lo; + __u32 counter_hi; +}; + +struct drm_msm_counter_read_op { + __u64 value; + __u32 groupid; + int counterid; +}; + +/** + * struct drm_msm_counter_read - Read a number of GPU performance counters + * ops: Pointer to the list of struct drm_msm_counter_read_op operations + * nr_ops: Number of operations in the list + */ +struct drm_msm_counter_read { + __u64 __user ops; + __u32 nr_ops; +}; + +#define MSM_GEM_SYNC_TO_DEV 0 +#define MSM_GEM_SYNC_TO_CPU 1 + +struct drm_msm_gem_syncop { + __u32 handle; + __u32 op; +}; + +struct drm_msm_gem_sync { + __u32 nr_ops; + __u64 __user ops; +}; + +/* + * Draw queues allow the user to set specific submission parameter. Command + * submissions will specify a specific submit queue id to use. id '0' is + * reserved as a "default" drawqueue with medium priority. The user can safely + * use and query 0 but cannot destroy it. + */ + +/* + * Allows a process to bypass the 2 second quality of service timeout. + * Only CAP_SYS_ADMIN capable processes can set this flag. + */ +#define MSM_SUBMITQUEUE_BYPASS_QOS_TIMEOUT 0x00000001 + +#define MSM_SUBMITQUEUE_FLAGS (MSM_SUBMITQUEUE_BYPASS_QOS_TIMEOUT) + +struct drm_msm_submitqueue { + __u32 flags; /* in, MSM_SUBMITQUEUE_x */ + __u32 prio; /* in, Priority level */ + __u32 id; /* out, identifier */ +}; + +#define MSM_SUBMITQUEUE_PARAM_FAULTS 0 + +struct drm_msm_submitqueue_query { + __u64 data; + __u32 id; + __u32 param; + __u32 len; +}; + #define DRM_MSM_GET_PARAM 0x00 /* placeholder: #define DRM_MSM_SET_PARAM 0x01 @@ -206,7 +462,28 @@ struct drm_msm_wait_fence { #define DRM_MSM_GEM_CPU_FINI 0x05 #define DRM_MSM_GEM_SUBMIT 0x06 #define DRM_MSM_WAIT_FENCE 0x07 -#define DRM_MSM_NUM_IOCTLS 0x08 +/* Gap for upstream DRM_MSM_GEM_MADVISE */ +#define DRM_MSM_GEM_SVM_NEW 0x09 +#define DRM_MSM_SUBMITQUEUE_NEW 0x0A +#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B +#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C + +#define DRM_SDE_WB_CONFIG 0x40 +#define DRM_MSM_REGISTER_EVENT 0x41 +#define DRM_MSM_DEREGISTER_EVENT 0x42 +#define DRM_MSM_COUNTER_GET 0x43 +#define DRM_MSM_COUNTER_PUT 0x44 +#define DRM_MSM_COUNTER_READ 0x45 +#define DRM_MSM_GEM_SYNC 0x46 +#define DRM_MSM_RMFB2 0x47 + +/** + * Currently DRM framework supports only VSYNC event. + * Starting the custom events at 0xff to provide space for DRM + * framework to add new events. + */ +#define DRM_EVENT_HISTOGRAM 0xff +#define DRM_EVENT_AD 0x100 #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) @@ -215,5 +492,38 @@ struct drm_msm_wait_fence { #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) +#define DRM_IOCTL_SDE_WB_CONFIG \ + DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg) +#define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ + DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req) +#define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \ + DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req) +#define DRM_IOCTL_MSM_COUNTER_GET \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_COUNTER_GET, struct drm_msm_counter) +#define DRM_IOCTL_MSM_COUNTER_PUT \ + DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_COUNTER_PUT, struct drm_msm_counter) +#define DRM_IOCTL_MSM_COUNTER_READ \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_COUNTER_READ, \ + struct drm_msm_counter_read) +#define DRM_IOCTL_MSM_GEM_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_SYNC,\ + struct drm_msm_gem_sync) +#define DRM_IOCTL_MSM_GEM_SVM_NEW \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SVM_NEW, \ + struct drm_msm_gem_svm_new) +#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, \ + struct drm_msm_submitqueue) +#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE \ + DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, \ + struct drm_msm_submitqueue) +#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, \ + struct drm_msm_submitqueue_query) +#define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + \ + DRM_MSM_RMFB2), unsigned int) + +#if defined(__cplusplus) +} +#endif #endif /* __MSM_DRM_H__ */ diff --git a/include/uapi/drm/msm_drm_pp.h b/include/uapi/drm/msm_drm_pp.h new file mode 100644 index 000000000000..5f5ca0345140 --- /dev/null +++ b/include/uapi/drm/msm_drm_pp.h @@ -0,0 +1,200 @@ +#ifndef _MSM_DRM_PP_H_ +#define _MSM_DRM_PP_H_ + +#include <drm/drm.h> + +/** + * struct drm_msm_pcc_coeff - PCC coefficient structure for each color + * component. + * @c: constant coefficient. + * @r: red coefficient. + * @g: green coefficient. + * @b: blue coefficient. + * @rg: red green coefficient. + * @gb: green blue coefficient. + * @rb: red blue coefficient. + * @rgb: red blue green coefficient. + */ + +struct drm_msm_pcc_coeff { + __u32 c; + __u32 r; + __u32 g; + __u32 b; + __u32 rg; + __u32 gb; + __u32 rb; + __u32 rgb; +}; + +/** + * struct drm_msm_pcc - pcc feature structure + * flags: for customizing operations + * r: red coefficients. + * g: green coefficients. + * b: blue coefficients. + */ + +struct drm_msm_pcc { + __u64 flags; + struct drm_msm_pcc_coeff r; + struct drm_msm_pcc_coeff g; + struct drm_msm_pcc_coeff b; +}; + +/* struct drm_msm_pa_vlut - picture adjustment vLUT structure + * flags: for customizing vlut operation + * val: vLUT values + */ +#define PA_VLUT_SIZE 256 +struct drm_msm_pa_vlut { + __u64 flags; + __u32 val[PA_VLUT_SIZE]; +}; + +#define PA_HSIC_HUE_ENABLE (1 << 0) +#define PA_HSIC_SAT_ENABLE (1 << 1) +#define PA_HSIC_VAL_ENABLE (1 << 2) +#define PA_HSIC_CONT_ENABLE (1 << 3) +#define PA_HSIC_LEFT_DISPLAY_ONLY (1 << 4) +#define PA_HSIC_RIGHT_DISPLAY_ONLY (1 << 5) +/** + * struct drm_msm_pa_hsic - pa hsic feature structure + * @flags: flags for the feature customization, values can be: + * - PA_HSIC_HUE_ENABLE: Enable hue adjustment + * - PA_HSIC_SAT_ENABLE: Enable saturation adjustment + * - PA_HSIC_VAL_ENABLE: Enable value adjustment + * - PA_HSIC_CONT_ENABLE: Enable contrast adjustment + * + * @hue: hue setting + * @saturation: saturation setting + * @value: value setting + * @contrast: contrast setting + */ +#define DRM_MSM_PA_HSIC +struct drm_msm_pa_hsic { + __u64 flags; + __u32 hue; + __u32 saturation; + __u32 value; + __u32 contrast; +}; + +/* struct drm_msm_memcol - Memory color feature strucuture. + * Skin, sky, foliage features are supported. + * @prot_flags: Bit mask for enabling protection feature. + * @color_adjust_p0: Adjustment curve. + * @color_adjust_p1: Adjustment curve. + * @color_adjust_p2: Adjustment curve. + * @blend_gain: Blend gain weightage from othe PA features. + * @sat_hold: Saturation hold value. + * @val_hold: Value hold info. + * @hue_region: Hue qualifier. + * @sat_region: Saturation qualifier. + * @val_region: Value qualifier. + */ +#define DRM_MSM_MEMCOL +struct drm_msm_memcol { + __u64 prot_flags; + __u32 color_adjust_p0; + __u32 color_adjust_p1; + __u32 color_adjust_p2; + __u32 blend_gain; + __u32 sat_hold; + __u32 val_hold; + __u32 hue_region; + __u32 sat_region; + __u32 val_region; +}; + +#define GAMUT_3D_MODE_17 1 +#define GAMUT_3D_MODE_5 2 +#define GAMUT_3D_MODE_13 3 + +#define GAMUT_3D_MODE17_TBL_SZ 1229 +#define GAMUT_3D_MODE5_TBL_SZ 32 +#define GAMUT_3D_MODE13_TBL_SZ 550 +#define GAMUT_3D_SCALE_OFF_SZ 16 +#define GAMUT_3D_SCALEB_OFF_SZ 12 +#define GAMUT_3D_TBL_NUM 4 +#define GAMUT_3D_SCALE_OFF_TBL_NUM 3 +#define GAMUT_3D_MAP_EN (1 << 0) + +/** + * struct drm_msm_3d_col - 3d gamut color component structure + * @c0: Holds c0 value + * @c2_c1: Holds c2/c1 values + */ +struct drm_msm_3d_col { + __u32 c2_c1; + __u32 c0; +}; +/** + * struct drm_msm_3d_gamut - 3d gamut feature structure + * @flags: flags for the feature values are: + * 0 - no map + * GAMUT_3D_MAP_EN - enable map + * @mode: lut mode can take following values: + * - GAMUT_3D_MODE_17 + * - GAMUT_3D_MODE_5 + * - GAMUT_3D_MODE_13 + * @scale_off: Scale offset table + * @col: Color component tables + */ +struct drm_msm_3d_gamut { + __u64 flags; + __u32 mode; + __u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ]; + struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ]; +}; + +#define PGC_TBL_LEN 512 +#define PGC_8B_ROUND (1 << 0) +/** + * struct drm_msm_pgc_lut - pgc lut feature structure + * @flags: flags for the featue values can be: + * - PGC_8B_ROUND + * @c0: color0 component lut + * @c1: color1 component lut + * @c2: color2 component lut + */ +struct drm_msm_pgc_lut { + __u64 flags; + __u32 c0[PGC_TBL_LEN]; + __u32 c1[PGC_TBL_LEN]; + __u32 c2[PGC_TBL_LEN]; +}; + + +#define IGC_TBL_LEN 256 +#define IGC_DITHER_ENABLE (1 << 0) +/** + * struct drm_msm_igc_lut - igc lut feature structure + * @flags: flags for the feature customization, values can be: + * - IGC_DITHER_ENABLE: Enable dither functionality + * @c0: color0 component lut + * @c1: color1 component lut + * @c2: color2 component lut + * @strength: dither strength, considered valid when IGC_DITHER_ENABLE + * is set in flags. Strength value based on source bit width. + */ +struct drm_msm_igc_lut { + __u64 flags; + __u32 c0[IGC_TBL_LEN]; + __u32 c1[IGC_TBL_LEN]; + __u32 c2[IGC_TBL_LEN]; + __u32 strength; +}; + +#define HIST_V_SIZE 256 +/** + * struct drm_msm_hist - histogram feature structure + * @flags: for customizing operations + * @data: histogram data + */ +struct drm_msm_hist { + __u64 flags; + __u32 data[HIST_V_SIZE]; +}; + +#endif /* _MSM_DRM_PP_H_ */ diff --git a/include/uapi/drm/sde_drm.h b/include/uapi/drm/sde_drm.h new file mode 100644 index 000000000000..aee96735572a --- /dev/null +++ b/include/uapi/drm/sde_drm.h @@ -0,0 +1,351 @@ +#ifndef _SDE_DRM_H_ +#define _SDE_DRM_H_ + +/* Total number of supported color planes */ +#define SDE_MAX_PLANES 4 + +/* Total number of parameterized detail enhancer mapping curves */ +#define SDE_MAX_DE_CURVES 3 + + /* Y/RGB and UV filter configuration */ +#define FILTER_EDGE_DIRECTED_2D 0x0 +#define FILTER_CIRCULAR_2D 0x1 +#define FILTER_SEPARABLE_1D 0x2 +#define FILTER_BILINEAR 0x3 + +/* Alpha filters */ +#define FILTER_ALPHA_DROP_REPEAT 0x0 +#define FILTER_ALPHA_BILINEAR 0x1 +#define FILTER_ALPHA_2D 0x3 + +/* Blend filters */ +#define FILTER_BLEND_CIRCULAR_2D 0x0 +#define FILTER_BLEND_SEPARABLE_1D 0x1 + +/* LUT configuration flags */ +#define SCALER_LUT_SWAP 0x1 +#define SCALER_LUT_DIR_WR 0x2 +#define SCALER_LUT_Y_CIR_WR 0x4 +#define SCALER_LUT_UV_CIR_WR 0x8 +#define SCALER_LUT_Y_SEP_WR 0x10 +#define SCALER_LUT_UV_SEP_WR 0x20 + +/** + * Blend operations for "blend_op" property + * + * @SDE_DRM_BLEND_OP_NOT_DEFINED: No blend operation defined for the layer. + * @SDE_DRM_BLEND_OP_OPAQUE: Apply a constant blend operation. The layer + * would appear opaque in case fg plane alpha + * is 0xff. + * @SDE_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already + * has alpha pre-multiplication done. If the fg + * plane alpha is less than 0xff, apply + * modulation as well. This operation is + * intended on layers having alpha channel. + * @SDE_DRM_BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not + * alpha pre-multiplied. Apply + * pre-multiplication. If fg plane alpha is + * less than 0xff, apply modulation as well. + * @SDE_DRM_BLEND_OP_MAX: Used to track maximum blend operation + * possible by mdp. + */ +#define SDE_DRM_BLEND_OP_NOT_DEFINED 0 +#define SDE_DRM_BLEND_OP_OPAQUE 1 +#define SDE_DRM_BLEND_OP_PREMULTIPLIED 2 +#define SDE_DRM_BLEND_OP_COVERAGE 3 +#define SDE_DRM_BLEND_OP_MAX 4 + +/** + * Bit masks for "src_config" property + * construct bitmask via (1UL << SDE_DRM_<flag>) + */ +#define SDE_DRM_DEINTERLACE 0 /* Specifies interlaced input */ +#define SDE_DRM_LINEPADDING 1 /* Specifies line padding input */ + +/* DRM bitmasks are restricted to 0..63 */ +#define SDE_DRM_BITMASK_COUNT 64 + +/** + * Framebuffer modes for "fb_translation_mode" PLANE property + * + * @SDE_DRM_FB_NON_SEC: IOMMU configuration for this framebuffer mode + * is non-secure domain and requires + * both stage I and stage II translations when + * this buffer is accessed by the display HW. + * This is the default mode of all frambuffers. + * @SDE_DRM_FB_SEC: IOMMU configuration for this framebuffer mode + * is secure domain and requires + * both stage I and stage II translations when + * this buffer is accessed by the display HW. + * @SDE_DRM_FB_NON_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode + * is non-secure domain and requires + * only stage II translation when + * this buffer is accessed by the display HW. + * @SDE_DRM_FB_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode + * is secure domain and requires + * only stage II translation when + * this buffer is accessed by the display HW. +*/ + +#define SDE_DRM_FB_NON_SEC 0 +#define SDE_DRM_FB_SEC 1 +#define SDE_DRM_FB_NON_SEC_DIR_TRANS 2 +#define SDE_DRM_FB_SEC_DIR_TRANS 3 + +/** + * Secure levels for "security_level" CRTC property. + * CRTC property which specifies what plane types + * can be attached to this CRTC. Plane component + * derives the plane type based on the FB_MODE. + * @ SDE_DRM_SEC_NON_SEC: Both Secure and non-secure plane types can be + * attached to this CRTC. This is the default state of + * the CRTC. + * @ SDE_DRM_SEC_ONLY: Only secure planes can be added to this CRTC. If a + * CRTC is instructed to be in this mode it follows the + * platform dependent restrictions. + */ +#define SDE_DRM_SEC_NON_SEC 0 +#define SDE_DRM_SEC_ONLY 1 + +/** + * struct sde_drm_pix_ext_v1 - version 1 of pixel ext structure + * @num_ext_pxls_lr: Number of total horizontal pixels + * @num_ext_pxls_tb: Number of total vertical lines + * @left_ftch: Number of extra pixels to overfetch from left + * @right_ftch: Number of extra pixels to overfetch from right + * @top_ftch: Number of extra lines to overfetch from top + * @btm_ftch: Number of extra lines to overfetch from bottom + * @left_rpt: Number of extra pixels to repeat from left + * @right_rpt: Number of extra pixels to repeat from right + * @top_rpt: Number of extra lines to repeat from top + * @btm_rpt: Number of extra lines to repeat from bottom + */ +struct sde_drm_pix_ext_v1 { + /* + * Number of pixels ext in left, right, top and bottom direction + * for all color components. + */ + int32_t num_ext_pxls_lr[SDE_MAX_PLANES]; + int32_t num_ext_pxls_tb[SDE_MAX_PLANES]; + + /* + * Number of pixels needs to be overfetched in left, right, top + * and bottom directions from source image for scaling. + */ + int32_t left_ftch[SDE_MAX_PLANES]; + int32_t right_ftch[SDE_MAX_PLANES]; + int32_t top_ftch[SDE_MAX_PLANES]; + int32_t btm_ftch[SDE_MAX_PLANES]; + /* + * Number of pixels needs to be repeated in left, right, top and + * bottom directions for scaling. + */ + int32_t left_rpt[SDE_MAX_PLANES]; + int32_t right_rpt[SDE_MAX_PLANES]; + int32_t top_rpt[SDE_MAX_PLANES]; + int32_t btm_rpt[SDE_MAX_PLANES]; + +}; + +/** + * struct sde_drm_scaler_v1 - version 1 of struct sde_drm_scaler + * @lr: Pixel extension settings for left/right + * @tb: Pixel extension settings for top/botton + * @init_phase_x: Initial scaler phase values for x + * @phase_step_x: Phase step values for x + * @init_phase_y: Initial scaler phase values for y + * @phase_step_y: Phase step values for y + * @horz_filter: Horizontal filter array + * @vert_filter: Vertical filter array + */ +struct sde_drm_scaler_v1 { + /* + * Pix ext settings + */ + struct sde_drm_pix_ext_v1 pe; + /* + * Phase settings + */ + int32_t init_phase_x[SDE_MAX_PLANES]; + int32_t phase_step_x[SDE_MAX_PLANES]; + int32_t init_phase_y[SDE_MAX_PLANES]; + int32_t phase_step_y[SDE_MAX_PLANES]; + + /* + * Filter type to be used for scaling in horizontal and vertical + * directions + */ + uint32_t horz_filter[SDE_MAX_PLANES]; + uint32_t vert_filter[SDE_MAX_PLANES]; +}; + +/** + * struct sde_drm_de_v1 - version 1 of detail enhancer structure + * @enable: Enables/disables detail enhancer + * @sharpen_level1: Sharpening strength for noise + * @sharpen_level2: Sharpening strength for context + * @clip: Clip coefficient + * @limit: Detail enhancer limit factor + * @thr_quiet: Quite zone threshold + * @thr_dieout: Die-out zone threshold + * @thr_low: Linear zone left threshold + * @thr_high: Linear zone right threshold + * @prec_shift: Detail enhancer precision + * @adjust_a: Mapping curves A coefficients + * @adjust_b: Mapping curves B coefficients + * @adjust_c: Mapping curves C coefficients + */ +struct sde_drm_de_v1 { + uint32_t enable; + int16_t sharpen_level1; + int16_t sharpen_level2; + uint16_t clip; + uint16_t limit; + uint16_t thr_quiet; + uint16_t thr_dieout; + uint16_t thr_low; + uint16_t thr_high; + uint16_t prec_shift; + int16_t adjust_a[SDE_MAX_DE_CURVES]; + int16_t adjust_b[SDE_MAX_DE_CURVES]; + int16_t adjust_c[SDE_MAX_DE_CURVES]; +}; + +/** + * struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler + * @enable: Scaler enable + * @dir_en: Detail enhancer enable + * @pe: Pixel extension settings + * @horz_decimate: Horizontal decimation factor + * @vert_decimate: Vertical decimation factor + * @init_phase_x: Initial scaler phase values for x + * @phase_step_x: Phase step values for x + * @init_phase_y: Initial scaler phase values for y + * @phase_step_y: Phase step values for y + * @preload_x: Horizontal preload value + * @preload_y: Vertical preload value + * @src_width: Source width + * @src_height: Source height + * @dst_width: Destination width + * @dst_height: Destination height + * @y_rgb_filter_cfg: Y/RGB plane filter configuration + * @uv_filter_cfg: UV plane filter configuration + * @alpha_filter_cfg: Alpha filter configuration + * @blend_cfg: Selection of blend coefficients + * @lut_flag: LUT configuration flags + * @dir_lut_idx: 2d 4x4 LUT index + * @y_rgb_cir_lut_idx: Y/RGB circular LUT index + * @uv_cir_lut_idx: UV circular LUT index + * @y_rgb_sep_lut_idx: Y/RGB separable LUT index + * @uv_sep_lut_idx: UV separable LUT index + * @de: Detail enhancer settings +*/ +struct sde_drm_scaler_v2 { + /* + * General definitions + */ + uint32_t enable; + uint32_t dir_en; + + /* + * Pix ext settings + */ + struct sde_drm_pix_ext_v1 pe; + + /* + * Decimation settings + */ + uint32_t horz_decimate; + uint32_t vert_decimate; + + /* + * Phase settings + */ + int32_t init_phase_x[SDE_MAX_PLANES]; + int32_t phase_step_x[SDE_MAX_PLANES]; + int32_t init_phase_y[SDE_MAX_PLANES]; + int32_t phase_step_y[SDE_MAX_PLANES]; + + uint32_t preload_x[SDE_MAX_PLANES]; + uint32_t preload_y[SDE_MAX_PLANES]; + uint32_t src_width[SDE_MAX_PLANES]; + uint32_t src_height[SDE_MAX_PLANES]; + + uint32_t dst_width; + uint32_t dst_height; + + uint32_t y_rgb_filter_cfg; + uint32_t uv_filter_cfg; + uint32_t alpha_filter_cfg; + uint32_t blend_cfg; + + uint32_t lut_flag; + uint32_t dir_lut_idx; + + /* for Y(RGB) and UV planes*/ + uint32_t y_rgb_cir_lut_idx; + uint32_t uv_cir_lut_idx; + uint32_t y_rgb_sep_lut_idx; + uint32_t uv_sep_lut_idx; + + /* + * Detail enhancer settings + */ + struct sde_drm_de_v1 de; +}; + + +/* + * Define constants for struct sde_drm_csc + */ +#define SDE_CSC_MATRIX_COEFF_SIZE 9 +#define SDE_CSC_CLAMP_SIZE 6 +#define SDE_CSC_BIAS_SIZE 3 + +/** + * struct sde_drm_csc_v1 - version 1 of struct sde_drm_csc + * @ctm_coeff: Matrix coefficients, in S31.32 format + * @pre_bias: Pre-bias array values + * @post_bias: Post-bias array values + * @pre_clamp: Pre-clamp array values + * @post_clamp: Post-clamp array values + */ +struct sde_drm_csc_v1 { + int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE]; + uint32_t pre_bias[SDE_CSC_BIAS_SIZE]; + uint32_t post_bias[SDE_CSC_BIAS_SIZE]; + uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE]; + uint32_t post_clamp[SDE_CSC_CLAMP_SIZE]; +}; + +/* Writeback Config version definition */ +#define SDE_DRM_WB_CFG 0x1 + +/* SDE_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */ +#define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1<<0) + +/** + * struct sde_drm_wb_cfg - Writeback configuration structure + * @flags: see DRM_MSM_WB_CONFIG_FLAGS + * @connector_id: writeback connector identifier + * @count_modes: Count of modes in modes_ptr + * @modes: Pointer to struct drm_mode_modeinfo + */ +struct sde_drm_wb_cfg { + uint32_t flags; + uint32_t connector_id; + uint32_t count_modes; + uint64_t modes; +}; + +/** + * Define extended power modes supported by the SDE connectors. + */ +#define SDE_MODE_DPMS_ON 0 +#define SDE_MODE_DPMS_LP1 1 +#define SDE_MODE_DPMS_LP2 2 +#define SDE_MODE_DPMS_STANDBY 3 +#define SDE_MODE_DPMS_SUSPEND 4 +#define SDE_MODE_DPMS_OFF 5 + +#endif /* _SDE_DRM_H_ */ |