diff options
Diffstat (limited to 'include/dt-bindings')
20 files changed, 4374 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/audio-ext-clk.h b/include/dt-bindings/clock/audio-ext-clk.h new file mode 100644 index 000000000000..6fe8a466cf0e --- /dev/null +++ b/include/dt-bindings/clock/audio-ext-clk.h @@ -0,0 +1,30 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AUDIO_EXT_CLK_H +#define __AUDIO_EXT_CLK_H + +/* Audio External Clocks */ +#define AUDIO_PMI_CLK 0 +#define AUDIO_PMIC_LNBB_CLK 0 +#define AUDIO_AP_CLK 1 +#define AUDIO_AP_CLK2 2 +#define AUDIO_LPASS_MCLK 3 +#define AUDIO_LPASS_MCLK2 4 + +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 +#define clk_audio_lpass_mclk 0xf0f2a284 +#define clk_audio_pmi_lnbb_clk 0x57312343 + +#endif diff --git a/include/dt-bindings/clock/mdss-pll-clk.h b/include/dt-bindings/clock/mdss-pll-clk.h new file mode 100644 index 000000000000..9015b4c0e1c9 --- /dev/null +++ b/include/dt-bindings/clock/mdss-pll-clk.h @@ -0,0 +1,49 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MDSS_PLL_CLK_H +#define __MDSS_PLL_CLK_H + +/* DSI PLL clocks */ +#define BYTE0_MUX_CLK 0 +#define BYTE0_SRC_CLK 1 +#define PIX0_MUX_CLK 2 +#define PIX0_SRC_CLK 3 +#define N2_DIV_0_CLK 4 +#define POST_N1_DIV_0_CLK 5 +#define VCO_CLK_0_CLK 6 +#define SHADOW_BYTE0_SRC_CLK 7 +#define SHADOW_PIX0_SRC_CLK 8 +#define SHADOW_N2_DIV_0_CLK 9 +#define SHADOW_POST_N1_DIV_0_CLK 10 +#define SHADOW_VCO_CLK_0_CLK 11 +#define BYTE1_MUX_CLK 12 +#define BYTE1_SRC_CLK 13 +#define PIX1_MUX_CLK 14 +#define PIX1_SRC_CLK 15 +#define N2_DIV_1_CLK 16 +#define POST_N1_DIV_1_CLK 17 +#define VCO_CLK_1_CLK 18 +#define SHADOW_BYTE1_SRC_CLK 19 +#define SHADOW_PIX1_SRC_CLK 20 +#define SHADOW_N2_DIV_1_CLK 21 +#define SHADOW_POST_N1_DIV_1_CLK 22 +#define SHADOW_VCO_CLK_1_CLK 23 + +/* DP PLL clocks */ +#define DP_VCO_CLK 0 +#define DP_LINK_2X_CLK_DIVSEL_FIVE 1 +#define DP_VCO_DIVSEL_FOUR_CLK_SRC 2 +#define DP_VCO_DIVSEL_TWO_CLK_SRC 3 +#define DP_VCO_DIVIDED_CLK_SRC_MUX 4 + +#endif diff --git a/include/dt-bindings/clock/msm-clocks-8996.h b/include/dt-bindings/clock/msm-clocks-8996.h new file mode 100644 index 000000000000..da794841d1eb --- /dev/null +++ b/include/dt-bindings/clock/msm-clocks-8996.h @@ -0,0 +1,574 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8996_H +#define __MSM_CLOCKS_8996_H + +#include "audio-ext-clk.h" + +/* clock_gcc controlled clocks */ +#define clk_cxo_clk_src 0x79e95308 +#define clk_pnoc_clk 0x4325d220 +#define clk_pnoc_a_clk 0x2808c12b +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_bb_clk1 0xf5304268 +#define clk_bb_clk1_ao 0xfa113810 +#define clk_bb_clk1_pin 0x6dd0a779 +#define clk_bb_clk1_pin_ao 0x9b637772 +#define clk_bb_clk2 0xfe15cb87 +#define clk_bb_clk2_ao 0x59682706 +#define clk_bb_clk2_pin 0x498938e5 +#define clk_bb_clk2_pin_ao 0x52513787 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_a_clk 0xeeec2919 +#define clk_ipa_clk 0xfa685cda +#define clk_ln_bb_clk 0x3ab0b36d +#define clk_ln_bb_a_clk 0xc7257ea8 +#define clk_ln_bb_clk_pin 0x1b1c476a +#define clk_ln_bb_a_clk_pin 0x9cbb5411 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_pnoc_keepalive_a_clk 0xf8f91f0b +#define clk_pnoc_msmbus_clk 0x38b95c77 +#define clk_pnoc_msmbus_a_clk 0x8c9b4e93 +#define clk_pnoc_pm_clk 0xd6f7dfb9 +#define clk_pnoc_sps_clk 0xd482ecc7 +#define clk_qdss_a_clk 0xdd121669 +#define clk_qdss_clk 0x1492202a +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_ce1_clk 0x42229c55 +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_mmssnoc_axi_rpm_clk 0x4d7f8cdc +#define clk_mmssnoc_axi_rpm_a_clk 0xfbea899b +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_mmssnoc_gds_clk 0x06a22afa + +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_ao 0xa1368304 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_usb20_master_clk_src 0x5680ac83 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp1_uart4_apps_clk_src 0x56bff15c +#define clk_blsp1_uart5_apps_clk_src 0x218ef697 +#define clk_blsp1_uart6_apps_clk_src 0x8fbdbe4c +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_blsp2_uart4_apps_clk_src 0x23a093d2 +#define clk_blsp2_uart5_apps_clk_src 0xe067616a +#define clk_blsp2_uart6_apps_clk_src 0xe02d2829 +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc1_apps_clk_src 0xd4975db2 +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc3_apps_clk_src 0xea34c7f4 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_usb20_mock_utmi_clk_src 0xc3aaeecb +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_periph_noc_usb20_ahb_clk 0xfb9f26e9 +#define clk_gcc_mmss_gcc_dbg_clk 0xe89d461c +#define clk_cpu_dbg_clk 0x6550dfa9 +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp1_uart4_apps_clk 0x26be16c0 +#define clk_gcc_blsp1_uart5_apps_clk 0x28a6bc74 +#define clk_gcc_blsp1_uart6_apps_clk 0x28fd3466 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_blsp2_uart4_apps_clk 0x87a44b42 +#define clk_gcc_blsp2_uart5_apps_clk 0x5cd30649 +#define clk_gcc_blsp2_uart6_apps_clk 0x8feee5ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_phy_reset 0xdc3201c1 +#define clk_gcc_pcie_1_aux_clk 0xc9bb962c +#define clk_gcc_pcie_1_cfg_ahb_clk 0xb6338658 +#define clk_gcc_pcie_1_mstr_axi_clk 0xc20f6269 +#define clk_gcc_pcie_1_slv_axi_clk 0xd54e40d6 +#define clk_gcc_pcie_1_pipe_clk 0xc1627422 +#define clk_gcc_pcie_1_phy_reset 0x674481bb +#define clk_gcc_pcie_2_aux_clk 0xa4dc7ae8 +#define clk_gcc_pcie_2_cfg_ahb_clk 0x4f1d3121 +#define clk_gcc_pcie_2_mstr_axi_clk 0x9e81724a +#define clk_gcc_pcie_2_slv_axi_clk 0x7990d8b2 +#define clk_gcc_pcie_2_pipe_clk 0xa757a834 +#define clk_gcc_pcie_2_phy_reset 0x82634880 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pcie_phy_cfg_ahb_clk 0x8533671a +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc1_ahb_clk 0x691e0caa +#define clk_gcc_sdcc1_apps_clk 0x9ad6fb96 +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc3_ahb_clk 0x565b2c03 +#define clk_gcc_sdcc3_apps_clk 0x0b27aeac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_rx_cfg_clk 0xa6747786 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_cfg_clk 0xba2cf8b5 +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_sys_clk_core_clk 0x360e5ac8 +#define clk_gcc_ufs_tx_symbol_clk_core_clk 0xf6fb0df7 +#define clk_gcc_usb20_master_clk 0x24c3b66a +#define clk_gcc_usb20_mock_utmi_clk 0xe8db8203 +#define clk_gcc_usb20_sleep_clk 0x6e8cb4b2 +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb_phy_cfg_ahb2phy_clk 0xd1231a0e +#define clk_gcc_aggre0_cnoc_ahb_clk 0x53a35559 +#define clk_gcc_aggre0_snoc_axi_clk 0x3c446400 +#define clk_gcc_aggre0_noc_qosgen_extref_clk 0x8c4356ba +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f01 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_usb2_clkref_clk 0x27ec24ba +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_smmu_aggre0_ahb_clk 0x47a06ce4 +#define clk_gcc_smmu_aggre0_axi_clk 0x3cac4a6c +#define clk_gcc_sys_noc_usb3_axi_clk 0x94d26800 +#define clk_gcc_sys_noc_ufs_axi_clk 0x19d38312 +#define clk_gcc_aggre2_usb3_axi_clk 0xd5822a8e +#define clk_gcc_aggre2_ufs_axi_clk 0xb31e5191 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_mmss_bimc_gfx_clk 0xe4f28754 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_qspi_ser_clk 0xfaf1e266 +#define clk_qspi_ser_clk_src 0x426676ee +#define clk_sdcc1_ice_core_clk_src 0xfd6a4301 +#define clk_gcc_sdcc1_ice_core_clk 0x0fd5680a +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_debug_mux_v2 0xf7e749f0 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_gcc_aggre0_noc_mpu_cfg_ahb_clk 0x5c1bb8e2 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmsscc_mmssnoc_ahb 0x7b4bd6f7 +#define clk_mmpll0 0xdd83b751 +#define clk_mmpll0_out_main 0x2f996a31 +#define clk_mmpll1 0x6da7fb90 +#define clk_mmpll1_out_main 0xa0d3a7da +#define clk_mmpll4 0x22c063c1 +#define clk_mmpll4_out_main 0xfb21c2fd +#define clk_mmpll3 0x18c76899 +#define clk_mmpll3_out_main 0x6eb6328f +#define clk_ahb_clk_src 0x86f49203 +#define clk_mmpll2 0x1190e4d8 +#define clk_mmpll2_out_main 0x1e9e24a8 +#define clk_mmpll8 0xd06ad45e +#define clk_mmpll8_out_main 0x75b1f386 +#define clk_mmpll9 0x1c50684c +#define clk_mmpll9_out_main 0x16b74937 +#define clk_mmpll5 0xa41e1936 +#define clk_mmpll5_out_main 0xcc1897bf +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_jpeg2_clk_src 0x5ad927f3 +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_video_core_clk_src 0x8be4c944 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_cci_clk_src 0x822f3d97 +#define clk_csiphy0_3p_clk_src 0xd2474b12 +#define clk_csiphy1_3p_clk_src 0x46a02aff +#define clk_csiphy2_3p_clk_src 0x1447813f +#define clk_camss_gp0_clk_src 0x6b57cfe6 +#define clk_camss_gp1_clk_src 0xf735368a +#define clk_jpeg_dma_clk_src 0xb68afcea +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_mmss_bto_ahb_clk 0xfdf8c361 +#define clk_camss_ahb_clk 0xc4ff91d4 +#define clk_camss_cci_ahb_clk 0x04c4441a +#define clk_camss_cci_clk 0xd6cb5eb9 +#define clk_camss_cpp_ahb_clk 0x12e9a87b +#define clk_camss_cpp_clk 0xb82f366b +#define clk_camss_cpp_axi_clk 0x5598c804 +#define clk_camss_cpp_vbif_ahb_clk 0xb5f31be4 +#define clk_camss_csi0_ahb_clk 0x6e29c972 +#define clk_camss_csi0_clk 0x30862ddb +#define clk_camss_csi0phy_clk 0x2cecfb84 +#define clk_camss_csi0pix_clk 0x6946f77b +#define clk_camss_csi0rdi_clk 0x83645ef5 +#define clk_camss_csi1_ahb_clk 0xccc15f06 +#define clk_camss_csi1_clk 0xb150f052 +#define clk_camss_csi1phy_clk 0xb989f06d +#define clk_camss_csi1pix_clk 0x58d19bf3 +#define clk_camss_csi1rdi_clk 0x4d2f3352 +#define clk_camss_csi2_ahb_clk 0x92d02d75 +#define clk_camss_csi2_clk 0x74fc92e8 +#define clk_camss_csi2phy_clk 0xda05d9d8 +#define clk_camss_csi2pix_clk 0xf8ed0731 +#define clk_camss_csi2rdi_clk 0xdc1b2081 +#define clk_camss_csi3_ahb_clk 0xee5e459c +#define clk_camss_csi3_clk 0x39488fdd +#define clk_camss_csi3phy_clk 0x8b6063b9 +#define clk_camss_csi3pix_clk 0xd82bd467 +#define clk_camss_csi3rdi_clk 0xb6750046 +#define clk_camss_csi_vfe0_clk 0x3023937a +#define clk_camss_csi_vfe1_clk 0xe66fa522 +#define clk_camss_csiphy0_3p_clk 0xf2a54f5a +#define clk_camss_csiphy1_3p_clk 0x8bf70cb2 +#define clk_camss_csiphy2_3p_clk 0x1c14c939 +#define clk_camss_gp0_clk 0xcee7e51d +#define clk_camss_gp1_clk 0x41f1c2e3 +#define clk_camss_ispif_ahb_clk 0x9a212c6d +#define clk_camss_jpeg0_clk 0x0b0e2db7 +#define clk_camss_jpeg2_clk 0xd7291c8d +#define clk_camss_jpeg_ahb_clk 0x1f47fd28 +#define clk_camss_jpeg_axi_clk 0x9e5545c8 +#define clk_camss_jpeg_dma_clk 0x2336e65d +#define clk_camss_mclk0_clk 0xcf0c61e0 +#define clk_camss_mclk1_clk 0xd1410ed4 +#define clk_camss_mclk2_clk 0x851286f2 +#define clk_camss_mclk3_clk 0x4db11c45 +#define clk_camss_micro_ahb_clk 0x33a23277 +#define clk_camss_csi0phytimer_clk 0xff93b3c8 +#define clk_camss_csi1phytimer_clk 0x6c399ab6 +#define clk_camss_csi2phytimer_clk 0x24f47f49 +#define clk_camss_top_ahb_clk 0x8f8b2d33 +#define clk_camss_vfe_ahb_clk 0x595197bc +#define clk_camss_vfe_axi_clk 0x273d4c31 +#define clk_camss_vfe0_ahb_clk 0x4652833c +#define clk_camss_vfe0_clk 0x1e9bb8c4 +#define clk_camss_vfe0_stream_clk 0x22835fa4 +#define clk_camss_vfe1_ahb_clk 0x6a56abd3 +#define clk_camss_vfe1_clk 0x5bffa69b +#define clk_camss_vfe1_stream_clk 0x92f849b9 +#define clk_fd_ahb_clk 0x868a2c5c +#define clk_fd_core_clk 0x3badcae4 +#define clk_fd_core_uar_clk 0x7e624e15 +#define clk_gpu_ahb_clk 0xf97f1d43 +#define clk_gpu_aon_isense_clk 0xa9e9b297 +#define clk_gpu_gx_gfx3d_clk 0xb7ece823 +#define clk_gpu_mx_clk 0xb80ccedf +#define clk_gpu_gx_rbbmtimer_clk 0xdeba634e +#define clk_mdss_ahb_clk 0x684ccb41 +#define clk_mdss_axi_clk 0xcc07d687 +#define clk_mdss_esc0_clk 0x28cafbe6 +#define clk_mdss_esc1_clk 0xc22c6883 +#define clk_mdss_hdmi_ahb_clk 0x01cef516 +#define clk_mdss_hdmi_clk 0x097a6de9 +#define clk_mdss_mdp_clk 0x618336ac +#define clk_mdss_vsync_clk 0x42a022d3 +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmagic_bimc_noc_cfg_ahb_clk 0x12d5ba72 +#define clk_mmagic_camss_axi_clk 0xa8b1c16b +#define clk_mmagic_camss_noc_cfg_ahb_clk 0x5182c819 +#define clk_mmss_mmagic_cfg_ahb_clk 0x5e94a822 +#define clk_mmagic_mdss_axi_clk 0xa0359d10 +#define clk_mmagic_mdss_noc_cfg_ahb_clk 0x9c6d5482 +#define clk_mmagic_video_axi_clk 0x7b9219c3 +#define clk_mmagic_video_noc_cfg_ahb_clk 0x5124d256 +#define clk_mmss_mmagic_ahb_clk 0x3d15f2b0 +#define clk_mmss_mmagic_maxi_clk 0xbdaf5af7 +#define clk_mmss_rbcpr_ahb_clk 0x623ba55f +#define clk_mmss_rbcpr_clk 0x69a23a6f +#define clk_mmss_spdm_cpp_clk 0xefe35cd2 +#define clk_mmss_spdm_jpeg_dma_clk 0xcb7bd5a0 +#define clk_smmu_cpp_ahb_clk 0x3ad82d84 +#define clk_smmu_cpp_axi_clk 0xa6bb2f4a +#define clk_smmu_jpeg_ahb_clk 0x10c436ec +#define clk_smmu_jpeg_axi_clk 0x41112f37 +#define clk_smmu_mdp_ahb_clk 0x04994cb2 +#define clk_smmu_mdp_axi_clk 0x7fd71687 +#define clk_smmu_rot_ahb_clk 0xa30772c9 +#define clk_smmu_rot_axi_clk 0xfed7c078 +#define clk_smmu_vfe_ahb_clk 0x4dabebe7 +#define clk_smmu_vfe_axi_clk 0xde483725 +#define clk_smmu_video_ahb_clk 0x2d738e2c +#define clk_smmu_video_axi_clk 0xe2b5b887 +#define clk_video_ahb_clk 0x90775cfb +#define clk_video_axi_clk 0xe6c16dba +#define clk_video_core_clk 0x7e876ec3 +#define clk_video_maxi_clk 0x97749db6 +#define clk_video_subcore0_clk 0xb6f63e6c +#define clk_video_subcore1_clk 0x26c29cb4 +#define clk_vmem_ahb_clk 0xab6223ff +#define clk_vmem_maxi_clk 0x15ef32db +#define clk_mmss_debug_mux 0xe646ffda +#define clk_mmss_gcc_dbg_clk 0xafa4d48a +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_mdss_byte0_clk 0xf5a03f64 +#define clk_mdss_byte1_clk 0xb8c7067d +#define clk_mdss_extpclk_clk 0xfa5aadb0 +#define clk_mdss_pclk0_clk 0x3487234a +#define clk_mdss_pclk1_clk 0xd5804246 +#define clk_gpu_gcc_dbg_clk 0x0ccc42cd +#define clk_mdss_mdp_vote_clk 0x588460a4 +#define clk_mdss_rotator_vote_clk 0x5b1f675e +#define clk_mmpll2_postdiv_clk 0x4fdeaaba +#define clk_mmpll8_postdiv_clk 0xedf57882 +#define clk_mmpll9_postdiv_clk 0x3064b618 +#define clk_gfx3d_clk_src_v2 0x4210acb7 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 + +/* clock_debug controlled clocks */ +#define clk_gcc_debug_mux 0x8121ac15 + +/* external multimedia clocks */ +#define clk_dsi0pll_pixel_clk_mux 0x792379e1 +#define clk_dsi0pll_byte_clk_mux 0x60e83f06 +#define clk_dsi0pll_byte_clk_src 0xbbaa30be +#define clk_dsi0pll_pixel_clk_src 0x45b3260f +#define clk_dsi0pll_n2_div_clk 0x1474c213 +#define clk_dsi0pll_post_n1_div_clk 0xdab8c389 +#define clk_dsi0pll_vco_clk 0x15940d40 +#define clk_dsi1pll_pixel_clk_mux 0x36458019 +#define clk_dsi1pll_byte_clk_mux 0xb5a42b7b +#define clk_dsi1pll_byte_clk_src 0x63930a8f +#define clk_dsi1pll_pixel_clk_src 0x0e4c9b56 +#define clk_dsi1pll_n2_div_clk 0x2c9d4007 +#define clk_dsi1pll_post_n1_div_clk 0x03020041 +#define clk_dsi1pll_vco_clk 0x99797b50 +#define clk_mdss_dsi1_vco_clk_src 0xfcd15658 +#define clk_hdmi_vco_clk 0x66003284 + +#define clk_dsi0pll_shadow_byte_clk_src 0x177c029c +#define clk_dsi0pll_shadow_pixel_clk_src 0x98ae3c92 +#define clk_dsi0pll_shadow_n2_div_clk 0xd5f0dad9 +#define clk_dsi0pll_shadow_post_n1_div_clk 0x1f7c8cf8 +#define clk_dsi0pll_shadow_vco_clk 0xb100ca83 +#define clk_dsi1pll_shadow_byte_clk_src 0xfc021ce5 +#define clk_dsi1pll_shadow_pixel_clk_src 0xdcca3ffc +#define clk_dsi1pll_shadow_n2_div_clk 0x189541bf +#define clk_dsi1pll_shadow_post_n1_div_clk 0x1637020e +#define clk_dsi1pll_shadow_vco_clk 0x68d8b6f7 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_pwrcl_pll 0x25454ca1 +#define clk_pwrcl_alt_pll 0xc445471b +#define clk_pwrcl_pll_main 0x28948e22 +#define clk_pwrcl_alt_pll_main 0x25c8270e +#define clk_pwrcl_hf_mux 0x77706ae6 +#define clk_pwrcl_lf_mux 0xd99e334d +#define clk_perfcl_clk 0x58869997 +#define clk_perfcl_pll 0x97dcec1c +#define clk_perfcl_alt_pll 0xfe2eaea1 +#define clk_perfcl_pll_main 0x0dbf0c0b +#define clk_perfcl_alt_pll_main 0x0b892aab +#define clk_perfcl_hf_mux 0x9e8bbe59 +#define clk_perfcl_lf_mux 0x2f9c278d +#define clk_cbf_pll 0xfe2e96a3 +#define clk_cbf_pll_main 0x2b05cf95 +#define clk_cbf_hf_mux 0x71244f73 +#define clk_cbf_clk 0x48e9e16b +#define clk_xo_ao 0x428c856d +#define clk_sys_apcsaux_clk 0x0b0dd513 +#define clk_cpu_debug_mux 0xc7acaa31 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_20_BCR 7 +#define USB_30_BCR 8 +#define USB3_PHY_BCR 9 +#define USB3PHY_PHY_BCR 10 +#define PCIE_0_PHY_BCR 11 +#define PCIE_1_PHY_BCR 12 +#define PCIE_2_PHY_BCR 13 +#define PCIE_PHY_BCR 14 +#define PCIE_PHY_COM_BCR 15 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 16 + +/* MMSS Block resets */ +#define VIDEO_BCR 0 +#define MDSS_BCR 1 +#define CAMSS_MICRO_BCR 2 +#define CAMSS_JPEG_BCR 3 +#define CAMSS_VFE0_BCR 4 +#define CAMSS_VFE1_BCR 5 +#define FD_BCR 6 +#define GPU_GX_BCR 7 + +#endif diff --git a/include/dt-bindings/clock/msm-clocks-8998.h b/include/dt-bindings/clock/msm-clocks-8998.h new file mode 100644 index 000000000000..67e47c46e09a --- /dev/null +++ b/include/dt-bindings/clock/msm-clocks-8998.h @@ -0,0 +1,534 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_CLOCKS_8998_H +#define __MSM_CLOCKS_8998_H + +#include "audio-ext-clk.h" + +/* clock_rpm controlled clocks */ +#define clk_ce1_clk 0x42229c55 +#define clk_ce1_a_clk 0x44a833fe +#define clk_cxo_clk_src 0x79e95308 +#define clk_bimc_clk 0x4b80bf00 +#define clk_bimc_a_clk 0x4b25668a +#define clk_cnoc_clk 0xd5ccb7f4 +#define clk_cnoc_a_clk 0xd8fe2ccc +#define clk_snoc_clk 0x2c341aa0 +#define clk_snoc_a_clk 0x8fcef2af +#define clk_cnoc_periph_clk 0xb11e9cf9 +#define clk_cnoc_periph_a_clk 0x1d7faa2e +#define clk_cnoc_periph_keepalive_a_clk 0x7287aef2 +#define clk_ln_bb_clk1 0xb867b147 +#define clk_ln_bb_clk1_ao 0x7f63a93a +#define clk_ln_bb_clk1_pin 0x6fc5653c +#define clk_ln_bb_clk1_pin_ao 0x25d625bf +#define clk_ln_bb_clk2 0xf83e6387 +#define clk_ln_bb_clk2_ao 0x96f09628 +#define clk_ln_bb_clk2_pin 0xa9ebe8d5 +#define clk_ln_bb_clk2_pin_ao 0x89a1226f +#define clk_ln_bb_clk3 0x4f52a39e +#define clk_ln_bb_clk3_ao 0xb15eba76 +#define clk_ln_bb_clk3_pin 0xc4de7dad +#define clk_ln_bb_clk3_pin_ao 0xc01022e8 +#define clk_bimc_msmbus_clk 0xd212feea +#define clk_bimc_msmbus_a_clk 0x71d1a499 +#define clk_cnoc_msmbus_clk 0x62228b5d +#define clk_cnoc_msmbus_a_clk 0x67442955 +#define clk_cxo_clk_src_ao 0x64eb6004 +#define clk_cxo_dwc3_clk 0xf79c19f6 +#define clk_cxo_lpm_clk 0x94adbf3d +#define clk_cxo_otg_clk 0x4eec0bb9 +#define clk_cxo_pil_lpass_clk 0xe17f0ff6 +#define clk_cxo_pil_ssc_clk 0x81832015 +#define clk_cxo_pil_spss_clk 0x5cd71a61 +#define clk_div_clk1 0xaa1157a6 +#define clk_div_clk1_ao 0x6b943d68 +#define clk_div_clk2 0xd454019f +#define clk_div_clk2_ao 0x53f9e788 +#define clk_div_clk3 0xa9a55a68 +#define clk_div_clk3_ao 0x3d6725a8 +#define clk_ipa_clk 0xfa685cda +#define clk_ipa_a_clk 0xeeec2919 +#define clk_mcd_ce1_clk 0xbb615d26 +#define clk_mmssnoc_axi_clk 0xdb4b31e6 +#define clk_mmssnoc_axi_a_clk 0xd4970614 +#define clk_qcedev_ce1_clk 0x293f97b0 +#define clk_qcrypto_ce1_clk 0xa6ac14df +#define clk_qdss_clk 0x1492202a +#define clk_qdss_a_clk 0xdd121669 +#define clk_qseecom_ce1_clk 0xaa858373 +#define clk_rf_clk1 0xaabeea5a +#define clk_rf_clk1_ao 0x72a10cb8 +#define clk_rf_clk1_pin 0x8f463562 +#define clk_rf_clk1_pin_ao 0x62549ff6 +#define clk_rf_clk2 0x24a30992 +#define clk_rf_clk2_ao 0x944d8bbd +#define clk_rf_clk2_pin 0xa7c5602a +#define clk_rf_clk2_pin_ao 0x2d75eb4d +#define clk_rf_clk3 0xb673936b +#define clk_rf_clk3_ao 0x038bb968 +#define clk_rf_clk3_pin 0x726f53f5 +#define clk_rf_clk3_pin_ao 0x76f9240f +#define clk_scm_ce1_clk 0xd8ebcc62 +#define clk_snoc_msmbus_clk 0xe6900bb6 +#define clk_snoc_msmbus_a_clk 0x5d4683bd +#define clk_gcc_ce1_ahb_m_clk 0x2eb28c01 +#define clk_gcc_ce1_axi_m_clk 0xc174dfba +#define clk_aggre1_noc_clk 0x049abba8 +#define clk_aggre1_noc_a_clk 0xc12e4220 +#define clk_aggre2_noc_clk 0xaa681404 +#define clk_aggre2_noc_a_clk 0xcab67089 +#define clk_measure_only_bimc_hmss_axi_clk 0xc1cc4f11 + +/* clock_gcc controlled clocks*/ +#define clk_debug_mmss_clk 0x977c99b6 +#define clk_debug_rpm_clk 0x8e2b07ca +#define clk_debug_cpu_clk 0x0e696b2b +#define clk_gpu_gcc_debug_clk 0x3eb88190 +#define clk_gfx_gcc_debug_clk 0xa3a64fec +#define clk_gpll0 0x1ebe3bc4 +#define clk_gpll0_out_main 0xe9374de7 +#define clk_gpll0_ao 0xa1368304 +#define clk_gcc_mmss_gpll0_clk 0x8050f008 +#define clk_gcc_mmss_gpll0_div_clk 0xdd06848d +#define clk_gcc_gpu_gpll0_clk 0xdad7a7a4 +#define clk_gcc_gpu_gpll0_div_clk 0x07d16c6a +#define clk_gpll4 0xb3b5d85b +#define clk_gpll4_out_main 0xa9a0ab9d +#define clk_usb30_master_clk_src 0xc6262f89 +#define clk_pcie_aux_clk_src 0xebc50566 +#define clk_ufs_axi_clk_src 0x297ca380 +#define clk_blsp1_qup1_i2c_apps_clk_src 0x17f78f5e +#define clk_blsp1_qup1_spi_apps_clk_src 0xf534c4fa +#define clk_blsp1_qup2_i2c_apps_clk_src 0x8de71c79 +#define clk_blsp1_qup2_spi_apps_clk_src 0x33cf809a +#define clk_blsp1_qup3_i2c_apps_clk_src 0xf161b902 +#define clk_blsp1_qup3_spi_apps_clk_src 0x5e95683f +#define clk_blsp1_qup4_i2c_apps_clk_src 0xb2ecce68 +#define clk_blsp1_qup4_spi_apps_clk_src 0xddb5bbdb +#define clk_blsp1_qup5_i2c_apps_clk_src 0x71ea7804 +#define clk_blsp1_qup5_spi_apps_clk_src 0x9752f35f +#define clk_blsp1_qup6_i2c_apps_clk_src 0x28806803 +#define clk_blsp1_qup6_spi_apps_clk_src 0x44a1edc4 +#define clk_blsp1_uart1_apps_clk_src 0xf8146114 +#define clk_blsp1_uart2_apps_clk_src 0xfc9c2f73 +#define clk_blsp1_uart3_apps_clk_src 0x600497f2 +#define clk_blsp2_qup1_i2c_apps_clk_src 0xd6d1e95d +#define clk_blsp2_qup1_spi_apps_clk_src 0xcc1b8365 +#define clk_blsp2_qup2_i2c_apps_clk_src 0x603b5c51 +#define clk_blsp2_qup2_spi_apps_clk_src 0xd577dc44 +#define clk_blsp2_qup3_i2c_apps_clk_src 0xea82959c +#define clk_blsp2_qup3_spi_apps_clk_src 0xd04b1e92 +#define clk_blsp2_qup4_i2c_apps_clk_src 0x73dc968c +#define clk_blsp2_qup4_spi_apps_clk_src 0x25d4a2b1 +#define clk_blsp2_qup5_i2c_apps_clk_src 0xcc3698bd +#define clk_blsp2_qup5_spi_apps_clk_src 0xfa0cf45e +#define clk_blsp2_qup6_i2c_apps_clk_src 0x2fa53151 +#define clk_blsp2_qup6_spi_apps_clk_src 0x5ca86755 +#define clk_blsp2_uart1_apps_clk_src 0x562c66dc +#define clk_blsp2_uart2_apps_clk_src 0xdd448080 +#define clk_blsp2_uart3_apps_clk_src 0x46b2e90f +#define clk_gp1_clk_src 0xad85b97a +#define clk_gp2_clk_src 0xfb1f0065 +#define clk_gp3_clk_src 0x63b693d6 +#define clk_hmss_rbcpr_clk_src 0xedd9a474 +#define clk_pdm2_clk_src 0x31e494fd +#define clk_sdcc2_apps_clk_src 0xfc46c821 +#define clk_sdcc4_apps_clk_src 0x7aaaaa0c +#define clk_tsif_ref_clk_src 0x4e9042d1 +#define clk_ufs_ice_core_clk_src 0xda8e7119 +#define clk_ufs_phy_aux_clk_src 0xc6bca085 +#define clk_ufs_unipro_core_clk_src 0x179e80a9 +#define clk_usb30_mock_utmi_clk_src 0xa024a976 +#define clk_usb3_phy_aux_clk_src 0x15eec63c +#define clk_qspi_ref_clk_src 0xfe6b8e11 +#define clk_gcc_pcie_phy_0_reset 0x6bb4df33 +#define clk_gcc_usb3_phy_reset 0x03d559f1 +#define clk_gcc_usb3phy_phy_reset 0xb1a4f885 +#define clk_gcc_aggre1_ufs_axi_clk 0x873459d8 +#define clk_gcc_aggre1_ufs_axi_hw_ctl_clk 0x117a6f39 +#define clk_gcc_aggre1_usb3_axi_clk 0xc5c3fbe8 +#define clk_gcc_bimc_mss_q6_axi_clk 0x7437988f +#define clk_gcc_blsp1_ahb_clk 0x8caa5b4f +#define clk_gcc_blsp1_qup1_i2c_apps_clk 0xc303fae9 +#define clk_gcc_blsp1_qup1_spi_apps_clk 0x759a76b0 +#define clk_gcc_blsp1_qup2_i2c_apps_clk 0x1076f220 +#define clk_gcc_blsp1_qup2_spi_apps_clk 0x3e77d48f +#define clk_gcc_blsp1_qup3_i2c_apps_clk 0x9e25ac82 +#define clk_gcc_blsp1_qup3_spi_apps_clk 0xfb978880 +#define clk_gcc_blsp1_qup4_i2c_apps_clk 0xd7f40f6f +#define clk_gcc_blsp1_qup4_spi_apps_clk 0x80f8722f +#define clk_gcc_blsp1_qup5_i2c_apps_clk 0xacae5604 +#define clk_gcc_blsp1_qup5_spi_apps_clk 0xbf3e15d7 +#define clk_gcc_blsp1_qup6_i2c_apps_clk 0x5c6ad820 +#define clk_gcc_blsp1_qup6_spi_apps_clk 0x780d9f85 +#define clk_gcc_blsp1_uart1_apps_clk 0xc7c62f90 +#define clk_gcc_blsp1_uart2_apps_clk 0xf8a61c96 +#define clk_gcc_blsp1_uart3_apps_clk 0xc3298bd7 +#define clk_gcc_blsp2_ahb_clk 0x8f283c1d +#define clk_gcc_blsp2_qup1_i2c_apps_clk 0x9ace11dd +#define clk_gcc_blsp2_qup1_spi_apps_clk 0xa32604cc +#define clk_gcc_blsp2_qup2_i2c_apps_clk 0x1bf9a57e +#define clk_gcc_blsp2_qup2_spi_apps_clk 0xbf54ca6d +#define clk_gcc_blsp2_qup3_i2c_apps_clk 0x336d4170 +#define clk_gcc_blsp2_qup3_spi_apps_clk 0xc68509d6 +#define clk_gcc_blsp2_qup4_i2c_apps_clk 0xbd22539d +#define clk_gcc_blsp2_qup4_spi_apps_clk 0x01a72b93 +#define clk_gcc_blsp2_qup5_i2c_apps_clk 0xe2b2ce1d +#define clk_gcc_blsp2_qup5_spi_apps_clk 0xf40999cd +#define clk_gcc_blsp2_qup6_i2c_apps_clk 0x894bcea4 +#define clk_gcc_blsp2_qup6_spi_apps_clk 0xfe1bd34a +#define clk_gcc_blsp2_uart1_apps_clk 0x8c3512ff +#define clk_gcc_blsp2_uart2_apps_clk 0x1e1965a3 +#define clk_gcc_blsp2_uart3_apps_clk 0x382415ab +#define clk_gcc_boot_rom_ahb_clk 0xde2adeb1 +#define clk_gcc_bimc_gfx_clk 0x3edd69ad +#define clk_gcc_cfg_noc_usb3_axi_clk 0x9ea4c2d9 +#define clk_gcc_gp1_clk 0x057f7b69 +#define clk_gcc_gp2_clk 0x9bf83ffd +#define clk_gcc_gp3_clk 0xec6539ee +#define clk_gcc_gpu_bimc_gfx_clk 0x3909459b +#define clk_gcc_gpu_cfg_ahb_clk 0x72f20a57 +#define clk_gcc_gpu_iref_clk 0xfd82abad +#define clk_gcc_hmss_dvm_bus_clk 0x17cc8b53 +#define clk_gcc_hmss_rbcpr_clk 0x699183be +#define clk_hmss_gpll0_clk_src 0x17eb05d0 +#define clk_hmss_gpll4_clk_src 0x20456cae +#define clk_gcc_mmss_sys_noc_axi_clk 0x4467b15b +#define clk_gcc_mss_at_clk 0x1692c5aa +#define clk_nav_gcc_dbg_clk 0x2221c544 +#define clk_gcc_pcie_0_aux_clk 0x3d2e3ece +#define clk_gcc_pcie_0_cfg_ahb_clk 0x4dd325c3 +#define clk_gcc_pcie_0_mstr_axi_clk 0x3f85285b +#define clk_gcc_pcie_0_pipe_clk 0x4f37621e +#define clk_gcc_pcie_0_slv_axi_clk 0xd69638a1 +#define clk_gcc_pcie_phy_aux_clk 0x4746e74f +#define clk_gcc_pdm2_clk 0x99d55711 +#define clk_gcc_pdm_ahb_clk 0x365664f6 +#define clk_gcc_prng_ahb_clk 0x397e7eaa +#define clk_gcc_sdcc2_ahb_clk 0x23d5727f +#define clk_gcc_sdcc2_apps_clk 0x861b20ac +#define clk_gcc_sdcc4_ahb_clk 0x64f3e6a8 +#define clk_gcc_sdcc4_apps_clk 0xbf7c4dc8 +#define clk_gcc_tsif_ahb_clk 0x88d2822c +#define clk_gcc_tsif_ref_clk 0x8f1ed2c2 +#define clk_gcc_ufs_ahb_clk 0x1914bb84 +#define clk_gcc_ufs_axi_clk 0x47c743a7 +#define clk_gcc_ufs_axi_hw_ctl_clk 0x69385b45 +#define clk_gcc_ufs_ice_core_clk 0x310b0710 +#define clk_gcc_ufs_ice_core_hw_ctl_clk 0x84e15a5b +#define clk_gcc_ufs_phy_aux_clk 0x17acc8fb +#define clk_gcc_ufs_phy_aux_hw_ctl_clk 0x7dbdb2e2 +#define clk_gcc_ufs_rx_symbol_0_clk 0x7f43251c +#define clk_gcc_ufs_rx_symbol_1_clk 0x03182fde +#define clk_gcc_ufs_tx_symbol_0_clk 0x6a9f747a +#define clk_ufs_tx_symbol_0_clk 0xb3fcd0f7 +#define clk_ufs_rx_symbol_0_clk 0x17a0f1cd +#define clk_gcc_ufs_unipro_core_clk 0x2daf7fd2 +#define clk_gcc_ufs_unipro_core_hw_ctl_clk 0x4a4e0f3d +#define clk_gcc_usb30_master_clk 0xb3b4e2cb +#define clk_gcc_usb30_mock_utmi_clk 0xa800b65a +#define clk_gcc_usb30_sleep_clk 0xd0b65c92 +#define clk_gcc_usb3_phy_aux_clk 0x0d9a36e0 +#define clk_gcc_usb3_phy_pipe_clk 0xf279aff2 +#define clk_gcc_usb3_clkref_clk 0xb6cc8f00 +#define clk_gcc_hdmi_clkref_clk 0x4d4eec04 +#define clk_gcc_edp_clkref_clk 0xa8685c3f +#define clk_gcc_ufs_clkref_clk 0x92aa126f +#define clk_gcc_pcie_clkref_clk 0xa2e247fa +#define clk_gcc_rx2_qlink_clkref_clk 0xd0ba986d +#define clk_gcc_rx1_usb2_clkref_clk 0x53351d25 +#define clk_gcc_pcie_phy_reset 0x9bc3c959 +#define clk_gcc_pcie_phy_com_reset 0x8bf513e6 +#define clk_gcc_pcie_phy_nocsr_com_phy_reset 0x0c16a2da +#define clk_gcc_qusb2phy_prim_reset 0x07550fa1 +#define clk_gcc_qusb2phy_sec_reset 0x3f3a87d0 +#define clk_gcc_mmss_noc_cfg_ahb_clk 0xb41a9d99 +#define clk_gcc_dcc_ahb_clk 0xfa14a88c +#define clk_hlos1_vote_lpass_core_smmu_clk 0x3aaa1743 +#define clk_hlos1_vote_lpass_adsp_smmu_clk 0xc76f702f +#define clk_gcc_mss_cfg_ahb_clk 0x111cde81 +#define clk_gcc_mss_q6_bimc_axi_clk 0x67544d62 +#define clk_gcc_mss_mnoc_bimc_axi_clk 0xf665d03f +#define clk_gpll0_out_msscc 0x7d794829 +#define clk_gcc_mss_snoc_axi_clk 0x0e71de85 +#define clk_gcc_qspi_ref_clk 0x766a0f7c +#define clk_gcc_qspi_ahb_clk 0x96969dc8 +#define clk_gcc_debug_mux 0x8121ac15 + +/* clock_mmss controlled clocks */ +#define clk_mmsscc_xo 0x05e63704 +#define clk_mmsscc_gpll0 0xe900c515 +#define clk_mmsscc_gpll0_div 0x73892e05 +#define clk_mmpll0_pll 0x361e3cfd +#define clk_mmpll1_pll 0x198e426b +#define clk_mmpll3_pll 0x18c76899 +#define clk_mmpll4_pll 0x22c063c1 +#define clk_mmpll5_pll 0xa41e1936 +#define clk_mmpll6_pll 0xc56fb440 +#define clk_mmpll7_pll 0x3ac216af +#define clk_mmpll10_pll 0x2561263b +#define clk_mmpll0_pll_out 0x1e9e24a8 +#define clk_mmpll1_pll_out 0x5fa32257 +#define clk_mmpll3_pll_out 0x6eb6328f +#define clk_mmpll4_pll_out 0xfb21c2fd +#define clk_mmpll5_pll_out 0xcc1897bf +#define clk_mmpll6_pll_out 0xfb1060bd +#define clk_mmpll7_pll_out 0x767758ed +#define clk_mmpll10_pll_out 0x3c5668f3 +#define clk_ahb_clk_src 0x86f49203 +#define clk_csi0_clk_src 0x227e65bc +#define clk_vfe0_clk_src 0xa0c2bd8f +#define clk_vfe1_clk_src 0x4e357366 +#define clk_mdp_clk_src 0x6dc1f8f1 +#define clk_maxi_clk_src 0x52c09777 +#define clk_cpp_clk_src 0x8382f56d +#define clk_jpeg0_clk_src 0x9a0a0ac3 +#define clk_rot_clk_src 0xce49b56c +#define clk_video_core_clk_src 0x8be4c944 +#define clk_csi1_clk_src 0x6a2a6c36 +#define clk_csi2_clk_src 0x4113589f +#define clk_csi3_clk_src 0xfd934012 +#define clk_fd_core_clk_src 0xe4799ab7 +#define clk_ext_dp_phy_pll_vco 0x441b576b +#define clk_ext_dp_phy_pll_link 0xea12644c +#define clk_dp_link_clk_src 0x370d0626 +#define clk_dp_crypto_clk_src 0xf8faa811 +#define clk_dp_pixel_clk_src 0xf5dfbabf +#define clk_ext_extpclk_clk_src 0xe5b273af +#define clk_ext_pclk0_clk_src 0x087c1612 +#define clk_ext_pclk1_clk_src 0x8067c5a3 +#define clk_pclk0_clk_src 0xccac1f35 +#define clk_pclk1_clk_src 0x090f68ac +#define clk_video_subcore0_clk_src 0x88d79636 +#define clk_video_subcore1_clk_src 0x4966930c +#define clk_cci_clk_src 0x822f3d97 +#define clk_camss_gp0_clk_src 0x43b063e9 +#define clk_camss_gp1_clk_src 0xa3315f1b +#define clk_mclk0_clk_src 0x266b3853 +#define clk_mclk1_clk_src 0xa73cad0c +#define clk_mclk2_clk_src 0x42545468 +#define clk_mclk3_clk_src 0x2bfbb714 +#define clk_csiphy_clk_src 0x8cceb70a +#define clk_csi0phytimer_clk_src 0xc8a309be +#define clk_csi1phytimer_clk_src 0x7c0fe23a +#define clk_csi2phytimer_clk_src 0x62ffea9c +#define clk_ext_byte0_clk_src 0xfb32f31e +#define clk_ext_byte1_clk_src 0x585ef6d4 +#define clk_byte0_clk_src 0x75cc885b +#define clk_byte1_clk_src 0x63c2c955 +#define clk_dp_aux_clk_src 0x2b6e972b +#define clk_dp_gtc_clk_src 0xc5a86a42 +#define clk_esc0_clk_src 0xb41d7c38 +#define clk_esc1_clk_src 0x3b0afa42 +#define clk_extpclk_clk_src 0xb2c31abd +#define clk_hdmi_clk_src 0xb40aeea9 +#define clk_vsync_clk_src 0xecb43940 +#define clk_mmss_bimc_smmu_ahb_clk 0x4825baf4 +#define clk_mmss_bimc_smmu_axi_clk 0xc365ac39 +#define clk_mmss_snoc_dvm_axi_clk 0x2c159a11 +#define clk_mmss_camss_ahb_clk 0xa51f2c1d +#define clk_mmss_camss_cci_ahb_clk 0xfda8bb6a +#define clk_mmss_camss_cci_clk 0x71bb5c97 +#define clk_mmss_camss_cpp_ahb_clk 0xd5554f15 +#define clk_mmss_camss_cpp_clk 0x8e99ef57 +#define clk_mmss_camss_cpp_axi_clk 0xd84e390b +#define clk_mmss_camss_cpp_vbif_ahb_clk 0x1b33a88e +#define clk_mmss_camss_cphy_csid0_clk 0x56114361 +#define clk_mmss_camss_csi0_ahb_clk 0x2b58d241 +#define clk_mmss_camss_csi0_clk 0xccfe39ef +#define clk_mmss_camss_csi0pix_clk 0x9e26509d +#define clk_mmss_camss_csi0rdi_clk 0x01d5bf83 +#define clk_mmss_camss_cphy_csid1_clk 0x79fbcd8a +#define clk_mmss_camss_csi1_ahb_clk 0x7073244b +#define clk_mmss_camss_csi1_clk 0x3eeeaac0 +#define clk_mmss_camss_csi1pix_clk 0xf1375139 +#define clk_mmss_camss_csi1rdi_clk 0x43185024 +#define clk_mmss_camss_cphy_csid2_clk 0xf295e3ef +#define clk_mmss_camss_csi2_ahb_clk 0x681c1479 +#define clk_mmss_camss_csi2_clk 0x94524569 +#define clk_mmss_camss_csi2pix_clk 0xf4de617d +#define clk_mmss_camss_csi2rdi_clk 0x4bf01dc5 +#define clk_mmss_camss_cphy_csid3_clk 0x100188e9 +#define clk_mmss_camss_csi3_ahb_clk 0xfae7c29b +#define clk_mmss_camss_csi3_clk 0x55e4bbae +#define clk_mmss_camss_csi3pix_clk 0xc166a015 +#define clk_mmss_camss_csi3rdi_clk 0x6983a4cd +#define clk_mmss_camss_csi_vfe0_clk 0x3b30b798 +#define clk_mmss_camss_csi_vfe1_clk 0xfe729af7 +#define clk_mmss_camss_csiphy0_clk 0x96c81af8 +#define clk_mmss_camss_csiphy1_clk 0xee9ac2bb +#define clk_mmss_camss_csiphy2_clk 0x3365e70e +#define clk_mmss_fd_ahb_clk 0x4ff1da4d +#define clk_mmss_fd_core_clk 0x749e7eb0 +#define clk_mmss_fd_core_uar_clk 0x8ea480c5 +#define clk_mmss_camss_gp0_clk 0x3f7f6c87 +#define clk_mmss_camss_gp1_clk 0xdccdd730 +#define clk_mmss_camss_ispif_ahb_clk 0xbda4f0e3 +#define clk_mmss_camss_jpeg0_clk 0x4cc73b07 +#define clk_mmss_camss_jpeg0_vote_clk 0xc9efa6ac +#define clk_mmss_camss_jpeg0_dma_vote_clk 0x371ec109 +#define clk_mmss_camss_jpeg_ahb_clk 0xde1fece3 +#define clk_mmss_camss_jpeg_axi_clk 0x7534616b +#define clk_mmss_camss_mclk0_clk 0x056293a7 +#define clk_mmss_camss_mclk1_clk 0x96c7b69b +#define clk_mmss_camss_mclk2_clk 0x8820556e +#define clk_mmss_camss_mclk3_clk 0xf90ffb67 +#define clk_mmss_camss_micro_ahb_clk 0x6c6fd3c7 +#define clk_mmss_camss_csi0phytimer_clk 0x7a78864e +#define clk_mmss_camss_csi1phytimer_clk 0x6e6c1de5 +#define clk_mmss_camss_csi2phytimer_clk 0x0235e2de +#define clk_mmss_camss_top_ahb_clk 0x120618d6 +#define clk_mmss_camss_vfe0_ahb_clk 0x137bd0bd +#define clk_mmss_camss_vfe0_clk 0xead28288 +#define clk_mmss_camss_vfe0_stream_clk 0xa0428287 +#define clk_mmss_camss_vfe1_ahb_clk 0xac0154c0 +#define clk_mmss_camss_vfe1_clk 0xc216b14d +#define clk_mmss_camss_vfe1_stream_clk 0x745af3b6 +#define clk_mmss_camss_vfe_vbif_ahb_clk 0x0109a9c6 +#define clk_mmss_camss_vfe_vbif_axi_clk 0xe626d8a1 +#define clk_mmss_mdss_ahb_clk 0x85d37ab5 +#define clk_mmss_mdss_axi_clk 0xdf04fc1d +#define clk_mmss_mdss_byte0_clk 0x38105d25 +#define clk_mmss_mdss_byte0_intf_clk 0x38e5aa79 +#define clk_mmss_mdss_byte0_intf_div_clk 0x8604f181 +#define clk_mmss_mdss_byte1_clk 0xe0c21354 +#define clk_mmss_mdss_byte1_intf_clk 0xcf654d8e +#define clk_mmss_mdss_byte1_intf_div_clk 0xcdf334c5 +#define clk_mmss_mdss_dp_aux_clk 0x23125eb6 +#define clk_mmss_mdss_dp_crypto_clk 0x9a072d4e +#define clk_mmss_mdss_dp_link_clk 0x8dd302d1 +#define clk_mmss_mdss_dp_link_intf_clk 0x70e386e6 +#define clk_mmss_mdss_dp_pixel_clk 0xb707b765 +#define clk_mmss_mdss_dp_gtc_clk 0xb59c151a +#define clk_mmss_mdss_esc0_clk 0x5721ff83 +#define clk_mmss_mdss_esc1_clk 0xc3d0376b +#define clk_mmss_mdss_extpclk_clk 0x74d5a954 +#define clk_mmss_mdss_hdmi_clk 0x28460a6d +#define clk_mmss_mdss_hdmi_dp_ahb_clk 0x5448519f +#define clk_mmss_mdss_mdp_clk 0x43539b0e +#define clk_mmss_mdss_mdp_lut_clk 0x00627b2b +#define clk_mmss_mdss_pclk0_clk 0xcc0e909d +#define clk_mmss_mdss_pclk1_clk 0x850d9146 +#define clk_mmss_mdss_rot_clk 0xbb7e71c4 +#define clk_mmss_mdss_vsync_clk 0x629b36dc +#define clk_mmss_misc_ahb_clk 0xea30b0e7 +#define clk_mmss_misc_cxo_clk 0xe620cd80 +#define clk_mmss_mnoc_ahb_clk 0x49a394f4 +#define clk_mmss_mnoc_maxi_clk 0xd8b7278f +#define clk_mmss_video_subcore0_clk 0x23fae359 +#define clk_mmss_video_subcore1_clk 0x5213a0c7 +#define clk_mmss_video_ahb_clk 0x94334ae9 +#define clk_mmss_video_axi_clk 0xf3178ba5 +#define clk_mmss_video_core_clk 0x78f14c85 +#define clk_mmss_video_maxi_clk 0x1785ef88 +#define clk_mmss_vmem_ahb_clk 0x4b18955b +#define clk_mmss_vmem_maxi_clk 0xb6067889 +#define clk_mmss_debug_mux 0xe646ffda + +/* external multimedia clocks */ +#define clk_dsi0pll_byteclk_mux 0xecf2c434 +#define clk_dsi0pll_byteclk_src 0x6f6f740f +#define clk_dsi0pll_pclk_mux 0x6c9da335 +#define clk_dsi0pll_pclk_src 0x5efd85d4 +#define clk_dsi0pll_pclk_src_mux 0x84b14663 +#define clk_dsi0pll_post_bit_div 0xf46dcf27 +#define clk_dsi0pll_pll_out_div1 0xeda5b7fe +#define clk_dsi0pll_pll_out_div2 0x97fa476d +#define clk_dsi0pll_pll_out_div4 0x90a98ce0 +#define clk_dsi0pll_pll_out_div8 0x9d9d85cf +#define clk_dsi0pll_pll_out_mux 0x179c27ca +#define clk_dsi0pll_post_vco_mux 0xfaf9bd1f +#define clk_dsi0pll_post_vco_div1 0xabb50b2a +#define clk_dsi0pll_post_vco_div4 0xbe51c091 +#define clk_dsi0pll_bitclk_src 0x36c3c437 +#define clk_dsi0pll_vco_clk 0x15940d40 + +#define clk_dsi1pll_byteclk_mux 0x14e2f38f +#define clk_dsi1pll_byteclk_src 0x4b65c298 +#define clk_dsi1pll_pclk_mux 0x4c0518b5 +#define clk_dsi1pll_pclk_src 0xeddcd80e +#define clk_dsi1pll_pclk_src_mux 0x3651feb3 +#define clk_dsi1pll_post_bit_div 0x712f0260 +#define clk_dsi1pll_pll_out_div8 0x87628ddb +#define clk_dsi1pll_pll_out_div4 0x0d9a384b +#define clk_dsi1pll_pll_out_div2 0x0c9b5748 +#define clk_dsi1pll_pll_out_div1 0x3193164e +#define clk_dsi1pll_pll_out_mux 0x171bf8fd +#define clk_dsi1pll_post_vco_mux 0xc6a90d20 +#define clk_dsi1pll_post_vco_div1 0x6f47ca7d +#define clk_dsi1pll_post_vco_div4 0x90628974 +#define clk_dsi1pll_bitclk_src 0x13ab045b +#define clk_dsi1pll_vco_clk 0x99797b50 + +#define clk_dp_vco_clk 0xfcaaeec7 +#define clk_dp_link_2x_clk_divsel_five 0xcfe3f5dd +#define clk_vco_divsel_four_clk_src 0xe0da19c0 +#define clk_vco_divsel_two_clk_src 0xb5cfc6a8 +#define clk_vco_divided_clk_src_mux 0x3f8197c2 +#define clk_hdmi_vco_clk 0xbb7dc20d + +/* clock_gpu controlled clocks*/ +#define clk_gpucc_xo 0xc4e1a890 +#define clk_gpucc_gpll0 0x0db0e37f +#define clk_gfx3d_clk_src 0x917f76ef +#define clk_rbbmtimer_clk_src 0x17649ecc +#define clk_gfx3d_isense_clk_src 0xecc3eafa +#define clk_rbcpr_clk_src 0x2c2e9af2 +#define clk_gpu_debug_div_clk 0x75d6f53f +#define clk_gpucc_gfx3d_clk 0x95f01bd5 +#define clk_gpucc_rbbmtimer_clk 0x58a0a7ca +#define clk_gpucc_gfx3d_isense_clk 0xb2678e80 +#define clk_gpucc_cxo_clk 0x6532dcae +#define clk_gpucc_rbcpr_clk 0x7bd750e8 +#define clk_gpu_pll0_pll 0x0e61ab4d +#define clk_gpu_pll0_pll_out_even 0xb0ed5009 +#define clk_gpu_pll0_pll_out_odd 0x08c5a8a5 +#define clk_gpu_pll0_postdiv_clk 0x76c19f3c +#define clk_gpucc_mx_clk 0x1edbb879 +#define clk_gpucc_gcc_dbg_clk 0x9ae8cd3c +#define clk_gfxcc_dbg_clk 0x3ed47625 + +/* CPU clocks */ +#define clk_pwrcl_clk 0xc554130e +#define clk_perfcl_clk 0x58869997 +#define clk_sys_apcsaux_clk_gcc 0xf905e862 +#define clk_xo_ao 0x428c856d +#define clk_osm_clk_src 0xaabe68c3 +#define clk_cpu_debug_mux 0x3ae8bcb2 + +/* Audio External Clocks */ +#define clk_audio_ap_clk 0x9b5727cb +#define clk_audio_pmi_clk 0xcbfe416d +#define clk_audio_ap_clk2 0x454d1e91 + +/* GCC block resets */ +#define QUSB2PHY_PRIM_BCR 0 +#define QUSB2PHY_SEC_BCR 1 +#define BLSP1_BCR 2 +#define BLSP2_BCR 3 +#define BOOT_ROM_BCR 4 +#define PRNG_BCR 5 +#define UFS_BCR 6 +#define USB_30_BCR 7 +#define USB3_PHY_BCR 8 +#define USB3PHY_PHY_BCR 9 +#define PCIE_0_PHY_BCR 10 +#define PCIE_PHY_BCR 11 +#define PCIE_PHY_COM_BCR 12 +#define PCIE_PHY_NOCSR_COM_PHY_BCR 13 + +/* MMSS block resets */ +#define CAMSS_MICRO_BCR 0 + +#endif diff --git a/include/dt-bindings/clock/msm-clocks-hwio-8996.h b/include/dt-bindings/clock/msm-clocks-hwio-8996.h new file mode 100644 index 000000000000..21dc1e6c55e3 --- /dev/null +++ b/include/dt-bindings/clock/msm-clocks-hwio-8996.h @@ -0,0 +1,499 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CLKFLAG_NO_RATE_CACHE 0x00004000 + +#define FMAX_LOWER 0 +#define FMAX_LOW 1 +#define FMAX_NOM 2 +#define FMAX_TURBO 3 + +#define HALT_CHECK_DELAY 5 + +#define RPM_MISC_CLK_TYPE 0x306b6c63 +#define RPM_BUS_CLK_TYPE 0x316b6c63 +#define RPM_MEM_CLK_TYPE 0x326b6c63 +#define RPM_IPA_CLK_TYPE 0x617069 +#define RPM_CE_CLK_TYPE 0x6563 +#define RPM_AGGR_CLK_TYPE 0x72676761 +#define RPM_SMD_KEY_ENABLE 0x62616E45 +#define RPM_MMAXI_CLK_TYPE 0x69786d6d + +#define CXO_CLK_SRC_ID 0x0 +#define QDSS_CLK_ID 0x1 + +#define PNOC_CLK_ID 0x0 +#define SNOC_CLK_ID 0x1 +#define CNOC_CLK_ID 0x2 +#define BIMC_CLK_ID 0x0 +#define IPA_CLK_ID 0x0 +#define CE1_CLK_ID 0x0 +#define BB_CLK1_ID 0x1 +#define BB_CLK2_ID 0x2 +#define RF_CLK1_ID 0x4 +#define RF_CLK2_ID 0x5 +#define LN_BB_CLK_ID 0x8 +#define LN_BB_CLK_PIN_ID 0x8 +#define DIV_CLK1_ID 0xb +#define DIV_CLK2_ID 0xc +#define DIV_CLK3_ID 0xd +#define BB_CLK1_PIN_ID 0x1 +#define BB_CLK2_PIN_ID 0x2 +#define RF_CLK1_PIN_ID 0x4 +#define RF_CLK2_PIN_ID 0x5 +#define AGGR1_NOC_ID 0x1 +#define AGGR2_NOC_ID 0x2 +#define MMXI_CLK_ID 0x0 + +#define MMSS_MMPLL0_MODE (0x0000) +#define MMSS_MMPLL1_MODE (0x0030) +#define MMSS_MMPLL2_MODE (0x4100) +#define MMSS_MMPLL2_USER_CTL_MODE (0X4110) +#define MMSS_MMPLL3_MODE (0x0060) +#define MMSS_MMPLL4_MODE (0x0090) +#define MMSS_MMPLL5_MODE (0x00C0) +#define MMSS_MMPLL8_MODE (0x4130) +#define MMSS_MMPLL8_USER_CTL_MODE (0X4140) +#define MMSS_MMPLL9_MODE (0x4200) +#define MMSS_MMPLL9_USER_CTL_MODE (0x4210) +#define MMSS_MMSS_PLL_VOTE_APCS (0x0100) +#define MMSS_PCLK0_CMD_RCGR (0x2000) +#define MMSS_PCLK1_CMD_RCGR (0x2020) +#define MMSS_MDP_CMD_RCGR (0x2040) +#define MMSS_EXTPCLK_CMD_RCGR (0x2060) +#define MMSS_VSYNC_CMD_RCGR (0x2080) +#define MMSS_HDMI_CMD_RCGR (0x2100) +#define MMSS_BYTE0_CMD_RCGR (0x2120) +#define MMSS_BYTE1_CMD_RCGR (0x2140) +#define MMSS_ESC0_CMD_RCGR (0x2160) +#define MMSS_ESC1_CMD_RCGR (0x2180) +#define MMSS_MDSS_AHB_CBCR (0x2308) +#define MMSS_MDSS_HDMI_AHB_CBCR (0x230C) +#define MMSS_MDSS_AXI_CBCR (0x2310) +#define MMSS_MDSS_PCLK0_CBCR (0x2314) +#define MMSS_MDSS_PCLK1_CBCR (0x2318) +#define MMSS_MDSS_MDP_CBCR (0x231C) +#define MMSS_MDSS_BCR (0x2300) +#define MMSS_MDSS_EXTPCLK_CBCR (0x2324) +#define MMSS_MDSS_VSYNC_CBCR (0x2328) +#define MMSS_MDSS_HDMI_CBCR (0x2338) +#define MMSS_MDSS_BYTE0_CBCR (0x233C) +#define MMSS_MDSS_BYTE1_CBCR (0x2340) +#define MMSS_MDSS_ESC0_CBCR (0x2344) +#define MMSS_MDSS_ESC1_CBCR (0x2348) +#define MMSS_CSI0PHYTIMER_CMD_RCGR (0x3000) +#define MMSS_CAMSS_PHY0_CSI0PHYTIMER_CBCR (0x3024) +#define MMSS_CSI1PHYTIMER_CMD_RCGR (0x3030) +#define MMSS_CAMSS_PHY1_CSI1PHYTIMER_CBCR (0x3054) +#define MMSS_CSI2PHYTIMER_CMD_RCGR (0x3060) +#define MMSS_CAMSS_PHY2_CSI2PHYTIMER_CBCR (0x3084) +#define MMSS_CSI0_CMD_RCGR (0x3090) +#define MMSS_CAMSS_CSI0_CBCR (0x30B4) +#define MMSS_CAMSS_CSI0_AHB_CBCR (0x30BC) +#define MMSS_CAMSS_CSI0PHY_CBCR (0x30C4) +#define MMSS_CAMSS_CSI0RDI_CBCR (0x30D4) +#define MMSS_CAMSS_CSI0PIX_CBCR (0x30E4) +#define MMSS_CSI1_CMD_RCGR (0x3100) +#define MMSS_CAMSS_CSI1_CBCR (0x3124) +#define MMSS_CAMSS_CSI1_AHB_CBCR (0x3128) +#define MMSS_CAMSS_CSI1PHY_CBCR (0x3134) +#define MMSS_CAMSS_CSI1RDI_CBCR (0x3144) +#define MMSS_CAMSS_CSI1PIX_CBCR (0x3154) +#define MMSS_CSI2_CMD_RCGR (0x3160) +#define MMSS_CAMSS_CSI2_CBCR (0x3184) +#define MMSS_CAMSS_CSI2_AHB_CBCR (0x3188) +#define MMSS_CAMSS_CSI2PHY_CBCR (0x3194) +#define MMSS_CAMSS_CSI2RDI_CBCR (0x31A4) +#define MMSS_CAMSS_CSI2PIX_CBCR (0x31B4) +#define MMSS_CSI3_CMD_RCGR (0x31C0) +#define MMSS_CAMSS_CSI3_CBCR (0x31E4) +#define MMSS_CAMSS_CSI3_AHB_CBCR (0x31E8) +#define MMSS_CAMSS_CSI3PHY_CBCR (0x31F4) +#define MMSS_CAMSS_CSI3RDI_CBCR (0x3204) +#define MMSS_CAMSS_CSI3PIX_CBCR (0x3214) +#define MMSS_CAMSS_ISPIF_AHB_CBCR (0x3224) +#define MMSS_CCI_CMD_RCGR (0x3300) +#define MMSS_CAMSS_CCI_CCI_CBCR (0x3344) +#define MMSS_CAMSS_CCI_CCI_AHB_CBCR (0x3348) +#define MMSS_MCLK0_CMD_RCGR (0x3360) +#define MMSS_CAMSS_MCLK0_CBCR (0x3384) +#define MMSS_MCLK1_CMD_RCGR (0x3390) +#define MMSS_CAMSS_MCLK1_CBCR (0x33B4) +#define MMSS_MCLK2_CMD_RCGR (0x33C0) +#define MMSS_CAMSS_MCLK2_CBCR (0x33E4) +#define MMSS_MCLK3_CMD_RCGR (0x33F0) +#define MMSS_CAMSS_MCLK3_CBCR (0x3414) +#define MMSS_CAMSS_GP0_CBCR (0x3444) +#define MMSS_CAMSS_GP1_CBCR (0x3474) +#define MMSS_CAMSS_TOP_AHB_CBCR (0x3484) +#define MMSS_CAMSS_AHB_CBCR (0x348C) +#define MMSS_CAMSS_MICRO_BCR (0x3490) +#define MMSS_CAMSS_MICRO_AHB_CBCR (0x3494) +#define MMSS_JPEG0_CMD_RCGR (0x3500) +#define MMSS_JPEG2_CMD_RCGR (0x3540) +#define MMSS_JPEG_DMA_CMD_RCGR (0x3560) +#define MMSS_CAMSS_JPEG0_CBCR (0x35A8) +#define MMSS_CAMSS_JPEG2_CBCR (0x35B0) +#define MMSS_CAMSS_JPEG_BCR (0x35A0) +#define MMSS_CAMSS_JPEG_DMA_CBCR (0x35C0) +#define MMSS_CAMSS_JPEG_AHB_CBCR (0x35B4) +#define MMSS_CAMSS_JPEG_AXI_CBCR (0x35B8) +#define MMSS_VFE0_CMD_RCGR (0x3600) +#define MMSS_VFE1_CMD_RCGR (0x3620) +#define MMSS_CPP_CMD_RCGR (0x3640) +#define MMSS_CAMSS_VFE_VFE0_CBCR (0x36A8) +#define MMSS_CAMSS_VFE_VFE1_CBCR (0x36AC) +#define MMSS_CAMSS_VFE_CPP_CBCR (0x36B0) +#define MMSS_CAMSS_VFE_CPP_AHB_CBCR (0x36B4) +#define MMSS_CAMSS_VFE_AHB_CBCR (0x36B8) +#define MMSS_CAMSS_VFE_AXI_CBCR (0x36BC) +#define MMSS_CAMSS_VFE_CPP_AXI_CBCR (0x36C4) +#define MMSS_CAMSS_CSI_VFE0_CBCR (0x3704) +#define MMSS_CAMSS_CSI_VFE1_CBCR (0x3714) +#define MMSS_FD_CORE_CMD_RCGR (0x3B00) +#define MMSS_FD_CORE_CBCR (0x3B68) +#define MMSS_FD_BCR (0x3B60) +#define MMSS_FD_CORE_UAR_CBCR (0x3B6C) +#define MMSS_FD_AHB_CBCR (0x3B74) +#define MMSS_OXILI_GFX3D_CBCR (0x4028) +#define MMSS_OXILICX_AHB_CBCR (0x403C) +#define MMSS_MMSS_MISC_AHB_CBCR (0x5018) +#define MMSS_MMSS_DEBUG_CLK_CTL (0x0900) +#define MMSS_MAXI_CMD_RCGR (0x5090) +#define MMSS_VIDEO_CORE_CMD_RCGR (0x1000) +#define MMSS_CSIPHY0_3P_CMD_RCGR (0x3240) +#define MMSS_CSIPHY1_3P_CMD_RCGR (0x3260) +#define MMSS_CSIPHY2_3P_CMD_RCGR (0x3280) +#define MMSS_CAMSS_GP0_CMD_RCGR (0x3420) +#define MMSS_CAMSS_GP1_CMD_RCGR (0x3450) +#define MMSS_RBBMTIMER_CMD_RCGR (0x4090) +#define MMSS_RBCPR_CMD_RCGR (0x4060) +#define MMSS_VIDEO_SUBCORE0_CMD_RCGR (0x1060) +#define MMSS_VIDEO_SUBCORE1_CMD_RCGR (0x1080) +#define MMSS_BTO_AHB_CBCR (0x5028) +#define MMSS_CAMSS_CCI_AHB_CBCR (0x3348) +#define MMSS_AHB_CMD_RCGR (0x5000) +#define MMSS_CAMSS_CCI_CBCR (0x3344) +#define MMSS_CAMSS_CPP_AHB_CBCR (0x36B4) +#define MMSS_CAMSS_CPP_CBCR (0x36B0) +#define MMSS_CAMSS_CPP_BCR (0x36D0) +#define MMSS_CAMSS_CPP_AXI_CBCR (0x36C4) +#define MMSS_CAMSS_CPP_VBIF_AHB_CBCR (0x36C8) +#define MMSS_CAMSS_CSIPHY0_3P_CBCR (0x3234) +#define MMSS_CAMSS_CSIPHY1_3P_CBCR (0x3254) +#define MMSS_CAMSS_CSIPHY2_3P_CBCR (0x3274) +#define MMSS_CAMSS_JPEG0_CBCR (0x35A8) +#define MMSS_CAMSS_JPEG2_CBCR (0x35B0) +#define MMSS_CAMSS_JPEG_AHB_CBCR (0x35B4) +#define MMSS_CAMSS_JPEG_AXI_CBCR (0x35B8) +#define MMSS_CAMSS_CSI0PHYTIMER_CBCR (0x3024) +#define MMSS_CAMSS_CSI1PHYTIMER_CBCR (0x3054) +#define MMSS_CAMSS_CSI2PHYTIMER_CBCR (0x3084) +#define MMSS_CAMSS_VFE0_AHB_CBCR (0x3668) +#define MMSS_CAMSS_VFE0_CBCR (0x36A8) +#define MMSS_CAMSS_VFE0_BCR (0x3660) +#define MMSS_CAMSS_VFE0_STREAM_CBCR (0x3720) +#define MMSS_CAMSS_VFE1_AHB_CBCR (0x3678) +#define MMSS_CAMSS_VFE1_CBCR (0x36AC) +#define MMSS_CAMSS_VFE1_BCR (0x3670) +#define MMSS_CAMSS_VFE1_STREAM_CBCR (0x3724) +#define MMSS_GPU_AHB_CBCR (0x403C) +#define MMSS_GPU_AON_ISENSE_CBCR (0x4044) +#define MMSS_GPU_GX_GFX3D_CBCR (0x4028) +#define MMSS_GPU_GX_BCR (0x4020) +#define MMSS_GPU_GX_RBBMTIMER_CBCR (0x40B0) +#define MMSS_MMSS_MISC_CXO_CBCR (0x5014) +#define MMSS_MMAGIC_BIMC_NOC_CFG_AHB_CBCR (0x5298) +#define MMSS_MMAGIC_CAMSS_AXI_CBCR (0x3C44) +#define MMSS_MMAGIC_CAMSS_NOC_CFG_AHB_CBCR (0x3C48) +#define MMSS_MMSS_MMAGIC_CFG_AHB_CBCR (0x5054) +#define MMSS_MMAGIC_MDSS_AXI_CBCR (0x2474) +#define MMSS_MMAGIC_MDSS_NOC_CFG_AHB_CBCR (0x2478) +#define MMSS_MMAGIC_VIDEO_AXI_CBCR (0x1194) +#define MMSS_MMAGIC_VIDEO_NOC_CFG_AHB_CBCR (0x1198) +#define MMSS_MMSS_MMAGIC_AHB_CBCR (0x5024) +#define MMSS_MMSS_MMAGIC_MAXI_CBCR (0x5074) +#define MMSS_MMSS_RBCPR_AHB_CBCR (0x4088) +#define MMSS_MMSS_RBCPR_CBCR (0x4084) +#define MMSS_MMSS_SPDM_CPP_CBCR (0x0220) +#define MMSS_MMSS_SPDM_JPEG_DMA_CBCR (0x0208) +#define MMSS_SMMU_CPP_AHB_CBCR (0x3C14) +#define MMSS_SMMU_CPP_AXI_CBCR (0x3C18) +#define MMSS_SMMU_JPEG_AHB_CBCR (0x3C24) +#define MMSS_SMMU_JPEG_AXI_CBCR (0x3C28) +#define MMSS_SMMU_MDP_AHB_CBCR (0x2454) +#define MMSS_SMMU_MDP_AXI_CBCR (0x2458) +#define MMSS_SMMU_ROT_AHB_CBCR (0x2444) +#define MMSS_SMMU_ROT_AXI_CBCR (0x2448) +#define MMSS_SMMU_VFE_AHB_CBCR (0x3C04) +#define MMSS_SMMU_VFE_AXI_CBCR (0x3C08) +#define MMSS_SMMU_VIDEO_AHB_CBCR (0x1174) +#define MMSS_SMMU_VIDEO_AXI_CBCR (0x1178) +#define MMSS_VIDEO_AHB_CBCR (0x1030) +#define MMSS_VIDEO_AXI_CBCR (0x1034) +#define MMSS_VIDEO_CXO_CBCR (0x1028) +#define MMSS_VIDEO_MAXI_CBCR (0x1038) +#define MMSS_VIDEO_SUBCORE0_CBCR (0x1048) +#define MMSS_VIDEO_SUBCORE1_CBCR (0x104C) +#define MMSS_VMEM_AHB_CBCR (0x1208) +#define MMSS_VMEM_MAXI_CBCR (0x1204) +#define MMSS_VIDEO_CORE_CBCR (0x1028) +#define MMSS_VIDEO_BCR (0x1020) +#define MMSS_GFX3D_CMD_RCGR (0x4000) +#define MMSS_MDSS_BCR (0x2300) +#define MMSS_MMAGICAHB_BCR (0x5020) +#define MMSS_MMAGICAXI_BCR (0x5060) +#define MMSS_MMSS_SPDM_BCR (0x0200) +#define MMSS_VIDEO_BCR (0x1020) +#define MMSS_MNOC_DCD_CONFIG_AHB (0x50D8) + +#define GCC_GPLL0_MODE (0x00000) +#define PLLTEST_PAD_CFG (0x6200C) +#define GCC_XO_DIV4_CBCR (0x43008) +#define CLOCK_FRQ_MEASURE_CTL (0x62004) +#define CLOCK_FRQ_MEASURE_STATUS (0x62008) +#define GCC_USB_30_BCR (0x0F000) +#define GCC_USB30_MASTER_CBCR (0x0F008) +#define GCC_USB30_SLEEP_CBCR (0x0F00C) +#define GCC_USB30_MOCK_UTMI_CBCR (0x0F010) +#define GCC_USB30_MASTER_CMD_RCGR (0x0F014) +#define GCC_USB30_MOCK_UTMI_CMD_RCGR (0x0F028) +#define GCC_USB3_PHY_BCR (0x50020) +#define GCC_USB3PHY_PHY_BCR (0x50024) +#define GCC_USB3_PHY_AUX_CBCR (0x50000) +#define GCC_USB3_PHY_PIPE_CBCR (0x50004) +#define GCC_USB3_PHY_AUX_CMD_RCGR (0x5000C) +#define GCC_USB_PHY_CFG_AHB2PHY_CBCR (0x6A004) +#define GCC_SDCC1_APPS_CMD_RCGR (0x13010) +#define GCC_SDCC1_APPS_CBCR (0x13004) +#define GCC_SDCC1_AHB_CBCR (0x13008) +#define GCC_SDCC2_APPS_CMD_RCGR (0x14010) +#define GCC_SDCC2_APPS_CBCR (0x14004) +#define GCC_SDCC2_AHB_CBCR (0x14008) +#define GCC_SDCC3_APPS_CMD_RCGR (0x15010) +#define GCC_SDCC3_APPS_CBCR (0x15004) +#define GCC_SDCC3_AHB_CBCR (0x15008) +#define GCC_SDCC4_APPS_CMD_RCGR (0x16010) +#define GCC_SDCC4_APPS_CBCR (0x16004) +#define GCC_SDCC4_AHB_CBCR (0x16008) +#define GCC_QUSB2PHY_PRIM_BCR (0x12038) +#define GCC_QUSB2PHY_SEC_BCR (0x1203C) +#define GCC_PERIPH_NOC_USB20_AHB_CBCR (0x06010) +#define GCC_BLSP1_AHB_CBCR (0x17004) +#define GCC_BLSP1_QUP1_SPI_APPS_CBCR (0x19004) +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR (0x19008) +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x19020) +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x1B020) +#define GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x1D020) +#define GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x1F020) +#define GCC_BLSP1_QUP5_I2C_APPS_CMD_RCGR (0x21020) +#define GCC_BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x23020) +#define GCC_BLSP2_QUP1_I2C_APPS_CMD_RCGR (0x26020) +#define GCC_BLSP2_QUP2_I2C_APPS_CMD_RCGR (0x28020) +#define GCC_BLSP2_QUP3_I2C_APPS_CMD_RCGR (0x2A020) +#define GCC_BLSP2_QUP4_I2C_APPS_CMD_RCGR (0x2C020) +#define GCC_BLSP2_QUP5_I2C_APPS_CMD_RCGR (0x2E020) +#define GCC_BLSP2_QUP6_I2C_APPS_CMD_RCGR (0x30020) +#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR (0x1900C) +#define GCC_BLSP1_UART1_APPS_CBCR (0x1A004) +#define GCC_BLSP1_UART1_APPS_CMD_RCGR (0x1A00C) +#define GCC_BLSP1_QUP2_SPI_APPS_CBCR (0x1B004) +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR (0x1B008) +#define GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR (0x1B00C) +#define GCC_BLSP1_UART2_APPS_CBCR (0x1C004) +#define GCC_BLSP1_UART2_APPS_CMD_RCGR (0x1C00C) +#define GCC_BLSP1_QUP3_SPI_APPS_CBCR (0x1D004) +#define GCC_BLSP1_QUP3_I2C_APPS_CBCR (0x1D008) +#define GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR (0x1D00C) +#define GCC_BLSP1_UART3_APPS_CBCR (0x1E004) +#define GCC_BLSP1_UART3_APPS_CMD_RCGR (0x1E00C) +#define GCC_BLSP1_QUP4_SPI_APPS_CBCR (0x1F004) +#define GCC_BLSP1_QUP4_I2C_APPS_CBCR (0x1F008) +#define GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR (0x1F00C) +#define GCC_BLSP1_UART4_APPS_CBCR (0x20004) +#define GCC_BLSP1_UART4_APPS_CMD_RCGR (0x2000C) +#define GCC_BLSP1_QUP5_SPI_APPS_CBCR (0x21004) +#define GCC_BLSP1_QUP5_I2C_APPS_CBCR (0x21008) +#define GCC_BLSP1_QUP5_SPI_APPS_CMD_RCGR (0x2100C) +#define GCC_BLSP1_UART5_APPS_CBCR (0x22004) +#define GCC_BLSP1_UART5_APPS_CMD_RCGR (0x2200C) +#define GCC_BLSP1_QUP6_SPI_APPS_CBCR (0x23004) +#define GCC_BLSP1_QUP6_I2C_APPS_CBCR (0x23008) +#define GCC_BLSP1_QUP6_SPI_APPS_CMD_RCGR (0x2300C) +#define GCC_BLSP1_UART6_APPS_CBCR (0x24004) +#define GCC_BLSP1_UART6_APPS_CMD_RCGR (0x2400C) +#define GCC_BLSP2_AHB_CBCR (0x25004) +#define GCC_BLSP2_QUP1_SPI_APPS_CBCR (0x26004) +#define GCC_BLSP2_QUP1_I2C_APPS_CBCR (0x26008) +#define GCC_BLSP2_QUP1_SPI_APPS_CMD_RCGR (0x2600C) +#define GCC_BLSP2_UART1_APPS_CBCR (0x27004) +#define GCC_BLSP2_UART1_APPS_CMD_RCGR (0x2700C) +#define GCC_BLSP2_QUP2_SPI_APPS_CBCR (0x28004) +#define GCC_BLSP2_QUP2_I2C_APPS_CBCR (0x28008) +#define GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR (0x2800C) +#define GCC_BLSP2_UART2_APPS_CBCR (0x29004) +#define GCC_BLSP2_UART2_APPS_CMD_RCGR (0x2900C) +#define GCC_BLSP2_QUP3_SPI_APPS_CBCR (0x2A004) +#define GCC_BLSP2_QUP3_I2C_APPS_CBCR (0x2A008) +#define GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR (0x2A00C) +#define GCC_BLSP2_UART3_APPS_CBCR (0x2B004) +#define GCC_BLSP2_UART3_APPS_CMD_RCGR (0x2B00C) +#define GCC_BLSP2_QUP4_SPI_APPS_CBCR (0x2C004) +#define GCC_BLSP2_QUP4_I2C_APPS_CBCR (0x2C008) +#define GCC_BLSP2_QUP4_SPI_APPS_CMD_RCGR (0x2C00C) +#define GCC_BLSP2_UART4_APPS_CBCR (0x2D004) +#define GCC_BLSP2_UART4_APPS_CMD_RCGR (0x2D00C) +#define GCC_BLSP2_QUP5_SPI_APPS_CBCR (0x2E004) +#define GCC_BLSP2_QUP5_I2C_APPS_CBCR (0x2E008) +#define GCC_BLSP2_QUP5_SPI_APPS_CMD_RCGR (0x2E00C) +#define GCC_BLSP2_UART5_APPS_CBCR (0x2F004) +#define GCC_BLSP2_UART5_APPS_CMD_RCGR (0x2F00C) +#define GCC_BLSP2_QUP6_SPI_APPS_CBCR (0x30004) +#define GCC_BLSP2_QUP6_I2C_APPS_CBCR (0x30008) +#define GCC_BLSP2_QUP6_SPI_APPS_CMD_RCGR (0x3000C) +#define GCC_BLSP2_UART6_APPS_CBCR (0x31004) +#define GCC_BLSP2_UART6_APPS_CMD_RCGR (0x3100C) +#define GCC_PDM_AHB_CBCR (0x33004) +#define GCC_PDM2_CBCR (0x3300C) +#define GCC_PDM2_CMD_RCGR (0x33010) +#define GCC_PRNG_AHB_CBCR (0x34004) +#define GCC_TSIF_AHB_CBCR (0x36004) +#define GCC_TSIF_REF_CBCR (0x36008) +#define GCC_TSIF_REF_CMD_RCGR (0x36010) +#define GCC_BOOT_ROM_AHB_CBCR (0x38004) +#define GCC_GCC_XO_DIV4_CBCR (0x43008) +#define GCC_APCS_GPLL_ENA_VOTE (0x52000) +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) +#define GCC_APCS_CLOCK_SLEEP_ENA_VOTE (0x52008) +#define GCC_GCC_DEBUG_CLK_CTL (0x62000) +#define GCC_CLOCK_FRQ_MEASURE_CTL (0x62004) +#define GCC_CLOCK_FRQ_MEASURE_STATUS (0x62008) +#define GCC_PLLTEST_PAD_CFG (0x6200C) +#define GCC_GP1_CBCR (0x64000) +#define GCC_GP1_CMD_RCGR (0x64004) +#define GCC_GP2_CBCR (0x65000) +#define GCC_GP2_CMD_RCGR (0x65004) +#define GCC_GP3_CBCR (0x66000) +#define GCC_GP3_CMD_RCGR (0x66004) +#define GCC_GPLL4_MODE (0x77000) +#define GCC_UFS_BCR (0x75000) +#define GCC_UFS_AXI_CBCR (0x75008) +#define GCC_UFS_AHB_CBCR (0x7500C) +#define GCC_UFS_TX_CFG_CBCR (0x75010) +#define GCC_UFS_RX_CFG_CBCR (0x75014) +#define GCC_UFS_TX_SYMBOL_0_CBCR (0x75018) +#define GCC_UFS_RX_SYMBOL_0_CBCR (0x7501C) +#define GCC_UFS_RX_SYMBOL_1_CBCR (0x75020) +#define GCC_UFS_AXI_CMD_RCGR (0x75024) +#define GCC_PCIE_0_AUX_CBCR (0x6B014) +#define GCC_PCIE_0_BCR (0x6B000) +#define GCC_PCIE_0_CFG_AHB_CBCR (0x6B010) +#define GCC_PCIE_0_GDSCR (0x6B004) +#define GCC_PCIE_0_LINK_DOWN_BCR (0x6C014) +#define GCC_PCIE_0_MISC_RESET (0x6C018) +#define GCC_PCIE_0_MSTR_AXI_CBCR (0x6B00C) +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR (0x6C020) +#define GCC_PCIE_0_PHY_BCR (0x6C01C) +#define GCC_PCIE_0_PIPE_CBCR (0x6B018) +#define GCC_PCIE_0_SLV_AXI_CBCR (0x6B008) +#define GCC_PCIE_1_AUX_CBCR (0x6D014) +#define GCC_PCIE_1_BCR (0x6D000) +#define GCC_PCIE_1_CFG_AHB_CBCR (0x6D010) +#define GCC_PCIE_1_GDSCR (0x6D004) +#define GCC_PCIE_1_LINK_DOWN_BCR (0x6D030) +#define GCC_PCIE_1_MISC (0x6D01C) +#define GCC_PCIE_1_MISC_RESET (0x6D034) +#define GCC_PCIE_1_MSTR_AXI_CBCR (0x6D00C) +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR (0x6D03C) +#define GCC_PCIE_1_PHY_BCR (0x6D038) +#define GCC_PCIE_1_PIPE_CBCR (0x6D018) +#define GCC_PCIE_1_SLV_AXI_CBCR (0x6D008) +#define GCC_PCIE_2_AUX_CBCR (0x6E014) +#define GCC_PCIE_2_BCR (0x6E000) +#define GCC_PCIE_2_CFG_AHB_CBCR (0x6E010) +#define GCC_PCIE_2_GDSCR (0x6E004) +#define GCC_PCIE_2_LINK_DOWN_BCR (0x6E030) +#define GCC_PCIE_2_MISC (0x6E01C) +#define GCC_PCIE_2_MISC_RESET (0x6E034) +#define GCC_PCIE_2_MSTR_AXI_CBCR (0x6E00C) +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR (0x6E03C) +#define GCC_PCIE_2_PHY_BCR (0x6E038) +#define GCC_PCIE_2_PIPE_CBCR (0x6E018) +#define GCC_PCIE_2_SLV_AXI_CBCR (0x6E008) +#define GCC_PCIE_AUX_CFG_RCGR (0x6C004) +#define GCC_PCIE_AUX_CMD_RCGR (0x6C000) +#define GCC_PCIE_AUX_D (0x6C010) +#define GCC_PCIE_AUX_M (0x6C008) +#define GCC_PCIE_AUX_N (0x6C00C) +#define GCC_PCIE_CLKREF_EN (0x88010) +#define GCC_PCIE_PHY_AUX_CBCR (0x6F008) +#define GCC_PCIE_PHY_BCR (0x6F000) +#define GCC_PCIE_PHY_CFG_AHB_BCR (0x6F010) +#define GCC_PCIE_PHY_CFG_AHB_CBCR (0x6F004) +#define GCC_PCIE_PHY_COM_BCR (0x6F014) +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR (0x6F00C) +#define GCC_SYS_NOC_HS_AXI_CMD_RCGR (0x04044) +#define GCC_USB20_MASTER_CMD_RCGR (0x12010) +#define GCC_UFS_ICE_CORE_CMD_RCGR (0x76014) +#define GCC_PCIE_0_PIPE_CMD_RCGR (0x6B01C) +#define GCC_PCIE_1_PIPE_CMD_RCGR (0x6D01C) +#define GCC_PCIE_2_PIPE_CMD_RCGR (0x6E01C) +#define GCC_USB20_MOCK_UTMI_CMD_RCGR (0x12024) +#define GCC_SYS_NOC_HS_AXI_CBCR (0x04034) +#define GCC_UFS_ICE_CORE_CBCR (0x76010) +#define GCC_UFS_UNIPRO_CORE_CBCR (0x7600C) +#define GCC_USB_20_BCR (0x12000) +#define GCC_USB20_MASTER_CBCR (0x12004) +#define GCC_USB20_MOCK_UTMI_CBCR (0x1200C) +#define GCC_USB20_SLEEP_CBCR (0x12008) +#define GCC_BIMC_BCR (0x44000) +#define GCC_BLSP1_BCR (0x17000) +#define GCC_BLSP2_BCR (0x25000) +#define GCC_BOOT_ROM_BCR (0x38000) +#define GCC_PRNG_BCR (0x34000) +#define GCC_AGGRE0_SNOC_AXI_CBCR (0x81008) +#define GCC_AGGRE0_CNOC_AHB_CBCR (0x8100C) +#define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CTL (0x8101C) +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR (0x7D010) +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR (0x7D014) +#define GCC_MMSS_NOC_CFG_AHB_CBCR (0x09008) +#define GCC_USB3_CLKREF_EN (0x8800C) +#define GCC_HDMI_CLKREF_EN (0x88000) +#define GCC_EDP_CLKREF_EN (0x88004) +#define GCC_UFS_CLKREF_EN (0x88008) +#define GCC_PCIE_CLKREF_EN (0x88010) +#define GCC_RX2_USB2_CLKREF_EN (0x88014) +#define GCC_RX1_USB2_CLKREF_EN (0x88018) +#define GCC_SMMU_AGGRE0_AXI_CBCR (0x81014) +#define GCC_SMMU_AGGRE0_AHB_CBCR (0x81018) +#define GCC_SYS_NOC_USB3_AXI_CBCR (0x0F03C) +#define GCC_SYS_NOC_UFS_AXI_CBCR (0x75038) +#define GCC_UFS_SYS_CLK_CORE_CBCR (0x76030) +#define GCC_UFS_TX_SYMBOL_CLK_CORE_CBCR (0x76034) +#define GCC_AGGRE2_USB3_AXI_CBCR (0x83018) +#define GCC_AGGRE2_UFS_AXI_CBCR (0x83014) +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 (0x5200C) +#define GCC_MMSS_BIMC_GFX_CBCR (0x09010) +#define GCC_BIMC_GFX_CBCR (0x46018) +#define GCC_HMSS_RBCPR_CBCR (0x4800C) +#define GCC_HMSS_RBCPR_CMD_RCGR (0x48040) +#define GCC_QSPI_AHB_CBCR (0x8B004) +#define GCC_QSPI_SER_CBCR (0x8B008) +#define GCC_QSPI_SER_CMD_RCGR (0x8B00C) +#define GCC_SDCC1_ICE_CORE_CBCR (0x13038) +#define GCC_SDCC1_ICE_CORE_CMD_RCGR (0x13024) +#define GCC_MSS_CFG_AHB_CBCR (0x8A000) +#define GCC_MSS_Q6_BIMC_AXI_CBCR (0x8A028) +#define GCC_MSS_SNOC_AXI_CBCR (0x8A024) +#define GCC_MSS_MNOC_BIMC_AXI_CBCR (0x8A004) +#define GCC_DCC_AHB_CBCR (0x84004) +#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CBCR (0x85000) diff --git a/include/dt-bindings/clock/msm-clocks-hwio-8998.h b/include/dt-bindings/clock/msm-clocks-hwio-8998.h new file mode 100644 index 000000000000..fc42ac3d49a0 --- /dev/null +++ b/include/dt-bindings/clock/msm-clocks-hwio-8998.h @@ -0,0 +1,395 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CLKFLAG_NO_RATE_CACHE 0x00004000 + +#define FMAX_LOWER 0 +#define FMAX_LOW 1 +#define FMAX_NOM 2 +#define FMAX_TURBO 3 + +#define HALT_CHECK_DELAY 5 + +#define RPM_MISC_CLK_TYPE 0x306b6c63 +#define RPM_BUS_CLK_TYPE 0x316b6c63 +#define RPM_MEM_CLK_TYPE 0x326b6c63 +#define RPM_IPA_CLK_TYPE 0x617069 +#define RPM_CE_CLK_TYPE 0x6563 +#define RPM_AGGR_CLK_TYPE 0x72676761 +#define RPM_SMD_KEY_ENABLE 0x62616E45 +#define RPM_MMAXI_CLK_TYPE 0x69786d6d + +#define CXO_CLK_SRC_ID 0x0 +#define QDSS_CLK_ID 0x1 +#define SNOC_CLK_ID 0x1 +#define CNOC_CLK_ID 0x2 +#define CNOC_PERIPH_CLK_ID 0x0 +#define BIMC_CLK_ID 0x0 +#define IPA_CLK_ID 0x0 +#define CE1_CLK_ID 0x0 +#define RF_CLK1_ID 0x4 +#define RF_CLK2_ID 0x5 +#define RF_CLK3_ID 0x6 +#define LN_BB_CLK1_ID 0x1 +#define LN_BB_CLK2_ID 0x2 +#define LN_BB_CLK3_ID 0x3 +#define DIV_CLK1_ID 0xb +#define DIV_CLK2_ID 0xc +#define DIV_CLK3_ID 0xd +#define RF_CLK1_PIN_ID 0x4 +#define RF_CLK2_PIN_ID 0x5 +#define RF_CLK3_PIN_ID 0x6 +#define LN_BB_CLK1_PIN_ID 0x1 +#define LN_BB_CLK2_PIN_ID 0x2 +#define LN_BB_CLK3_PIN_ID 0x3 +#define AGGR1_NOC_ID 0x1 +#define AGGR2_NOC_ID 0x2 +#define MMSSNOC_AXI_CLK_ID 0x0 + +#define APCS_COMMON_LMH_CMD_RCGR 0x0012C + +#define GCC_APCS_GPLL_ENA_VOTE 0x52000 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE 0x52004 +#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1 0x5200C +#define PLLTEST_PAD_CFG 0x6200C +#define GCC_XO_DIV4_CBCR 0x43008 +#define CLOCK_FRQ_MEASURE_CTL 0x62004 +#define CLOCK_FRQ_MEASURE_STATUS 0x62008 +#define GCC_GPLL0_MODE 0x00000 +#define GCC_GPLL4_MODE 0x77000 +#define GCC_USB30_MASTER_CMD_RCGR 0x0F014 +#define GCC_PCIE_AUX_CMD_RCGR 0x6C000 +#define GCC_UFS_AXI_CMD_RCGR 0x75018 +#define GCC_BLSP1_QUP1_I2C_APPS_CMD_RCGR 0x19020 +#define GCC_BLSP1_QUP1_SPI_APPS_CMD_RCGR 0x1900C +#define GCC_BLSP1_QUP2_I2C_APPS_CMD_RCGR 0x1B020 +#define GCC_BLSP1_QUP2_SPI_APPS_CMD_RCGR 0x1B00C +#define GCC_BLSP1_QUP3_I2C_APPS_CMD_RCGR 0x1D020 +#define GCC_BLSP1_QUP3_SPI_APPS_CMD_RCGR 0x1D00C +#define GCC_BLSP1_QUP4_I2C_APPS_CMD_RCGR 0x1F020 +#define GCC_BLSP1_QUP4_SPI_APPS_CMD_RCGR 0x1F00C +#define GCC_BLSP1_QUP5_I2C_APPS_CMD_RCGR 0x21020 +#define GCC_BLSP1_QUP5_SPI_APPS_CMD_RCGR 0x2100C +#define GCC_BLSP1_QUP6_I2C_APPS_CMD_RCGR 0x23020 +#define GCC_BLSP1_QUP6_SPI_APPS_CMD_RCGR 0x2300C +#define GCC_BLSP1_UART1_APPS_CMD_RCGR 0x1A00C +#define GCC_BLSP1_UART2_APPS_CMD_RCGR 0x1C00C +#define GCC_BLSP1_UART3_APPS_CMD_RCGR 0x1E00C +#define GCC_BLSP2_QUP1_I2C_APPS_CMD_RCGR 0x26020 +#define GCC_BLSP2_QUP2_I2C_APPS_CMD_RCGR 0x28020 +#define GCC_BLSP2_QUP3_I2C_APPS_CMD_RCGR 0x2A020 +#define GCC_BLSP2_QUP4_I2C_APPS_CMD_RCGR 0x2C020 +#define GCC_BLSP2_QUP5_I2C_APPS_CMD_RCGR 0x2E020 +#define GCC_BLSP2_QUP6_I2C_APPS_CMD_RCGR 0x30020 +#define GCC_BLSP2_QUP1_SPI_APPS_CMD_RCGR 0x2600C +#define GCC_BLSP2_QUP2_SPI_APPS_CMD_RCGR 0x2800C +#define GCC_BLSP2_QUP3_SPI_APPS_CMD_RCGR 0x2A00C +#define GCC_BLSP2_QUP4_SPI_APPS_CMD_RCGR 0x2C00C +#define GCC_BLSP2_QUP5_SPI_APPS_CMD_RCGR 0x2E00C +#define GCC_BLSP2_QUP6_SPI_APPS_CMD_RCGR 0x3000C +#define GCC_BLSP2_UART1_APPS_CMD_RCGR 0x2700C +#define GCC_BLSP2_UART2_APPS_CMD_RCGR 0x2900C +#define GCC_BLSP2_UART3_APPS_CMD_RCGR 0x2B00C +#define GCC_GP1_CMD_RCGR 0x64004 +#define GCC_GP2_CMD_RCGR 0x65004 +#define GCC_GP3_CMD_RCGR 0x66004 +#define GCC_HMSS_RBCPR_CMD_RCGR 0x48044 +#define GCC_PDM2_CMD_RCGR 0x33010 +#define GCC_SDCC2_APPS_CMD_RCGR 0x14010 +#define GCC_SDCC4_APPS_CMD_RCGR 0x16010 +#define GCC_TSIF_REF_CMD_RCGR 0x36010 +#define GCC_UFS_ICE_CORE_CMD_RCGR 0x76010 +#define GCC_UFS_PHY_AUX_CMD_RCGR 0x76044 +#define GCC_UFS_UNIPRO_CORE_CMD_RCGR 0x76028 +#define GCC_USB30_MOCK_UTMI_CMD_RCGR 0x0F028 +#define GCC_USB3_PHY_AUX_CMD_RCGR 0x5000C +#define GCC_QSPI_REF_CMD_RCGR 0x9000C +#define GCC_PCIE_0_PHY_BCR 0x6C01C +#define GCC_HDMI_CLKREF_EN 0x88000 +#define GCC_UFS_CLKREF_EN 0x88004 +#define GCC_USB3_CLKREF_EN 0x88008 +#define GCC_PCIE_CLKREF_EN 0x8800C +#define GCC_RX1_USB2_CLKREF_EN 0x88014 +#define GCC_USB3_PHY_BCR 0x50020 +#define GCC_AGGRE1_NOC_XO_CBCR 0x8202C +#define GCC_AGGRE1_UFS_AXI_CBCR 0x82028 +#define GCC_AGGRE1_USB3_AXI_CBCR 0x82024 +#define GCC_BIMC_MSS_Q6_AXI_CBCR 0x4401C +#define GCC_BLSP1_AHB_CBCR 0x17004 +#define GCC_BLSP1_BCR 0x17000 +#define GCC_BLSP1_QUP1_SPI_APPS_CBCR 0x19004 +#define GCC_BLSP1_QUP1_I2C_APPS_CBCR 0x19008 +#define GCC_BLSP1_QUP2_SPI_APPS_CBCR 0x1B004 +#define GCC_BLSP1_QUP2_I2C_APPS_CBCR 0x1B008 +#define GCC_BLSP1_QUP3_SPI_APPS_CBCR 0x1D004 +#define GCC_BLSP1_QUP3_I2C_APPS_CBCR 0x1D008 +#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 0x1F004 +#define GCC_BLSP1_QUP4_I2C_APPS_CBCR 0x1F008 +#define GCC_BLSP1_QUP5_SPI_APPS_CBCR 0x21004 +#define GCC_BLSP1_QUP5_I2C_APPS_CBCR 0x21008 +#define GCC_BLSP1_QUP6_SPI_APPS_CBCR 0x23004 +#define GCC_BLSP1_QUP6_I2C_APPS_CBCR 0x23008 +#define GCC_BLSP1_UART1_APPS_CBCR 0x1A004 +#define GCC_BLSP1_UART2_APPS_CBCR 0x1C004 +#define GCC_BLSP1_UART3_APPS_CBCR 0x1E004 +#define GCC_BLSP2_AHB_CBCR 0x25004 +#define GCC_BLSP2_BCR 0x25000 +#define GCC_BLSP2_QUP1_SPI_APPS_CBCR 0x26004 +#define GCC_BLSP2_QUP1_I2C_APPS_CBCR 0x26008 +#define GCC_BLSP2_QUP2_I2C_APPS_CBCR 0x28008 +#define GCC_BLSP2_QUP2_SPI_APPS_CBCR 0x28004 +#define GCC_BLSP2_QUP3_SPI_APPS_CBCR 0x2A004 +#define GCC_BLSP2_QUP3_I2C_APPS_CBCR 0x2A008 +#define GCC_BLSP2_QUP4_SPI_APPS_CBCR 0x2C004 +#define GCC_BLSP2_QUP4_I2C_APPS_CBCR 0x2C008 +#define GCC_BLSP2_QUP5_SPI_APPS_CBCR 0x2E004 +#define GCC_BLSP2_QUP5_I2C_APPS_CBCR 0x2E008 +#define GCC_BLSP2_QUP6_SPI_APPS_CBCR 0x30004 +#define GCC_BLSP2_QUP6_I2C_APPS_CBCR 0x30008 +#define GCC_BLSP2_UART1_APPS_CBCR 0x27004 +#define GCC_BLSP2_UART2_APPS_CBCR 0x29004 +#define GCC_BLSP2_UART3_APPS_CBCR 0x2B004 +#define GCC_BOOT_ROM_AHB_CBCR 0x38004 +#define GCC_BOOT_ROM_BCR 0x38000 +#define GCC_CFG_NOC_USB3_AXI_CBCR 0x05018 +#define GCC_BIMC_GFX_CBCR 0x46040 +#define GCC_GP1_CBCR 0x64000 +#define GCC_GP2_CBCR 0x65000 +#define GCC_GP3_CBCR 0x66000 +#define GCC_GPU_BIMC_GFX_CBCR 0x71010 +#define GCC_GPU_CFG_AHB_CBCR 0x71004 +#define GCC_GPU_IREF_EN 0x88010 +#define GCC_HMSS_DVM_BUS_CBCR 0x4808C +#define GCC_HMSS_RBCPR_CBCR 0x48008 +#define GCC_MMSS_SYS_NOC_AXI_CBCR 0x09000 +#define GCC_MMSS_NOC_CFG_AHB_CBCR 0x09004 +#define GCC_PCIE_0_SLV_AXI_CBCR 0x6B008 +#define GCC_PCIE_0_MSTR_AXI_CBCR 0x6B00C +#define GCC_PCIE_0_CFG_AHB_CBCR 0x6B010 +#define GCC_PCIE_0_AUX_CBCR 0x6B014 +#define GCC_PCIE_0_PIPE_CBCR 0x6B018 +#define GCC_PCIE_PHY_AUX_CBCR 0x6F004 +#define GCC_PCIE_PHY_BCR 0x6F000 +#define GCC_PCIE_PHY_COM_BCR 0x6F014 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 0x6F00C +#define GCC_QUSB2PHY_PRIM_BCR 0x12000 +#define GCC_QUSB2PHY_SEC_BCR 0x12004 +#define GCC_PDM2_CBCR 0x3300C +#define GCC_PDM_AHB_CBCR 0x33004 +#define GCC_PRNG_AHB_CBCR 0x34004 +#define GCC_PRNG_BCR 0x34000 +#define GCC_SDCC2_APPS_CBCR 0x14004 +#define GCC_SDCC2_AHB_CBCR 0x14008 +#define GCC_SDCC4_APPS_CBCR 0x16004 +#define GCC_SDCC4_AHB_CBCR 0x16008 +#define GCC_TSIF_AHB_CBCR 0x36004 +#define GCC_TSIF_REF_CBCR 0x36008 +#define GCC_UFS_AXI_CBCR 0x75008 +#define GCC_UFS_BCR 0x75000 +#define GCC_UFS_AHB_CBCR 0x7500C +#define GCC_UFS_TX_SYMBOL_0_CBCR 0x75010 +#define GCC_UFS_RX_SYMBOL_0_CBCR 0x75014 +#define GCC_UFS_RX_SYMBOL_1_CBCR 0x7605C +#define GCC_UFS_UNIPRO_CORE_CBCR 0x76008 +#define GCC_UFS_ICE_CORE_CBCR 0x7600C +#define GCC_UFS_PHY_AUX_CBCR 0x76040 +#define GCC_USB30_MASTER_CBCR 0x0F008 +#define GCC_USB30_SLEEP_CBCR 0x0F00C +#define GCC_USB30_MOCK_UTMI_CBCR 0x0F010 +#define GCC_USB_30_BCR 0x0F000 +#define GCC_USB3_PHY_AUX_CBCR 0x50000 +#define GCC_USB3_PHY_PIPE_CBCR 0x50004 +#define GCC_USB3PHY_PHY_BCR 0x50024 +#define GCC_APCS_CLOCK_SLEEP_ENA_VOTE 0x52008 +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_HMSS_GPLL0_CMD_RCGR 0x4805C +#define GCC_MSS_CFG_AHB_CBCR 0x8A000 +#define GCC_MSS_Q6_BIMC_AXI_CBCR 0x8A040 +#define GCC_MSS_MNOC_BIMC_AXI_CBCR 0x8A004 +#define GCC_MSS_SNOC_AXI_CBCR 0x8A03C +#define GCC_DCC_AHB_CBCR 0x84004 +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR 0x7D010 +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CBCR 0x7D014 +#define GCC_QSPI_AHB_CBCR 0x90004 +#define GCC_QSPI_REF_CBCR 0x90008 +#define GCC_MMSS_MISC 0x0902C +#define GCC_GPU_MISC 0x71028 + +#define GPUCC_GPU_PLL0_PLL_MODE 0x00000 +#define GPUCC_GPU_PLL0_USER_CTL_MODE 0x0000C +#define GPUCC_GFX3D_CMD_RCGR 0x01070 +#define GPUCC_RBBMTIMER_CMD_RCGR 0x010B0 +#define GPUCC_GFX3D_ISENSE_CMD_RCGR 0x01100 +#define GPUCC_RBCPR_CMD_RCGR 0x01030 +#define GPUCC_GFX3D_CBCR 0x01098 +#define GPUCC_RBBMTIMER_CBCR 0x010D0 +#define GPUCC_GFX3D_ISENSE_CBCR 0x01124 +#define GPUCC_CXO_CBCR 0x01020 +#define GPUCC_RBCPR_CBCR 0x01054 +#define GPU_GX_BCR 0x01090 +#define GPUCC_GX_DOMAIN_MISC 0x00130 +#define GPUCC_GPU_DD_WRAP_CTRL 0x00430 +#define GPUCC_DEBUG_CLK_CTL 0x00120 + +#define MMSS_PLL_VOTE_APCS 0x001E0 +#define MMSS_MMPLL0_PLL_MODE 0x0C000 +#define MMSS_MMPLL1_PLL_MODE 0x0C050 +#define MMSS_MMPLL3_PLL_MODE 0x00000 +#define MMSS_MMPLL4_PLL_MODE 0x00050 +#define MMSS_MMPLL5_PLL_MODE 0x000A0 +#define MMSS_MMPLL6_PLL_MODE 0x000F0 +#define MMSS_MMPLL7_PLL_MODE 0x00140 +#define MMSS_MMPLL10_PLL_MODE 0x00190 +#define MMSS_AHB_CMD_RCGR 0x05000 +#define MMSS_CSI0_CMD_RCGR 0x03090 +#define MMSS_VFE0_CMD_RCGR 0x03600 +#define MMSS_VFE1_CMD_RCGR 0x03620 +#define MMSS_MDP_CMD_RCGR 0x02040 +#define MMSS_MAXI_CMD_RCGR 0x0F020 +#define MMSS_CPP_CMD_RCGR 0x03640 +#define MMSS_JPEG0_CMD_RCGR 0x03500 +#define MMSS_ROT_CMD_RCGR 0x021A0 +#define MMSS_VIDEO_CORE_CMD_RCGR 0x01000 +#define MMSS_CSI1_CMD_RCGR 0x03100 +#define MMSS_CSI2_CMD_RCGR 0x03160 +#define MMSS_CSI3_CMD_RCGR 0x031C0 +#define MMSS_FD_CORE_CMD_RCGR 0x03B00 +#define MMSS_BYTE0_CMD_RCGR 0x02120 +#define MMSS_BYTE1_CMD_RCGR 0x02140 +#define MMSS_PCLK0_CMD_RCGR 0x02000 +#define MMSS_PCLK1_CMD_RCGR 0x02020 +#define MMSS_VIDEO_SUBCORE0_CMD_RCGR 0x01060 +#define MMSS_VIDEO_SUBCORE1_CMD_RCGR 0x01080 +#define MMSS_CSIPHY_CMD_RCGR 0x03800 +#define MMSS_CCI_CMD_RCGR 0x03300 +#define MMSS_CAMSS_GP0_CMD_RCGR 0x03420 +#define MMSS_CAMSS_GP1_CMD_RCGR 0x03450 +#define MMSS_MCLK0_CMD_RCGR 0x03360 +#define MMSS_MCLK1_CMD_RCGR 0x03390 +#define MMSS_MCLK2_CMD_RCGR 0x033C0 +#define MMSS_MCLK3_CMD_RCGR 0x033F0 +#define MMSS_CAMSS_CSI2PHYTIMER_CBCR 0x03084 +#define MMSS_CSI0PHYTIMER_CMD_RCGR 0x03000 +#define MMSS_CSI1PHYTIMER_CMD_RCGR 0x03030 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_DP_GTC_CMD_RCGR 0x02280 +#define MMSS_ESC0_CMD_RCGR 0x02160 +#define MMSS_ESC1_CMD_RCGR 0x02180 +#define MMSS_EXTPCLK_CMD_RCGR 0x02060 +#define MMSS_HDMI_CMD_RCGR 0x02100 +#define MMSS_VSYNC_CMD_RCGR 0x02080 +#define MMSS_BIMC_SMMU_AHB_CBCR 0x0E004 +#define MMSS_BIMC_SMMU_AXI_CBCR 0x0E008 +#define MMSS_SNOC_DVM_AXI_CBCR 0x0E040 +#define MMSS_CAMSS_AHB_CBCR 0x0348C +#define MMSS_CAMSS_CCI_AHB_CBCR 0x03348 +#define MMSS_CAMSS_CCI_CBCR 0x03344 +#define MMSS_CAMSS_CPP_AHB_CBCR 0x036B4 +#define MMSS_CAMSS_CPP_CBCR 0x036B0 +#define MMSS_CAMSS_CPP_AXI_CBCR 0x036C4 +#define MMSS_CAMSS_CPP_VBIF_AHB_CBCR 0x036C8 +#define MMSS_CAMSS_CPHY_CSID0_CBCR 0x03730 +#define MMSS_CAMSS_CSI0_AHB_CBCR 0x030BC +#define MMSS_CAMSS_CSI0_CBCR 0x030B4 +#define MMSS_CAMSS_CSI0PIX_CBCR 0x030E4 +#define MMSS_CAMSS_CSI0RDI_CBCR 0x030D4 +#define MMSS_CAMSS_CPHY_CSID1_CBCR 0x03734 +#define MMSS_CAMSS_CSI1_AHB_CBCR 0x03128 +#define MMSS_CAMSS_CSI1_CBCR 0x03124 +#define MMSS_CAMSS_CSI1PIX_CBCR 0x03154 +#define MMSS_CAMSS_CSI1RDI_CBCR 0x03144 +#define MMSS_CAMSS_CPHY_CSID2_CBCR 0x03738 +#define MMSS_CAMSS_CSI2_AHB_CBCR 0x03188 +#define MMSS_CAMSS_CSI2_CBCR 0x03184 +#define MMSS_CAMSS_CSI2PIX_CBCR 0x031B4 +#define MMSS_CAMSS_CSI2RDI_CBCR 0x031A4 +#define MMSS_CAMSS_CPHY_CSID3_CBCR 0x0373C +#define MMSS_CAMSS_CSI3_AHB_CBCR 0x031E8 +#define MMSS_CAMSS_CSI3_CBCR 0x031E4 +#define MMSS_CAMSS_CSI3PIX_CBCR 0x03214 +#define MMSS_CAMSS_CSI3RDI_CBCR 0x03204 +#define MMSS_CAMSS_CSI_VFE0_CBCR 0x03704 +#define MMSS_CAMSS_CSI_VFE1_CBCR 0x03714 +#define MMSS_CAMSS_CSIPHY0_CBCR 0x03740 +#define MMSS_CAMSS_CSIPHY1_CBCR 0x03744 +#define MMSS_CAMSS_CSIPHY2_CBCR 0x03748 +#define MMSS_FD_AHB_CBCR 0x03B74 +#define MMSS_FD_CORE_CBCR 0x03B68 +#define MMSS_FD_CORE_UAR_CBCR 0x03B6C +#define MMSS_CAMSS_GP0_CBCR 0x03444 +#define MMSS_CAMSS_GP1_CBCR 0x03474 +#define MMSS_CAMSS_ISPIF_AHB_CBCR 0x03224 +#define MMSS_CAMSS_JPEG0_CBCR 0x035A8 +#define MMSS_CAMSS_JPEG_AHB_CBCR 0x035B4 +#define MMSS_CAMSS_JPEG_AXI_CBCR 0x035B8 +#define MMSS_CAMSS_MCLK0_CBCR 0x03384 +#define MMSS_CAMSS_MCLK1_CBCR 0x033B4 +#define MMSS_CAMSS_MCLK2_CBCR 0x033E4 +#define MMSS_CAMSS_MCLK3_CBCR 0x03414 +#define MMSS_CAMSS_MICRO_AHB_CBCR 0x03494 +#define MMSS_CAMSS_CSI0PHYTIMER_CBCR 0x03024 +#define MMSS_CAMSS_CSI1PHYTIMER_CBCR 0x03054 +#define MMSS_CSI2PHYTIMER_CMD_RCGR 0x03060 +#define MMSS_CAMSS_TOP_AHB_CBCR 0x03484 +#define MMSS_CAMSS_VFE0_AHB_CBCR 0x03668 +#define MMSS_CAMSS_VFE0_CBCR 0x036A8 +#define MMSS_CAMSS_VFE0_STREAM_CBCR 0x03720 +#define MMSS_CAMSS_VFE1_AHB_CBCR 0x03678 +#define MMSS_CAMSS_VFE1_CBCR 0x036AC +#define MMSS_CAMSS_VFE1_STREAM_CBCR 0x03724 +#define MMSS_CAMSS_VFE_VBIF_AHB_CBCR 0x036B8 +#define MMSS_CAMSS_VFE_VBIF_AXI_CBCR 0x036BC +#define MMSS_MDSS_AHB_CBCR 0x02308 +#define MMSS_MDSS_AXI_CBCR 0x02310 +#define MMSS_MDSS_BYTE0_CBCR 0x0233C +#define MMSS_MDSS_BYTE0_INTF_CBCR 0x02374 +#define MMSS_MDSS_BYTE0_INTF_DIV 0x0237C +#define MMSS_MDSS_BYTE1_CBCR 0x02340 +#define MMSS_MDSS_BYTE1_INTF_CBCR 0x02378 +#define MMSS_MDSS_BYTE1_INTF_DIV 0x02380 +#define MMSS_MDSS_DP_AUX_CBCR 0x02364 +#define MMSS_MDSS_DP_CRYPTO_CBCR 0x0235C +#define MMSS_MDSS_DP_GTC_CBCR 0x02368 +#define MMSS_MDSS_DP_LINK_CBCR 0x02354 +#define MMSS_MDSS_DP_LINK_INTF_CBCR 0x02358 +#define MMSS_MDSS_DP_PIXEL_CBCR 0x02360 +#define MMSS_MDSS_ESC0_CBCR 0x02344 +#define MMSS_MDSS_ESC1_CBCR 0x02348 +#define MMSS_MDSS_EXTPCLK_CBCR 0x02324 +#define MMSS_MDSS_HDMI_CBCR 0x02338 +#define MMSS_MDSS_HDMI_DP_AHB_CBCR 0x0230C +#define MMSS_MDSS_MDP_CBCR 0x0231C +#define MMSS_MDSS_MDP_LUT_CBCR 0x02320 +#define MMSS_MDSS_PCLK0_CBCR 0x02314 +#define MMSS_MDSS_PCLK1_CBCR 0x02318 +#define MMSS_MDSS_ROT_CBCR 0x02350 +#define MMSS_MDSS_VSYNC_CBCR 0x02328 +#define MMSS_MISC_AHB_CBCR 0x00328 +#define MMSS_MISC_CXO_CBCR 0x00324 +#define MMSS_MNOC_AHB_CBCR 0x05024 +#define MMSS_MNOC_MAXI_CBCR 0x0F004 +#define MMSS_VIDEO_SUBCORE0_CBCR 0x01048 +#define MMSS_VIDEO_SUBCORE1_CBCR 0x0104C +#define MMSS_VIDEO_AHB_CBCR 0x01030 +#define MMSS_VIDEO_AXI_CBCR 0x01034 +#define MMSS_VIDEO_CORE_CBCR 0x01028 +#define MMSS_VIDEO_MAXI_CBCR 0x01038 +#define MMSS_VMEM_AHB_CBCR 0x0F068 +#define MMSS_VMEM_MAXI_CBCR 0x0F064 +#define MMSS_DP_AUX_CMD_RCGR 0x02260 +#define MMSS_DP_CRYPTO_CMD_RCGR 0x02220 +#define MMSS_DP_LINK_CMD_RCGR 0x02200 +#define MMSS_DP_PIXEL_CMD_RCGR 0x02240 +#define MMSS_DEBUG_CLK_CTL 0x00900 diff --git a/include/dt-bindings/clock/qcom,cpu-osm.h b/include/dt-bindings/clock/qcom,cpu-osm.h new file mode 100644 index 000000000000..71745fab287a --- /dev/null +++ b/include/dt-bindings/clock/qcom,cpu-osm.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_CPU_OSM_H +#define _DT_BINDINGS_CLK_MSM_CPU_OSM_H + +/* CPU clock IDs */ +#define SYS_APCSAUX_CLK_GCC 0 +#define PWRCL_CLK 1 +#define PERFCL_CLK 2 +#define OSM_CLK_SRC 3 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h new file mode 100644 index 000000000000..efed312fe914 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H +#define _DT_BINDINGS_CLK_MSM_GCC_8996_H + +/* Hardware/Dummy/Voter clocks */ +#define GCC_XO 0 +#define GCC_CE1_AHB_M_CLK 1 +#define GCC_CE1_AXI_M_CLK 2 +#define GCC_GPLL0_EARLY_DIV 3 +#define GCC_UFS_TX_CFG_CLK_SRC 4 +#define GCC_UFS_RX_CFG_CLK_SRC 5 +#define GCC_UFS_ICE_CORE_PDIV_CLK_SRC 6 + +/* RCGs and Branches */ +#define GPLL0_EARLY 7 +#define GPLL0 8 +#define GPLL4_EARLY 9 +#define GPLL4 10 +#define SYSTEM_NOC_CLK_SRC 11 +#define CONFIG_NOC_CLK_SRC 12 +#define PERIPH_NOC_CLK_SRC 13 +#define MMSS_BIMC_GFX_CLK_SRC 14 +#define USB30_MASTER_CLK_SRC 15 +#define USB30_MOCK_UTMI_CLK_SRC 16 +#define USB3_PHY_AUX_CLK_SRC 17 +#define USB20_MASTER_CLK_SRC 18 +#define USB20_MOCK_UTMI_CLK_SRC 19 +#define SDCC1_APPS_CLK_SRC 20 +#define SDCC1_ICE_CORE_CLK_SRC 21 +#define SDCC2_APPS_CLK_SRC 22 +#define SDCC3_APPS_CLK_SRC 23 +#define SDCC4_APPS_CLK_SRC 24 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 25 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 26 +#define BLSP1_UART1_APPS_CLK_SRC 27 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 28 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29 +#define BLSP1_UART2_APPS_CLK_SRC 30 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 31 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 32 +#define BLSP1_UART3_APPS_CLK_SRC 33 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 35 +#define BLSP1_UART4_APPS_CLK_SRC 36 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 37 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 38 +#define BLSP1_UART5_APPS_CLK_SRC 39 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 40 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 41 +#define BLSP1_UART6_APPS_CLK_SRC 42 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 43 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 44 +#define BLSP2_UART1_APPS_CLK_SRC 45 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 46 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47 +#define BLSP2_UART2_APPS_CLK_SRC 48 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 49 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 50 +#define BLSP2_UART3_APPS_CLK_SRC 51 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 53 +#define BLSP2_UART4_APPS_CLK_SRC 54 +#define BLSP2_QUP5_SPI_APPS_CLK_SRC 55 +#define BLSP2_QUP5_I2C_APPS_CLK_SRC 56 +#define BLSP2_UART5_APPS_CLK_SRC 57 +#define BLSP2_QUP6_SPI_APPS_CLK_SRC 58 +#define BLSP2_QUP6_I2C_APPS_CLK_SRC 59 +#define BLSP2_UART6_APPS_CLK_SRC 60 +#define PDM2_CLK_SRC 61 +#define TSIF_REF_CLK_SRC 62 +#define CE1_CLK_SRC 63 +#define GCC_SLEEP_CLK_SRC 64 +#define BIMC_CLK_SRC 65 +#define HMSS_AHB_CLK_SRC 66 +#define BIMC_HMSS_AXI_CLK_SRC 67 +#define HMSS_RBCPR_CLK_SRC 68 +#define HMSS_GPLL0_CLK_SRC 69 +#define GP1_CLK_SRC 70 +#define GP2_CLK_SRC 71 +#define GP3_CLK_SRC 72 +#define PCIE_AUX_CLK_SRC 73 +#define UFS_AXI_CLK_SRC 74 +#define UFS_ICE_CORE_CLK_SRC 75 +#define QSPI_SER_CLK_SRC 76 +#define GCC_SYS_NOC_AXI_CLK 77 +#define GCC_SYS_NOC_HMSS_AHB_CLK 78 +#define GCC_SNOC_CNOC_AHB_CLK 79 +#define GCC_SNOC_PNOC_AHB_CLK 80 +#define GCC_SYS_NOC_AT_CLK 81 +#define GCC_SYS_NOC_USB3_AXI_CLK 82 +#define GCC_SYS_NOC_UFS_AXI_CLK 83 +#define GCC_CFG_NOC_AHB_CLK 84 +#define GCC_PERIPH_NOC_AHB_CLK 85 +#define GCC_PERIPH_NOC_USB20_AHB_CLK 86 +#define GCC_TIC_CLK 87 +#define GCC_IMEM_AXI_CLK 88 +#define GCC_MMSS_SYS_NOC_AXI_CLK 89 +#define GCC_MMSS_NOC_CFG_AHB_CLK 90 +#define GCC_MMSS_BIMC_GFX_CLK 91 +#define GCC_USB30_MASTER_CLK 92 +#define GCC_USB30_SLEEP_CLK 93 +#define GCC_USB30_MOCK_UTMI_CLK 94 +#define GCC_USB3_PHY_AUX_CLK 95 +#define GCC_USB3_PHY_PIPE_CLK 96 +#define GCC_USB20_MASTER_CLK 97 +#define GCC_USB20_SLEEP_CLK 98 +#define GCC_USB20_MOCK_UTMI_CLK 99 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 100 +#define GCC_SDCC1_APPS_CLK 101 +#define GCC_SDCC1_AHB_CLK 102 +#define GCC_SDCC1_ICE_CORE_CLK 103 +#define GCC_SDCC2_APPS_CLK 104 +#define GCC_SDCC2_AHB_CLK 105 +#define GCC_SDCC3_APPS_CLK 106 +#define GCC_SDCC3_AHB_CLK 107 +#define GCC_SDCC4_APPS_CLK 108 +#define GCC_SDCC4_AHB_CLK 109 +#define GCC_BLSP1_AHB_CLK 110 +#define GCC_BLSP1_SLEEP_CLK 111 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 112 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 113 +#define GCC_BLSP1_UART1_APPS_CLK 114 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 115 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 116 +#define GCC_BLSP1_UART2_APPS_CLK 117 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 118 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 119 +#define GCC_BLSP1_UART3_APPS_CLK 120 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 121 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 122 +#define GCC_BLSP1_UART4_APPS_CLK 123 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 124 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 125 +#define GCC_BLSP1_UART5_APPS_CLK 126 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 127 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 128 +#define GCC_BLSP1_UART6_APPS_CLK 129 +#define GCC_BLSP2_AHB_CLK 130 +#define GCC_BLSP2_SLEEP_CLK 131 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 132 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 133 +#define GCC_BLSP2_UART1_APPS_CLK 134 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 135 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 136 +#define GCC_BLSP2_UART2_APPS_CLK 137 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 138 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 139 +#define GCC_BLSP2_UART3_APPS_CLK 140 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 141 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 142 +#define GCC_BLSP2_UART4_APPS_CLK 143 +#define GCC_BLSP2_QUP5_SPI_APPS_CLK 144 +#define GCC_BLSP2_QUP5_I2C_APPS_CLK 145 +#define GCC_BLSP2_UART5_APPS_CLK 146 +#define GCC_BLSP2_QUP6_SPI_APPS_CLK 147 +#define GCC_BLSP2_QUP6_I2C_APPS_CLK 148 +#define GCC_BLSP2_UART6_APPS_CLK 149 +#define GCC_PDM_AHB_CLK 150 +#define GCC_PDM_XO4_CLK 151 +#define GCC_PDM2_CLK 152 +#define GCC_PRNG_AHB_CLK 153 +#define GCC_TSIF_AHB_CLK 154 +#define GCC_TSIF_REF_CLK 155 +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 156 +#define GCC_TCSR_AHB_CLK 157 +#define GCC_BOOT_ROM_AHB_CLK 158 +#define GCC_MSG_RAM_AHB_CLK 159 +#define GCC_TLMM_AHB_CLK 160 +#define GCC_TLMM_CLK 161 +#define GCC_MPM_AHB_CLK 162 +#define GCC_SPMI_SER_CLK 163 +#define GCC_SPMI_CNOC_AHB_CLK 164 +#define GCC_BIMC_HMSS_AXI_CLK 165 +#define GCC_BIMC_GFX_CLK 166 +#define GCC_HMSS_AHB_CLK 167 +#define GCC_HMSS_SLV_AXI_CLK 168 +#define GCC_HMSS_MSTR_AXI_CLK 169 +#define GCC_HMSS_RBCPR_CLK 170 +#define GCC_GP1_CLK 171 +#define GCC_GP2_CLK 172 +#define GCC_GP3_CLK 173 +#define GCC_PCIE_0_SLV_AXI_CLK 174 +#define GCC_PCIE_0_MSTR_AXI_CLK 175 +#define GCC_PCIE_0_CFG_AHB_CLK 176 +#define GCC_PCIE_0_AUX_CLK 177 +#define GCC_PCIE_0_PIPE_CLK 178 +#define GCC_PCIE_1_SLV_AXI_CLK 179 +#define GCC_PCIE_1_MSTR_AXI_CLK 180 +#define GCC_PCIE_1_CFG_AHB_CLK 181 +#define GCC_PCIE_1_AUX_CLK 182 +#define GCC_PCIE_1_PIPE_CLK 183 +#define GCC_PCIE_2_SLV_AXI_CLK 184 +#define GCC_PCIE_2_MSTR_AXI_CLK 185 +#define GCC_PCIE_2_CFG_AHB_CLK 186 +#define GCC_PCIE_2_AUX_CLK 187 +#define GCC_PCIE_2_PIPE_CLK 188 +#define GCC_PCIE_PHY_CFG_AHB_CLK 189 +#define GCC_PCIE_PHY_AUX_CLK 190 +#define GCC_UFS_AXI_CLK 191 +#define GCC_UFS_AHB_CLK 192 +#define GCC_UFS_TX_CFG_CLK 193 +#define GCC_UFS_RX_CFG_CLK 194 +#define GCC_UFS_TX_SYMBOL_0_CLK 195 +#define GCC_UFS_RX_SYMBOL_0_CLK 196 +#define GCC_UFS_RX_SYMBOL_1_CLK 197 +#define GCC_UFS_UNIPRO_CORE_CLK 198 +#define GCC_UFS_ICE_CORE_CLK 199 +#define GCC_UFS_SYS_CLK_CORE_CLK 200 +#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 201 +#define GCC_AGGRE0_SNOC_AXI_CLK 202 +#define GCC_AGGRE0_CNOC_AHB_CLK 203 +#define GCC_SMMU_AGGRE0_AXI_CLK 204 +#define GCC_SMMU_AGGRE0_AHB_CLK 205 +#define GCC_AGGRE2_UFS_AXI_CLK 206 +#define GCC_AGGRE2_USB3_AXI_CLK 207 +#define GCC_QSPI_AHB_CLK 208 +#define GCC_QSPI_SER_CLK 209 +#define GCC_USB3_CLKREF_CLK 210 +#define GCC_HDMI_CLKREF_CLK 211 +#define GCC_UFS_CLKREF_CLK 212 +#define GCC_PCIE_CLKREF_CLK 213 +#define GCC_RX2_USB2_CLKREF_CLK 214 +#define GCC_RX1_USB2_CLKREF_CLK 215 +#define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CLK 216 +#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 217 +#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 218 +#define GCC_EDP_CLKREF_CLK 219 +#define GCC_MSS_CFG_AHB_CLK 220 +#define GCC_MSS_Q6_BIMC_AXI_CLK 221 +#define GCC_MSS_SNOC_AXI_CLK 222 +#define GCC_MSS_MNOC_BIMC_AXI_CLK 223 +#define GCC_DCC_AHB_CLK 224 +#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 225 +#define GCC_MMSS_GPLL0_DIV_CLK 226 +#define GPLL0_OUT_MSSCC_CLK 227 + +/* Block resets */ +#define GCC_SYSTEM_NOC_BCR 0 +#define GCC_CONFIG_NOC_BCR 1 +#define GCC_PERIPH_NOC_BCR 2 +#define GCC_IMEM_BCR 3 +#define GCC_MMSS_BCR 4 +#define GCC_PIMEM_BCR 5 +#define GCC_QDSS_BCR 6 +#define GCC_USB_30_BCR 7 +#define GCC_USB_20_BCR 8 +#define GCC_QUSB2PHY_PRIM_BCR 9 +#define GCC_QUSB2PHY_SEC_BCR 10 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 +#define GCC_SDCC1_BCR 12 +#define GCC_SDCC2_BCR 13 +#define GCC_SDCC3_BCR 14 +#define GCC_SDCC4_BCR 15 +#define GCC_BLSP1_BCR 16 +#define GCC_BLSP1_QUP1_BCR 17 +#define GCC_BLSP1_UART1_BCR 18 +#define GCC_BLSP1_QUP2_BCR 19 +#define GCC_BLSP1_UART2_BCR 20 +#define GCC_BLSP1_QUP3_BCR 21 +#define GCC_BLSP1_UART3_BCR 22 +#define GCC_BLSP1_QUP4_BCR 23 +#define GCC_BLSP1_UART4_BCR 24 +#define GCC_BLSP1_QUP5_BCR 25 +#define GCC_BLSP1_UART5_BCR 26 +#define GCC_BLSP1_QUP6_BCR 27 +#define GCC_BLSP1_UART6_BCR 28 +#define GCC_BLSP2_BCR 29 +#define GCC_BLSP2_QUP1_BCR 30 +#define GCC_BLSP2_UART1_BCR 31 +#define GCC_BLSP2_QUP2_BCR 32 +#define GCC_BLSP2_UART2_BCR 33 +#define GCC_BLSP2_QUP3_BCR 34 +#define GCC_BLSP2_UART3_BCR 35 +#define GCC_BLSP2_QUP4_BCR 36 +#define GCC_BLSP2_UART4_BCR 37 +#define GCC_BLSP2_QUP5_BCR 38 +#define GCC_BLSP2_UART5_BCR 39 +#define GCC_BLSP2_QUP6_BCR 40 +#define GCC_BLSP2_UART6_BCR 41 +#define GCC_PDM_BCR 42 +#define GCC_PRNG_BCR 43 +#define GCC_TSIF_BCR 44 +#define GCC_TCSR_BCR 45 +#define GCC_BOOT_ROM_BCR 46 +#define GCC_MSG_RAM_BCR 47 +#define GCC_TLMM_BCR 48 +#define GCC_MPM_BCR 49 +#define GCC_SEC_CTRL_BCR 50 +#define GCC_SPMI_BCR 51 +#define GCC_SPDM_BCR 52 +#define GCC_CE1_BCR 53 +#define GCC_BIMC_BCR 54 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 55 +#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 +#define GCC_SNOC_BUS_TIMEOUT1_BCR 57 +#define GCC_SNOC_BUS_TIMEOUT3_BCR 58 +#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 +#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 +#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 +#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 +#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 +#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 +#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 +#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 +#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 +#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 +#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 +#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 +#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 +#define GCC_CNOC_BUS_TIMEOUT7_BCR 72 +#define GCC_CNOC_BUS_TIMEOUT8_BCR 73 +#define GCC_CNOC_BUS_TIMEOUT9_BCR 74 +#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 +#define GCC_APB2JTAG_BCR 76 +#define GCC_RBCPR_CX_BCR 77 +#define GCC_RBCPR_MX_BCR 78 +#define GCC_PCIE_0_BCR 79 +#define GCC_PCIE_0_PHY_BCR 80 +#define GCC_PCIE_1_BCR 81 +#define GCC_PCIE_1_PHY_BCR 82 +#define GCC_PCIE_2_BCR 83 +#define GCC_PCIE_2_PHY_BCR 84 +#define GCC_PCIE_PHY_BCR 85 +#define GCC_DCD_BCR 86 +#define GCC_OBT_ODT_BCR 87 +#define GCC_UFS_BCR 88 +#define GCC_SSC_BCR 89 +#define GCC_VS_BCR 90 +#define GCC_AGGRE0_NOC_BCR 91 +#define GCC_AGGRE1_NOC_BCR 92 +#define GCC_AGGRE2_NOC_BCR 93 +#define GCC_DCC_BCR 94 +#define GCC_IPA_BCR 95 +#define GCC_QSPI_BCR 96 +#define GCC_SKL_BCR 97 +#define GCC_MSMPU_BCR 98 +#define GCC_MSS_Q6_BCR 99 +#define GCC_QREFS_VBG_CAL_BCR 100 +#define GCC_USB3_PHY_BCR 101 +#define GCC_USB3PHY_PHY_BCR 102 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 103 +#define GCC_PCIE_PHY_COM_BCR 104 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h new file mode 100644 index 000000000000..b622a662daa8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H +#define _DT_BINDINGS_CLK_MSM_GCC_660_H + +/* Hardware/Dummy/Voter clocks */ +#define GCC_XO 0 +#define GCC_GPLL0_EARLY_DIV 1 +#define GCC_GPLL1_EARLY_DIV 2 +#define GCC_CE1_AHB_M_CLK 3 +#define GCC_CE1_AXI_M_CLK 4 + +/* RCGs and Branches */ +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 10 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 11 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 12 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 13 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 14 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 15 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 16 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 17 +#define BLSP1_UART1_APPS_CLK_SRC 18 +#define BLSP1_UART2_APPS_CLK_SRC 19 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 20 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 21 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 22 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 23 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 24 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 25 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 26 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 27 +#define BLSP2_UART1_APPS_CLK_SRC 28 +#define BLSP2_UART2_APPS_CLK_SRC 29 +#define GCC_AGGRE2_UFS_AXI_CLK 30 +#define GCC_AGGRE2_USB3_AXI_CLK 31 +#define GCC_BIMC_GFX_CLK 32 +#define GCC_BIMC_HMSS_AXI_CLK 33 +#define GCC_BIMC_MSS_Q6_AXI_CLK 34 +#define GCC_BLSP1_AHB_CLK 35 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 36 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 37 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 38 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 39 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 40 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 41 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 42 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 43 +#define GCC_BLSP1_UART1_APPS_CLK 44 +#define GCC_BLSP1_UART2_APPS_CLK 45 +#define GCC_BLSP2_AHB_CLK 46 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 47 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 48 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 49 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 50 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 51 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 52 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 53 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 54 +#define GCC_BLSP2_UART1_APPS_CLK 55 +#define GCC_BLSP2_UART2_APPS_CLK 56 +#define GCC_BOOT_ROM_AHB_CLK 57 +#define GCC_CFG_NOC_USB2_AXI_CLK 58 +#define GCC_CFG_NOC_USB3_AXI_CLK 59 +#define GCC_DCC_AHB_CLK 60 +#define GCC_GP1_CLK 61 +#define GCC_GP2_CLK 62 +#define GCC_GP3_CLK 63 +#define GCC_GPU_BIMC_GFX_CLK 64 +#define GCC_GPU_CFG_AHB_CLK 66 +#define GCC_GPU_GPLL0_CLK 67 +#define GCC_GPU_GPLL0_DIV_CLK 68 +#define GCC_HMSS_DVM_BUS_CLK 71 +#define GCC_HMSS_RBCPR_CLK 72 +#define GCC_MMSS_GPLL0_CLK 73 +#define GCC_MMSS_GPLL0_DIV_CLK 74 +#define GCC_MMSS_NOC_CFG_AHB_CLK 75 +#define GCC_MMSS_SYS_NOC_AXI_CLK 76 +#define GCC_MSS_CFG_AHB_CLK 77 +#define GCC_MSS_GPLL0_DIV_CLK 78 +#define GCC_MSS_MNOC_BIMC_AXI_CLK 79 +#define GCC_MSS_Q6_BIMC_AXI_CLK 80 +#define GCC_MSS_SNOC_AXI_CLK 81 +#define GCC_PDM2_CLK 82 +#define GCC_PDM_AHB_CLK 83 +#define GCC_PRNG_AHB_CLK 84 +#define GCC_QSPI_AHB_CLK 85 +#define GCC_QSPI_SER_CLK 86 +#define GCC_RX0_USB2_CLKREF_CLK 87 +#define GCC_RX1_USB2_CLKREF_CLK 88 +#define GCC_SDCC1_AHB_CLK 90 +#define GCC_SDCC1_APPS_CLK 91 +#define GCC_SDCC1_ICE_CORE_CLK 92 +#define GCC_SDCC2_AHB_CLK 93 +#define GCC_SDCC2_APPS_CLK 94 +#define GCC_UFS_AHB_CLK 95 +#define GCC_UFS_AXI_CLK 96 +#define GCC_UFS_CLKREF_CLK 97 +#define GCC_UFS_ICE_CORE_CLK 98 +#define GCC_UFS_PHY_AUX_CLK 99 +#define GCC_UFS_RX_SYMBOL_0_CLK 100 +#define GCC_UFS_RX_SYMBOL_1_CLK 101 +#define GCC_UFS_TX_SYMBOL_0_CLK 102 +#define GCC_UFS_UNIPRO_CORE_CLK 103 +#define GCC_USB20_MASTER_CLK 104 +#define GCC_USB20_MOCK_UTMI_CLK 105 +#define GCC_USB20_SLEEP_CLK 106 +#define GCC_USB30_MASTER_CLK 107 +#define GCC_USB30_MOCK_UTMI_CLK 108 +#define GCC_USB30_SLEEP_CLK 109 +#define GCC_USB3_CLKREF_CLK 110 +#define GCC_USB3_PHY_AUX_CLK 111 +#define GCC_USB3_PHY_PIPE_CLK 112 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 113 +#define GP1_CLK_SRC 114 +#define GP2_CLK_SRC 115 +#define GP3_CLK_SRC 116 +#define GPLL0 117 +#define GPLL0_OUT_AUX 118 +#define GPLL0_OUT_AUX2 119 +#define GPLL0_OUT_EARLY 120 +#define GPLL0_OUT_MAIN 121 +#define GPLL0_AO 122 +#define GPLL1 123 +#define GPLL1_OUT_AUX 124 +#define GPLL1_OUT_AUX2 125 +#define GPLL1_OUT_EARLY 126 +#define GPLL1_OUT_MAIN 127 +#define GPLL1_OUT_TEST 128 +#define GPLL2 129 +#define GPLL2_OUT_AUX 130 +#define GPLL2_OUT_AUX2 131 +#define GPLL2_OUT_EARLY 132 +#define GPLL2_OUT_MAIN 133 +#define GPLL2_OUT_TEST 134 +#define GPLL3 135 +#define GPLL3_OUT_AUX 136 +#define GPLL3_OUT_AUX2 137 +#define GPLL3_OUT_EARLY 138 +#define GPLL3_OUT_MAIN 139 +#define GPLL3_OUT_TEST 140 +#define GPLL4 141 +#define GPLL4_OUT_AUX 142 +#define GPLL4_OUT_AUX2 143 +#define GPLL4_OUT_EARLY 144 +#define GPLL4_OUT_MAIN 145 +#define GPLL4_OUT_TEST 146 +#define GPLL5 147 +#define GPLL5_OUT_AUX 148 +#define GPLL5_OUT_AUX2 149 +#define GPLL5_OUT_EARLY 150 +#define GPLL5_OUT_MAIN 151 +#define GPLL5_OUT_TEST 152 +#define GPLL6 153 +#define GPLL6_OUT_AUX 154 +#define GPLL6_OUT_AUX2 155 +#define GPLL6_OUT_EARLY 156 +#define GPLL6_OUT_MAIN 157 +#define GPLL6_OUT_TEST 158 +#define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 159 +#define HMSS_GPLL0_CLK_SRC 161 +#define HMSS_GPLL4_CLK_SRC 162 +#define HMSS_RBCPR_CLK_SRC 163 +#define PDM2_CLK_SRC 164 +#define QSPI_SER_CLK_SRC 165 +#define SDCC1_APPS_CLK_SRC 166 +#define SDCC1_ICE_CORE_CLK_SRC 167 +#define SDCC2_APPS_CLK_SRC 168 +#define UFS_AXI_CLK_SRC 169 +#define UFS_ICE_CORE_CLK_SRC 170 +#define UFS_PHY_AUX_CLK_SRC 171 +#define UFS_UNIPRO_CORE_CLK_SRC 172 +#define USB20_MASTER_CLK_SRC 173 +#define USB20_MOCK_UTMI_CLK_SRC 174 +#define USB30_MASTER_CLK_SRC 175 +#define USB30_MOCK_UTMI_CLK_SRC 176 +#define USB3_PHY_AUX_CLK_SRC 177 +#define GPLL0_OUT_MSSCC 178 +#define GCC_UFS_AXI_HW_CTL_CLK 179 +#define GCC_UFS_ICE_CORE_HW_CTL_CLK 180 +#define GCC_UFS_PHY_AUX_HW_CTL_CLK 181 +#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 182 +#define HLOS1_VOTE_TURING_ADSP_SMMU_CLK 183 +#define HLOS2_VOTE_TURING_ADSP_SMMU_CLK 184 + +/* Block resets */ +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_UFS_BCR 2 +#define GCC_USB3_DP_PHY_BCR 3 +#define GCC_USB3_PHY_BCR 4 +#define GCC_USB3PHY_PHY_BCR 5 +#define GCC_USB_20_BCR 6 +#define GCC_USB_30_BCR 7 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpu-sdm660.h b/include/dt-bindings/clock/qcom,gpu-sdm660.h new file mode 100644 index 000000000000..fd5328c056b8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpu-sdm660.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GPU_660_H +#define _DT_BINDINGS_CLK_MSM_GPU_660_H + +#define GPU_PLL0_PLL 0 +#define GPU_PLL0_PLL_OUT_AUX 1 +#define GPU_PLL0_PLL_OUT_AUX2 2 +#define GPU_PLL0_PLL_OUT_EARLY 3 +#define GPU_PLL0_PLL_OUT_MAIN 4 +#define GPU_PLL0_PLL_OUT_TEST 5 +#define GPU_PLL1_PLL 6 +#define GPU_PLL1_PLL_OUT_AUX 7 +#define GPU_PLL1_PLL_OUT_AUX2 8 +#define GPU_PLL1_PLL_OUT_EARLY 9 +#define GPU_PLL1_PLL_OUT_MAIN 10 +#define GPU_PLL1_PLL_OUT_TEST 11 +#define GFX3D_CLK_SRC 12 +#define GPUCC_GFX3D_CLK 13 +#define GPUCC_RBBMTIMER_CLK 14 +#define RBBMTIMER_CLK_SRC 15 +#define GPUCC_CXO_CLK 16 + +/* RBCPR GPUCC clocks */ +#define RBCPR_CLK_SRC 0 +#define GPUCC_RBCPR_CLK 1 + +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#define GPUCC_GPU_CX_BCR 0 +#define GPUCC_GPU_GX_BCR 1 +#define GPUCC_RBCPR_BCR 2 +#define GPUCC_SPDM_BCR 3 + +#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h new file mode 100644 index 000000000000..436badbaad7d --- /dev/null +++ b/include/dt-bindings/clock/qcom,mmcc-msm8996.h @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H +#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H + +/* Hardware/Dummy/Voter clocks */ +#define GPLL0_DIV 0 +#define MDSS_MDP_VOTE_CLK 1 +#define MDSS_ROTATOR_VOTE_CLK 2 + +/* RCG and Branches */ +#define MMPLL0_EARLY 10 +#define MMPLL0_PLL 11 +#define MMPLL1_EARLY 12 +#define MMPLL1_PLL 13 +#define MMPLL2_EARLY 14 +#define MMPLL2_PLL 15 +#define MMPLL3_EARLY 16 +#define MMPLL3_PLL 17 +#define MMPLL4_EARLY 18 +#define MMPLL4_PLL 19 +#define MMPLL5_EARLY 20 +#define MMPLL5_PLL 21 +#define MMPLL8_EARLY 22 +#define MMPLL8_PLL 23 +#define MMPLL9_EARLY 24 +#define MMPLL9_PLL 25 +#define AHB_CLK_SRC 26 +#define MAXI_CLK_SRC 27 +#define RBCPR_CLK_SRC 28 +#define VIDEO_CORE_CLK_SRC 29 +#define VIDEO_SUBCORE0_CLK_SRC 30 +#define VIDEO_SUBCORE1_CLK_SRC 31 +#define PCLK0_CLK_SRC 32 +#define PCLK1_CLK_SRC 33 +#define MDP_CLK_SRC 34 +#define EXTPCLK_CLK_SRC 35 +#define VSYNC_CLK_SRC 36 +#define HDMI_CLK_SRC 37 +#define BYTE0_CLK_SRC 38 +#define BYTE1_CLK_SRC 39 +#define ESC0_CLK_SRC 40 +#define ESC1_CLK_SRC 41 +#define CAMSS_GP0_CLK_SRC 42 +#define CAMSS_GP1_CLK_SRC 43 +#define MCLK0_CLK_SRC 44 +#define MCLK1_CLK_SRC 45 +#define MCLK2_CLK_SRC 46 +#define MCLK3_CLK_SRC 47 +#define CCI_CLK_SRC 48 +#define CSI0PHYTIMER_CLK_SRC 49 +#define CSI1PHYTIMER_CLK_SRC 50 +#define CSI2PHYTIMER_CLK_SRC 51 +#define CSIPHY0_3P_CLK_SRC 52 +#define CSIPHY1_3P_CLK_SRC 53 +#define CSIPHY2_3P_CLK_SRC 54 +#define JPEG0_CLK_SRC 55 +#define JPEG2_CLK_SRC 56 +#define JPEG_DMA_CLK_SRC 57 +#define VFE0_CLK_SRC 58 +#define VFE1_CLK_SRC 59 +#define CPP_CLK_SRC 60 +#define CSI0_CLK_SRC 61 +#define CSI1_CLK_SRC 62 +#define CSI2_CLK_SRC 63 +#define CSI3_CLK_SRC 64 +#define FD_CORE_CLK_SRC 65 +#define MMSS_MMAGIC_AHB_CLK 66 +#define MMSS_MMAGIC_CFG_AHB_CLK 67 +#define MMSS_MISC_AHB_CLK 68 +#define MMSS_MISC_CXO_CLK 69 +#define MMSS_MMAGIC_MAXI_CLK 70 +#define MMAGIC_CAMSS_AXI_CLK 71 +#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 72 +#define SMMU_VFE_AHB_CLK 73 +#define SMMU_VFE_AXI_CLK 74 +#define SMMU_CPP_AHB_CLK 75 +#define SMMU_CPP_AXI_CLK 76 +#define SMMU_JPEG_AHB_CLK 77 +#define SMMU_JPEG_AXI_CLK 78 +#define MMAGIC_MDSS_AXI_CLK 79 +#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 80 +#define SMMU_ROT_AHB_CLK 81 +#define SMMU_ROT_AXI_CLK 82 +#define SMMU_MDP_AHB_CLK 83 +#define SMMU_MDP_AXI_CLK 84 +#define MMAGIC_VIDEO_AXI_CLK 85 +#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 86 +#define SMMU_VIDEO_AHB_CLK 87 +#define SMMU_VIDEO_AXI_CLK 88 +#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 89 +#define VMEM_MAXI_CLK 90 +#define VMEM_AHB_CLK 91 +#define MMSS_RBCPR_CLK 92 +#define MMSS_RBCPR_AHB_CLK 93 +#define VIDEO_CORE_CLK 94 +#define VIDEO_AXI_CLK 95 +#define VIDEO_MAXI_CLK 96 +#define VIDEO_AHB_CLK 97 +#define VIDEO_SUBCORE0_CLK 98 +#define VIDEO_SUBCORE1_CLK 99 +#define MDSS_AHB_CLK 100 +#define MDSS_HDMI_AHB_CLK 101 +#define MDSS_AXI_CLK 102 +#define MDSS_PCLK0_CLK 103 +#define MDSS_PCLK1_CLK 104 +#define MDSS_MDP_CLK 105 +#define MDSS_EXTPCLK_CLK 106 +#define MDSS_VSYNC_CLK 107 +#define MDSS_HDMI_CLK 108 +#define MDSS_BYTE0_CLK 109 +#define MDSS_BYTE1_CLK 110 +#define MDSS_ESC0_CLK 111 +#define MDSS_ESC1_CLK 112 +#define CAMSS_TOP_AHB_CLK 113 +#define CAMSS_AHB_CLK 114 +#define CAMSS_MICRO_AHB_CLK 115 +#define CAMSS_GP0_CLK 116 +#define CAMSS_GP1_CLK 117 +#define CAMSS_MCLK0_CLK 118 +#define CAMSS_MCLK1_CLK 119 +#define CAMSS_MCLK2_CLK 120 +#define CAMSS_MCLK3_CLK 121 +#define CAMSS_CCI_CLK 122 +#define CAMSS_CCI_AHB_CLK 123 +#define CAMSS_CSI0PHYTIMER_CLK 124 +#define CAMSS_CSI1PHYTIMER_CLK 125 +#define CAMSS_CSI2PHYTIMER_CLK 126 +#define CAMSS_CSIPHY0_3P_CLK 127 +#define CAMSS_CSIPHY1_3P_CLK 128 +#define CAMSS_CSIPHY2_3P_CLK 129 +#define CAMSS_JPEG0_CLK 130 +#define CAMSS_JPEG2_CLK 131 +#define CAMSS_JPEG_DMA_CLK 132 +#define CAMSS_JPEG_AHB_CLK 133 +#define CAMSS_JPEG_AXI_CLK 134 +#define CAMSS_VFE_AHB_CLK 135 +#define CAMSS_VFE_AXI_CLK 136 +#define CAMSS_VFE0_CLK 137 +#define CAMSS_VFE0_STREAM_CLK 138 +#define CAMSS_VFE0_AHB_CLK 139 +#define CAMSS_VFE1_CLK 140 +#define CAMSS_VFE1_STREAM_CLK 141 +#define CAMSS_VFE1_AHB_CLK 142 +#define CAMSS_CSI_VFE0_CLK 143 +#define CAMSS_CSI_VFE1_CLK 144 +#define CAMSS_CPP_VBIF_AHB_CLK 145 +#define CAMSS_CPP_AXI_CLK 146 +#define CAMSS_CPP_CLK 147 +#define CAMSS_CPP_AHB_CLK 148 +#define CAMSS_CSI0_CLK 149 +#define CAMSS_CSI0_AHB_CLK 150 +#define CAMSS_CSI0PHY_CLK 151 +#define CAMSS_CSI0RDI_CLK 152 +#define CAMSS_CSI0PIX_CLK 153 +#define CAMSS_CSI1_CLK 154 +#define CAMSS_CSI1_AHB_CLK 155 +#define CAMSS_CSI1PHY_CLK 156 +#define CAMSS_CSI1RDI_CLK 157 +#define CAMSS_CSI1PIX_CLK 158 +#define CAMSS_CSI2_CLK 159 +#define CAMSS_CSI2_AHB_CLK 160 +#define CAMSS_CSI2PHY_CLK 161 +#define CAMSS_CSI2RDI_CLK 162 +#define CAMSS_CSI2PIX_CLK 163 +#define CAMSS_CSI3_CLK 164 +#define CAMSS_CSI3_AHB_CLK 165 +#define CAMSS_CSI3PHY_CLK 166 +#define CAMSS_CSI3RDI_CLK 167 +#define CAMSS_CSI3PIX_CLK 168 +#define CAMSS_ISPIF_AHB_CLK 169 +#define FD_CORE_CLK 170 +#define FD_CORE_UAR_CLK 171 +#define FD_AHB_CLK 172 + +/* Block resets */ +#define MMAGICAHB_BCR 0 +#define MMAGIC_CFG_BCR 1 +#define MISC_BCR 2 +#define BTO_BCR 3 +#define MMAGICAXI_BCR 4 +#define MMAGICMAXI_BCR 5 +#define DSA_BCR 6 +#define MMAGIC_CAMSS_BCR 7 +#define THROTTLE_CAMSS_BCR 8 +#define SMMU_VFE_BCR 9 +#define SMMU_CPP_BCR 10 +#define SMMU_JPEG_BCR 11 +#define MMAGIC_MDSS_BCR 12 +#define THROTTLE_MDSS_BCR 13 +#define SMMU_ROT_BCR 14 +#define SMMU_MDP_BCR 15 +#define MMAGIC_VIDEO_BCR 16 +#define THROTTLE_VIDEO_BCR 17 +#define SMMU_VIDEO_BCR 18 +#define MMAGIC_BIMC_BCR 19 +#define VMEM_BCR 20 +#define MMSS_RBCPR_BCR 21 +#define VIDEO_BCR 22 +#define MDSS_BCR 23 +#define CAMSS_TOP_BCR 24 +#define CAMSS_AHB_BCR 25 +#define CAMSS_MICRO_BCR 26 +#define CAMSS_CCI_BCR 27 +#define CAMSS_PHY0_BCR 28 +#define CAMSS_PHY1_BCR 29 +#define CAMSS_PHY2_BCR 30 +#define CAMSS_CSIPHY0_3P_BCR 31 +#define CAMSS_CSIPHY1_3P_BCR 32 +#define CAMSS_CSIPHY2_3P_BCR 33 +#define CAMSS_JPEG_BCR 34 +#define CAMSS_VFE_BCR 35 +#define CAMSS_VFE0_BCR 36 +#define CAMSS_VFE1_BCR 37 +#define CAMSS_CSI_VFE0_BCR 38 +#define CAMSS_CSI_VFE1_BCR 39 +#define CAMSS_CPP_TOP_BCR 40 +#define CAMSS_CPP_BCR 41 +#define CAMSS_CSI0_BCR 42 +#define CAMSS_CSI0RDI_BCR 43 +#define CAMSS_CSI0PIX_BCR 44 +#define CAMSS_CSI1_BCR 45 +#define CAMSS_CSI1RDI_BCR 46 +#define CAMSS_CSI1PIX_BCR 47 +#define CAMSS_CSI2_BCR 48 +#define CAMSS_CSI2RDI_BCR 49 +#define CAMSS_CSI2PIX_BCR 50 +#define CAMSS_CSI3_BCR 51 +#define CAMSS_CSI3RDI_BCR 52 +#define CAMSS_CSI3PIX_BCR 53 +#define CAMSS_ISPIF_BCR 54 +#define FD_BCR 55 +#define MMSS_SPDM_RM_BCR 56 + +/* Indexes for GDSCs */ +#define MMAGIC_VIDEO_GDSC 0 +#define MMAGIC_MDSS_GDSC 1 +#define MMAGIC_CAMSS_GDSC 2 +#define GPU_GDSC 3 +#define VENUS_GDSC 4 +#define VENUS_CORE0_GDSC 5 +#define VENUS_CORE1_GDSC 6 +#define CAMSS_GDSC 7 +#define VFE0_GDSC 8 +#define VFE1_GDSC 9 +#define JPEG_GDSC 10 +#define CPP_GDSC 11 +#define FD_GDSC 12 +#define MDSS_GDSC 13 +#define GPU_GX_GDSC 14 +#define MMAGIC_BIMC_GDSC 15 + +#endif diff --git a/include/dt-bindings/clock/qcom,mmcc-sdm660.h b/include/dt-bindings/clock/qcom,mmcc-sdm660.h new file mode 100644 index 000000000000..68657c5d9761 --- /dev/null +++ b/include/dt-bindings/clock/qcom,mmcc-sdm660.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H +#define _DT_BINDINGS_CLK_MSM_MMCC_660_H + +#define MMSS_CAMSS_JPEG0_VOTE_CLK 0 +#define MMSS_CAMSS_JPEG0_DMA_VOTE_CLK 1 + +#define AHB_CLK_SRC 5 +#define BYTE0_CLK_SRC 6 +#define BYTE1_CLK_SRC 7 +#define CAMSS_GP0_CLK_SRC 8 +#define CAMSS_GP1_CLK_SRC 9 +#define CCI_CLK_SRC 10 +#define CPP_CLK_SRC 11 +#define CSI0_CLK_SRC 12 +#define CSI0PHYTIMER_CLK_SRC 13 +#define CSI1_CLK_SRC 14 +#define CSI1PHYTIMER_CLK_SRC 15 +#define CSI2_CLK_SRC 16 +#define CSI2PHYTIMER_CLK_SRC 17 +#define CSI3_CLK_SRC 18 +#define CSIPHY_CLK_SRC 19 +#define DP_AUX_CLK_SRC 20 +#define DP_CRYPTO_CLK_SRC 21 +#define DP_GTC_CLK_SRC 22 +#define DP_LINK_CLK_SRC 23 +#define DP_PIXEL_CLK_SRC 24 +#define ESC0_CLK_SRC 25 +#define ESC1_CLK_SRC 26 +#define JPEG0_CLK_SRC 27 +#define MCLK0_CLK_SRC 28 +#define MCLK1_CLK_SRC 29 +#define MCLK2_CLK_SRC 30 +#define MCLK3_CLK_SRC 31 +#define MDP_CLK_SRC 32 +#define MMPLL0_PLL 33 +#define MMPLL0_PLL_OUT_AUX 34 +#define MMPLL0_PLL_OUT_AUX2 35 +#define MMPLL0_PLL_OUT_EARLY 36 +#define MMPLL0_PLL_OUT_MAIN 37 +#define MMPLL0_PLL_OUT_TEST 38 +#define MMPLL10_PLL 39 +#define MMPLL10_PLL_OUT_AUX 40 +#define MMPLL10_PLL_OUT_AUX2 41 +#define MMPLL10_PLL_OUT_EARLY 42 +#define MMPLL10_PLL_OUT_MAIN 43 +#define MMPLL10_PLL_OUT_TEST 44 +#define MMPLL1_PLL 45 +#define MMPLL1_PLL_OUT_AUX 46 +#define MMPLL1_PLL_OUT_AUX2 47 +#define MMPLL1_PLL_OUT_EARLY 48 +#define MMPLL1_PLL_OUT_MAIN 49 +#define MMPLL1_PLL_OUT_TEST 50 +#define MMPLL3_PLL 51 +#define MMPLL3_PLL_OUT_AUX 52 +#define MMPLL3_PLL_OUT_AUX2 53 +#define MMPLL3_PLL_OUT_EARLY 54 +#define MMPLL3_PLL_OUT_MAIN 55 +#define MMPLL3_PLL_OUT_TEST 56 +#define MMPLL4_PLL 57 +#define MMPLL4_PLL_OUT_AUX 58 +#define MMPLL4_PLL_OUT_AUX2 59 +#define MMPLL4_PLL_OUT_EARLY 60 +#define MMPLL4_PLL_OUT_MAIN 61 +#define MMPLL4_PLL_OUT_TEST 62 +#define MMPLL5_PLL 63 +#define MMPLL5_PLL_OUT_AUX 64 +#define MMPLL5_PLL_OUT_AUX2 65 +#define MMPLL5_PLL_OUT_EARLY 66 +#define MMPLL5_PLL_OUT_MAIN 67 +#define MMPLL5_PLL_OUT_TEST 68 +#define MMPLL6_PLL 69 +#define MMPLL6_PLL_OUT_AUX 70 +#define MMPLL6_PLL_OUT_AUX2 71 +#define MMPLL6_PLL_OUT_EARLY 72 +#define MMPLL6_PLL_OUT_MAIN 73 +#define MMPLL6_PLL_OUT_TEST 74 +#define MMPLL7_PLL 75 +#define MMPLL7_PLL_OUT_AUX 76 +#define MMPLL7_PLL_OUT_AUX2 77 +#define MMPLL7_PLL_OUT_EARLY 78 +#define MMPLL7_PLL_OUT_MAIN 79 +#define MMPLL7_PLL_OUT_TEST 80 +#define MMPLL8_PLL 81 +#define MMPLL8_PLL_OUT_AUX 82 +#define MMPLL8_PLL_OUT_AUX2 83 +#define MMPLL8_PLL_OUT_EARLY 84 +#define MMPLL8_PLL_OUT_MAIN 85 +#define MMPLL8_PLL_OUT_TEST 86 +#define MMSS_BIMC_SMMU_AHB_CLK 87 +#define MMSS_BIMC_SMMU_AXI_CLK 88 +#define MMSS_CAMSS_AHB_CLK 89 +#define MMSS_CAMSS_CCI_AHB_CLK 90 +#define MMSS_CAMSS_CCI_CLK 91 +#define MMSS_CAMSS_CPHY_CSID0_CLK 92 +#define MMSS_CAMSS_CPHY_CSID1_CLK 93 +#define MMSS_CAMSS_CPHY_CSID2_CLK 94 +#define MMSS_CAMSS_CPHY_CSID3_CLK 95 +#define MMSS_CAMSS_CPP_AHB_CLK 96 +#define MMSS_CAMSS_CPP_AXI_CLK 97 +#define MMSS_CAMSS_CPP_CLK 98 +#define MMSS_CAMSS_CPP_VBIF_AHB_CLK 99 +#define MMSS_CAMSS_CSI0_AHB_CLK 100 +#define MMSS_CAMSS_CSI0_CLK 101 +#define MMSS_CAMSS_CSI0PHYTIMER_CLK 102 +#define MMSS_CAMSS_CSI0PIX_CLK 103 +#define MMSS_CAMSS_CSI0RDI_CLK 104 +#define MMSS_CAMSS_CSI1_AHB_CLK 105 +#define MMSS_CAMSS_CSI1_CLK 106 +#define MMSS_CAMSS_CSI1PHYTIMER_CLK 107 +#define MMSS_CAMSS_CSI1PIX_CLK 108 +#define MMSS_CAMSS_CSI1RDI_CLK 109 +#define MMSS_CAMSS_CSI2_AHB_CLK 110 +#define MMSS_CAMSS_CSI2_CLK 111 +#define MMSS_CAMSS_CSI2PHYTIMER_CLK 112 +#define MMSS_CAMSS_CSI2PIX_CLK 113 +#define MMSS_CAMSS_CSI2RDI_CLK 114 +#define MMSS_CAMSS_CSI3_AHB_CLK 115 +#define MMSS_CAMSS_CSI3_CLK 116 +#define MMSS_CAMSS_CSI3PIX_CLK 117 +#define MMSS_CAMSS_CSI3RDI_CLK 118 +#define MMSS_CAMSS_CSI_VFE0_CLK 119 +#define MMSS_CAMSS_CSI_VFE1_CLK 120 +#define MMSS_CAMSS_CSIPHY0_CLK 121 +#define MMSS_CAMSS_CSIPHY1_CLK 122 +#define MMSS_CAMSS_CSIPHY2_CLK 123 +#define MMSS_CAMSS_GP0_CLK 124 +#define MMSS_CAMSS_GP1_CLK 125 +#define MMSS_CAMSS_ISPIF_AHB_CLK 126 +#define MMSS_CAMSS_JPEG0_CLK 127 +#define MMSS_CAMSS_JPEG_AHB_CLK 128 +#define MMSS_CAMSS_JPEG_AXI_CLK 129 +#define MMSS_CAMSS_MCLK0_CLK 130 +#define MMSS_CAMSS_MCLK1_CLK 131 +#define MMSS_CAMSS_MCLK2_CLK 132 +#define MMSS_CAMSS_MCLK3_CLK 133 +#define MMSS_CAMSS_MICRO_AHB_CLK 134 +#define MMSS_CAMSS_TOP_AHB_CLK 135 +#define MMSS_CAMSS_VFE0_AHB_CLK 136 +#define MMSS_CAMSS_VFE0_CLK 137 +#define MMSS_CAMSS_VFE0_STREAM_CLK 138 +#define MMSS_CAMSS_VFE1_AHB_CLK 139 +#define MMSS_CAMSS_VFE1_CLK 140 +#define MMSS_CAMSS_VFE1_STREAM_CLK 141 +#define MMSS_CAMSS_VFE_VBIF_AHB_CLK 142 +#define MMSS_CAMSS_VFE_VBIF_AXI_CLK 143 +#define MMSS_CSIPHY_AHB2CRIF_CLK 144 +#define MMSS_CXO_CLK 145 +#define MMSS_MDSS_AHB_CLK 146 +#define MMSS_MDSS_AXI_CLK 147 +#define MMSS_MDSS_BYTE0_CLK 148 +#define MMSS_MDSS_BYTE0_INTF_CLK 149 +#define MMSS_MDSS_BYTE0_INTF_DIV_CLK 150 +#define MMSS_MDSS_BYTE1_CLK 151 +#define MMSS_MDSS_BYTE1_INTF_CLK 152 +#define MMSS_MDSS_DP_AUX_CLK 153 +#define MMSS_MDSS_DP_CRYPTO_CLK 154 +#define MMSS_MDSS_DP_GTC_CLK 155 +#define MMSS_MDSS_DP_LINK_CLK 156 +#define MMSS_MDSS_DP_LINK_INTF_CLK 157 +#define MMSS_MDSS_DP_PIXEL_CLK 158 +#define MMSS_MDSS_ESC0_CLK 159 +#define MMSS_MDSS_ESC1_CLK 160 +#define MMSS_MDSS_HDMI_DP_AHB_CLK 161 +#define MMSS_MDSS_MDP_CLK 162 +#define MMSS_MDSS_PCLK0_CLK 163 +#define MMSS_MDSS_PCLK1_CLK 164 +#define MMSS_MDSS_ROT_CLK 165 +#define MMSS_MDSS_VSYNC_CLK 166 +#define MMSS_MISC_AHB_CLK 167 +#define MMSS_MISC_CXO_CLK 168 +#define MMSS_MNOC_AHB_CLK 169 +#define MMSS_SNOC_DVM_AXI_CLK 170 +#define MMSS_THROTTLE_CAMSS_AHB_CLK 171 +#define MMSS_THROTTLE_CAMSS_AXI_CLK 172 +#define MMSS_THROTTLE_CAMSS_CXO_CLK 173 +#define MMSS_THROTTLE_MDSS_AHB_CLK 174 +#define MMSS_THROTTLE_MDSS_AXI_CLK 175 +#define MMSS_THROTTLE_MDSS_CXO_CLK 176 +#define MMSS_THROTTLE_VIDEO_AHB_CLK 177 +#define MMSS_THROTTLE_VIDEO_AXI_CLK 178 +#define MMSS_THROTTLE_VIDEO_CXO_CLK 179 +#define MMSS_VIDEO_AHB_CLK 180 +#define MMSS_VIDEO_AXI_CLK 181 +#define MMSS_VIDEO_CORE_CLK 182 +#define MMSS_VIDEO_SUBCORE0_CLK 183 +#define PCLK0_CLK_SRC 184 +#define PCLK1_CLK_SRC 185 +#define ROT_CLK_SRC 186 +#define VFE0_CLK_SRC 187 +#define VFE1_CLK_SRC 188 +#define VIDEO_CORE_CLK_SRC 189 +#define VSYNC_CLK_SRC 190 +#define MMSS_MDSS_BYTE1_INTF_DIV_CLK 191 + +#define BIMC_SMMU_GDSC 0 +#define CAMSS_CPP_GDSC 1 +#define CAMSS_TOP_GDSC 2 +#define CAMSS_VFE0_GDSC 3 +#define CAMSS_VFE1_GDSC 4 +#define MDSS_GDSC 5 +#define VIDEO_SUBCORE0_GDSC 6 +#define VIDEO_TOP_GDSC 7 + +#define CAMSS_MICRO_BCR 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h new file mode 100644 index 000000000000..cb5329bc9ba8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -0,0 +1,137 @@ +/* + * Copyright 2015 Linaro Limited + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H +#define _DT_BINDINGS_CLK_MSM_RPMCC_H + +/* apq8064 */ +#define RPM_PXO_CLK 0 +#define RPM_PXO_A_CLK 1 +#define RPM_CXO_CLK 2 +#define RPM_CXO_A_CLK 3 +#define RPM_APPS_FABRIC_CLK 4 +#define RPM_APPS_FABRIC_A_CLK 5 +#define RPM_CFPB_CLK 6 +#define RPM_CFPB_A_CLK 7 +#define RPM_QDSS_CLK 8 +#define RPM_QDSS_A_CLK 9 +#define RPM_DAYTONA_FABRIC_CLK 10 +#define RPM_DAYTONA_FABRIC_A_CLK 11 +#define RPM_EBI1_CLK 12 +#define RPM_EBI1_A_CLK 13 +#define RPM_MM_FABRIC_CLK 14 +#define RPM_MM_FABRIC_A_CLK 15 +#define RPM_MMFPB_CLK 16 +#define RPM_MMFPB_A_CLK 17 +#define RPM_SYS_FABRIC_CLK 18 +#define RPM_SYS_FABRIC_A_CLK 19 +#define RPM_SFPB_CLK 20 +#define RPM_SFPB_A_CLK 21 + +/* msm8916 and msm8996 */ +#define RPM_XO_CLK_SRC 0 +#define RPM_XO_A_CLK_SRC 1 +#define RPM_PCNOC_CLK 2 +#define RPM_PCNOC_A_CLK 3 +#define RPM_SNOC_CLK 4 +#define RPM_SNOC_A_CLK 5 +#define RPM_BIMC_CLK 6 +#define RPM_BIMC_A_CLK 7 +#define RPM_QDSS_CLK 8 +#define RPM_QDSS_A_CLK 9 +#define RPM_BB_CLK1 10 +#define RPM_BB_CLK1_A 11 +#define RPM_BB_CLK1_PIN 12 +#define RPM_BB_CLK1_A_PIN 13 +#define RPM_BB_CLK2 14 +#define RPM_BB_CLK2_A 15 +#define RPM_BB_CLK2_PIN 16 +#define RPM_BB_CLK2_A_PIN 17 +#define RPM_RF_CLK1 18 +#define RPM_RF_CLK1_A 19 +#define RPM_RF_CLK1_PIN 20 +#define RPM_RF_CLK1_A_PIN 21 +#define RPM_RF_CLK2 22 +#define RPM_RF_CLK2_A 23 +#define RPM_RF_CLK2_PIN 24 +#define RPM_RF_CLK2_A_PIN 25 +#define RPM_AGGR1_NOC_CLK 26 +#define RPM_AGGR1_NOC_A_CLK 27 +#define RPM_AGGR2_NOC_CLK 28 +#define RPM_AGGR2_NOC_A_CLK 29 +#define RPM_CNOC_CLK 30 +#define RPM_CNOC_A_CLK 31 +#define RPM_MMAXI_CLK 32 +#define RPM_MMAXI_A_CLK 33 +#define RPM_IPA_CLK 34 +#define RPM_IPA_A_CLK 35 +#define RPM_CE1_CLK 36 +#define RPM_CE1_A_CLK 37 +#define RPM_DIV_CLK1 38 +#define RPM_DIV_CLK1_AO 39 +#define RPM_DIV_CLK2 40 +#define RPM_DIV_CLK2_AO 41 +#define RPM_DIV_CLK3 42 +#define RPM_DIV_CLK3_AO 43 +#define RPM_LN_BB_CLK 44 +#define RPM_LN_BB_A_CLK 45 +#define RPM_LN_BB_CLK1 46 +#define RPM_LN_BB_CLK1_AO 47 +#define RPM_LN_BB_CLK1_PIN 48 +#define RPM_LN_BB_CLK1_PIN_AO 49 +#define RPM_LN_BB_CLK2 50 +#define RPM_LN_BB_CLK2_AO 51 +#define RPM_LN_BB_CLK2_PIN 52 +#define RPM_LN_BB_CLK2_PIN_AO 53 +#define RPM_LN_BB_CLK3 54 +#define RPM_LN_BB_CLK3_AO 55 +#define RPM_LN_BB_CLK3_PIN 56 +#define RPM_LN_BB_CLK3_PIN_AO 57 +#define RPM_CNOC_PERIPH_CLK 58 +#define RPM_CNOC_PERIPH_A_CLK 59 + +/* Voter clocks */ +#define MMSSNOC_AXI_CLK 60 +#define MMSSNOC_AXI_A_CLK 61 +#define MMSSNOC_GDS_CLK 62 +#define BIMC_MSMBUS_CLK 63 +#define BIMC_MSMBUS_A_CLK 64 +#define CNOC_MSMBUS_CLK 65 +#define CNOC_MSMBUS_A_CLK 66 +#define PNOC_KEEPALIVE_A_CLK 67 +#define PNOC_MSMBUS_CLK 68 +#define PNOC_MSMBUS_A_CLK 69 +#define PNOC_PM_CLK 70 +#define PNOC_SPS_CLK 71 +#define MCD_CE1_CLK 72 +#define QCEDEV_CE1_CLK 73 +#define QCRYPTO_CE1_CLK 74 +#define QSEECOM_CE1_CLK 75 +#define SCM_CE1_CLK 76 +#define SNOC_MSMBUS_CLK 77 +#define SNOC_MSMBUS_A_CLK 78 +#define CXO_DWC3_CLK 79 +#define CXO_LPM_CLK 80 +#define CXO_OTG_CLK 81 +#define CXO_PIL_LPASS_CLK 82 +#define CXO_PIL_SSC_CLK 83 +#define CXO_PIL_CDSP_CLK 84 +#define CNOC_PERIPH_KEEPALIVE_A_CLK 85 +#define MMSSNOC_A_CLK_CPU_VOTE 86 +#define AGGR2_NOC_MSMBUS_CLK 87 +#define AGGR2_NOC_MSMBUS_A_CLK 88 +#define AGGR2_NOC_SMMU_CLK 89 +#define AGGR2_NOC_USB_CLK 90 + +#endif diff --git a/include/dt-bindings/msm/msm-bus-ids.h b/include/dt-bindings/msm/msm-bus-ids.h new file mode 100644 index 000000000000..a75d304473d5 --- /dev/null +++ b/include/dt-bindings/msm/msm-bus-ids.h @@ -0,0 +1,887 @@ +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_IDS_H +#define __MSM_BUS_IDS_H + +/* Aggregation types */ +#define AGG_SCHEME_NONE 0 +#define AGG_SCHEME_LEG 1 +#define AGG_SCHEME_1 2 + +/* Topology related enums */ +#define MSM_BUS_FAB_DEFAULT 0 +#define MSM_BUS_FAB_APPSS 0 +#define MSM_BUS_FAB_SYSTEM 1024 +#define MSM_BUS_FAB_MMSS 2048 +#define MSM_BUS_FAB_SYSTEM_FPB 3072 +#define MSM_BUS_FAB_CPSS_FPB 4096 + +#define MSM_BUS_FAB_BIMC 0 +#define MSM_BUS_FAB_SYS_NOC 1024 +#define MSM_BUS_FAB_MMSS_NOC 2048 +#define MSM_BUS_FAB_OCMEM_NOC 3072 +#define MSM_BUS_FAB_PERIPH_NOC 4096 +#define MSM_BUS_FAB_CONFIG_NOC 5120 +#define MSM_BUS_FAB_OCMEM_VNOC 6144 +#define MSM_BUS_FAB_MMSS_AHB 2049 +#define MSM_BUS_FAB_A0_NOC 6145 +#define MSM_BUS_FAB_A1_NOC 6146 +#define MSM_BUS_FAB_A2_NOC 6147 +#define MSM_BUS_FAB_GNOC 6148 +#define MSM_BUS_FAB_CR_VIRT 6149 + +#define MSM_BUS_MASTER_FIRST 1 +#define MSM_BUS_MASTER_AMPSS_M0 1 +#define MSM_BUS_MASTER_AMPSS_M1 2 +#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3 +#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4 +#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5 +#define MSM_BUS_MASTER_SPS 6 +#define MSM_BUS_MASTER_ADM_PORT0 7 +#define MSM_BUS_MASTER_ADM_PORT1 8 +#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9 +#define MSM_BUS_MASTER_ADM1_PORT1 10 +#define MSM_BUS_MASTER_LPASS_PROC 11 +#define MSM_BUS_MASTER_MSS_PROCI 12 +#define MSM_BUS_MASTER_MSS_PROCD 13 +#define MSM_BUS_MASTER_MSS_MDM_PORT0 14 +#define MSM_BUS_MASTER_LPASS 15 +#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16 +#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17 +#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18 +#define MSM_BUS_MASTER_ADM1_CI 19 +#define MSM_BUS_MASTER_ADM0_CI 20 +#define MSM_BUS_MASTER_MSS_MDM_PORT1 21 +#define MSM_BUS_MASTER_MDP_PORT0 22 +#define MSM_BUS_MASTER_MDP_PORT1 23 +#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24 +#define MSM_BUS_MASTER_ROTATOR 25 +#define MSM_BUS_MASTER_GRAPHICS_3D 26 +#define MSM_BUS_MASTER_JPEG_DEC 27 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28 +#define MSM_BUS_MASTER_VFE 29 +#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE +#define MSM_BUS_MASTER_VPE 30 +#define MSM_BUS_MASTER_JPEG_ENC 31 +#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32 +#define MSM_BUS_MMSS_MASTER_APPS_FAB 33 +#define MSM_BUS_MASTER_HD_CODEC_PORT0 34 +#define MSM_BUS_MASTER_HD_CODEC_PORT1 35 +#define MSM_BUS_MASTER_SPDM 36 +#define MSM_BUS_MASTER_RPM 37 +#define MSM_BUS_MASTER_MSS 38 +#define MSM_BUS_MASTER_RIVA 39 +#define MSM_BUS_MASTER_SNOC_VMEM 40 +#define MSM_BUS_MASTER_MSS_SW_PROC 41 +#define MSM_BUS_MASTER_MSS_FW_PROC 42 +#define MSM_BUS_MASTER_HMSS 43 +#define MSM_BUS_MASTER_GSS_NAV 44 +#define MSM_BUS_MASTER_PCIE 45 +#define MSM_BUS_MASTER_SATA 46 +#define MSM_BUS_MASTER_CRYPTO 47 +#define MSM_BUS_MASTER_VIDEO_CAP 48 +#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49 +#define MSM_BUS_MASTER_VIDEO_ENC 50 +#define MSM_BUS_MASTER_VIDEO_DEC 51 +#define MSM_BUS_MASTER_LPASS_AHB 52 +#define MSM_BUS_MASTER_QDSS_BAM 53 +#define MSM_BUS_MASTER_SNOC_CFG 54 +#define MSM_BUS_MASTER_CRYPTO_CORE0 55 +#define MSM_BUS_MASTER_CRYPTO_CORE1 56 +#define MSM_BUS_MASTER_MSS_NAV 57 +#define MSM_BUS_MASTER_OCMEM_DMA 58 +#define MSM_BUS_MASTER_WCSS 59 +#define MSM_BUS_MASTER_QDSS_ETR 60 +#define MSM_BUS_MASTER_USB3 61 +#define MSM_BUS_MASTER_JPEG 62 +#define MSM_BUS_MASTER_VIDEO_P0 63 +#define MSM_BUS_MASTER_VIDEO_P1 64 +#define MSM_BUS_MASTER_MSS_PROC 65 +#define MSM_BUS_MASTER_JPEG_OCMEM 66 +#define MSM_BUS_MASTER_MDP_OCMEM 67 +#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68 +#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69 +#define MSM_BUS_MASTER_VFE_OCMEM 70 +#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71 +#define MSM_BUS_MASTER_RPM_INST 72 +#define MSM_BUS_MASTER_RPM_DATA 73 +#define MSM_BUS_MASTER_RPM_SYS 74 +#define MSM_BUS_MASTER_DEHR 75 +#define MSM_BUS_MASTER_QDSS_DAP 76 +#define MSM_BUS_MASTER_TIC 77 +#define MSM_BUS_MASTER_SDCC_1 78 +#define MSM_BUS_MASTER_SDCC_3 79 +#define MSM_BUS_MASTER_SDCC_4 80 +#define MSM_BUS_MASTER_SDCC_2 81 +#define MSM_BUS_MASTER_TSIF 82 +#define MSM_BUS_MASTER_BAM_DMA 83 +#define MSM_BUS_MASTER_BLSP_2 84 +#define MSM_BUS_MASTER_USB_HSIC 85 +#define MSM_BUS_MASTER_BLSP_1 86 +#define MSM_BUS_MASTER_USB_HS 87 +#define MSM_BUS_MASTER_PNOC_CFG 88 +#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89 +#define MSM_BUS_MASTER_IPA 90 +#define MSM_BUS_MASTER_QPIC 91 +#define MSM_BUS_MASTER_MDPE 92 +#define MSM_BUS_MASTER_USB_HS2 93 +#define MSM_BUS_MASTER_VPU 94 +#define MSM_BUS_MASTER_UFS 95 +#define MSM_BUS_MASTER_BCAST 96 +#define MSM_BUS_MASTER_CRYPTO_CORE2 97 +#define MSM_BUS_MASTER_EMAC 98 +#define MSM_BUS_MASTER_VPU_1 99 +#define MSM_BUS_MASTER_PCIE_1 100 +#define MSM_BUS_MASTER_USB3_1 101 +#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102 +#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103 +#define MSM_BUS_MASTER_TCU_0 104 +#define MSM_BUS_MASTER_TCU_1 105 +#define MSM_BUS_MASTER_CPP 106 +#define MSM_BUS_MASTER_AUDIO 107 +#define MSM_BUS_MASTER_PCIE_2 108 +#define MSM_BUS_MASTER_VFE1 109 +#define MSM_BUS_MASTER_XM_USB_HS1 110 +#define MSM_BUS_MASTER_PCNOC_BIMC_1 111 +#define MSM_BUS_MASTER_BIMC_PCNOC 112 +#define MSM_BUS_MASTER_XI_USB_HSIC 113 +#define MSM_BUS_MASTER_SGMII 114 +#define MSM_BUS_SPMI_FETCHER 115 +#define MSM_BUS_MASTER_GNOC_BIMC 116 +#define MSM_BUS_MASTER_CRVIRT_A2NOC 117 +#define MSM_BUS_MASTER_CNOC_A2NOC 118 +#define MSM_BUS_MASTER_WLAN 119 +#define MSM_BUS_MASTER_MSS_CE 120 +#define MSM_BUS_MASTER_CDSP_PROC 121 +#define MSM_BUS_MASTER_GNOC_SNOC 122 +#define MSM_BUS_MASTER_PIMEM 123 +#define MSM_BUS_MASTER_MASTER_LAST 124 + +#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB + +#define MSM_BUS_SNOC_MM_INT_0 10000 +#define MSM_BUS_SNOC_MM_INT_1 10001 +#define MSM_BUS_SNOC_MM_INT_2 10002 +#define MSM_BUS_SNOC_MM_INT_BIMC 10003 +#define MSM_BUS_SNOC_INT_0 10004 +#define MSM_BUS_SNOC_INT_1 10005 +#define MSM_BUS_SNOC_INT_BIMC 10006 +#define MSM_BUS_SNOC_BIMC_0_MAS 10007 +#define MSM_BUS_SNOC_BIMC_1_MAS 10008 +#define MSM_BUS_SNOC_QDSS_INT 10009 +#define MSM_BUS_PNOC_SNOC_MAS 10010 +#define MSM_BUS_PNOC_SNOC_SLV 10011 +#define MSM_BUS_PNOC_INT_0 10012 +#define MSM_BUS_PNOC_INT_1 10013 +#define MSM_BUS_PNOC_M_0 10014 +#define MSM_BUS_PNOC_M_1 10015 +#define MSM_BUS_BIMC_SNOC_MAS 10016 +#define MSM_BUS_BIMC_SNOC_SLV 10017 +#define MSM_BUS_PNOC_SLV_0 10018 +#define MSM_BUS_PNOC_SLV_1 10019 +#define MSM_BUS_PNOC_SLV_2 10020 +#define MSM_BUS_PNOC_SLV_3 10021 +#define MSM_BUS_PNOC_SLV_4 10022 +#define MSM_BUS_PNOC_SLV_8 10023 +#define MSM_BUS_PNOC_SLV_9 10024 +#define MSM_BUS_SNOC_BIMC_0_SLV 10025 +#define MSM_BUS_SNOC_BIMC_1_SLV 10026 +#define MSM_BUS_MNOC_BIMC_MAS 10027 +#define MSM_BUS_MNOC_BIMC_SLV 10028 +#define MSM_BUS_BIMC_MNOC_MAS 10029 +#define MSM_BUS_BIMC_MNOC_SLV 10030 +#define MSM_BUS_SNOC_BIMC_MAS 10031 +#define MSM_BUS_SNOC_BIMC_SLV 10032 +#define MSM_BUS_CNOC_SNOC_MAS 10033 +#define MSM_BUS_CNOC_SNOC_SLV 10034 +#define MSM_BUS_SNOC_CNOC_MAS 10035 +#define MSM_BUS_SNOC_CNOC_SLV 10036 +#define MSM_BUS_OVNOC_SNOC_MAS 10037 +#define MSM_BUS_OVNOC_SNOC_SLV 10038 +#define MSM_BUS_SNOC_OVNOC_MAS 10039 +#define MSM_BUS_SNOC_OVNOC_SLV 10040 +#define MSM_BUS_SNOC_PNOC_MAS 10041 +#define MSM_BUS_SNOC_PNOC_SLV 10042 +#define MSM_BUS_BIMC_INT_APPS_EBI 10043 +#define MSM_BUS_BIMC_INT_APPS_SNOC 10044 +#define MSM_BUS_SNOC_BIMC_2_MAS 10045 +#define MSM_BUS_SNOC_BIMC_2_SLV 10046 +#define MSM_BUS_PNOC_SLV_5 10047 +#define MSM_BUS_PNOC_SLV_7 10048 +#define MSM_BUS_PNOC_INT_2 10049 +#define MSM_BUS_PNOC_INT_3 10050 +#define MSM_BUS_PNOC_INT_4 10051 +#define MSM_BUS_PNOC_INT_5 10052 +#define MSM_BUS_PNOC_INT_6 10053 +#define MSM_BUS_PNOC_INT_7 10054 +#define MSM_BUS_BIMC_SNOC_1_MAS 10055 +#define MSM_BUS_BIMC_SNOC_1_SLV 10056 +#define MSM_BUS_PNOC_A1NOC_MAS 10057 +#define MSM_BUS_PNOC_A1NOC_SLV 10058 +#define MSM_BUS_CNOC_A1NOC_MAS 10059 +#define MSM_BUS_A0NOC_SNOC_MAS 10060 +#define MSM_BUS_A0NOC_SNOC_SLV 10061 +#define MSM_BUS_A1NOC_SNOC_SLV 10062 +#define MSM_BUS_A1NOC_SNOC_MAS 10063 +#define MSM_BUS_A2NOC_SNOC_MAS 10064 +#define MSM_BUS_A2NOC_SNOC_SLV 10065 +#define MSM_BUS_SNOC_INT_2 10066 +#define MSM_BUS_A0NOC_QDSS_INT 10067 +#define MSM_BUS_INT_LAST 10068 + +#define MSM_BUS_INT_TEST_ID 20000 +#define MSM_BUS_INT_TEST_LAST 20050 + +#define MSM_BUS_SLAVE_FIRST 512 +#define MSM_BUS_SLAVE_EBI_CH0 512 +#define MSM_BUS_SLAVE_EBI_CH1 513 +#define MSM_BUS_SLAVE_AMPSS_L2 514 +#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515 +#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516 +#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517 +#define MSM_BUS_SLAVE_SPS 518 +#define MSM_BUS_SLAVE_SYSTEM_IMEM 519 +#define MSM_BUS_SLAVE_AMPSS 520 +#define MSM_BUS_SLAVE_MSS 521 +#define MSM_BUS_SLAVE_LPASS 522 +#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523 +#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524 +#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525 +#define MSM_BUS_SLAVE_CORESIGHT 526 +#define MSM_BUS_SLAVE_RIVA 527 +#define MSM_BUS_SLAVE_SMI 528 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529 +#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530 +#define MSM_BUS_SLAVE_MM_IMEM 531 +#define MSM_BUS_SLAVE_CRYPTO 532 +#define MSM_BUS_SLAVE_SPDM 533 +#define MSM_BUS_SLAVE_RPM 534 +#define MSM_BUS_SLAVE_RPM_MSG_RAM 535 +#define MSM_BUS_SLAVE_MPM 536 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538 +#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540 +#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541 +#define MSM_BUS_SLAVE_GSBI1_UART 542 +#define MSM_BUS_SLAVE_GSBI2_UART 543 +#define MSM_BUS_SLAVE_GSBI3_UART 544 +#define MSM_BUS_SLAVE_GSBI4_UART 545 +#define MSM_BUS_SLAVE_GSBI5_UART 546 +#define MSM_BUS_SLAVE_GSBI6_UART 547 +#define MSM_BUS_SLAVE_GSBI7_UART 548 +#define MSM_BUS_SLAVE_GSBI8_UART 549 +#define MSM_BUS_SLAVE_GSBI9_UART 550 +#define MSM_BUS_SLAVE_GSBI10_UART 551 +#define MSM_BUS_SLAVE_GSBI11_UART 552 +#define MSM_BUS_SLAVE_GSBI12_UART 553 +#define MSM_BUS_SLAVE_GSBI1_QUP 554 +#define MSM_BUS_SLAVE_GSBI2_QUP 555 +#define MSM_BUS_SLAVE_GSBI3_QUP 556 +#define MSM_BUS_SLAVE_GSBI4_QUP 557 +#define MSM_BUS_SLAVE_GSBI5_QUP 558 +#define MSM_BUS_SLAVE_GSBI6_QUP 559 +#define MSM_BUS_SLAVE_GSBI7_QUP 560 +#define MSM_BUS_SLAVE_GSBI8_QUP 561 +#define MSM_BUS_SLAVE_GSBI9_QUP 562 +#define MSM_BUS_SLAVE_GSBI10_QUP 563 +#define MSM_BUS_SLAVE_GSBI11_QUP 564 +#define MSM_BUS_SLAVE_GSBI12_QUP 565 +#define MSM_BUS_SLAVE_EBI2_NAND 566 +#define MSM_BUS_SLAVE_EBI2_CS0 567 +#define MSM_BUS_SLAVE_EBI2_CS1 568 +#define MSM_BUS_SLAVE_EBI2_CS2 569 +#define MSM_BUS_SLAVE_EBI2_CS3 570 +#define MSM_BUS_SLAVE_EBI2_CS4 571 +#define MSM_BUS_SLAVE_EBI2_CS5 572 +#define MSM_BUS_SLAVE_USB_FS1 573 +#define MSM_BUS_SLAVE_USB_FS2 574 +#define MSM_BUS_SLAVE_TSIF 575 +#define MSM_BUS_SLAVE_MSM_TSSC 576 +#define MSM_BUS_SLAVE_MSM_PDM 577 +#define MSM_BUS_SLAVE_MSM_DIMEM 578 +#define MSM_BUS_SLAVE_MSM_TCSR 579 +#define MSM_BUS_SLAVE_MSM_PRNG 580 +#define MSM_BUS_SLAVE_GSS 581 +#define MSM_BUS_SLAVE_SATA 582 +#define MSM_BUS_SLAVE_USB3 583 +#define MSM_BUS_SLAVE_WCSS 584 +#define MSM_BUS_SLAVE_OCIMEM 585 +#define MSM_BUS_SLAVE_SNOC_OCMEM 586 +#define MSM_BUS_SLAVE_SERVICE_SNOC 587 +#define MSM_BUS_SLAVE_QDSS_STM 588 +#define MSM_BUS_SLAVE_CAMERA_CFG 589 +#define MSM_BUS_SLAVE_DISPLAY_CFG 590 +#define MSM_BUS_SLAVE_OCMEM_CFG 591 +#define MSM_BUS_SLAVE_CPR_CFG 592 +#define MSM_BUS_SLAVE_CPR_XPU_CFG 593 +#define MSM_BUS_SLAVE_MISC_CFG 594 +#define MSM_BUS_SLAVE_MISC_XPU_CFG 595 +#define MSM_BUS_SLAVE_VENUS_CFG 596 +#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597 +#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598 +#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599 +#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600 +#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601 +#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602 +#define MSM_BUS_SLAVE_SERVICE_MNOC 603 +#define MSM_BUS_SLAVE_OCMEM 604 +#define MSM_BUS_SLAVE_SERVICE_ONOC 605 +#define MSM_BUS_SLAVE_SDCC_1 606 +#define MSM_BUS_SLAVE_SDCC_3 607 +#define MSM_BUS_SLAVE_SDCC_2 608 +#define MSM_BUS_SLAVE_SDCC_4 609 +#define MSM_BUS_SLAVE_BAM_DMA 610 +#define MSM_BUS_SLAVE_BLSP_2 611 +#define MSM_BUS_SLAVE_USB_HSIC 612 +#define MSM_BUS_SLAVE_BLSP_1 613 +#define MSM_BUS_SLAVE_USB_HS 614 +#define MSM_BUS_SLAVE_PDM 615 +#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616 +#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617 +#define MSM_BUS_SLAVE_PRNG 618 +#define MSM_BUS_SLAVE_SERVICE_PNOC 619 +#define MSM_BUS_SLAVE_CLK_CTL 620 +#define MSM_BUS_SLAVE_CNOC_MSS 621 +#define MSM_BUS_SLAVE_SECURITY 622 +#define MSM_BUS_SLAVE_TCSR 623 +#define MSM_BUS_SLAVE_TLMM 624 +#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625 +#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626 +#define MSM_BUS_SLAVE_IMEM_CFG 627 +#define MSM_BUS_SLAVE_MESSAGE_RAM 628 +#define MSM_BUS_SLAVE_BIMC_CFG 629 +#define MSM_BUS_SLAVE_BOOT_ROM 630 +#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631 +#define MSM_BUS_SLAVE_PMIC_ARB 632 +#define MSM_BUS_SLAVE_SPDM_WRAPPER 633 +#define MSM_BUS_SLAVE_DEHR_CFG 634 +#define MSM_BUS_SLAVE_QDSS_CFG 635 +#define MSM_BUS_SLAVE_RBCPR_CFG 636 +#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637 +#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638 +#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639 +#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640 +#define MSM_BUS_SLAVE_PNOC_CFG 641 +#define MSM_BUS_SLAVE_SNOC_CFG 642 +#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643 +#define MSM_BUS_SLAVE_PHY_APU_CFG 644 +#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645 +#define MSM_BUS_SLAVE_SERVICE_CNOC 646 +#define MSM_BUS_SLAVE_IPS_CFG 647 +#define MSM_BUS_SLAVE_QPIC 648 +#define MSM_BUS_SLAVE_DSI_CFG 649 +#define MSM_BUS_SLAVE_UFS_CFG 650 +#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651 +#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652 +#define MSM_BUS_SLAVE_PCIE_CFG 653 +#define MSM_BUS_SLAVE_USB_PHYS_CFG 654 +#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655 +#define MSM_BUS_SLAVE_AVSYNC_CFG 656 +#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657 +#define MSM_BUS_SLAVE_VPU_CFG 658 +#define MSM_BUS_SLAVE_BCAST_CFG 659 +#define MSM_BUS_SLAVE_KLM_CFG 660 +#define MSM_BUS_SLAVE_GENI_IR_CFG 661 +#define MSM_BUS_SLAVE_OCMEM_GFX 662 +#define MSM_BUS_SLAVE_CATS_128 663 +#define MSM_BUS_SLAVE_OCMEM_64 664 +#define MSM_BUS_SLAVE_PCIE_0 665 +#define MSM_BUS_SLAVE_PCIE_1 666 +#define MSM_BUS_SLAVE_PCIE_0_CFG 667 +#define MSM_BUS_SLAVE_PCIE_1_CFG 668 +#define MSM_BUS_SLAVE_SRVC_MNOC 669 +#define MSM_BUS_SLAVE_USB_HS2 670 +#define MSM_BUS_SLAVE_AUDIO 671 +#define MSM_BUS_SLAVE_TCU 672 +#define MSM_BUS_SLAVE_APPSS 673 +#define MSM_BUS_SLAVE_PCIE_PARF 674 +#define MSM_BUS_SLAVE_USB3_PHY_CFG 675 +#define MSM_BUS_SLAVE_IPA_CFG 676 +#define MSM_BUS_SLAVE_A0NOC_SNOC 677 +#define MSM_BUS_SLAVE_A1NOC_SNOC 678 +#define MSM_BUS_SLAVE_A2NOC_SNOC 679 +#define MSM_BUS_SLAVE_HMSS_L3 680 +#define MSM_BUS_SLAVE_PIMEM_CFG 681 +#define MSM_BUS_SLAVE_DCC_CFG 682 +#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683 +#define MSM_BUS_SLAVE_PCIE_2_CFG 684 +#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685 +#define MSM_BUS_SLAVE_A0NOC_CFG 686 +#define MSM_BUS_SLAVE_A1NOC_CFG 687 +#define MSM_BUS_SLAVE_A2NOC_CFG 688 +#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689 +#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690 +#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691 +#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692 +#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693 +#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694 +#define MSM_BUS_SLAVE_MMAGIC_CFG 695 +#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696 +#define MSM_BUS_SLAVE_SSC_CFG 697 +#define MSM_BUS_SLAVE_DSA_CFG 698 +#define MSM_BUS_SLAVE_DSA_MPU_CFG 699 +#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700 +#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701 +#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702 +#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703 +#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704 +#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705 +#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706 +#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707 +#define MSM_BUS_SLAVE_VMEM_CFG 708 +#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709 +#define MSM_BUS_SLAVE_VMEM 710 +#define MSM_BUS_SLAVE_AHB2PHY 711 +#define MSM_BUS_SLAVE_PIMEM 712 +#define MSM_BUS_SLAVE_SNOC_VMEM 713 +#define MSM_BUS_SLAVE_PCIE_2 714 +#define MSM_BUS_SLAVE_RBCPR_MX 715 +#define MSM_BUS_SLAVE_RBCPR_CX 716 +#define MSM_BUS_SLAVE_BIMC_PCNOC 717 +#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718 +#define MSM_BUS_SLAVE_SGMII 719 +#define MSM_BUS_SLAVE_SPMI_FETCHER 720 +#define MSM_BUS_PNOC_SLV_6 721 +#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722 +#define MSM_BUS_SLAVE_WLAN 723 +#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724 +#define MSM_BUS_SLAVE_CNOC_A2NOC 725 +#define MSM_BUS_SLAVE_GLM 726 +#define MSM_BUS_SLAVE_GNOC_BIMC 727 +#define MSM_BUS_SLAVE_GNOC_SNOC 728 +#define MSM_BUS_SLAVE_QM_CFG 729 +#define MSM_BUS_SLAVE_TLMM_EAST 730 +#define MSM_BUS_SLAVE_TLMM_NORTH 731 +#define MSM_BUS_SLAVE_TLMM_WEST 732 +#define MSM_BUS_SLAVE_SKL 733 +#define MSM_BUS_SLAVE_LPASS_TCM 734 +#define MSM_BUS_SLAVE_TLMM_SOUTH 735 +#define MSM_BUS_SLAVE_TLMM_CENTER 736 +#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737 +#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738 +#define MSM_BUS_SLAVE_CDSP 739 +#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740 +#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741 +#define MSM_BUS_SLAVE_CSI_PHY_CFG 742 +#define MSM_BUS_SLAVE_LAST 743 + +#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB +#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB + +/* + * ID's used in RPM messages + */ +#define ICBID_MASTER_APPSS_PROC 0 +#define ICBID_MASTER_MSS_PROC 1 +#define ICBID_MASTER_MNOC_BIMC 2 +#define ICBID_MASTER_SNOC_BIMC 3 +#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC +#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4 +#define ICBID_MASTER_CNOC_MNOC_CFG 5 +#define ICBID_MASTER_GFX3D 6 +#define ICBID_MASTER_JPEG 7 +#define ICBID_MASTER_MDP 8 +#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP +#define ICBID_MASTER_MDPS ICBID_MASTER_MDP +#define ICBID_MASTER_VIDEO 9 +#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO +#define ICBID_MASTER_VIDEO_P1 10 +#define ICBID_MASTER_VFE 11 +#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE +#define ICBID_MASTER_CNOC_ONOC_CFG 12 +#define ICBID_MASTER_JPEG_OCMEM 13 +#define ICBID_MASTER_MDP_OCMEM 14 +#define ICBID_MASTER_VIDEO_P0_OCMEM 15 +#define ICBID_MASTER_VIDEO_P1_OCMEM 16 +#define ICBID_MASTER_VFE_OCMEM 17 +#define ICBID_MASTER_LPASS_AHB 18 +#define ICBID_MASTER_QDSS_BAM 19 +#define ICBID_MASTER_SNOC_CFG 20 +#define ICBID_MASTER_BIMC_SNOC 21 +#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC +#define ICBID_MASTER_CNOC_SNOC 22 +#define ICBID_MASTER_CRYPTO 23 +#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO +#define ICBID_MASTER_CRYPTO_CORE1 24 +#define ICBID_MASTER_LPASS_PROC 25 +#define ICBID_MASTER_MSS 26 +#define ICBID_MASTER_MSS_NAV 27 +#define ICBID_MASTER_OCMEM_DMA 28 +#define ICBID_MASTER_PNOC_SNOC 29 +#define ICBID_MASTER_WCSS 30 +#define ICBID_MASTER_QDSS_ETR 31 +#define ICBID_MASTER_USB3 32 +#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3 +#define ICBID_MASTER_SDCC_1 33 +#define ICBID_MASTER_SDCC_3 34 +#define ICBID_MASTER_SDCC_2 35 +#define ICBID_MASTER_SDCC_4 36 +#define ICBID_MASTER_TSIF 37 +#define ICBID_MASTER_BAM_DMA 38 +#define ICBID_MASTER_BLSP_2 39 +#define ICBID_MASTER_USB_HSIC 40 +#define ICBID_MASTER_BLSP_1 41 +#define ICBID_MASTER_USB_HS 42 +#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS +#define ICBID_MASTER_PNOC_CFG 43 +#define ICBID_MASTER_SNOC_PNOC 44 +#define ICBID_MASTER_RPM_INST 45 +#define ICBID_MASTER_RPM_DATA 46 +#define ICBID_MASTER_RPM_SYS 47 +#define ICBID_MASTER_DEHR 48 +#define ICBID_MASTER_QDSS_DAP 49 +#define ICBID_MASTER_SPDM 50 +#define ICBID_MASTER_TIC 51 +#define ICBID_MASTER_SNOC_CNOC 52 +#define ICBID_MASTER_GFX3D_OCMEM 53 +#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM +#define ICBID_MASTER_OVIRT_SNOC 54 +#define ICBID_MASTER_SNOC_OVIRT 55 +#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT +#define ICBID_MASTER_ONOC_OVIRT 56 +#define ICBID_MASTER_USB_HS2 57 +#define ICBID_MASTER_QPIC 58 +#define ICBID_MASTER_IPA 59 +#define ICBID_MASTER_DSI 60 +#define ICBID_MASTER_MDP1 61 +#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1 +#define ICBID_MASTER_VPU_PROC 62 +#define ICBID_MASTER_VPU 63 +#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU +#define ICBID_MASTER_CRYPTO_CORE2 64 +#define ICBID_MASTER_PCIE_0 65 +#define ICBID_MASTER_PCIE_1 66 +#define ICBID_MASTER_SATA 67 +#define ICBID_MASTER_UFS 68 +#define ICBID_MASTER_USB3_1 69 +#define ICBID_MASTER_VIDEO_OCMEM 70 +#define ICBID_MASTER_VPU1 71 +#define ICBID_MASTER_VCAP 72 +#define ICBID_MASTER_EMAC 73 +#define ICBID_MASTER_BCAST 74 +#define ICBID_MASTER_MMSS_PROC 75 +#define ICBID_MASTER_SNOC_BIMC_1 76 +#define ICBID_MASTER_SNOC_PCNOC 77 +#define ICBID_MASTER_AUDIO 78 +#define ICBID_MASTER_MM_INT_0 79 +#define ICBID_MASTER_MM_INT_1 80 +#define ICBID_MASTER_MM_INT_2 81 +#define ICBID_MASTER_MM_INT_BIMC 82 +#define ICBID_MASTER_MSS_INT 83 +#define ICBID_MASTER_PCNOC_CFG 84 +#define ICBID_MASTER_PCNOC_INT_0 85 +#define ICBID_MASTER_PCNOC_INT_1 86 +#define ICBID_MASTER_PCNOC_M_0 87 +#define ICBID_MASTER_PCNOC_M_1 88 +#define ICBID_MASTER_PCNOC_S_0 89 +#define ICBID_MASTER_PCNOC_S_1 90 +#define ICBID_MASTER_PCNOC_S_2 91 +#define ICBID_MASTER_PCNOC_S_3 92 +#define ICBID_MASTER_PCNOC_S_4 93 +#define ICBID_MASTER_PCNOC_S_6 94 +#define ICBID_MASTER_PCNOC_S_7 95 +#define ICBID_MASTER_PCNOC_S_8 96 +#define ICBID_MASTER_PCNOC_S_9 97 +#define ICBID_MASTER_QDSS_INT 98 +#define ICBID_MASTER_SNOC_INT_0 99 +#define ICBID_MASTER_SNOC_INT_1 100 +#define ICBID_MASTER_SNOC_INT_BIMC 101 +#define ICBID_MASTER_TCU_0 102 +#define ICBID_MASTER_TCU_1 103 +#define ICBID_MASTER_BIMC_INT_0 104 +#define ICBID_MASTER_BIMC_INT_1 105 +#define ICBID_MASTER_CAMERA 106 +#define ICBID_MASTER_RICA 107 +#define ICBID_MASTER_SNOC_BIMC_2 108 +#define ICBID_MASTER_BIMC_SNOC_1 109 +#define ICBID_MASTER_A0NOC_SNOC 110 +#define ICBID_MASTER_A1NOC_SNOC 111 +#define ICBID_MASTER_A2NOC_SNOC 112 +#define ICBID_MASTER_PIMEM 113 +#define ICBID_MASTER_SNOC_VMEM 114 +#define ICBID_MASTER_CPP 115 +#define ICBID_MASTER_CNOC_A1NOC 116 +#define ICBID_MASTER_PNOC_A1NOC 117 +#define ICBID_MASTER_HMSS 118 +#define ICBID_MASTER_PCIE_2 119 +#define ICBID_MASTER_ROTATOR 120 +#define ICBID_MASTER_VENUS_VMEM 121 +#define ICBID_MASTER_DCC 122 +#define ICBID_MASTER_MCDMA 123 +#define ICBID_MASTER_PCNOC_INT_2 124 +#define ICBID_MASTER_PCNOC_INT_3 125 +#define ICBID_MASTER_PCNOC_INT_4 126 +#define ICBID_MASTER_PCNOC_INT_5 127 +#define ICBID_MASTER_PCNOC_INT_6 128 +#define ICBID_MASTER_PCNOC_S_5 129 +#define ICBID_MASTER_SENSORS_AHB 130 +#define ICBID_MASTER_SENSORS_PROC 131 +#define ICBID_MASTER_QSPI 132 +#define ICBID_MASTER_VFE1 133 +#define ICBID_MASTER_SNOC_INT_2 134 +#define ICBID_MASTER_SMMNOC_BIMC 135 +#define ICBID_MASTER_CRVIRT_A1NOC 136 +#define ICBID_MASTER_XM_USB_HS1 137 +#define ICBID_MASTER_XI_USB_HS1 138 +#define ICBID_MASTER_PCNOC_BIMC_1 139 +#define ICBID_MASTER_BIMC_PCNOC 140 +#define ICBID_MASTER_XI_HSIC 141 +#define ICBID_MASTER_SGMII 142 +#define ICBID_MASTER_SPMI_FETCHER 143 +#define ICBID_MASTER_GNOC_BIMC 144 +#define ICBID_MASTER_CRVIRT_A2NOC 145 +#define ICBID_MASTER_CNOC_A2NOC 146 +#define ICBID_MASTER_WLAN 147 +#define ICBID_MASTER_MSS_CE 148 +#define ICBID_MASTER_CDSP_PROC 149 +#define ICBID_MASTER_GNOC_SNOC 150 + +#define ICBID_SLAVE_EBI1 0 +#define ICBID_SLAVE_APPSS_L2 1 +#define ICBID_SLAVE_BIMC_SNOC 2 +#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC +#define ICBID_SLAVE_CAMERA_CFG 3 +#define ICBID_SLAVE_DISPLAY_CFG 4 +#define ICBID_SLAVE_OCMEM_CFG 5 +#define ICBID_SLAVE_CPR_CFG 6 +#define ICBID_SLAVE_CPR_XPU_CFG 7 +#define ICBID_SLAVE_MISC_CFG 8 +#define ICBID_SLAVE_MISC_XPU_CFG 9 +#define ICBID_SLAVE_VENUS_CFG 10 +#define ICBID_SLAVE_GFX3D_CFG 11 +#define ICBID_SLAVE_MMSS_CLK_CFG 12 +#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13 +#define ICBID_SLAVE_MNOC_MPU_CFG 14 +#define ICBID_SLAVE_ONOC_MPU_CFG 15 +#define ICBID_SLAVE_MNOC_BIMC 16 +#define ICBID_SLAVE_SERVICE_MNOC 17 +#define ICBID_SLAVE_OCMEM 18 +#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM +#define ICBID_SLAVE_SERVICE_ONOC 19 +#define ICBID_SLAVE_APPSS 20 +#define ICBID_SLAVE_LPASS 21 +#define ICBID_SLAVE_USB3 22 +#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3 +#define ICBID_SLAVE_WCSS 23 +#define ICBID_SLAVE_SNOC_BIMC 24 +#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC +#define ICBID_SLAVE_SNOC_CNOC 25 +#define ICBID_SLAVE_IMEM 26 +#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM +#define ICBID_SLAVE_SNOC_OVIRT 27 +#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT +#define ICBID_SLAVE_SNOC_PNOC 28 +#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC +#define ICBID_SLAVE_SERVICE_SNOC 29 +#define ICBID_SLAVE_QDSS_STM 30 +#define ICBID_SLAVE_SDCC_1 31 +#define ICBID_SLAVE_SDCC_3 32 +#define ICBID_SLAVE_SDCC_2 33 +#define ICBID_SLAVE_SDCC_4 34 +#define ICBID_SLAVE_TSIF 35 +#define ICBID_SLAVE_BAM_DMA 36 +#define ICBID_SLAVE_BLSP_2 37 +#define ICBID_SLAVE_USB_HSIC 38 +#define ICBID_SLAVE_BLSP_1 39 +#define ICBID_SLAVE_USB_HS 40 +#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS +#define ICBID_SLAVE_PDM 41 +#define ICBID_SLAVE_PERIPH_APU_CFG 42 +#define ICBID_SLAVE_PNOC_MPU_CFG 43 +#define ICBID_SLAVE_PRNG 44 +#define ICBID_SLAVE_PNOC_SNOC 45 +#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC +#define ICBID_SLAVE_SERVICE_PNOC 46 +#define ICBID_SLAVE_CLK_CTL 47 +#define ICBID_SLAVE_CNOC_MSS 48 +#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS +#define ICBID_SLAVE_SECURITY 49 +#define ICBID_SLAVE_TCSR 50 +#define ICBID_SLAVE_TLMM 51 +#define ICBID_SLAVE_CRYPTO_0_CFG 52 +#define ICBID_SLAVE_CRYPTO_1_CFG 53 +#define ICBID_SLAVE_IMEM_CFG 54 +#define ICBID_SLAVE_MESSAGE_RAM 55 +#define ICBID_SLAVE_BIMC_CFG 56 +#define ICBID_SLAVE_BOOT_ROM 57 +#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58 +#define ICBID_SLAVE_PMIC_ARB 59 +#define ICBID_SLAVE_SPDM_WRAPPER 60 +#define ICBID_SLAVE_DEHR_CFG 61 +#define ICBID_SLAVE_MPM 62 +#define ICBID_SLAVE_QDSS_CFG 63 +#define ICBID_SLAVE_RBCPR_CFG 64 +#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG +#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65 +#define ICBID_SLAVE_CNOC_MNOC_CFG 66 +#define ICBID_SLAVE_SNOC_MPU_CFG 67 +#define ICBID_SLAVE_CNOC_ONOC_CFG 68 +#define ICBID_SLAVE_PNOC_CFG 69 +#define ICBID_SLAVE_SNOC_CFG 70 +#define ICBID_SLAVE_EBI1_DLL_CFG 71 +#define ICBID_SLAVE_PHY_APU_CFG 72 +#define ICBID_SLAVE_EBI1_PHY_CFG 73 +#define ICBID_SLAVE_RPM 74 +#define ICBID_SLAVE_CNOC_SNOC 75 +#define ICBID_SLAVE_SERVICE_CNOC 76 +#define ICBID_SLAVE_OVIRT_SNOC 77 +#define ICBID_SLAVE_OVIRT_OCMEM 78 +#define ICBID_SLAVE_USB_HS2 79 +#define ICBID_SLAVE_QPIC 80 +#define ICBID_SLAVE_IPS_CFG 81 +#define ICBID_SLAVE_DSI_CFG 82 +#define ICBID_SLAVE_USB3_1 83 +#define ICBID_SLAVE_PCIE_0 84 +#define ICBID_SLAVE_PCIE_1 85 +#define ICBID_SLAVE_PSS_SMMU_CFG 86 +#define ICBID_SLAVE_CRYPTO_2_CFG 87 +#define ICBID_SLAVE_PCIE_0_CFG 88 +#define ICBID_SLAVE_PCIE_1_CFG 89 +#define ICBID_SLAVE_SATA_CFG 90 +#define ICBID_SLAVE_SPSS_GENI_IR 91 +#define ICBID_SLAVE_UFS_CFG 92 +#define ICBID_SLAVE_AVSYNC_CFG 93 +#define ICBID_SLAVE_VPU_CFG 94 +#define ICBID_SLAVE_USB_PHY_CFG 95 +#define ICBID_SLAVE_RBCPR_MX_CFG 96 +#define ICBID_SLAVE_PCIE_PARF 97 +#define ICBID_SLAVE_VCAP_CFG 98 +#define ICBID_SLAVE_EMAC_CFG 99 +#define ICBID_SLAVE_BCAST_CFG 100 +#define ICBID_SLAVE_KLM_CFG 101 +#define ICBID_SLAVE_DISPLAY_PWM 102 +#define ICBID_SLAVE_GENI 103 +#define ICBID_SLAVE_SNOC_BIMC_1 104 +#define ICBID_SLAVE_AUDIO 105 +#define ICBID_SLAVE_CATS_0 106 +#define ICBID_SLAVE_CATS_1 107 +#define ICBID_SLAVE_MM_INT_0 108 +#define ICBID_SLAVE_MM_INT_1 109 +#define ICBID_SLAVE_MM_INT_2 110 +#define ICBID_SLAVE_MM_INT_BIMC 111 +#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112 +#define ICBID_SLAVE_MSS_INT 113 +#define ICBID_SLAVE_PCNOC_INT_0 114 +#define ICBID_SLAVE_PCNOC_INT_1 115 +#define ICBID_SLAVE_PCNOC_M_0 116 +#define ICBID_SLAVE_PCNOC_M_1 117 +#define ICBID_SLAVE_PCNOC_S_0 118 +#define ICBID_SLAVE_PCNOC_S_1 119 +#define ICBID_SLAVE_PCNOC_S_2 120 +#define ICBID_SLAVE_PCNOC_S_3 121 +#define ICBID_SLAVE_PCNOC_S_4 122 +#define ICBID_SLAVE_PCNOC_S_6 123 +#define ICBID_SLAVE_PCNOC_S_7 124 +#define ICBID_SLAVE_PCNOC_S_8 125 +#define ICBID_SLAVE_PCNOC_S_9 126 +#define ICBID_SLAVE_PRNG_XPU_CFG 127 +#define ICBID_SLAVE_QDSS_INT 128 +#define ICBID_SLAVE_RPM_XPU_CFG 129 +#define ICBID_SLAVE_SNOC_INT_0 130 +#define ICBID_SLAVE_SNOC_INT_1 131 +#define ICBID_SLAVE_SNOC_INT_BIMC 132 +#define ICBID_SLAVE_TCU 133 +#define ICBID_SLAVE_BIMC_INT_0 134 +#define ICBID_SLAVE_BIMC_INT_1 135 +#define ICBID_SLAVE_RICA_CFG 136 +#define ICBID_SLAVE_SNOC_BIMC_2 137 +#define ICBID_SLAVE_BIMC_SNOC_1 138 +#define ICBID_SLAVE_PNOC_A1NOC 139 +#define ICBID_SLAVE_SNOC_VMEM 140 +#define ICBID_SLAVE_A0NOC_SNOC 141 +#define ICBID_SLAVE_A1NOC_SNOC 142 +#define ICBID_SLAVE_A2NOC_SNOC 143 +#define ICBID_SLAVE_A0NOC_CFG 144 +#define ICBID_SLAVE_A0NOC_MPU_CFG 145 +#define ICBID_SLAVE_A0NOC_SMMU_CFG 146 +#define ICBID_SLAVE_A1NOC_CFG 147 +#define ICBID_SLAVE_A1NOC_MPU_CFG 148 +#define ICBID_SLAVE_A1NOC_SMMU_CFG 149 +#define ICBID_SLAVE_A2NOC_CFG 150 +#define ICBID_SLAVE_A2NOC_MPU_CFG 151 +#define ICBID_SLAVE_A2NOC_SMMU_CFG 152 +#define ICBID_SLAVE_AHB2PHY 153 +#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154 +#define ICBID_SLAVE_DCC_CFG 155 +#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156 +#define ICBID_SLAVE_DSA_CFG 157 +#define ICBID_SLAVE_DSA_MPU_CFG 158 +#define ICBID_SLAVE_SSC_MPU_CFG 159 +#define ICBID_SLAVE_HMSS_L3 160 +#define ICBID_SLAVE_LPASS_SMMU_CFG 161 +#define ICBID_SLAVE_MMAGIC_CFG 162 +#define ICBID_SLAVE_PCIE20_AHB2PHY 163 +#define ICBID_SLAVE_PCIE_2 164 +#define ICBID_SLAVE_PCIE_2_CFG 165 +#define ICBID_SLAVE_PIMEM 166 +#define ICBID_SLAVE_PIMEM_CFG 167 +#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168 +#define ICBID_SLAVE_RBCPR_CX 169 +#define ICBID_SLAVE_RBCPR_MX 170 +#define ICBID_SLAVE_SMMU_CPP_CFG 171 +#define ICBID_SLAVE_SMMU_JPEG_CFG 172 +#define ICBID_SLAVE_SMMU_MDP_CFG 173 +#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174 +#define ICBID_SLAVE_SMMU_VENUS_CFG 175 +#define ICBID_SLAVE_SMMU_VFE_CFG 176 +#define ICBID_SLAVE_SSC_CFG 177 +#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178 +#define ICBID_SLAVE_VMEM 179 +#define ICBID_SLAVE_VMEM_CFG 180 +#define ICBID_SLAVE_QDSS_MPU_CFG 181 +#define ICBID_SLAVE_USB3_PHY_CFG 182 +#define ICBID_SLAVE_IPA_CFG 183 +#define ICBID_SLAVE_PCNOC_INT_2 184 +#define ICBID_SLAVE_PCNOC_INT_3 185 +#define ICBID_SLAVE_PCNOC_INT_4 186 +#define ICBID_SLAVE_PCNOC_INT_5 187 +#define ICBID_SLAVE_PCNOC_INT_6 188 +#define ICBID_SLAVE_PCNOC_S_5 189 +#define ICBID_SLAVE_QSPI 190 +#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191 +#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192 +#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193 +#define ICBID_SLAVE_MSS_MPU_CFG 194 +#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195 +#define ICBID_SLAVE_SKL 196 +#define ICBID_SLAVE_SNOC_INT_2 197 +#define ICBID_SLAVE_SMMNOC_BIMC 198 +#define ICBID_SLAVE_CRVIRT_A1NOC 199 +#define ICBID_SLAVE_SGMII 200 +#define ICBID_SLAVE_QHS4_APPS 201 +#define ICBID_SLAVE_BIMC_PCNOC 202 +#define ICBID_SLAVE_PCNOC_BIMC_1 203 +#define ICBID_SLAVE_SPMI_FETCHER 204 +#define ICBID_SLAVE_MMSS_SMMU_CFG 205 +#define ICBID_SLAVE_WLAN 206 +#define ICBID_SLAVE_CRVIRT_A2NOC 207 +#define ICBID_SLAVE_CNOC_A2NOC 208 +#define ICBID_SLAVE_GLM 209 +#define ICBID_SLAVE_GNOC_BIMC 210 +#define ICBID_SLAVE_GNOC_SNOC 211 +#define ICBID_SLAVE_QM_CFG 212 +#define ICBID_SLAVE_TLMM_EAST 213 +#define ICBID_SLAVE_TLMM_NORTH 214 +#define ICBID_SLAVE_TLMM_WEST 215 +#define ICBID_SLAVE_LPASS_TCM 216 +#define ICBID_SLAVE_TLMM_SOUTH 217 +#define ICBID_SLAVE_TLMM_CENTER 218 +#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219 +#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220 +#define ICBID_SLAVE_CDSP 221 +#define ICBID_SLAVE_CDSP_SMMU_CFG 222 +#define ICBID_SLAVE_LPASS_MPU_CFG 223 +#define ICBID_SLAVE_CSI_PHY_CFG 224 +#endif diff --git a/include/dt-bindings/msm/msm-bus-rule-ops.h b/include/dt-bindings/msm/msm-bus-rule-ops.h new file mode 100644 index 000000000000..3dcbebd4418b --- /dev/null +++ b/include/dt-bindings/msm/msm-bus-rule-ops.h @@ -0,0 +1,34 @@ +/* Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_BUS_RULE_OPS_H +#define __MSM_BUS_RULE_OPS_H + +#define FLD_IB 0 +#define FLD_AB 1 +#define FLD_CLK 2 + +#define OP_LE 0 +#define OP_LT 1 +#define OP_GE 2 +#define OP_GT 3 +#define OP_NOOP 4 + +#define RULE_STATE_NOT_APPLIED 0 +#define RULE_STATE_APPLIED 1 + +#define THROTTLE_ON 0 +#define THROTTLE_OFF 1 +#define THROTTLE_REG 2 + + +#endif diff --git a/include/dt-bindings/msm/pm.h b/include/dt-bindings/msm/pm.h new file mode 100644 index 000000000000..50987a08d807 --- /dev/null +++ b/include/dt-bindings/msm/pm.h @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_MSM_PM_H__ +#define __DT_MSM_PM_H__ + +#define LPM_RESET_LVL_NONE 0 +#define LPM_RESET_LVL_RET 1 +#define LPM_RESET_LVL_GDHS 2 +#define LPM_RESET_LVL_PC 3 + +#define LPM_AFF_LVL_CPU 0 +#define LPM_AFF_LVL_L2 1 +#define LPM_AFF_LVL_CCI 2 + +#endif diff --git a/include/dt-bindings/msm/power-on.h b/include/dt-bindings/msm/power-on.h new file mode 100644 index 000000000000..f43841eea7b7 --- /dev/null +++ b/include/dt-bindings/msm/power-on.h @@ -0,0 +1,24 @@ +/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MSM_POWER_ON_H__ +#define __MSM_POWER_ON_H__ + +#define PON_POWER_OFF_RESERVED 0x00 +#define PON_POWER_OFF_WARM_RESET 0x01 +#define PON_POWER_OFF_SHUTDOWN 0x04 +#define PON_POWER_OFF_DVDD_SHUTDOWN 0x05 +#define PON_POWER_OFF_HARD_RESET 0x07 +#define PON_POWER_OFF_DVDD_HARD_RESET 0x08 +#define PON_POWER_OFF_MAX_TYPE 0x10 + +#endif diff --git a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h index aafa76cb569d..7ac6f1631098 100644 --- a/include/dt-bindings/pinctrl/qcom,pmic-gpio.h +++ b/include/dt-bindings/pinctrl/qcom,pmic-gpio.h @@ -11,9 +11,14 @@ #define PMIC_GPIO_PULL_UP_1P5_30 3 #define PMIC_GPIO_STRENGTH_NO 0 -#define PMIC_GPIO_STRENGTH_HIGH 1 +#define PMIC_GPIO_STRENGTH_LOW 1 #define PMIC_GPIO_STRENGTH_MED 2 -#define PMIC_GPIO_STRENGTH_LOW 3 +#define PMIC_GPIO_STRENGTH_HIGH 3 + +#define PM8921_GPIO_STRENGTH_NO 0 +#define PM8921_GPIO_STRENGTH_HIGH 1 +#define PM8921_GPIO_STRENGTH_MED 2 +#define PM8921_GPIO_STRENGTH_LOW 3 /* * Note: PM8018 GPIO3 and GPIO4 are supporting @@ -89,15 +94,30 @@ #define PMA8084_GPIO_S4 2 #define PMA8084_GPIO_L6 3 +/* ATEST MUX selection for analog-pass-through mode */ +#define PMIC_GPIO_AOUT_ATEST1 0 +#define PMIC_GPIO_AOUT_ATEST2 1 +#define PMIC_GPIO_AOUT_ATEST3 2 +#define PMIC_GPIO_AOUT_ATEST4 3 + +/* DTEST buffer for digital input mode */ +#define PMIC_GPIO_DIN_DTEST1 0 +#define PMIC_GPIO_DIN_DTEST2 1 +#define PMIC_GPIO_DIN_DTEST3 2 +#define PMIC_GPIO_DIN_DTEST4 3 + /* To be used with "function" */ #define PMIC_GPIO_FUNC_NORMAL "normal" #define PMIC_GPIO_FUNC_PAIRED "paired" #define PMIC_GPIO_FUNC_FUNC1 "func1" #define PMIC_GPIO_FUNC_FUNC2 "func2" +#define PMIC_GPIO_FUNC_FUNC3 "func3" +#define PMIC_GPIO_FUNC_FUNC4 "func4" #define PMIC_GPIO_FUNC_DTEST1 "dtest1" #define PMIC_GPIO_FUNC_DTEST2 "dtest2" #define PMIC_GPIO_FUNC_DTEST3 "dtest3" #define PMIC_GPIO_FUNC_DTEST4 "dtest4" +#define PMIC_GPIO_FUNC_ANALOG "analog" #define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1 #define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1 diff --git a/include/dt-bindings/regulator/max20010.h b/include/dt-bindings/regulator/max20010.h new file mode 100644 index 000000000000..492e7287216f --- /dev/null +++ b/include/dt-bindings/regulator/max20010.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_REGULATOR_MAX20010_H +#define _DT_BINDINGS_REGULATOR_MAX20010_H + +/* Regulator operating modes */ +#define MAX20010_OPMODE_SYNC 0 +#define MAX20010_OPMODE_FPWM 8 + +#endif /* _DT_BINDINGS_REGULATOR_MAX20010_H */ diff --git a/include/dt-bindings/regulator/qcom,rpm-smd-regulator.h b/include/dt-bindings/regulator/qcom,rpm-smd-regulator.h new file mode 100644 index 000000000000..cd38c026f815 --- /dev/null +++ b/include/dt-bindings/regulator/qcom,rpm-smd-regulator.h @@ -0,0 +1,28 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __QCOM_RPM_SMD_REGULATOR_H +#define __QCOM_RPM_SMD_REGULATOR_H + +#define RPM_SMD_REGULATOR_LEVEL_NONE 0 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION 16 +#define RPM_SMD_REGULATOR_LEVEL_RETENTION_PLUS 32 +#define RPM_SMD_REGULATOR_LEVEL_MIN_SVS 48 +#define RPM_SMD_REGULATOR_LEVEL_LOW_SVS 64 +#define RPM_SMD_REGULATOR_LEVEL_SVS 128 +#define RPM_SMD_REGULATOR_LEVEL_SVS_PLUS 192 +#define RPM_SMD_REGULATOR_LEVEL_NOM 256 +#define RPM_SMD_REGULATOR_LEVEL_NOM_PLUS 320 +#define RPM_SMD_REGULATOR_LEVEL_TURBO 384 +#define RPM_SMD_REGULATOR_LEVEL_BINNING 512 + +#endif |