diff options
Diffstat (limited to 'drivers/hwmon')
| -rw-r--r-- | drivers/hwmon/Kconfig | 28 | ||||
| -rw-r--r-- | drivers/hwmon/Makefile | 3 | ||||
| -rw-r--r-- | drivers/hwmon/epm_adc.c | 496 | ||||
| -rw-r--r-- | drivers/hwmon/qpnp-adc-common.c | 2094 | ||||
| -rw-r--r-- | drivers/hwmon/qpnp-adc-current.c | 1664 | ||||
| -rw-r--r-- | drivers/hwmon/qpnp-adc-voltage.c | 2909 |
6 files changed, 7194 insertions, 0 deletions
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 80a73bfc1a65..0799e117a7ab 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1200,6 +1200,34 @@ config SENSORS_PCF8591 These devices are hard to detect and rarely found on mainstream hardware. If unsure, say N. +config SENSORS_EPM_ADC + tristate "EPM ADC Driver for power measurement" + depends on I2C && SPI_MASTER + default n + help + Provides interface for measuring the current on specific power rails + through the channels on ADC1158 ADC + +config SENSORS_QPNP_ADC_VOLTAGE + tristate "Support for Qualcomm QPNP Voltage ADC" + depends on SPMI + help + This is the VADC arbiter driver for Qualcomm QPNP ADC Chip. + + The driver supports reading the HKADC, XOADC through the ADC AMUX arbiter. + The VADC includes support for the conversion sequencer. The driver supports + reading the ADC through the AMUX channels for external pull-ups simultaneously. + +config SENSORS_QPNP_ADC_CURRENT + tristate "Support for Qualcomm QPNP current ADC" + depends on SPMI + help + This is the IADC driver for Qualcomm QPNP ADC Chip. + + The driver supports single mode operation to read from upto seven channel + configuration that include reading the external/internal Rsense, CSP_EX, + CSN_EX pair along with the gain and offset calibration. + source drivers/hwmon/pmbus/Kconfig config SENSORS_PWM_FAN diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 12a32398fdcc..d50394029008 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -160,6 +160,9 @@ obj-$(CONFIG_SENSORS_W83L785TS) += w83l785ts.o obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o +obj-$(CONFIG_SENSORS_EPM_ADC) += epm_adc.o +obj-$(CONFIG_SENSORS_QPNP_ADC_VOLTAGE) += qpnp-adc-voltage.o qpnp-adc-common.o +obj-$(CONFIG_SENSORS_QPNP_ADC_CURRENT) += qpnp-adc-current.o qpnp-adc-common.o obj-$(CONFIG_PMBUS) += pmbus/ diff --git a/drivers/hwmon/epm_adc.c b/drivers/hwmon/epm_adc.c new file mode 100644 index 000000000000..905e6f3252c1 --- /dev/null +++ b/drivers/hwmon/epm_adc.c @@ -0,0 +1,496 @@ +/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/fs.h> +#include <linux/mutex.h> +#include <linux/err.h> +#include <linux/slab.h> +#include <linux/gpio.h> +#include <linux/of_gpio.h> +#include <linux/hwmon.h> +#include <linux/delay.h> +#include <linux/epm_adc.h> +#include <linux/uaccess.h> +#include <linux/spi/spi.h> +#include <linux/hwmon-sysfs.h> +#include <linux/miscdevice.h> +#include <linux/platform_device.h> + +#define EPM_ADC_DRIVER_NAME "epm_adc" +#define EPM_ADC_MAX_FNAME 20 +#define EPM_ADC_CONVERSION_DELAY 100 /* milliseconds */ + +#define EPM_ADC_SPI_BITS_PER_WORD 8 +#define GPIO_EPM_GLOBAL_ENABLE 86 +#define GPIO_EPM_MARKER1 96 +#define GPIO_EPM_MARKER2 85 +#define EPM_ADC_CONVERSION_TIME_MIN 50000 +#define EPM_ADC_CONVERSION_TIME_MAX 51000 +/* PSoc Commands */ + +#define EPM_PSOC_GLOBAL_ENABLE 81 +#define EPM_PSOC_VREF_VOLTAGE 2048 +#define EPM_PSOC_MAX_ADC_CODE_15_BIT 32767 +#define EPM_PSOC_MAX_ADC_CODE_12_BIT 4096 +#define EPM_GLOBAL_ENABLE_MIN_DELAY 5000 +#define EPM_GLOBAL_ENABLE_MAX_DELAY 5100 + +struct epm_adc_drv { + struct platform_device *pdev; + struct device *hwmon; + struct spi_device *epm_spi_client; + struct mutex conv_lock; + uint32_t bus_id; + struct miscdevice misc; + uint32_t channel_mask; + uint32_t epm_global_en_gpio; + struct epm_chan_properties epm_psoc_ch_prop[0]; +}; + +static struct epm_adc_drv *epm_adc_drv; + +static int epm_adc_psoc_gpio_init(struct epm_adc_drv *epm_adc, + bool enable) +{ + int rc = 0; + + if (enable) { + rc = gpio_request(epm_adc->epm_global_en_gpio, + "EPM_PSOC_GLOBAL_EN"); + if (!rc) { + gpio_direction_output(epm_adc->epm_global_en_gpio, 1); + } else { + pr_err("%s: Configure EPM_GLOBAL_EN Failed\n", + __func__); + return rc; + } + } else { + gpio_direction_output(epm_adc->epm_global_en_gpio, 0); + gpio_free(epm_adc->epm_global_en_gpio); + } + + return 0; +} + +static int epm_request_marker1(void) +{ + int rc = 0; + + rc = gpio_request(GPIO_EPM_MARKER1, "EPM_MARKER1"); + if (!rc) { + gpio_direction_output(GPIO_EPM_MARKER1, 1); + } else { + pr_err("%s: Configure MARKER1 GPIO Failed\n", + __func__); + return rc; + } + + return 0; +} + +static int epm_set_marker1(struct epm_marker_level *marker_init) +{ + gpio_set_value(GPIO_EPM_MARKER1, marker_init->level); + + return 0; +} + +static int epm_request_marker2(void) +{ + int rc = 0; + + rc = gpio_request(GPIO_EPM_MARKER2, "EPM_MARKER2"); + if (!rc) { + gpio_direction_output(GPIO_EPM_MARKER2, 1); + } else { + pr_err("%s: Configure MARKER2 GPIO Failed\n", + __func__); + return rc; + } + + return 0; +} + +static int epm_set_marker2(struct epm_marker_level *marker_init) +{ + gpio_set_value(GPIO_EPM_MARKER2, marker_init->level); + + return 0; +} + +static int epm_marker1_release(void) +{ + gpio_free(GPIO_EPM_MARKER1); + + return 0; +} + +static int epm_marker2_release(void) +{ + gpio_free(GPIO_EPM_MARKER2); + + return 0; +} + +static int epm_psoc_generic_request(struct epm_adc_drv *epm_adc, + struct epm_generic_request *psoc_get_data) +{ + struct spi_message m; + struct spi_transfer t; + char tx_buf[64], rx_buf[64]; + int rc = 0, data_loop = 0; + + spi_setup(epm_adc->epm_spi_client); + + memset(&t, 0, sizeof(t)); + memset(tx_buf, 0, sizeof(tx_buf)); + memset(rx_buf, 0, sizeof(tx_buf)); + t.tx_buf = tx_buf; + t.rx_buf = rx_buf; + spi_message_init(&m); + spi_message_add_tail(&t, &m); + + for (data_loop = 0; data_loop < 64; data_loop++) + tx_buf[data_loop] = psoc_get_data->buf[data_loop]; + + t.len = sizeof(tx_buf); + t.bits_per_word = EPM_ADC_SPI_BITS_PER_WORD; + + rc = spi_sync(epm_adc->epm_spi_client, &m); + if (rc) + return rc; + + for (data_loop = 0; data_loop < 64; data_loop++) + psoc_get_data->buf[data_loop] = rx_buf[data_loop]; + + return rc; +} + +static long epm_adc_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct epm_adc_drv *epm_adc = epm_adc_drv; + + switch (cmd) { + case EPM_MARKER1_REQUEST: + { + uint32_t result; + result = epm_request_marker1(); + + if (copy_to_user((void __user *)arg, &result, + sizeof(uint32_t))) + return -EFAULT; + break; + } + case EPM_MARKER2_REQUEST: + { + uint32_t result; + result = epm_request_marker2(); + + if (copy_to_user((void __user *)arg, &result, + sizeof(uint32_t))) + return -EFAULT; + break; + } + case EPM_MARKER1_SET_LEVEL: + { + struct epm_marker_level marker_init; + uint32_t result; + + if (copy_from_user(&marker_init, (void __user *)arg, + sizeof(struct epm_marker_level))) + return -EFAULT; + + result = epm_set_marker1(&marker_init); + + if (copy_to_user((void __user *)arg, &result, + sizeof(uint32_t))) + return -EFAULT; + break; + } + case EPM_MARKER2_SET_LEVEL: + { + struct epm_marker_level marker_init; + uint32_t result; + + if (copy_from_user(&marker_init, (void __user *)arg, + sizeof(struct epm_marker_level))) + return -EFAULT; + + result = epm_set_marker2(&marker_init); + + if (copy_to_user((void __user *)arg, &result, + sizeof(uint32_t))) + return -EFAULT; + break; + } + case EPM_MARKER1_RELEASE: + { + uint32_t result; + result = epm_marker1_release(); + + if (copy_to_user((void __user *)arg, &result, + sizeof(uint32_t))) + return -EFAULT; + break; + } + case EPM_MARKER2_RELEASE: + { + uint32_t result; + result = epm_marker2_release(); + + if (copy_to_user((void __user *)arg, &result, + sizeof(uint32_t))) + return -EFAULT; + break; + } + case EPM_PSOC_ADC_INIT: + { + int rc; + + rc = epm_adc_psoc_gpio_init(epm_adc, true); + if (rc) + pr_err("GPIO init failed with %d\n", rc); + + if (copy_to_user((void __user *)arg, &rc, + sizeof(int))) + return -EFAULT; + break; + } + case EPM_PSOC_ADC_DEINIT: + { + int rc; + rc = epm_adc_psoc_gpio_init(epm_adc, false); + + if (copy_to_user((void __user *)arg, &rc, + sizeof(int))) + return -EFAULT; + break; + } + case EPM_PSOC_GENERIC_REQUEST: + { + struct epm_generic_request psoc_get_data; + int rc; + + if (copy_from_user(&psoc_get_data, + (void __user *)arg, + sizeof(struct + epm_generic_request))) + return -EFAULT; + + rc = epm_psoc_generic_request(epm_adc, &psoc_get_data); + if (rc) + pr_err("Generic request failed\n"); + + if (copy_to_user((void __user *)arg, &psoc_get_data, + sizeof(struct + epm_generic_request))) + return -EFAULT; + break; + } + default: + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_COMPAT +static long epm_adc_compat_ioctl_process(struct file *filep, + unsigned int cmd, unsigned long arg) +{ + arg = (unsigned long)compat_ptr(arg); + return epm_adc_ioctl(filep, cmd, arg); +} +#endif /* CONFIG_COMPAT */ + +const struct file_operations epm_adc_fops = { + .unlocked_ioctl = epm_adc_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = epm_adc_compat_ioctl_process, +#endif /* CONFIG_COMPAT */ +}; + +static int get_device_tree_data(struct spi_device *spi) +{ + const struct device_node *node = spi->dev.of_node; + struct epm_adc_drv *epm_adc; + u32 *epm_ch_gain, *epm_ch_rsense; + u32 rc = 0, epm_num_channels, i, channel_mask, epm_gpio_num; + + if (!node) + return -EINVAL; + + rc = of_property_read_u32(node, + "qcom,channels", &epm_num_channels); + if (rc) { + dev_err(&spi->dev, "missing channel numbers\n"); + return -ENODEV; + } + + epm_ch_gain = devm_kzalloc(&spi->dev, + epm_num_channels * sizeof(u32), GFP_KERNEL); + if (!epm_ch_gain) { + dev_err(&spi->dev, "cannot allocate gain\n"); + return -ENOMEM; + } + + epm_ch_rsense = devm_kzalloc(&spi->dev, + epm_num_channels * sizeof(u32), GFP_KERNEL); + if (!epm_ch_rsense) { + dev_err(&spi->dev, "cannot allocate rsense\n"); + return -ENOMEM; + } + + rc = of_property_read_u32_array(node, + "qcom,gain", epm_ch_gain, epm_num_channels); + if (rc) { + dev_err(&spi->dev, "invalid gain property:%d\n", rc); + return rc; + } + + rc = of_property_read_u32_array(node, + "qcom,rsense", epm_ch_rsense, epm_num_channels); + if (rc) { + dev_err(&spi->dev, "invalid rsense property:%d\n", rc); + return rc; + } + + rc = of_property_read_u32(node, + "qcom,channel-type", &channel_mask); + if (rc) { + dev_err(&spi->dev, "missing channel mask\n"); + return -ENODEV; + } + + epm_gpio_num = of_get_named_gpio(spi->dev.of_node, + "qcom,epm-enable-gpio", 0); + if (epm_gpio_num < 0) { + dev_err(&spi->dev, "missing global en gpio num\n"); + return -ENODEV; + } + + epm_adc = devm_kzalloc(&spi->dev, + sizeof(struct epm_adc_drv) + + (epm_num_channels * + sizeof(struct epm_chan_properties)), + GFP_KERNEL); + if (!epm_adc) { + dev_err(&spi->dev, "Unable to allocate memory\n"); + return -ENOMEM; + } + + for (i = 0; i < epm_num_channels; i++) { + epm_adc->epm_psoc_ch_prop[i].resistorvalue = + epm_ch_rsense[i]; + epm_adc->epm_psoc_ch_prop[i].gain = + epm_ch_gain[i]; + } + + epm_adc->channel_mask = channel_mask; + epm_adc->epm_global_en_gpio = epm_gpio_num; + epm_adc_drv = epm_adc; + + return 0; +} + +static int epm_adc_psoc_spi_probe(struct spi_device *spi) +{ + + struct epm_adc_drv *epm_adc; + struct device_node *node = spi->dev.of_node; + int rc = 0; + + if (node) { + rc = get_device_tree_data(spi); + if (rc) + return rc; + } else { + epm_adc = epm_adc_drv; + epm_adc_drv->epm_spi_client = spi; + epm_adc_drv->epm_spi_client->bits_per_word = + EPM_ADC_SPI_BITS_PER_WORD; + return rc; + } + + epm_adc = epm_adc_drv; + epm_adc->misc.name = EPM_ADC_DRIVER_NAME; + epm_adc->misc.minor = MISC_DYNAMIC_MINOR; + + if (node) { + epm_adc->misc.fops = &epm_adc_fops; + if (misc_register(&epm_adc->misc)) { + pr_err("Unable to register misc device!\n"); + return -EFAULT; + } + } + + epm_adc_drv->epm_spi_client = spi; + epm_adc_drv->epm_spi_client->bits_per_word = + EPM_ADC_SPI_BITS_PER_WORD; + + epm_adc->hwmon = hwmon_device_register(&spi->dev); + if (IS_ERR(epm_adc->hwmon)) { + dev_err(&spi->dev, "hwmon_device_register failed\n"); + return rc; + } + + mutex_init(&epm_adc->conv_lock); + return rc; +} + +static int epm_adc_psoc_spi_remove(struct spi_device *spi) +{ + epm_adc_drv->epm_spi_client = NULL; + return 0; +} + +static const struct of_device_id epm_adc_psoc_match_table[] = { + { .compatible = "cy,epm-adc-cy8c5568lti-114", + }, + {} +}; + +static struct spi_driver epm_spi_driver = { + .probe = epm_adc_psoc_spi_probe, + .remove = epm_adc_psoc_spi_remove, + .driver = { + .name = EPM_ADC_DRIVER_NAME, + .of_match_table = epm_adc_psoc_match_table, + }, +}; + +static int __init epm_adc_init(void) +{ + int ret = 0; + + ret = spi_register_driver(&epm_spi_driver); + if (ret) + pr_err("%s: spi register failed: rc=%d\n", __func__, ret); + + return ret; +} + +static void __exit epm_adc_exit(void) +{ + spi_unregister_driver(&epm_spi_driver); +} + +module_init(epm_adc_init); +module_exit(epm_adc_exit); + +MODULE_DESCRIPTION("EPM ADC Driver"); +MODULE_ALIAS("platform:epm_adc"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwmon/qpnp-adc-common.c b/drivers/hwmon/qpnp-adc-common.c new file mode 100644 index 000000000000..6f4c094309f6 --- /dev/null +++ b/drivers/hwmon/qpnp-adc-common.c @@ -0,0 +1,2094 @@ +/* Copyright (c) 2012-2018, 2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/mutex.h> +#include <linux/types.h> +#include <linux/hwmon.h> +#include <linux/module.h> +#include <linux/debugfs.h> +#include <linux/spmi.h> +#include <linux/platform_device.h> +#include <linux/of_irq.h> +#include <linux/interrupt.h> +#include <linux/completion.h> +#include <linux/qpnp/qpnp-adc.h> + +#define KELVINMIL_DEGMIL 273160 +#define QPNP_VADC_LDO_VOLTAGE_MIN 1800000 +#define QPNP_VADC_LDO_VOLTAGE_MAX 1800000 +#define QPNP_VADC_OK_VOLTAGE_MIN 1000000 +#define QPNP_VADC_OK_VOLTAGE_MAX 1000000 +#define PMI_CHG_SCALE_1 -138890 +#define PMI_CHG_SCALE_2 391750000000 +#define QPNP_VADC_HC_VREF_CODE 0x4000 +#define QPNP_VADC_HC_VDD_REFERENCE_MV 1875 +/* Clamp negative ADC code to 0 */ +#define QPNP_VADC_HC_MAX_CODE 0x7FFF + +/* Units for temperature below (on x axis) is in 0.1DegC as + required by the battery driver. Note the resolution used + here to compute the table was done for DegC to milli-volts. + In consideration to limit the size of the table for the given + temperature range below, the result is linearly interpolated + and provided to the battery driver in the units desired for + their framework which is 0.1DegC. True resolution of 0.1DegC + will result in the below table size to increase by 10 times */ +static const struct qpnp_vadc_map_pt adcmap_btm_threshold[] = { + {-300, 1642}, + {-200, 1544}, + {-100, 1414}, + {0, 1260}, + {10, 1244}, + {20, 1228}, + {30, 1212}, + {40, 1195}, + {50, 1179}, + {60, 1162}, + {70, 1146}, + {80, 1129}, + {90, 1113}, + {100, 1097}, + {110, 1080}, + {120, 1064}, + {130, 1048}, + {140, 1032}, + {150, 1016}, + {160, 1000}, + {170, 985}, + {180, 969}, + {190, 954}, + {200, 939}, + {210, 924}, + {220, 909}, + {230, 894}, + {240, 880}, + {250, 866}, + {260, 852}, + {270, 838}, + {280, 824}, + {290, 811}, + {300, 798}, + {310, 785}, + {320, 773}, + {330, 760}, + {340, 748}, + {350, 736}, + {360, 725}, + {370, 713}, + {380, 702}, + {390, 691}, + {400, 681}, + {410, 670}, + {420, 660}, + {430, 650}, + {440, 640}, + {450, 631}, + {460, 622}, + {470, 613}, + {480, 604}, + {490, 595}, + {500, 587}, + {510, 579}, + {520, 571}, + {530, 563}, + {540, 556}, + {550, 548}, + {560, 541}, + {570, 534}, + {580, 527}, + {590, 521}, + {600, 514}, + {610, 508}, + {620, 502}, + {630, 496}, + {640, 490}, + {650, 485}, + {660, 281}, + {670, 274}, + {680, 267}, + {690, 260}, + {700, 254}, + {710, 247}, + {720, 241}, + {730, 235}, + {740, 229}, + {750, 224}, + {760, 218}, + {770, 213}, + {780, 208}, + {790, 203} +}; + +static const struct qpnp_vadc_map_pt adcmap_qrd_btm_threshold[] = { + {-200, 1540}, + {-180, 1517}, + {-160, 1492}, + {-140, 1467}, + {-120, 1440}, + {-100, 1412}, + {-80, 1383}, + {-60, 1353}, + {-40, 1323}, + {-20, 1292}, + {0, 1260}, + {20, 1228}, + {40, 1196}, + {60, 1163}, + {80, 1131}, + {100, 1098}, + {120, 1066}, + {140, 1034}, + {160, 1002}, + {180, 971}, + {200, 941}, + {220, 911}, + {240, 882}, + {260, 854}, + {280, 826}, + {300, 800}, + {320, 774}, + {340, 749}, + {360, 726}, + {380, 703}, + {400, 681}, + {420, 660}, + {440, 640}, + {460, 621}, + {480, 602}, + {500, 585}, + {520, 568}, + {540, 552}, + {560, 537}, + {580, 523}, + {600, 510}, + {620, 497}, + {640, 485}, + {660, 473}, + {680, 462}, + {700, 452}, + {720, 442}, + {740, 433}, + {760, 424}, + {780, 416}, + {800, 408}, +}; + +static const struct qpnp_vadc_map_pt adcmap_qrd_skuaa_btm_threshold[] = { + {-200, 1476}, + {-180, 1450}, + {-160, 1422}, + {-140, 1394}, + {-120, 1365}, + {-100, 1336}, + {-80, 1306}, + {-60, 1276}, + {-40, 1246}, + {-20, 1216}, + {0, 1185}, + {20, 1155}, + {40, 1126}, + {60, 1096}, + {80, 1068}, + {100, 1040}, + {120, 1012}, + {140, 986}, + {160, 960}, + {180, 935}, + {200, 911}, + {220, 888}, + {240, 866}, + {260, 844}, + {280, 824}, + {300, 805}, + {320, 786}, + {340, 769}, + {360, 752}, + {380, 737}, + {400, 722}, + {420, 707}, + {440, 694}, + {460, 681}, + {480, 669}, + {500, 658}, + {520, 648}, + {540, 637}, + {560, 628}, + {580, 619}, + {600, 611}, + {620, 603}, + {640, 595}, + {660, 588}, + {680, 582}, + {700, 575}, + {720, 569}, + {740, 564}, + {760, 559}, + {780, 554}, + {800, 549}, +}; + +static const struct qpnp_vadc_map_pt adcmap_qrd_skug_btm_threshold[] = { + {-200, 1338}, + {-180, 1307}, + {-160, 1276}, + {-140, 1244}, + {-120, 1213}, + {-100, 1182}, + {-80, 1151}, + {-60, 1121}, + {-40, 1092}, + {-20, 1063}, + {0, 1035}, + {20, 1008}, + {40, 982}, + {60, 957}, + {80, 933}, + {100, 910}, + {120, 889}, + {140, 868}, + {160, 848}, + {180, 830}, + {200, 812}, + {220, 795}, + {240, 780}, + {260, 765}, + {280, 751}, + {300, 738}, + {320, 726}, + {340, 714}, + {360, 704}, + {380, 694}, + {400, 684}, + {420, 675}, + {440, 667}, + {460, 659}, + {480, 652}, + {500, 645}, + {520, 639}, + {540, 633}, + {560, 627}, + {580, 622}, + {600, 617}, + {620, 613}, + {640, 608}, + {660, 604}, + {680, 600}, + {700, 597}, + {720, 593}, + {740, 590}, + {760, 587}, + {780, 585}, + {800, 582}, +}; + +static const struct qpnp_vadc_map_pt adcmap_qrd_skuh_btm_threshold[] = { + {-200, 1531}, + {-180, 1508}, + {-160, 1483}, + {-140, 1458}, + {-120, 1432}, + {-100, 1404}, + {-80, 1377}, + {-60, 1348}, + {-40, 1319}, + {-20, 1290}, + {0, 1260}, + {20, 1230}, + {40, 1200}, + {60, 1171}, + {80, 1141}, + {100, 1112}, + {120, 1083}, + {140, 1055}, + {160, 1027}, + {180, 1000}, + {200, 973}, + {220, 948}, + {240, 923}, + {260, 899}, + {280, 876}, + {300, 854}, + {320, 832}, + {340, 812}, + {360, 792}, + {380, 774}, + {400, 756}, + {420, 739}, + {440, 723}, + {460, 707}, + {480, 692}, + {500, 679}, + {520, 665}, + {540, 653}, + {560, 641}, + {580, 630}, + {600, 619}, + {620, 609}, + {640, 600}, + {660, 591}, + {680, 583}, + {700, 575}, + {720, 567}, + {740, 560}, + {760, 553}, + {780, 547}, + {800, 541}, + {820, 535}, + {840, 530}, + {860, 524}, + {880, 520}, +}; + +static const struct qpnp_vadc_map_pt adcmap_qrd_skut1_btm_threshold[] = { + {-400, 1759}, + {-350, 1742}, + {-300, 1720}, + {-250, 1691}, + {-200, 1654}, + {-150, 1619}, + {-100, 1556}, + {-50, 1493}, + {0, 1422}, + {50, 1345}, + {100, 1264}, + {150, 1180}, + {200, 1097}, + {250, 1017}, + {300, 942}, + {350, 873}, + {400, 810}, + {450, 754}, + {500, 706}, + {550, 664}, + {600, 627}, + {650, 596}, + {700, 570}, + {750, 547}, + {800, 528}, + {850, 512}, + {900, 499}, + {950, 487}, + {1000, 477}, +}; + +/* Voltage to temperature */ +static const struct qpnp_vadc_map_pt adcmap_100k_104ef_104fb[] = { + {1758, -40}, + {1742, -35}, + {1719, -30}, + {1691, -25}, + {1654, -20}, + {1608, -15}, + {1551, -10}, + {1483, -5}, + {1404, 0}, + {1315, 5}, + {1218, 10}, + {1114, 15}, + {1007, 20}, + {900, 25}, + {795, 30}, + {696, 35}, + {605, 40}, + {522, 45}, + {448, 50}, + {383, 55}, + {327, 60}, + {278, 65}, + {237, 70}, + {202, 75}, + {172, 80}, + {146, 85}, + {125, 90}, + {107, 95}, + {92, 100}, + {79, 105}, + {68, 110}, + {59, 115}, + {51, 120}, + {44, 125} +}; + +/* Voltage to temperature */ +static const struct qpnp_vadc_map_pt adcmap_150k_104ef_104fb[] = { + {1738, -40}, + {1714, -35}, + {1682, -30}, + {1641, -25}, + {1589, -20}, + {1526, -15}, + {1451, -10}, + {1363, -5}, + {1266, 0}, + {1159, 5}, + {1048, 10}, + {936, 15}, + {825, 20}, + {720, 25}, + {622, 30}, + {533, 35}, + {454, 40}, + {385, 45}, + {326, 50}, + {275, 55}, + {232, 60}, + {195, 65}, + {165, 70}, + {139, 75}, + {118, 80}, + {100, 85}, + {85, 90}, + {73, 95}, + {62, 100}, + {53, 105}, + {46, 110}, + {40, 115}, + {34, 120}, + {30, 125} +}; + +static const struct qpnp_vadc_map_pt adcmap_smb_batt_therm[] = { + {-300, 1625}, + {-200, 1515}, + {-100, 1368}, + {0, 1192}, + {10, 1173}, + {20, 1154}, + {30, 1135}, + {40, 1116}, + {50, 1097}, + {60, 1078}, + {70, 1059}, + {80, 1040}, + {90, 1020}, + {100, 1001}, + {110, 982}, + {120, 963}, + {130, 944}, + {140, 925}, + {150, 907}, + {160, 888}, + {170, 870}, + {180, 851}, + {190, 833}, + {200, 815}, + {210, 797}, + {220, 780}, + {230, 762}, + {240, 745}, + {250, 728}, + {260, 711}, + {270, 695}, + {280, 679}, + {290, 663}, + {300, 647}, + {310, 632}, + {320, 616}, + {330, 602}, + {340, 587}, + {350, 573}, + {360, 559}, + {370, 545}, + {380, 531}, + {390, 518}, + {400, 505}, + {410, 492}, + {420, 480}, + {430, 465}, + {440, 456}, + {450, 445}, + {460, 433}, + {470, 422}, + {480, 412}, + {490, 401}, + {500, 391}, + {510, 381}, + {520, 371}, + {530, 362}, + {540, 352}, + {550, 343}, + {560, 335}, + {570, 326}, + {580, 318}, + {590, 309}, + {600, 302}, + {610, 294}, + {620, 286}, + {630, 279}, + {640, 272}, + {650, 265}, + {660, 258}, + {670, 252}, + {680, 245}, + {690, 239}, + {700, 233}, + {710, 227}, + {720, 221}, + {730, 216}, + {740, 211}, + {750, 205}, + {760, 200}, + {770, 195}, + {780, 190}, + {790, 186} +}; + +/* Voltage to temperature */ +static const struct qpnp_vadc_map_pt adcmap_ncp03wf683[] = { + {1742, -40}, + {1718, -35}, + {1687, -30}, + {1647, -25}, + {1596, -20}, + {1534, -15}, + {1459, -10}, + {1372, -5}, + {1275, 0}, + {1169, 5}, + {1058, 10}, + {945, 15}, + {834, 20}, + {729, 25}, + {630, 30}, + {541, 35}, + {461, 40}, + {392, 45}, + {332, 50}, + {280, 55}, + {236, 60}, + {199, 65}, + {169, 70}, + {142, 75}, + {121, 80}, + {102, 85}, + {87, 90}, + {74, 95}, + {64, 100}, + {55, 105}, + {47, 110}, + {40, 115}, + {35, 120}, + {30, 125} +}; + +/* + * Voltage to temperature table for 100k pull up for NTCG104EF104 with + * 1.875V reference. + */ +static const struct qpnp_vadc_map_pt adcmap_100k_104ef_104fb_1875_vref[] = { + { 1831, -40 }, + { 1814, -35 }, + { 1791, -30 }, + { 1761, -25 }, + { 1723, -20 }, + { 1675, -15 }, + { 1616, -10 }, + { 1545, -5 }, + { 1463, 0 }, + { 1370, 5 }, + { 1268, 10 }, + { 1160, 15 }, + { 1049, 20 }, + { 937, 25 }, + { 828, 30 }, + { 726, 35 }, + { 630, 40 }, + { 544, 45 }, + { 467, 50 }, + { 399, 55 }, + { 340, 60 }, + { 290, 65 }, + { 247, 70 }, + { 209, 75 }, + { 179, 80 }, + { 153, 85 }, + { 130, 90 }, + { 112, 95 }, + { 96, 100 }, + { 82, 105 }, + { 71, 110 }, + { 62, 115 }, + { 53, 120 }, + { 46, 125 }, +}; + +static int32_t qpnp_adc_map_voltage_temp(const struct qpnp_vadc_map_pt *pts, + uint32_t tablesize, int32_t input, int64_t *output) +{ + bool descending = 1; + uint32_t i = 0; + + if (pts == NULL) + return -EINVAL; + + /* Check if table is descending or ascending */ + if (tablesize > 1) { + if (pts[0].x < pts[1].x) + descending = 0; + } + + while (i < tablesize) { + if ((descending == 1) && (pts[i].x < input)) { + /* table entry is less than measured + value and table is descending, stop */ + break; + } else if ((descending == 0) && + (pts[i].x > input)) { + /* table entry is greater than measured + value and table is ascending, stop */ + break; + } else { + i++; + } + } + + if (i == 0) + *output = pts[0].y; + else if (i == tablesize) + *output = pts[tablesize-1].y; + else { + /* result is between search_index and search_index-1 */ + /* interpolate linearly */ + *output = (((int32_t) ((pts[i].y - pts[i-1].y)* + (input - pts[i-1].x))/ + (pts[i].x - pts[i-1].x))+ + pts[i-1].y); + } + + return 0; +} + +static int32_t qpnp_adc_map_temp_voltage(const struct qpnp_vadc_map_pt *pts, + uint32_t tablesize, int32_t input, int64_t *output) +{ + bool descending = 1; + uint32_t i = 0; + + if (pts == NULL) + return -EINVAL; + + /* Check if table is descending or ascending */ + if (tablesize > 1) { + if (pts[0].y < pts[1].y) + descending = 0; + } + + while (i < tablesize) { + if ((descending == 1) && (pts[i].y < input)) { + /* table entry is less than measured + value and table is descending, stop */ + break; + } else if ((descending == 0) && (pts[i].y > input)) { + /* table entry is greater than measured + value and table is ascending, stop */ + break; + } else { + i++; + } + } + + if (i == 0) { + *output = pts[0].x; + } else if (i == tablesize) { + *output = pts[tablesize-1].x; + } else { + /* result is between search_index and search_index-1 */ + /* interpolate linearly */ + *output = (((int32_t) ((pts[i].x - pts[i-1].x)* + (input - pts[i-1].y))/ + (pts[i].y - pts[i-1].y))+ + pts[i-1].x); + } + + return 0; +} + +static void qpnp_adc_scale_with_calib_param(int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + int64_t *scale_voltage) +{ + *scale_voltage = (adc_code - + chan_properties->adc_graph[chan_properties->calib_type].adc_gnd) + * chan_properties->adc_graph[chan_properties->calib_type].dx; + *scale_voltage = div64_s64(*scale_voltage, + chan_properties->adc_graph[chan_properties->calib_type].dy); + + if (chan_properties->calib_type == CALIB_ABSOLUTE) + *scale_voltage += + chan_properties->adc_graph[chan_properties->calib_type].dx; + + if (*scale_voltage < 0) + *scale_voltage = 0; +} + +int32_t qpnp_adc_scale_pmic_therm(struct qpnp_vadc_chip *vadc, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t pmic_voltage = 0; + + if (!chan_properties || !chan_properties->offset_gain_numerator || + !chan_properties->offset_gain_denominator || !adc_properties + || !adc_chan_result) + return -EINVAL; + + if (adc_properties->adc_hc) { + /* (ADC code * vref_vadc (1.875V)) / 0x4000 */ + if (adc_code > QPNP_VADC_HC_MAX_CODE) + adc_code = 0; + pmic_voltage = (int64_t) adc_code; + pmic_voltage *= (int64_t) (adc_properties->adc_vdd_reference + * 1000); + pmic_voltage = div64_s64(pmic_voltage, + QPNP_VADC_HC_VREF_CODE); + } else { + if (!chan_properties->adc_graph[CALIB_ABSOLUTE].dy) + return -EINVAL; + qpnp_adc_scale_with_calib_param(adc_code, adc_properties, + chan_properties, &pmic_voltage); + } + + if (pmic_voltage > 0) { + /* 2mV/K */ + adc_chan_result->measurement = pmic_voltage* + chan_properties->offset_gain_denominator; + + do_div(adc_chan_result->measurement, + chan_properties->offset_gain_numerator * 2); + } else + adc_chan_result->measurement = 0; + + /* Change to .001 deg C */ + adc_chan_result->measurement -= KELVINMIL_DEGMIL; + adc_chan_result->physical = (int32_t) adc_chan_result->measurement; + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_scale_pmic_therm); + +int32_t qpnp_adc_scale_millidegc_pmic_voltage_thr(struct qpnp_vadc_chip *chip, + struct qpnp_adc_tm_btm_param *param, + uint32_t *low_threshold, uint32_t *high_threshold) +{ + struct qpnp_vadc_linear_graph btm_param; + int64_t low_output = 0, high_output = 0; + int rc = 0, sign = 0; + + /* Convert to Kelvin and account for voltage to be written as 2mV/K */ + low_output = (param->low_temp + KELVINMIL_DEGMIL) * 2; + /* Convert to Kelvin and account for voltage to be written as 2mV/K */ + high_output = (param->high_temp + KELVINMIL_DEGMIL) * 2; + + if (param->adc_tm_hc) { + low_output *= QPNP_VADC_HC_VREF_CODE; + do_div(low_output, (QPNP_VADC_HC_VDD_REFERENCE_MV * 1000)); + high_output *= QPNP_VADC_HC_VREF_CODE; + do_div(high_output, (QPNP_VADC_HC_VDD_REFERENCE_MV * 1000)); + } else { + rc = qpnp_get_vadc_gain_and_offset(chip, &btm_param, + CALIB_ABSOLUTE); + if (rc < 0) { + pr_err("Could not acquire gain and offset\n"); + return rc; + } + + /* Convert to voltage threshold */ + low_output = (low_output - QPNP_ADC_625_UV) * btm_param.dy; + if (low_output < 0) { + sign = 1; + low_output = -low_output; + } + do_div(low_output, QPNP_ADC_625_UV); + if (sign) + low_output = -low_output; + low_output += btm_param.adc_gnd; + + sign = 0; + /* Convert to voltage threshold */ + high_output = (high_output - QPNP_ADC_625_UV) * btm_param.dy; + if (high_output < 0) { + sign = 1; + high_output = -high_output; + } + do_div(high_output, QPNP_ADC_625_UV); + if (sign) + high_output = -high_output; + high_output += btm_param.adc_gnd; + } + + *low_threshold = (uint32_t) low_output; + *high_threshold = (uint32_t) high_output; + + pr_debug("high_temp:%d, low_temp:%d\n", param->high_temp, + param->low_temp); + pr_debug("adc_code_high:%x, adc_code_low:%x\n", *high_threshold, + *low_threshold); + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_scale_millidegc_pmic_voltage_thr); + +/* Scales the ADC code to degC using the mapping + * table for the XO thermistor. + */ +int32_t qpnp_adc_tdkntcg_therm(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t xo_thm_voltage = 0; + + if (!chan_properties || !chan_properties->offset_gain_numerator || + !chan_properties->offset_gain_denominator || !adc_properties + || !adc_chan_result) + return -EINVAL; + + if (adc_properties->adc_hc) { + /* (ADC code * vref_vadc (1.875V) * 1000) / (0x4000 * 1000) */ + if (adc_code > QPNP_VADC_HC_MAX_CODE) + adc_code = 0; + xo_thm_voltage = (int64_t) adc_code; + xo_thm_voltage *= (int64_t) (adc_properties->adc_vdd_reference + * 1000); + xo_thm_voltage = div64_s64(xo_thm_voltage, + QPNP_VADC_HC_VREF_CODE * 1000); + qpnp_adc_map_voltage_temp(adcmap_100k_104ef_104fb_1875_vref, + ARRAY_SIZE(adcmap_100k_104ef_104fb_1875_vref), + xo_thm_voltage, &adc_chan_result->physical); + } else { + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &xo_thm_voltage); + + if (chan_properties->calib_type == CALIB_ABSOLUTE) + do_div(xo_thm_voltage, 1000); + + qpnp_adc_map_voltage_temp(adcmap_100k_104ef_104fb, + ARRAY_SIZE(adcmap_100k_104ef_104fb), + xo_thm_voltage, &adc_chan_result->physical); + } + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_tdkntcg_therm); + +int32_t qpnp_adc_scale_batt_therm(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t bat_voltage = 0; + + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &bat_voltage); + + adc_chan_result->measurement = bat_voltage; + + return qpnp_adc_map_temp_voltage( + adcmap_btm_threshold, + ARRAY_SIZE(adcmap_btm_threshold), + bat_voltage, + &adc_chan_result->physical); +} +EXPORT_SYMBOL(qpnp_adc_scale_batt_therm); + +int32_t qpnp_adc_scale_qrd_batt_therm(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t bat_voltage = 0; + + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &bat_voltage); + + adc_chan_result->measurement = bat_voltage; + + return qpnp_adc_map_temp_voltage( + adcmap_qrd_btm_threshold, + ARRAY_SIZE(adcmap_qrd_btm_threshold), + bat_voltage, + &adc_chan_result->physical); +} +EXPORT_SYMBOL(qpnp_adc_scale_qrd_batt_therm); + +int32_t qpnp_adc_scale_qrd_skuaa_batt_therm(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t bat_voltage = 0; + + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &bat_voltage); + + adc_chan_result->measurement = bat_voltage; + + return qpnp_adc_map_temp_voltage( + adcmap_qrd_skuaa_btm_threshold, + ARRAY_SIZE(adcmap_qrd_skuaa_btm_threshold), + bat_voltage, + &adc_chan_result->physical); +} +EXPORT_SYMBOL(qpnp_adc_scale_qrd_skuaa_batt_therm); + +int32_t qpnp_adc_scale_qrd_skug_batt_therm(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t bat_voltage = 0; + + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &bat_voltage); + adc_chan_result->measurement = bat_voltage; + + return qpnp_adc_map_temp_voltage( + adcmap_qrd_skug_btm_threshold, + ARRAY_SIZE(adcmap_qrd_skug_btm_threshold), + bat_voltage, + &adc_chan_result->physical); +} +EXPORT_SYMBOL(qpnp_adc_scale_qrd_skug_batt_therm); + +int32_t qpnp_adc_scale_qrd_skuh_batt_therm(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t bat_voltage = 0; + + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &bat_voltage); + + return qpnp_adc_map_temp_voltage( + adcmap_qrd_skuh_btm_threshold, + ARRAY_SIZE(adcmap_qrd_skuh_btm_threshold), + bat_voltage, + &adc_chan_result->physical); +} +EXPORT_SYMBOL(qpnp_adc_scale_qrd_skuh_batt_therm); + +int32_t qpnp_adc_scale_qrd_skut1_batt_therm(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t bat_voltage = 0; + + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &bat_voltage); + + return qpnp_adc_map_temp_voltage( + adcmap_qrd_skut1_btm_threshold, + ARRAY_SIZE(adcmap_qrd_skut1_btm_threshold), + bat_voltage, + &adc_chan_result->physical); +} +EXPORT_SYMBOL(qpnp_adc_scale_qrd_skut1_batt_therm); + +int32_t qpnp_adc_scale_smb_batt_therm(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t bat_voltage = 0; + + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &bat_voltage); + + return qpnp_adc_map_temp_voltage( + adcmap_smb_batt_therm, + ARRAY_SIZE(adcmap_smb_batt_therm), + bat_voltage, + &adc_chan_result->physical); +} +EXPORT_SYMBOL(qpnp_adc_scale_smb_batt_therm); + +int32_t qpnp_adc_scale_therm_pu1(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t therm_voltage = 0; + + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &therm_voltage); + + qpnp_adc_map_voltage_temp(adcmap_150k_104ef_104fb, + ARRAY_SIZE(adcmap_150k_104ef_104fb), + therm_voltage, &adc_chan_result->physical); + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_scale_therm_pu1); + +int32_t qpnp_adc_scale_therm_pu2(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t therm_voltage = 0; + + if (!chan_properties || !chan_properties->offset_gain_numerator || + !chan_properties->offset_gain_denominator || !adc_properties) + return -EINVAL; + + if (adc_properties->adc_hc) { + /* (ADC code * vref_vadc (1.875V) * 1000) / (0x4000 * 1000) */ + if (adc_code > QPNP_VADC_HC_MAX_CODE) + adc_code = 0; + therm_voltage = (int64_t) adc_code; + therm_voltage *= (int64_t) (adc_properties->adc_vdd_reference + * 1000); + therm_voltage = div64_s64(therm_voltage, + (QPNP_VADC_HC_VREF_CODE * 1000)); + + qpnp_adc_map_voltage_temp(adcmap_100k_104ef_104fb_1875_vref, + ARRAY_SIZE(adcmap_100k_104ef_104fb_1875_vref), + therm_voltage, &adc_chan_result->physical); + } else { + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &therm_voltage); + + if (chan_properties->calib_type == CALIB_ABSOLUTE) + do_div(therm_voltage, 1000); + + qpnp_adc_map_voltage_temp(adcmap_100k_104ef_104fb, + ARRAY_SIZE(adcmap_100k_104ef_104fb), + therm_voltage, &adc_chan_result->physical); + } + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_scale_therm_pu2); + +int32_t qpnp_adc_tm_scale_voltage_therm_pu2(struct qpnp_vadc_chip *chip, + const struct qpnp_adc_properties *adc_properties, + uint32_t reg, int64_t *result) +{ + int64_t adc_voltage = 0; + struct qpnp_vadc_linear_graph param1; + int negative_offset = 0; + + if (adc_properties->adc_hc) { + /* (ADC code * vref_vadc (1.875V)) / 0x4000 */ + if (reg > QPNP_VADC_HC_MAX_CODE) + reg = 0; + adc_voltage = (int64_t) reg; + adc_voltage *= QPNP_VADC_HC_VDD_REFERENCE_MV; + adc_voltage = div64_s64(adc_voltage, + QPNP_VADC_HC_VREF_CODE); + qpnp_adc_map_voltage_temp(adcmap_100k_104ef_104fb_1875_vref, + ARRAY_SIZE(adcmap_100k_104ef_104fb_1875_vref), + adc_voltage, result); + } else { + qpnp_get_vadc_gain_and_offset(chip, ¶m1, CALIB_RATIOMETRIC); + + adc_voltage = (reg - param1.adc_gnd) * param1.adc_vref; + if (adc_voltage < 0) { + negative_offset = 1; + adc_voltage = -adc_voltage; + } + + do_div(adc_voltage, param1.dy); + + qpnp_adc_map_voltage_temp(adcmap_100k_104ef_104fb, + ARRAY_SIZE(adcmap_100k_104ef_104fb), + adc_voltage, result); + if (negative_offset) + adc_voltage = -adc_voltage; + } + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_tm_scale_voltage_therm_pu2); + +int32_t qpnp_adc_tm_scale_therm_voltage_pu2(struct qpnp_vadc_chip *chip, + const struct qpnp_adc_properties *adc_properties, + struct qpnp_adc_tm_config *param) +{ + struct qpnp_vadc_linear_graph param1; + int rc; + + if (adc_properties->adc_hc) { + rc = qpnp_adc_map_temp_voltage( + adcmap_100k_104ef_104fb_1875_vref, + ARRAY_SIZE(adcmap_100k_104ef_104fb_1875_vref), + param->low_thr_temp, ¶m->low_thr_voltage); + if (rc) + return rc; + param->low_thr_voltage *= QPNP_VADC_HC_VREF_CODE; + do_div(param->low_thr_voltage, QPNP_VADC_HC_VDD_REFERENCE_MV); + + rc = qpnp_adc_map_temp_voltage( + adcmap_100k_104ef_104fb_1875_vref, + ARRAY_SIZE(adcmap_100k_104ef_104fb_1875_vref), + param->high_thr_temp, ¶m->high_thr_voltage); + if (rc) + return rc; + param->high_thr_voltage *= QPNP_VADC_HC_VREF_CODE; + do_div(param->high_thr_voltage, QPNP_VADC_HC_VDD_REFERENCE_MV); + } else { + qpnp_get_vadc_gain_and_offset(chip, ¶m1, CALIB_RATIOMETRIC); + + rc = qpnp_adc_map_temp_voltage(adcmap_100k_104ef_104fb, + ARRAY_SIZE(adcmap_100k_104ef_104fb), + param->low_thr_temp, ¶m->low_thr_voltage); + if (rc) + return rc; + + param->low_thr_voltage *= param1.dy; + do_div(param->low_thr_voltage, param1.adc_vref); + param->low_thr_voltage += param1.adc_gnd; + + rc = qpnp_adc_map_temp_voltage(adcmap_100k_104ef_104fb, + ARRAY_SIZE(adcmap_100k_104ef_104fb), + param->high_thr_temp, ¶m->high_thr_voltage); + if (rc) + return rc; + + param->high_thr_voltage *= param1.dy; + do_div(param->high_thr_voltage, param1.adc_vref); + param->high_thr_voltage += param1.adc_gnd; + } + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_tm_scale_therm_voltage_pu2); + +int32_t qpnp_adc_scale_therm_ncp03(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t therm_voltage = 0; + + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &therm_voltage); + + qpnp_adc_map_voltage_temp(adcmap_ncp03wf683, + ARRAY_SIZE(adcmap_ncp03wf683), + therm_voltage, &adc_chan_result->physical); + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_scale_therm_ncp03); + +int32_t qpnp_adc_scale_batt_id(struct qpnp_vadc_chip *chip, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t batt_id_voltage = 0; + + qpnp_adc_scale_with_calib_param(adc_code, + adc_properties, chan_properties, &batt_id_voltage); + + adc_chan_result->physical = batt_id_voltage; + adc_chan_result->physical = adc_chan_result->measurement; + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_scale_batt_id); + +int32_t qpnp_adc_scale_default(struct qpnp_vadc_chip *vadc, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int64_t scale_voltage = 0; + + if (!chan_properties || !chan_properties->offset_gain_numerator || + !chan_properties->offset_gain_denominator || !adc_properties + || !adc_chan_result) + return -EINVAL; + + if (adc_properties->adc_hc) { + /* (ADC code * vref_vadc (1.875V)) / 0x4000 */ + if (adc_code > QPNP_VADC_HC_MAX_CODE) + adc_code = 0; + scale_voltage = (int64_t) adc_code; + scale_voltage *= (adc_properties->adc_vdd_reference * 1000); + scale_voltage = div64_s64(scale_voltage, + QPNP_VADC_HC_VREF_CODE); + } else { + qpnp_adc_scale_with_calib_param(adc_code, adc_properties, + chan_properties, &scale_voltage); + if (!(chan_properties->calib_type == CALIB_ABSOLUTE)) + scale_voltage *= 1000; + } + + + scale_voltage *= chan_properties->offset_gain_denominator; + scale_voltage = div64_s64(scale_voltage, + chan_properties->offset_gain_numerator); + adc_chan_result->measurement = scale_voltage; + /* + * Note: adc_chan_result->measurement is in the unit of + * adc_properties.adc_reference. For generic channel processing, + * channel measurement is a scale/ratio relative to the adc + * reference input + */ + adc_chan_result->physical = adc_chan_result->measurement; + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_scale_default); + +int32_t qpnp_adc_usb_scaler(struct qpnp_vadc_chip *chip, + struct qpnp_adc_tm_btm_param *param, + uint32_t *low_threshold, uint32_t *high_threshold) +{ + struct qpnp_vadc_linear_graph usb_param; + + qpnp_get_vadc_gain_and_offset(chip, &usb_param, CALIB_RATIOMETRIC); + + *low_threshold = param->low_thr * usb_param.dy; + do_div(*low_threshold, usb_param.adc_vref); + *low_threshold += usb_param.adc_gnd; + + *high_threshold = param->high_thr * usb_param.dy; + do_div(*high_threshold, usb_param.adc_vref); + *high_threshold += usb_param.adc_gnd; + + pr_debug("high_volt:%d, low_volt:%d\n", param->high_thr, + param->low_thr); + return 0; +} +EXPORT_SYMBOL(qpnp_adc_usb_scaler); + +int32_t qpnp_adc_absolute_rthr(struct qpnp_vadc_chip *chip, + struct qpnp_adc_tm_btm_param *param, + uint32_t *low_threshold, uint32_t *high_threshold) +{ + struct qpnp_vadc_linear_graph vbatt_param; + int rc = 0, sign = 0; + int64_t low_thr = 0, high_thr = 0; + + if (param->adc_tm_hc) { + low_thr = (param->low_thr/param->gain_den); + low_thr *= param->gain_num; + low_thr *= QPNP_VADC_HC_VREF_CODE; + do_div(low_thr, (QPNP_VADC_HC_VDD_REFERENCE_MV * 1000)); + *low_threshold = low_thr; + + high_thr = (param->high_thr/param->gain_den); + high_thr *= param->gain_num; + high_thr *= QPNP_VADC_HC_VREF_CODE; + do_div(high_thr, (QPNP_VADC_HC_VDD_REFERENCE_MV * 1000)); + *high_threshold = high_thr; + } else { + rc = qpnp_get_vadc_gain_and_offset(chip, &vbatt_param, + CALIB_ABSOLUTE); + if (rc < 0) + return rc; + + low_thr = (((param->low_thr/param->gain_den) - + QPNP_ADC_625_UV) * vbatt_param.dy); + if (low_thr < 0) { + sign = 1; + low_thr = -low_thr; + } + low_thr = low_thr * param->gain_num; + do_div(low_thr, QPNP_ADC_625_UV); + if (sign) + low_thr = -low_thr; + *low_threshold = low_thr + vbatt_param.adc_gnd; + + sign = 0; + high_thr = (((param->high_thr/param->gain_den) - + QPNP_ADC_625_UV) * vbatt_param.dy); + if (high_thr < 0) { + sign = 1; + high_thr = -high_thr; + } + high_thr = high_thr * param->gain_num; + do_div(high_thr, QPNP_ADC_625_UV); + if (sign) + high_thr = -high_thr; + *high_threshold = high_thr + vbatt_param.adc_gnd; + } + + pr_debug("high_volt:%d, low_volt:%d\n", param->high_thr, + param->low_thr); + pr_debug("adc_code_high:%x, adc_code_low:%x\n", *high_threshold, + *low_threshold); + return 0; +} +EXPORT_SYMBOL(qpnp_adc_absolute_rthr); + +int32_t qpnp_adc_vbatt_rscaler(struct qpnp_vadc_chip *chip, + struct qpnp_adc_tm_btm_param *param, + uint32_t *low_threshold, uint32_t *high_threshold) +{ + return qpnp_adc_absolute_rthr(chip, param, low_threshold, + high_threshold); +} +EXPORT_SYMBOL(qpnp_adc_vbatt_rscaler); + +int32_t qpnp_vadc_absolute_rthr(struct qpnp_vadc_chip *chip, + const struct qpnp_vadc_chan_properties *chan_prop, + struct qpnp_adc_tm_btm_param *param, + uint32_t *low_threshold, uint32_t *high_threshold) +{ + struct qpnp_vadc_linear_graph vbatt_param; + int rc = 0, sign = 0; + int64_t low_thr = 0, high_thr = 0; + + if (!chan_prop || !chan_prop->offset_gain_numerator || + !chan_prop->offset_gain_denominator) + return -EINVAL; + + rc = qpnp_get_vadc_gain_and_offset(chip, &vbatt_param, CALIB_ABSOLUTE); + if (rc < 0) + return rc; + + low_thr = (((param->low_thr)/(int)chan_prop->offset_gain_denominator + - QPNP_ADC_625_UV) * vbatt_param.dy); + if (low_thr < 0) { + sign = 1; + low_thr = -low_thr; + } + low_thr = low_thr * chan_prop->offset_gain_numerator; + do_div(low_thr, QPNP_ADC_625_UV); + if (sign) + low_thr = -low_thr; + *low_threshold = low_thr + vbatt_param.adc_gnd; + + sign = 0; + high_thr = (((param->high_thr)/(int)chan_prop->offset_gain_denominator + - QPNP_ADC_625_UV) * vbatt_param.dy); + if (high_thr < 0) { + sign = 1; + high_thr = -high_thr; + } + high_thr = high_thr * chan_prop->offset_gain_numerator; + do_div(high_thr, QPNP_ADC_625_UV); + if (sign) + high_thr = -high_thr; + *high_threshold = high_thr + vbatt_param.adc_gnd; + + pr_debug("high_volt:%d, low_volt:%d\n", param->high_thr, + param->low_thr); + pr_debug("adc_code_high:%x, adc_code_low:%x\n", *high_threshold, + *low_threshold); + return 0; +} +EXPORT_SYMBOL(qpnp_vadc_absolute_rthr); + +int32_t qpnp_adc_btm_scaler(struct qpnp_vadc_chip *chip, + struct qpnp_adc_tm_btm_param *param, + uint32_t *low_threshold, uint32_t *high_threshold) +{ + struct qpnp_vadc_linear_graph btm_param; + int64_t low_output = 0, high_output = 0; + int rc = 0; + + if (param->adc_tm_hc) { + pr_err("Update scaling for VADC_TM_HC\n"); + return -EINVAL; + } + + qpnp_get_vadc_gain_and_offset(chip, &btm_param, CALIB_RATIOMETRIC); + + pr_debug("warm_temp:%d and cool_temp:%d\n", param->high_temp, + param->low_temp); + rc = qpnp_adc_map_voltage_temp( + adcmap_btm_threshold, + ARRAY_SIZE(adcmap_btm_threshold), + (param->low_temp), + &low_output); + if (rc) { + pr_debug("low_temp mapping failed with %d\n", rc); + return rc; + } + + pr_debug("low_output:%lld\n", low_output); + low_output *= btm_param.dy; + do_div(low_output, btm_param.adc_vref); + low_output += btm_param.adc_gnd; + + rc = qpnp_adc_map_voltage_temp( + adcmap_btm_threshold, + ARRAY_SIZE(adcmap_btm_threshold), + (param->high_temp), + &high_output); + if (rc) { + pr_debug("high temp mapping failed with %d\n", rc); + return rc; + } + + pr_debug("high_output:%lld\n", high_output); + high_output *= btm_param.dy; + do_div(high_output, btm_param.adc_vref); + high_output += btm_param.adc_gnd; + + /* btm low temperature correspondes to high voltage threshold */ + *low_threshold = high_output; + /* btm high temperature correspondes to low voltage threshold */ + *high_threshold = low_output; + + pr_debug("high_volt:%d, low_volt:%d\n", *high_threshold, + *low_threshold); + return 0; +} +EXPORT_SYMBOL(qpnp_adc_btm_scaler); + +int32_t qpnp_adc_qrd_skuh_btm_scaler(struct qpnp_vadc_chip *chip, + struct qpnp_adc_tm_btm_param *param, + uint32_t *low_threshold, uint32_t *high_threshold) +{ + struct qpnp_vadc_linear_graph btm_param; + int64_t low_output = 0, high_output = 0; + int rc = 0; + + if (param->adc_tm_hc) { + pr_err("Update scaling for VADC_TM_HC\n"); + return -EINVAL; + } + + qpnp_get_vadc_gain_and_offset(chip, &btm_param, CALIB_RATIOMETRIC); + + pr_debug("warm_temp:%d and cool_temp:%d\n", param->high_temp, + param->low_temp); + rc = qpnp_adc_map_voltage_temp( + adcmap_qrd_skuh_btm_threshold, + ARRAY_SIZE(adcmap_qrd_skuh_btm_threshold), + (param->low_temp), + &low_output); + if (rc) { + pr_debug("low_temp mapping failed with %d\n", rc); + return rc; + } + + pr_debug("low_output:%lld\n", low_output); + low_output *= btm_param.dy; + do_div(low_output, btm_param.adc_vref); + low_output += btm_param.adc_gnd; + + rc = qpnp_adc_map_voltage_temp( + adcmap_qrd_skuh_btm_threshold, + ARRAY_SIZE(adcmap_qrd_skuh_btm_threshold), + (param->high_temp), + &high_output); + if (rc) { + pr_debug("high temp mapping failed with %d\n", rc); + return rc; + } + + pr_debug("high_output:%lld\n", high_output); + high_output *= btm_param.dy; + do_div(high_output, btm_param.adc_vref); + high_output += btm_param.adc_gnd; + + /* btm low temperature correspondes to high voltage threshold */ + *low_threshold = high_output; + /* btm high temperature correspondes to low voltage threshold */ + *high_threshold = low_output; + + pr_debug("high_volt:%d, low_volt:%d\n", *high_threshold, + *low_threshold); + return 0; +} +EXPORT_SYMBOL(qpnp_adc_qrd_skuh_btm_scaler); + +int32_t qpnp_adc_qrd_skut1_btm_scaler(struct qpnp_vadc_chip *chip, + struct qpnp_adc_tm_btm_param *param, + uint32_t *low_threshold, uint32_t *high_threshold) +{ + struct qpnp_vadc_linear_graph btm_param; + int64_t low_output = 0, high_output = 0; + int rc = 0; + + if (param->adc_tm_hc) { + pr_err("Update scaling for VADC_TM_HC\n"); + return -EINVAL; + } + + qpnp_get_vadc_gain_and_offset(chip, &btm_param, CALIB_RATIOMETRIC); + + pr_debug("warm_temp:%d and cool_temp:%d\n", param->high_temp, + param->low_temp); + rc = qpnp_adc_map_voltage_temp( + adcmap_qrd_skut1_btm_threshold, + ARRAY_SIZE(adcmap_qrd_skut1_btm_threshold), + (param->low_temp), + &low_output); + if (rc) { + pr_debug("low_temp mapping failed with %d\n", rc); + return rc; + } + + pr_debug("low_output:%lld\n", low_output); + low_output *= btm_param.dy; + do_div(low_output, btm_param.adc_vref); + low_output += btm_param.adc_gnd; + + rc = qpnp_adc_map_voltage_temp( + adcmap_qrd_skut1_btm_threshold, + ARRAY_SIZE(adcmap_qrd_skut1_btm_threshold), + (param->high_temp), + &high_output); + if (rc) { + pr_debug("high temp mapping failed with %d\n", rc); + return rc; + } + + pr_debug("high_output:%lld\n", high_output); + high_output *= btm_param.dy; + do_div(high_output, btm_param.adc_vref); + high_output += btm_param.adc_gnd; + + /* btm low temperature correspondes to high voltage threshold */ + *low_threshold = high_output; + /* btm high temperature correspondes to low voltage threshold */ + *high_threshold = low_output; + + pr_debug("high_volt:%d, low_volt:%d\n", *high_threshold, + *low_threshold); + return 0; +} +EXPORT_SYMBOL(qpnp_adc_qrd_skut1_btm_scaler); + +int32_t qpnp_adc_smb_btm_rscaler(struct qpnp_vadc_chip *chip, + struct qpnp_adc_tm_btm_param *param, + uint32_t *low_threshold, uint32_t *high_threshold) +{ + struct qpnp_vadc_linear_graph btm_param; + int64_t low_output = 0, high_output = 0; + int rc = 0; + + if (param->adc_tm_hc) { + pr_err("Update scaling for VADC_TM_HC\n"); + return -EINVAL; + } + + qpnp_get_vadc_gain_and_offset(chip, &btm_param, CALIB_RATIOMETRIC); + + pr_debug("warm_temp:%d and cool_temp:%d\n", param->high_temp, + param->low_temp); + rc = qpnp_adc_map_voltage_temp( + adcmap_smb_batt_therm, + ARRAY_SIZE(adcmap_smb_batt_therm), + (param->low_temp), + &low_output); + if (rc) { + pr_debug("low_temp mapping failed with %d\n", rc); + return rc; + } + + pr_debug("low_output:%lld\n", low_output); + low_output *= btm_param.dy; + do_div(low_output, btm_param.adc_vref); + low_output += btm_param.adc_gnd; + + rc = qpnp_adc_map_voltage_temp( + adcmap_smb_batt_therm, + ARRAY_SIZE(adcmap_smb_batt_therm), + (param->high_temp), + &high_output); + if (rc) { + pr_debug("high temp mapping failed with %d\n", rc); + return rc; + } + + pr_debug("high_output:%lld\n", high_output); + high_output *= btm_param.dy; + do_div(high_output, btm_param.adc_vref); + high_output += btm_param.adc_gnd; + + /* btm low temperature correspondes to high voltage threshold */ + *low_threshold = high_output; + /* btm high temperature correspondes to low voltage threshold */ + *high_threshold = low_output; + + pr_debug("high_volt:%d, low_volt:%d\n", *high_threshold, + *low_threshold); + return 0; +} +EXPORT_SYMBOL(qpnp_adc_smb_btm_rscaler); + +int32_t qpnp_adc_scale_pmi_chg_temp(struct qpnp_vadc_chip *vadc, + int32_t adc_code, + const struct qpnp_adc_properties *adc_properties, + const struct qpnp_vadc_chan_properties *chan_properties, + struct qpnp_vadc_result *adc_chan_result) +{ + int rc = 0; + + rc = qpnp_adc_scale_default(vadc, adc_code, adc_properties, + chan_properties, adc_chan_result); + if (rc < 0) + return rc; + + pr_debug("raw_code:%x, v_adc:%lld\n", adc_code, + adc_chan_result->physical); + adc_chan_result->physical = (int64_t) ((PMI_CHG_SCALE_1) * + (adc_chan_result->physical * 2)); + adc_chan_result->physical = (int64_t) (adc_chan_result->physical + + PMI_CHG_SCALE_2); + adc_chan_result->physical = (int64_t) adc_chan_result->physical; + adc_chan_result->physical = div64_s64(adc_chan_result->physical, + 1000000); + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_scale_pmi_chg_temp); + +int32_t qpnp_adc_enable_voltage(struct qpnp_adc_drv *adc) +{ + int rc = 0; + + if (adc->hkadc_ldo) { + rc = regulator_enable(adc->hkadc_ldo); + if (rc < 0) { + pr_err("Failed to enable hkadc ldo\n"); + return rc; + } + } + + if (adc->hkadc_ldo_ok) { + rc = regulator_enable(adc->hkadc_ldo_ok); + if (rc < 0) { + pr_err("Failed to enable hkadc ok signal\n"); + return rc; + } + } + + return rc; +} +EXPORT_SYMBOL(qpnp_adc_enable_voltage); + +void qpnp_adc_disable_voltage(struct qpnp_adc_drv *adc) +{ + if (adc->hkadc_ldo) + regulator_disable(adc->hkadc_ldo); + + if (adc->hkadc_ldo_ok) + regulator_disable(adc->hkadc_ldo_ok); + +} +EXPORT_SYMBOL(qpnp_adc_disable_voltage); + +void qpnp_adc_free_voltage_resource(struct qpnp_adc_drv *adc) +{ + if (adc->hkadc_ldo) + regulator_put(adc->hkadc_ldo); + + if (adc->hkadc_ldo_ok) + regulator_put(adc->hkadc_ldo_ok); +} +EXPORT_SYMBOL(qpnp_adc_free_voltage_resource); + +int qpnp_adc_get_revid_version(struct device *dev) +{ + struct pmic_revid_data *revid_data; + struct device_node *revid_dev_node; + + revid_dev_node = of_parse_phandle(dev->of_node, + "qcom,pmic-revid", 0); + if (!revid_dev_node) { + pr_debug("Missing qcom,pmic-revid property\n"); + return -EINVAL; + } + + revid_data = get_revid_data(revid_dev_node); + if (IS_ERR_OR_NULL(revid_data)) { + pr_debug("revid error rc = %ld\n", PTR_ERR(revid_data)); + return -EINVAL; + } + + if ((revid_data->rev1 == PM8941_V3P1_REV1) && + (revid_data->rev2 == PM8941_V3P1_REV2) && + (revid_data->rev3 == PM8941_V3P1_REV3) && + (revid_data->rev4 == PM8941_V3P1_REV4) && + (revid_data->pmic_subtype == PM8941_SUBTYPE)) + return QPNP_REV_ID_8941_3_1; + else if ((revid_data->rev1 == PM8941_V3P0_REV1) && + (revid_data->rev2 == PM8941_V3P0_REV2) && + (revid_data->rev3 == PM8941_V3P0_REV3) && + (revid_data->rev4 == PM8941_V3P0_REV4) && + (revid_data->pmic_subtype == PM8941_SUBTYPE)) + return QPNP_REV_ID_8941_3_0; + else if ((revid_data->rev1 == PM8941_V2P0_REV1) && + (revid_data->rev2 == PM8941_V2P0_REV2) && + (revid_data->rev3 == PM8941_V2P0_REV3) && + (revid_data->rev4 == PM8941_V2P0_REV4) && + (revid_data->pmic_subtype == PM8941_SUBTYPE)) + return QPNP_REV_ID_8941_2_0; + else if ((revid_data->rev1 == PM8226_V2P2_REV1) && + (revid_data->rev2 == PM8226_V2P2_REV2) && + (revid_data->rev3 == PM8226_V2P2_REV3) && + (revid_data->rev4 == PM8226_V2P2_REV4) && + (revid_data->pmic_subtype == PM8226_SUBTYPE)) + return QPNP_REV_ID_8026_2_2; + else if ((revid_data->rev1 == PM8226_V2P1_REV1) && + (revid_data->rev2 == PM8226_V2P1_REV2) && + (revid_data->rev3 == PM8226_V2P1_REV3) && + (revid_data->rev4 == PM8226_V2P1_REV4) && + (revid_data->pmic_subtype == PM8226_SUBTYPE)) + return QPNP_REV_ID_8026_2_1; + else if ((revid_data->rev1 == PM8226_V2P0_REV1) && + (revid_data->rev2 == PM8226_V2P0_REV2) && + (revid_data->rev3 == PM8226_V2P0_REV3) && + (revid_data->rev4 == PM8226_V2P0_REV4) && + (revid_data->pmic_subtype == PM8226_SUBTYPE)) + return QPNP_REV_ID_8026_2_0; + else if ((revid_data->rev1 == PM8226_V1P0_REV1) && + (revid_data->rev2 == PM8226_V1P0_REV2) && + (revid_data->rev3 == PM8226_V1P0_REV3) && + (revid_data->rev4 == PM8226_V1P0_REV4) && + (revid_data->pmic_subtype == PM8226_SUBTYPE)) + return QPNP_REV_ID_8026_1_0; + else if ((revid_data->rev1 == PM8110_V1P0_REV1) && + (revid_data->rev2 == PM8110_V1P0_REV2) && + (revid_data->rev3 == PM8110_V1P0_REV3) && + (revid_data->rev4 == PM8110_V1P0_REV4) && + (revid_data->pmic_subtype == PM8110_SUBTYPE)) + return QPNP_REV_ID_8110_1_0; + else if ((revid_data->rev1 == PM8110_V2P0_REV1) && + (revid_data->rev2 == PM8110_V2P0_REV2) && + (revid_data->rev3 == PM8110_V2P0_REV3) && + (revid_data->rev4 == PM8110_V2P0_REV4) && + (revid_data->pmic_subtype == PM8110_SUBTYPE)) + return QPNP_REV_ID_8110_2_0; + else if ((revid_data->rev1 == PM8916_V1P0_REV1) && + (revid_data->rev2 == PM8916_V1P0_REV2) && + (revid_data->rev3 == PM8916_V1P0_REV3) && + (revid_data->rev4 == PM8916_V1P0_REV4) && + (revid_data->pmic_subtype == PM8916_SUBTYPE)) + return QPNP_REV_ID_8916_1_0; + else if ((revid_data->rev1 == PM8916_V1P1_REV1) && + (revid_data->rev2 == PM8916_V1P1_REV2) && + (revid_data->rev3 == PM8916_V1P1_REV3) && + (revid_data->rev4 == PM8916_V1P1_REV4) && + (revid_data->pmic_subtype == PM8916_SUBTYPE)) + return QPNP_REV_ID_8916_1_1; + else if ((revid_data->rev1 == PM8916_V2P0_REV1) && + (revid_data->rev2 == PM8916_V2P0_REV2) && + (revid_data->rev3 == PM8916_V2P0_REV3) && + (revid_data->rev4 == PM8916_V2P0_REV4) && + (revid_data->pmic_subtype == PM8916_SUBTYPE)) + return QPNP_REV_ID_8916_2_0; + else if ((revid_data->rev1 == PM8909_V1P0_REV1) && + (revid_data->rev2 == PM8909_V1P0_REV2) && + (revid_data->rev3 == PM8909_V1P0_REV3) && + (revid_data->rev4 == PM8909_V1P0_REV4) && + (revid_data->pmic_subtype == PM8909_SUBTYPE)) + return QPNP_REV_ID_8909_1_0; + else if ((revid_data->rev1 == PM8909_V1P1_REV1) && + (revid_data->rev2 == PM8909_V1P1_REV2) && + (revid_data->rev3 == PM8909_V1P1_REV3) && + (revid_data->rev4 == PM8909_V1P1_REV4) && + (revid_data->pmic_subtype == PM8909_SUBTYPE)) + return QPNP_REV_ID_8909_1_1; + else if ((revid_data->rev4 == PM8950_V1P0_REV4) && + (revid_data->pmic_subtype == PM8950_SUBTYPE)) + return QPNP_REV_ID_PM8950_1_0; + else + return -EINVAL; +} +EXPORT_SYMBOL(qpnp_adc_get_revid_version); + +int32_t qpnp_adc_get_devicetree_data(struct platform_device *pdev, + struct qpnp_adc_drv *adc_qpnp) +{ + struct device_node *node = pdev->dev.of_node; + unsigned int base; + struct device_node *child; + struct qpnp_adc_amux *adc_channel_list; + struct qpnp_adc_properties *adc_prop; + struct qpnp_adc_amux_properties *amux_prop; + int count_adc_channel_list = 0, decimation = 0, rc = 0, i = 0; + int decimation_tm_hc = 0, fast_avg_setup_tm_hc = 0, cal_val_hc = 0; + bool adc_hc; + + if (!node) + return -EINVAL; + + for_each_child_of_node(node, child) + count_adc_channel_list++; + + if (!count_adc_channel_list) { + pr_err("No channel listing\n"); + return -EINVAL; + } + + adc_qpnp->pdev = pdev; + + adc_prop = devm_kzalloc(&pdev->dev, + sizeof(struct qpnp_adc_properties), + GFP_KERNEL); + if (!adc_prop) + return -ENOMEM; + + adc_channel_list = devm_kzalloc(&pdev->dev, + ((sizeof(struct qpnp_adc_amux)) * count_adc_channel_list), + GFP_KERNEL); + if (!adc_channel_list) + return -ENOMEM; + + amux_prop = devm_kzalloc(&pdev->dev, + sizeof(struct qpnp_adc_amux_properties) + + sizeof(struct qpnp_vadc_chan_properties), GFP_KERNEL); + if (!amux_prop) { + dev_err(&pdev->dev, "Unable to allocate memory\n"); + return -ENOMEM; + } + + adc_qpnp->adc_channels = adc_channel_list; + adc_qpnp->amux_prop = amux_prop; + adc_hc = adc_qpnp->adc_hc; + adc_prop->adc_hc = adc_hc; + + if (of_device_is_compatible(node, "qcom,qpnp-adc-tm-hc")) { + rc = of_property_read_u32(node, "qcom,decimation", + &decimation_tm_hc); + if (rc) { + pr_err("Invalid decimation property\n"); + return -EINVAL; + } + + rc = of_property_read_u32(node, + "qcom,fast-avg-setup", &fast_avg_setup_tm_hc); + if (rc) { + pr_err("Invalid fast average setup with %d\n", rc); + return -EINVAL; + } + + if ((fast_avg_setup_tm_hc) > ADC_FAST_AVG_SAMPLE_16) { + pr_err("Max average support is 2^16\n"); + return -EINVAL; + } + } + + for_each_child_of_node(node, child) { + int channel_num, scaling = 0, post_scaling = 0; + int fast_avg_setup, calib_type = 0, rc, hw_settle_time = 0; + const char *calibration_param, *channel_name; + + channel_name = of_get_property(child, + "label", NULL) ? : child->name; + if (!channel_name) { + pr_err("Invalid channel name\n"); + return -EINVAL; + } + + rc = of_property_read_u32(child, "reg", &channel_num); + if (rc) { + pr_err("Invalid channel num\n"); + return -EINVAL; + } + + if (!of_device_is_compatible(node, "qcom,qpnp-iadc")) { + rc = of_property_read_u32(child, + "qcom,hw-settle-time", &hw_settle_time); + if (rc) { + pr_err("Invalid channel hw settle time property\n"); + return -EINVAL; + } + rc = of_property_read_u32(child, + "qcom,pre-div-channel-scaling", &scaling); + if (rc) { + pr_err("Invalid channel scaling property\n"); + return -EINVAL; + } + rc = of_property_read_u32(child, + "qcom,scale-function", &post_scaling); + if (rc) { + pr_err("Invalid channel post scaling property\n"); + return -EINVAL; + } + rc = of_property_read_string(child, + "qcom,calibration-type", &calibration_param); + if (rc) { + pr_err("Invalid calibration type\n"); + return -EINVAL; + } + + if (!strcmp(calibration_param, "absolute")) { + if (adc_hc) + calib_type = ADC_HC_ABS_CAL; + else + calib_type = CALIB_ABSOLUTE; + } else if (!strcmp(calibration_param, "ratiometric")) { + if (adc_hc) + calib_type = ADC_HC_RATIO_CAL; + else + calib_type = CALIB_RATIOMETRIC; + } else if (!strcmp(calibration_param, "no_cal")) { + if (adc_hc) + calib_type = ADC_HC_NO_CAL; + else { + pr_err("%s: Invalid calibration property\n", + __func__); + return -EINVAL; + } + } else { + pr_err("%s: Invalid calibration property\n", + __func__); + return -EINVAL; + } + } + + /* ADC_TM_HC fast avg setting is common across channels */ + if (!of_device_is_compatible(node, "qcom,qpnp-adc-tm-hc")) { + rc = of_property_read_u32(child, + "qcom,fast-avg-setup", &fast_avg_setup); + if (rc) { + pr_err("Invalid channel fast average setup\n"); + return -EINVAL; + } + } else { + fast_avg_setup = fast_avg_setup_tm_hc; + } + + /* ADC_TM_HC decimation setting is common across channels */ + if (!of_device_is_compatible(node, "qcom,qpnp-adc-tm-hc")) { + rc = of_property_read_u32(child, + "qcom,decimation", &decimation); + if (rc) { + pr_err("Invalid decimation\n"); + return -EINVAL; + } + } else { + decimation = decimation_tm_hc; + } + + if (of_device_is_compatible(node, "qcom,qpnp-vadc-hc")) { + rc = of_property_read_u32(child, "qcom,cal-val", + &cal_val_hc); + if (rc) { + pr_debug("Use calibration value from timer\n"); + adc_channel_list[i].cal_val = ADC_TIMER_CAL; + } else { + adc_channel_list[i].cal_val = cal_val_hc; + } + } + + /* Individual channel properties */ + adc_channel_list[i].name = (char *)channel_name; + adc_channel_list[i].channel_num = channel_num; + adc_channel_list[i].adc_decimation = decimation; + adc_channel_list[i].fast_avg_setup = fast_avg_setup; + if (!of_device_is_compatible(node, "qcom,qpnp-iadc")) { + adc_channel_list[i].chan_path_prescaling = scaling; + adc_channel_list[i].adc_scale_fn = post_scaling; + adc_channel_list[i].hw_settle_time = hw_settle_time; + adc_channel_list[i].calib_type = calib_type; + } + i++; + } + + /* Get the ADC VDD reference voltage and ADC bit resolution */ + rc = of_property_read_u32(node, "qcom,adc-vdd-reference", + &adc_prop->adc_vdd_reference); + if (rc) { + pr_err("Invalid adc vdd reference property\n"); + return -EINVAL; + } + rc = of_property_read_u32(node, "qcom,adc-bit-resolution", + &adc_prop->bitresolution); + if (rc) { + pr_err("Invalid adc bit resolution property\n"); + return -EINVAL; + } + adc_qpnp->adc_prop = adc_prop; + + /* Get the peripheral address */ + rc = of_property_read_u32(pdev->dev.of_node, "reg", &base); + if (rc < 0) { + dev_err(&pdev->dev, + "Couldn't find reg in node = %s rc = %d\n", + pdev->dev.of_node->full_name, rc); + return rc; + } + + adc_qpnp->slave = to_spmi_device(pdev->dev.parent)->usid; + adc_qpnp->offset = base; + + /* Register the ADC peripheral interrupt */ + adc_qpnp->adc_irq_eoc = platform_get_irq_byname(pdev, + "eoc-int-en-set"); + if (adc_qpnp->adc_irq_eoc < 0) { + pr_err("Invalid irq\n"); + return -ENXIO; + } + + init_completion(&adc_qpnp->adc_rslt_completion); + + if (of_get_property(node, "hkadc_ldo-supply", NULL)) { + adc_qpnp->hkadc_ldo = regulator_get(&pdev->dev, "hkadc_ldo"); + if (IS_ERR(adc_qpnp->hkadc_ldo)) { + pr_err("hkadc_ldo-supply node not found\n"); + return -EINVAL; + } + + rc = regulator_set_voltage(adc_qpnp->hkadc_ldo, + QPNP_VADC_LDO_VOLTAGE_MIN, + QPNP_VADC_LDO_VOLTAGE_MAX); + if (rc < 0) { + pr_err("setting voltage for hkadc_ldo failed\n"); + return rc; + } + + rc = regulator_set_load(adc_qpnp->hkadc_ldo, 100000); + if (rc < 0) { + pr_err("hkadc_ldo optimum mode failed%d\n", rc); + return rc; + } + } + + if (of_get_property(node, "hkadc_ok-supply", NULL)) { + adc_qpnp->hkadc_ldo_ok = regulator_get(&pdev->dev, + "hkadc_ok"); + if (IS_ERR(adc_qpnp->hkadc_ldo_ok)) { + pr_err("hkadc_ok node not found\n"); + return -EINVAL; + } + + rc = regulator_set_voltage(adc_qpnp->hkadc_ldo_ok, + QPNP_VADC_OK_VOLTAGE_MIN, + QPNP_VADC_OK_VOLTAGE_MAX); + if (rc < 0) { + pr_err("setting voltage for hkadc-ldo-ok failed\n"); + return rc; + } + } + + return 0; +} +EXPORT_SYMBOL(qpnp_adc_get_devicetree_data); diff --git a/drivers/hwmon/qpnp-adc-current.c b/drivers/hwmon/qpnp-adc-current.c new file mode 100644 index 000000000000..b156224dc26f --- /dev/null +++ b/drivers/hwmon/qpnp-adc-current.c @@ -0,0 +1,1664 @@ +/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include <linux/kernel.h> +#include <linux/regmap.h> +#include <linux/of.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/mutex.h> +#include <linux/types.h> +#include <linux/hwmon.h> +#include <linux/module.h> +#include <linux/debugfs.h> +#include <linux/spmi.h> +#include <linux/platform_device.h> +#include <linux/of_irq.h> +#ifdef CONFIG_WAKELOCK +#include <linux/wakelock.h> +#endif +#include <linux/interrupt.h> +#include <linux/completion.h> +#include <linux/hwmon-sysfs.h> +#include <linux/qpnp/qpnp-adc.h> +#include <linux/platform_device.h> +#ifdef CONFIG_WAKELOCK +#include <linux/wakelock.h> +#endif + +/* QPNP IADC register definition */ +#define QPNP_IADC_REVISION1 0x0 +#define QPNP_IADC_REVISION2 0x1 +#define QPNP_IADC_REVISION3 0x2 +#define QPNP_IADC_REVISION4 0x3 +#define QPNP_IADC_PERPH_TYPE 0x4 +#define QPNP_IADC_PERH_SUBTYPE 0x5 + +#define QPNP_IADC_SUPPORTED_REVISION2 1 + +#define QPNP_STATUS1 0x8 +#define QPNP_STATUS1_OP_MODE 4 +#define QPNP_STATUS1_MULTI_MEAS_EN BIT(3) +#define QPNP_STATUS1_MEAS_INTERVAL_EN_STS BIT(2) +#define QPNP_STATUS1_REQ_STS BIT(1) +#define QPNP_STATUS1_EOC BIT(0) +#define QPNP_STATUS1_REQ_STS_EOC_MASK 0x3 +#define QPNP_STATUS2 0x9 +#define QPNP_STATUS2_CONV_SEQ_STATE_SHIFT 4 +#define QPNP_STATUS2_FIFO_NOT_EMPTY_FLAG BIT(1) +#define QPNP_STATUS2_CONV_SEQ_TIMEOUT_STS BIT(0) +#define QPNP_CONV_TIMEOUT_ERR 2 + +#define QPNP_IADC_MODE_CTL 0x40 +#define QPNP_OP_MODE_SHIFT 4 +#define QPNP_USE_BMS_DATA BIT(4) +#define QPNP_VADC_SYNCH_EN BIT(2) +#define QPNP_OFFSET_RMV_EN BIT(1) +#define QPNP_ADC_TRIM_EN BIT(0) +#define QPNP_IADC_EN_CTL1 0x46 +#define QPNP_IADC_ADC_EN BIT(7) +#define QPNP_ADC_CH_SEL_CTL 0x48 +#define QPNP_ADC_DIG_PARAM 0x50 +#define QPNP_ADC_CLK_SEL_MASK 0x3 +#define QPNP_ADC_DEC_RATIO_SEL_MASK 0xc +#define QPNP_ADC_DIG_DEC_RATIO_SEL_SHIFT 2 + +#define QPNP_CONV_REQ 0x52 +#define QPNP_CONV_REQ_SET BIT(7) +#define QPNP_CONV_SEQ_CTL 0x54 +#define QPNP_CONV_SEQ_HOLDOFF_SHIFT 4 +#define QPNP_CONV_SEQ_TRIG_CTL 0x55 +#define QPNP_FAST_AVG_CTL 0x5a + +#define QPNP_M0_LOW_THR_LSB 0x5c +#define QPNP_M0_LOW_THR_MSB 0x5d +#define QPNP_M0_HIGH_THR_LSB 0x5e +#define QPNP_M0_HIGH_THR_MSB 0x5f +#define QPNP_M1_LOW_THR_LSB 0x69 +#define QPNP_M1_LOW_THR_MSB 0x6a +#define QPNP_M1_HIGH_THR_LSB 0x6b +#define QPNP_M1_HIGH_THR_MSB 0x6c + +#define QPNP_DATA0 0x60 +#define QPNP_DATA1 0x61 +#define QPNP_CONV_TIMEOUT_ERR 2 + +#define QPNP_IADC_SEC_ACCESS 0xD0 +#define QPNP_IADC_SEC_ACCESS_DATA 0xA5 +#define QPNP_IADC_MSB_OFFSET 0xF2 +#define QPNP_IADC_LSB_OFFSET 0xF3 +#define QPNP_IADC_NOMINAL_RSENSE 0xF4 +#define QPNP_IADC_ATE_GAIN_CALIB_OFFSET 0xF5 +#define QPNP_INT_TEST_VAL 0xE1 + +#define QPNP_IADC_ADC_CH_SEL_CTL 0x48 +#define QPNP_IADC_ADC_CHX_SEL_SHIFT 3 + +#define QPNP_IADC_ADC_DIG_PARAM 0x50 +#define QPNP_IADC_CLK_SEL_SHIFT 1 +#define QPNP_IADC_DEC_RATIO_SEL 3 + +#define QPNP_IADC_CONV_REQUEST 0x52 +#define QPNP_IADC_CONV_REQ BIT(7) + +#define QPNP_IADC_DATA0 0x60 +#define QPNP_IADC_DATA1 0x61 + +#define QPNP_ADC_CONV_TIME_MIN 2000 +#define QPNP_ADC_CONV_TIME_MAX 2100 +#define QPNP_ADC_ERR_COUNT 20 + +#define QPNP_ADC_GAIN_NV 17857 +#define QPNP_OFFSET_CALIBRATION_SHORT_CADC_LEADS_IDEAL 0 +#define QPNP_IADC_INTERNAL_RSENSE_N_OHMS_FACTOR 10000000 +#define QPNP_IADC_NANO_VOLTS_FACTOR 1000000 +#define QPNP_IADC_CALIB_SECONDS 300000 +#define QPNP_IADC_RSENSE_LSB_N_OHMS_PER_BIT 15625 +#define QPNP_IADC_DIE_TEMP_CALIB_OFFSET 5000 + +#define QPNP_RAW_CODE_16_BIT_MSB_MASK 0xff00 +#define QPNP_RAW_CODE_16_BIT_LSB_MASK 0xff +#define QPNP_BIT_SHIFT_8 8 +#define QPNP_RSENSE_MSB_SIGN_CHECK 0x80 +#define QPNP_ADC_COMPLETION_TIMEOUT HZ +#define SMBB_BAT_IF_TRIM_CNST_RDS_MASK 0x7 +#define SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_0 0 +#define SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2 2 +#define QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST 127 +#define QPNP_IADC_RSENSE_DEFAULT_VALUE 7800000 +#define QPNP_IADC_RSENSE_DEFAULT_TYPEB_GF 9000000 +#define QPNP_IADC_RSENSE_DEFAULT_TYPEB_SMIC 9700000 + +struct qpnp_iadc_comp { + bool ext_rsense; + u8 id; + u8 sys_gain; + u8 revision_dig_major; + u8 revision_ana_minor; +}; + +struct qpnp_iadc_chip { + struct device *dev; + struct qpnp_adc_drv *adc; + int32_t rsense; + bool external_rsense; + bool default_internal_rsense; + struct device *iadc_hwmon; + struct list_head list; + int64_t die_temp; + struct delayed_work iadc_work; + bool iadc_mode_sel; + struct qpnp_iadc_comp iadc_comp; + struct qpnp_vadc_chip *vadc_dev; + struct work_struct trigger_completion_work; + bool skip_auto_calibrations; + bool iadc_poll_eoc; + u16 batt_id_trim_cnst_rds; + int rds_trim_default_type; + int max_channels_available; + bool rds_trim_default_check; + int32_t rsense_workaround_value; + struct sensor_device_attribute sens_attr[0]; +}; + +LIST_HEAD(qpnp_iadc_device_list); + +enum qpnp_iadc_rsense_rds_workaround { + QPNP_IADC_RDS_DEFAULT_TYPEA, + QPNP_IADC_RDS_DEFAULT_TYPEB, + QPNP_IADC_RDS_DEFAULT_TYPEC, +}; + +static int32_t qpnp_iadc_read_reg(struct qpnp_iadc_chip *iadc, + uint32_t reg, u8 *data) +{ + int rc; + uint val; + + rc = regmap_read(iadc->adc->regmap, (iadc->adc->offset + reg), &val); + if (rc < 0) { + pr_err("qpnp iadc read reg %d failed with %d\n", reg, rc); + return rc; + } + *data = (u8)val; + + return 0; +} + +static int32_t qpnp_iadc_write_reg(struct qpnp_iadc_chip *iadc, + uint32_t reg, u8 data) +{ + int rc; + u8 *buf; + + buf = &data; + rc = regmap_write(iadc->adc->regmap, (iadc->adc->offset + reg), *buf); + if (rc < 0) { + pr_err("qpnp iadc write reg %d failed with %d\n", reg, rc); + return rc; + } + + return 0; +} + +static int qpnp_iadc_is_valid(struct qpnp_iadc_chip *iadc) +{ + struct qpnp_iadc_chip *iadc_chip = NULL; + + list_for_each_entry(iadc_chip, &qpnp_iadc_device_list, list) + if (iadc == iadc_chip) + return 0; + + return -EINVAL; +} + +static void qpnp_iadc_trigger_completion(struct work_struct *work) +{ + struct qpnp_iadc_chip *iadc = container_of(work, + struct qpnp_iadc_chip, trigger_completion_work); + + if (qpnp_iadc_is_valid(iadc) < 0) + return; + + complete(&iadc->adc->adc_rslt_completion); + + return; +} + +static irqreturn_t qpnp_iadc_isr(int irq, void *dev_id) +{ + struct qpnp_iadc_chip *iadc = dev_id; + + schedule_work(&iadc->trigger_completion_work); + + return IRQ_HANDLED; +} + +static int32_t qpnp_iadc_enable(struct qpnp_iadc_chip *dev, bool state) +{ + int rc = 0; + u8 data = 0; + + data = QPNP_IADC_ADC_EN; + if (state) { + rc = qpnp_iadc_write_reg(dev, QPNP_IADC_EN_CTL1, + data); + if (rc < 0) { + pr_err("IADC enable failed\n"); + return rc; + } + } else { + rc = qpnp_iadc_write_reg(dev, QPNP_IADC_EN_CTL1, + (~data & QPNP_IADC_ADC_EN)); + if (rc < 0) { + pr_err("IADC disable failed\n"); + return rc; + } + } + + return 0; +} + +static int32_t qpnp_iadc_status_debug(struct qpnp_iadc_chip *dev) +{ + int rc = 0; + u8 mode = 0, status1 = 0, chan = 0, dig = 0, en = 0; + + rc = qpnp_iadc_read_reg(dev, QPNP_IADC_MODE_CTL, &mode); + if (rc < 0) { + pr_err("mode ctl register read failed with %d\n", rc); + return rc; + } + + rc = qpnp_iadc_read_reg(dev, QPNP_ADC_DIG_PARAM, &dig); + if (rc < 0) { + pr_err("digital param read failed with %d\n", rc); + return rc; + } + + rc = qpnp_iadc_read_reg(dev, QPNP_IADC_ADC_CH_SEL_CTL, &chan); + if (rc < 0) { + pr_err("channel read failed with %d\n", rc); + return rc; + } + + rc = qpnp_iadc_read_reg(dev, QPNP_STATUS1, &status1); + if (rc < 0) { + pr_err("status1 read failed with %d\n", rc); + return rc; + } + + rc = qpnp_iadc_read_reg(dev, QPNP_IADC_EN_CTL1, &en); + if (rc < 0) { + pr_err("en read failed with %d\n", rc); + return rc; + } + + pr_debug("EOC not set with status:%x, dig:%x, ch:%x, mode:%x, en:%x\n", + status1, dig, chan, mode, en); + + rc = qpnp_iadc_enable(dev, false); + if (rc < 0) { + pr_err("IADC disable failed with %d\n", rc); + return rc; + } + + return 0; +} + +static int32_t qpnp_iadc_read_conversion_result(struct qpnp_iadc_chip *iadc, + int16_t *data) +{ + uint8_t rslt_lsb, rslt_msb; + uint16_t rslt; + int32_t rc; + + rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_DATA0, &rslt_lsb); + if (rc < 0) { + pr_err("qpnp adc result read failed with %d\n", rc); + return rc; + } + + rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_DATA1, &rslt_msb); + if (rc < 0) { + pr_err("qpnp adc result read failed with %d\n", rc); + return rc; + } + + rslt = (rslt_msb << 8) | rslt_lsb; + *data = rslt; + + rc = qpnp_iadc_enable(iadc, false); + if (rc) + return rc; + + return 0; +} + +#define QPNP_IADC_PM8026_2_REV2 4 +#define QPNP_IADC_PM8026_2_REV3 2 + +#define QPNP_COEFF_1 969000 +#define QPNP_COEFF_2 32 +#define QPNP_COEFF_3_TYPEA 1700000 +#define QPNP_COEFF_3_TYPEB 1000000 +#define QPNP_COEFF_4 100 +#define QPNP_COEFF_5 15 +#define QPNP_COEFF_6 100000 +#define QPNP_COEFF_7 21 +#define QPNP_COEFF_8 100000000 +#define QPNP_COEFF_9 38 +#define QPNP_COEFF_10 40 +#define QPNP_COEFF_11 7 +#define QPNP_COEFF_12 11 +#define QPNP_COEFF_13 37 +#define QPNP_COEFF_14 39 +#define QPNP_COEFF_15 9 +#define QPNP_COEFF_16 11 +#define QPNP_COEFF_17 851200 +#define QPNP_COEFF_18 296500 +#define QPNP_COEFF_19 222400 +#define QPNP_COEFF_20 813800 +#define QPNP_COEFF_21 1059100 +#define QPNP_COEFF_22 5000000 +#define QPNP_COEFF_23 3722500 +#define QPNP_COEFF_24 84 +#define QPNP_COEFF_25 33 +#define QPNP_COEFF_26 22 +#define QPNP_COEFF_27 53 +#define QPNP_COEFF_28 48 + +static int32_t qpnp_iadc_comp(int64_t *result, struct qpnp_iadc_chip *iadc, + int64_t die_temp) +{ + int64_t temp_var = 0, sys_gain_coeff = 0, old; + int32_t coeff_a = 0, coeff_b = 0; + int version = 0; + + version = qpnp_adc_get_revid_version(iadc->dev); + if (version == -EINVAL) + return 0; + + old = *result; + *result = *result * 1000000; + + if (iadc->iadc_comp.sys_gain > 127) + sys_gain_coeff = -QPNP_COEFF_6 * + (iadc->iadc_comp.sys_gain - 128); + else + sys_gain_coeff = QPNP_COEFF_6 * + iadc->iadc_comp.sys_gain; + + switch (version) { + case QPNP_REV_ID_8941_3_1: + switch (iadc->iadc_comp.id) { + case COMP_ID_GF: + if (!iadc->iadc_comp.ext_rsense) { + /* internal rsense */ + coeff_a = QPNP_COEFF_2; + coeff_b = -QPNP_COEFF_3_TYPEA; + } else { + if (*result < 0) { + /* charge */ + coeff_a = QPNP_COEFF_5; + coeff_b = QPNP_COEFF_6; + } else { + /* discharge */ + coeff_a = -QPNP_COEFF_7; + coeff_b = QPNP_COEFF_6; + } + } + break; + case COMP_ID_TSMC: + default: + if (!iadc->iadc_comp.ext_rsense) { + /* internal rsense */ + coeff_a = QPNP_COEFF_2; + coeff_b = -QPNP_COEFF_3_TYPEB; + } else { + if (*result < 0) { + /* charge */ + coeff_a = QPNP_COEFF_5; + coeff_b = QPNP_COEFF_6; + } else { + /* discharge */ + coeff_a = -QPNP_COEFF_7; + coeff_b = QPNP_COEFF_6; + } + } + break; + } + break; + case QPNP_REV_ID_8026_2_1: + case QPNP_REV_ID_8026_2_2: + /* pm8026 rev 2.1 and 2.2 */ + switch (iadc->iadc_comp.id) { + case COMP_ID_GF: + if (!iadc->iadc_comp.ext_rsense) { + /* internal rsense */ + if (*result < 0) { + /* charge */ + coeff_a = 0; + coeff_b = 0; + } else { + coeff_a = QPNP_COEFF_25; + coeff_b = 0; + } + } else { + if (*result < 0) { + /* charge */ + coeff_a = 0; + coeff_b = 0; + } else { + /* discharge */ + coeff_a = 0; + coeff_b = 0; + } + } + break; + case COMP_ID_TSMC: + default: + if (!iadc->iadc_comp.ext_rsense) { + /* internal rsense */ + if (*result < 0) { + /* charge */ + coeff_a = 0; + coeff_b = 0; + } else { + coeff_a = QPNP_COEFF_26; + coeff_b = 0; + } + } else { + if (*result < 0) { + /* charge */ + coeff_a = 0; + coeff_b = 0; + } else { + /* discharge */ + coeff_a = 0; + coeff_b = 0; + } + } + break; + } + break; + case QPNP_REV_ID_8026_1_0: + /* pm8026 rev 1.0 */ + switch (iadc->iadc_comp.id) { + case COMP_ID_GF: + if (!iadc->iadc_comp.ext_rsense) { + /* internal rsense */ + if (*result < 0) { + /* charge */ + coeff_a = QPNP_COEFF_9; + coeff_b = -QPNP_COEFF_17; + } else { + coeff_a = QPNP_COEFF_10; + coeff_b = QPNP_COEFF_18; + } + } else { + if (*result < 0) { + /* charge */ + coeff_a = -QPNP_COEFF_11; + coeff_b = 0; + } else { + /* discharge */ + coeff_a = -QPNP_COEFF_17; + coeff_b = -QPNP_COEFF_19; + } + } + break; + case COMP_ID_TSMC: + default: + if (!iadc->iadc_comp.ext_rsense) { + /* internal rsense */ + if (*result < 0) { + /* charge */ + coeff_a = QPNP_COEFF_13; + coeff_b = -QPNP_COEFF_20; + } else { + coeff_a = QPNP_COEFF_14; + coeff_b = QPNP_COEFF_21; + } + } else { + if (*result < 0) { + /* charge */ + coeff_a = -QPNP_COEFF_15; + coeff_b = 0; + } else { + /* discharge */ + coeff_a = -QPNP_COEFF_12; + coeff_b = -QPNP_COEFF_19; + } + } + break; + } + break; + case QPNP_REV_ID_8110_1_0: + /* pm8110 rev 1.0 */ + switch (iadc->iadc_comp.id) { + case COMP_ID_GF: + if (!iadc->iadc_comp.ext_rsense) { + /* internal rsense */ + if (*result < 0) { + /* charge */ + coeff_a = QPNP_COEFF_24; + coeff_b = -QPNP_COEFF_22; + } else { + coeff_a = QPNP_COEFF_24; + coeff_b = -QPNP_COEFF_23; + } + } + break; + case COMP_ID_SMIC: + default: + if (!iadc->iadc_comp.ext_rsense) { + /* internal rsense */ + if (*result < 0) { + /* charge */ + coeff_a = QPNP_COEFF_24; + coeff_b = -QPNP_COEFF_22; + } else { + coeff_a = QPNP_COEFF_24; + coeff_b = -QPNP_COEFF_23; + } + } + break; + } + break; + case QPNP_REV_ID_8110_2_0: + die_temp -= 25000; + /* pm8110 rev 2.0 */ + switch (iadc->iadc_comp.id) { + case COMP_ID_GF: + if (!iadc->iadc_comp.ext_rsense) { + /* internal rsense */ + if (*result < 0) { + /* charge */ + coeff_a = 0; + coeff_b = 0; + } else { + coeff_a = QPNP_COEFF_27; + coeff_b = 0; + } + } + break; + case COMP_ID_SMIC: + default: + if (!iadc->iadc_comp.ext_rsense) { + /* internal rsense */ + if (*result < 0) { + /* charge */ + coeff_a = 0; + coeff_b = 0; + } else { + coeff_a = QPNP_COEFF_28; + coeff_b = 0; + } + } + break; + } + break; + default: + case QPNP_REV_ID_8026_2_0: + /* pm8026 rev 1.0 */ + coeff_a = 0; + coeff_b = 0; + break; + } + + temp_var = (coeff_a * die_temp) + coeff_b; + temp_var = div64_s64(temp_var, QPNP_COEFF_4); + temp_var = 1000 * (1000000 - temp_var); + + if (!iadc->iadc_comp.ext_rsense) { + /* internal rsense */ + *result = div64_s64(*result * 1000, temp_var); + } + + if (iadc->iadc_comp.ext_rsense) { + /* external rsense */ + sys_gain_coeff = (1000000 + + div64_s64(sys_gain_coeff, QPNP_COEFF_4)); + temp_var = div64_s64(temp_var * sys_gain_coeff, 1000000); + *result = div64_s64(*result * 1000, temp_var); + } + pr_debug("%lld compensated into %lld, a: %d, b: %d, sys_gain: %lld\n", + old, *result, coeff_a, coeff_b, sys_gain_coeff); + + return 0; +} + +int32_t qpnp_iadc_comp_result(struct qpnp_iadc_chip *iadc, int64_t *result) +{ + return qpnp_iadc_comp(result, iadc, iadc->die_temp); +} +EXPORT_SYMBOL(qpnp_iadc_comp_result); + +static int qpnp_iadc_rds_trim_update_check(struct qpnp_iadc_chip *iadc) +{ + int rc = 0; + u8 trim2_val = 0; + uint smbb_batt_trm_data = 0; + u8 smbb_batt_trm_cnst_rds = 0; + + if (!iadc->rds_trim_default_check) { + pr_debug("No internal rds trim check needed\n"); + return 0; + } + + rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_NOMINAL_RSENSE, &trim2_val); + if (rc < 0) { + pr_err("qpnp adc trim2_fullscale1 reg read failed %d\n", rc); + return rc; + } + + rc = regmap_read(iadc->adc->regmap, iadc->batt_id_trim_cnst_rds, + &smbb_batt_trm_data); + if (rc < 0) { + pr_err("batt_id trim_cnst rds reg read failed %d\n", rc); + return rc; + } + + smbb_batt_trm_cnst_rds = (u8)smbb_batt_trm_data & + SMBB_BAT_IF_TRIM_CNST_RDS_MASK; + + pr_debug("n_trim:0x%x smb_trm:0x%02x\n", trim2_val, smbb_batt_trm_data); + + if (iadc->rds_trim_default_type == QPNP_IADC_RDS_DEFAULT_TYPEA) { + + if ((smbb_batt_trm_cnst_rds == + SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) && + (trim2_val == QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) { + iadc->rsense_workaround_value = + QPNP_IADC_RSENSE_DEFAULT_VALUE; + iadc->default_internal_rsense = true; + } + } else if (iadc->rds_trim_default_type == + QPNP_IADC_RDS_DEFAULT_TYPEB) { + if ((smbb_batt_trm_cnst_rds >= + SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) && + (trim2_val == QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) { + iadc->rsense_workaround_value = + QPNP_IADC_RSENSE_DEFAULT_VALUE; + iadc->default_internal_rsense = true; + } else if ((smbb_batt_trm_cnst_rds < + SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) && + (trim2_val == + QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) { + if (iadc->iadc_comp.id == COMP_ID_GF) { + iadc->rsense_workaround_value = + QPNP_IADC_RSENSE_DEFAULT_TYPEB_GF; + iadc->default_internal_rsense = true; + } else if (iadc->iadc_comp.id == COMP_ID_SMIC) { + iadc->rsense_workaround_value = + QPNP_IADC_RSENSE_DEFAULT_TYPEB_SMIC; + iadc->default_internal_rsense = true; + } + } + } else if (iadc->rds_trim_default_type == QPNP_IADC_RDS_DEFAULT_TYPEC) { + + if ((smbb_batt_trm_cnst_rds > + SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_0) && + (smbb_batt_trm_cnst_rds <= + SMBB_BAT_IF_TRIM_CNST_RDS_MASK_CONST_2) && + (trim2_val == QPNP_IADC1_USR_TRIM2_ADC_FULLSCALE1_CONST)) { + iadc->rsense_workaround_value = + QPNP_IADC_RSENSE_DEFAULT_VALUE; + iadc->default_internal_rsense = true; + } + } + + return 0; +} + +static int32_t qpnp_iadc_comp_info(struct qpnp_iadc_chip *iadc) +{ + int rc = 0; + + rc = qpnp_iadc_read_reg(iadc, QPNP_INT_TEST_VAL, &iadc->iadc_comp.id); + if (rc < 0) { + pr_err("qpnp adc comp id failed with %d\n", rc); + return rc; + } + + rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_REVISION2, + &iadc->iadc_comp.revision_dig_major); + if (rc < 0) { + pr_err("qpnp adc revision2 read failed with %d\n", rc); + return rc; + } + + rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_REVISION3, + &iadc->iadc_comp.revision_ana_minor); + if (rc < 0) { + pr_err("qpnp adc revision3 read failed with %d\n", rc); + return rc; + } + + rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_ATE_GAIN_CALIB_OFFSET, + &iadc->iadc_comp.sys_gain); + if (rc < 0) { + pr_err("full scale read failed with %d\n", rc); + return rc; + } + + if (iadc->external_rsense) + iadc->iadc_comp.ext_rsense = true; + + pr_debug("fab id = %u, revision_dig_major = %u, revision_ana_minor = %u sys gain = %u, external_rsense = %d\n", + iadc->iadc_comp.id, + iadc->iadc_comp.revision_dig_major, + iadc->iadc_comp.revision_ana_minor, + iadc->iadc_comp.sys_gain, + iadc->iadc_comp.ext_rsense); + return rc; +} + +static int32_t qpnp_iadc_configure(struct qpnp_iadc_chip *iadc, + enum qpnp_iadc_channels channel, + uint16_t *raw_code, uint32_t mode_sel) +{ + u8 qpnp_iadc_mode_reg = 0, qpnp_iadc_ch_sel_reg = 0; + u8 qpnp_iadc_conv_req = 0, qpnp_iadc_dig_param_reg = 0; + u8 status1 = 0; + uint32_t count = 0; + int32_t rc = 0; + + qpnp_iadc_ch_sel_reg = channel; + + qpnp_iadc_dig_param_reg |= iadc->adc->amux_prop->decimation << + QPNP_IADC_DEC_RATIO_SEL; + if (iadc->iadc_mode_sel) + qpnp_iadc_mode_reg |= (QPNP_ADC_TRIM_EN | QPNP_VADC_SYNCH_EN); + else + qpnp_iadc_mode_reg |= QPNP_ADC_TRIM_EN; + + qpnp_iadc_conv_req = QPNP_IADC_CONV_REQ; + + rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_MODE_CTL, qpnp_iadc_mode_reg); + if (rc) { + pr_err("qpnp adc read adc failed with %d\n", rc); + return rc; + } + + rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_ADC_CH_SEL_CTL, + qpnp_iadc_ch_sel_reg); + if (rc) { + pr_err("qpnp adc read adc failed with %d\n", rc); + return rc; + } + + rc = qpnp_iadc_write_reg(iadc, QPNP_ADC_DIG_PARAM, + qpnp_iadc_dig_param_reg); + if (rc) { + pr_err("qpnp adc read adc failed with %d\n", rc); + return rc; + } + + rc = qpnp_iadc_write_reg(iadc, QPNP_FAST_AVG_CTL, + iadc->adc->amux_prop->fast_avg_setup); + if (rc < 0) { + pr_err("qpnp adc fast averaging configure error\n"); + return rc; + } + + if (!iadc->iadc_poll_eoc) + reinit_completion(&iadc->adc->adc_rslt_completion); + + rc = qpnp_iadc_enable(iadc, true); + if (rc) + return rc; + + rc = qpnp_iadc_write_reg(iadc, QPNP_CONV_REQ, qpnp_iadc_conv_req); + if (rc) { + pr_err("qpnp adc read adc failed with %d\n", rc); + return rc; + } + + if (iadc->iadc_poll_eoc) { + while (status1 != QPNP_STATUS1_EOC) { + rc = qpnp_iadc_read_reg(iadc, QPNP_STATUS1, &status1); + if (rc < 0) + return rc; + status1 &= QPNP_STATUS1_REQ_STS_EOC_MASK; + usleep_range(QPNP_ADC_CONV_TIME_MIN, + QPNP_ADC_CONV_TIME_MAX); + count++; + if (count > QPNP_ADC_ERR_COUNT) { + pr_err("retry error exceeded\n"); + rc = qpnp_iadc_status_debug(iadc); + if (rc < 0) + pr_err("IADC status debug failed\n"); + rc = -EINVAL; + return rc; + } + } + } else { + rc = wait_for_completion_timeout( + &iadc->adc->adc_rslt_completion, + QPNP_ADC_COMPLETION_TIMEOUT); + if (!rc) { + rc = qpnp_iadc_read_reg(iadc, QPNP_STATUS1, &status1); + if (rc < 0) + return rc; + status1 &= QPNP_STATUS1_REQ_STS_EOC_MASK; + if (status1 == QPNP_STATUS1_EOC) + pr_debug("End of conversion status set\n"); + else { + rc = qpnp_iadc_status_debug(iadc); + if (rc < 0) { + pr_err("status debug failed %d\n", rc); + return rc; + } + return -EINVAL; + } + } + } + + rc = qpnp_iadc_read_conversion_result(iadc, raw_code); + if (rc) { + pr_err("qpnp adc read adc failed with %d\n", rc); + return rc; + } + + return 0; +} + +#define IADC_CENTER 0xC000 +#define IADC_READING_RESOLUTION_N 542535 +#define IADC_READING_RESOLUTION_D 100000 +static int32_t qpnp_convert_raw_offset_voltage(struct qpnp_iadc_chip *iadc) +{ + s64 numerator; + + if ((iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw) == 0) { + pr_err("raw offset errors! raw_gain:0x%x and raw_offset:0x%x\n", + iadc->adc->calib.gain_raw, iadc->adc->calib.offset_raw); + return -EINVAL; + } + + numerator = iadc->adc->calib.offset_raw - IADC_CENTER; + numerator *= IADC_READING_RESOLUTION_N; + iadc->adc->calib.offset_uv = div_s64(numerator, + IADC_READING_RESOLUTION_D); + + numerator = iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw; + numerator *= IADC_READING_RESOLUTION_N; + + iadc->adc->calib.gain_uv = div_s64(numerator, + IADC_READING_RESOLUTION_D); + + pr_debug("gain_uv:%d offset_uv:%d\n", + iadc->adc->calib.gain_uv, iadc->adc->calib.offset_uv); + return 0; +} + +#define IADC_IDEAL_RAW_GAIN 3291 +int32_t qpnp_iadc_calibrate_for_trim(struct qpnp_iadc_chip *iadc, + bool batfet_closed) +{ + uint8_t rslt_lsb, rslt_msb; + int32_t rc = 0, version = 0; + uint16_t raw_data; + uint32_t mode_sel = 0; + bool iadc_offset_ch_batfet_check; + + if (qpnp_iadc_is_valid(iadc) < 0) + return -EPROBE_DEFER; + + mutex_lock(&iadc->adc->adc_lock); + + if (iadc->iadc_poll_eoc) { + pr_debug("acquiring iadc eoc wakelock\n"); + pm_stay_awake(iadc->dev); + } + + iadc->adc->amux_prop->decimation = DECIMATION_TYPE1; + iadc->adc->amux_prop->fast_avg_setup = ADC_FAST_AVG_SAMPLE_1; + + rc = qpnp_iadc_configure(iadc, GAIN_CALIBRATION_17P857MV, + &raw_data, mode_sel); + if (rc < 0) { + pr_err("qpnp adc result read failed with %d\n", rc); + goto fail; + } + + iadc->adc->calib.gain_raw = raw_data; + + /* + * there is a features on PM8941 in the BMS where if the batfet is + * opened the BMS reads from INTERNAL_RSENSE (channel 0) actually go to + * OFFSET_CALIBRATION_CSP_CSN (channel 5). Hence if batfet is opened + * we have to calibrate based on OFFSET_CALIBRATION_CSP_CSN even for + * internal rsense. + */ + version = qpnp_adc_get_revid_version(iadc->dev); + if ((version == QPNP_REV_ID_8941_3_1) || + (version == QPNP_REV_ID_8941_3_0) || + (version == QPNP_REV_ID_8941_2_0)) + iadc_offset_ch_batfet_check = true; + else + iadc_offset_ch_batfet_check = false; + + if ((iadc_offset_ch_batfet_check && !batfet_closed) || + (iadc->external_rsense)) { + /* external offset calculation */ + rc = qpnp_iadc_configure(iadc, OFFSET_CALIBRATION_CSP_CSN, + &raw_data, mode_sel); + if (rc < 0) { + pr_err("qpnp adc result read failed with %d\n", rc); + goto fail; + } + } else { + /* internal offset calculation */ + rc = qpnp_iadc_configure(iadc, OFFSET_CALIBRATION_CSP2_CSN2, + &raw_data, mode_sel); + if (rc < 0) { + pr_err("qpnp adc result read failed with %d\n", rc); + goto fail; + } + } + + iadc->adc->calib.offset_raw = raw_data; + if (rc < 0) { + pr_err("qpnp adc offset/gain calculation failed\n"); + goto fail; + } + + if (iadc->iadc_comp.revision_dig_major == QPNP_IADC_PM8026_2_REV2 + && iadc->iadc_comp.revision_ana_minor == + QPNP_IADC_PM8026_2_REV3) + iadc->adc->calib.gain_raw = + iadc->adc->calib.offset_raw + IADC_IDEAL_RAW_GAIN; + + pr_debug("raw gain:0x%x, raw offset:0x%x\n", + iadc->adc->calib.gain_raw, iadc->adc->calib.offset_raw); + + rc = qpnp_convert_raw_offset_voltage(iadc); + if (rc < 0) { + pr_err("qpnp raw_voltage conversion failed\n"); + goto fail; + } + + rslt_msb = (raw_data & QPNP_RAW_CODE_16_BIT_MSB_MASK) >> + QPNP_BIT_SHIFT_8; + rslt_lsb = raw_data & QPNP_RAW_CODE_16_BIT_LSB_MASK; + + pr_debug("trim values:lsb:0x%x and msb:0x%x\n", rslt_lsb, rslt_msb); + + rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_SEC_ACCESS, + QPNP_IADC_SEC_ACCESS_DATA); + if (rc < 0) { + pr_err("qpnp iadc configure error for sec access\n"); + goto fail; + } + + rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_MSB_OFFSET, + rslt_msb); + if (rc < 0) { + pr_err("qpnp iadc configure error for MSB write\n"); + goto fail; + } + + rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_SEC_ACCESS, + QPNP_IADC_SEC_ACCESS_DATA); + if (rc < 0) { + pr_err("qpnp iadc configure error for sec access\n"); + goto fail; + } + + rc = qpnp_iadc_write_reg(iadc, QPNP_IADC_LSB_OFFSET, + rslt_lsb); + if (rc < 0) { + pr_err("qpnp iadc configure error for LSB write\n"); + goto fail; + } +fail: + if (iadc->iadc_poll_eoc) { + pr_debug("releasing iadc eoc wakelock\n"); + pm_relax(iadc->dev); + } + mutex_unlock(&iadc->adc->adc_lock); + return rc; +} +EXPORT_SYMBOL(qpnp_iadc_calibrate_for_trim); + +static void qpnp_iadc_work(struct work_struct *work) +{ + struct qpnp_iadc_chip *iadc = container_of(work, + struct qpnp_iadc_chip, iadc_work.work); + int rc = 0; + + if (!iadc->skip_auto_calibrations) { + rc = qpnp_iadc_calibrate_for_trim(iadc, true); + if (rc) + pr_debug("periodic IADC calibration failed\n"); + } + + schedule_delayed_work(&iadc->iadc_work, + round_jiffies_relative(msecs_to_jiffies + (QPNP_IADC_CALIB_SECONDS))); + return; +} + +static int32_t qpnp_iadc_version_check(struct qpnp_iadc_chip *iadc) +{ + uint8_t revision; + int rc; + + rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_REVISION2, &revision); + if (rc < 0) { + pr_err("qpnp adc result read failed with %d\n", rc); + return rc; + } + + if (revision < QPNP_IADC_SUPPORTED_REVISION2) { + pr_err("IADC Version not supported\n"); + return -EINVAL; + } + + return 0; +} + +struct qpnp_iadc_chip *qpnp_get_iadc(struct device *dev, const char *name) +{ + struct qpnp_iadc_chip *iadc; + struct device_node *node = NULL; + char prop_name[QPNP_MAX_PROP_NAME_LEN]; + + snprintf(prop_name, QPNP_MAX_PROP_NAME_LEN, "qcom,%s-iadc", name); + + node = of_parse_phandle(dev->of_node, prop_name, 0); + if (node == NULL) + return ERR_PTR(-ENODEV); + + list_for_each_entry(iadc, &qpnp_iadc_device_list, list) + if (iadc->adc->pdev->dev.of_node == node) + return iadc; + return ERR_PTR(-EPROBE_DEFER); +} +EXPORT_SYMBOL(qpnp_get_iadc); + +int32_t qpnp_iadc_get_rsense(struct qpnp_iadc_chip *iadc, int32_t *rsense) +{ + uint8_t rslt_rsense = 0; + int32_t rc = 0, sign_bit = 0; + + if (qpnp_iadc_is_valid(iadc) < 0) + return -EPROBE_DEFER; + + if (iadc->external_rsense) { + *rsense = iadc->rsense; + } else if (iadc->default_internal_rsense) { + *rsense = iadc->rsense_workaround_value; + } else { + + rc = qpnp_iadc_read_reg(iadc, QPNP_IADC_NOMINAL_RSENSE, + &rslt_rsense); + if (rc < 0) { + pr_err("qpnp adc rsense read failed with %d\n", rc); + return rc; + } + + pr_debug("rsense:0%x\n", rslt_rsense); + + if (rslt_rsense & QPNP_RSENSE_MSB_SIGN_CHECK) + sign_bit = 1; + + rslt_rsense &= ~QPNP_RSENSE_MSB_SIGN_CHECK; + + if (sign_bit) + *rsense = QPNP_IADC_INTERNAL_RSENSE_N_OHMS_FACTOR - + (rslt_rsense * QPNP_IADC_RSENSE_LSB_N_OHMS_PER_BIT); + else + *rsense = QPNP_IADC_INTERNAL_RSENSE_N_OHMS_FACTOR + + (rslt_rsense * QPNP_IADC_RSENSE_LSB_N_OHMS_PER_BIT); + } + pr_debug("rsense value is %d\n", *rsense); + + if (*rsense == 0) + pr_err("incorrect rsens value:%d rslt_rsense:%d\n", + *rsense, rslt_rsense); + + return rc; +} +EXPORT_SYMBOL(qpnp_iadc_get_rsense); + +static int32_t qpnp_check_pmic_temp(struct qpnp_iadc_chip *iadc) +{ + struct qpnp_vadc_result result_pmic_therm; + int64_t die_temp_offset; + int rc = 0; + + rc = qpnp_vadc_read(iadc->vadc_dev, DIE_TEMP, &result_pmic_therm); + if (rc < 0) + return rc; + + die_temp_offset = result_pmic_therm.physical - + iadc->die_temp; + if (die_temp_offset < 0) + die_temp_offset = -die_temp_offset; + + if (die_temp_offset > QPNP_IADC_DIE_TEMP_CALIB_OFFSET) { + iadc->die_temp = result_pmic_therm.physical; + if (!iadc->skip_auto_calibrations) { + rc = qpnp_iadc_calibrate_for_trim(iadc, true); + if (rc) + pr_err("IADC calibration failed rc = %d\n", rc); + } + } + + return rc; +} + +int32_t qpnp_iadc_read(struct qpnp_iadc_chip *iadc, + enum qpnp_iadc_channels channel, + struct qpnp_iadc_result *result) +{ + int32_t rc, rsense_n_ohms, sign = 0, num, mode_sel = 0; + int32_t rsense_u_ohms = 0; + int64_t result_current; + uint16_t raw_data; + int dt_index = 0; + + if (qpnp_iadc_is_valid(iadc) < 0) + return -EPROBE_DEFER; + + if ((iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw) == 0) { + pr_err("raw offset errors! run iadc calibration again\n"); + return -EINVAL; + } + + rc = qpnp_check_pmic_temp(iadc); + if (rc) { + pr_err("Error checking pmic therm temp\n"); + return rc; + } + + mutex_lock(&iadc->adc->adc_lock); + + while (((enum qpnp_iadc_channels) + iadc->adc->adc_channels[dt_index].channel_num + != channel) && (dt_index < iadc->max_channels_available)) + dt_index++; + + if (dt_index >= iadc->max_channels_available) { + pr_err("not a valid IADC channel\n"); + rc = -EINVAL; + goto fail; + } + + iadc->adc->amux_prop->decimation = + iadc->adc->adc_channels[dt_index].adc_decimation; + iadc->adc->amux_prop->fast_avg_setup = + iadc->adc->adc_channels[dt_index].fast_avg_setup; + + if (iadc->iadc_poll_eoc) { + pr_debug("acquiring iadc eoc wakelock\n"); + pm_stay_awake(iadc->dev); + } + + rc = qpnp_iadc_configure(iadc, channel, &raw_data, mode_sel); + if (rc < 0) { + pr_err("qpnp adc result read failed with %d\n", rc); + goto fail; + } + + rc = qpnp_iadc_get_rsense(iadc, &rsense_n_ohms); + pr_debug("current raw:0%x and rsense:%d\n", + raw_data, rsense_n_ohms); + rsense_u_ohms = rsense_n_ohms/1000; + num = raw_data - iadc->adc->calib.offset_raw; + if (num < 0) { + sign = 1; + num = -num; + } + + result->result_uv = (num * QPNP_ADC_GAIN_NV)/ + (iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw); + result_current = result->result_uv; + result_current *= QPNP_IADC_NANO_VOLTS_FACTOR; + /* Intentional fall through. Process the result w/o comp */ + do_div(result_current, rsense_u_ohms); + + if (sign) { + result->result_uv = -result->result_uv; + result_current = -result_current; + } + result_current *= -1; + rc = qpnp_iadc_comp_result(iadc, &result_current); + if (rc < 0) + pr_err("Error during compensating the IADC\n"); + rc = 0; + result_current *= -1; + + result->result_ua = (int32_t) result_current; +fail: + if (iadc->iadc_poll_eoc) { + pr_debug("releasing iadc eoc wakelock\n"); + pm_relax(iadc->dev); + } + mutex_unlock(&iadc->adc->adc_lock); + + return rc; +} +EXPORT_SYMBOL(qpnp_iadc_read); + +int32_t qpnp_iadc_get_gain_and_offset(struct qpnp_iadc_chip *iadc, + struct qpnp_iadc_calib *result) +{ + int rc; + + if (qpnp_iadc_is_valid(iadc) < 0) + return -EPROBE_DEFER; + + rc = qpnp_check_pmic_temp(iadc); + if (rc) { + pr_err("Error checking pmic therm temp\n"); + return rc; + } + + mutex_lock(&iadc->adc->adc_lock); + result->gain_raw = iadc->adc->calib.gain_raw; + result->ideal_gain_nv = QPNP_ADC_GAIN_NV; + result->gain_uv = iadc->adc->calib.gain_uv; + result->offset_raw = iadc->adc->calib.offset_raw; + result->ideal_offset_uv = + QPNP_OFFSET_CALIBRATION_SHORT_CADC_LEADS_IDEAL; + result->offset_uv = iadc->adc->calib.offset_uv; + pr_debug("raw gain:0%x, raw offset:0%x\n", + result->gain_raw, result->offset_raw); + pr_debug("gain_uv:%d offset_uv:%d\n", + result->gain_uv, result->offset_uv); + mutex_unlock(&iadc->adc->adc_lock); + + return 0; +} +EXPORT_SYMBOL(qpnp_iadc_get_gain_and_offset); + +int qpnp_iadc_skip_calibration(struct qpnp_iadc_chip *iadc) +{ + iadc->skip_auto_calibrations = true; + return 0; +} +EXPORT_SYMBOL(qpnp_iadc_skip_calibration); + +int qpnp_iadc_resume_calibration(struct qpnp_iadc_chip *iadc) +{ + iadc->skip_auto_calibrations = false; + return 0; +} +EXPORT_SYMBOL(qpnp_iadc_resume_calibration); + +int32_t qpnp_iadc_vadc_sync_read(struct qpnp_iadc_chip *iadc, + enum qpnp_iadc_channels i_channel, struct qpnp_iadc_result *i_result, + enum qpnp_vadc_channels v_channel, struct qpnp_vadc_result *v_result) +{ + int rc = 0, mode_sel = 0, num = 0, rsense_n_ohms = 0, sign = 0; + int dt_index = 0; + uint16_t raw_data; + int32_t rsense_u_ohms = 0; + int64_t result_current; + + if (qpnp_iadc_is_valid(iadc) < 0) + return -EPROBE_DEFER; + + if ((iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw) == 0) { + pr_err("raw offset errors! run iadc calibration again\n"); + return -EINVAL; + } + + mutex_lock(&iadc->adc->adc_lock); + + if (iadc->iadc_poll_eoc) { + pr_debug("acquiring iadc eoc wakelock\n"); + pm_stay_awake(iadc->dev); + } + + iadc->iadc_mode_sel = true; + + rc = qpnp_vadc_iadc_sync_request(iadc->vadc_dev, v_channel); + if (rc) { + pr_err("Configuring VADC failed\n"); + goto fail; + } + + while (((enum qpnp_iadc_channels) + iadc->adc->adc_channels[dt_index].channel_num + != i_channel) && (dt_index < iadc->max_channels_available)) + dt_index++; + + if (dt_index >= iadc->max_channels_available) { + pr_err("not a valid IADC channel\n"); + rc = -EINVAL; + goto fail; + } + + iadc->adc->amux_prop->decimation = + iadc->adc->adc_channels[dt_index].adc_decimation; + iadc->adc->amux_prop->fast_avg_setup = + iadc->adc->adc_channels[dt_index].fast_avg_setup; + + rc = qpnp_iadc_configure(iadc, i_channel, &raw_data, mode_sel); + if (rc < 0) { + pr_err("qpnp adc result read failed with %d\n", rc); + goto fail_release_vadc; + } + + rc = qpnp_iadc_get_rsense(iadc, &rsense_n_ohms); + pr_debug("current raw:0%x and rsense:%d\n", + raw_data, rsense_n_ohms); + rsense_u_ohms = rsense_n_ohms/1000; + num = raw_data - iadc->adc->calib.offset_raw; + if (num < 0) { + sign = 1; + num = -num; + } + + i_result->result_uv = (num * QPNP_ADC_GAIN_NV)/ + (iadc->adc->calib.gain_raw - iadc->adc->calib.offset_raw); + result_current = i_result->result_uv; + result_current *= QPNP_IADC_NANO_VOLTS_FACTOR; + /* Intentional fall through. Process the result w/o comp */ + if (!rsense_u_ohms) { + pr_err("rsense error=%d\n", rsense_u_ohms); + goto fail_release_vadc; + } + + do_div(result_current, rsense_u_ohms); + + if (sign) { + i_result->result_uv = -i_result->result_uv; + result_current = -result_current; + } + result_current *= -1; + rc = qpnp_iadc_comp_result(iadc, &result_current); + if (rc < 0) + pr_err("Error during compensating the IADC\n"); + rc = 0; + result_current *= -1; + + i_result->result_ua = (int32_t) result_current; + +fail_release_vadc: + rc = qpnp_vadc_iadc_sync_complete_request(iadc->vadc_dev, v_channel, + v_result); + if (rc) + pr_err("Releasing VADC failed\n"); +fail: + iadc->iadc_mode_sel = false; + + if (iadc->iadc_poll_eoc) { + pr_debug("releasing iadc eoc wakelock\n"); + pm_relax(iadc->dev); + } + mutex_unlock(&iadc->adc->adc_lock); + + return rc; +} +EXPORT_SYMBOL(qpnp_iadc_vadc_sync_read); + +static ssize_t qpnp_iadc_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct qpnp_iadc_chip *iadc = dev_get_drvdata(dev); + struct qpnp_iadc_result result; + int rc = -1; + + rc = qpnp_iadc_read(iadc, attr->index, &result); + + if (rc) + return 0; + + return snprintf(buf, QPNP_ADC_HWMON_NAME_LENGTH, + "Result:%d\n", result.result_ua); +} + +static struct sensor_device_attribute qpnp_adc_attr = + SENSOR_ATTR(NULL, S_IRUGO, qpnp_iadc_show, NULL, 0); + +static int32_t qpnp_iadc_init_hwmon(struct qpnp_iadc_chip *iadc, + struct platform_device *pdev) +{ + struct device_node *child; + struct device_node *node = pdev->dev.of_node; + int rc = 0, i = 0, channel; + + for_each_child_of_node(node, child) { + channel = iadc->adc->adc_channels[i].channel_num; + qpnp_adc_attr.index = iadc->adc->adc_channels[i].channel_num; + qpnp_adc_attr.dev_attr.attr.name = + iadc->adc->adc_channels[i].name; + memcpy(&iadc->sens_attr[i], &qpnp_adc_attr, + sizeof(qpnp_adc_attr)); + sysfs_attr_init(&iadc->sens_attr[i].dev_attr.attr); + rc = device_create_file(&pdev->dev, + &iadc->sens_attr[i].dev_attr); + if (rc) { + dev_err(&pdev->dev, + "device_create_file failed for dev %s\n", + iadc->adc->adc_channels[i].name); + goto hwmon_err_sens; + } + i++; + } + + return 0; +hwmon_err_sens: + pr_err("Init HWMON failed for qpnp_iadc with %d\n", rc); + return rc; +} + +static int qpnp_iadc_probe(struct platform_device *pdev) +{ + struct qpnp_iadc_chip *iadc; + struct qpnp_adc_drv *adc_qpnp; + struct device_node *node = pdev->dev.of_node; + struct device_node *child; + unsigned int base; + int rc, count_adc_channel_list = 0, i = 0; + + for_each_child_of_node(node, child) + count_adc_channel_list++; + + if (!count_adc_channel_list) { + pr_err("No channel listing\n"); + return -EINVAL; + } + + iadc = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_iadc_chip) + + (sizeof(struct sensor_device_attribute) * + count_adc_channel_list), GFP_KERNEL); + if (!iadc) { + dev_err(&pdev->dev, "Unable to allocate memory\n"); + return -ENOMEM; + } + + adc_qpnp = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_adc_drv), + GFP_KERNEL); + if (!adc_qpnp) { + dev_err(&pdev->dev, "Unable to allocate memory\n"); + return -ENOMEM; + } + + adc_qpnp->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!adc_qpnp->regmap) { + dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); + return -EINVAL; + } + + iadc->dev = &(pdev->dev); + iadc->adc = adc_qpnp; + + rc = qpnp_adc_get_devicetree_data(pdev, iadc->adc); + if (rc) { + dev_err(&pdev->dev, "failed to read device tree\n"); + return rc; + } + + rc = of_property_read_u32(pdev->dev.of_node, "batt-id-trim-cnst-rds", + &base); + if (rc < 0) { + dev_err(&pdev->dev, + "Couldn't find batt-id-trim-cnst-rds in node = %s rc = %d\n", + pdev->dev.of_node->full_name, rc); + return rc; + } + iadc->batt_id_trim_cnst_rds = base; + rc = of_property_read_u32(node, "qcom,use-default-rds-trim", + &iadc->rds_trim_default_type); + if (rc) + pr_debug("No trim workaround needed\n"); + else { + pr_debug("Use internal RDS trim workaround\n"); + iadc->rds_trim_default_check = true; + } + + iadc->vadc_dev = qpnp_get_vadc(&pdev->dev, "iadc"); + if (IS_ERR(iadc->vadc_dev)) { + rc = PTR_ERR(iadc->vadc_dev); + if (rc != -EPROBE_DEFER) + pr_err("vadc property missing, rc=%d\n", rc); + return rc; + } + + mutex_init(&iadc->adc->adc_lock); + + rc = of_property_read_u32(node, "qcom,rsense", + &iadc->rsense); + if (rc) + pr_debug("Defaulting to internal rsense\n"); + else { + pr_debug("Use external rsense\n"); + iadc->external_rsense = true; + } + + iadc->iadc_poll_eoc = of_property_read_bool(node, + "qcom,iadc-poll-eoc"); + if (!iadc->iadc_poll_eoc) { + rc = devm_request_irq(&pdev->dev, iadc->adc->adc_irq_eoc, + qpnp_iadc_isr, IRQF_TRIGGER_RISING, + "qpnp_iadc_interrupt", iadc); + if (rc) { + dev_err(&pdev->dev, "failed to request adc irq\n"); + return rc; + } else { + enable_irq_wake(iadc->adc->adc_irq_eoc); + } + } + + rc = qpnp_iadc_init_hwmon(iadc, pdev); + if (rc) { + dev_err(&pdev->dev, "failed to initialize qpnp hwmon adc\n"); + return rc; + } + iadc->iadc_hwmon = hwmon_device_register(&iadc->adc->pdev->dev); + + rc = qpnp_iadc_version_check(iadc); + if (rc) { + dev_err(&pdev->dev, "IADC version not supported\n"); + goto fail; + } + + iadc->max_channels_available = count_adc_channel_list; + INIT_WORK(&iadc->trigger_completion_work, qpnp_iadc_trigger_completion); + INIT_DELAYED_WORK(&iadc->iadc_work, qpnp_iadc_work); + rc = qpnp_iadc_comp_info(iadc); + if (rc) { + dev_err(&pdev->dev, "abstracting IADC comp info failed!\n"); + goto fail; + } + + rc = qpnp_iadc_rds_trim_update_check(iadc); + if (rc) { + dev_err(&pdev->dev, "Rds trim update failed!\n"); + goto fail; + } + + dev_set_drvdata(&pdev->dev, iadc); + list_add(&iadc->list, &qpnp_iadc_device_list); + rc = qpnp_iadc_calibrate_for_trim(iadc, true); + if (rc) + dev_err(&pdev->dev, "failed to calibrate for USR trim\n"); + + if (iadc->iadc_poll_eoc) + device_init_wakeup(iadc->dev, 1); + + schedule_delayed_work(&iadc->iadc_work, + round_jiffies_relative(msecs_to_jiffies + (QPNP_IADC_CALIB_SECONDS))); + return 0; +fail: + for_each_child_of_node(node, child) { + device_remove_file(&pdev->dev, &iadc->sens_attr[i].dev_attr); + i++; + } + hwmon_device_unregister(iadc->iadc_hwmon); + + return rc; +} + +static int qpnp_iadc_remove(struct platform_device *pdev) +{ + struct qpnp_iadc_chip *iadc = dev_get_drvdata(&pdev->dev); + struct device_node *node = pdev->dev.of_node; + struct device_node *child; + int i = 0; + + cancel_delayed_work(&iadc->iadc_work); + for_each_child_of_node(node, child) { + device_remove_file(&pdev->dev, &iadc->sens_attr[i].dev_attr); + i++; + } + hwmon_device_unregister(iadc->iadc_hwmon); + if (iadc->iadc_poll_eoc) + pm_relax(iadc->dev); + dev_set_drvdata(&pdev->dev, NULL); + + return 0; +} + +static const struct of_device_id qpnp_iadc_match_table[] = { + { .compatible = "qcom,qpnp-iadc", + }, + {} +}; + +static struct platform_driver qpnp_iadc_driver = { + .driver = { + .name = "qcom,qpnp-iadc", + .of_match_table = qpnp_iadc_match_table, + }, + .probe = qpnp_iadc_probe, + .remove = qpnp_iadc_remove, +}; + +static int __init qpnp_iadc_init(void) +{ + return platform_driver_register(&qpnp_iadc_driver); +} +module_init(qpnp_iadc_init); + +static void __exit qpnp_iadc_exit(void) +{ + platform_driver_unregister(&qpnp_iadc_driver); +} +module_exit(qpnp_iadc_exit); + +MODULE_DESCRIPTION("QPNP PMIC current ADC driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwmon/qpnp-adc-voltage.c b/drivers/hwmon/qpnp-adc-voltage.c new file mode 100644 index 000000000000..81ad68548c6b --- /dev/null +++ b/drivers/hwmon/qpnp-adc-voltage.c @@ -0,0 +1,2909 @@ +/* Copyright (c) 2012-2016, 2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include <linux/kernel.h> +#include <linux/regmap.h> +#include <linux/of.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/mutex.h> +#include <linux/types.h> +#include <linux/hwmon.h> +#include <linux/module.h> +#include <linux/debugfs.h> +#include <linux/spmi.h> +#include <linux/platform_device.h> +#include <linux/of_irq.h> +#include <linux/interrupt.h> +#include <linux/completion.h> +#include <linux/hwmon-sysfs.h> +#include <linux/qpnp/qpnp-adc.h> +#include <linux/platform_device.h> +#include <linux/power_supply.h> +#include <linux/thermal.h> + +/* QPNP VADC register definition */ +#define QPNP_VADC_REVISION1 0x0 +#define QPNP_VADC_REVISION2 0x1 +#define QPNP_VADC_REVISION3 0x2 +#define QPNP_VADC_REVISION4 0x3 +#define QPNP_VADC_PERPH_TYPE 0x4 +#define QPNP_VADC_PERH_SUBTYPE 0x5 + +#define QPNP_VADC_SUPPORTED_REVISION2 1 + +#define QPNP_VADC_STATUS1 0x8 +#define QPNP_VADC_STATUS1_OP_MODE 4 +#define QPNP_VADC_STATUS1_MEAS_INTERVAL_EN_STS BIT(2) +#define QPNP_VADC_STATUS1_REQ_STS BIT(1) +#define QPNP_VADC_STATUS1_EOC BIT(0) +#define QPNP_VADC_STATUS1_REQ_STS_EOC_MASK 0x3 +#define QPNP_VADC_STATUS1_OP_MODE_MASK 0x18 +#define QPNP_VADC_MEAS_INT_MODE 0x2 +#define QPNP_VADC_MEAS_INT_MODE_MASK 0x10 + +#define QPNP_VADC_STATUS2 0x9 +#define QPNP_VADC_STATUS2_CONV_SEQ_STATE 6 +#define QPNP_VADC_STATUS2_FIFO_NOT_EMPTY_FLAG BIT(1) +#define QPNP_VADC_STATUS2_CONV_SEQ_TIMEOUT_STS BIT(0) +#define QPNP_VADC_STATUS2_CONV_SEQ_STATE_SHIFT 4 +#define QPNP_VADC_CONV_TIMEOUT_ERR 2 + +#define QPNP_VADC_MODE_CTL 0x40 +#define QPNP_VADC_OP_MODE_SHIFT 3 +#define QPNP_VADC_VREF_XO_THM_FORCE BIT(2) +#define QPNP_VADC_AMUX_TRIM_EN BIT(1) +#define QPNP_VADC_TRIM_EN BIT(0) +#define QPNP_VADC_EN_CTL1 0x46 +#define QPNP_VADC_EN BIT(7) +#define QPNP_VADC_CH_SEL_CTL 0x48 +#define QPNP_VADC_DIG_PARAM 0x50 +#define QPNP_VADC_DIG_DEC_RATIO_SEL_SHIFT 3 +#define QPNP_VADC_HW_SETTLE_DELAY 0x51 +#define QPNP_VADC_CONV_REQ 0x52 +#define QPNP_VADC_CONV_REQ_SET BIT(7) +#define QPNP_VADC_CONV_SEQ_CTL 0x54 +#define QPNP_VADC_CONV_SEQ_HOLDOFF_SHIFT 4 +#define QPNP_VADC_CONV_SEQ_TRIG_CTL 0x55 +#define QPNP_VADC_MEAS_INTERVAL_CTL 0x57 +#define QPNP_VADC_MEAS_INTERVAL_OP_CTL 0x59 +#define QPNP_VADC_MEAS_INTERVAL_OP_SET BIT(7) + +#define QPNP_VADC_CONV_SEQ_FALLING_EDGE 0x0 +#define QPNP_VADC_CONV_SEQ_RISING_EDGE 0x1 +#define QPNP_VADC_CONV_SEQ_EDGE_SHIFT 7 +#define QPNP_VADC_FAST_AVG_CTL 0x5a + +#define QPNP_VADC_LOW_THR_LSB 0x5c +#define QPNP_VADC_LOW_THR_MSB 0x5d +#define QPNP_VADC_HIGH_THR_LSB 0x5e +#define QPNP_VADC_HIGH_THR_MSB 0x5f +#define QPNP_VADC_ACCESS 0xd0 +#define QPNP_VADC_ACCESS_DATA 0xa5 +#define QPNP_VADC_PERH_RESET_CTL3 0xda +#define QPNP_FOLLOW_OTST2_RB BIT(3) +#define QPNP_FOLLOW_WARM_RB BIT(2) +#define QPNP_FOLLOW_SHUTDOWN1_RB BIT(1) +#define QPNP_FOLLOW_SHUTDOWN2_RB BIT(0) + +#define QPNP_INT_TEST_VAL 0xE1 + +#define QPNP_VADC_DATA0 0x60 +#define QPNP_VADC_DATA1 0x61 +#define QPNP_VADC_CONV_TIMEOUT_ERR 2 +#define QPNP_VADC_CONV_TIME_MIN 1000 +#define QPNP_VADC_CONV_TIME_MAX 1100 +#define QPNP_ADC_COMPLETION_TIMEOUT HZ +#define QPNP_VADC_ERR_COUNT 20 +#define QPNP_OP_MODE_SHIFT 3 + +#define QPNP_VADC_THR_LSB_MASK(val) (val & 0xff) +#define QPNP_VADC_THR_MSB_MASK(val) ((val & 0xff00) >> 8) +#define QPNP_MIN_TIME 2000 +#define QPNP_MAX_TIME 2000 +#define QPNP_RETRY 100 +#define QPNP_VADC_ABSOLUTE_RECALIB_OFFSET 8 +#define QPNP_VADC_RATIOMETRIC_RECALIB_OFFSET 12 +#define QPNP_VADC_RECALIB_MAXCNT 10 +#define QPNP_VADC_OFFSET_DUMP 8 +#define QPNP_VADC_REG_DUMP 14 + +/* QPNP VADC refreshed register set */ +#define QPNP_VADC_HC1_STATUS1 0x8 + +#define QPNP_VADC_HC1_DATA_HOLD_CTL 0x3f +#define QPNP_VADC_HC1_DATA_HOLD_CTL_FIELD BIT(1) + +#define QPNP_VADC_HC1_ADC_DIG_PARAM 0x42 +#define QPNP_VADC_HC1_CAL_VAL BIT(6) +#define QPNP_VADC_HC1_CAL_VAL_SHIFT 6 +#define QPNP_VADC_HC1_CAL_SEL_MASK 0x30 +#define QPNP_VADC_HC1_CAL_SEL_SHIFT 4 +#define QPNP_VADC_HC1_DEC_RATIO_SEL 0xc +#define QPNP_VADC_HC1_DEC_RATIO_SHIFT 2 +#define QPNP_VADC_HC1_FAST_AVG_CTL 0x43 +#define QPNP_VADC_HC1_FAST_AVG_SAMPLES_MASK 0x7 +#define QPNP_VADC_HC1_ADC_CH_SEL_CTL 0x44 +#define QPNP_VADC_HC1_DELAY_CTL 0x45 +#define QPNP_VADC_HC1_DELAY_CTL_MASK 0xf +#define QPNP_VADC_MC1_EN_CTL1 0x46 +#define QPNP_VADC_HC1_ADC_EN BIT(7) +#define QPNP_VADC_MC1_CONV_REQ 0x47 +#define QPNP_VADC_HC1_CONV_REQ_START BIT(7) + +#define QPNP_VADC_HC1_VBAT_MIN_THR0 0x48 +#define QPNP_VADC_HC1_VBAT_MIN_THR1 0x49 + +#define QPNP_VADC_HC1_DATA0 0x50 +#define QPNP_VADC_HC1_DATA1 0x51 +#define QPNP_VADC_HC1_DATA_CHECK_USR 0x8000 + +#define QPNP_VADC_HC1_VBAT_MIN_DATA0 0x52 +#define QPNP_VADC_MC1_VBAT_MIN_DATA1 0x53 + +/* + * Conversion time varies between 213uS to 6827uS based on the decimation, + * clock rate, fast average samples with no measurement in queue. + */ +#define QPNP_VADC_HC1_CONV_TIME_MIN_US 213 +#define QPNP_VADC_HC1_CONV_TIME_MAX_US 214 +#define QPNP_VADC_HC1_ERR_COUNT 1600 + +struct qpnp_vadc_mode_state { + bool meas_int_mode; + bool meas_int_request_in_queue; + bool vadc_meas_int_enable; + struct qpnp_adc_tm_btm_param *param; + struct qpnp_adc_amux vadc_meas_amux; +}; + +struct qpnp_vadc_thermal_data { + bool thermal_node; + int thermal_chan; + enum qpnp_vadc_channels vadc_channel; + struct thermal_zone_device *tz_dev; + struct qpnp_vadc_chip *vadc_dev; +}; + +struct qpnp_vadc_chip { + struct device *dev; + struct qpnp_adc_drv *adc; + struct list_head list; + struct device *vadc_hwmon; + bool vadc_init_calib; + int max_channels_available; + bool vadc_iadc_sync_lock; + u8 id; + struct work_struct trigger_completion_work; + bool vadc_poll_eoc; + bool vadc_recalib_check; + u8 revision_ana_minor; + u8 revision_dig_major; + struct work_struct trigger_high_thr_work; + struct work_struct trigger_low_thr_work; + struct qpnp_vadc_mode_state *state_copy; + struct qpnp_vadc_thermal_data *vadc_therm_chan; + struct power_supply *vadc_chg_vote; + bool vadc_hc; + int vadc_debug_count; + struct sensor_device_attribute sens_attr[0]; +}; + +LIST_HEAD(qpnp_vadc_device_list); + +static struct qpnp_vadc_scale_fn vadc_scale_fn[] = { + [SCALE_DEFAULT] = {qpnp_adc_scale_default}, + [SCALE_BATT_THERM] = {qpnp_adc_scale_batt_therm}, + [SCALE_PMIC_THERM] = {qpnp_adc_scale_pmic_therm}, + [SCALE_XOTHERM] = {qpnp_adc_tdkntcg_therm}, + [SCALE_THERM_100K_PULLUP] = {qpnp_adc_scale_therm_pu2}, + [SCALE_THERM_150K_PULLUP] = {qpnp_adc_scale_therm_pu1}, + [SCALE_QRD_BATT_THERM] = {qpnp_adc_scale_qrd_batt_therm}, + [SCALE_QRD_SKUAA_BATT_THERM] = {qpnp_adc_scale_qrd_skuaa_batt_therm}, + [SCALE_SMB_BATT_THERM] = {qpnp_adc_scale_smb_batt_therm}, + [SCALE_QRD_SKUG_BATT_THERM] = {qpnp_adc_scale_qrd_skug_batt_therm}, + [SCALE_QRD_SKUH_BATT_THERM] = {qpnp_adc_scale_qrd_skuh_batt_therm}, + [SCALE_NCP_03WF683_THERM] = {qpnp_adc_scale_therm_ncp03}, + [SCALE_QRD_SKUT1_BATT_THERM] = {qpnp_adc_scale_qrd_skut1_batt_therm}, + [SCALE_PMI_CHG_TEMP] = {qpnp_adc_scale_pmi_chg_temp}, +}; + +static struct qpnp_vadc_rscale_fn adc_vadc_rscale_fn[] = { + [SCALE_RVADC_ABSOLUTE] = {qpnp_vadc_absolute_rthr}, +}; + +static int32_t qpnp_vadc_calib_device(struct qpnp_vadc_chip *vadc); + +static int32_t qpnp_vadc_read_reg(struct qpnp_vadc_chip *vadc, int16_t reg, + u8 *data, int len) +{ + int rc; + + rc = regmap_bulk_read(vadc->adc->regmap, + (vadc->adc->offset + reg), data, len); + if (rc < 0) { + pr_err("qpnp adc read reg %d failed with %d\n", reg, rc); + return rc; + } + + return 0; +} + +static int32_t qpnp_vadc_write_reg(struct qpnp_vadc_chip *vadc, int16_t reg, + u8 *buf, int len) +{ + int rc; + + rc = regmap_bulk_write(vadc->adc->regmap, + (vadc->adc->offset + reg), buf, len); + if (rc < 0) { + pr_err("qpnp adc write reg %d failed with %d\n", reg, rc); + return rc; + } + + return 0; +} + +static int qpnp_vadc_is_valid(struct qpnp_vadc_chip *vadc) +{ + struct qpnp_vadc_chip *vadc_chip = NULL; + + list_for_each_entry(vadc_chip, &qpnp_vadc_device_list, list) + if (vadc == vadc_chip) + return 0; + + return -EINVAL; +} + +static int32_t qpnp_vadc_warm_rst_configure(struct qpnp_vadc_chip *vadc) +{ + int rc = 0; + u8 data = 0, buf = 0; + + buf = QPNP_VADC_ACCESS_DATA; + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_ACCESS, &buf, 1); + if (rc < 0) { + pr_err("VADC write access failed\n"); + return rc; + } + + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_PERH_RESET_CTL3, &data, 1); + if (rc < 0) { + pr_err("VADC perh reset ctl3 read failed\n"); + return rc; + } + + buf = QPNP_VADC_ACCESS_DATA; + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_ACCESS, &buf, 1); + if (rc < 0) { + pr_err("VADC write access failed\n"); + return rc; + } + + data |= QPNP_FOLLOW_WARM_RB; + + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_PERH_RESET_CTL3, &data, 1); + if (rc < 0) { + pr_err("VADC perh reset ctl3 write failed\n"); + return rc; + } + + return 0; +} + +static int32_t qpnp_vadc_mode_select(struct qpnp_vadc_chip *vadc, u8 mode_ctl) +{ + int rc; + + mode_ctl |= (QPNP_VADC_TRIM_EN | QPNP_VADC_AMUX_TRIM_EN); + + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_MODE_CTL, &mode_ctl, 1); + if (rc < 0) + pr_err("vadc write mode selection err:%d\n", rc); + + return rc; +} + +static int32_t qpnp_vadc_enable(struct qpnp_vadc_chip *vadc, bool state) +{ + int rc = 0; + u8 data = 0; + + data = QPNP_VADC_EN; + if (state) { + if (vadc->adc->hkadc_ldo && vadc->adc->hkadc_ldo_ok) { + rc = qpnp_adc_enable_voltage(vadc->adc); + if (rc) { + pr_err("failed enabling VADC LDO\n"); + return rc; + } + } + + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_EN_CTL1, &data, 1); + if (rc < 0) { + pr_err("VADC enable failed\n"); + return rc; + } + } else { + data = (~data & QPNP_VADC_EN); + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_EN_CTL1, &data, 1); + if (rc < 0) { + pr_err("VADC disable failed\n"); + return rc; + } + + if (vadc->adc->hkadc_ldo && vadc->adc->hkadc_ldo_ok) + qpnp_adc_disable_voltage(vadc->adc); + } + + return 0; +} + +static int32_t qpnp_vadc_status_debug(struct qpnp_vadc_chip *vadc) +{ + int rc = 0, i = 0; + u8 buf[8], offset = 0; + + if (vadc->vadc_debug_count < 3) { + for (i = 0; i < QPNP_VADC_REG_DUMP; i++) { + rc = qpnp_vadc_read_reg(vadc, offset, buf, 8); + if (rc) { + pr_err("debug register dump failed\n"); + return rc; + } + offset += QPNP_VADC_OFFSET_DUMP; + pr_err("row%d: 0%x 0%x 0%x 0%x 0%x 0%x 0%x 0%x\n", + i, buf[0], buf[1], buf[2], buf[3], buf[4], + buf[5], buf[6], buf[7]); + } + } else + pr_debug("VADC peripheral dumps got printed before\n"); + + vadc->vadc_debug_count++; + + rc = qpnp_vadc_enable(vadc, false); + if (rc < 0) { + pr_err("VADC disable failed with %d\n", rc); + return rc; + } + + return 0; +} + +static int qpnp_vadc_hc_check_conversion_status(struct qpnp_vadc_chip *vadc) +{ + int rc = 0, count = 0; + u8 status1 = 0; + + while (status1 != QPNP_VADC_STATUS1_EOC) { + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); + if (rc < 0) + return rc; + status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; + if (status1 == QPNP_VADC_STATUS1_EOC) + break; + usleep_range(QPNP_VADC_HC1_CONV_TIME_MIN_US, + QPNP_VADC_HC1_CONV_TIME_MAX_US); + count++; + if (count > QPNP_VADC_HC1_ERR_COUNT) { + pr_err("retry error exceeded\n"); + rc = qpnp_vadc_status_debug(vadc); + if (rc < 0) + pr_err("VADC disable failed with %d\n", rc); + return -EINVAL; + } + } + + return rc; +} + +static int qpnp_vadc_hc_read_data(struct qpnp_vadc_chip *vadc, int *data) +{ + int rc = 0; + u8 buf = 0, rslt_lsb = 0, rslt_msb = 0; + + /* Set hold bit */ + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_HC1_DATA_HOLD_CTL, &buf, 1); + if (rc) { + pr_err("debug register dump failed\n"); + return rc; + } + buf |= QPNP_VADC_HC1_DATA_HOLD_CTL_FIELD; + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_DATA_HOLD_CTL, &buf, 1); + if (rc) { + pr_err("debug register dump failed\n"); + return rc; + } + + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_HC1_DATA0, &rslt_lsb, 1); + if (rc < 0) { + pr_err("qpnp adc result read failed for data0\n"); + return rc; + } + + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_HC1_DATA1, &rslt_msb, 1); + if (rc < 0) { + pr_err("qpnp adc result read failed for data1\n"); + return rc; + } + + *data = (rslt_msb << 8) | rslt_lsb; + + if (*data == QPNP_VADC_HC1_DATA_CHECK_USR) { + pr_err("Invalid data :0x%x\n", *data); + return -EINVAL; + } + + rc = qpnp_vadc_enable(vadc, false); + if (rc) { + pr_err("VADC disable failed\n"); + return rc; + } + + /* De-assert hold bit */ + buf &= ~QPNP_VADC_HC1_DATA_HOLD_CTL_FIELD; + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_DATA_HOLD_CTL, &buf, 1); + if (rc) + pr_err("de-asserting hold bit failed\n"); + + return rc; +} + +static void qpnp_vadc_hc_update_adc_dig_param(struct qpnp_vadc_chip *vadc, + struct qpnp_adc_amux_properties *amux_prop, u8 *data) +{ + /* Update CAL value */ + *data &= ~QPNP_VADC_HC1_CAL_VAL; + *data |= (amux_prop->cal_val << QPNP_VADC_HC1_CAL_VAL_SHIFT); + + /* Update CAL select */ + *data &= ~QPNP_VADC_HC1_CAL_SEL_MASK; + *data |= (amux_prop->calib_type << QPNP_VADC_HC1_CAL_SEL_SHIFT); + + /* Update Decimation ratio select */ + *data &= ~QPNP_VADC_HC1_DEC_RATIO_SEL; + *data |= (amux_prop->decimation << QPNP_VADC_HC1_DEC_RATIO_SHIFT); + + pr_debug("VADC_DIG_PARAM value:0x%x\n", *data); +} + +static int qpnp_vadc_hc_configure(struct qpnp_vadc_chip *vadc, + struct qpnp_adc_amux_properties *amux_prop) +{ + int rc = 0; + u8 buf[6]; + + /* Read registers 0x42 through 0x46 */ + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_HC1_ADC_DIG_PARAM, buf, 6); + if (rc < 0) { + pr_err("qpnp adc configure block read failed\n"); + return rc; + } + + /* ADC Digital param selection */ + qpnp_vadc_hc_update_adc_dig_param(vadc, amux_prop, &buf[0]); + + /* Update fast average sample value */ + buf[1] &= (u8) ~QPNP_VADC_HC1_FAST_AVG_SAMPLES_MASK; + buf[1] |= amux_prop->fast_avg_setup; + + /* Select ADC channel */ + buf[2] = amux_prop->amux_channel; + + /* Select hw settle delay for the channel */ + buf[3] &= (u8) ~QPNP_VADC_HC1_DELAY_CTL_MASK; + buf[3] |= amux_prop->hw_settle_time; + + /* Select ADC enable */ + buf[4] |= QPNP_VADC_HC1_ADC_EN; + + /* Select CONV request */ + buf[5] |= QPNP_VADC_HC1_CONV_REQ_START; + + if (!vadc->vadc_poll_eoc) + reinit_completion(&vadc->adc->adc_rslt_completion); + + pr_debug("dig:0x%x, fast_avg:0x%x, channel:0x%x, hw_settle:0x%x\n", + buf[0], buf[1], buf[2], buf[3]); + + /* Block register write from 0x42 through 0x46 */ + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HC1_ADC_DIG_PARAM, buf, 6); + if (rc < 0) { + pr_err("qpnp adc block register configure failed\n"); + return rc; + } + + return 0; +} + +int32_t qpnp_vadc_hc_read(struct qpnp_vadc_chip *vadc, + enum qpnp_vadc_channels channel, + struct qpnp_vadc_result *result) +{ + int rc = 0, scale_type, amux_prescaling, dt_index = 0, calib_type = 0; + struct qpnp_adc_amux_properties amux_prop; + + if (qpnp_vadc_is_valid(vadc)) + return -EPROBE_DEFER; + + mutex_lock(&vadc->adc->adc_lock); + + while ((vadc->adc->adc_channels[dt_index].channel_num + != channel) && (dt_index < vadc->max_channels_available)) + dt_index++; + + if (dt_index >= vadc->max_channels_available) { + pr_err("not a valid VADC channel:%d\n", channel); + rc = -EINVAL; + goto fail_unlock; + } + + if (!vadc->vadc_init_calib) { + rc = qpnp_vadc_calib_device(vadc); + if (rc) { + pr_err("Calibration failed\n"); + goto fail_unlock; + } else { + vadc->vadc_init_calib = true; + } + } + + calib_type = vadc->adc->adc_channels[dt_index].calib_type; + if (calib_type >= ADC_HC_CAL_SEL_NONE) { + pr_err("not a valid calib_type\n"); + rc = -EINVAL; + goto fail_unlock; + } + + amux_prop.decimation = + vadc->adc->adc_channels[dt_index].adc_decimation; + amux_prop.calib_type = vadc->adc->adc_channels[dt_index].calib_type; + amux_prop.cal_val = vadc->adc->adc_channels[dt_index].cal_val; + amux_prop.fast_avg_setup = + vadc->adc->adc_channels[dt_index].fast_avg_setup; + amux_prop.amux_channel = channel; + amux_prop.hw_settle_time = + vadc->adc->adc_channels[dt_index].hw_settle_time; + + rc = qpnp_vadc_hc_configure(vadc, &amux_prop); + if (rc < 0) { + pr_err("Configuring VADC channel failed with %d\n", rc); + goto fail_unlock; + } + + if (vadc->vadc_poll_eoc) { + rc = qpnp_vadc_hc_check_conversion_status(vadc); + if (rc < 0) { + pr_err("polling mode conversion failed\n"); + goto fail_unlock; + } + } else { + rc = wait_for_completion_timeout( + &vadc->adc->adc_rslt_completion, + QPNP_ADC_COMPLETION_TIMEOUT); + if (!rc) { + rc = qpnp_vadc_hc_check_conversion_status(vadc); + if (rc < 0) { + pr_err("interrupt mode conversion failed\n"); + goto fail_unlock; + } + pr_debug("End of conversion status set\n"); + } + } + + rc = qpnp_vadc_hc_read_data(vadc, &result->adc_code); + if (rc) { + pr_err("qpnp vadc read adc code failed with %d\n", rc); + goto fail_unlock; + } + + amux_prescaling = + vadc->adc->adc_channels[dt_index].chan_path_prescaling; + + if (amux_prescaling >= PATH_SCALING_NONE) { + rc = -EINVAL; + goto fail_unlock; + } + + vadc->adc->amux_prop->chan_prop->offset_gain_numerator = + qpnp_vadc_amux_scaling_ratio[amux_prescaling].num; + vadc->adc->amux_prop->chan_prop->offset_gain_denominator = + qpnp_vadc_amux_scaling_ratio[amux_prescaling].den; + + scale_type = vadc->adc->adc_channels[dt_index].adc_scale_fn; + if (scale_type >= SCALE_NONE) { + rc = -EBADF; + goto fail_unlock; + } + + /* Note: Scaling functions for VADC_HC do not need offset/gain */ + vadc_scale_fn[scale_type].chan(vadc, result->adc_code, + vadc->adc->adc_prop, vadc->adc->amux_prop->chan_prop, result); + + pr_debug("channel=0x%x, adc_code=0x%x adc_result=%lld\n", + channel, result->adc_code, result->physical); + +fail_unlock: + mutex_unlock(&vadc->adc->adc_lock); + + return rc; +} +EXPORT_SYMBOL(qpnp_vadc_hc_read); + +static int32_t qpnp_vadc_configure(struct qpnp_vadc_chip *vadc, + struct qpnp_adc_amux_properties *chan_prop) +{ + u8 decimation = 0, conv_sequence = 0, conv_sequence_trig = 0; + u8 mode_ctrl = 0, meas_int_op_ctl_data = 0, buf = 0; + int rc = 0; + + /* Mode selection */ + mode_ctrl |= ((chan_prop->mode_sel << QPNP_VADC_OP_MODE_SHIFT) | + (QPNP_VADC_TRIM_EN | QPNP_VADC_AMUX_TRIM_EN)); + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_MODE_CTL, &mode_ctrl, 1); + if (rc < 0) { + pr_err("Mode configure write error\n"); + return rc; + } + + /* Channel selection */ + buf = chan_prop->amux_channel; + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_CH_SEL_CTL, &buf, 1); + if (rc < 0) { + pr_err("Channel configure error\n"); + return rc; + } + + /* Digital parameter setup */ + decimation = chan_prop->decimation << + QPNP_VADC_DIG_DEC_RATIO_SEL_SHIFT; + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_DIG_PARAM, &decimation, 1); + if (rc < 0) { + pr_err("Digital parameter configure write error\n"); + return rc; + } + + /* HW settling time delay */ + buf = chan_prop->hw_settle_time; + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HW_SETTLE_DELAY, &buf, 1); + if (rc < 0) { + pr_err("HW settling time setup error\n"); + return rc; + } + + pr_debug("mode:%d, channel:%d, decimation:%d, hw_settle:%d\n", + mode_ctrl, chan_prop->amux_channel, decimation, + chan_prop->hw_settle_time); + + if (chan_prop->mode_sel == (ADC_OP_NORMAL_MODE << + QPNP_VADC_OP_MODE_SHIFT)) { + /* Normal measurement mode */ + buf = chan_prop->fast_avg_setup; + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_FAST_AVG_CTL, + &buf, 1); + if (rc < 0) { + pr_err("Fast averaging configure error\n"); + return rc; + } + /* Ensure MEAS_INTERVAL_OP_CTL is set to 0 */ + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_MEAS_INTERVAL_OP_CTL, + &meas_int_op_ctl_data, 1); + if (rc < 0) { + pr_err("Measurement interval OP configure error\n"); + return rc; + } + } else if (chan_prop->mode_sel == (ADC_OP_CONVERSION_SEQUENCER << + QPNP_VADC_OP_MODE_SHIFT)) { + /* Conversion sequence mode */ + conv_sequence = ((ADC_SEQ_HOLD_100US << + QPNP_VADC_CONV_SEQ_HOLDOFF_SHIFT) | + ADC_CONV_SEQ_TIMEOUT_5MS); + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_CONV_SEQ_CTL, + &conv_sequence, 1); + if (rc < 0) { + pr_err("Conversion sequence error\n"); + return rc; + } + + conv_sequence_trig = ((QPNP_VADC_CONV_SEQ_RISING_EDGE << + QPNP_VADC_CONV_SEQ_EDGE_SHIFT) | + chan_prop->trigger_channel); + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_CONV_SEQ_TRIG_CTL, + &conv_sequence_trig, 1); + if (rc < 0) { + pr_err("Conversion trigger error\n"); + return rc; + } + } else if (chan_prop->mode_sel == ADC_OP_MEASUREMENT_INTERVAL) { + buf = QPNP_VADC_MEAS_INTERVAL_OP_SET; + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_MEAS_INTERVAL_OP_CTL, + &buf, 1); + if (rc < 0) { + pr_err("Measurement interval OP configure error\n"); + return rc; + } + } + + if (!vadc->vadc_poll_eoc) + reinit_completion(&vadc->adc->adc_rslt_completion); + + rc = qpnp_vadc_enable(vadc, true); + if (rc) + return rc; + + if (!vadc->vadc_iadc_sync_lock) { + /* Request conversion */ + buf = QPNP_VADC_CONV_REQ_SET; + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_CONV_REQ, &buf, 1); + if (rc < 0) { + pr_err("Request conversion failed\n"); + return rc; + } + } + + return 0; +} + +static int32_t qpnp_vadc_read_conversion_result(struct qpnp_vadc_chip *vadc, + int32_t *data) +{ + uint8_t rslt_lsb, rslt_msb; + int rc = 0, status = 0; + + status = qpnp_vadc_read_reg(vadc, QPNP_VADC_DATA0, &rslt_lsb, 1); + if (status < 0) { + pr_err("qpnp adc result read failed for data0\n"); + goto fail; + } + + status = qpnp_vadc_read_reg(vadc, QPNP_VADC_DATA1, &rslt_msb, 1); + if (status < 0) { + pr_err("qpnp adc result read failed for data1\n"); + goto fail; + } + + *data = (rslt_msb << 8) | rslt_lsb; + +fail: + rc = qpnp_vadc_enable(vadc, false); + if (rc) + return rc; + + return status; +} + +static int32_t qpnp_vadc_read_status(struct qpnp_vadc_chip *vadc, int mode_sel) +{ + u8 status1, status2, status2_conv_seq_state; + u8 status_err = QPNP_VADC_CONV_TIMEOUT_ERR; + int rc; + + switch (mode_sel) { + case (ADC_OP_CONVERSION_SEQUENCER << QPNP_VADC_OP_MODE_SHIFT): + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); + if (rc) { + pr_err("qpnp_vadc read mask interrupt failed\n"); + return rc; + } + + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS2, &status2, 1); + if (rc) { + pr_err("qpnp_vadc read mask interrupt failed\n"); + return rc; + } + + if (!(status2 & ~QPNP_VADC_STATUS2_CONV_SEQ_TIMEOUT_STS) && + (status1 & (~QPNP_VADC_STATUS1_REQ_STS | + QPNP_VADC_STATUS1_EOC))) { + rc = status_err; + return rc; + } + + status2_conv_seq_state = status2 >> + QPNP_VADC_STATUS2_CONV_SEQ_STATE_SHIFT; + if (status2_conv_seq_state != ADC_CONV_SEQ_IDLE) { + pr_err("qpnp vadc seq error with status %d\n", + status2); + rc = -EINVAL; + return rc; + } + } + + return 0; +} + +static void qpnp_vadc_work(struct work_struct *work) +{ + struct qpnp_vadc_chip *vadc = container_of(work, + struct qpnp_vadc_chip, trigger_completion_work); + + if (qpnp_vadc_is_valid(vadc) < 0) + return; + + complete(&vadc->adc->adc_rslt_completion); +} + +static void qpnp_vadc_low_thr_fn(struct work_struct *work) +{ + struct qpnp_vadc_chip *vadc = container_of(work, + struct qpnp_vadc_chip, trigger_low_thr_work); + + vadc->state_copy->meas_int_mode = false; + vadc->state_copy->meas_int_request_in_queue = false; + vadc->state_copy->param->threshold_notification( + ADC_TM_LOW_STATE, + vadc->state_copy->param->btm_ctx); +} + +static void qpnp_vadc_high_thr_fn(struct work_struct *work) +{ + struct qpnp_vadc_chip *vadc = container_of(work, + struct qpnp_vadc_chip, trigger_high_thr_work); + + vadc->state_copy->meas_int_mode = false; + vadc->state_copy->meas_int_request_in_queue = false; + vadc->state_copy->param->threshold_notification( + ADC_TM_HIGH_STATE, + vadc->state_copy->param->btm_ctx); +} + +static irqreturn_t qpnp_vadc_isr(int irq, void *dev_id) +{ + struct qpnp_vadc_chip *vadc = dev_id; + + schedule_work(&vadc->trigger_completion_work); + + return IRQ_HANDLED; +} + +static irqreturn_t qpnp_vadc_low_thr_isr(int irq, void *data) +{ + struct qpnp_vadc_chip *vadc = data; + u8 mode_ctl = 0, mode = 0; + int rc = 0; + + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_MODE_CTL, &mode, 1); + if (rc < 0) { + pr_err("mode ctl register read failed with %d\n", rc); + return rc; + } + + if (!(mode & QPNP_VADC_MEAS_INT_MODE_MASK)) { + pr_debug("Spurious VADC threshold 0x%x\n", mode); + return IRQ_HANDLED; + } + + mode_ctl = ADC_OP_NORMAL_MODE; + /* Set measurement in single measurement mode */ + qpnp_vadc_mode_select(vadc, mode_ctl); + qpnp_vadc_enable(vadc, false); + schedule_work(&vadc->trigger_low_thr_work); + + return IRQ_HANDLED; +} + +static irqreturn_t qpnp_vadc_high_thr_isr(int irq, void *data) +{ + struct qpnp_vadc_chip *vadc = data; + u8 mode_ctl = 0, mode = 0; + int rc = 0; + + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_MODE_CTL, &mode, 1); + if (rc < 0) { + pr_err("mode ctl register read failed with %d\n", rc); + return rc; + } + + if (!(mode & QPNP_VADC_MEAS_INT_MODE_MASK)) { + pr_debug("Spurious VADC threshold 0x%x\n", mode); + return IRQ_HANDLED; + } + + mode_ctl = ADC_OP_NORMAL_MODE; + /* Set measurement in single measurement mode */ + qpnp_vadc_mode_select(vadc, mode_ctl); + qpnp_vadc_enable(vadc, false); + schedule_work(&vadc->trigger_high_thr_work); + + return IRQ_HANDLED; +} + +static int32_t qpnp_vadc_version_check(struct qpnp_vadc_chip *dev) +{ + uint8_t revision; + int rc; + + rc = qpnp_vadc_read_reg(dev, QPNP_VADC_REVISION2, &revision, 1); + if (rc < 0) { + pr_err("qpnp adc result read failed with %d\n", rc); + return rc; + } + + if (revision < QPNP_VADC_SUPPORTED_REVISION2) { + pr_err("VADC Version not supported\n"); + return -EINVAL; + } + + return 0; +} + +static int32_t + qpnp_vadc_channel_post_scaling_calib_check(struct qpnp_vadc_chip *vadc, + int channel) +{ + int version, rc = 0; + + version = qpnp_adc_get_revid_version(vadc->dev); + + if (version == QPNP_REV_ID_PM8950_1_0) { + if ((channel == LR_MUX7_HW_ID) || + (channel == P_MUX2_1_1) || + (channel == LR_MUX3_XO_THERM) || + (channel == LR_MUX3_BUF_XO_THERM_BUF) || + (channel == P_MUX4_1_1)) { + vadc->adc->amux_prop->chan_prop->calib_type = + CALIB_ABSOLUTE; + return rc; + } + } + + return -EINVAL; +} + +#define QPNP_VBAT_COEFF_1 3000 +#define QPNP_VBAT_COEFF_2 45810000 +#define QPNP_VBAT_COEFF_3 100000 +#define QPNP_VBAT_COEFF_4 3500 +#define QPNP_VBAT_COEFF_5 80000000 +#define QPNP_VBAT_COEFF_6 4400 +#define QPNP_VBAT_COEFF_7 32200000 +#define QPNP_VBAT_COEFF_8 3880 +#define QPNP_VBAT_COEFF_9 5770 +#define QPNP_VBAT_COEFF_10 3660 +#define QPNP_VBAT_COEFF_11 5320 +#define QPNP_VBAT_COEFF_12 8060000 +#define QPNP_VBAT_COEFF_13 102640000 +#define QPNP_VBAT_COEFF_14 22220000 +#define QPNP_VBAT_COEFF_15 83060000 +#define QPNP_VBAT_COEFF_16 2810 +#define QPNP_VBAT_COEFF_17 5260 +#define QPNP_VBAT_COEFF_18 8027 +#define QPNP_VBAT_COEFF_19 2347 +#define QPNP_VBAT_COEFF_20 6043 +#define QPNP_VBAT_COEFF_21 1914 +#define QPNP_VBAT_OFFSET_SMIC 9446 +#define QPNP_VBAT_OFFSET_GF 9441 +#define QPNP_OCV_OFFSET_SMIC 4596 +#define QPNP_OCV_OFFSET_GF 5896 +#define QPNP_VBAT_COEFF_22 6800 +#define QPNP_VBAT_COEFF_23 3500 +#define QPNP_VBAT_COEFF_24 4360 +#define QPNP_VBAT_COEFF_25 8060 +#define QPNP_VBAT_COEFF_26 7895 +#define QPNP_VBAT_COEFF_27 5658 +#define QPNP_VBAT_COEFF_28 5760 +#define QPNP_VBAT_COEFF_29 7900 +#define QPNP_VBAT_COEFF_30 5660 +#define QPNP_VBAT_COEFF_31 3620 +#define QPNP_VBAT_COEFF_32 1230 +#define QPNP_VBAT_COEFF_33 5760 +#define QPNP_VBAT_COEFF_34 4080 +#define QPNP_VBAT_COEFF_35 7000 +#define QPNP_VBAT_COEFF_36 3040 +#define QPNP_VBAT_COEFF_37 3850 +#define QPNP_VBAT_COEFF_38 5000 +#define QPNP_VBAT_COEFF_39 2610 +#define QPNP_VBAT_COEFF_40 4190 +#define QPNP_VBAT_COEFF_41 5800 +#define QPNP_VBAT_COEFF_42 2620 +#define QPNP_VBAT_COEFF_43 4030 +#define QPNP_VBAT_COEFF_44 3230 +#define QPNP_VBAT_COEFF_45 3450 +#define QPNP_VBAT_COEFF_46 2120 +#define QPNP_VBAT_COEFF_47 3560 +#define QPNP_VBAT_COEFF_48 2190 +#define QPNP_VBAT_COEFF_49 4180 +#define QPNP_VBAT_COEFF_50 27800000 +#define QPNP_VBAT_COEFF_51 5110 +#define QPNP_VBAT_COEFF_52 34444000 + +static int32_t qpnp_ocv_comp(int64_t *result, + struct qpnp_vadc_chip *vadc, int64_t die_temp) +{ + int64_t temp_var = 0, offset = 0; + int64_t old = *result; + int version; + + version = qpnp_adc_get_revid_version(vadc->dev); + if (version == -EINVAL) + return 0; + + if (version == QPNP_REV_ID_8026_2_2) { + if (die_temp > 25000) + return 0; + } + + switch (version) { + case QPNP_REV_ID_8941_3_1: + switch (vadc->id) { + case COMP_ID_TSMC: + temp_var = ((die_temp - 25000) * + (-QPNP_VBAT_COEFF_4)); + break; + default: + case COMP_ID_GF: + temp_var = ((die_temp - 25000) * + (-QPNP_VBAT_COEFF_1)); + break; + } + break; + case QPNP_REV_ID_8026_1_0: + switch (vadc->id) { + case COMP_ID_TSMC: + temp_var = (((die_temp * + (-QPNP_VBAT_COEFF_10)) + - QPNP_VBAT_COEFF_14)); + break; + default: + case COMP_ID_GF: + temp_var = (((die_temp * + (-QPNP_VBAT_COEFF_8)) + + QPNP_VBAT_COEFF_12)); + break; + } + break; + case QPNP_REV_ID_8026_2_0: + case QPNP_REV_ID_8026_2_1: + switch (vadc->id) { + case COMP_ID_TSMC: + temp_var = ((die_temp - 25000) * + (-QPNP_VBAT_COEFF_10)); + break; + default: + case COMP_ID_GF: + temp_var = ((die_temp - 25000) * + (-QPNP_VBAT_COEFF_8)); + break; + } + break; + case QPNP_REV_ID_8026_2_2: + switch (vadc->id) { + case COMP_ID_TSMC: + *result -= QPNP_VBAT_COEFF_22; + temp_var = (die_temp - 25000) * + QPNP_VBAT_COEFF_24; + break; + default: + case COMP_ID_GF: + *result -= QPNP_VBAT_COEFF_22; + temp_var = (die_temp - 25000) * + QPNP_VBAT_COEFF_25; + break; + } + break; + case QPNP_REV_ID_8110_2_0: + switch (vadc->id) { + case COMP_ID_SMIC: + *result -= QPNP_OCV_OFFSET_SMIC; + if (die_temp < 25000) + temp_var = QPNP_VBAT_COEFF_18; + else + temp_var = QPNP_VBAT_COEFF_19; + temp_var = (die_temp - 25000) * temp_var; + break; + default: + case COMP_ID_GF: + *result -= QPNP_OCV_OFFSET_GF; + if (die_temp < 25000) + temp_var = QPNP_VBAT_COEFF_20; + else + temp_var = QPNP_VBAT_COEFF_21; + temp_var = (die_temp - 25000) * temp_var; + break; + } + break; + case QPNP_REV_ID_8916_1_0: + switch (vadc->id) { + case COMP_ID_SMIC: + if (die_temp < 25000) + temp_var = QPNP_VBAT_COEFF_26; + else + temp_var = QPNP_VBAT_COEFF_27; + temp_var = (die_temp - 25000) * temp_var; + break; + default: + case COMP_ID_GF: + offset = QPNP_OCV_OFFSET_GF; + if (die_temp < 25000) + temp_var = QPNP_VBAT_COEFF_26; + else + temp_var = QPNP_VBAT_COEFF_27; + temp_var = (die_temp - 25000) * temp_var; + break; + } + break; + case QPNP_REV_ID_8916_1_1: + switch (vadc->id) { + /* FAB_ID is zero */ + case COMP_ID_GF: + if (die_temp < 25000) + temp_var = QPNP_VBAT_COEFF_29; + else + temp_var = QPNP_VBAT_COEFF_30; + temp_var = (die_temp - 25000) * temp_var; + break; + /* FAB_ID is non-zero */ + default: + if (die_temp < 25000) + temp_var = QPNP_VBAT_COEFF_31; + else + temp_var = (-QPNP_VBAT_COEFF_32); + temp_var = (die_temp - 25000) * temp_var; + break; + } + break; + case QPNP_REV_ID_8916_2_0: + switch (vadc->id) { + case COMP_ID_SMIC: + offset = (-QPNP_VBAT_COEFF_38); + if (die_temp < 0) + temp_var = die_temp * QPNP_VBAT_COEFF_36; + else if (die_temp > 40000) + temp_var = ((die_temp - 40000) * + (-QPNP_VBAT_COEFF_37)); + break; + case COMP_ID_TSMC: + if (die_temp < 10000) + temp_var = ((die_temp - 10000) * + QPNP_VBAT_COEFF_41); + else if (die_temp > 50000) + temp_var = ((die_temp - 50000) * + (-QPNP_VBAT_COEFF_42)); + break; + default: + case COMP_ID_GF: + if (die_temp < 20000) + temp_var = ((die_temp - 20000) * + QPNP_VBAT_COEFF_45); + else if (die_temp > 40000) + temp_var = ((die_temp - 40000) * + (-QPNP_VBAT_COEFF_46)); + break; + } + break; + case QPNP_REV_ID_8909_1_0: + switch (vadc->id) { + case COMP_ID_SMIC: + temp_var = (-QPNP_VBAT_COEFF_50); + break; + } + break; + case QPNP_REV_ID_8909_1_1: + switch (vadc->id) { + case COMP_ID_SMIC: + temp_var = (QPNP_VBAT_COEFF_52); + break; + } + break; + default: + temp_var = 0; + break; + } + + temp_var = div64_s64(temp_var, QPNP_VBAT_COEFF_3); + + temp_var = 1000000 + temp_var; + + *result = *result * temp_var; + + if (offset) + *result -= offset; + + *result = div64_s64(*result, 1000000); + pr_debug("%lld compensated into %lld\n", old, *result); + + return 0; +} + +static int32_t qpnp_vbat_sns_comp(int64_t *result, + struct qpnp_vadc_chip *vadc, int64_t die_temp) +{ + int64_t temp_var = 0, offset = 0; + int64_t old = *result; + int version; + + version = qpnp_adc_get_revid_version(vadc->dev); + if (version == -EINVAL) + return 0; + + if (version != QPNP_REV_ID_8941_3_1) { + /* min(die_temp_c, 60_degC) */ + if (die_temp > 60000) + die_temp = 60000; + } + + switch (version) { + case QPNP_REV_ID_8941_3_1: + switch (vadc->id) { + case COMP_ID_TSMC: + temp_var = ((die_temp - 25000) * + (-QPNP_VBAT_COEFF_1)); + break; + default: + case COMP_ID_GF: + /* min(die_temp_c, 60_degC) */ + if (die_temp > 60000) + die_temp = 60000; + temp_var = ((die_temp - 25000) * + (-QPNP_VBAT_COEFF_1)); + break; + } + break; + case QPNP_REV_ID_8026_1_0: + switch (vadc->id) { + case COMP_ID_TSMC: + temp_var = (((die_temp * + (-QPNP_VBAT_COEFF_11)) + + QPNP_VBAT_COEFF_15)); + break; + default: + case COMP_ID_GF: + temp_var = (((die_temp * + (-QPNP_VBAT_COEFF_9)) + + QPNP_VBAT_COEFF_13)); + break; + } + break; + case QPNP_REV_ID_8026_2_0: + case QPNP_REV_ID_8026_2_1: + switch (vadc->id) { + case COMP_ID_TSMC: + temp_var = ((die_temp - 25000) * + (-QPNP_VBAT_COEFF_11)); + break; + default: + case COMP_ID_GF: + temp_var = ((die_temp - 25000) * + (-QPNP_VBAT_COEFF_9)); + break; + } + break; + case QPNP_REV_ID_8026_2_2: + switch (vadc->id) { + case COMP_ID_TSMC: + *result -= QPNP_VBAT_COEFF_23; + temp_var = 0; + break; + default: + case COMP_ID_GF: + *result -= QPNP_VBAT_COEFF_23; + temp_var = 0; + break; + } + break; + case QPNP_REV_ID_8110_2_0: + switch (vadc->id) { + case COMP_ID_SMIC: + *result -= QPNP_VBAT_OFFSET_SMIC; + temp_var = ((die_temp - 25000) * + (QPNP_VBAT_COEFF_17)); + break; + default: + case COMP_ID_GF: + *result -= QPNP_VBAT_OFFSET_GF; + temp_var = ((die_temp - 25000) * + (QPNP_VBAT_COEFF_16)); + break; + } + break; + case QPNP_REV_ID_8916_1_0: + switch (vadc->id) { + case COMP_ID_SMIC: + temp_var = ((die_temp - 25000) * + (QPNP_VBAT_COEFF_28)); + break; + default: + case COMP_ID_GF: + temp_var = ((die_temp - 25000) * + (QPNP_VBAT_COEFF_28)); + break; + } + break; + case QPNP_REV_ID_8916_1_1: + switch (vadc->id) { + /* FAB_ID is zero */ + case COMP_ID_GF: + temp_var = ((die_temp - 25000) * + (QPNP_VBAT_COEFF_33)); + break; + /* FAB_ID is non-zero */ + default: + offset = QPNP_VBAT_COEFF_35; + if (die_temp > 50000) { + temp_var = ((die_temp - 25000) * + (QPNP_VBAT_COEFF_34)); + } + break; + } + break; + case QPNP_REV_ID_8916_2_0: + switch (vadc->id) { + case COMP_ID_SMIC: + if (die_temp < 0) { + temp_var = (die_temp * + QPNP_VBAT_COEFF_39); + } else if (die_temp > 40000) { + temp_var = ((die_temp - 40000) * + (-QPNP_VBAT_COEFF_40)); + } + break; + case COMP_ID_TSMC: + if (die_temp < 10000) + temp_var = ((die_temp - 10000) * + QPNP_VBAT_COEFF_43); + else if (die_temp > 50000) + temp_var = ((die_temp - 50000) * + (-QPNP_VBAT_COEFF_44)); + break; + default: + case COMP_ID_GF: + if (die_temp < 20000) + temp_var = ((die_temp - 20000) * + QPNP_VBAT_COEFF_47); + else if (die_temp > 40000) + temp_var = ((die_temp - 40000) * + (-QPNP_VBAT_COEFF_48)); + break; + } + break; + case QPNP_REV_ID_8909_1_0: + switch (vadc->id) { + case COMP_ID_SMIC: + if (die_temp < 30000) + temp_var = (-QPNP_VBAT_COEFF_50); + else if (die_temp > 30000) + temp_var = (((die_temp - 30000) * + (-QPNP_VBAT_COEFF_49)) + + (-QPNP_VBAT_COEFF_50)); + break; + } + break; + case QPNP_REV_ID_8909_1_1: + switch (vadc->id) { + case COMP_ID_SMIC: + if (die_temp < 30000) + temp_var = (QPNP_VBAT_COEFF_52); + else if (die_temp > 30000) + temp_var = (((die_temp - 30000) * + (-QPNP_VBAT_COEFF_51)) + + (QPNP_VBAT_COEFF_52)); + break; + } + break; + default: + temp_var = 0; + break; + } + + temp_var = div64_s64(temp_var, QPNP_VBAT_COEFF_3); + + temp_var = 1000000 + temp_var; + + *result = *result * temp_var; + + if (offset) + *result -= offset; + + *result = div64_s64(*result, 1000000); + pr_debug("%lld compensated into %lld\n", old, *result); + + return 0; +} + +int32_t qpnp_vbat_sns_comp_result(struct qpnp_vadc_chip *vadc, + int64_t *result, bool is_pon_ocv) +{ + struct qpnp_vadc_result die_temp_result; + int rc = 0; + + rc = qpnp_vadc_is_valid(vadc); + if (rc < 0) + return rc; + + rc = qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE, + DIE_TEMP, &die_temp_result); + if (rc < 0) { + pr_err("Error reading die_temp\n"); + return rc; + } + + pr_debug("die-temp = %lld\n", die_temp_result.physical); + + if (is_pon_ocv) + rc = qpnp_ocv_comp(result, vadc, die_temp_result.physical); + else + rc = qpnp_vbat_sns_comp(result, vadc, + die_temp_result.physical); + + if (rc < 0) + pr_err("Error with vbat compensation\n"); + + return rc; +} +EXPORT_SYMBOL(qpnp_vbat_sns_comp_result); + +static void qpnp_vadc_625mv_channel_sel(struct qpnp_vadc_chip *vadc, + uint32_t *ref_channel_sel) +{ + uint32_t dt_index = 0; + + /* Check if the buffered 625mV channel exists */ + while ((vadc->adc->adc_channels[dt_index].channel_num + != SPARE1) && (dt_index < vadc->max_channels_available)) + dt_index++; + + if (dt_index >= vadc->max_channels_available) { + pr_debug("Use default 625mV ref channel\n"); + *ref_channel_sel = REF_625MV; + } else { + pr_debug("Use buffered 625mV ref channel\n"); + *ref_channel_sel = SPARE1; + } +} + +int32_t qpnp_vadc_calib_vref(struct qpnp_vadc_chip *vadc, + enum qpnp_adc_calib_type calib_type, + int *calib_data) +{ + struct qpnp_adc_amux_properties conv; + int rc, count = 0, calib_read = 0; + u8 status1 = 0; + + if (vadc->vadc_hc) { + if (calib_type == ADC_HC_ABS_CAL) + conv.amux_channel = VADC_CALIB_VREF_1P25; + else if (calib_type == CALIB_RATIOMETRIC) + conv.amux_channel = VADC_CALIB_VREF; + } else { + if (calib_type == CALIB_ABSOLUTE) + conv.amux_channel = REF_125V; + else if (calib_type == CALIB_RATIOMETRIC) + conv.amux_channel = VDD_VADC; + } + + conv.decimation = DECIMATION_TYPE2; + conv.mode_sel = ADC_OP_NORMAL_MODE << QPNP_VADC_OP_MODE_SHIFT; + conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US; + conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1; + conv.cal_val = (enum qpnp_adc_cal_val)calib_type; + + if (vadc->vadc_hc) { + rc = qpnp_vadc_hc_configure(vadc, &conv); + if (rc) { + pr_err("qpnp_vadc configure failed with %d\n", rc); + goto calib_fail; + } + } else { + rc = qpnp_vadc_configure(vadc, &conv); + if (rc) { + pr_err("qpnp_vadc configure failed with %d\n", rc); + goto calib_fail; + } + } + + while (status1 != QPNP_VADC_STATUS1_EOC) { + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); + if (rc < 0) + return rc; + status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; + usleep_range(QPNP_VADC_CONV_TIME_MIN, + QPNP_VADC_CONV_TIME_MAX); + count++; + if (count > QPNP_VADC_ERR_COUNT) { + rc = -ENODEV; + goto calib_fail; + } + } + + if (vadc->vadc_hc) { + rc = qpnp_vadc_hc_read_data(vadc, &calib_read); + if (rc) { + pr_err("qpnp vadc read adc code failed with %d\n", rc); + goto calib_fail; + } + } else { + rc = qpnp_vadc_read_conversion_result(vadc, &calib_read); + if (rc) { + pr_err("qpnp adc read adc failed with %d\n", rc); + goto calib_fail; + } + } + + *calib_data = calib_read; +calib_fail: + return rc; +} + + +int32_t qpnp_vadc_calib_gnd(struct qpnp_vadc_chip *vadc, + enum qpnp_adc_calib_type calib_type, + int *calib_data) +{ + struct qpnp_adc_amux_properties conv; + int rc, count = 0, calib_read = 0; + u8 status1 = 0; + uint32_t ref_channel_sel = 0; + + if (vadc->vadc_hc) { + conv.amux_channel = VADC_VREF_GND; + } else { + if (calib_type == CALIB_ABSOLUTE) { + qpnp_vadc_625mv_channel_sel(vadc, &ref_channel_sel); + conv.amux_channel = ref_channel_sel; + } else if (calib_type == CALIB_RATIOMETRIC) + conv.amux_channel = GND_REF; + } + + conv.decimation = DECIMATION_TYPE2; + conv.mode_sel = ADC_OP_NORMAL_MODE << QPNP_VADC_OP_MODE_SHIFT; + conv.hw_settle_time = ADC_CHANNEL_HW_SETTLE_DELAY_0US; + conv.fast_avg_setup = ADC_FAST_AVG_SAMPLE_1; + conv.cal_val = (enum qpnp_adc_cal_val)calib_type; + + if (vadc->vadc_hc) { + rc = qpnp_vadc_hc_configure(vadc, &conv); + if (rc) { + pr_err("qpnp_vadc configure failed with %d\n", rc); + goto calib_fail; + } + } else { + rc = qpnp_vadc_configure(vadc, &conv); + if (rc) { + pr_err("qpnp_vadc configure failed with %d\n", rc); + goto calib_fail; + } + } + + while (status1 != QPNP_VADC_STATUS1_EOC) { + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); + if (rc < 0) + return rc; + status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; + usleep_range(QPNP_VADC_CONV_TIME_MIN, + QPNP_VADC_CONV_TIME_MAX); + count++; + if (count > QPNP_VADC_ERR_COUNT) { + rc = -ENODEV; + goto calib_fail; + } + } + + if (vadc->vadc_hc) { + rc = qpnp_vadc_hc_read_data(vadc, &calib_read); + if (rc) { + pr_err("qpnp vadc read adc code failed with %d\n", rc); + goto calib_fail; + } + } else { + rc = qpnp_vadc_read_conversion_result(vadc, &calib_read); + if (rc) { + pr_err("qpnp adc read adc failed with %d\n", rc); + goto calib_fail; + } + } + *calib_data = calib_read; +calib_fail: + return rc; +} + +static int32_t qpnp_vadc_calib_device(struct qpnp_vadc_chip *vadc) +{ + int rc, calib_read_1 = 0, calib_read_2 = 0; + enum qpnp_adc_calib_type calib_type; + + if (vadc->vadc_hc) + calib_type = ADC_HC_ABS_CAL; + else + calib_type = CALIB_ABSOLUTE; + + rc = qpnp_vadc_calib_vref(vadc, calib_type, &calib_read_1); + if (rc) { + pr_err("qpnp adc absolute vref calib failed with %d\n", rc); + goto calib_fail; + } + rc = qpnp_vadc_calib_gnd(vadc, calib_type, &calib_read_2); + if (rc) { + pr_err("qpnp adc absolute gnd calib failed with %d\n", rc); + goto calib_fail; + } + pr_debug("absolute reference raw: 1.25V:0x%x, 625mV/GND:0x%x\n", + calib_read_1, calib_read_2); + + if (calib_read_1 == calib_read_2) { + pr_err("absolute reference raw: 1.25V:0x%x625mV:0x%x\n", + calib_read_2, calib_read_1); + rc = -EINVAL; + goto calib_fail; + } + + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dy = + (calib_read_1 - calib_read_2); + + if (calib_type == CALIB_ABSOLUTE) + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dx + = QPNP_ADC_625_UV; + else if (calib_type == ADC_HC_ABS_CAL) + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dx + = QPNP_ADC_1P25_UV; + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].adc_vref = + calib_read_1; + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].adc_gnd = + calib_read_2; + + calib_read_1 = 0; + calib_read_2 = 0; + rc = qpnp_vadc_calib_vref(vadc, CALIB_RATIOMETRIC, &calib_read_1); + if (rc) { + pr_err("qpnp adc ratiometric vref calib failed with %d\n", rc); + goto calib_fail; + } + rc = qpnp_vadc_calib_gnd(vadc, CALIB_RATIOMETRIC, &calib_read_2); + if (rc) { + pr_err("qpnp adc ratiometric gnd calib failed with %d\n", rc); + goto calib_fail; + } + pr_debug("ratiometric reference raw: VDD:0x%x GND:0x%x\n", + calib_read_1, calib_read_2); + + if (calib_read_1 == calib_read_2) { + pr_err("ratiometric reference raw: VDD:0x%x GND:0x%x\n", + calib_read_1, calib_read_2); + rc = -EINVAL; + goto calib_fail; + } + + vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].dy = + (calib_read_1 - calib_read_2); + vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].dx = + vadc->adc->adc_prop->adc_vdd_reference; + vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].adc_vref = + calib_read_1; + vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].adc_gnd = + calib_read_2; + +calib_fail: + return rc; +} + +int32_t qpnp_get_vadc_gain_and_offset(struct qpnp_vadc_chip *vadc, + struct qpnp_vadc_linear_graph *param, + enum qpnp_adc_calib_type calib_type) +{ + int rc = 0; + struct qpnp_vadc_result result; + + rc = qpnp_vadc_is_valid(vadc); + if (rc < 0) + return rc; + + if (!vadc->vadc_init_calib) { + if (vadc->vadc_hc) { + rc = qpnp_vadc_hc_read(vadc, VADC_CALIB_VREF_1P25, + &result); + if (rc) { + pr_debug("vadc read failed with rc = %d\n", rc); + return rc; + } + } else { + rc = qpnp_vadc_read(vadc, REF_125V, &result); + if (rc) { + pr_debug("vadc read failed with rc = %d\n", rc); + return rc; + } + } + } + + switch (calib_type) { + case CALIB_RATIOMETRIC: + param->dy = + vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].dy; + param->dx = + vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].dx; + param->adc_vref = vadc->adc->adc_prop->adc_vdd_reference; + param->adc_gnd = + vadc->adc->amux_prop->chan_prop->adc_graph[CALIB_RATIOMETRIC].adc_gnd; + break; + case CALIB_ABSOLUTE: + case ADC_HC_ABS_CAL: + param->dy = + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dy; + param->dx = + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dx; + param->adc_vref = vadc->adc->adc_prop->adc_vdd_reference; + param->adc_gnd = + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].adc_gnd; + break; + default: + rc = -EINVAL; + } + + return rc; +} +EXPORT_SYMBOL(qpnp_get_vadc_gain_and_offset); + +static int32_t qpnp_vadc_wait_for_req_sts_check(struct qpnp_vadc_chip *vadc) +{ + u8 status1 = 0; + int rc, count = 0; + + /* Re-enable the peripheral */ + rc = qpnp_vadc_enable(vadc, true); + if (rc) { + pr_err("vadc re-enable peripheral failed with %d\n", rc); + return rc; + } + + /* The VADC_TM bank needs to be disabled for new conversion request */ + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); + if (rc) { + pr_err("vadc read status1 failed with %d\n", rc); + return rc; + } + + /* Disable the bank if a conversion is occuring */ + while ((status1 & QPNP_VADC_STATUS1_REQ_STS) && (count < QPNP_RETRY)) { + /* Wait time is based on the optimum sampling rate + * and adding enough time buffer to account for ADC conversions + * occurring on different peripheral banks + */ + usleep_range(QPNP_MIN_TIME, QPNP_MAX_TIME); + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); + if (rc < 0) { + pr_err("vadc disable failed with %d\n", rc); + return rc; + } + count++; + } + + if (count >= QPNP_RETRY) + pr_err("QPNP vadc status req bit did not fall low!!\n"); + + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status1, 1); + + /* Disable the peripheral */ + rc = qpnp_vadc_enable(vadc, false); + if (rc < 0) + pr_err("vadc peripheral disable failed with %d\n", rc); + + return rc; +} + +static int32_t qpnp_vadc_manage_meas_int_requests(struct qpnp_vadc_chip *chip) +{ + struct qpnp_vadc_chip *vadc = dev_get_drvdata(chip->dev); + int rc = 0, dt_index = 0; + u8 mode_ctl = 0; + + pr_debug("meas_int_mode:0x%x, mode_ctl:%0x\n", + vadc->state_copy->meas_int_mode, mode_ctl); + + if (vadc->state_copy->meas_int_mode) { + pr_debug("meas interval in progress. Procced to disable it\n"); + /* measurement interval in progress. Proceed to disable it */ + mode_ctl = ADC_OP_NORMAL_MODE; + rc = qpnp_vadc_mode_select(vadc, mode_ctl); + if (rc < 0) { + pr_err("NORM mode select failed with %d\n", rc); + return rc; + } + + /* Disable bank */ + rc = qpnp_vadc_enable(vadc, false); + if (rc) { + pr_err("Disable bank failed with %d\n", rc); + return rc; + } + + /* Check if a conversion is in progress */ + rc = qpnp_vadc_wait_for_req_sts_check(vadc); + if (rc < 0) { + pr_err("req_sts check failed with %d\n", rc); + return rc; + } + + vadc->state_copy->meas_int_mode = false; + vadc->state_copy->meas_int_request_in_queue = true; + } else if (vadc->state_copy->meas_int_request_in_queue) { + /* put the meas interval back in queue */ + pr_debug("put meas interval back in queue\n"); + vadc->adc->amux_prop->amux_channel = + vadc->state_copy->vadc_meas_amux.channel_num; + while ((vadc->adc->adc_channels[dt_index].channel_num + != vadc->adc->amux_prop->amux_channel) && + (dt_index < vadc->max_channels_available)) + dt_index++; + if (dt_index >= vadc->max_channels_available) { + pr_err("not a valid VADC channel\n"); + rc = -EINVAL; + return rc; + } + + vadc->adc->amux_prop->decimation = + vadc->adc->amux_prop->decimation; + vadc->adc->amux_prop->hw_settle_time = + vadc->adc->amux_prop->hw_settle_time; + vadc->adc->amux_prop->fast_avg_setup = + vadc->adc->amux_prop->fast_avg_setup; + vadc->adc->amux_prop->mode_sel = ADC_OP_MEASUREMENT_INTERVAL; + rc = qpnp_vadc_configure(vadc, vadc->adc->amux_prop); + if (rc) { + pr_err("vadc configure failed with %d\n", rc); + return rc; + } + + vadc->state_copy->meas_int_mode = true; + vadc->state_copy->meas_int_request_in_queue = false; + } + dev_set_drvdata(vadc->dev, vadc); + + return 0; +} + +struct qpnp_vadc_chip *qpnp_get_vadc(struct device *dev, const char *name) +{ + struct qpnp_vadc_chip *vadc; + struct device_node *node = NULL; + char prop_name[QPNP_MAX_PROP_NAME_LEN]; + + snprintf(prop_name, QPNP_MAX_PROP_NAME_LEN, "qcom,%s-vadc", name); + + node = of_parse_phandle(dev->of_node, prop_name, 0); + if (node == NULL) + return ERR_PTR(-ENODEV); + + list_for_each_entry(vadc, &qpnp_vadc_device_list, list) + if (vadc->adc->pdev->dev.of_node == node) + return vadc; + return ERR_PTR(-EPROBE_DEFER); +} +EXPORT_SYMBOL(qpnp_get_vadc); + +int32_t qpnp_vadc_conv_seq_request(struct qpnp_vadc_chip *vadc, + enum qpnp_vadc_trigger trigger_channel, + enum qpnp_vadc_channels channel, + struct qpnp_vadc_result *result) +{ + int rc = 0, scale_type, amux_prescaling, dt_index = 0, calib_type = 0; + uint32_t ref_channel, count = 0, local_idx = 0; + int32_t vref_calib = 0, gnd_calib = 0, new_vref_calib = 0, offset = 0; + int32_t calib_offset = 0; + u8 status1 = 0; + + if (qpnp_vadc_is_valid(vadc)) + return -EPROBE_DEFER; + + mutex_lock(&vadc->adc->adc_lock); + + if (vadc->state_copy->vadc_meas_int_enable) + qpnp_vadc_manage_meas_int_requests(vadc); + + if (channel == REF_625MV) { + qpnp_vadc_625mv_channel_sel(vadc, &ref_channel); + channel = ref_channel; + } + + vadc->adc->amux_prop->amux_channel = channel; + + while ((vadc->adc->adc_channels[dt_index].channel_num + != channel) && (dt_index < vadc->max_channels_available)) + dt_index++; + + if (dt_index >= vadc->max_channels_available) { + pr_err("not a valid VADC channel\n"); + rc = -EINVAL; + goto fail_unlock; + } + + calib_type = vadc->adc->adc_channels[dt_index].calib_type; + if (calib_type >= CALIB_NONE) { + pr_err("not a valid calib_type\n"); + rc = -EINVAL; + goto fail_unlock; + } + calib_offset = (calib_type == CALIB_ABSOLUTE) ? + QPNP_VADC_ABSOLUTE_RECALIB_OFFSET : + QPNP_VADC_RATIOMETRIC_RECALIB_OFFSET; + rc = qpnp_vadc_version_check(vadc); + if (rc) + goto fail_unlock; + if (vadc->vadc_recalib_check) { + rc = qpnp_vadc_calib_vref(vadc, calib_type, &vref_calib); + if (rc) { + pr_err("Calibration failed\n"); + goto fail_unlock; + } + } else if (!vadc->vadc_init_calib) { + rc = qpnp_vadc_calib_device(vadc); + if (rc) { + pr_err("Calibration failed\n"); + goto fail_unlock; + } else { + vadc->vadc_init_calib = true; + } + } + +recalibrate: + status1 = 0; + vadc->adc->amux_prop->decimation = + vadc->adc->adc_channels[dt_index].adc_decimation; + vadc->adc->amux_prop->hw_settle_time = + vadc->adc->adc_channels[dt_index].hw_settle_time; + vadc->adc->amux_prop->fast_avg_setup = + vadc->adc->adc_channels[dt_index].fast_avg_setup; + + if (trigger_channel < ADC_SEQ_NONE) + vadc->adc->amux_prop->mode_sel = (ADC_OP_CONVERSION_SEQUENCER + << QPNP_VADC_OP_MODE_SHIFT); + else if (trigger_channel == ADC_SEQ_NONE) + vadc->adc->amux_prop->mode_sel = (ADC_OP_NORMAL_MODE + << QPNP_VADC_OP_MODE_SHIFT); + else { + pr_err("Invalid trigger channel:%d\n", trigger_channel); + goto fail_unlock; + } + + vadc->adc->amux_prop->trigger_channel = trigger_channel; + + rc = qpnp_vadc_configure(vadc, vadc->adc->amux_prop); + if (rc) { + pr_err("qpnp vadc configure failed with %d\n", rc); + goto fail_unlock; + } + + if (vadc->vadc_poll_eoc) { + while (status1 != QPNP_VADC_STATUS1_EOC) { + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, + &status1, 1); + if (rc < 0) + goto fail_unlock; + status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; + if (status1 == QPNP_VADC_STATUS1_EOC) + break; + usleep_range(QPNP_VADC_CONV_TIME_MIN, + QPNP_VADC_CONV_TIME_MAX); + count++; + if (count > QPNP_VADC_ERR_COUNT) { + pr_err("retry error exceeded\n"); + rc = qpnp_vadc_status_debug(vadc); + if (rc < 0) + pr_err("VADC disable failed\n"); + rc = -EINVAL; + goto fail_unlock; + } + } + } else { + rc = wait_for_completion_timeout( + &vadc->adc->adc_rslt_completion, + QPNP_ADC_COMPLETION_TIMEOUT); + if (!rc) { + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, + &status1, 1); + if (rc < 0) + goto fail_unlock; + status1 &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; + if (status1 == QPNP_VADC_STATUS1_EOC) + pr_debug("End of conversion status set\n"); + else { + rc = qpnp_vadc_status_debug(vadc); + if (rc < 0) + pr_err("VADC disable failed\n"); + rc = -EINVAL; + goto fail_unlock; + } + } + } + + if (trigger_channel < ADC_SEQ_NONE) { + rc = qpnp_vadc_read_status(vadc, + vadc->adc->amux_prop->mode_sel); + if (rc) + pr_debug("Conversion sequence timed out - %d\n", rc); + } + + rc = qpnp_vadc_read_conversion_result(vadc, &result->adc_code); + if (rc) { + pr_err("qpnp vadc read adc code failed with %d\n", rc); + goto fail_unlock; + } + + if (vadc->vadc_recalib_check) { + rc = qpnp_vadc_calib_gnd(vadc, calib_type, &gnd_calib); + if (rc) { + pr_err("Calibration failed\n"); + goto fail_unlock; + } + rc = qpnp_vadc_calib_vref(vadc, calib_type, &new_vref_calib); + if (rc < 0) { + pr_err("qpnp vadc calib read failed with %d\n", rc); + goto fail_unlock; + } + + if (local_idx >= QPNP_VADC_RECALIB_MAXCNT) { + pr_err("invalid recalib count=%d\n", local_idx); + rc = -EINVAL; + goto fail_unlock; + } + pr_debug( + "chan=%d, calib=%s, vref_calib=0x%x, gnd_calib=0x%x, new_vref_calib=0x%x\n", + channel, + ((calib_type == CALIB_ABSOLUTE) ? + "ABSOLUTE" : "RATIOMETRIC"), + vref_calib, gnd_calib, new_vref_calib); + + offset = (new_vref_calib - vref_calib); + if (offset < 0) + offset = -offset; + if (offset <= calib_offset) { + pr_debug( + "qpnp vadc recalibration not required,offset:%d\n", + offset); + local_idx = 0; + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dy = + (vref_calib - gnd_calib); + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].dx = + (calib_type == CALIB_ABSOLUTE) ? QPNP_ADC_625_UV : + vadc->adc->adc_prop->adc_vdd_reference; + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].adc_vref + = vref_calib; + vadc->adc->amux_prop->chan_prop->adc_graph[calib_type].adc_gnd + = gnd_calib; + } else { + vref_calib = new_vref_calib; + local_idx = local_idx + 1; + if (local_idx >= QPNP_VADC_RECALIB_MAXCNT) { + pr_err( + "qpnp_vadc recalibration failed, count=%d", + local_idx); + } else { + pr_debug( + "qpnp vadc recalibration requested,offset:%d\n", + offset); + offset = 0; + goto recalibrate; + } + } + } + + amux_prescaling = + vadc->adc->adc_channels[dt_index].chan_path_prescaling; + + if (amux_prescaling >= PATH_SCALING_NONE) { + rc = -EINVAL; + goto fail_unlock; + } + + vadc->adc->amux_prop->chan_prop->offset_gain_numerator = + qpnp_vadc_amux_scaling_ratio[amux_prescaling].num; + vadc->adc->amux_prop->chan_prop->offset_gain_denominator = + qpnp_vadc_amux_scaling_ratio[amux_prescaling].den; + vadc->adc->amux_prop->chan_prop->calib_type = + vadc->adc->adc_channels[dt_index].calib_type; + + scale_type = vadc->adc->adc_channels[dt_index].adc_scale_fn; + if (scale_type >= SCALE_NONE) { + rc = -EBADF; + goto fail_unlock; + } + + if ((qpnp_vadc_channel_post_scaling_calib_check(vadc, channel)) < 0) + pr_debug("Post scaling calib type not updated\n"); + + vadc_scale_fn[scale_type].chan(vadc, result->adc_code, + vadc->adc->adc_prop, vadc->adc->amux_prop->chan_prop, result); + + pr_debug("channel=%d, adc_code=%d adc_result=%lld\n", + channel, result->adc_code, result->physical); + +fail_unlock: + if (vadc->state_copy->vadc_meas_int_enable) + qpnp_vadc_manage_meas_int_requests(vadc); + + mutex_unlock(&vadc->adc->adc_lock); + + return rc; +} +EXPORT_SYMBOL(qpnp_vadc_conv_seq_request); + +int32_t qpnp_vadc_read(struct qpnp_vadc_chip *vadc, + enum qpnp_vadc_channels channel, + struct qpnp_vadc_result *result) +{ + struct qpnp_vadc_result die_temp_result; + int rc = 0; + enum power_supply_property prop; + union power_supply_propval ret = {0, }; + + if (vadc->vadc_hc) { + rc = qpnp_vadc_hc_read(vadc, channel, result); + if (rc < 0) { + pr_err("Error reading vadc_hc channel %d\n", channel); + return rc; + } + + return 0; + } + + if (channel == VBAT_SNS) { + rc = qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE, + channel, result); + if (rc < 0) { + pr_err("Error reading vbatt\n"); + return rc; + } + + rc = qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE, + DIE_TEMP, &die_temp_result); + if (rc < 0) { + pr_err("Error reading die_temp\n"); + return rc; + } + + rc = qpnp_vbat_sns_comp(&result->physical, vadc, + die_temp_result.physical); + if (rc < 0) + pr_err("Error with vbat compensation\n"); + + return 0; + } else if (channel == SPARE2) { + /* chg temp channel */ + if (!vadc->vadc_chg_vote) { + vadc->vadc_chg_vote = + power_supply_get_by_name("battery"); + if (!vadc->vadc_chg_vote) { + pr_err("no vadc_chg_vote found\n"); + return -EINVAL; + } + } + + prop = POWER_SUPPLY_PROP_FORCE_TLIM; + ret.intval = 1; + + rc = power_supply_set_property(vadc->vadc_chg_vote, + prop, &ret); + if (rc) { + pr_err("error enabling the charger circuitry vote\n"); + return rc; + } + + rc = qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE, + channel, result); + if (rc < 0) + pr_err("Error reading die_temp\n"); + + ret.intval = 0; + rc = power_supply_set_property(vadc->vadc_chg_vote, + prop, &ret); + if (rc) { + pr_err("error enabling the charger circuitry vote\n"); + return rc; + } + + return 0; + } else + return qpnp_vadc_conv_seq_request(vadc, ADC_SEQ_NONE, + channel, result); +} +EXPORT_SYMBOL(qpnp_vadc_read); + +static void qpnp_vadc_lock(struct qpnp_vadc_chip *vadc) +{ + mutex_lock(&vadc->adc->adc_lock); +} + +static void qpnp_vadc_unlock(struct qpnp_vadc_chip *vadc) +{ + mutex_unlock(&vadc->adc->adc_lock); +} + +int32_t qpnp_vadc_iadc_sync_request(struct qpnp_vadc_chip *vadc, + enum qpnp_vadc_channels channel) +{ + int rc = 0, dt_index = 0, calib_type = 0; + + if (qpnp_vadc_is_valid(vadc)) + return -EPROBE_DEFER; + + qpnp_vadc_lock(vadc); + + + vadc->adc->amux_prop->amux_channel = channel; + + while ((vadc->adc->adc_channels[dt_index].channel_num + != channel) && (dt_index < vadc->max_channels_available)) + dt_index++; + + if (dt_index >= vadc->max_channels_available) { + pr_err("not a valid VADC channel\n"); + rc = -EINVAL; + goto fail; + } + + calib_type = vadc->adc->adc_channels[dt_index].calib_type; + if (!vadc->vadc_init_calib) { + rc = qpnp_vadc_version_check(vadc); + if (rc) + goto fail; + + rc = qpnp_vadc_calib_device(vadc); + if (rc) { + pr_err("Calibration failed\n"); + goto fail; + } else + vadc->vadc_init_calib = true; + } + + vadc->adc->amux_prop->decimation = + vadc->adc->adc_channels[dt_index].adc_decimation; + vadc->adc->amux_prop->hw_settle_time = + vadc->adc->adc_channels[dt_index].hw_settle_time; + vadc->adc->amux_prop->fast_avg_setup = + vadc->adc->adc_channels[dt_index].fast_avg_setup; + vadc->adc->amux_prop->mode_sel = (ADC_OP_NORMAL_MODE + << QPNP_VADC_OP_MODE_SHIFT); + vadc->vadc_iadc_sync_lock = true; + + rc = qpnp_vadc_configure(vadc, vadc->adc->amux_prop); + if (rc) { + pr_err("qpnp vadc configure failed with %d\n", rc); + goto fail; + } + + return rc; +fail: + vadc->vadc_iadc_sync_lock = false; + qpnp_vadc_unlock(vadc); + return rc; +} +EXPORT_SYMBOL(qpnp_vadc_iadc_sync_request); + +int32_t qpnp_vadc_iadc_sync_complete_request(struct qpnp_vadc_chip *vadc, + enum qpnp_vadc_channels channel, + struct qpnp_vadc_result *result) +{ + int rc = 0, scale_type, amux_prescaling, dt_index = 0; + + vadc->adc->amux_prop->amux_channel = channel; + + while ((vadc->adc->adc_channels[dt_index].channel_num + != channel) && (dt_index < vadc->max_channels_available)) + dt_index++; + + rc = qpnp_vadc_read_conversion_result(vadc, &result->adc_code); + if (rc) { + pr_err("qpnp vadc read adc code failed with %d\n", rc); + goto fail; + } + + amux_prescaling = + vadc->adc->adc_channels[dt_index].chan_path_prescaling; + + if (amux_prescaling >= PATH_SCALING_NONE) { + rc = -EINVAL; + goto fail; + } + + vadc->adc->amux_prop->chan_prop->offset_gain_numerator = + qpnp_vadc_amux_scaling_ratio[amux_prescaling].num; + vadc->adc->amux_prop->chan_prop->offset_gain_denominator = + qpnp_vadc_amux_scaling_ratio[amux_prescaling].den; + + scale_type = vadc->adc->adc_channels[dt_index].adc_scale_fn; + if (scale_type >= SCALE_NONE) { + rc = -EBADF; + goto fail; + } + + vadc_scale_fn[scale_type].chan(vadc, result->adc_code, + vadc->adc->adc_prop, vadc->adc->amux_prop->chan_prop, result); + +fail: + vadc->vadc_iadc_sync_lock = false; + qpnp_vadc_unlock(vadc); + return rc; +} +EXPORT_SYMBOL(qpnp_vadc_iadc_sync_complete_request); + +static int32_t qpnp_vadc_thr_update(struct qpnp_vadc_chip *vadc, + int32_t high_thr, int32_t low_thr) +{ + int rc = 0; + u8 buf = 0; + + pr_debug("client requested high:%d and low:%d\n", + high_thr, low_thr); + + buf = QPNP_VADC_THR_LSB_MASK(low_thr); + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_LOW_THR_LSB, &buf, 1); + if (rc < 0) { + pr_err("low threshold lsb setting failed, err:%d\n", rc); + return rc; + } + + buf = QPNP_VADC_THR_MSB_MASK(low_thr); + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_LOW_THR_MSB, &buf, 1); + if (rc < 0) { + pr_err("low threshold msb setting failed, err:%d\n", rc); + return rc; + } + + buf = QPNP_VADC_THR_LSB_MASK(high_thr); + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HIGH_THR_LSB, &buf, 1); + if (rc < 0) { + pr_err("high threshold lsb setting failed, err:%d\n", rc); + return rc; + } + + buf = QPNP_VADC_THR_MSB_MASK(high_thr); + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_HIGH_THR_MSB, &buf, 1); + if (rc < 0) { + pr_err("high threshold msb setting failed, err:%d\n", rc); + return rc; + } + + pr_debug("client requested high:%d and low:%d\n", high_thr, low_thr); + + return rc; +} + +int32_t qpnp_vadc_channel_monitor(struct qpnp_vadc_chip *chip, + struct qpnp_adc_tm_btm_param *param) +{ + uint32_t channel, scale_type = 0; + uint32_t low_thr = 0, high_thr = 0; + int rc = 0, idx = 0, amux_prescaling = 0; + struct qpnp_vadc_chip *vadc = dev_get_drvdata(chip->dev); + u8 buf = 0; + + if (qpnp_vadc_is_valid(vadc)) + return -EPROBE_DEFER; + + if (!vadc->state_copy->vadc_meas_int_enable) { + pr_err("Recurring measurement interval not available\n"); + return -EINVAL; + } + + if (param->threshold_notification == NULL) { + pr_debug("No notification for high/low temp??\n"); + return -EINVAL; + } + + mutex_lock(&vadc->adc->adc_lock); + + channel = param->channel; + while (idx < vadc->max_channels_available) { + if (vadc->adc->adc_channels[idx].channel_num == channel) + break; + else + idx++; + } + + if (idx >= vadc->max_channels_available) { + pr_err("not a valid VADC channel\n"); + rc = -EINVAL; + goto fail_unlock; + } + + scale_type = vadc->adc->adc_channels[idx].adc_scale_fn; + if (scale_type >= SCALE_RVADC_SCALE_NONE) { + rc = -EBADF; + goto fail_unlock; + } + + amux_prescaling = + vadc->adc->adc_channels[idx].chan_path_prescaling; + + if (amux_prescaling >= PATH_SCALING_NONE) { + rc = -EINVAL; + goto fail_unlock; + } + + vadc->adc->amux_prop->chan_prop->offset_gain_numerator = + qpnp_vadc_amux_scaling_ratio[amux_prescaling].num; + vadc->adc->amux_prop->chan_prop->offset_gain_denominator = + qpnp_vadc_amux_scaling_ratio[amux_prescaling].den; + vadc->adc->amux_prop->chan_prop->calib_type = + vadc->adc->adc_channels[idx].calib_type; + + pr_debug("channel:%d, scale_type:%d, dt_idx:%d", + channel, scale_type, idx); + vadc->adc->amux_prop->amux_channel = channel; + vadc->adc->amux_prop->decimation = + vadc->adc->adc_channels[idx].adc_decimation; + vadc->adc->amux_prop->hw_settle_time = + vadc->adc->adc_channels[idx].hw_settle_time; + vadc->adc->amux_prop->fast_avg_setup = + vadc->adc->adc_channels[idx].fast_avg_setup; + vadc->adc->amux_prop->mode_sel = ADC_OP_MEASUREMENT_INTERVAL; + adc_vadc_rscale_fn[scale_type].chan(vadc, + vadc->adc->amux_prop->chan_prop, param, + &low_thr, &high_thr); + + if (param->timer_interval >= ADC_MEAS1_INTERVAL_NONE) { + pr_err("Invalid timer interval :%d\n", param->timer_interval); + goto fail_unlock; + } + + buf = param->timer_interval; + rc = qpnp_vadc_write_reg(vadc, QPNP_VADC_MEAS_INTERVAL_CTL, &buf, 1); + if (rc) { + pr_err("vadc meas timer failed with %d\n", rc); + goto fail_unlock; + } + + rc = qpnp_vadc_thr_update(vadc, high_thr, low_thr); + if (rc) { + pr_err("vadc thr update failed with %d\n", rc); + goto fail_unlock; + } + + rc = qpnp_vadc_configure(vadc, vadc->adc->amux_prop); + if (rc) { + pr_err("vadc configure failed with %d\n", rc); + goto fail_unlock; + } + + vadc->state_copy->meas_int_mode = true; + vadc->state_copy->param = param; + vadc->state_copy->vadc_meas_amux.channel_num = channel; + vadc->state_copy->vadc_meas_amux.adc_decimation = + vadc->adc->amux_prop->decimation; + vadc->state_copy->vadc_meas_amux.hw_settle_time = + vadc->adc->amux_prop->hw_settle_time; + vadc->state_copy->vadc_meas_amux.fast_avg_setup = + vadc->adc->amux_prop->fast_avg_setup; + vadc->state_copy->meas_int_request_in_queue = false; + dev_set_drvdata(vadc->dev, vadc); + +fail_unlock: + mutex_unlock(&vadc->adc->adc_lock); + + return rc; +} +EXPORT_SYMBOL(qpnp_vadc_channel_monitor); + +int32_t qpnp_vadc_end_channel_monitor(struct qpnp_vadc_chip *chip) +{ + struct qpnp_vadc_chip *vadc = dev_get_drvdata(chip->dev); + u8 mode_ctl = 0; + + if (qpnp_vadc_is_valid(vadc)) + return -EPROBE_DEFER; + + if (!vadc->state_copy->vadc_meas_int_enable) { + pr_err("Recurring measurement interval not available\n"); + return -EINVAL; + } + + vadc->state_copy->meas_int_mode = false; + vadc->state_copy->meas_int_request_in_queue = false; + dev_set_drvdata(vadc->dev, vadc); + mode_ctl = ADC_OP_NORMAL_MODE; + /* Set measurement in single measurement mode */ + qpnp_vadc_mode_select(vadc, mode_ctl); + qpnp_vadc_enable(vadc, false); + + return 0; +} +EXPORT_SYMBOL(qpnp_vadc_end_channel_monitor); + +static ssize_t qpnp_adc_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct qpnp_vadc_chip *vadc = dev_get_drvdata(dev); + struct qpnp_vadc_result result; + int rc = -1; + + rc = qpnp_vadc_read(vadc, attr->index, &result); + + if (rc) { + pr_err("VADC read error with %d\n", rc); + return 0; + } + + return snprintf(buf, QPNP_ADC_HWMON_NAME_LENGTH, + "Result:%lld Raw:%x\n", result.physical, result.adc_code); +} + +static struct sensor_device_attribute qpnp_adc_attr = + SENSOR_ATTR(NULL, S_IRUGO, qpnp_adc_show, NULL, 0); + +static int32_t qpnp_vadc_init_hwmon(struct qpnp_vadc_chip *vadc, + struct platform_device *pdev) +{ + struct device_node *child; + struct device_node *node = pdev->dev.of_node; + int rc = 0, i = 0, channel; + + for_each_child_of_node(node, child) { + channel = vadc->adc->adc_channels[i].channel_num; + qpnp_adc_attr.index = vadc->adc->adc_channels[i].channel_num; + qpnp_adc_attr.dev_attr.attr.name = + vadc->adc->adc_channels[i].name; + memcpy(&vadc->sens_attr[i], &qpnp_adc_attr, + sizeof(qpnp_adc_attr)); + sysfs_attr_init(&vadc->sens_attr[i].dev_attr.attr); + rc = device_create_file(&pdev->dev, + &vadc->sens_attr[i].dev_attr); + if (rc) { + dev_err(&pdev->dev, + "device_create_file failed for dev %s\n", + vadc->adc->adc_channels[i].name); + goto hwmon_err_sens; + } + i++; + } + + return 0; +hwmon_err_sens: + pr_err("Init HWMON failed for qpnp_adc with %d\n", rc); + return rc; +} + +static int qpnp_vadc_get_temp(struct thermal_zone_device *thermal, + int *temp) +{ + struct qpnp_vadc_thermal_data *vadc_therm = thermal->devdata; + struct qpnp_vadc_chip *vadc = vadc_therm->vadc_dev; + struct qpnp_vadc_result result; + int rc = 0; + + rc = qpnp_vadc_read(vadc, + vadc_therm->vadc_channel, &result); + if (rc) { + if (rc != -EPROBE_DEFER) + pr_err("VADC read error with %d\n", rc); + return rc; + } + + *temp = result.physical; + + return rc; +} + +static struct thermal_zone_device_ops qpnp_vadc_thermal_ops = { + .get_temp = qpnp_vadc_get_temp, +}; + +static int32_t qpnp_vadc_init_thermal(struct qpnp_vadc_chip *vadc, + struct platform_device *pdev) +{ + struct device_node *child; + struct device_node *node = pdev->dev.of_node; + int rc = 0, i = 0; + bool thermal_node = false; + + if (node == NULL) + goto thermal_err_sens; + for_each_child_of_node(node, child) { + char name[QPNP_THERMALNODE_NAME_LENGTH]; + + vadc->vadc_therm_chan[i].vadc_channel = + vadc->adc->adc_channels[i].channel_num; + vadc->vadc_therm_chan[i].thermal_chan = i; + thermal_node = of_property_read_bool(child, + "qcom,vadc-thermal-node"); + if (thermal_node) { + /* Register with the thermal zone */ + vadc->vadc_therm_chan[i].thermal_node = true; + snprintf(name, sizeof(name), "%s", + vadc->adc->adc_channels[i].name); + vadc->vadc_therm_chan[i].vadc_dev = vadc; + vadc->vadc_therm_chan[i].tz_dev = + thermal_zone_device_register(name, + 0, 0, &vadc->vadc_therm_chan[i], + &qpnp_vadc_thermal_ops, NULL, 0, 0); + if (IS_ERR(vadc->vadc_therm_chan[i].tz_dev)) { + pr_err("thermal device register failed.\n"); + goto thermal_err_sens; + } + } + i++; + thermal_node = false; + } + return 0; +thermal_err_sens: + pr_err("Init HWMON failed for qpnp_adc with %d\n", rc); + return rc; +} + +static const struct of_device_id qpnp_vadc_match_table[] = { + { .compatible = "qcom,qpnp-vadc", + }, + { .compatible = "qcom,qpnp-vadc-hc", + }, + {} +}; + +static int qpnp_vadc_probe(struct platform_device *pdev) +{ + struct qpnp_vadc_chip *vadc; + struct qpnp_adc_drv *adc_qpnp; + struct qpnp_vadc_thermal_data *adc_thermal; + struct device_node *node = pdev->dev.of_node; + struct device_node *child; + const struct of_device_id *id; + int rc, count_adc_channel_list = 0, i = 0; + u8 fab_id = 0; + + for_each_child_of_node(node, child) + count_adc_channel_list++; + + if (!count_adc_channel_list) { + pr_err("No channel listing\n"); + return -EINVAL; + } + + id = of_match_node(qpnp_vadc_match_table, node); + if (id == NULL) { + pr_err("qpnp_vadc_match of_node prop not present\n"); + return -ENODEV; + } + + vadc = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_vadc_chip) + + (sizeof(struct sensor_device_attribute) * + count_adc_channel_list), GFP_KERNEL); + if (!vadc) { + dev_err(&pdev->dev, "Unable to allocate memory\n"); + return -ENOMEM; + } + + vadc->dev = &(pdev->dev); + adc_qpnp = devm_kzalloc(&pdev->dev, sizeof(struct qpnp_adc_drv), + GFP_KERNEL); + if (!adc_qpnp) + return -ENOMEM; + + adc_qpnp->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!adc_qpnp->regmap) { + dev_err(&pdev->dev, "Couldn't get parent's regmap\n"); + return -EINVAL; + } + + vadc->state_copy = devm_kzalloc(&pdev->dev, + sizeof(struct qpnp_vadc_mode_state), GFP_KERNEL); + if (!vadc->state_copy) + return -ENOMEM; + + vadc->adc = adc_qpnp; + adc_thermal = devm_kzalloc(&pdev->dev, + (sizeof(struct qpnp_vadc_thermal_data) * + count_adc_channel_list), GFP_KERNEL); + if (!adc_thermal) { + dev_err(&pdev->dev, "Unable to allocate memory\n"); + return -ENOMEM; + } + + vadc->vadc_therm_chan = adc_thermal; + if (!strcmp(id->compatible, "qcom,qpnp-vadc-hc")) { + vadc->vadc_hc = true; + vadc->adc->adc_hc = true; + } + + rc = qpnp_adc_get_devicetree_data(pdev, vadc->adc); + if (rc) { + dev_err(&pdev->dev, "failed to read device tree\n"); + return rc; + } + mutex_init(&vadc->adc->adc_lock); + + rc = qpnp_vadc_init_hwmon(vadc, pdev); + if (rc) { + dev_err(&pdev->dev, "failed to initialize qpnp hwmon adc\n"); + return rc; + } + vadc->vadc_hwmon = hwmon_device_register(&vadc->adc->pdev->dev); + rc = qpnp_vadc_init_thermal(vadc, pdev); + if (rc) { + dev_err(&pdev->dev, "failed to initialize qpnp thermal adc\n"); + return rc; + } + vadc->vadc_init_calib = false; + vadc->max_channels_available = count_adc_channel_list; + rc = qpnp_vadc_read_reg(vadc, QPNP_INT_TEST_VAL, &fab_id, 1); + if (rc < 0) { + pr_err("qpnp adc comp id failed with %d\n", rc); + goto err_setup; + } + vadc->id = fab_id; + pr_debug("fab_id = %d\n", fab_id); + + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_REVISION2, + &vadc->revision_dig_major, 1); + if (rc < 0) { + pr_err("qpnp adc dig_major rev read failed with %d\n", rc); + goto err_setup; + } + + rc = qpnp_vadc_read_reg(vadc, QPNP_VADC_REVISION3, + &vadc->revision_ana_minor, 1); + if (rc < 0) { + pr_err("qpnp adc ana_minor rev read failed with %d\n", rc); + goto err_setup; + } + + rc = qpnp_vadc_warm_rst_configure(vadc); + if (rc < 0) { + pr_err("Setting perp reset on warm reset failed %d\n", rc); + goto err_setup; + } + + INIT_WORK(&vadc->trigger_completion_work, qpnp_vadc_work); + + vadc->vadc_recalib_check = of_property_read_bool(node, + "qcom,vadc-recalib-check"); + + vadc->vadc_poll_eoc = of_property_read_bool(node, + "qcom,vadc-poll-eoc"); + if (!vadc->vadc_poll_eoc) { + rc = devm_request_irq(&pdev->dev, vadc->adc->adc_irq_eoc, + qpnp_vadc_isr, IRQF_TRIGGER_RISING, + "qpnp_vadc_interrupt", vadc); + if (rc) { + dev_err(&pdev->dev, + "failed to request adc irq with error %d\n", rc); + goto err_setup; + } else { + enable_irq_wake(vadc->adc->adc_irq_eoc); + } + } else + device_init_wakeup(vadc->dev, 1); + + vadc->state_copy->vadc_meas_int_enable = of_property_read_bool(node, + "qcom,vadc-meas-int-mode"); + if (vadc->state_copy->vadc_meas_int_enable) { + vadc->adc->adc_high_thr_irq = platform_get_irq_byname(pdev, + "high-thr-en-set"); + if (vadc->adc->adc_high_thr_irq < 0) { + pr_err("Invalid irq\n"); + rc = -ENXIO; + goto err_setup; + } + + vadc->adc->adc_low_thr_irq = platform_get_irq_byname(pdev, + "low-thr-en-set"); + if (vadc->adc->adc_low_thr_irq < 0) { + pr_err("Invalid irq\n"); + rc = -ENXIO; + goto err_setup; + } + + rc = devm_request_irq(&pdev->dev, vadc->adc->adc_high_thr_irq, + qpnp_vadc_high_thr_isr, + IRQF_TRIGGER_RISING, "qpnp_vadc_high_interrupt", vadc); + if (rc) { + dev_err(&pdev->dev, "failed to request adc irq\n"); + goto err_setup; + } else { + enable_irq_wake(vadc->adc->adc_high_thr_irq); + } + + rc = devm_request_irq(&pdev->dev, vadc->adc->adc_low_thr_irq, + qpnp_vadc_low_thr_isr, + IRQF_TRIGGER_RISING, "qpnp_vadc_low_interrupt", vadc); + if (rc) { + dev_err(&pdev->dev, "failed to request adc irq\n"); + goto err_setup; + } else { + enable_irq_wake(vadc->adc->adc_low_thr_irq); + } + INIT_WORK(&vadc->trigger_high_thr_work, + qpnp_vadc_high_thr_fn); + INIT_WORK(&vadc->trigger_low_thr_work, qpnp_vadc_low_thr_fn); + } + + vadc->vadc_iadc_sync_lock = false; + dev_set_drvdata(&pdev->dev, vadc); + list_add(&vadc->list, &qpnp_vadc_device_list); + + return 0; + +err_setup: + for_each_child_of_node(node, child) { + device_remove_file(&pdev->dev, &vadc->sens_attr[i].dev_attr); + if (vadc->vadc_therm_chan[i].thermal_node) + thermal_zone_device_unregister( + vadc->vadc_therm_chan[i].tz_dev); + i++; + } + hwmon_device_unregister(vadc->vadc_hwmon); + + return rc; +} + +static int qpnp_vadc_remove(struct platform_device *pdev) +{ + struct qpnp_vadc_chip *vadc = dev_get_drvdata(&pdev->dev); + struct device_node *node = pdev->dev.of_node; + struct device_node *child; + int i = 0; + + for_each_child_of_node(node, child) { + device_remove_file(&pdev->dev, &vadc->sens_attr[i].dev_attr); + if (vadc->vadc_therm_chan[i].thermal_node) + thermal_zone_device_unregister( + vadc->vadc_therm_chan[i].tz_dev); + i++; + } + hwmon_device_unregister(vadc->vadc_hwmon); + list_del(&vadc->list); + if (vadc->adc->hkadc_ldo && vadc->adc->hkadc_ldo_ok) + qpnp_adc_free_voltage_resource(vadc->adc); + dev_set_drvdata(&pdev->dev, NULL); + + return 0; +} + +static int qpnp_vadc_suspend_noirq(struct device *dev) +{ + struct qpnp_vadc_chip *vadc = dev_get_drvdata(dev); + u8 status = 0; + + qpnp_vadc_read_reg(vadc, QPNP_VADC_STATUS1, &status, 1); + if (((status & QPNP_VADC_STATUS1_OP_MODE_MASK) >> + QPNP_VADC_OP_MODE_SHIFT) == QPNP_VADC_MEAS_INT_MODE) { + pr_debug("Meas interval in progress\n"); + } else if (vadc->vadc_poll_eoc) { + status &= QPNP_VADC_STATUS1_REQ_STS_EOC_MASK; + pr_debug("vadc conversion status=%d\n", status); + if (status != QPNP_VADC_STATUS1_EOC) { + pr_err( + "Aborting suspend, adc conversion requested while suspending\n"); + return -EBUSY; + } + } + + return 0; +} + +static const struct dev_pm_ops qpnp_vadc_pm_ops = { + .suspend_noirq = qpnp_vadc_suspend_noirq, +}; + +static struct platform_driver qpnp_vadc_driver = { + .driver = { + .name = "qcom,qpnp-vadc", + .of_match_table = qpnp_vadc_match_table, + .pm = &qpnp_vadc_pm_ops, + }, + .probe = qpnp_vadc_probe, + .remove = qpnp_vadc_remove, +}; + +static int __init qpnp_vadc_init(void) +{ + return platform_driver_register(&qpnp_vadc_driver); +} +module_init(qpnp_vadc_init); + +static void __exit qpnp_vadc_exit(void) +{ + platform_driver_unregister(&qpnp_vadc_driver); +} +module_exit(qpnp_vadc_exit); + +MODULE_DESCRIPTION("QPNP PMIC Voltage ADC driver"); +MODULE_LICENSE("GPL v2"); |