4 files changed, 110 insertions, 6 deletions

diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
index 76310e249fb2..0987c8e7f807 100644
--- a/drivers/clk/qcom/clk-branch.c
+++ b/drivers/clk/qcom/clk-branch.c
@@ -125,15 +125,62 @@ static int clk_branch_enable(struct clk_hw *hw)
 	return clk_branch_toggle(hw, true, clk_branch_check_halt);
 }
 
+static int clk_cbcr_set_flags(struct regmap *regmap, unsigned int reg,
+				unsigned long flags)
+{
+	u32 cbcr_val;
+
+	regmap_read(regmap, reg, &cbcr_val);
+
+	switch (flags) {
+	case CLKFLAG_PERIPH_OFF_SET:
+		cbcr_val |= BIT(12);
+		break;
+	case CLKFLAG_PERIPH_OFF_CLEAR:
+		cbcr_val &= ~BIT(12);
+		break;
+	case CLKFLAG_RETAIN_PERIPH:
+		cbcr_val |= BIT(13);
+		break;
+	case CLKFLAG_NORETAIN_PERIPH:
+		cbcr_val &= ~BIT(13);
+		break;
+	case CLKFLAG_RETAIN_MEM:
+		cbcr_val |= BIT(14);
+		break;
+	case CLKFLAG_NORETAIN_MEM:
+		cbcr_val &= ~BIT(14);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	regmap_write(regmap, reg, cbcr_val);
+
+	/* Make sure power is enabled/disabled before returning. */
+	mb();
+	udelay(1);
+
+	return 0;
+}
+
 static void clk_branch_disable(struct clk_hw *hw)
 {
 	clk_branch_toggle(hw, false, clk_branch_check_halt);
 }
 
+static int clk_branch_set_flags(struct clk_hw *hw, unsigned flags)
+{
+	struct clk_branch *br = to_clk_branch(hw);
+
+	return clk_cbcr_set_flags(br->clkr.regmap, br->halt_reg, flags);
+}
+
 const struct clk_ops clk_branch_ops = {
 	.enable = clk_branch_enable,
 	.disable = clk_branch_disable,
 	.is_enabled = clk_is_enabled_regmap,
+	.set_flags = clk_branch_set_flags,
 };
 EXPORT_SYMBOL_GPL(clk_branch_ops);
 
@@ -151,6 +198,7 @@ const struct clk_ops clk_branch2_ops = {
 	.enable = clk_branch2_enable,
 	.disable = clk_branch2_disable,
 	.is_enabled = clk_is_enabled_regmap,
+	.set_flags = clk_branch_set_flags,
 };
 EXPORT_SYMBOL_GPL(clk_branch2_ops);
 
diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h
index 915c54f9351f..331f58d651e5 100644
--- a/drivers/clk/qcom/clk-branch.h
+++ b/drivers/clk/qcom/clk-branch.h
@@ -73,4 +73,13 @@ extern const struct clk_ops clk_branch_simple_ops;
 #define to_clk_gate2(_hw) \
 	container_of(to_clk_regmap(_hw), struct clk_gate2, clkr)
 
+enum branch_mem_flags {
+	CLKFLAG_RETAIN_PERIPH,
+	CLKFLAG_NORETAIN_PERIPH,
+	CLKFLAG_RETAIN_MEM,
+	CLKFLAG_NORETAIN_MEM,
+	CLKFLAG_PERIPH_OFF_SET,
+	CLKFLAG_PERIPH_OFF_CLEAR,
+};
+
 #endif
diff --git a/drivers/clk/qcom/clk-dummy.c b/drivers/clk/qcom/clk-dummy.c
index 3205fbc6b8ba..e06a829e508c 100644
--- a/drivers/clk/qcom/clk-dummy.c
+++ b/drivers/clk/qcom/clk-dummy.c
@@ -15,14 +15,18 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/reset-controller.h>
 
 struct clk_dummy {
 	struct clk_hw hw;
+	struct reset_controller_dev reset;
 	unsigned long rrate;
 };
 
 #define to_clk_dummy(_hw)	container_of(_hw, struct clk_dummy, hw)
 
+#define RESET_MAX	100
+
 static int dummy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 					unsigned long parent_rate)
 {
@@ -51,22 +55,48 @@ static unsigned long dummy_clk_recalc_rate(struct clk_hw *hw,
 	return dummy->rrate;
 }
 
+static int dummy_clk_set_flags(struct clk_hw *hw, unsigned flags)
+{
+	return 0;
+}
+
 struct clk_ops clk_dummy_ops = {
 	.set_rate = dummy_clk_set_rate,
 	.round_rate = dummy_clk_round_rate,
 	.recalc_rate = dummy_clk_recalc_rate,
+	.set_flags = dummy_clk_set_flags,
 };
 EXPORT_SYMBOL_GPL(clk_dummy_ops);
 
+static int dummy_reset_assert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	pr_debug("%s\n", __func__);
+	return 0;
+}
+
+static int dummy_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	pr_debug("%s\n", __func__);
+	return 0;
+}
+
+static struct reset_control_ops dummy_reset_ops = {
+	.assert         = dummy_reset_assert,
+	.deassert       = dummy_reset_deassert,
+};
+
 /**
  * clk_register_dummy - register dummy clock with the
  *				   clock framework
  * @dev: device that is registering this clock
  * @name: name of this clock
  * @flags: framework-specific flags
+ * @node: device node
  */
 static struct clk *clk_register_dummy(struct device *dev, const char *name,
-		unsigned long flags)
+		unsigned long flags, struct device_node *node)
 {
 	struct clk_dummy *dummy;
 	struct clk *clk;
@@ -85,8 +115,20 @@ static struct clk *clk_register_dummy(struct device *dev, const char *name,
 
 	/* register the clock */
 	clk = clk_register(dev, &dummy->hw);
-	if (IS_ERR(clk))
+	if (IS_ERR(clk)) {
 		kfree(dummy);
+		return clk;
+	}
+
+	dummy->reset.of_node = node;
+	dummy->reset.ops = &dummy_reset_ops;
+	dummy->reset.nr_resets = RESET_MAX;
+
+	if (reset_controller_register(&dummy->reset))
+		pr_err("Failed to register reset controller for %s\n", name);
+	else
+		pr_info("Successfully registered a dummy reset controller for %s\n",
+								name);
 
 	return clk;
 }
@@ -101,10 +143,15 @@ static void of_dummy_clk_setup(struct device_node *node)
 
 	of_property_read_string(node, "clock-output-names", &clk_name);
 
-	clk = clk_register_dummy(NULL, clk_name, 0);
+	clk = clk_register_dummy(NULL, clk_name, 0, node);
 	if (!IS_ERR(clk))
 		of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	else {
+		pr_err("Failed to register dummy clock controller for %s\n",
+								clk_name);
+		return;
+	}
 
-	pr_info("%s: Dummy clock registered\n", clk_name);
+	pr_info("Successfully registered dummy clock for %s\n", clk_name);
 }
 CLK_OF_DECLARE(dummy_clk, "qcom,dummycc", of_dummy_clk_setup);
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index 8b9c388bc43c..6c899fb5b856 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -2722,7 +2722,7 @@ static struct clk_rcg ce3_src = {
 	},
 	.freq_tbl = clk_tbl_ce3,
 	.clkr = {
-		.enable_reg = 0x36c0,
+		.enable_reg = 0x2c08,
 		.enable_mask = BIT(7),
 		.hw.init = &(struct clk_init_data){
 			.name = "ce3_src",
@@ -2738,7 +2738,7 @@ static struct clk_branch ce3_core_clk = {
 	.halt_reg = 0x2fdc,
 	.halt_bit = 5,
 	.clkr = {
-		.enable_reg = 0x36cc,
+		.enable_reg = 0x36c4,
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "ce3_core_clk",