diff options
Diffstat (limited to 'arch')
55 files changed, 2655 insertions, 622 deletions
diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 7ab87629378a..7810842100cd 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -128,7 +128,8 @@ dtb-$(CONFIG_ARCH_MSMCOBALT) += msmcobalt-sim.dtb \ apqcobalt-v2.1-cdp.dtb \ apqcobalt-v2.1-qrd.dtb \ msmcobalt-v2.1-interposer-msmfalcon-cdp.dtb \ - msmcobalt-v2.1-interposer-msmfalcon-mtp.dtb + msmcobalt-v2.1-interposer-msmfalcon-mtp.dtb \ + msmcobalt-v2.1-interposer-msmfalcon-qrd.dtb dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb diff --git a/arch/arm/boot/dts/qcom/apq8096-auto-dragonboard.dtsi b/arch/arm/boot/dts/qcom/apq8096-auto-dragonboard.dtsi index 9083c89802f3..70156b1f8493 100644 --- a/arch/arm/boot/dts/qcom/apq8096-auto-dragonboard.dtsi +++ b/arch/arm/boot/dts/qcom/apq8096-auto-dragonboard.dtsi @@ -361,7 +361,7 @@ &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &ibb_regulator { diff --git a/arch/arm/boot/dts/qcom/apq8096-dragonboard.dtsi b/arch/arm/boot/dts/qcom/apq8096-dragonboard.dtsi index a2085945ac33..a7482bcce112 100644 --- a/arch/arm/boot/dts/qcom/apq8096-dragonboard.dtsi +++ b/arch/arm/boot/dts/qcom/apq8096-dragonboard.dtsi @@ -361,7 +361,7 @@ &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &rpm_bus { diff --git a/arch/arm/boot/dts/qcom/apq8096-sbc.dtsi b/arch/arm/boot/dts/qcom/apq8096-sbc.dtsi index 4e7379d9e164..0ee28c2c427e 100644 --- a/arch/arm/boot/dts/qcom/apq8096-sbc.dtsi +++ b/arch/arm/boot/dts/qcom/apq8096-sbc.dtsi @@ -364,7 +364,7 @@ &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &ibb_regulator { diff --git a/arch/arm/boot/dts/qcom/batterydata-qrd-skuk-4v4-3000mah.dtsi b/arch/arm/boot/dts/qcom/batterydata-qrd-skuk-4v4-3000mah.dtsi index 76126c21c43a..8bf98d83d381 100644 --- a/arch/arm/boot/dts/qcom/batterydata-qrd-skuk-4v4-3000mah.dtsi +++ b/arch/arm/boot/dts/qcom/batterydata-qrd-skuk-4v4-3000mah.dtsi @@ -18,44 +18,44 @@ qcom,qrd_msmcobalt_skuk_3000mah { qcom,battery-type = "qrd_msmcobalt_skuk_300mah"; qcom,checksum = <0x0F19>; qcom,fg-profile-data = [ - 05 B2 1F 6F - FC A3 0A 6E - FD DB 1D 8C - 1D AE 12 C2 - 23 00 18 7E - 52 B4 45 8D - 00 00 00 55 - 00 00 00 0F - C5 92 00 00 - CA A0 CD 95 - 00 0C 00 1F - EC C3 F2 56 - F3 27 06 7B - 12 FF 01 02 - 3A 21 DA 1C - 40 40 09 1C - 00 05 00 07 - 05 B4 1F AC - FC EF 0A 57 - 00 2E 1D 6A - 14 BA 0B 12 - 22 DC 19 40 - 53 03 45 79 - 00 00 00 53 - 00 00 00 0E - CC 05 00 00 - CA 24 BB 3A - 00 00 00 1C - EC C3 F2 56 - F2 A2 06 A6 - 01 C7 06 96 - 1A CF EA 8B - 33 08 33 BA - 00 00 10 07 - 46 66 0C 3A - 00 19 00 1C - FA 0A 01 98 - 00 00 00 FF + 6F 1F B2 05 + 6E 0A A3 FC + 8C 1D DB FD + C2 12 AE 1D + 7E 18 00 23 + 8D 45 B4 52 + 55 00 00 00 + 0F 00 00 00 + 00 00 92 C5 + 95 CD A0 CA + 1F 00 0C 00 + 56 F2 C3 EC + 7B 06 27 F3 + 02 01 FF 12 + 1C DA 21 3A + 1C 09 40 40 + 07 00 05 00 + AC 1F B4 05 + 57 0A EF FC + 6A 1D 2E 00 + 12 0B BA 14 + 40 19 DC 22 + 79 45 03 53 + 53 00 00 00 + 0E 00 00 00 + 00 00 05 CC + 3A BB 24 CA + 1C 00 00 00 + 56 F2 C3 EC + A6 06 A2 F2 + 96 06 C7 01 + 8B EA CF 1A + BA 33 08 33 + 07 10 00 00 + 3A 0C 66 46 + 1C 00 19 00 + 98 01 0A FA + FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/arch/arm/boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi new file mode 100644 index 000000000000..f500079e6953 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi @@ -0,0 +1,238 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpb1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpb2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpb3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpb5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpb"; + qcom,resource-id = <5>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldob"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwsc"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldob10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "rwsm"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-bobb { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "bobb"; + qcom,resource-id = <1>; + qcom,regulator-type = <4>; + status = "disabled"; + + regulator-bob { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_bob"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi index 41589d02f6fc..0e5a999e4642 100644 --- a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi @@ -357,10 +357,6 @@ qcom,led-name = "led:switch_0"; qcom,led-mask = <3>; qcom,default-led-trigger = "switch0_trigger"; - reg0 { - regulator-name = "pmfalcon_bob"; - max-voltage-uv = <3600000>; - }; }; pm2falcon_switch1: qcom,led_switch_1 { @@ -368,10 +364,6 @@ qcom,led-name = "led:switch_1"; qcom,led-mask = <4>; qcom,default-led-trigger = "switch1_trigger"; - reg0 { - regulator-name = "pmfalcon_bob"; - max-voltage-uv = <3600000>; - }; }; }; }; diff --git a/arch/arm/boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi new file mode 100644 index 000000000000..0b625bf04ef5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi @@ -0,0 +1,298 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&rpm_bus { + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <5>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_s5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <6>; + qcom,regulator-type = <1>; + status = "disabled"; + + regulator-s6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_s6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pmfalcon_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi b/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi index bba70329c819..c46c0963ff56 100644 --- a/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi @@ -497,7 +497,7 @@ qcom,qpnp-lab-pull-down-enable; qcom,qpnp-lab-switching-clock-frequency = <1600>; - qcom,qpnp-lab-limit-maximum-current = <800>; + qcom,qpnp-lab-limit-maximum-current = <1600>; qcom,qpnp-lab-limit-max-current-enable; qcom,qpnp-lab-ps-threshold = <20>; qcom,qpnp-lab-ps-enable; diff --git a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi b/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi index a5243aff4282..640aa53364a5 100644 --- a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi @@ -321,7 +321,7 @@ qcom,pmic-revid = <&pmicobalt_revid>; io-channels = <&pmicobalt_rradc 0>; io-channel-names = "rradc_batt_id"; - qcom,fg-esr-timer-awake = <64>; + qcom,fg-esr-timer-awake = <96>; qcom,fg-esr-timer-asleep = <256>; qcom,cycle-counter-en; status = "okay"; @@ -334,7 +334,8 @@ <0x2 0x40 0x2 IRQ_TYPE_EDGE_BOTH>, <0x2 0x40 0x3 IRQ_TYPE_EDGE_BOTH>, <0x2 0x40 0x4 IRQ_TYPE_EDGE_BOTH>, - <0x2 0x40 0x5 IRQ_TYPE_EDGE_BOTH>, + <0x2 0x40 0x5 + IRQ_TYPE_EDGE_RISING>, <0x2 0x40 0x6 IRQ_TYPE_EDGE_BOTH>, <0x2 0x40 0x7 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "soc-update", @@ -554,6 +555,9 @@ regulator-min-microvolt = <4600000>; regulator-max-microvolt = <6000000>; + interrupts = <0x3 0xde 0x0 + IRQ_TYPE_EDGE_RISING>; + interrupt-names = "lab-vreg-ok"; qcom,qpnp-lab-min-voltage = <4600000>; qcom,qpnp-lab-step-size = <100000>; qcom,qpnp-lab-slew-rate = <5000>; @@ -568,13 +572,13 @@ qcom,qpnp-lab-pull-down-enable; qcom,qpnp-lab-switching-clock-frequency = <1600>; - qcom,qpnp-lab-limit-maximum-current = <800>; + qcom,qpnp-lab-limit-maximum-current = <1600>; qcom,qpnp-lab-limit-max-current-enable; qcom,qpnp-lab-ps-threshold = <20>; qcom,qpnp-lab-ps-enable; qcom,qpnp-lab-nfet-size = <100>; qcom,qpnp-lab-pfet-size = <100>; - qcom,qpnp-lab-max-precharge-time = <300>; + qcom,qpnp-lab-max-precharge-time = <500>; }; }; @@ -740,10 +744,6 @@ qcom,led-name = "led:switch_0"; qcom,led-mask = <3>; qcom,default-led-trigger = "switch0_trigger"; - reg0 { - regulator-name = "pmicobalt_bob"; - max-voltage-uv = <3600000>; - }; }; pmicobalt_switch1: qcom,led_switch_1 { @@ -751,10 +751,6 @@ qcom,led-name = "led:switch_1"; qcom,led-mask = <4>; qcom,default-led-trigger = "switch1_trigger"; - reg0 { - regulator-name = "pmicobalt_bob"; - max-voltage-uv = <3600000>; - }; }; }; }; diff --git a/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi b/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi index 40df8b7ff4de..48cf099b84a8 100644 --- a/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi @@ -388,7 +388,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,cont-splash-enabled; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 128 720 64 720 64>; }; @@ -432,7 +432,7 @@ qcom,5v-boost-gpio = <&pmi8994_gpios 8 0>; qcom,cont-splash-enabled; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <4 4 2 2 20 20>; }; diff --git a/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi index 30646dba1cd9..34e41c2bf28f 100644 --- a/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi @@ -376,7 +376,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,cont-splash-enabled; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 128 720 64 720 64>; }; diff --git a/arch/arm/boot/dts/qcom/msm8996-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8996-cdp.dtsi index 4855da387e21..165c7de039e5 100644 --- a/arch/arm/boot/dts/qcom/msm8996-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-cdp.dtsi @@ -387,7 +387,7 @@ &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &dsi_dual_sharp_video { @@ -409,7 +409,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 128 720 64 720 64>; }; @@ -432,7 +432,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; /* panel supports slice height of 8/16/32/48/3840 */ qcom,panel-roi-alignment = <1080 8 1080 8 1080 8>; }; @@ -480,7 +480,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,5v-boost-gpio = <&pmi8994_gpios 8 0>; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <4 2 4 2 20 20>; }; diff --git a/arch/arm/boot/dts/qcom/msm8996-dtp.dtsi b/arch/arm/boot/dts/qcom/msm8996-dtp.dtsi index 19d052791c9a..5c62766b1a26 100644 --- a/arch/arm/boot/dts/qcom/msm8996-dtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-dtp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -452,7 +452,7 @@ &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &mdss_mdp { diff --git a/arch/arm/boot/dts/qcom/msm8996-fluid.dtsi b/arch/arm/boot/dts/qcom/msm8996-fluid.dtsi index 824d31afb7d8..baecf4b8574e 100644 --- a/arch/arm/boot/dts/qcom/msm8996-fluid.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-fluid.dtsi @@ -629,14 +629,14 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; /* panel supports slice height of 8/16/32/48/3840 */ qcom,panel-roi-alignment = <1080 8 1080 8 1080 8>; }; &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &pmi8994_mpps { diff --git a/arch/arm/boot/dts/qcom/msm8996-gpu.dtsi b/arch/arm/boot/dts/qcom/msm8996-gpu.dtsi index 07423a601b35..215608959dc5 100644 --- a/arch/arm/boot/dts/qcom/msm8996-gpu.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-gpu.dtsi @@ -129,6 +129,40 @@ vddcx-supply = <&gdsc_gpu>; vdd-supply = <&gdsc_gpu_gx>; + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells= <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + /* Power levels */ qcom,gpu-pwrlevels { #address-cells = <1>; diff --git a/arch/arm/boot/dts/qcom/msm8996-liquid.dtsi b/arch/arm/boot/dts/qcom/msm8996-liquid.dtsi index 33397e3e4762..dae7306cdd07 100644 --- a/arch/arm/boot/dts/qcom/msm8996-liquid.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-liquid.dtsi @@ -319,7 +319,7 @@ &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &dsi_dual_jdi_4k_nofbc_video { diff --git a/arch/arm/boot/dts/qcom/msm8996-mmxf-adp.dtsi b/arch/arm/boot/dts/qcom/msm8996-mmxf-adp.dtsi index 3d534ff1550e..bd8aa7fe02f7 100644 --- a/arch/arm/boot/dts/qcom/msm8996-mmxf-adp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-mmxf-adp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -343,7 +343,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,cont-splash-enabled; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 128 720 64 720 64>; }; @@ -387,7 +387,7 @@ qcom,5v-boost-gpio = <&pmi8994_gpios 8 0>; qcom,cont-splash-enabled; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <4 4 2 2 20 20>; }; diff --git a/arch/arm/boot/dts/qcom/msm8996-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8996-mtp.dtsi index 96279288d336..27d3eea5bc20 100644 --- a/arch/arm/boot/dts/qcom/msm8996-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-mtp.dtsi @@ -368,7 +368,7 @@ &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &dsi_dual_sharp_video { @@ -397,7 +397,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 128 720 64 720 64>; }; @@ -420,7 +420,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; /* panel supports slice height of 8/16/32/48/3840 */ qcom,panel-roi-alignment = <1080 8 1080 8 1080 8>; }; @@ -468,7 +468,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,5v-boost-gpio = <&pmi8994_gpios 8 0>; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <4 4 2 2 20 20>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-qrd-vr1.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-qrd-vr1.dtsi new file mode 100644 index 000000000000..0fb1a0425dd5 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-qrd-vr1.dtsi @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash0: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pmicobalt_flash0 &pmicobalt_flash1>; + qcom,switch-source = <&pmicobalt_switch0>; + status = "ok"; + }; + + led_flash1: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pmicobalt_flash2>; + qcom,switch-source = <&pmicobalt_switch1>; + status = "ok"; + }; +}; + +&tlmm{ + cam_sensor_front_active: cam_sensor_front_active { + /* RESET */ + mux { + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_suspend: cam_sensor_front_suspend { + /* RESET */ + mux { + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_active: cam_sensor_rear2_active { + /* RESET, STANDBY */ + mux { + pins = "gpio27","gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio27","gpio8"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio27","gpio8"; + function = "gpio"; + }; + config { + pins = "gpio27","gpio8"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; + + +&cci { + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pmcobalt_lvs1>; + cam_vana-supply = <&pmicobalt_bob>; + cam_vdig-supply = <&pmcobalt_s3>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <0 3312000 1352000>; + qcom,cam-vreg-max-voltage = <0 3600000 1352000>; + qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>, + <&pmcobalt_gpios 20 0>, + <&tlmm 29 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss clk_mclk0_clk_src>, + <&clock_mmss clk_mmss_camss_mclk0_clk>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pmcobalt_lvs1>; + cam_vio-supply = <&pmcobalt_lvs1>; + cam_vana-supply = <&pmicobalt_bob>; + qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; + qcom,cam-vreg-min-voltage = <0 0 3312000>; + qcom,cam-vreg-max-voltage = <0 0 3600000>; + qcom,cam-vreg-op-mode = <0 0 80000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 27 0>, + <&tlmm 8 0>; + qcom,gpio-standby = <1>; + qcom,gpio-vana = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_STANDBY1", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss clk_mclk1_clk_src>, + <&clock_mmss clk_mmss_camss_mclk1_clk>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom2: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pmcobalt_lvs1>; + cam_vana-supply = <&pmcobalt_l22>; + cam_vdig-supply = <&pmcobalt_s3>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <0 2864000 1352000>; + qcom,cam-vreg-max-voltage = <0 2864000 1352000>; + qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_active + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 9 0>, + <&pmcobalt_gpios 9 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss clk_mclk2_clk_src>, + <&clock_mmss clk_mmss_camss_mclk2_clk>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <270>; + qcom,led-flash-src = <&led_flash0>; + qcom,actuator-src = <&actuator0>; + qcom,eeprom-src = <&eeprom0>; + cam_vio-supply = <&pmcobalt_lvs1>; + cam_vana-supply = <&pmicobalt_bob>; + cam_vdig-supply = <&pmcobalt_s3>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <0 3312000 1352000>; + qcom,cam-vreg-max-voltage = <0 3600000 1352000>; + qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>, + <&pmcobalt_gpios 20 0>, + <&tlmm 29 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss clk_mclk0_clk_src>, + <&clock_mmss clk_mmss_camss_mclk0_clk>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <90>; + qcom,eeprom-src = <&eeprom1>; + cam_vio-supply = <&pmcobalt_lvs1>; + cam_vana-supply = <&pmicobalt_bob>; + qcom,cam-vreg-name = "cam_vio", "cam_vana"; + qcom,cam-vreg-min-voltage = <0 3312000>; + qcom,cam-vreg-max-voltage = <0 3600000>; + qcom,cam-vreg-op-mode = <0 80000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 27 0>, + <&tlmm 8 0>; + qcom,gpio-standby = <1>; + qcom,gpio-vana = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_STANDBY1", + "CAM_VANA1"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss clk_mclk1_clk_src>, + <&clock_mmss clk_mmss_camss_mclk1_clk>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,eeprom-src = <&eeprom2>; + qcom,led-flash-src = <&led_flash1>; + qcom,actuator-src = <&actuator1>; + cam_vio-supply = <&pmcobalt_lvs1>; + cam_vana-supply = <&pmcobalt_l22>; + cam_vdig-supply = <&pmcobalt_s3>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <0 2864000 1352000>; + qcom,cam-vreg-max-voltage = <0 2864000 1352000>; + qcom,cam-vreg-op-mode = <0 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 9 0>, + <&pmcobalt_gpios 9 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss clk_mclk2_clk_src>, + <&clock_mmss clk_mmss_camss_mclk2_clk>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; + +&pmcobalt_gpios { + gpio@c800 { /* GPIO 9 - CAMERA SENSOR 2 VDIG */ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; + + gpio@d300 { /* GPIO 20 - CAMERA SENSOR 0 VDIG */ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <1>; /* VIN1 GPIO_MV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi index 4822823aa63f..ca504a798659 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi @@ -17,11 +17,11 @@ compatible = "qca,wcn3990"; qca,bt-vdd-io-supply = <&pmcobalt_s3>; qca,bt-vdd-xtal-supply = <&pmcobalt_s5>; - qca,bt-vdd-core-supply = <&pmcobalt_l7_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmcobalt_l17_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmcobalt_l25_pin_ctrl>; + qca,bt-vdd-core-supply = <&pmcobalt_l7>; + qca,bt-vdd-pa-supply = <&pmcobalt_l17>; + qca,bt-vdd-ldo-supply = <&pmcobalt_l25>; qca,bt-chip-pwd-supply = <&pmicobalt_bob_pin1>; - clocks = <&clock_gcc clk_rf_clk2>; + clocks = <&clock_gcc clk_rf_clk2_pin>; clock-names = "rf_clk2"; qca,bt-vdd-io-voltage-level = <1352000 1352000>; @@ -299,7 +299,7 @@ &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &pmicobalt_wled { @@ -382,7 +382,7 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,5v-boost-gpio = <&tlmm 51 0>; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,partial-update-enabled; + qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <4 2 4 2 20 20>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi index e140074465ef..8739e8f22549 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi @@ -77,6 +77,9 @@ qcom,tsens-name = "tsens_tz_sensor12"; + /* Quirks */ + qcom,gpu-quirk-lmloadkill-disable; + clocks = <&clock_gfx clk_gpucc_gfx3d_clk>, <&clock_gcc clk_gcc_gpu_cfg_ahb_clk>, <&clock_gpu clk_gpucc_rbbmtimer_clk>, @@ -119,6 +122,40 @@ vddcx-supply = <&gdsc_gpu_cx>; vdd-supply = <&gdsc_gpu_gx>; + /* GPU Mempools */ + qcom,gpu-mempools { + #address-cells= <1>; + #size-cells = <0>; + compatible = "qcom,gpu-mempools"; + + /* 4K Page Pool configuration */ + qcom,gpu-mempool@0 { + reg = <0>; + qcom,mempool-page-size = <4096>; + qcom,mempool-reserved = <2048>; + qcom,mempool-allocate; + }; + /* 8K Page Pool configuration */ + qcom,gpu-mempool@1 { + reg = <1>; + qcom,mempool-page-size = <8192>; + qcom,mempool-reserved = <1024>; + qcom,mempool-allocate; + }; + /* 64K Page Pool configuration */ + qcom,gpu-mempool@2 { + reg = <2>; + qcom,mempool-page-size = <65536>; + qcom,mempool-reserved = <256>; + }; + /* 1M Page Pool configuration */ + qcom,gpu-mempool@3 { + reg = <3>; + qcom,mempool-page-size = <1048576>; + qcom,mempool-reserved = <32>; + }; + }; + /* Power levels */ qcom,gpu-pwrlevels { #address-cells = <1>; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon.dtsi index 32f616e1dc7a..ffb42576ffd3 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon.dtsi @@ -3088,3 +3088,48 @@ #include "msmcobalt-mdss-pll.dtsi" #include "msmcobalt-blsp.dtsi" #include "msmcobalt-audio.dtsi" + + +/* GPU overrides */ +&msm_gpu { + qcom,initial-pwrlevel = <0>; + + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <332000000>; + qcom,bus-freq = <7>; + qcom,bus-min = <6>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <251000000>; + qcom,bus-freq = <4>; + qcom,bus-min = <3>; + qcom,bus-max = <5>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <171000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <4>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; + +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi index 9c72ebf4a0bd..75c985189842 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi @@ -468,9 +468,10 @@ reg = <0xc990000 0xa84>, <0xc011000 0x910>, <0x1fcb200 0x050>, + <0xc8c2200 0x1a0>, <0x780000 0x621c>, <0xc9e1000 0x02c>; - reg-names = "dp_ctrl", "dp_phy", "tcsr_regs", + reg-names = "dp_ctrl", "dp_phy", "tcsr_regs", "dp_mmss_cc", "qfprom_physical","hdcp_physical"; clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>, diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi index 81f53f1512fd..0cd6d0ab1f1d 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi @@ -18,11 +18,11 @@ compatible = "qca,wcn3990"; qca,bt-vdd-io-supply = <&pmcobalt_s3>; qca,bt-vdd-xtal-supply = <&pmcobalt_s5>; - qca,bt-vdd-core-supply = <&pmcobalt_l7_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmcobalt_l17_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmcobalt_l25_pin_ctrl>; + qca,bt-vdd-core-supply = <&pmcobalt_l7>; + qca,bt-vdd-pa-supply = <&pmcobalt_l17>; + qca,bt-vdd-ldo-supply = <&pmcobalt_l25>; qca,bt-chip-pwd-supply = <&pmicobalt_bob_pin1>; - clocks = <&clock_gcc clk_rf_clk2>; + clocks = <&clock_gcc clk_rf_clk2_pin>; clock-names = "rf_clk2"; qca,bt-vdd-io-voltage-level = <1352000 1352000>; @@ -269,7 +269,7 @@ batt_i@3 { reg = <3>; qcom,channel = <3>; - qcom,scale = <20000000>; + qcom,scale = <(-20000000)>; }; batt_v@4 { @@ -362,7 +362,7 @@ &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &pmicobalt_wled { @@ -469,6 +469,10 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; }; +&mem_client_3_size { + qcom,peripheral-size = <0x500000>; +}; + &pmicobalt_haptics { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dts b/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dts index b5a94de9aab7..88a5e945436c 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dts +++ b/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dts @@ -15,7 +15,6 @@ #include "msmcobalt.dtsi" #include "msmcobalt-qrd-skuk.dtsi" -#include "msmcobalt-camera-sensor-skuk.dtsi" / { model = "Qualcomm Technologies, Inc. MSM COBALT SKUK"; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi index 58471f6d0fd1..15756d13d2e0 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include "msmcobalt-pinctrl.dtsi" #include "msmcobalt-audio.dtsi" +#include "msmcobalt-camera-sensor-skuk.dtsi" &blsp1_uart3_hs { status = "ok"; @@ -184,7 +185,7 @@ &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &dsi_dual_jdi_a407_cmd { @@ -193,3 +194,19 @@ qcom,mdss-dsi-bl-max-level = <4095>; qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; }; + +/{ + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + + #include "batterydata-qrd-skuk-4v4-3000mah.dtsi" + }; +}; + +&pmicobalt_fg { + qcom,battery-data = <&qrd_batterydata>; +}; + +&pmicobalt_haptics { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd-vr1.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-qrd-vr1.dtsi index f0607ac3a34a..71fd5cc1383f 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd-vr1.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-qrd-vr1.dtsi @@ -12,6 +12,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include "msmcobalt-pinctrl.dtsi" +#include "msmcobalt-camera-sensor-qrd-vr1.dtsi" &blsp1_uart3_hs { status = "ok"; @@ -127,3 +128,19 @@ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft"; }; }; + +/{ + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + + #include "batterydata-qrd-skuk-4v4-3000mah.dtsi" + }; +}; + +&pmicobalt_fg { + qcom,battery-data = <&qrd_batterydata>; +}; + +&pmicobalt_haptics { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-qrd.dtsi index 682ea8a260ef..6483453ec5fa 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-qrd.dtsi @@ -260,7 +260,7 @@ &labibb { status = "ok"; - qpnp,qpnp-labibb-mode = "lcd"; + qcom,qpnp-labibb-mode = "lcd"; }; &pmicobalt_wled { diff --git a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi index bb72cf3a0d2c..32cf1663cf43 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi @@ -590,8 +590,9 @@ qcom,cpr-idle-cycles = <15>; qcom,cpr-up-down-delay-time = <3000>; qcom,cpr-step-quot-init-min = <11>; - qcom,cpr-step-quot-init-max = <13>; + qcom,cpr-step-quot-init-max = <12>; qcom,cpr-count-mode = <0>; /* All at once */ + qcom,cpr-count-repeat = <1>; qcom,cpr-down-error-step-limit = <1>; qcom,cpr-up-error-step-limit = <1>; qcom,cpr-corner-switch-delay-time = <209>; @@ -618,7 +619,7 @@ thread@0 { qcom,cpr-thread-id = <0>; qcom,cpr-consecutive-up = <0>; - qcom,cpr-consecutive-down = <0>; + qcom,cpr-consecutive-down = <2>; qcom,cpr-up-threshold = <2>; qcom,cpr-down-threshold = <2>; @@ -740,7 +741,7 @@ qcom,cpr-aging-max-voltage-adjustment = <15000>; qcom,cpr-aging-ref-corner = <22>; - qcom,cpr-aging-ro-scaling-factor = <2950>; + qcom,cpr-aging-ro-scaling-factor = <1620>; qcom,allow-aging-voltage-adjustment = <0>; qcom,allow-aging-open-loop-voltage-adjustment = <1>; @@ -761,9 +762,10 @@ qcom,cpr-loop-time = <5000000>; qcom,cpr-idle-cycles = <15>; qcom,cpr-up-down-delay-time = <3000>; - qcom,cpr-step-quot-init-min = <11>; - qcom,cpr-step-quot-init-max = <13>; + qcom,cpr-step-quot-init-min = <9>; + qcom,cpr-step-quot-init-max = <14>; qcom,cpr-count-mode = <0>; /* All at once */ + qcom,cpr-count-repeat = <1>; qcom,cpr-down-error-step-limit = <1>; qcom,cpr-up-error-step-limit = <1>; qcom,cpr-corner-switch-delay-time = <209>; @@ -790,7 +792,7 @@ thread@0 { qcom,cpr-thread-id = <0>; qcom,cpr-consecutive-up = <0>; - qcom,cpr-consecutive-down = <0>; + qcom,cpr-consecutive-down = <2>; qcom,cpr-up-threshold = <2>; qcom,cpr-down-threshold = <2>; @@ -932,7 +934,7 @@ qcom,cpr-aging-max-voltage-adjustment = <15000>; qcom,cpr-aging-ref-corner = <25>; - qcom,cpr-aging-ro-scaling-factor = <2950>; + qcom,cpr-aging-ro-scaling-factor = <1700>; qcom,allow-aging-voltage-adjustment = <0>; qcom,allow-aging-open-loop-voltage-adjustment = <1>; @@ -959,6 +961,7 @@ qcom,cpr-step-quot-init-min = <8>; qcom,cpr-step-quot-init-max = <12>; qcom,cpr-count-mode = <0>; /* All-at-once min */ + qcom,cpr-count-repeat = <1>; vdd-supply = <&pm8005_s1>; qcom,voltage-step = <4000>; @@ -1098,6 +1101,8 @@ qcom,cpr-aging-ref-corner = <6>; qcom,cpr-aging-ro-scaling-factor = <2950>; qcom,allow-aging-voltage-adjustment = <0>; + qcom,allow-aging-open-loop-voltage-adjustment = + <1>; }; }; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2-interposer-msmfalcon.dtsi index 02cc86212301..46ed1f219970 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2-interposer-msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-v2-interposer-msmfalcon.dtsi @@ -750,7 +750,7 @@ &msm_gpu { /* Updated chip ID */ qcom,chipid = <0x05040001>; - qcom,initial-pwrlevel = <5>; + qcom,initial-pwrlevel = <0>; qcom,gpu-pwrlevels { #address-cells = <1>; @@ -760,61 +760,29 @@ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <670000000>; - qcom,bus-freq = <12>; - qcom,bus-min = <11>; - qcom,bus-max = <12>; - }; - - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <596000000>; - qcom,bus-freq = <11>; - qcom,bus-min = <9>; - qcom,bus-max = <12>; - }; - - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <515000000>; - qcom,bus-freq = <11>; - qcom,bus-min = <9>; - qcom,bus-max = <12>; - }; - - qcom,gpu-pwrlevel@3 { - reg = <3>; - qcom,gpu-freq = <414000000>; - qcom,bus-freq = <9>; - qcom,bus-min = <8>; - qcom,bus-max = <11>; - }; - - qcom,gpu-pwrlevel@4 { - reg = <4>; qcom,gpu-freq = <342000000>; qcom,bus-freq = <8>; qcom,bus-min = <5>; qcom,bus-max = <9>; }; - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@1 { + reg = <1>; qcom,gpu-freq = <257000000>; qcom,bus-freq = <5>; qcom,bus-min = <3>; qcom,bus-max = <8>; }; - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <180000000>; qcom,bus-freq = <3>; qcom,bus-min = <1>; qcom,bus-max = <5>; }; - qcom,gpu-pwrlevel@7 { - reg = <7>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <27000000>; qcom,bus-freq = <0>; qcom,bus-min = <0>; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-qrd-skuk.dts b/arch/arm/boot/dts/qcom/msmcobalt-v2-qrd-skuk.dts index 78e810b816c9..581e9fef1aeb 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2-qrd-skuk.dts +++ b/arch/arm/boot/dts/qcom/msmcobalt-v2-qrd-skuk.dts @@ -19,5 +19,5 @@ / { model = "Qualcomm Technologies, Inc. MSM COBALT V2 SKUK"; compatible = "qcom,msmcobalt-qrd", "qcom,msmcobalt", "qcom,qrd"; - qcom,board-id = <0x01000b 0x80>; + qcom,board-id = <0x01000b 0x10>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dts b/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dts new file mode 100644 index 000000000000..e5ad123f52a7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dts @@ -0,0 +1,214 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "msmcobalt-v2.1-interposer-msmfalcon-qrd.dtsi" + +/ { + model = + "Qualcomm Technologies, Inc. MSM COBALT v2.1 MSM FALCON Interposer QRD"; + compatible = "qcom,msmcobalt-qrd", "qcom,msmcobalt", "qcom,qrd"; + qcom,board-id = <0x03000b 0x80>; +}; + +&slim_aud { + tasha_codec { + /delete-property/cdc-vdd-buck-supply; + /delete-property/cdc-buck-sido-supply; + /delete-property/cdc-vdd-tx-h-supply; + /delete-property/cdc-vdd-rx-h-supply; + /delete-property/cdc-vddpx-1-supply; + }; + + tavil_codec { + /delete-property/cdc-vdd-buck-supply; + /delete-property/cdc-buck-sido-supply; + /delete-property/cdc-vdd-tx-h-supply; + /delete-property/cdc-vdd-rx-h-supply; + /delete-property/cdc-vddpx-1-supply; + }; +}; + +&clock_gcc { + /delete-property/vdd_dig-supply; + /delete-property/vdd_dig_ao-supply; +}; + +&clock_mmss { + /delete-property/vdd_dig-supply; + /delete-property/vdd_mmsscc_mx-supply; +}; + +&clock_gpu { + /delete-property/vdd_dig-supply; +}; + +&clock_gfx { + /delete-property/vdd_mx-supply; + /delete-property/vdd_gpu_mx-supply; +}; + +&pcie0 { + /delete-property/vreg-1.8-supply; + /delete-property/vreg-0.9-supply; + /delete-property/vreg-cx-supply; +}; + +&qusb_phy0 { + /delete-property/vdd-supply; + /delete-property/vdda18-supply; + /delete-property/vdda33-supply; +}; + +&ssphy { + /delete-property/vdd-supply; + /delete-property/core-supply; +}; + +&usb3 { + /delete-property/extcon; +}; + +&mdss_dsi { + /delete-property/vdda-1p2-supply; + /delete-property/vdda-0p9-supply; +}; + +&mdss_dsi0 { + /delete-property/wqhd-vddio-supply; + /delete-property/lab-supply; + /delete-property/ibb-supply; +}; + +&mdss_dsi1 { + /delete-property/wqhd-vddio-supply; + /delete-property/lab-supply; + /delete-property/ibb-supply; +}; + +&mdss_hdmi_pll { + /delete-property/vdda-pll-supply; + /delete-property/vdda-phy-supply; +}; + +&mdss_dp_ctrl { + /delete-property/vdda-1p2-supply; + /delete-property/vdda-0p9-supply; + /delete-property/qcom,dp-usbpd-detection; +}; + +&apc0_cpr { + /* disable aging and closed-loop */ + /delete-property/vdd-supply; + /delete-property/qcom,cpr-enable; + /delete-property/qcom,cpr-hw-closed-loop; + /delete-property/qcom,cpr-aging-ref-voltage; +}; + +&apc0_pwrcl_vreg { + /delete-property/qcom,cpr-aging-max-voltage-adjustment; + /delete-property/qcom,cpr-aging-ref-corner; + /delete-property/qcom,cpr-aging-ro-scaling-factor; + /delete-property/qcom,allow-aging-voltage-adjustment; + /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; +}; + +&apc1_cpr { + /* disable aging and closed-loop */ + /delete-property/vdd-supply; + /delete-property/qcom,cpr-enable; + /delete-property/qcom,cpr-hw-closed-loop; + /delete-property/qcom,cpr-aging-ref-voltage; +}; + +&apc1_perfcl_vreg { + /delete-property/qcom,cpr-aging-max-voltage-adjustment; + /delete-property/qcom,cpr-aging-ref-corner; + /delete-property/qcom,cpr-aging-ro-scaling-factor; + /delete-property/qcom,allow-aging-voltage-adjustment; + /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; +}; + +&gfx_cpr { + reg = <0x05061000 0x4000>, + <0x00784000 0x1000>; + reg-names = "cpr_ctrl", "fuse_base"; + + /* disable aging and closed-loop */ + /delete-property/vdd-supply; + /delete-property/qcom,cpr-enable; + /delete-property/qcom,cpr-aging-ref-voltage; + /delete-property/qcom,cpr-aging-allowed-reg-mask; + /delete-property/qcom,cpr-aging-allowed-reg-value; +}; + +&gfx_vreg { + /delete-property/qcom,cpr-aging-max-voltage-adjustment; + /delete-property/qcom,cpr-aging-ref-corner; + /delete-property/qcom,cpr-aging-ro-scaling-factor; + /delete-property/qcom,allow-aging-voltage-adjustment; + /delete-property/qcom,allow-aging-open-loop-voltage-adjustment; +}; + +&clock_audio { + /delete-property/qcom,audio-ref-clk-gpio; +}; + +&soc { + /delete-node/qcom,csid@ca30000; + /delete-node/qcom,csid@ca30400; + /delete-node/qcom,csid@ca30800; + /delete-node/qcom,csid@ca30c00; + + /delete-node/qcom,lpass@17300000; + /delete-node/qcom,mss@4080000; + /delete-node/qcom,spss@1d00000; + /delete-node/qcom,bcl; + /delete-node/qcom,msm-thermal; + /delete-node/qcom,ssc@5c00000; + /delete-node/qcom,icnss@18800000; + /delete-node/qcom,wil6210; + /delete-node/qcom,rpm-smd; + /delete-node/qcom,spmi@800f000; + + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-glink"; + qcom,glink-edge = "rpm"; + rpm-channel-name = "rpm_requests"; + }; + + spmi_bus: qcom,spmi@800f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x800f000 0x1000>, + <0x8400000 0x1000000>, + <0x9400000 0x1000000>, + <0xa400000 0x220000>, + <0x800a000 0x3000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; +}; + +#include "msm-pmfalcon.dtsi" +#include "msm-pm2falcon.dtsi" +#include "msmfalcon-regulator.dtsi" diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dtsi new file mode 100644 index 000000000000..b257281466a9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dtsi @@ -0,0 +1,85 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include "msmcobalt-v2.1-interposer-msmfalcon.dtsi" + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&ufsphy1 { + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14600>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-max-microamp = <750000>; + vccq-max-microamp = <560000>; + vccq2-max-microamp = <750000>; + status = "ok"; +}; + +&ufs_ice { + status = "ok"; +}; + +&sdc2_cd_on { + mux { + pins = "gpio54"; + }; + + config { + pins = "gpio54"; + /delete-property/ bias-pull-up; + bias-disable; + }; +}; + +&sdc2_cd_off { + mux { + pins = "gpio54"; + }; + + config { + pins = "gpio54"; + /delete-property/ bias-pull-up; + bias-disable; + }; +}; + +&sdhc_2 { + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + qcom,clk-rates = <400000 20000000 25000000 + 50000000 100000000 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + cd-gpios = <&tlmm 54 0x0>; + + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi index beecee843778..93b586df5640 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi @@ -26,6 +26,25 @@ &clock_cpu { compatible = "qcom,cpu-clock-osm-msmcobalt-v2"; + reg = <0x179c0000 0x4000>, + <0x17916000 0x1000>, + <0x17816000 0x1000>, + <0x179d1000 0x1000>, + <0x17914800 0x800>, + <0x17814800 0x800>, + <0x00784130 0x8>, + <0x1791101c 0x8>; + reg-names = "osm", "pwrcl_pll", "perfcl_pll", + "apcs_common", "pwrcl_acd", "perfcl_acd", + "perfcl_efuse", "debug"; + + qcom,acdtd-val = <0x00009611 0x00009611>; + qcom,acdcr-val = <0x002b5ffd 0x002b5ffd>; + qcom,acdsscr-val = <0x00000501 0x00000501>; + qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8>; + qcom,acdextint1-val = <0x2cf9afc 0x2cf9afc>; + qcom,acdautoxfer-val = <0x00000015 0x00000015>; + /delete-property/ qcom,llm-sw-overr; qcom,pwrcl-speedbin0-v0 = < 300000000 0x0004000f 0x01200020 0x1 1 >, @@ -186,6 +205,24 @@ }; }; +&devfreq_memlat_0 { + qcom,core-dev-table = + < 595200 3143 >, + < 1324800 4173 >, + < 1555200 5859 >, + < 1747200 5859 >, + < 1900800 7759 >; +}; + +&devfreq_memlat_4 { + qcom,core-dev-table = + < 576000 3143 >, + < 1132800 4173 >, + < 1344000 5859 >, + < 1728000 7759 >, + < 1958400 11863 >, + < 2208000 13763 >; +}; &clock_gcc { compatible = "qcom,gcc-cobalt-v2"; }; @@ -208,7 +245,8 @@ < 414000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, < 515000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, < 596000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >; + < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >; qcom,gfxfreq-mx-speedbin0 = < 0 0 >, < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, @@ -217,7 +255,8 @@ < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, + < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; }; &mdss_mdp { @@ -419,51 +458,53 @@ qcom,cpr-open-loop-voltage-fuse-adjustment = /* Speed bin 0 */ - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <25000 9000 (-15000) 15000>, + <25000 9000 (-15000) 15000>, + <25000 9000 (-15000) 15000>, + <25000 9000 (-15000) 15000>, /* Speed bin 1 */ - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>, - <40000 24000 0 30000>; + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <40000 24000 0 30000>, + <25000 9000 (-15000) 15000>, + <25000 9000 (-15000) 15000>, + <25000 9000 (-15000) 15000>, + <25000 9000 (-15000) 15000>; qcom,cpr-closed-loop-voltage-fuse-adjustment = /* Speed bin 0 */ - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + < 5000 11000 (-15000) 15000>, + < 5000 11000 (-15000) 15000>, + < 5000 11000 (-15000) 15000>, + < 5000 11000 (-15000) 15000>, /* Speed bin 1 */ - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>, - <20000 26000 0 30000>; + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + <20000 26000 0 30000>, + < 5000 11000 (-15000) 15000>, + < 5000 11000 (-15000) 15000>, + < 5000 11000 (-15000) 15000>, + < 5000 11000 (-15000) 15000>; qcom,allow-voltage-interpolation; qcom,allow-quotient-interpolation; qcom,cpr-scaled-open-loop-voltage-as-ceiling; qcom,cpr-aging-ref-corner = <22 22>; - qcom,cpr-aging-ro-scaling-factor = <2950>; - qcom,allow-aging-voltage-adjustment = <0>; + qcom,cpr-aging-ro-scaling-factor = <1620>; + qcom,allow-aging-voltage-adjustment = + <0 0 0 0 1 1 1 1>, + <0 0 0 0 1 1 1 1>; }; &apc1_cpr { @@ -580,51 +621,53 @@ qcom,cpr-open-loop-voltage-fuse-adjustment = /* Speed bin 0 */ - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, + < 8000 0 0 52000>, + < 8000 0 0 52000>, + < 8000 0 0 52000>, + < 8000 0 0 52000>, + <(-7000) (-15000) (-15000) 37000>, + <(-7000) (-15000) (-15000) 37000>, + <(-7000) (-15000) (-15000) 37000>, + <(-7000) (-15000) (-15000) 37000>, /* Speed bin 1 */ - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>, - <8000 0 0 52000>; + < 8000 0 0 52000>, + < 8000 0 0 52000>, + < 8000 0 0 52000>, + < 8000 0 0 52000>, + <(-7000) (-15000) (-15000) 37000>, + <(-7000) (-15000) (-15000) 37000>, + <(-7000) (-15000) (-15000) 37000>, + <(-7000) (-15000) (-15000) 37000>; qcom,cpr-closed-loop-voltage-fuse-adjustment = /* Speed bin 0 */ - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, + < 0 0 0 50000>, + < 0 0 0 50000>, + < 0 0 0 50000>, + < 0 0 0 50000>, + <(-15000) (-15000) (-15000) 35000>, + <(-15000) (-15000) (-15000) 35000>, + <(-15000) (-15000) (-15000) 35000>, + <(-15000) (-15000) (-15000) 35000>, /* Speed bin 1 */ - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>, - <0 0 0 50000>; + < 0 0 0 50000>, + < 0 0 0 50000>, + < 0 0 0 50000>, + < 0 0 0 50000>, + <(-15000) (-15000) (-15000) 35000>, + <(-15000) (-15000) (-15000) 35000>, + <(-15000) (-15000) (-15000) 35000>, + <(-15000) (-15000) (-15000) 35000>; qcom,allow-voltage-interpolation; qcom,allow-quotient-interpolation; qcom,cpr-scaled-open-loop-voltage-as-ceiling; qcom,cpr-aging-ref-corner = <30 26>; - qcom,cpr-aging-ro-scaling-factor = <2950>; - qcom,allow-aging-voltage-adjustment = <0>; + qcom,cpr-aging-ro-scaling-factor = <1700>; + qcom,allow-aging-voltage-adjustment = + <0 0 0 0 1 1 1 1>, + <0 0 0 0 1 1 1 1>; }; &pm8005_s1 { @@ -648,14 +691,14 @@ qcom,cpr-corner-fmax-map = <1 3 5 8>; qcom,cpr-voltage-ceiling = - <656000 716000 772000 880000 908000 948000 1016000 1088000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>, - <660000 724000 772000 832000 916000 968000 1024000 1024000>; + <716000 716000 772000 880000 908000 948000 1016000 1088000>, + <724000 724000 772000 832000 916000 968000 1024000 1024000>, + <724000 724000 772000 832000 916000 968000 1024000 1024000>, + <724000 724000 772000 832000 916000 968000 1024000 1024000>, + <724000 724000 772000 832000 916000 968000 1024000 1024000>, + <724000 724000 772000 832000 916000 968000 1024000 1024000>, + <724000 724000 772000 832000 916000 968000 1024000 1024000>, + <724000 724000 772000 832000 916000 968000 1024000 1024000>; qcom,cpr-voltage-floor = <516000 516000 532000 584000 632000 672000 712000 756000>; @@ -703,46 +746,46 @@ 0 0 2168 0 2209 1849 1997 0>; qcom,cpr-open-loop-voltage-fuse-adjustment = - < 100000 0 0 0>, - < 100000 0 0 0>, - < 85000 (-15000) (-15000) (-15000)>, - < 85000 (-15000) (-15000) (-15000)>, - < 85000 (-15000) (-15000) (-15000)>, - < 85000 (-15000) (-15000) (-15000)>, - < 85000 (-15000) (-15000) (-15000)>, - < 85000 (-15000) (-15000) (-15000)>; + < 60000 0 0 0>, + < 60000 0 0 0>, + < 60000 0 0 0>, + < 45000 (-15000) (-15000) (-15000)>, + < 45000 (-15000) (-15000) (-15000)>, + < 45000 (-15000) (-15000) (-15000)>, + < 45000 (-15000) (-15000) (-15000)>, + < 45000 (-15000) (-15000) (-15000)>; qcom,cpr-closed-loop-voltage-adjustment = - < 96000 18000 4000 0 - 0 13000 9000 0>, - < 96000 18000 4000 0 - 0 13000 9000 0>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>, - < 81000 3000 (-11000) (-15000) - (-15000) (-2000) (-6000) (-15000)>; + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 90000 38000 28000 8000 + 0 29000 11000 0>, + < 75000 23000 13000 (-7000) + (-15000) 14000 (-4000) (-15000)>, + < 75000 23000 13000 (-7000) + (-15000) 14000 (-4000) (-15000)>, + < 75000 23000 13000 (-7000) + (-15000) 14000 (-4000) (-15000)>, + < 75000 23000 13000 (-7000) + (-15000) 14000 (-4000) (-15000)>, + < 75000 23000 13000 (-7000) + (-15000) 14000 (-4000) (-15000)>; qcom,cpr-floor-to-ceiling-max-range = <50000 50000 50000 50000 50000 50000 70000 70000>; qcom,cpr-fused-closed-loop-voltage-adjustment-map = - <0 0 1 2 3 0 0 4>; + <0 0 0 0 1 2 3 4>; qcom,allow-voltage-interpolation; qcom,cpr-scaled-open-loop-voltage-as-ceiling; qcom,cpr-aging-max-voltage-adjustment = <15000>; qcom,cpr-aging-ref-corner = <8>; - qcom,cpr-aging-ro-scaling-factor = <2950>; - qcom,allow-aging-voltage-adjustment = <0 0 1 1 1 1 1 1>; + qcom,cpr-aging-ro-scaling-factor = <1620>; + qcom,allow-aging-voltage-adjustment = <0 0 0 1 1 1 1 1>; }; &qusb_phy0 { @@ -886,13 +929,6 @@ qcom,gpu-pwrlevel@6 { reg = <6>; - qcom,gpu-freq = <180000000>; - qcom,bus-freq = <3>; - qcom,bus-min = <1>; - qcom,bus-max = <5>; - }; - qcom,gpu-pwrlevel@7 { - reg = <7>; qcom,gpu-freq = <27000000>; qcom,bus-freq = <0>; qcom,bus-min = <0>; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi index f17be7570742..a8655c2e88a0 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi @@ -25,6 +25,7 @@ qcom,firmware-name = "venus"; qcom,never-unload-fw; qcom,sw-power-collapse; + qcom,max-secure-instances = <5>; qcom,debug-timeout; qcom,reg-presets = <0x80124 0x00000003>, diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 3ad4b6b5622d..9b0d3f674032 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -611,7 +611,7 @@ < 13763 /* 1804 MHz */ >; }; - qcom,arm-memlat-mon-0 { + devfreq_memlat_0: qcom,arm-memlat-mon-0 { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; qcom,target-dev = <&memlat_cpu0>; @@ -622,7 +622,7 @@ < 1881600 5859 >; }; - qcom,arm-memlat-mon-4 { + devfreq_memlat_4: qcom,arm-memlat-mon-4 { compatible = "qcom,arm-memlat-mon"; qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,target-dev = <&memlat_cpu4>; @@ -1568,6 +1568,10 @@ qcom,vreg-cx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_BINNING RPM_SMD_REGULATOR_LEVEL_SVS 0>; + qcom,l1-supported; + qcom,l1ss-supported; + qcom,aux-clk-sync; + qcom,ep-latency = <10>; qcom,ep-wakeirq; @@ -1887,6 +1891,7 @@ usb-phy = <&qusb_phy0>, <&ssphy>; tx-fifo-resize; snps,nominal-elastic-buffer; + snps,disable-clk-gating; snps,hird_thresh = <0x10>; snps,num-gsi-evt-buffs = <0x3>; }; @@ -2157,6 +2162,32 @@ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>; }; + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x200000>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x300000>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <1>; + label = "modem"; + }; + }; + pil_modem: qcom,mss@4080000 { compatible = "qcom,pil-q6v55-mss"; reg = <0x4080000 0x100>, @@ -3117,5 +3148,6 @@ #include "msm-audio-lpass.dtsi" #include "msmcobalt-mdss.dtsi" #include "msmcobalt-mdss-pll.dtsi" +#include "msm-rdbg.dtsi" #include "msmcobalt-blsp.dtsi" #include "msmcobalt-audio.dtsi" diff --git a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi index 124ab341ba6b..cfe968a7310a 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi @@ -10,351 +10,438 @@ * GNU General Public License for more details. */ -/* Stub regulators */ - -/ { - /* PMFALCON S1 - VDD_APC0 supply */ - pmfalcon_s1a: regulator-pmfalcon-s1a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s1a"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <565000>; - regulator-max-microvolt = <1170000>; - }; - - /* PMFALCON S2 + S3 = VDD_APC1 supply */ - pmfalcon_s2a: regulator-pmfalcon-s2a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s2a"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <565000>; - regulator-max-microvolt = <1170000>; - }; - - pmfalcon_s4a: regulator-pmfalcon-s4a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s4a"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <1805000>; - regulator-max-microvolt = <2040000>; - }; - - pmfalcon_s5a: regulator-pmfalcon-s5a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s5a"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - }; - - pmfalcon_s6a: regulator-pmfalcon-s6a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s6a"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <504000>; - regulator-max-microvolt = <992000>; - }; - - pmfalcon_s1b: regulator-pmfalcon-s1b { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s1b"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <1125000>; - regulator-max-microvolt = <1125000>; - }; - - pmfalcon_s2b: regulator-pmfalcon-s2b { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s2b"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - }; - - /* PMFALCON S3 + S4 - VDD_CX supply */ - pmfalcon_s3b_level: regulator-pmfalcon-s3b-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s3b_level"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - }; - - pmfalcon_s3b_floor_level: regulator-pmfalcon-s3b-floor-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s3b_floor_level"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - }; - - pmfalcon_s3b_level_ao: regulator-pmfalcon-s3b-level-ao { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s3b_level_ao"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - }; - - /* PMFALCON S5 - VDD_MX supply */ - pmfalcon_s5b_level: regulator-pmfalcon-s5b-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s5b_level"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - }; - - pmfalcon_s5b_floor_level: regulator-pmfalcon-s5b-floor-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s5b_floor_level"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - }; - - pmfalcon_s5b_level_ao: regulator-pmfalcon-s5b-level-ao { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_s5b_level_ao"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - }; - - pmfalcon_l1a: regulator-pmfalcon-l1a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l1a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1250000>; - }; - - pmfalcon_l2a: regulator-pmfalcon-l2a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l2a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1010000>; - }; - - pmfalcon_l3a: regulator-pmfalcon-l3a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l3a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1010000>; +&rpm_bus { + rpm-regulator-smpa4 { + status = "okay"; + pmfalcon_s4: regulator-s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa5 { + status = "okay"; + pmfalcon_s5: regulator-s5 { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa6 { + status = "okay"; + pmfalcon_s6: regulator-s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + status = "okay"; + }; + }; + + rpm-regulator-smpb1 { + status = "okay"; + pm2falcon_s1: regulator-s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + status = "okay"; + }; + }; + + rpm-regulator-smpb2 { + status = "okay"; + pm2falcon_s2: regulator-s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + }; + + /* PM2FALCON S3 + S4 - VDD_CX supply */ + rpm-regulator-smpb3 { + status = "okay"; + pm2falcon_s3_level: regulator-s3-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_s3_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + pm2falcon_s3_floor_level: regulator-s3-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_s3_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm2falcon_s3_level_ao: regulator-s3-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_s3_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + }; + + /* PM2FALCON S5 - VDD_MX supply */ + rpm-regulator-smpb5 { + status = "okay"; + pm2falcon_s5_level: regulator-s5-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_s5_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + pm2falcon_s5_floor_level: regulator-s5-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_s5_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm2falcon_s5_level_ao: regulator-s5-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_s5_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pmfalcon_l1: regulator-l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pmfalcon_l2: regulator-l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pmfalcon_l3: regulator-l3 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + status = "okay"; + }; }; /* TODO: remove if ADRASTEA CX/MX not voted from APPS */ - pmfalcon_l5a: regulator-pmfalcon-l5a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l5a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <525000>; - regulator-max-microvolt = <950000>; - }; - - pmfalcon_l6a: regulator-pmfalcon-l6a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l6a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1370000>; - }; - - pmfalcon_l7a: regulator-pmfalcon-l7a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l7a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - pmfalcon_l8a: regulator-pmfalcon-l8a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l8a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1900000>; - }; - - pmfalcon_l9a: regulator-pmfalcon-l9a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l9a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1900000>; - }; - - pmfalcon_l10a: regulator-pmfalcon-l10a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l10a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1780000>; - regulator-max-microvolt = <1950000>; - }; - - pmfalcon_l11a: regulator-pmfalcon-l11a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l11a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1780000>; - regulator-max-microvolt = <1950000>; - }; - - pmfalcon_l12a: regulator-pmfalcon-l12a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l12a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1780000>; - regulator-max-microvolt = <1950000>; - }; - - pmfalcon_l13a: regulator-pmfalcon-l13a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l13a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1950000>; - }; - - pmfalcon_l14a: regulator-pmfalcon-l14a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l14a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1900000>; - }; - - pmfalcon_l15a: regulator-pmfalcon-l15a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l15a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2950000>; - }; - - pmfalcon_l17a: regulator-pmfalcon-l17a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l17a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2950000>; - }; - - pmfalcon_l19a: regulator-pmfalcon-l19a { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l19a"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; - }; - - pmfalcon_l1b: regulator-pmfalcon-l1b { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l1b"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <925000>; - }; - - pmfalcon_l2b: regulator-pmfalcon-l2b { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l2b"; - qcom,hpm-min-load = <5000>; - regulator-min-microvolt = <350000>; - regulator-max-microvolt = <3100000>; - }; - - pmfalcon_l3b: regulator-pmfalcon-l3b { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l3b"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <3600000>; - }; - - pmfalcon_l4b: regulator-pmfalcon-l4b { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l4b"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <2950000>; - }; - - pmfalcon_l5b: regulator-pmfalcon-l5b { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l5b"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1721000>; - regulator-max-microvolt = <3600000>; - }; - - pmfalcon_l6b: regulator-pmfalcon-l6b { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l6b"; - qcom,hpm-min-load = <5000>; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <3300000>; - }; - - pmfalcon_l7b: regulator-pmfalcon-l7b { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l7b"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3125000>; - }; - - pmfalcon_l8b: regulator-pmfalcon-l8b { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l8b"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; - }; - - /* PMFALCON L9 = VDD_SSC_CX supply */ - pmfalcon_l9b_level: regulator-pmfalcon-l9b-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l9b_level"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - }; - - pmfalcon_l9b_floor_level: regulator-pmfalcon-l9b-floor-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l9b_floor_level"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - }; - - /* PMFALCON L10 = VDD_SSC_MX supply */ - pmfalcon_l10b_level: regulator-pmfalcon-l10b-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l10b_level"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - }; - - pmfalcon_l10b_floor_level: regulator-pmfalcon-l10b-floor-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_l10b_floor_level"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - }; - - pmfalcon_bob: regulator-pmfalcon-bob { - compatible = "qcom,stub-regulator"; - regulator-name = "pmfalcon_bob"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + rpm-regulator-ldoa5 { + status = "okay"; + pmfalcon_l5: regulator-l5 { + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pmfalcon_l6: regulator-l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pmfalcon_l7: regulator-l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pmfalcon_l8: regulator-l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pmfalcon_l9: regulator-l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pmfalcon_l10: regulator-l10 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pmfalcon_l11: regulator-l11 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pmfalcon_l12: regulator-l12 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pmfalcon_l13: regulator-l13 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pmfalcon_l14: regulator-l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pmfalcon_l15: regulator-l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pmfalcon_l17: regulator-l17 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pmfalcon_l19: regulator-l19 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob1 { + status = "okay"; + pm2falcon_l1: regulator-l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob2 { + status = "okay"; + pm2falcon_l2: regulator-l2 { + regulator-min-microvolt = <350000>; + regulator-max-microvolt = <3100000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob3 { + status = "okay"; + pm2falcon_l3: regulator-l3 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <3600000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob4 { + status = "okay"; + pm2falcon_l4: regulator-l4 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob5 { + status = "okay"; + pm2falcon_l5: regulator-l5 { + regulator-min-microvolt = <1721000>; + regulator-max-microvolt = <3600000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob6 { + status = "okay"; + pm2falcon_l6: regulator-l6 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob7 { + status = "okay"; + pm2falcon_l7: regulator-l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob8 { + status = "okay"; + pm2falcon_l8: regulator-l8 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + status = "okay"; + }; + }; + + /* PM2FALCON L9 = VDD_SSC_CX supply */ + rpm-regulator-ldob9 { + status = "okay"; + pm2falcon_l9_level: regulator-l9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l9_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + pm2falcon_l9_floor_level: regulator-l9-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l9_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + /* PM2FALCON L10 = VDD_SSC_MX supply */ + rpm-regulator-ldob10 { + status = "okay"; + pm2falcon_l10_level: regulator-l10-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l10_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + pm2falcon_l10_floor_level: regulator-l10-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_l10_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-bobb { + status = "okay"; + pm2falcon_bob: regulator-bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + status = "okay"; + }; + + pm2falcon_bob_pin1: regulator-bob-pin1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_bob_pin1"; + qcom,set = <3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + qcom,use-pin-ctrl-voltage1; + }; + + pm2falcon_bob_pin2: regulator-bob-pin2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_bob_pin2"; + qcom,set = <3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + qcom,use-pin-ctrl-voltage2; + }; + + pm2falcon_bob_pin3: regulator-bob-pin3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2falcon_bob_pin3"; + qcom,set = <3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + qcom,use-pin-ctrl-voltage3; + }; }; +}; +/* Stub regulators */ +/ { /* GFX Supply */ gfx_vreg_corner: regulator-gfx-corner { compatible = "qcom,stub-regulator"; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts index f0ba8b115120..c94ba0df3e6e 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts @@ -20,6 +20,10 @@ model = "Qualcomm Technologies, Inc. MSM FALCON RUMI"; compatible = "qcom,msmfalcon-rumi", "qcom,msmfalcon", "qcom,rumi"; qcom,board-id = <15 0>; + + chosen { + bootargs = "lpm_levels.sleep_disabled=1"; + }; }; &uartblsp1dm1 { @@ -30,12 +34,12 @@ &sdhc_1 { /* device core power supply */ - vdd-supply = <&pmfalcon_l4b>; + vdd-supply = <&pm2falcon_l4>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ - vdd-io-supply = <&pmfalcon_l8a>; + vdd-io-supply = <&pmfalcon_l8>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; @@ -53,3 +57,8 @@ status = "ok"; }; + +&clock_gcc { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts b/arch/arm/boot/dts/qcom/msmfalcon-sim.dts index 085419b7e108..00d97c8fdd32 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts +++ b/arch/arm/boot/dts/qcom/msmfalcon-sim.dts @@ -20,6 +20,10 @@ model = "Qualcomm Technologies, Inc. MSM FALCON SIM"; compatible = "qcom,msmfalcon-sim", "qcom,msmfalcon", "qcom,sim"; qcom,board-id = <16 0>; + + chosen { + bootargs = "lpm_levels.sleep_disabled=1"; + }; }; &uartblsp1dm1 { @@ -30,12 +34,12 @@ &sdhc_1 { /* device core power supply */ - vdd-supply = <&pmfalcon_l4b>; + vdd-supply = <&pm2falcon_l4>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ - vdd-io-supply = <&pmfalcon_l8a>; + vdd-io-supply = <&pmfalcon_l8>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index f2adc32fb732..473270d6e87d 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -287,6 +287,32 @@ qcom,pipe-attr-ee; }; + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x200000>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x300000>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <1>; + label = "modem"; + }; + }; + tsens: tsens@10ad000 { compatible = "qcom,msmfalcon-tsens"; reg = <0x10ad000 0x2000>, @@ -319,6 +345,31 @@ clock-names = "core", "iface"; }; + slim_aud: slim@151c0000 { + cell-index = <1>; + compatible = "qcom,slim-ngd"; + reg = <0x151c0000 0x2c000>, + <0x15180000 0x2e000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 163 0>, <0 164 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x7e0000>; + qcom,ea-pc = <0x260>; + status = "disabled"; + }; + + slim_qca: slim@15240000 { + cell-index = <3>; + compatible = "qcom,slim-ngd"; + reg = <0x15240000 0x2c000>, + <0x15200000 0x24000>; + reg-names = "slimbus_physical", "slimbus_bam_physical"; + interrupts = <0 291 0>, <0 292 0>; + interrupt-names = "slimbus_irq", "slimbus_bam_irq"; + qcom,apps-ch-pipes = <0x1800>; + status = "disabled"; + }; + timer@17920000 { #address-cells = <1>; #size-cells = <1>; @@ -384,8 +435,10 @@ }; clock_gcc: clock-controller@100000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,gcc-msmfalcon"; + reg = <0x100000 0x94000>; + vdd_dig-supply = <&pm2falcon_s3_level>; + vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -696,7 +749,7 @@ reg = <0x15700000 0x00100>; interrupts = <0 162 1>; - vdd_cx-supply = <&pmfalcon_s3b_level>; + vdd_cx-supply = <&pm2falcon_s3_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; @@ -728,7 +781,7 @@ reg = <0x1a300000 0x00100>; interrupts = <0 518 1>; - vdd_cx-supply = <&pmfalcon_s3b_level>; + vdd_cx-supply = <&pm2falcon_s3_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; @@ -783,9 +836,9 @@ "mnoc_axi_clk"; interrupts = <0 448 1>; - vdd_cx-supply = <&pmfalcon_s3b_level>; + vdd_cx-supply = <&pm2falcon_s3_level>; vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - vdd_mx-supply = <&pmfalcon_s5b_level>; + vdd_mx-supply = <&pm2falcon_s5_level>; vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; qcom,firmware-name = "modem"; qcom,pil-self-auth; @@ -807,10 +860,25 @@ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; status = "ok"; }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + }; }; #include "msmfalcon-ion.dtsi" #include "msmfalcon-bus.dtsi" +#include "msm-pmfalcon-rpm-regulator.dtsi" +#include "msm-pm2falcon-rpm-regulator.dtsi" #include "msmfalcon-regulator.dtsi" #include "msm-gdsc-falcon.dtsi" diff --git a/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi b/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi new file mode 100644 index 000000000000..323024278406 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi @@ -0,0 +1,365 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Stub regulators */ + +/ { + /* PMFALCON S1 - VDD_APC0 supply */ + pmfalcon_s1: regulator-pmfalcon-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_s1"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <565000>; + regulator-max-microvolt = <1170000>; + }; + + /* PMFALCON S2 + S3 = VDD_APC1 supply */ + pmfalcon_s2: regulator-pmfalcon-s2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_s2"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <565000>; + regulator-max-microvolt = <1170000>; + }; + + pmfalcon_s4: regulator-pmfalcon-s4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_s4"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + }; + + pmfalcon_s5: regulator-pmfalcon-s5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_s5"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + }; + + pmfalcon_s6: regulator-pmfalcon-s6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_s6"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + }; + + pm2falcon_s1: regulator-pm2falcon-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_s1"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + }; + + pm2falcon_s2: regulator-pm2falcon-s2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_s2"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + /* PMFALCON S3 + S4 - VDD_CX supply */ + pm2falcon_s3_level: regulator-pm2falcon-s3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_s3_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + }; + + pm2falcon_s3_floor_level: regulator-pm2falcon-s3-floor-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_s3_floor_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + }; + + pm2falcon_s3_level_ao: regulator-pm2falcon-s3-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_s3_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + }; + + /* PMFALCON S5 - VDD_MX supply */ + pm2falcon_s5_level: regulator-pm2falcon-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_s5_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + }; + + pm2falcon_s5_floor_level: regulator-pm2falcon-s5-floor-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_s5_floor_level"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + }; + + pm2falcon_s5_level_ao: regulator-pm2falcon-s5-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_s5_level_ao"; + qcom,hpm-min-load = <100000>; + regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + }; + + pmfalcon_l1: regulator-pmfalcon-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + }; + + pmfalcon_l2: regulator-pmfalcon-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + }; + + pmfalcon_l3: regulator-pmfalcon-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + }; + + /* TODO: remove if ADRASTEA CX/MX not voted from APPS */ + pmfalcon_l5: regulator-pmfalcon-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <950000>; + }; + + pmfalcon_l6: regulator-pmfalcon-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + }; + + pmfalcon_l7: regulator-pmfalcon-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pmfalcon_l8: regulator-pmfalcon-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + }; + + pmfalcon_l9: regulator-pmfalcon-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + }; + + pmfalcon_l10: regulator-pmfalcon-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + }; + + pmfalcon_l11: regulator-pmfalcon-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + }; + + pmfalcon_l12: regulator-pmfalcon-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + }; + + pmfalcon_l13: regulator-pmfalcon-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1950000>; + }; + + pmfalcon_l14: regulator-pmfalcon-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l14"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1900000>; + }; + + pmfalcon_l15: regulator-pmfalcon-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l15"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + }; + + pmfalcon_l17: regulator-pmfalcon-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + }; + + pmfalcon_l19: regulator-pmfalcon-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmfalcon_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + + pm2falcon_l1: regulator-pm2falcon-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + }; + + pm2falcon_l2: regulator-pm2falcon-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l2"; + qcom,hpm-min-load = <5000>; + regulator-min-microvolt = <350000>; + regulator-max-microvolt = <3100000>; + }; + + pm2falcon_l3: regulator-pm2falcon-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <3600000>; + }; + + pm2falcon_l4: regulator-pm2falcon-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2950000>; + }; + + pm2falcon_l5: regulator-pm2falcon-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1721000>; + regulator-max-microvolt = <3600000>; + }; + + pm2falcon_l6: regulator-pm2falcon-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l6"; + qcom,hpm-min-load = <5000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + }; + + pm2falcon_l7: regulator-pm2falcon-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + }; + + pm2falcon_l8: regulator-pm2falcon-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + + /* PMFALCON L9 = VDD_SSC_CX supply */ + pm2falcon_l9_level: regulator-pm2falcon-l9-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l9_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + }; + + pm2falcon_l9_floor_level: regulator-pm2falcon-l9-floor-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l9_floor_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + }; + + /* PMFALCON L10 = VDD_SSC_MX supply */ + pm2falcon_l10_level: regulator-pm2falcon-l10-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l10_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + }; + + pm2falcon_l10_floor_level: regulator-pm2falcon-l10-floor-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_l10_floor_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = <RPM_SMD_REGULATOR_LEVEL_TURBO>; + }; + + pm2falcon_bob: regulator-pm2falcon-bob { + compatible = "qcom,stub-regulator"; + regulator-name = "pm2falcon_bob"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* GFX Supply */ + gfx_vreg_corner: regulator-gfx-corner { + compatible = "qcom,stub-regulator"; + regulator-name = "gfx_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts index d3c62dbf99f2..0317c35d1f44 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts @@ -27,3 +27,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; }; + +&clock_gcc { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; +}; diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi index 8374d27e5b56..06f296a49113 100644 --- a/arch/arm/boot/dts/qcom/msmtriton.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi @@ -246,6 +246,32 @@ qcom,pipe-attr-ee; }; + qcom,memshare { + compatible = "qcom,memshare"; + + qcom,client_1 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x200000>; + qcom,client-id = <0>; + qcom,allocate-boot-time; + label = "modem"; + }; + + qcom,client_2 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x300000>; + qcom,client-id = <2>; + label = "modem"; + }; + + mem_client_3_size: qcom,client_3 { + compatible = "qcom,memshare-peripheral"; + qcom,peripheral-size = <0x0>; + qcom,client-id = <1>; + label = "modem"; + }; + }; + tsens: tsens@10ad000 { compatible = "qcom,msmtriton-tsens"; reg = <0x10ad000 0x2000>; @@ -340,8 +366,10 @@ }; clock_gcc: clock-controller@100000 { - compatible = "qcom,dummycc"; - clock-output-names = "gcc_clocks"; + compatible = "qcom,gcc-msmfalcon"; + reg = <0x100000 0x94000>; + vdd_dig-supply = <&pm2falcon_s3_level>; + vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -503,6 +531,13 @@ qcom,xprt = "smem"; }; + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-glink"; + qcom,glink-edge = "rpm"; + rpm-channel-name = "rpm_requests"; + rpm-standalone; + }; + qcom,ipc_router { compatible = "qcom,ipc_router"; qcom,node-id = <1>; @@ -554,7 +589,7 @@ reg = <0x15700000 0x00100>; interrupts = <0 162 1>; - vdd_cx-supply = <&pmfalcon_s3b_level>; + vdd_cx-supply = <&pm2falcon_s3_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; @@ -638,9 +673,9 @@ "mnoc_axi_clk"; interrupts = <0 448 1>; - vdd_cx-supply = <&pmfalcon_s3b_level>; + vdd_cx-supply = <&pm2falcon_s3_level>; vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - vdd_mx-supply = <&pmfalcon_s5b_level>; + vdd_mx-supply = <&pm2falcon_s5_level>; vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; qcom,firmware-name = "modem"; qcom,pil-self-auth; @@ -662,10 +697,23 @@ qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>; status = "ok"; }; + + qcom,msm-imem@146bf000 { + compatible = "qcom,msm-imem"; + reg = <0x146bf000 0x1000>; + ranges = <0x0 0x146bf000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 200>; + }; + }; }; #include "msmtriton-ion.dtsi" -#include "msmfalcon-regulator.dtsi" +#include "msmtriton-regulator.dtsi" #include "msm-gdsc-falcon.dtsi" &gdsc_usb30 { diff --git a/arch/arm/configs/msmcortex_defconfig b/arch/arm/configs/msmcortex_defconfig index 8be2b187a524..f8743e760054 100644 --- a/arch/arm/configs/msmcortex_defconfig +++ b/arch/arm/configs/msmcortex_defconfig @@ -27,6 +27,7 @@ CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_ARCH_MMAP_RND_BITS=16 CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y @@ -440,6 +441,7 @@ CONFIG_MSM_GLINK_PKT=y CONFIG_MSM_SPM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_IRQ_HELPER=y CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_ICNSS=y CONFIG_ICNSS_DEBUG=y diff --git a/arch/arm/configs/msmfalcon_defconfig b/arch/arm/configs/msmfalcon_defconfig index 74ee9792a284..511b9fe32b9b 100644 --- a/arch/arm/configs/msmfalcon_defconfig +++ b/arch/arm/configs/msmfalcon_defconfig @@ -38,6 +38,7 @@ CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_QCOM=y CONFIG_ARCH_MSMFALCON=y +CONFIG_ARCH_MSMTRITON=y CONFIG_SMP=y CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 @@ -450,6 +451,7 @@ CONFIG_MSM_GLINK_PKT=y CONFIG_MSM_SPM=y CONFIG_QCOM_SCM=y CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_IRQ_HELPER=y CONFIG_QCOM_MEMORY_DUMP_V2=y CONFIG_ICNSS=y CONFIG_ICNSS_DEBUG=y diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index d4d355531169..cbccbeb483c9 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -39,6 +39,38 @@ config ARCH_MSMFALCON This enables support for the MSMFALCON chipset. If you do not wish to build a kernel that runs on this chipset, say 'N' here. +config ARCH_MSMTRITON + bool "Enable Support for Qualcomm MSMTRITON" + select CLKDEV_LOOKUP + select HAVE_CLK + select HAVE_CLK_PREPARE + select PM_OPP + select SOC_BUS + select MSM_IRQ + select THERMAL_WRITABLE_TRIPS + select ARM_GIC_V3 + select ARM_AMBA + select SPARSE_IRQ + select MULTI_IRQ_HANDLER + select HAVE_ARM_ARCH_TIMER + select MAY_HAVE_SPARSE_IRQ + select MSM_PM if PM + select QMI_ENCDEC + select CPU_FREQ + select CPU_FREQ_MSM + select PM_DEVFREQ + select MSM_DEVFREQ_DEVBW + select DEVFREQ_SIMPLE_DEV + select DEVFREQ_GOV_MSM_BW_HWMON + select MSM_BIMC_BWMON + select MSM_QDSP6V2_CODECS + select MSM_AUDIO_QDSP6V2 if SND_SOC + select MSM_RPM_SMD + select MSM_JTAGV8 if CORESIGHT_ETMV4 + help + This enables support for the MSMTRITON chipset. If you do not + wish to build a kernel that runs on this chipset, say 'N' here. + config ARCH_MSM8X60 bool "Enable support for MSM8X60" select ARCH_SUPPORTS_BIG_ENDIAN diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 52486c0e6598..80c4c50814d8 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -807,6 +807,7 @@ static void arm_dma_unremap(struct device *dev, void *remapped_addr, unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP; struct vm_struct *area; + size = PAGE_ALIGN(size); remapped_addr = (void *)((unsigned long)remapped_addr & PAGE_MASK); area = find_vm_area(remapped_addr); @@ -1818,7 +1819,7 @@ void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, total_length = PAGE_ALIGN((iova & ~PAGE_MASK) + total_length); iova &= PAGE_MASK; - iommu_unmap_range(mapping->domain, iova, total_length); + iommu_unmap(mapping->domain, iova, total_length); __free_iova(mapping, iova, total_length); } diff --git a/arch/arm64/configs/msm-perf_defconfig b/arch/arm64/configs/msm-perf_defconfig index 5f8b02904d49..520a60c46106 100644 --- a/arch/arm64/configs/msm-perf_defconfig +++ b/arch/arm64/configs/msm-perf_defconfig @@ -32,6 +32,7 @@ CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=16 CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y diff --git a/arch/arm64/configs/msm_defconfig b/arch/arm64/configs/msm_defconfig index c1c0ae9da001..6249b604466b 100644 --- a/arch/arm64/configs/msm_defconfig +++ b/arch/arm64/configs/msm_defconfig @@ -29,6 +29,7 @@ CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=16 CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig index 0bda100dfb5a..3990bece1dd1 100644 --- a/arch/arm64/configs/msmcortex-perf_defconfig +++ b/arch/arm64/configs/msmcortex-perf_defconfig @@ -35,6 +35,7 @@ CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=16 CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y @@ -249,6 +250,8 @@ CONFIG_DM_CRYPT=y CONFIG_DM_REQ_CRYPT=y CONFIG_DM_UEVENT=y CONFIG_DM_VERITY=y +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_ANDROID_VERITY=y CONFIG_NETDEVICES=y CONFIG_BONDING=y CONFIG_DUMMY=y @@ -380,9 +383,9 @@ CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y CONFIG_MSMB_JPEG=y CONFIG_MSM_FD=y CONFIG_MSM_JPEGDMA=y -CONFIG_MSM_VIDC_V4L2=m -CONFIG_MSM_VIDC_VMEM=m -CONFIG_MSM_VIDC_GOVERNORS=m +CONFIG_MSM_VIDC_V4L2=y +CONFIG_MSM_VIDC_VMEM=y +CONFIG_MSM_VIDC_GOVERNORS=y CONFIG_MSM_SDE_ROTATOR=y CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y CONFIG_QCOM_KGSL=y diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig index 3568fe4ed29f..15ca50859eca 100644 --- a/arch/arm64/configs/msmcortex_defconfig +++ b/arch/arm64/configs/msmcortex_defconfig @@ -34,6 +34,7 @@ CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=16 CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y @@ -251,6 +252,8 @@ CONFIG_DM_CRYPT=y CONFIG_DM_REQ_CRYPT=y CONFIG_DM_UEVENT=y CONFIG_DM_VERITY=y +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_ANDROID_VERITY=y CONFIG_NETDEVICES=y CONFIG_BONDING=y CONFIG_DUMMY=y @@ -383,9 +386,9 @@ CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y CONFIG_MSMB_JPEG=y CONFIG_MSM_FD=y CONFIG_MSM_JPEGDMA=y -CONFIG_MSM_VIDC_V4L2=m -CONFIG_MSM_VIDC_VMEM=m -CONFIG_MSM_VIDC_GOVERNORS=m +CONFIG_MSM_VIDC_V4L2=y +CONFIG_MSM_VIDC_VMEM=y +CONFIG_MSM_VIDC_GOVERNORS=y CONFIG_MSM_SDE_ROTATOR=y CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y CONFIG_QCOM_KGSL=y diff --git a/arch/arm64/configs/msmfalcon-perf_defconfig b/arch/arm64/configs/msmfalcon-perf_defconfig index dde7a01a9a36..df695f993ed9 100644 --- a/arch/arm64/configs/msmfalcon-perf_defconfig +++ b/arch/arm64/configs/msmfalcon-perf_defconfig @@ -259,9 +259,15 @@ CONFIG_SMSC911X=y CONFIG_PPP=y CONFIG_PPP_BSDCOMP=y CONFIG_PPP_DEFLATE=y +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=y +CONFIG_PPPOL2TP=y CONFIG_PPPOLAC=y CONFIG_PPPOPNS=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y CONFIG_USB_USBNET=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_ATH_CARDS=y diff --git a/arch/arm64/configs/msmfalcon_defconfig b/arch/arm64/configs/msmfalcon_defconfig index 7c56e933c853..8719eb7cb92e 100644 --- a/arch/arm64/configs/msmfalcon_defconfig +++ b/arch/arm64/configs/msmfalcon_defconfig @@ -260,9 +260,15 @@ CONFIG_PHYLIB=y CONFIG_PPP=y CONFIG_PPP_BSDCOMP=y CONFIG_PPP_DEFLATE=y +CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=y +CONFIG_PPPOL2TP=y CONFIG_PPPOLAC=y CONFIG_PPPOPNS=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_ATH_CARDS=y CONFIG_WIL6210=m diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 07c67348b815..df083e9350c4 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -455,6 +455,7 @@ static void arm64_dma_unremap(struct device *dev, void *remapped_addr, { struct vm_struct *area; + size = PAGE_ALIGN(size); remapped_addr = (void *)((unsigned long)remapped_addr & PAGE_MASK); area = find_vm_area(remapped_addr); |