diff options
Diffstat (limited to 'arch/arm')
57 files changed, 2136 insertions, 301 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 863f2cd9096a..83082a5790d8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -641,6 +641,7 @@ config ARCH_QCOM select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select GENERIC_ALLOCATOR + select ARM_GIC select ARM_PATCH_PHYS_VIRT select ARM_HAS_SG_CHAIN select ARCH_HAS_OPP diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index b87d5d924238..815018770fb9 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -173,10 +173,9 @@ choice mobile SoCs in the Kona family of chips (e.g. bcm28155, bcm11351, etc...) - config DEBUG_BCM63XX + config DEBUG_BCM63XX_UART bool "Kernel low-level debugging on BCM63XX UART" depends on ARCH_BCM_63XX - select DEBUG_UART_BCM63XX config DEBUG_BERLIN_UART bool "Marvell Berlin SoC Debug UART" @@ -1359,7 +1358,7 @@ config DEBUG_LL_INCLUDE default "debug/vf.S" if DEBUG_VF_UART default "debug/vt8500.S" if DEBUG_VT8500_UART0 default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 - default "debug/bcm63xx.S" if DEBUG_UART_BCM63XX + default "debug/bcm63xx.S" if DEBUG_BCM63XX_UART default "debug/digicolor.S" if DEBUG_DIGICOLOR_UA0 default "mach/debug-macro.S" @@ -1375,10 +1374,6 @@ config DEBUG_UART_8250 ARCH_IOP33X || ARCH_IXP4XX || \ ARCH_LPC32XX || ARCH_MV78XX0 || ARCH_ORION5X || ARCH_RPC -# Compatibility options for BCM63xx -config DEBUG_UART_BCM63XX - def_bool ARCH_BCM_63XX - config DEBUG_UART_PHYS hex "Physical base address of debug UART" default 0x00100a00 if DEBUG_NETX_UART @@ -1473,7 +1468,7 @@ config DEBUG_UART_PHYS default 0xfffb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 default 0xfffb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 default 0xfffb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 - default 0xfffe8600 if DEBUG_UART_BCM63XX + default 0xfffe8600 if DEBUG_BCM63XX_UART default 0xfffff700 if ARCH_IOP33X depends on ARCH_EP93XX || \ DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ @@ -1485,7 +1480,7 @@ config DEBUG_UART_PHYS DEBUG_RCAR_GEN2_SCIF0 || DEBUG_RCAR_GEN2_SCIF2 || \ DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \ DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \ - DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART || \ + DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \ DEBUG_AT91_UART @@ -1526,7 +1521,7 @@ config DEBUG_UART_VIRT default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT default 0xfc40ab00 if DEBUG_BRCMSTB_UART default 0xfc705000 if DEBUG_ZTE_ZX - default 0xfcfe8600 if DEBUG_UART_BCM63XX + default 0xfcfe8600 if DEBUG_BCM63XX_UART default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX default 0xfd000000 if ARCH_SPEAR13XX default 0xfd012000 if ARCH_MV78XX0 @@ -1577,7 +1572,7 @@ config DEBUG_UART_VIRT DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ DEBUG_NETX_UART || \ DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \ - DEBUG_UART_BCM63XX || DEBUG_ASM9260_UART || \ + DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 config DEBUG_UART_8250_SHIFT diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index 23fc670c0427..5c21b236721f 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -70,8 +70,8 @@ soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000 - MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>; + MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index f774101416a5..ebe1d267406d 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -76,8 +76,8 @@ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000 - MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000 - MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>; + MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; devbus-bootcs { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 4878d7353069..5730b875c4f5 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -95,8 +95,8 @@ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000 - MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000 - MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>; + MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; devbus-bootcs { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts index 58b500873bfd..d960fef77ca1 100644 --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts @@ -65,8 +65,8 @@ soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000 - MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>; + MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 6e9820e141f8..b89e6cf1271a 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -70,8 +70,8 @@ soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000 - MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>; + MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts index 6ab33837a2b6..6522b04f4a8e 100644 --- a/arch/arm/boot/dts/armada-xp-matrix.dts +++ b/arch/arm/boot/dts/armada-xp-matrix.dts @@ -68,8 +68,8 @@ soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000 - MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>; + MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; internal-regs { serial@12000 { diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index 6fe8972de0a2..db54c7158a36 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -64,8 +64,8 @@ soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000 - MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>; + MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index a5db17782e08..853bd392a4fe 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -65,9 +65,9 @@ soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000 - MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000 - MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>; + MBUS_ID(0x01, 0x2f) 0 0 0xe8000000 0x8000000 + MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; devbus-bootcs { status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts index 2391b11dc546..d17dab0a6f51 100644 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -78,8 +78,8 @@ soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 - MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000 - MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>; + MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; pcie-controller { status = "okay"; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index fe99231cbde5..c2a03c740e79 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1497,6 +1497,16 @@ 0x48485200 0x2E00>; #address-cells = <1>; #size-cells = <1>; + + /* + * Do not allow gating of cpsw clock as workaround + * for errata i877. Keeping internal clock disabled + * causes the device switching characteristics + * to degrade over time and eventually fail to meet + * the data manual delay time/skew specs. + */ + ti,no-idle; + /* * rx_thresh_pend * rx_pend diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index dd955be6c908..a42019b58897 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -116,7 +116,8 @@ dtb-$(CONFIG_ARCH_MSMCOBALT) += msmcobalt-sim.dtb \ dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb -dtb-$(CONFIG_ARCH_MSMFALCON) += msmfalcon-sim.dtb +dtb-$(CONFIG_ARCH_MSMFALCON) += msmfalcon-sim.dtb \ + msmfalcon-rumi.dtb ifeq ($(CONFIG_ARM64),y) always := $(dtb-y) diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi new file mode 100644 index 000000000000..28b0d6d9cf14 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi @@ -0,0 +1,225 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_nt35597_truly_cmd: qcom,mdss_dsi_nt35597_truly_wqxga_cmd{ + qcom,mdss-dsi-panel-name = + "Dual nt35597 cmd mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = [cd 32 22 00 60 64 26 34 29 03 + 04 00]; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,ulps-enabled; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 10 00 02 FF 20 + 15 01 00 00 10 00 02 fb 01 + 15 01 00 00 10 00 02 00 01 + 15 01 00 00 10 00 02 01 55 + 15 01 00 00 10 00 02 02 45 + 15 01 00 00 10 00 02 05 40 + 15 01 00 00 10 00 02 06 19 + 15 01 00 00 10 00 02 07 1E + 15 01 00 00 10 00 02 0B 73 + 15 01 00 00 10 00 02 0C 73 + 15 01 00 00 10 00 02 0E B0 + 15 01 00 00 10 00 02 0F AE + 15 01 00 00 10 00 02 11 B8 + 15 01 00 00 10 00 02 13 00 + 15 01 00 00 10 00 02 58 80 + 15 01 00 00 10 00 02 59 01 + 15 01 00 00 10 00 02 5A 00 + 15 01 00 00 10 00 02 5B 01 + 15 01 00 00 10 00 02 5C 80 + 15 01 00 00 10 00 02 5D 81 + 15 01 00 00 10 00 02 5E 00 + 15 01 00 00 10 00 02 5F 01 + 15 01 00 00 10 00 02 72 31 + 15 01 00 00 10 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 10 00 02 ff 24 + 15 01 00 00 10 00 02 fb 01 + 15 01 00 00 10 00 02 00 1C + 15 01 00 00 10 00 02 01 0B + 15 01 00 00 10 00 02 02 0C + 15 01 00 00 10 00 02 03 01 + 15 01 00 00 10 00 02 04 0F + 15 01 00 00 10 00 02 05 10 + 15 01 00 00 10 00 02 06 10 + 15 01 00 00 10 00 02 07 10 + 15 01 00 00 10 00 02 08 89 + 15 01 00 00 10 00 02 09 8A + 15 01 00 00 10 00 02 0A 13 + 15 01 00 00 10 00 02 0B 13 + 15 01 00 00 10 00 02 0C 15 + 15 01 00 00 10 00 02 0D 15 + 15 01 00 00 10 00 02 0E 17 + 15 01 00 00 10 00 02 0F 17 + 15 01 00 00 10 00 02 10 1C + 15 01 00 00 10 00 02 11 0B + 15 01 00 00 10 00 02 12 0C + 15 01 00 00 10 00 02 13 01 + 15 01 00 00 10 00 02 14 0F + 15 01 00 00 10 00 02 15 10 + 15 01 00 00 10 00 02 16 10 + 15 01 00 00 10 00 02 17 10 + 15 01 00 00 10 00 02 18 89 + 15 01 00 00 10 00 02 19 8A + 15 01 00 00 10 00 02 1A 13 + 15 01 00 00 10 00 02 1B 13 + 15 01 00 00 10 00 02 1C 15 + 15 01 00 00 10 00 02 1D 15 + 15 01 00 00 10 00 02 1E 17 + 15 01 00 00 10 00 02 1F 17 + /* STV */ + 15 01 00 00 10 00 02 20 40 + 15 01 00 00 10 00 02 21 01 + 15 01 00 00 10 00 02 22 00 + 15 01 00 00 10 00 02 23 40 + 15 01 00 00 10 00 02 24 40 + 15 01 00 00 10 00 02 25 6D + 15 01 00 00 10 00 02 26 40 + 15 01 00 00 10 00 02 27 40 + /* Vend */ + 15 01 00 00 10 00 02 E0 00 + 15 01 00 00 10 00 02 DC 21 + 15 01 00 00 10 00 02 DD 22 + 15 01 00 00 10 00 02 DE 07 + 15 01 00 00 10 00 02 DF 07 + 15 01 00 00 10 00 02 E3 6D + 15 01 00 00 10 00 02 E1 07 + 15 01 00 00 10 00 02 E2 07 + /* UD */ + 15 01 00 00 10 00 02 29 D8 + 15 01 00 00 10 00 02 2A 2A + /* CLK */ + 15 01 00 00 10 00 02 4B 03 + 15 01 00 00 10 00 02 4C 11 + 15 01 00 00 10 00 02 4D 10 + 15 01 00 00 10 00 02 4E 01 + 15 01 00 00 10 00 02 4F 01 + 15 01 00 00 10 00 02 50 10 + 15 01 00 00 10 00 02 51 00 + 15 01 00 00 10 00 02 52 80 + 15 01 00 00 10 00 02 53 00 + 15 01 00 00 10 00 02 56 00 + 15 01 00 00 10 00 02 54 07 + 15 01 00 00 10 00 02 58 07 + 15 01 00 00 10 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 10 00 02 5B 43 + 15 01 00 00 10 00 02 5C 00 + 15 01 00 00 10 00 02 5F 73 + 15 01 00 00 10 00 02 60 73 + 15 01 00 00 10 00 02 63 22 + 15 01 00 00 10 00 02 64 00 + 15 01 00 00 10 00 02 67 08 + 15 01 00 00 10 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 10 00 02 72 02 + /* mux */ + 15 01 00 00 10 00 02 7A 80 + 15 01 00 00 10 00 02 7B 91 + 15 01 00 00 10 00 02 7C D8 + 15 01 00 00 10 00 02 7D 60 + 15 01 00 00 10 00 02 7F 15 + 15 01 00 00 10 00 02 75 15 + /* ABOFF */ + 15 01 00 00 10 00 02 B3 C0 + 15 01 00 00 10 00 02 B4 00 + 15 01 00 00 10 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 10 00 02 78 00 + 15 01 00 00 10 00 02 79 00 + 15 01 00 00 10 00 02 80 00 + 15 01 00 00 10 00 02 83 00 + /* FP BP */ + 15 01 00 00 10 00 02 93 0A + 15 01 00 00 10 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 10 00 02 8A 00 + 15 01 00 00 10 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 10 00 02 9D B0 + 15 01 00 00 10 00 02 9F 63 + 15 01 00 00 10 00 02 98 10 + /* FRM */ + 15 01 00 00 10 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 10 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 10 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 10 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 10 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 10 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 10 00 02 FB 01 + /* SlpOut + DispOn */ + 05 01 00 00 a0 00 02 11 00 + 05 01 00 00 a0 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,config-select = <&dsi_dual_nt35597_truly_cmd_config0>; + + dsi_dual_nt35597_truly_cmd_config0: config0 { + qcom,split-mode = "dualctl-split"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi new file mode 100644 index 000000000000..d125a5783f9e --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi @@ -0,0 +1,213 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_nt35597_truly_video: qcom,mdss_dsi_nt35597_wqxga_video_truly { + qcom,mdss-dsi-panel-name = + "Dual nt35597 video mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 10 00 02 FF 20 + 15 01 00 00 10 00 02 FB 01 + 15 01 00 00 10 00 02 00 01 + 15 01 00 00 10 00 02 01 55 + 15 01 00 00 10 00 02 02 45 + 15 01 00 00 10 00 02 05 40 + 15 01 00 00 10 00 02 06 19 + 15 01 00 00 10 00 02 07 1E + 15 01 00 00 10 00 02 0B 73 + 15 01 00 00 10 00 02 0C 73 + 15 01 00 00 10 00 02 0E B0 + 15 01 00 00 10 00 02 0F AE + 15 01 00 00 10 00 02 11 B8 + 15 01 00 00 10 00 02 13 00 + 15 01 00 00 10 00 02 58 80 + 15 01 00 00 10 00 02 59 01 + 15 01 00 00 10 00 02 5A 00 + 15 01 00 00 10 00 02 5B 01 + 15 01 00 00 10 00 02 5C 80 + 15 01 00 00 10 00 02 5D 81 + 15 01 00 00 10 00 02 5E 00 + 15 01 00 00 10 00 02 5F 01 + 15 01 00 00 10 00 02 72 31 + 15 01 00 00 10 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 10 00 02 FF 24 + 15 01 00 00 10 00 02 FB 01 + 15 01 00 00 10 00 02 00 1C + 15 01 00 00 10 00 02 01 0B + 15 01 00 00 10 00 02 02 0C + 15 01 00 00 10 00 02 03 01 + 15 01 00 00 10 00 02 04 0F + 15 01 00 00 10 00 02 05 10 + 15 01 00 00 10 00 02 06 10 + 15 01 00 00 10 00 02 07 10 + 15 01 00 00 10 00 02 08 89 + 15 01 00 00 10 00 02 09 8A + 15 01 00 00 10 00 02 0A 13 + 15 01 00 00 10 00 02 0B 13 + 15 01 00 00 10 00 02 0C 15 + 15 01 00 00 10 00 02 0D 15 + 15 01 00 00 10 00 02 0E 17 + 15 01 00 00 10 00 02 0F 17 + 15 01 00 00 10 00 02 10 1C + 15 01 00 00 10 00 02 11 0B + 15 01 00 00 10 00 02 12 0C + 15 01 00 00 10 00 02 13 01 + 15 01 00 00 10 00 02 14 0F + 15 01 00 00 10 00 02 15 10 + 15 01 00 00 10 00 02 16 10 + 15 01 00 00 10 00 02 17 10 + 15 01 00 00 10 00 02 18 89 + 15 01 00 00 10 00 02 19 8A + 15 01 00 00 10 00 02 1A 13 + 15 01 00 00 10 00 02 1B 13 + 15 01 00 00 10 00 02 1C 15 + 15 01 00 00 10 00 02 1D 15 + 15 01 00 00 10 00 02 1E 17 + 15 01 00 00 10 00 02 1F 17 + /* STV */ + 15 01 00 00 10 00 02 20 40 + 15 01 00 00 10 00 02 21 01 + 15 01 00 00 10 00 02 22 00 + 15 01 00 00 10 00 02 23 40 + 15 01 00 00 10 00 02 24 40 + 15 01 00 00 10 00 02 25 6D + 15 01 00 00 10 00 02 26 40 + 15 01 00 00 10 00 02 27 40 + /* Vend */ + 15 01 00 00 10 00 02 E0 00 + 15 01 00 00 10 00 02 DC 21 + 15 01 00 00 10 00 02 DD 22 + 15 01 00 00 10 00 02 DE 07 + 15 01 00 00 10 00 02 DF 07 + 15 01 00 00 10 00 02 E3 6D + 15 01 00 00 10 00 02 E1 07 + 15 01 00 00 10 00 02 E2 07 + /* UD */ + 15 01 00 00 10 00 02 29 D8 + 15 01 00 00 10 00 02 2A 2A + /* CLK */ + 15 01 00 00 10 00 02 4B 03 + 15 01 00 00 10 00 02 4C 11 + 15 01 00 00 10 00 02 4D 10 + 15 01 00 00 10 00 02 4E 01 + 15 01 00 00 10 00 02 4F 01 + 15 01 00 00 10 00 02 50 10 + 15 01 00 00 10 00 02 51 00 + 15 01 00 00 10 00 02 52 80 + 15 01 00 00 10 00 02 53 00 + 15 01 00 00 10 00 02 56 00 + 15 01 00 00 10 00 02 54 07 + 15 01 00 00 10 00 02 58 07 + 15 01 00 00 10 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 10 00 02 5B 43 + 15 01 00 00 10 00 02 5C 00 + 15 01 00 00 10 00 02 5F 73 + 15 01 00 00 10 00 02 60 73 + 15 01 00 00 10 00 02 63 22 + 15 01 00 00 10 00 02 64 00 + 15 01 00 00 10 00 02 67 08 + 15 01 00 00 10 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 10 00 02 72 02 + /* mux */ + 15 01 00 00 10 00 02 7A 80 + 15 01 00 00 10 00 02 7B 91 + 15 01 00 00 10 00 02 7C D8 + 15 01 00 00 10 00 02 7D 60 + 15 01 00 00 10 00 02 7F 15 + 15 01 00 00 10 00 02 75 15 + /* ABOFF */ + 15 01 00 00 10 00 02 B3 C0 + 15 01 00 00 10 00 02 B4 00 + 15 01 00 00 10 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 10 00 02 78 00 + 15 01 00 00 10 00 02 79 00 + 15 01 00 00 10 00 02 80 00 + 15 01 00 00 10 00 02 83 00 + /* FP BP */ + 15 01 00 00 10 00 02 93 0A + 15 01 00 00 10 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 10 00 02 8A 00 + 15 01 00 00 10 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 10 00 02 9D B0 + 15 01 00 00 10 00 02 9F 63 + 15 01 00 00 10 00 02 98 10 + /* FRM */ + 15 01 00 00 10 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 10 00 02 FF 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 10 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 10 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 10 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 10 00 02 BB 03 + /* Non Reload MTP */ + 15 01 00 00 10 00 02 FB 01 + /* SlpOut + DispOn */ + 05 01 00 00 a0 00 02 11 00 + 05 01 00 00 a0 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-panel-timings = [e2 36 24 00 66 6a 28 38 2a 03 + 04 00]; + qcom,mdss-dsi-t-clk-post = <0x0d>; + qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>; + + qcom,config-select = <&dsi_dual_nt35597_truly_video_config0>; + + dsi_dual_nt35597_truly_video_config0: config0 { + qcom,split-mode = "dualctl-split"; + }; + + + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi index 41af9b66d3c9..ab46221089f3 100644 --- a/arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi @@ -23,16 +23,16 @@ qcom,register-save; qcom,skip-init; #global-interrupts = <2>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>; clocks = <&clock_gcc clk_aggre1_noc_clk>; clock-names = "smmu_aggre1_noc_clk"; #clock-cells = <1>; @@ -46,28 +46,28 @@ qcom,register-save; qcom,skip-init; #global-interrupts = <2>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 353 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 358 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; clocks = <&clock_gcc clk_aggre2_noc_clk>; clock-names = "smmu_aggre2_noc_clk"; #clock-cells = <1>; @@ -113,6 +113,7 @@ reg = <0xcd00000 0x40000>; #iommu-cells = <1>; qcom,register-save; + qcom,no-smr-check; qcom,skip-init; #global-interrupts = <2>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, @@ -164,14 +165,14 @@ qcom,register-save; qcom,skip-init; #global-interrupts = <2>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>; vdd-supply = <&gdsc_gpu_cx>; clocks = <&clock_gcc clk_gcc_gpu_cfg_ahb_clk>, <&clock_gcc clk_gcc_bimc_gfx_clk>, diff --git a/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi b/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi index ab6b614471e5..6729899379c5 100644 --- a/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi +++ b/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi @@ -51,7 +51,6 @@ voice: qcom,msm-pcm-voice { compatible = "qcom,msm-pcm-voice"; qcom,destroy-cvd; - qcom,vote-bms; }; stub_codec: qcom,msm-stub-codec { diff --git a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi b/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi index b612ec3f42b5..fad834199be5 100644 --- a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi @@ -383,7 +383,6 @@ qcom,supported-sizes = <6>, <9>; qcom,ramp-index = <2>; #pwm-cells = <2>; - status = "disabled"; }; pmicobalt_pwm_4: pwm@b400 { @@ -396,7 +395,6 @@ qcom,supported-sizes = <6>, <9>; qcom,ramp-index = <3>; #pwm-cells = <2>; - status = "disabled"; }; pmicobalt_pwm_5: pwm@b500 { @@ -409,7 +407,6 @@ qcom,supported-sizes = <6>, <9>; qcom,ramp-index = <4>; #pwm-cells = <2>; - status = "disabled"; }; pmicobalt_pwm_6: pwm@b600 { @@ -425,6 +422,50 @@ status = "disabled"; }; + qcom,leds@d000 { + compatible = "qcom,leds-qpnp"; + reg = <0xd000 0x100>; + label = "rgb"; + status = "okay"; + + red_led: qcom,rgb_0 { + label = "rgb"; + qcom,id = <3>; + qcom,mode = "pwm"; + pwms = <&pmicobalt_pwm_5 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "red"; + linux,default-trigger = + "battery-charging"; + }; + + green_led: qcom,rgb_1 { + label = "rgb"; + qcom,id = <4>; + qcom,mode = "pwm"; + pwms = <&pmicobalt_pwm_4 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "green"; + linux,default-trigger = "battery-full"; + }; + + blue_led: qcom,rgb_2 { + label = "rgb"; + qcom,id = <5>; + qcom,mode = "pwm"; + pwms = <&pmicobalt_pwm_3 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "blue"; + linux,default-trigger = "boot-indication"; + }; + }; + labibb: qpnp-labibb-regulator { compatible = "qcom,qpnp-labibb-regulator"; #address-cells = <1>; @@ -565,9 +606,9 @@ label = "flash"; qcom,led-name = "led:flash_0"; qcom,max-current = <1500>; - qcom,default-led-trigger = - "flash0_trigger"; + qcom,default-led-trigger = "flash0_trigger"; qcom,id = <0>; + qcom,current-ma = <1000>; qcom,duration-ms = <1280>; qcom,ires-ua = <12500>; qcom,hdrm-voltage-mv = <325>; @@ -578,9 +619,9 @@ label = "flash"; qcom,led-name = "led:flash_1"; qcom,max-current = <1500>; - qcom,default-led-trigger = - "flash1_trigger"; + qcom,default-led-trigger = "flash1_trigger"; qcom,id = <1>; + qcom,current-ma = <1000>; qcom,duration-ms = <1280>; qcom,ires-ua = <12500>; qcom,hdrm-voltage-mv = <325>; @@ -591,9 +632,9 @@ label = "flash"; qcom,led-name = "led:flash_2"; qcom,max-current = <750>; - qcom,default-led-trigger = - "flash2_trigger"; + qcom,default-led-trigger = "flash2_trigger"; qcom,id = <2>; + qcom,current-ma = <500>; qcom,duration-ms = <1280>; qcom,ires-ua = <12500>; qcom,hdrm-voltage-mv = <325>; @@ -603,11 +644,65 @@ pinctrl-1 = <&led_disable>; }; - pmicobalt_switch: qcom,led_switch { + pmicobalt_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmicobalt_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pmicobalt_torch2: qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + pinctrl-names = "led_enable","led_disable"; + pinctrl-0 = <&led_enable>; + pinctrl-1 = <&led_disable>; + }; + + pmicobalt_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; + reg0 { + regulator-name = "pmicobalt_bob"; + max-voltage-uv = <3600000>; + }; + }; + + pmicobalt_switch1: qcom,led_switch_1 { label = "switch"; - qcom,led-name = "led:switch"; - qcom,default-led-trigger = - "switch_trigger"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <4>; + qcom,default-led-trigger = "switch1_trigger"; + reg0 { + regulator-name = "pmicobalt_bob"; + max-voltage-uv = <3600000>; + }; }; }; }; diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi index d81cc3dd14d8..2da89bd9ac6e 100644 --- a/arch/arm/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996.dtsi @@ -42,7 +42,7 @@ chosen { stdout-path = "serial0"; - bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1"; + bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1 rcupdate.rcu_expedited=1"; }; psci { diff --git a/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi index ae878c7f5bac..1ef5e6351aa6 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi @@ -30,6 +30,7 @@ sound-9335 { compatible = "qcom,msmcobalt-asoc-snd-tasha"; qcom,model = "msmcobalt-tasha-snd-card"; + qcom,hdmi-audio-rx; qcom,audio-routing = "AIF4 VI", "MCLK", @@ -98,8 +99,9 @@ "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673"; - asoc-codec = <&stub_codec>; - asoc-codec-names = "msm-stub-codec.1"; + asoc-codec = <&stub_codec>, <&hdmi_audio>; + asoc-codec-names = "msm-stub-codec.1", + "msm-hdmi-audio-codec-rx"; qcom,wsa-max-devs = <2>; qcom,wsa-devs = <&wsa881x_211>, <&wsa881x_212>, <&wsa881x_213>, <&wsa881x_214>; @@ -107,6 +109,78 @@ "SpkrLeft", "SpkrRight"; }; + sound-tavil { + compatible = "qcom,msmcobalt-asoc-snd-tavil"; + qcom,model = "msmcobalt-tavil-snd-card"; + + qcom,audio-routing = + "RX_BIAS", "MCLK", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; + qcom,tavil-mclk-clk-freq = <9600000>; + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>, + <&loopback>, <&compress>, <&hostless>, + <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-pcm-dsp.2", "msm-voip-dsp", + "msm-pcm-voice", "msm-pcm-loopback", + "msm-compress-dsp", "msm-pcm-hostless", + "msm-pcm-afe", "msm-lsm-client", + "msm-pcm-routing", "msm-cpe-lsm", + "msm-compr-dsp"; + asoc-cpu = <&dai_hdmi>, + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>, + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>, + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&incall_music_2_rx>, <&sb_5_rx>, + <&usb_audio_rx>, <&usb_audio_tx>; + asoc-cpu-names = "msm-dai-q6-hdmi.8", + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385", + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387", + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389", + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391", + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393", + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673"; + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + }; + cpe: qcom,msm-cpe-lsm { compatible = "qcom,msm-cpe-lsm"; }; @@ -139,6 +213,15 @@ #clock-cells = <1>; }; + clock_audio_lnbb: audio_ext_clk_lnbb { + status = "ok"; + compatible = "qcom,audio-ref-clk"; + clock-names = "osr_clk"; + clocks = <&clock_gcc clk_ln_bb_clk2>; + qcom,node_has_rpm_clock; + #clock-cells = <1>; + }; + wcd_rst_gpio: msm_cdc_pinctrl@64 { compatible = "qcom,msm-cdc-pinctrl"; qcom,cdc-rst-n-gpio = <&tlmm 64 0>; @@ -206,4 +289,56 @@ qcom,cdc-dmic-sample-rate = <4800000>; qcom,cdc-mad-dmic-rate = <600000>; }; + + tavil_codec { + compatible = "qcom,tavil-slim-pgd"; + elemental-addr = [00 01 50 02 17 02]; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio_lnbb clk_audio_pmi_lnbb_clk>; + + cdc-vdd-buck-supply = <&pmcobalt_s4>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&pmcobalt_s4>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <250000>; + + cdc-vdd-tx-h-supply = <&pmcobalt_s4>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pmcobalt_s4>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pmcobalt_s4>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-slim-ifd = "tavil-slim-ifd"; + qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02]; + qcom,cdc-dmic-sample-rate = <4800000>; + qcom,cdc-mad-dmic-rate = <600000>; + }; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-bus.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-bus.dtsi index 4eb242fc1140..86decf438430 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-bus.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-bus.dtsi @@ -114,13 +114,9 @@ fab_gnoc: fab-gnoc { cell-id = <MSM_BUS_FAB_GNOC>; label = "fab-gnoc"; - qcom,fab-dev; qcom,virt-dev; qcom,base-name = "gnoc-base"; qcom,bypass-qos-prg; - clock-names = "bus_clk", "bus_a_clk"; - clocks = <&clock_gcc clk_bimc_msmbus_clk>, - <&clock_gcc clk_bimc_msmbus_a_clk>; }; fab_mnoc: fab-mnoc { @@ -135,6 +131,16 @@ clock-names = "bus_clk", "bus_a_clk"; clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_gcc clk_mmssnoc_axi_a_clk>; + clk-mdss-axi-no-rate-supply = + <&gdsc_mdss>; + clk-mdss-ahb-no-rate-supply = + <&gdsc_mdss>; + clk-camss-ahb-no-rate-supply = + <&gdsc_camss_top>; + clk-video-ahb-no-rate-supply = + <&gdsc_venus>; + clk-video-axi-no-rate-supply = + <&gdsc_venus>; qcom,node-qos-clks { clock-names = "clk-noc-cfg-ahb-no-rate", @@ -145,6 +151,7 @@ "clk-video-ahb-no-rate", "clk-video-axi-no-rate"; clocks = + <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_gcc clk_gcc_mmss_noc_cfg_ahb_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_mdss_ahb_clk>, @@ -1450,7 +1457,6 @@ devfreq_spdm_gov { compatible = "qcom,gov_spdm_hyp"; interrupt-names = "spdm-irq"; - interrupt-edge; - interrupts = <0 192 0>; + interrupts = <0 192 IRQ_TYPE_EDGE_RISING>; }; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-cdp.dtsi index 83b55da92fa2..3ed038069319 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-cdp.dtsi @@ -16,7 +16,7 @@ cell-index = <0>; compatible = "qcom,camera-flash"; qcom,flash-source = <&pmicobalt_flash0 &pmicobalt_flash1>; - qcom,switch-source = <&pmicobalt_switch>; + qcom,switch-source = <&pmicobalt_switch0>; status = "ok"; }; @@ -24,7 +24,7 @@ cell-index = <1>; compatible = "qcom,camera-flash"; qcom,flash-source = <&pmicobalt_flash2>; - qcom,switch-source = <&pmicobalt_switch>; + qcom,switch-source = <&pmicobalt_switch1>; status = "ok"; }; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-mtp.dtsi index 83b55da92fa2..d152c0049f96 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-mtp.dtsi @@ -16,7 +16,7 @@ cell-index = <0>; compatible = "qcom,camera-flash"; qcom,flash-source = <&pmicobalt_flash0 &pmicobalt_flash1>; - qcom,switch-source = <&pmicobalt_switch>; + qcom,switch-source = <&pmicobalt_switch0>; status = "ok"; }; @@ -24,7 +24,7 @@ cell-index = <1>; compatible = "qcom,camera-flash"; qcom,flash-source = <&pmicobalt_flash2>; - qcom,switch-source = <&pmicobalt_switch>; + qcom,switch-source = <&pmicobalt_switch1>; status = "ok"; }; }; @@ -198,7 +198,7 @@ reg = <0x0>; qcom,csiphy-sd-index = <0>; qcom,csid-sd-index = <0>; - qcom,mount-angle = <90>; + qcom,mount-angle = <270>; qcom,led-flash-src = <&led_flash0>; qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi index 2d0c674eaba8..b9626cd61553 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi @@ -254,6 +254,22 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; }; +&dsi_dual_nt35597_truly_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + &dsi_nt35597_dsc_video { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; qcom,mdss-dsi-bl-min-level = <1>; @@ -284,6 +300,22 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; }; +&dsi_dual_jdi_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,5v-boost-gpio = <&tlmm 51 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_jdi_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,5v-boost-gpio = <&tlmm 51 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + &mdss_hdmi_tx { pinctrl-names = "hdmi_hpd_active", "hdmi_ddc_active", "hdmi_cec_active", "hdmi_active", "hdmi_sleep"; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi index 7a12053bef70..6ab19b298aa7 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi @@ -67,11 +67,12 @@ qcom,initial-pwrlevel = <4>; qcom,idle-timeout = <80>; //<HZ/12> + qcom,no-nap; /* * Timeout to enter deeper power saving state * from NAP. */ - qcom,deep-nap-timeout = <2>; //<HZ/50> + qcom,deep-nap-timeout = <200>; qcom,strtstp-sleepwake; qcom,highest-bank-bit = <15>; @@ -91,6 +92,7 @@ "mem_clk", "mem_iface_clk", "isense_clk", "rbcpr_clk", "iref_clk"; + qcom,isense-clk-on-level = <1>; /* Bus Scale Settings */ qcom,gpubw-dev = <&gpubw>; qcom,bus-control; @@ -128,9 +130,9 @@ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <504000000>; - qcom,bus-freq = <11>; - qcom,bus-min = <10>; + qcom,gpu-freq = <650000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <11>; qcom,bus-max = <12>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi index 4953886f03b8..fc6c4d2eadd7 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi @@ -14,10 +14,14 @@ #include "dsi-panel-sim-dualmipi-video.dtsi" #include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi" #include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" +#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" #include "dsi-panel-nt35597-dsc-wqxga-video.dtsi" #include "dsi-panel-nt35597-dsc-wqxga-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-jdi-dualmipi-video.dtsi" +#include "dsi-panel-jdi-dualmipi-cmd.dtsi" &soc { dsi_panel_pwr_supply: dsi_panel_pwr_supply { @@ -74,6 +78,8 @@ qcom,mdss-dsi-panel-timings = [00 1a 04 06 0a 0a 05 06 05 03 04 00]; qcom,mdss-dsi-t-clk-post = <0x0d>; qcom,mdss-dsi-t-clk-pre = <0x2d>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "bta_check"; }; &dsi_dual_nt35597_cmd { @@ -82,6 +88,18 @@ qcom,mdss-dsi-t-clk-pre = <0x2d>; }; +&dsi_dual_nt35597_truly_video { + qcom,mdss-dsi-panel-timings = [00 1a 04 06 0a 0a 05 06 05 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x07>; + qcom,mdss-dsi-t-clk-pre = <0x25>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,mdss-dsi-panel-timings = [00 1a 04 06 0a 0a 05 06 05 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x07>; + qcom,mdss-dsi-t-clk-pre = <0x25>; +}; + &dsi_nt35597_dsc_video { qcom,mdss-dsi-panel-timings = [00 12 03 04 07 07 04 04 03 03 04 00]; qcom,mdss-dsi-t-clk-post = <0x0b>; @@ -105,3 +123,15 @@ qcom,mdss-dsi-t-clk-post = <0x0d>; qcom,mdss-dsi-t-clk-pre = <0x25>; }; + +&dsi_dual_jdi_video { + qcom,mdss-dsi-panel-timings = [00 18 04 05 09 0a 05 06 04 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x06>; + qcom,mdss-dsi-t-clk-pre = <0x22>; +}; + +&dsi_dual_jdi_cmd { + qcom,mdss-dsi-panel-timings = [00 18 04 05 09 0a 05 06 04 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x06>; + qcom,mdss-dsi-t-clk-pre = <0x22>; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi index b2f22572dcc8..3018ecd4e5eb 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi @@ -521,15 +521,16 @@ qcom,enable-load = <0>; qcom,disable-load = <0>; - clocks = <&clock_mmss clk_mmss_mdss_mdp_clk>, - <&clock_mmss clk_mmss_mnoc_ahb_clk>, + clocks = <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_mdss_ahb_clk>, <&clock_mmss clk_mmss_mdss_hdmi_clk>, + <&clock_mmss clk_mmss_mdss_mdp_clk>, <&clock_mmss clk_mmss_mdss_hdmi_dp_ahb_clk>, <&clock_mmss clk_mmss_mdss_extpclk_clk>; - clock-names = "mdp_core_clk", "mnoc_clk", "iface_clk", - "core_clk", "alt_iface_clk", "extp_clk"; + clock-names = "hpd_mnoc_clk", "hpd_iface_clk", + "hpd_core_clk", "hpd_mdp_core_clk", + "hpd_alt_iface_clk", "core_extp_clk"; qcom,mdss-fb-map = <&mdss_fb2>; qcom,pluggable; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi index c9af303b3738..6833bd1d7f4a 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi @@ -270,6 +270,22 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; }; +&dsi_dual_nt35597_truly_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_nt35597_truly_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + &dsi_nt35597_dsc_video { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; qcom,mdss-dsi-bl-min-level = <1>; @@ -300,6 +316,22 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; }; +&dsi_dual_jdi_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,5v-boost-gpio = <&tlmm 51 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + +&dsi_dual_jdi_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,5v-boost-gpio = <&tlmm 51 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; +}; + &i2c_7 { status = "okay"; qcom,smb138x@8 { diff --git a/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi index fdcda8765a22..1094d96bd100 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi @@ -1375,24 +1375,24 @@ pmx_mdss: pmx_mdss { mdss_dsi_active: mdss_dsi_active { mux { - pins = "gpio94", "gpio91"; + pins = "gpio94", "gpio91", "gpio51"; function = "gpio"; }; config { - pins = "gpio94", "gpio91"; + pins = "gpio94", "gpio91", "gpio51"; drive-strength = <8>; /* 8 mA */ bias-disable = <0>; /* no pull */ }; }; mdss_dsi_suspend: mdss_dsi_suspend { mux { - pins = "gpio94", "gpio91"; + pins = "gpio94", "gpio91", "gpio51"; function = "gpio"; }; config { - pins = "gpio94", "gpio91"; + pins = "gpio94", "gpio91", "gpio51"; drive-strength = <2>; /* 2 mA */ bias-pull-down; /* pull down */ }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-pm.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-pm.dtsi index 73f612516f84..b5d3a85f9b15 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-pm.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-pm.dtsi @@ -382,7 +382,13 @@ <0xff 324>, /* lpass_qca_slimbus_bam_ee1_irq */ <0xff 432>, /* smmu_Cirpt[8] */ <0xff 433>, /* smmu_Cirpt[9] */ - <0xff 461>; /* o_ocimem_nonsec_irq */ + <0xff 461>, /* o_ocimem_nonsec_irq */ + <0xff 69>, /* o_pwr_dcvsh_interrupt */ + <0xff 70>, /* o_perf_dcvsh_interrupt */ + <0xff 166>, /* o_lm_int_2qgic */ + <0xff 238>, /* crypto_bam_irq[0] */ + <0xff 132>; /* qup_irq */ + qcom,gpio-parent = <&tlmm>; qcom,gpio-map = <3 1>, diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd.dts b/arch/arm/boot/dts/qcom/msmcobalt-qrd.dts index 9848d6da33a5..d95507b505c2 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd.dts +++ b/arch/arm/boot/dts/qcom/msmcobalt-qrd.dts @@ -14,7 +14,7 @@ /dts-v1/; #include "msmcobalt.dtsi" -#include "msmcobalt-mtp.dtsi" +#include "msmcobalt-qrd.dtsi" / { model = "Qualcomm Technologies, Inc. MSM COBALT QRD"; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-qrd.dtsi new file mode 100644 index 000000000000..1720aca3b298 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmcobalt-qrd.dtsi @@ -0,0 +1,13 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "msmcobalt-mtp.dtsi" diff --git a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi index 21dbb8143061..12ee61b34d8c 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi @@ -82,7 +82,7 @@ rpm-regulator-smpa5 { status = "okay"; pmcobalt_s5: regulator-s5 { - regulator-min-microvolt = <2040000>; + regulator-min-microvolt = <1904000>; regulator-max-microvolt = <2040000>; status = "okay"; }; @@ -91,7 +91,7 @@ rpm-regulator-smpa7 { status = "okay"; pmcobalt_s7: regulator-s7 { - regulator-min-microvolt = <1028000>; + regulator-min-microvolt = <900000>; regulator-max-microvolt = <1028000>; status = "okay"; }; @@ -149,6 +149,9 @@ pmcobalt_l1: regulator-l1 { regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; + proxy-supply = <&pmcobalt_l1>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <73400>; status = "okay"; }; }; @@ -158,6 +161,9 @@ pmcobalt_l2: regulator-l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + proxy-supply = <&pmcobalt_l2>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <12560>; status = "okay"; }; }; @@ -298,6 +304,9 @@ pmcobalt_l14: regulator-l14 { regulator-min-microvolt = <1880000>; regulator-max-microvolt = <1880000>; + proxy-supply = <&pmcobalt_l14>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <32000>; status = "okay"; }; }; @@ -533,45 +542,6 @@ /* Stub regulators */ / { - - /* PMCOBALT S10 = APC_0 supply */ - pmcobalt_s10: regulator-pmcobalt-s10 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmcobalt_s10"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <352000>; - regulator-max-microvolt = <952000>; - }; - - /* - * PMCOBALT S11 + S12 + S13 = 3 phase APC_1 supply - * S13 is the gang leader - */ - pmcobalt_s13: regulator-pmcobalt-s13 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmcobalt_s13"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <352000>; - regulator-max-microvolt = <952000>; - }; - - /* PM8005 S2 = VDD_MODEM supply */ - pm8005_s2: regulator-pm8005-s2 { - compatible = "qcom,stub-regulator"; - regulator-name = "pm8005_s2"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <352000>; - regulator-max-microvolt = <952000>; - }; - - pm8005_s3: regulator-pm8005-s3 { - compatible = "qcom,stub-regulator"; - regulator-name = "pm8005_s3"; - qcom,hpm-min-load = <100000>; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - }; - gfx_stub_vreg: regulator-gfx-stub { compatible = "qcom,stub-regulator"; regulator-name = "gfx_stub_corner"; @@ -901,23 +871,23 @@ qcom,cpr-open-loop-voltage-fuse-adjustment = <0 0 0 0>, - <0 0 0 20000>, - <0 0 0 20000>, - <0 0 0 20000>, - <0 0 0 20000>, - <0 0 0 20000>, - <0 0 0 20000>, - <0 0 0 20000>; + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>, + <8000 0 0 52000>; qcom,cpr-closed-loop-voltage-fuse-adjustment = <0 0 0 0>, - <1000 0 0 21000>, - <1000 0 0 21000>, - <1000 0 0 21000>, - <1000 0 0 21000>, - <1000 0 0 21000>, - <1000 0 0 21000>, - <1000 0 0 21000>; + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>, + <0 0 0 50000>; qcom,allow-voltage-interpolation; qcom,allow-quotient-interpolation; @@ -1040,35 +1010,35 @@ 1580 1602 2158 3042 2780 2069 0 0>; qcom,cpr-open-loop-voltage-fuse-adjustment = - < 0 0 0 0>, - < 0 0 0 0>, - < 0 0 0 0>, - < 0 0 0 0>, - < 0 0 0 0>, - < 0 0 0 0>, - < 0 0 0 0>, - < 0 0 0 0>; + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>, + < 72000 0 0 0>; qcom,cpr-closed-loop-voltage-adjustment = - < 150000 150000 150000 150000 - 150000 150000>, - < 150000 150000 150000 150000 - 150000 150000>, - < 150000 150000 150000 150000 - 150000 150000>, - < 150000 150000 150000 150000 - 150000 150000>, - < 150000 150000 150000 150000 - 150000 150000>, - < 150000 150000 150000 150000 - 150000 150000>, - < 150000 150000 150000 150000 - 150000 150000>, - < 150000 150000 150000 150000 - 150000 150000>; + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>, + < 65000 26000 8000 0 + 0 0>; qcom,cpr-floor-to-ceiling-max-range = - <50000 50000 50000 50000 50000 50000>; + <75000 75000 75000 75000 75000 75000>; qcom,cpr-fused-closed-loop-voltage-adjustment-map = <0 0 1 2 3 4>; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi index 20d38f5616cb..105a83b56056 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi @@ -277,3 +277,11 @@ &pmicobalt_charger { qcom,suspend-input; }; + +&tsens0 { + status = "disabled"; +}; + +&tsens1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi index 3b79cee0ae1e..4e6b1dd9211a 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi @@ -114,3 +114,11 @@ &pmicobalt_charger { qcom,suspend-input; }; + +&tsens0 { + status = "disabled"; +}; + +&tsens1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-wcd.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-wcd.dtsi new file mode 100644 index 000000000000..7ae084debe06 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmcobalt-wcd.dtsi @@ -0,0 +1,96 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&slim_aud { + tasha_codec { + wsa_spkr_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; + }; + + wsa_spkr_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-1 = <&spkr_2_sd_n_sleep>; + }; + }; + + tavil_codec { + wcd: wcd_pinctrl@5 { + compatible = "qcom,wcd-pinctrl"; + qcom,num-gpios = <5>; + gpio-controller; + #gpio-cells = <2>; + + spkr_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spkr_2_wcd_en_active: spkr_2_sd_n_active { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + }; + + wsa_spkr_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_wcd_en_active>; + pinctrl-1 = <&spkr_1_wcd_en_sleep>; + }; + + wsa_spkr_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_wcd_en_active>; + pinctrl-1 = <&spkr_2_wcd_en_sleep>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-wsa881x.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-wsa881x.dtsi index 8f1f699cfc1f..baf05c1c241b 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-wsa881x.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-wsa881x.dtsi @@ -9,24 +9,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -&soc { - wsa_spkr_sd1: msm_cdc_pinctrl@65 { - compatible = "qcom,msm-cdc-pinctrl"; - qcom,cdc-rst-n-gpio = <&tlmm 65 0>; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&spkr_1_sd_n_active>; - pinctrl-1 = <&spkr_1_sd_n_sleep>; - }; - - wsa_spkr_sd2: msm_cdc_pinctrl@66 { - compatible = "qcom,msm-cdc-pinctrl"; - qcom,cdc-rst-n-gpio = <&tlmm 66 0>; - pinctrl-names = "aud_active", "aud_sleep"; - pinctrl-0 = <&spkr_2_sd_n_active>; - pinctrl-1 = <&spkr_2_sd_n_sleep>; - }; -}; +#include "msmcobalt-wcd.dtsi" &slim_aud { tasha_codec { @@ -60,4 +43,36 @@ }; }; }; + + tavil_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_0211: wsa881x@20170211 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0212: wsa881x@20170212 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + + wsa881x_0213: wsa881x@21170213 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 7d61d8f1d341..e748783b0c7d 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -34,6 +34,7 @@ chosen { stdout-path = "serial0"; + bootargs = "rcupdate.rcu_expedited=1"; }; cpus { @@ -258,13 +259,25 @@ removed_regions: removed_regions@85800000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x85800000 0 0x5300000>; + reg = <0 0x85800000 0 0x3700000>; }; - peripheral_mem: peripheral_region@91900000 { + pil_slpi_mem: pil_slpi_region@93800000 { compatible = "removed-dma-pool"; no-map; - reg = <0 0x91900000 0 0x2e00000>; + reg = <0 0x93800000 0 0xf00000>; + }; + + pil_video_mem: pil_video_region@93300000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x93300000 0 0x500000>; + }; + + pil_adsp_mem: pil_adsp_region@91900000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0x91900000 0 0x1a00000>; }; modem_mem: modem_region@8ac00000 { @@ -284,7 +297,7 @@ alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; - size = <0 0x400000>; + size = <0 0x800000>; }; qseecom_mem: qseecom_region { @@ -310,6 +323,16 @@ alignment = <0 0x200000>; size = <0 0x5c00000>; }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x2000000>; + linux,cma-default; + }; }; }; @@ -646,7 +669,31 @@ < 1881600 >; qcom,cpufreq-table-4 = - < 300000 >; + < 300000 >, + < 345600 >, + < 422400 >, + < 480000 >, + < 556800 >, + < 633600 >, + < 710400 >, + < 787200 >, + < 844800 >, + < 902400 >, + < 979200 >, + < 1056000 >, + < 1171200 >, + < 1248000 >, + < 1324800 >, + < 1401600 >, + < 1478400 >, + < 1536000 >, + < 1632000 >, + < 1708800 >, + < 1785600 >, + < 1862400 >, + < 1939200 >, + < 2016000 >, + < 2092800 >; }; arm64-cpu-erp { @@ -774,7 +821,31 @@ < 1881600000 0x04040062 0x094e004e 0x4 >; qcom,perfcl-speedbin0-v0 = - < 300000000 0x0004000f 0x03200020 0x1>; + < 300000000 0x0004000f 0x01200020 0x1 >, + < 345600000 0x05040012 0x02200020 0x1 >, + < 422400000 0x05040016 0x02200020 0x1 >, + < 480000000 0x05040019 0x02200020 0x1 >, + < 556800000 0x0504001d 0x03200020 0x1 >, + < 633600000 0x05040021 0x03200020 0x1 >, + < 710400000 0x05040025 0x03200020 0x1 >, + < 787200000 0x05040029 0x04200020 0x1 >, + < 844800000 0x0404002c 0x04230023 0x1 >, + < 902400000 0x0404002f 0x04260026 0x1 >, + < 979200000 0x04040033 0x05290029 0x1 >, + < 1056000000 0x04040037 0x052c002c 0x1 >, + < 1171200000 0x0404003d 0x06310031 0x2 >, + < 1248000000 0x04040041 0x06340034 0x2 >, + < 1324800000 0x04040045 0x06370037 0x2 >, + < 1401600000 0x04040049 0x073a003a 0x2 >, + < 1478400000 0x0404004d 0x073e003e 0x2 >, + < 1536000000 0x04040050 0x07400040 0x2 >, + < 1632000000 0x04040055 0x08440044 0x3 >, + < 1708800000 0x04040059 0x08470047 0x3 >, + < 1785600000 0x0404005d 0x094a004a 0x3 >, + < 1862400000 0x04040061 0x094e004e 0x3 >, + < 1939200000 0x04040065 0x09510051 0x3 >, + < 2016000000 0x04040069 0x0a540054 0x3 >, + < 2092800000 0x0404006d 0x0a570057 0x3 >; qcom,up-timer = <1000 1000>; @@ -1052,34 +1123,6 @@ reg-names = "smem", "irq-reg-base", "aux-mem1", "smem_targ_info_reg"; qcom,mpu-enabled; - - qcom,smd-modem { - compatible = "qcom,smd"; - qcom,smd-edge = <0>; - qcom,smd-irq-offset = <0x0>; - qcom,smd-irq-bitmask = <0x1000>; - interrupts = <0 449 1>; - label = "modem"; - qcom,not-loadable; - }; - - qcom,smd-adsp { - compatible = "qcom,smd"; - qcom,smd-edge = <1>; - qcom,smd-irq-offset = <0x0>; - qcom,smd-irq-bitmask = <0x100>; - interrupts = <0 156 1>; - label = "adsp"; - }; - - qcom,smd-dsps { - compatible = "qcom,smd"; - qcom,smd-edge = <3>; - qcom,smd-irq-offset = <0x0>; - qcom,smd-irq-bitmask = <0x2000000>; - interrupts = <0 176 1>; - label = "dsps"; - }; }; qcom,msm-adsprpc-mem { @@ -1117,11 +1160,6 @@ label = "adsprpc-smd"; iommus = <&lpass_q6_smmu 11>; }; - qcom,msm_fastrpc_compute_cb5 { - compatible = "qcom,msm-fastrpc-compute-cb"; - label = "adsprpc-smd"; - iommus = <&lpass_q6_smmu 12>; - }; qcom,msm_fastrpc_compute_cb6 { compatible = "qcom,msm-fastrpc-compute-cb"; label = "adsprpc-smd"; @@ -1411,10 +1449,6 @@ qcom,vreg-cx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_BINNING RPM_SMD_REGULATOR_LEVEL_SVS 0>; - qcom,l1-supported; - qcom,l1ss-supported; - qcom,aux-clk-sync; - qcom,ep-latency = <10>; qcom,ep-wakeirq; @@ -1906,6 +1940,13 @@ "phy_phy_reset", "ref_clk_src", "ref_clk"; }; + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&lpass_q6_smmu 12>; + qcom,usb-audio-stream-id = <12>; + qcom,usb-audio-intr-num = <2>; + }; + dbm_1p5: dbm@a8f8000 { compatible = "qcom,usb-dbm-1p5"; reg = <0xa8f8000 0x300>; @@ -1936,7 +1977,7 @@ status = "ok"; qcom,ssctl-instance-id = <0x14>; qcom,firmware-name = "adsp"; - memory-region = <&peripheral_mem>; + memory-region = <&pil_adsp_mem>; /* GPIO inputs from lpass */ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>; @@ -2416,7 +2457,7 @@ qcom,ssctl-instance-id = <0x16>; qcom,firmware-name = "slpi"; status = "ok"; - memory-region = <&peripheral_mem>; + memory-region = <&pil_slpi_mem>; /* GPIO inputs from ssc */ qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_3_in 0 0>; @@ -2449,7 +2490,7 @@ qcom,pas-id = <9>; qcom,proxy-timeout-ms = <10000>; qcom,firmware-name = "venus"; - memory-region = <&peripheral_mem>; + memory-region = <&pil_video_mem>; status = "ok"; }; @@ -2497,6 +2538,12 @@ qcom,rtb-size = <0x100000>; }; + qcom,mpm2-sleep-counter@10a3000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x010a3000 0x1000>; + clock-frequency = <32768>; + }; + qcom,msm-imem@146bf000 { compatible = "qcom,msm-imem"; reg = <0x146bf000 0x1000>; @@ -2707,6 +2754,18 @@ qcom,smmu-support; status = "disabled"; }; + + qcom,qsee_ipc_irq_bridge { + compatible = "qcom,qsee-ipc-irq-bridge"; + + qcom,qsee-ipc-irq-spss { + qcom,rx-irq-clr = <0x1d08008 0x4>; + qcom,rx-irq-clr-mask = <0x2>; + qcom,dev-name = "qsee_ipc_irq_spss"; + interrupts = <0 349 4>; + label = "spss"; + }; + }; }; &clock_cpu { @@ -2746,6 +2805,8 @@ &gdsc_bimc_smmu { clock-names = "bus_clk"; clocks = <&clock_mmss clk_mmss_bimc_smmu_axi_clk>; + proxy-supply = <&gdsc_bimc_smmu>; + qcom,proxy-consumer-enable; status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-ion.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-ion.dtsi new file mode 100644 index 000000000000..f6deef335844 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmfalcon-ion.dtsi @@ -0,0 +1,52 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + system_contig_heap: qcom,ion-heap@21 { + reg = <21>; + qcom,ion-heap-type = "SYSTEM_CONTIG"; + }; + + qcom,ion-heap@22 { /* ADSP HEAP */ + reg = <22>; + memory-region = <&adsp_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts new file mode 100644 index 000000000000..6631d31bac6d --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts @@ -0,0 +1,29 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "msmfalcon.dtsi" +#include "msmfalcon-pinctrl.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. MSM FALCON RUMI"; + compatible = "qcom,msmfalcon-rumi", "qcom,msmfalcon", "qcom,rumi"; + qcom,board-id = <15 0>; +}; + +&uartblsp2dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index 6d931c1fbb89..ea60ed90cf4f 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -11,7 +11,9 @@ */ #include "skeleton64.dtsi" -#include <dt-bindings/clock/msm-clocks-cobalt.h> +#include <dt-bindings/clock/qcom,gcc-msmfalcon.h> +#include <dt-bindings/clock/qcom,gpu-msmfalcon.h> +#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { @@ -128,6 +130,68 @@ }; soc: soc { }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + removed_regions: removed_regions@85800000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x85800000 0x0 0x3700000>; + }; + + modem_fw_mem: modem_fw_region@8ac00000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x8ac00000 0x0 0x7800000>; + }; + + adsp_fw_mem: adsp_fw_region@92400000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x92400000 0x0 0x1e00000>; + }; + + cdsp_fw_mem: cdsp_fw_region@94200000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0x0 0x94200000 0x0 0x600000>; + }; + + venus_fw_mem: venus_fw_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x80000000 0x0 0x20000000>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x400000>; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + secure_display_memory: secure_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x5c00000>; + }; + }; }; &soc { @@ -159,13 +223,30 @@ clock-frequency = <19200000>; }; + qcom,sps { + compatible = "qcom,msm_sps_4k"; + qcom,pipe-attr-ee; + }; + + tsens: tsens@10ad000 { + compatible = "qcom,msmfalcon-tsens"; + reg = <0x10ad000 0x2000>, + <0x784240 0x1000>; + reg-names = "tsens_physical", "tsens_eeprom_physical"; + interrupts = <0 184 0>, <0 430 0>; + interrupt-names = "tsens-upper-lower", "tsens-critical"; + qcom,sensors = <14>; + qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 + 3200 3200 3200 3200 3200 3200>; + }; + uartblsp2dm1: serial@0c1b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xc1b0000 0x1000>; interrupts = <0 114 0>; status = "disabled"; - clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>, - <&clock_gcc clk_gcc_blsp2_ahb_clk>; + clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; }; @@ -232,4 +313,59 @@ compatible = "qcom,dummycc"; #clock-cells = <1>; }; + + qcom,ipc-spinlock@1f40000 { + compatible = "qcom,ipc-spinlock-sfpb"; + reg = <0x1f40000 0x8000>; + qcom,num-locks = <8>; + }; + + qcom,smem@86000000 { + compatible = "qcom,smem"; + reg = <0x86000000 0x200000>, + <0x17911008 0x4>, + <0x778000 0x7000>, + <0x1fd4000 0x8>; + reg-names = "smem", "irq-reg-base", "aux-mem1", + "smem_targ_info_reg"; + qcom,mpu-enabled; + }; + + glink_mpss: qcom,glink-ssr-modem { + compatible = "qcom,glink_ssr"; + label = "modem"; + qcom,edge = "mpss"; + qcom,notify-edges = <&glink_lpass>, <&glink_rpm>, + <&glink_cdsp>; + qcom,xprt = "smem"; + }; + + glink_lpass: qcom,glink-ssr-adsp { + compatible = "qcom,glink_ssr"; + label = "adsp"; + qcom,edge = "lpass"; + qcom,notify-edges = <&glink_mpss>, <&glink_rpm>, + <&glink_cdsp>; + qcom,xprt = "smem"; + }; + + glink_rpm: qcom,glink-ssr-rpm { + compatible = "qcom,glink_ssr"; + label = "rpm"; + qcom,edge = "rpm"; + qcom,notify-edges = <&glink_lpass>, <&glink_mpss>, + <&glink_cdsp>; + qcom,xprt = "smem"; + }; + + glink_cdsp: qcom,glink-ssr-cdsp { + compatible = "qcom,glink_ssr"; + label = "cdsp"; + qcom,edge = "cdsp"; + qcom,notify-edges = <&glink_lpass>, <&glink_mpss>, + <&glink_rpm>; + qcom,xprt = "smem"; + }; }; + +#include "msmfalcon-ion.dtsi" diff --git a/arch/arm/boot/dts/qcom/msmhamster.dtsi b/arch/arm/boot/dts/qcom/msmhamster.dtsi index cf34ad20f84a..e87cf7c153ea 100644 --- a/arch/arm/boot/dts/qcom/msmhamster.dtsi +++ b/arch/arm/boot/dts/qcom/msmhamster.dtsi @@ -58,3 +58,15 @@ < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; }; + +&tsens0 { + compatible = "qcom,msmhamster-tsens"; +}; + +&tsens1 { + compatible = "qcom,msmhamster-tsens"; + qcom,client-id = <14 15 16 17 18 19 20>; + qcom,sensor-id = <0 1 3 4 5 6 7>; + qcom,sensors = <7>; + qcom,slope = <2901 2846 3200 3200 3200 3200 3200>; +}; diff --git a/arch/arm/boot/dts/sama5d2-pinfunc.h b/arch/arm/boot/dts/sama5d2-pinfunc.h index 1afe24629d1f..b0c912feaa2f 100644 --- a/arch/arm/boot/dts/sama5d2-pinfunc.h +++ b/arch/arm/boot/dts/sama5d2-pinfunc.h @@ -90,7 +90,7 @@ #define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2) #define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1) #define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2) -#define PIN_PA15 14 +#define PIN_PA15 15 #define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) #define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1) #define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1) diff --git a/arch/arm/configs/msmcortex_defconfig b/arch/arm/configs/msmcortex_defconfig new file mode 100644 index 000000000000..9a3ffc5e555f --- /dev/null +++ b/arch/arm/configs/msmcortex_defconfig @@ -0,0 +1,562 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_RCU_EXPERT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_SCHED_HMP=y +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_MEMBARRIER is not set +CONFIG_EMBEDDED=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SIG=y +CONFIG_MODULE_SIG_SHA512=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_MSMFALCON=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=8 +CONFIG_ARM_PSCI=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_CLEANCACHE=y +CONFIG_CMA=y +CONFIG_ZSMALLOC=y +CONFIG_SECCOMP=y +CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y +CONFIG_SCHED_FREQ_INPUT=y +# CONFIG_CPU_FREQ_STAT is not set +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_PM_DEBUG=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +# CONFIG_INET_LRO is not set +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_TEE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +CONFIG_NETFILTER_XT_TARGET_SECMARK=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_SECURITY=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_L2TP=y +CONFIG_L2TP_DEBUGFS=y +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=y +CONFIG_L2TP_ETH=y +CONFIG_BRIDGE=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=y +CONFIG_NET_EMATCH_NBYTE=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_EMATCH_META=y +CONFIG_NET_EMATCH_TEXT=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_DNS_RESOLVER=y +CONFIG_RMNET_DATA=y +CONFIG_RMNET_DATA_FC=y +CONFIG_RMNET_DATA_DEBUG_PKT=y +CONFIG_SOCKEV_NLMCAST=y +CONFIG_BT=y +CONFIG_MSM_BT_POWER=y +CONFIG_BTFM_SLIM=y +CONFIG_BTFM_SLIM_WCN3990=y +CONFIG_CFG80211=y +CONFIG_CFG80211_INTERNAL_REGDB=y +# CONFIG_CFG80211_CRDA_SUPPORT is not set +CONFIG_RFKILL=y +CONFIG_NFC_NQ=y +CONFIG_IPC_ROUTER=y +CONFIG_IPC_ROUTER_SECURITY=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=40 +CONFIG_ZRAM=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_UID_STAT=y +CONFIG_UID_CPUTIME=y +CONFIG_MSM_ULTRASOUND=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_UFSHCD=y +CONFIG_SCSI_UFSHCD_PLATFORM=y +CONFIG_SCSI_UFS_QCOM=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_UEVENT=y +CONFIG_DM_VERITY=y +CONFIG_NETDEVICES=y +CONFIG_BONDING=y +CONFIG_DUMMY=y +CONFIG_TUN=y +CONFIG_RNDIS_IPA=y +CONFIG_PHYLIB=y +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_MPPE=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_WCNSS_MEM_PRE_ALLOC=y +CONFIG_ATH_CARDS=y +CONFIG_CLD_LL_CORE=y +CONFIG_QPNP_POWER_ON=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_KEYRESET=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_KEYCHORD=y +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_SERIAL_MSM_HS=y +CONFIG_SERIAL_MSM_SMD=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_MSM_ADSPRPC=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MSM_V2=y +CONFIG_SLIMBUS=y +CONFIG_SLIMBUS_MSM_NGD=y +CONFIG_SOUNDWIRE=y +CONFIG_SPI=y +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=y +CONFIG_SPMI=y +CONFIG_PINCTRL_MSMCOBALT=y +CONFIG_PINCTRL_MSMFALCON=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_QPNP_PIN=y +CONFIG_APSS_CORE_EA=y +CONFIG_MSM_APM=y +CONFIG_QPNP_SMBCHARGER=y +CONFIG_SMB135X_CHARGER=y +CONFIG_SMB1351_USB_CHARGER=y +CONFIG_MSM_BCL_CTL=y +CONFIG_MSM_BCL_PERIPHERAL_CTL=y +CONFIG_QPNP_SMB2=y +CONFIG_SMB138X_CHARGER=y +CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y +CONFIG_THERMAL=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_MFD_I2C_PMIC=y +CONFIG_MSM_CDC_PINCTRL=y +CONFIG_MSM_CDC_SUPPLY=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_RPM_SMD=y +CONFIG_REGULATOR_QPNP=y +CONFIG_REGULATOR_QPNP_LABIBB=y +CONFIG_REGULATOR_SPM=y +CONFIG_REGULATOR_CPR3_HMSS=y +CONFIG_REGULATOR_CPR3_MMSS=y +CONFIG_REGULATOR_CPRH_KBSS=y +CONFIG_REGULATOR_MEM_ACC=y +CONFIG_REGULATOR_PROXY_CONSUMER=y +CONFIG_REGULATOR_STUB=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_ADV_DEBUG=y +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_MSM_CAMERA=y +CONFIG_MSM_CAMERA_DEBUG=y +CONFIG_MSM_SDE_ROTATOR=y +CONFIG_QCOM_KGSL=y +CONFIG_FB=y +CONFIG_FB_VIRTUAL=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SOC=y +CONFIG_UHID=y +CONFIG_HID_APPLE=y +CONFIG_HID_MICROSOFT=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_ISP1760=y +CONFIG_USB_ISP1760_HOST_ROLE=y +CONFIG_USB_OTG_WAKELOCK=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MSM_SSPHY_QMP=y +CONFIG_MSM_QUSB_PHY=y +CONFIG_DUAL_ROLE_USB_INTF=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_MTP=y +CONFIG_USB_CONFIGFS_F_PTP=y +CONFIG_USB_CONFIGFS_F_ACC=y +CONFIG_USB_CONFIGFS_UEVENT=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_DIAG=y +CONFIG_USB_CONFIGFS_F_GSI=y +CONFIG_USB_CONFIGFS_F_CDEV=y +CONFIG_USB_CONFIGFS_F_QDSS=y +CONFIG_MMC=y +CONFIG_MMC_PERF_PROFILING=y +CONFIG_MMC_PARANOID_SD_INIT=y +CONFIG_MMC_CLKGATE=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_TEST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_QPNP=y +CONFIG_LEDS_QPNP_FLASH_V2=y +CONFIG_LEDS_QPNP_WLED=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_SWITCH=y +CONFIG_EDAC=y +CONFIG_EDAC_MM_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_QPNP=y +CONFIG_DMADEVICES=y +CONFIG_QCOM_SPS_DMA=y +CONFIG_UIO=y +CONFIG_UIO_MSM_SHAREDMEM=y +CONFIG_STAGING=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_SYNC=y +CONFIG_ION=y +CONFIG_ION_MSM=y +CONFIG_QPNP_REVID=y +CONFIG_QPNP_COINCELL=y +CONFIG_SPS=y +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_IPA=y +CONFIG_RMNET_IPA=y +CONFIG_GSI=y +CONFIG_IPA3=y +CONFIG_RMNET_IPA3=y +CONFIG_GPIO_USB_DETECT=y +CONFIG_USB_BAM=y +CONFIG_REMOTE_SPINLOCK_MSM=y +CONFIG_ARM_SMMU=y +CONFIG_QCOM_COMMON_LOG=y +CONFIG_MSM_SMEM=y +CONFIG_QPNP_HAPTIC=y +CONFIG_MSM_SMD=y +CONFIG_MSM_SMD_DEBUG=y +CONFIG_MSM_GLINK=y +CONFIG_MSM_GLINK_LOOPBACK_SERVER=y +CONFIG_MSM_GLINK_SMD_XPRT=y +CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y +CONFIG_MSM_SPCOM=y +CONFIG_MSM_SMEM_LOGGING=y +CONFIG_MSM_SMP2P=y +CONFIG_MSM_SMP2P_TEST=y +CONFIG_MSM_QMI_INTERFACE=y +CONFIG_QCOM_BUS_SCALING=y +CONFIG_MSM_SERVICE_LOCATOR=y +CONFIG_QCOM_DCC=y +CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y +CONFIG_MSM_SYSMON_GLINK_COMM=y +CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y +CONFIG_MSM_GLINK_PKT=y +CONFIG_MSM_SPM=y +CONFIG_QCOM_SCM=y +CONFIG_QCOM_WATCHDOG_V2=y +CONFIG_QCOM_MEMORY_DUMP_V2=y +CONFIG_ICNSS=y +CONFIG_MSM_GLADIATOR_ERP_V2=y +CONFIG_PANIC_ON_GLADIATOR_ERROR_V2=y +CONFIG_MSM_GLADIATOR_HANG_DETECT=y +CONFIG_MSM_CORE_HANG_DETECT=y +CONFIG_MSM_RUN_QUEUE_STATS=y +CONFIG_MSM_BOOT_STATS=y +CONFIG_QCOM_CPUSS_DUMP=y +CONFIG_MSM_QDSP6_APRV2_GLINK=y +CONFIG_MSM_PERFORMANCE=y +CONFIG_MSM_SUBSYSTEM_RESTART=y +CONFIG_MSM_PIL=y +CONFIG_MSM_PIL_SSR_GENERIC=y +CONFIG_MSM_PIL_MSS_QDSP6V5=y +CONFIG_TRACER_PKT=y +CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y +CONFIG_MSM_MPM_OF=y +CONFIG_MSM_EVENT_TIMER=y +CONFIG_MSM_CORE_CTL_HELPER=y +CONFIG_MSM_SERVICE_NOTIFIER=y +CONFIG_MEM_SHARE_QMI_SERVICE=y +CONFIG_QCOM_BIMC_BWMON=y +CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y +CONFIG_QCOM_DEVFREQ_DEVBW=y +CONFIG_EXTCON=y +CONFIG_IIO=y +CONFIG_QCOM_RRADC=y +CONFIG_PWM=y +CONFIG_PWM_QPNP=y +CONFIG_ARM_GIC_V3_ACL=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_MSM_TZ_LOG=y +CONFIG_SENSORS_SSC=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=y +CONFIG_ECRYPT_FS_MESSAGING=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_PAGE_OWNER=y +CONFIG_PAGE_OWNER_ENABLE_DEFAULT=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_SLUB_DEBUG_PANIC_ON=y +CONFIG_DEBUG_OBJECTS=y +CONFIG_DEBUG_OBJECTS_FREE=y +CONFIG_DEBUG_OBJECTS_TIMERS=y +CONFIG_DEBUG_OBJECTS_WORK=y +CONFIG_DEBUG_OBJECTS_RCU_HEAD=y +CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y +CONFIG_SLUB_DEBUG_ON=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 +CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y +CONFIG_DEBUG_STACK_USAGE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_PANIC_ON_SCHED_BUG=y +CONFIG_PANIC_ON_RT_THROTTLING=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_LIST=y +CONFIG_FAULT_INJECTION=y +CONFIG_FAIL_PAGE_ALLOC=y +CONFIG_UFS_FAULT_INJECTION=y +CONFIG_FAULT_INJECTION_DEBUG_FS=y +CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y +CONFIG_IPC_LOGGING=y +CONFIG_QCOM_RTB=y +CONFIG_FUNCTION_TRACER=y +CONFIG_TRACER_SNAPSHOT=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_CPU_FREQ_SWITCH_PROFILER=y +CONFIG_MEMTEST=y +CONFIG_PANIC_ON_DATA_CORRUPTION=y +CONFIG_PID_IN_CONTEXTIDR=y +CONFIG_DEBUG_SET_MODULE_RONX=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_REMOTE_ETM=y +CONFIG_CORESIGHT_REMOTE_ETM_DEFAULT_ENABLE=0 +CONFIG_CORESIGHT_CTI=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +CONFIG_CORESIGHT_QPDI=y +CONFIG_CORESIGHT_SOURCE_DUMMY=y +CONFIG_SECURITY=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SMACK=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_XCBC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DEV_QCRYPTO=y +CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y +CONFIG_CRYPTO_DEV_QCEDEV=y +CONFIG_CRYPTO_DEV_OTA_CRYPTO=y +CONFIG_CRYPTO_DEV_QCE=y +CONFIG_XZ_DEC=y diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 9623a8a87e18..2005a47b491e 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -512,7 +512,6 @@ static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; } #endif #ifdef CONFIG_DEBUG_RODATA -void mark_rodata_ro(void); void set_kernel_text_rw(void); void set_kernel_text_ro(void); #else diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index 68ee3ce17b82..b4c6d99364f1 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -16,7 +16,7 @@ extern struct smp_operations psci_smp_ops; -#ifdef CONFIG_ARM_PSCI +#if defined(CONFIG_SMP) && defined(CONFIG_ARM_PSCI) bool psci_smp_available(void); #else static inline bool psci_smp_available(void) { return false; } diff --git a/arch/arm/include/asm/xen/page-coherent.h b/arch/arm/include/asm/xen/page-coherent.h index 0375c8caa061..9408a994cc91 100644 --- a/arch/arm/include/asm/xen/page-coherent.h +++ b/arch/arm/include/asm/xen/page-coherent.h @@ -35,14 +35,21 @@ static inline void xen_dma_map_page(struct device *hwdev, struct page *page, dma_addr_t dev_addr, unsigned long offset, size_t size, enum dma_data_direction dir, struct dma_attrs *attrs) { - bool local = XEN_PFN_DOWN(dev_addr) == page_to_xen_pfn(page); + unsigned long page_pfn = page_to_xen_pfn(page); + unsigned long dev_pfn = XEN_PFN_DOWN(dev_addr); + unsigned long compound_pages = + (1<<compound_order(page)) * XEN_PFN_PER_PAGE; + bool local = (page_pfn <= dev_pfn) && + (dev_pfn - page_pfn < compound_pages); + /* - * Dom0 is mapped 1:1, while the Linux page can be spanned accross - * multiple Xen page, it's not possible to have a mix of local and - * foreign Xen page. So if the first xen_pfn == mfn the page is local - * otherwise it's a foreign page grant-mapped in dom0. If the page is - * local we can safely call the native dma_ops function, otherwise we - * call the xen specific function. + * Dom0 is mapped 1:1, while the Linux page can span across + * multiple Xen pages, it's not possible for it to contain a + * mix of local and foreign Xen pages. So if the first xen_pfn + * == mfn the page is local otherwise it's a foreign page + * grant-mapped in dom0. If the page is local we can safely + * call the native dma_ops function, otherwise we call the xen + * specific function. */ if (local) __generic_dma_ops(hwdev)->map_page(hwdev, page, offset, size, dir, attrs); diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index edb0a0036110..598323a1842e 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -234,6 +234,9 @@ static int __init parse_dt_topology(void) unsigned long capacity = 0; int cpu = 0, ret = 0; + __cpu_capacity = kcalloc(nr_cpu_ids, sizeof(*__cpu_capacity), + GFP_NOWAIT); + cn = of_find_node_by_path("/cpus"); if (!cn) { pr_err("No CPU information found in DT\n"); @@ -260,9 +263,6 @@ static int __init parse_dt_topology(void) if (cpu_topology[cpu].cluster_id == -1) ret = -EINVAL; - __cpu_capacity = kcalloc(nr_cpu_ids, sizeof(*__cpu_capacity), - GFP_NOWAIT); - for_each_possible_cpu(cpu) { const u32 *rate; int len; @@ -456,38 +456,46 @@ static struct sched_domain_topology_level arm_topology[] = { { NULL, }, }; -/* - * init_cpu_topology is called at boot when only one cpu is running - * which prevent simultaneous write access to cpu_topology array - */ -void __init init_cpu_topology(void) +static void __init reset_cpu_topology(void) { unsigned int cpu; - /* init core mask and capacity */ for_each_possible_cpu(cpu) { - struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]); + struct cputopo_arm *cpu_topo = &cpu_topology[cpu]; cpu_topo->thread_id = -1; - cpu_topo->core_id = -1; + cpu_topo->core_id = -1; cpu_topo->cluster_id = -1; + cpumask_clear(&cpu_topo->core_sibling); cpumask_clear(&cpu_topo->thread_sibling); + } +} +static void __init reset_cpu_capacity(void) +{ + unsigned int cpu; + + for_each_possible_cpu(cpu) set_capacity_scale(cpu, SCHED_CAPACITY_SCALE); - } - smp_wmb(); +} - if (parse_dt_topology()) { - struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]); +/* + * init_cpu_topology is called at boot when only one cpu is running + * which prevent simultaneous write access to cpu_topology array + */ +void __init init_cpu_topology(void) +{ + unsigned int cpu; - cpu_topo->thread_id = -1; - cpu_topo->core_id = -1; - cpu_topo->cluster_id = -1; - cpumask_clear(&cpu_topo->core_sibling); - cpumask_clear(&cpu_topo->thread_sibling); + /* init core mask and capacity */ + reset_cpu_topology(); + reset_cpu_capacity(); + smp_wmb(); - set_capacity_scale(cpu, SCHED_CAPACITY_SCALE); + if (parse_dt_topology()) { + reset_cpu_topology(); + reset_cpu_capacity(); } for_each_possible_cpu(cpu) diff --git a/arch/arm/kvm/guest.c b/arch/arm/kvm/guest.c index 96e935bbc38c..3705fc2921c2 100644 --- a/arch/arm/kvm/guest.c +++ b/arch/arm/kvm/guest.c @@ -155,7 +155,7 @@ static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) u64 val; val = kvm_arm_timer_get_reg(vcpu, reg->id); - return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)); + return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0; } static unsigned long num_core_regs(void) diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 7b76ce01c21d..8633c703546a 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c @@ -101,10 +101,8 @@ static void omap2_onenand_set_async_mode(void __iomem *onenand_base) static void set_onenand_cfg(void __iomem *onenand_base) { - u32 reg; + u32 reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT; - reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); - reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9)); reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) | ONENAND_SYS_CFG1_BL_16; if (onenand_flags & ONENAND_FLAG_SYNCREAD) @@ -123,6 +121,7 @@ static void set_onenand_cfg(void __iomem *onenand_base) reg |= ONENAND_SYS_CFG1_VHF; else reg &= ~ONENAND_SYS_CFG1_VHF; + writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); } @@ -289,6 +288,7 @@ static int omap2_onenand_setup_async(void __iomem *onenand_base) } } + onenand_async.sync_write = true; omap2_onenand_calc_async_timings(&t); ret = gpmc_cs_program_settings(gpmc_onenand_data->cs, &onenand_async); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 48495ad82aba..8e0bd5939e5a 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2200,6 +2200,11 @@ static int _enable(struct omap_hwmod *oh) */ static int _idle(struct omap_hwmod *oh) { + if (oh->flags & HWMOD_NO_IDLE) { + oh->_int_flags |= _HWMOD_SKIP_ENABLE; + return 0; + } + pr_debug("omap_hwmod: %s: idling\n", oh->name); if (oh->_state != _HWMOD_STATE_ENABLED) { @@ -2504,6 +2509,8 @@ static int __init _init(struct omap_hwmod *oh, void *data) oh->flags |= HWMOD_INIT_NO_RESET; if (of_find_property(np, "ti,no-idle-on-init", NULL)) oh->flags |= HWMOD_INIT_NO_IDLE; + if (of_find_property(np, "ti,no-idle", NULL)) + oh->flags |= HWMOD_NO_IDLE; } oh->_state = _HWMOD_STATE_INITIALIZED; @@ -2630,7 +2637,7 @@ static void __init _setup_postsetup(struct omap_hwmod *oh) * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - * it should be set by the core code as a runtime flag during startup */ - if ((oh->flags & HWMOD_INIT_NO_IDLE) && + if ((oh->flags & (HWMOD_INIT_NO_IDLE | HWMOD_NO_IDLE)) && (postsetup_state == _HWMOD_STATE_IDLE)) { oh->_int_flags |= _HWMOD_SKIP_ENABLE; postsetup_state = _HWMOD_STATE_ENABLED; diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 76bce11c85a4..7c7a31169475 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -525,6 +525,8 @@ struct omap_hwmod_omap4_prcm { * or idled. * HWMOD_OPT_CLKS_NEEDED: The optional clocks are needed for the module to * operate and they need to be handled at the same time as the main_clk. + * HWMOD_NO_IDLE: Do not idle the hwmod at all. Useful to handle certain + * IPs like CPSW on DRA7, where clocks to this module cannot be disabled. */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -541,6 +543,7 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_SWSUP_SIDLE_ACT (1 << 12) #define HWMOD_RECONFIG_IO_CHAIN (1 << 13) #define HWMOD_OPT_CLKS_NEEDED (1 << 14) +#define HWMOD_NO_IDLE (1 << 15) /* * omap_hwmod._int_flags definitions diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index 918a3fa7e938..69261c70e1dd 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -1,10 +1,43 @@ if ARCH_QCOM menu "QCOM SoC Type" +config ARCH_MSMFALCON + bool "Enable Support for Qualcomm MSMFALCON" + select CLKDEV_LOOKUP + select HAVE_CLK + select HAVE_CLK_PREPARE + select PM_OPP + select SOC_BUS + select MSM_IRQ + select THERMAL_WRITABLE_TRIPS + select ARM_GIC_V3 + select ARM_AMBA + select SPARSE_IRQ + select MULTI_IRQ_HANDLER + select HAVE_ARM_ARCH_TIMER + select MAY_HAVE_SPARSE_IRQ + select PINCTRL_MSM_TLMM + select USE_PINCTRL_IRQ + select MSM_PM if PM + select QMI_ENCDEC + select CPU_FREQ + select CPU_FREQ_MSM + select PM_DEVFREQ + select MSM_DEVFREQ_DEVBW + select DEVFREQ_SIMPLE_DEV + select DEVFREQ_GOV_MSM_BW_HWMON + select MSM_BIMC_BWMON + select MSM_QDSP6V2_CODECS + select MSM_AUDIO_QDSP6V2 if SND_SOC + select MSM_RPM_SMD + select MSM_JTAGV8 if CORESIGHT_ETMV4 + help + This enables support for the MSMFALCON chipset. If you do not + wish to build a kernel that runs on this chipset, say 'N' here. + config ARCH_MSM8X60 bool "Enable support for MSM8X60" select ARCH_SUPPORTS_BIG_ENDIAN - select ARM_GIC select ARM_AMBA select QCOM_SCM if SMP select CLKSRC_QCOM @@ -15,7 +48,6 @@ config ARCH_MSM8960 bool "Enable support for MSM8960" select CLKSRC_QCOM select ARCH_SUPPORTS_BIG_ENDIAN - select ARM_GIC select ARM_AMBA select QCOM_SCM if SMP select CLKSRC_OF @@ -25,7 +57,6 @@ config ARCH_MSM8974 bool "Enable support for MSM8974" select HAVE_ARM_ARCH_TIMER select ARCH_SUPPORTS_BIG_ENDIAN - select ARM_GIC select ARM_AMBA select QCOM_SCM if SMP select CLKSRC_OF diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile index 3d9f893ba3af..c5e30fff2b1e 100644 --- a/arch/arm/mach-qcom/Makefile +++ b/arch/arm/mach-qcom/Makefile @@ -1,3 +1,4 @@ obj-y := board.o obj-$(CONFIG_USE_OF) += board-dt.o +obj-$(CONFIG_ARCH_MSMFALCON) += board-falcon.o obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-qcom/board-falcon.c b/arch/arm/mach-qcom/board-falcon.c new file mode 100644 index 000000000000..e9374050b2cb --- /dev/null +++ b/arch/arm/mach-qcom/board-falcon.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <asm/mach/arch.h> +#include "board-dt.h" + +static const char *msmfalcon_dt_match[] __initconst = { + "qcom,msmfalcon", + "qcom,apqfalcon", + NULL +}; + +static void __init msmfalcon_init(void) +{ + board_dt_populate(NULL); +} + +DT_MACHINE_START(MSMFALCON_DT, + "Qualcomm Technologies, Inc. MSM FALCON (Flattened Device Tree)") + .init_machine = msmfalcon_init, + .dt_compat = msmfalcon_dt_match, +MACHINE_END diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index bf6a92504175..d41957eae6ef 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -2284,6 +2284,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, set_dma_ops(dev, dma_ops); } +EXPORT_SYMBOL(arch_setup_dma_ops); void arch_teardown_dma_ops(struct device *dev) { diff --git a/arch/arm/vdso/vdso.S b/arch/arm/vdso/vdso.S index b2b97e3e7bab..a62a7b64f49c 100644 --- a/arch/arm/vdso/vdso.S +++ b/arch/arm/vdso/vdso.S @@ -23,9 +23,8 @@ #include <linux/const.h> #include <asm/page.h> - __PAGE_ALIGNED_DATA - .globl vdso_start, vdso_end + .section .data..ro_after_init .balign PAGE_SIZE vdso_start: .incbin "arch/arm/vdso/vdso.so" |