diff options
Diffstat (limited to 'arch/arm/include')
28 files changed, 1036 insertions, 495 deletions
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild index 628a38a11a70..730b4e850f6f 100644 --- a/arch/arm/include/asm/Kbuild +++ b/arch/arm/include/asm/Kbuild @@ -6,6 +6,7 @@ generic-y += current.h generic-y += emergency-restart.h generic-y += errno.h generic-y += exec.h +generic-y += hash.h generic-y += ioctl.h generic-y += ipcbuf.h generic-y += irq_regs.h @@ -36,3 +37,6 @@ generic-y += termbits.h generic-y += termios.h generic-y += timex.h generic-y += trace_clock.h + +generated-y += mach-types.h +generated-y += unistd-nr.h diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 9156fc303afd..012a3aafcf33 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -94,6 +94,21 @@ * DMA Cache Coherency * =================== * + * dma_inv_range(start, end) + * + * Invalidate (discard) the specified virtual address range. + * May not write back any entries. If 'start' or 'end' + * are not cache line aligned, those lines must be written + * back. + * - start - virtual start address + * - end - virtual end address + * + * dma_clean_range(start, end) + * + * Clean (write back) the specified virtual address range. + * - start - virtual start address + * - end - virtual end address + * * dma_flush_range(start, end) * * Clean and invalidate the specified virtual address range. @@ -115,6 +130,8 @@ struct cpu_cache_fns { void (*dma_map_area)(const void *, size_t, int); void (*dma_unmap_area)(const void *, size_t, int); + void (*dma_inv_range)(const void *, const void *); + void (*dma_clean_range)(const void *, const void *); void (*dma_flush_range)(const void *, const void *); }; @@ -140,6 +157,8 @@ extern struct cpu_cache_fns cpu_cache; * is visible to DMA, or data written by DMA to system memory is * visible to the CPU. */ +#define dmac_inv_range cpu_cache.dma_inv_range +#define dmac_clean_range cpu_cache.dma_clean_range #define dmac_flush_range cpu_cache.dma_flush_range #else @@ -159,6 +178,11 @@ extern void __cpuc_flush_dcache_area(void *, size_t); * is visible to DMA, or data written by DMA to system memory is * visible to the CPU. */ +extern void __dma_map_area(const void *, size_t, int); +extern void __dma_unmap_area(const void *, size_t, int); + +extern void dmac_inv_range(const void *, const void *); +extern void dmac_clean_range(const void *, const void *); extern void dmac_flush_range(const void *, const void *); #endif @@ -518,4 +542,13 @@ static inline void secure_flush_area(const void *addr, size_t size) outer_flush_range(phys, phys + size); } +#ifdef CONFIG_FREE_PAGES_RDONLY +#define mark_addr_rdonly(a) set_memory_ro((unsigned long)a, 1) +#define mark_addr_rdwrite(a) set_memory_rw((unsigned long)a, 1) +#else +#define mark_addr_rdonly(a) +#define mark_addr_rdwrite(a) +#endif + + #endif diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h index 0f8424924902..3848259bebf8 100644 --- a/arch/arm/include/asm/cpuidle.h +++ b/arch/arm/include/asm/cpuidle.h @@ -30,7 +30,7 @@ static inline int arm_cpuidle_simple_enter(struct cpuidle_device *dev, struct device_node; struct cpuidle_ops { - int (*suspend)(int cpu, unsigned long arg); + int (*suspend)(unsigned long arg); int (*init)(struct device_node *, int cpu); }; diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h index 4111592f0130..d8a572f9c187 100644 --- a/arch/arm/include/asm/device.h +++ b/arch/arm/include/asm/device.h @@ -7,7 +7,7 @@ #define ASMARM_DEVICE_H struct dev_archdata { - struct dma_map_ops *dma_ops; + const struct dma_map_ops *dma_ops; #ifdef CONFIG_DMABOUNCE struct dmabounce_device_info *dmabounce; #endif diff --git a/arch/arm/include/asm/dma-contiguous.h b/arch/arm/include/asm/dma-contiguous.h index 4f8e9e5514b1..d54f8feec78f 100644 --- a/arch/arm/include/asm/dma-contiguous.h +++ b/arch/arm/include/asm/dma-contiguous.h @@ -1,14 +1,25 @@ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #ifndef ASMARM_DMA_CONTIGUOUS_H #define ASMARM_DMA_CONTIGUOUS_H #ifdef __KERNEL__ -#ifdef CONFIG_DMA_CMA #include <linux/types.h> void dma_contiguous_early_fixup(phys_addr_t base, unsigned long size); #endif -#endif #endif diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h index 2ef282f96651..74643f5b41c4 100644 --- a/arch/arm/include/asm/dma-iommu.h +++ b/arch/arm/include/asm/dma-iommu.h @@ -8,6 +8,7 @@ #include <linux/dma-debug.h> #include <linux/kmemcheck.h> #include <linux/kref.h> +#include <linux/dma-mapping-fast.h> struct dma_iommu_mapping { /* iommu specific data */ @@ -22,8 +23,12 @@ struct dma_iommu_mapping { spinlock_t lock; struct kref kref; + + struct dma_fast_smmu_mapping *fast; }; +#ifdef CONFIG_ARM_DMA_USE_IOMMU + struct dma_iommu_mapping * arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size); @@ -33,5 +38,29 @@ int arm_iommu_attach_device(struct device *dev, struct dma_iommu_mapping *mapping); void arm_iommu_detach_device(struct device *dev); +#else /* !CONFIG_ARM_DMA_USE_IOMMU */ + +static inline struct dma_iommu_mapping * +arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size) +{ + return NULL; +} + +static inline void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) +{ +} + +static inline int arm_iommu_attach_device(struct device *dev, + struct dma_iommu_mapping *mapping) +{ + return -ENODEV; +} + +static inline void arm_iommu_detach_device(struct device *dev) +{ +} + +#endif /* CONFIG_ARM_DMA_USE_IOMMU */ + #endif /* __KERNEL__ */ #endif diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index b91a2d17a521..c8bfa1aabd6a 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h @@ -17,14 +17,14 @@ extern struct dma_map_ops arm_dma_ops; extern struct dma_map_ops arm_coherent_dma_ops; -static inline struct dma_map_ops *__generic_dma_ops(struct device *dev) +static inline const struct dma_map_ops *__generic_dma_ops(struct device *dev) { if (dev && dev->archdata.dma_ops) return dev->archdata.dma_ops; return &arm_dma_ops; } -static inline struct dma_map_ops *get_dma_ops(struct device *dev) +static inline const struct dma_map_ops *get_dma_ops(struct device *dev) { if (xen_initial_domain()) return xen_dma_ops; @@ -32,7 +32,8 @@ static inline struct dma_map_ops *get_dma_ops(struct device *dev) return __generic_dma_ops(dev); } -static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops) +static inline void set_dma_ops(struct device *dev, + const struct dma_map_ops *ops) { BUG_ON(!dev); dev->archdata.dma_ops = ops; diff --git a/arch/arm/include/asm/etmv4x.h b/arch/arm/include/asm/etmv4x.h new file mode 100644 index 000000000000..5251d55df3b3 --- /dev/null +++ b/arch/arm/include/asm/etmv4x.h @@ -0,0 +1,387 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ETMV4X_H +#define __ASM_ETMV4X_H + +#include <linux/types.h> + + +/* 32 bit register read for AArch32 */ +#define trc_readl(reg) RSYSL_##reg() +#define trc_readq(reg) RSYSL_##reg() + +/* 32 bit register write for AArch32 */ +#define trc_write(val, reg) WSYS_##reg(val) + +#define MRC(op0, op1, crn, crm, op2) \ +({ \ +uint32_t val; \ +asm volatile("mrc p"#op0", "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \ +val; \ +}) + +#define MCR(val, op0, op1, crn, crm, op2) \ +({ \ +asm volatile("mcr p"#op0", "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\ +}) + +/* Clock and Power Management Register */ +#define RSYSL_CPMR_EL1() MRC(15, 7, c15, c0, 5) +#define WSYS_CPMR_EL1(val) MCR(val, 15, 7, c15, c0, 5) + +/* + * ETMv4 Registers + * + * Read only + * ETMAUTHSTATUS, ETMDEVARCH, ETMDEVID, ETMIDRn[0-13], ETMOSLSR, ETMSTATR + * + * Write only + * ETMOSLAR + */ +/* 32 bit registers */ +#define RSYSL_ETMAUTHSTATUS() MRC(14, 1, c7, c14, 6) +#define RSYSL_ETMAUXCTLR() MRC(14, 1, c0, c6, 0) +#define RSYSL_ETMCCCTLR() MRC(14, 1, c0, c14, 0) +#define RSYSL_ETMCIDCCTLR0() MRC(14, 1, c3, c0, 2) +#define RSYSL_ETMCNTCTLR0() MRC(14, 1, c0, c4, 5) +#define RSYSL_ETMCNTCTLR1() MRC(14, 1, c0, c5, 5) +#define RSYSL_ETMCNTCTLR2() MRC(14, 1, c0, c6, 5) +#define RSYSL_ETMCNTCTLR3() MRC(14, 1, c0, c7, 5) +#define RSYSL_ETMCNTRLDVR0() MRC(14, 1, c0, c0, 5) +#define RSYSL_ETMCNTRLDVR1() MRC(14, 1, c0, c1, 5) +#define RSYSL_ETMCNTRLDVR2() MRC(14, 1, c0, c2, 5) +#define RSYSL_ETMCNTRLDVR3() MRC(14, 1, c0, c3, 5) +#define RSYSL_ETMCNTVR0() MRC(14, 1, c0, c8, 5) +#define RSYSL_ETMCNTVR1() MRC(14, 1, c0, c9, 5) +#define RSYSL_ETMCNTVR2() MRC(14, 1, c0, c10, 5) +#define RSYSL_ETMCNTVR3() MRC(14, 1, c0, c11, 5) +#define RSYSL_ETMCONFIGR() MRC(14, 1, c0, c4, 0) +#define RSYSL_ETMDEVARCH() MRC(14, 1, c7, c15, 6) +#define RSYSL_ETMDEVID() MRC(14, 1, c7, c2, 7) +#define RSYSL_ETMEVENTCTL0R() MRC(14, 1, c0, c8, 0) +#define RSYSL_ETMEVENTCTL1R() MRC(14, 1, c0, c9, 0) +#define RSYSL_ETMEXTINSELR() MRC(14, 1, c0, c8, 4) +#define RSYSL_ETMIDR0() MRC(14, 1, c0, c8, 7) +#define RSYSL_ETMIDR1() MRC(14, 1, c0, c9, 7) +#define RSYSL_ETMIDR10() MRC(14, 1, c0, c2, 6) +#define RSYSL_ETMIDR11() MRC(14, 1, c0, c3, 6) +#define RSYSL_ETMIDR12() MRC(14, 1, c0, c4, 6) +#define RSYSL_ETMIDR13() MRC(14, 1, c0, c5, 6) +#define RSYSL_ETMIDR2() MRC(14, 1, c0, c10, 7) +#define RSYSL_ETMIDR3() MRC(14, 1, c0, c11, 7) +#define RSYSL_ETMIDR4() MRC(14, 1, c0, c12, 7) +#define RSYSL_ETMIDR5() MRC(14, 1, c0, c13, 7) +#define RSYSL_ETMIDR6() MRC(14, 1, c0, c14, 7) +#define RSYSL_ETMIDR7() MRC(14, 1, c0, c15, 7) +#define RSYSL_ETMIDR8() MRC(14, 1, c0, c0, 6) +#define RSYSL_ETMIDR9() MRC(14, 1, c0, c1, 6) +#define RSYSL_ETMIMSPEC0() MRC(14, 1, c0, c0, 7) +#define RSYSL_ETMOSLSR() MRC(14, 1, c1, c1, 4) +#define RSYSL_ETMPRGCTLR() MRC(14, 1, c0, c1, 0) +#define RSYSL_ETMRSCTLR10() MRC(14, 1, c1, c10, 0) +#define RSYSL_ETMRSCTLR11() MRC(14, 1, c1, c11, 0) +#define RSYSL_ETMRSCTLR12() MRC(14, 1, c1, c12, 0) +#define RSYSL_ETMRSCTLR13() MRC(14, 1, c1, c13, 0) +#define RSYSL_ETMRSCTLR14() MRC(14, 1, c1, c14, 0) +#define RSYSL_ETMRSCTLR15() MRC(14, 1, c1, c15, 0) +#define RSYSL_ETMRSCTLR2() MRC(14, 1, c1, c2, 0) +#define RSYSL_ETMRSCTLR3() MRC(14, 1, c1, c3, 0) +#define RSYSL_ETMRSCTLR4() MRC(14, 1, c1, c4, 0) +#define RSYSL_ETMRSCTLR5() MRC(14, 1, c1, c5, 0) +#define RSYSL_ETMRSCTLR6() MRC(14, 1, c1, c6, 0) +#define RSYSL_ETMRSCTLR7() MRC(14, 1, c1, c7, 0) +#define RSYSL_ETMRSCTLR8() MRC(14, 1, c1, c8, 0) +#define RSYSL_ETMRSCTLR9() MRC(14, 1, c1, c9, 0) +#define RSYSL_ETMRSCTLR16() MRC(14, 1, c1, c0, 1) +#define RSYSL_ETMRSCTLR17() MRC(14, 1, c1, c1, 1) +#define RSYSL_ETMRSCTLR18() MRC(14, 1, c1, c2, 1) +#define RSYSL_ETMRSCTLR19() MRC(14, 1, c1, c3, 1) +#define RSYSL_ETMRSCTLR20() MRC(14, 1, c1, c4, 1) +#define RSYSL_ETMRSCTLR21() MRC(14, 1, c1, c5, 1) +#define RSYSL_ETMRSCTLR22() MRC(14, 1, c1, c6, 1) +#define RSYSL_ETMRSCTLR23() MRC(14, 1, c1, c7, 1) +#define RSYSL_ETMRSCTLR24() MRC(14, 1, c1, c8, 1) +#define RSYSL_ETMRSCTLR25() MRC(14, 1, c1, c9, 1) +#define RSYSL_ETMRSCTLR26() MRC(14, 1, c1, c10, 1) +#define RSYSL_ETMRSCTLR27() MRC(14, 1, c1, c11, 1) +#define RSYSL_ETMRSCTLR28() MRC(14, 1, c1, c12, 1) +#define RSYSL_ETMRSCTLR29() MRC(14, 1, c1, c13, 1) +#define RSYSL_ETMRSCTLR30() MRC(14, 1, c1, c14, 1) +#define RSYSL_ETMRSCTLR31() MRC(14, 1, c1, c15, 1) +#define RSYSL_ETMSEQEVR0() MRC(14, 1, c0, c0, 4) +#define RSYSL_ETMSEQEVR1() MRC(14, 1, c0, c1, 4) +#define RSYSL_ETMSEQEVR2() MRC(14, 1, c0, c2, 4) +#define RSYSL_ETMSEQRSTEVR() MRC(14, 1, c0, c6, 4) +#define RSYSL_ETMSEQSTR() MRC(14, 1, c0, c7, 4) +#define RSYSL_ETMSTALLCTLR() MRC(14, 1, c0, c11, 0) +#define RSYSL_ETMSTATR() MRC(14, 1, c0, c3, 0) +#define RSYSL_ETMSYNCPR() MRC(14, 1, c0, c13, 0) +#define RSYSL_ETMTRACEIDR() MRC(14, 1, c0, c0, 1) +#define RSYSL_ETMTSCTLR() MRC(14, 1, c0, c12, 0) +#define RSYSL_ETMVICTLR() MRC(14, 1, c0, c0, 2) +#define RSYSL_ETMVIIECTLR() MRC(14, 1, c0, c1, 2) +#define RSYSL_ETMVISSCTLR() MRC(14, 1, c0, c2, 2) +#define RSYSL_ETMSSCCR0() MRC(14, 1, c1, c0, 2) +#define RSYSL_ETMSSCCR1() MRC(14, 1, c1, c1, 2) +#define RSYSL_ETMSSCCR2() MRC(14, 1, c1, c2, 2) +#define RSYSL_ETMSSCCR3() MRC(14, 1, c1, c3, 2) +#define RSYSL_ETMSSCCR4() MRC(14, 1, c1, c4, 2) +#define RSYSL_ETMSSCCR5() MRC(14, 1, c1, c5, 2) +#define RSYSL_ETMSSCCR6() MRC(14, 1, c1, c6, 2) +#define RSYSL_ETMSSCCR7() MRC(14, 1, c1, c7, 2) +#define RSYSL_ETMSSCSR0() MRC(14, 1, c1, c8, 2) +#define RSYSL_ETMSSCSR1() MRC(14, 1, c1, c9, 2) +#define RSYSL_ETMSSCSR2() MRC(14, 1, c1, c10, 2) +#define RSYSL_ETMSSCSR3() MRC(14, 1, c1, c11, 2) +#define RSYSL_ETMSSCSR4() MRC(14, 1, c1, c12, 2) +#define RSYSL_ETMSSCSR5() MRC(14, 1, c1, c13, 2) +#define RSYSL_ETMSSCSR6() MRC(14, 1, c1, c14, 2) +#define RSYSL_ETMSSCSR7() MRC(14, 1, c1, c15, 2) +#define RSYSL_ETMSSPCICR0() MRC(14, 1, c1, c0, 3) +#define RSYSL_ETMSSPCICR1() MRC(14, 1, c1, c1, 3) +#define RSYSL_ETMSSPCICR2() MRC(14, 1, c1, c2, 3) +#define RSYSL_ETMSSPCICR3() MRC(14, 1, c1, c3, 3) +#define RSYSL_ETMSSPCICR4() MRC(14, 1, c1, c4, 3) +#define RSYSL_ETMSSPCICR5() MRC(14, 1, c1, c5, 3) +#define RSYSL_ETMSSPCICR6() MRC(14, 1, c1, c6, 3) +#define RSYSL_ETMSSPCICR7() MRC(14, 1, c1, c7, 3) + +/* + * 64 bit registers, ignore the upper 32bit + * A read from a 32-bit register location using a 64-bit access result + * in the upper 32bits being return as RES0. + */ +#define RSYSL_ETMACATR0() MRC(14, 1, c2, c0, 2) +#define RSYSL_ETMACATR1() MRC(14, 1, c2, c2, 2) +#define RSYSL_ETMACATR2() MRC(14, 1, c2, c4, 2) +#define RSYSL_ETMACATR3() MRC(14, 1, c2, c6, 2) +#define RSYSL_ETMACATR4() MRC(14, 1, c2, c8, 2) +#define RSYSL_ETMACATR5() MRC(14, 1, c2, c10, 2) +#define RSYSL_ETMACATR6() MRC(14, 1, c2, c12, 2) +#define RSYSL_ETMACATR7() MRC(14, 1, c2, c14, 2) +#define RSYSL_ETMACATR8() MRC(14, 1, c2, c0, 3) +#define RSYSL_ETMACATR9() MRC(14, 1, c2, c2, 3) +#define RSYSL_ETMACATR10() MRC(14, 1, c2, c4, 3) +#define RSYSL_ETMACATR11() MRC(14, 1, c2, c6, 3) +#define RSYSL_ETMACATR12() MRC(14, 1, c2, c8, 3) +#define RSYSL_ETMACATR13() MRC(14, 1, c2, c10, 3) +#define RSYSL_ETMACATR14() MRC(14, 1, c2, c12, 3) +#define RSYSL_ETMACATR15() MRC(14, 1, c2, c14, 3) +#define RSYSL_ETMCIDCVR0() MRC(14, 1, c3, c0, 0) +#define RSYSL_ETMCIDCVR1() MRC(14, 1, c3, c2, 0) +#define RSYSL_ETMCIDCVR2() MRC(14, 1, c3, c4, 0) +#define RSYSL_ETMCIDCVR3() MRC(14, 1, c3, c6, 0) +#define RSYSL_ETMCIDCVR4() MRC(14, 1, c3, c8, 0) +#define RSYSL_ETMCIDCVR5() MRC(14, 1, c3, c10, 0) +#define RSYSL_ETMCIDCVR6() MRC(14, 1, c3, c12, 0) +#define RSYSL_ETMCIDCVR7() MRC(14, 1, c3, c14, 0) +#define RSYSL_ETMACVR0() MRC(14, 1, c2, c0, 0) +#define RSYSL_ETMACVR1() MRC(14, 1, c2, c2, 0) +#define RSYSL_ETMACVR2() MRC(14, 1, c2, c4, 0) +#define RSYSL_ETMACVR3() MRC(14, 1, c2, c6, 0) +#define RSYSL_ETMACVR4() MRC(14, 1, c2, c8, 0) +#define RSYSL_ETMACVR5() MRC(14, 1, c2, c10, 0) +#define RSYSL_ETMACVR6() MRC(14, 1, c2, c12, 0) +#define RSYSL_ETMACVR7() MRC(14, 1, c2, c14, 0) +#define RSYSL_ETMACVR8() MRC(14, 1, c2, c0, 1) +#define RSYSL_ETMACVR9() MRC(14, 1, c2, c2, 1) +#define RSYSL_ETMACVR10() MRC(14, 1, c2, c4, 1) +#define RSYSL_ETMACVR11() MRC(14, 1, c2, c6, 1) +#define RSYSL_ETMACVR12() MRC(14, 1, c2, c8, 1) +#define RSYSL_ETMACVR13() MRC(14, 1, c2, c10, 1) +#define RSYSL_ETMACVR14() MRC(14, 1, c2, c12, 1) +#define RSYSL_ETMACVR15() MRC(14, 1, c2, c14, 1) +#define RSYSL_ETMVMIDCVR0() MRC(14, 1, c3, c0, 1) +#define RSYSL_ETMVMIDCVR1() MRC(14, 1, c3, c2, 1) +#define RSYSL_ETMVMIDCVR2() MRC(14, 1, c3, c4, 1) +#define RSYSL_ETMVMIDCVR3() MRC(14, 1, c3, c6, 1) +#define RSYSL_ETMVMIDCVR4() MRC(14, 1, c3, c8, 1) +#define RSYSL_ETMVMIDCVR5() MRC(14, 1, c3, c10, 1) +#define RSYSL_ETMVMIDCVR6() MRC(14, 1, c3, c12, 1) +#define RSYSL_ETMVMIDCVR7() MRC(14, 1, c3, c14, 1) +#define RSYSL_ETMDVCVR0() MRC(14, 1, c2, c0, 4) +#define RSYSL_ETMDVCVR1() MRC(14, 1, c2, c4, 4) +#define RSYSL_ETMDVCVR2() MRC(14, 1, c2, c8, 4) +#define RSYSL_ETMDVCVR3() MRC(14, 1, c2, c12, 4) +#define RSYSL_ETMDVCVR4() MRC(14, 1, c2, c0, 5) +#define RSYSL_ETMDVCVR5() MRC(14, 1, c2, c4, 5) +#define RSYSL_ETMDVCVR6() MRC(14, 1, c2, c8, 5) +#define RSYSL_ETMDVCVR7() MRC(14, 1, c2, c12, 5) +#define RSYSL_ETMDVCMR0() MRC(14, 1, c2, c0, 6) +#define RSYSL_ETMDVCMR1() MRC(14, 1, c2, c4, 6) +#define RSYSL_ETMDVCMR2() MRC(14, 1, c2, c8, 6) +#define RSYSL_ETMDVCMR3() MRC(14, 1, c2, c12, 6) +#define RSYSL_ETMDVCMR4() MRC(14, 1, c2, c0, 7) +#define RSYSL_ETMDVCMR5() MRC(14, 1, c2, c4, 7) +#define RSYSL_ETMDVCMR6() MRC(14, 1, c2, c8, 7) +#define RSYSL_ETMDVCMR7() MRC(14, 1, c2, c12, 7) + +/* + * 32 and 64 bit registers + * A write to a 32-bit register location using a 64-bit access result + * in the upper 32bit of access + */ +#define WSYS_ETMAUXCTLR(val) MCR(val, 14, 1, c0, c6, 0) +#define WSYS_ETMACATR0(val) MCR(val, 14, 1, c2, c0, 2) +#define WSYS_ETMACATR1(val) MCR(val, 14, 1, c2, c2, 2) +#define WSYS_ETMACATR2(val) MCR(val, 14, 1, c2, c4, 2) +#define WSYS_ETMACATR3(val) MCR(val, 14, 1, c2, c6, 2) +#define WSYS_ETMACATR4(val) MCR(val, 14, 1, c2, c8, 2) +#define WSYS_ETMACATR5(val) MCR(val, 14, 1, c2, c10, 2) +#define WSYS_ETMACATR6(val) MCR(val, 14, 1, c2, c12, 2) +#define WSYS_ETMACATR7(val) MCR(val, 14, 1, c2, c14, 2) +#define WSYS_ETMACATR8(val) MCR(val, 14, 1, c2, c0, 3) +#define WSYS_ETMACATR9(val) MCR(val, 14, 1, c2, c2, 3) +#define WSYS_ETMACATR10(val) MCR(val, 14, 1, c2, c4, 3) +#define WSYS_ETMACATR11(val) MCR(val, 14, 1, c2, c6, 3) +#define WSYS_ETMACATR12(val) MCR(val, 14, 1, c2, c8, 3) +#define WSYS_ETMACATR13(val) MCR(val, 14, 1, c2, c10, 3) +#define WSYS_ETMACATR14(val) MCR(val, 14, 1, c2, c12, 3) +#define WSYS_ETMACATR15(val) MCR(val, 14, 1, c2, c14, 3) +#define WSYS_ETMACVR0(val) MCR(val, 14, 1, c2, c0, 0) +#define WSYS_ETMACVR1(val) MCR(val, 14, 1, c2, c2, 0) +#define WSYS_ETMACVR2(val) MCR(val, 14, 1, c2, c4, 0) +#define WSYS_ETMACVR3(val) MCR(val, 14, 1, c2, c6, 0) +#define WSYS_ETMACVR4(val) MCR(val, 14, 1, c2, c8, 0) +#define WSYS_ETMACVR5(val) MCR(val, 14, 1, c2, c10, 0) +#define WSYS_ETMACVR6(val) MCR(val, 14, 1, c2, c12, 0) +#define WSYS_ETMACVR7(val) MCR(val, 14, 1, c2, c14, 0) +#define WSYS_ETMACVR8(val) MCR(val, 14, 1, c2, c0, 1) +#define WSYS_ETMACVR9(val) MCR(val, 14, 1, c2, c2, 1) +#define WSYS_ETMACVR10(val) MCR(val, 14, 1, c2, c4, 1) +#define WSYS_ETMACVR11(val) MCR(val, 14, 1, c2, c6, 1) +#define WSYS_ETMACVR12(val) MCR(val, 14, 1, c2, c8, 1) +#define WSYS_ETMACVR13(val) MCR(val, 14, 1, c2, c10, 1) +#define WSYS_ETMACVR14(val) MCR(val, 14, 1, c2, c12, 1) +#define WSYS_ETMACVR15(val) MCR(val, 14, 1, c2, c14, 1) +#define WSYS_ETMCCCTLR(val) MCR(val, 14, 1, c0, c14, 0) +#define WSYS_ETMCIDCCTLR0(val) MCR(val, 14, 1, c3, c0, 2) +#define WSYS_ETMCIDCVR0(val) MCR(val, 14, 1, c3, c0, 0) +#define WSYS_ETMCIDCVR1(val) MCR(val, 14, 1, c3, c2, 0) +#define WSYS_ETMCIDCVR2(val) MCR(val, 14, 1, c3, c4, 0) +#define WSYS_ETMCIDCVR3(val) MCR(val, 14, 1, c3, c6, 0) +#define WSYS_ETMCIDCVR4(val) MCR(val, 14, 1, c3, c8, 0) +#define WSYS_ETMCIDCVR5(val) MCR(val, 14, 1, c3, c10, 0) +#define WSYS_ETMCIDCVR6(val) MCR(val, 14, 1, c3, c12, 0) +#define WSYS_ETMCIDCVR7(val) MCR(val, 14, 1, c3, c14, 0) +#define WSYS_ETMCNTCTLR0(val) MCR(val, 14, 1, c0, c4, 5) +#define WSYS_ETMCNTCTLR1(val) MCR(val, 14, 1, c0, c5, 5) +#define WSYS_ETMCNTCTLR2(val) MCR(val, 14, 1, c0, c6, 5) +#define WSYS_ETMCNTCTLR3(val) MCR(val, 14, 1, c0, c7, 5) +#define WSYS_ETMCNTRLDVR0(val) MCR(val, 14, 1, c0, c0, 5) +#define WSYS_ETMCNTRLDVR1(val) MCR(val, 14, 1, c0, c1, 5) +#define WSYS_ETMCNTRLDVR2(val) MCR(val, 14, 1, c0, c2, 5) +#define WSYS_ETMCNTRLDVR3(val) MCR(val, 14, 1, c0, c3, 5) +#define WSYS_ETMCNTVR0(val) MCR(val, 14, 1, c0, c8, 5) +#define WSYS_ETMCNTVR1(val) MCR(val, 14, 1, c0, c9, 5) +#define WSYS_ETMCNTVR2(val) MCR(val, 14, 1, c0, c10, 5) +#define WSYS_ETMCNTVR3(val) MCR(val, 14, 1, c0, c11, 5) +#define WSYS_ETMCONFIGR(val) MCR(val, 14, 1, c0, c4, 0) +#define WSYS_ETMEVENTCTL0R(val) MCR(val, 14, 1, c0, c8, 0) +#define WSYS_ETMEVENTCTL1R(val) MCR(val, 14, 1, c0, c9, 0) +#define WSYS_ETMEXTINSELR(val) MCR(val, 14, 1, c0, c8, 4) +#define WSYS_ETMIMSPEC0(val) MCR(val, 14, 1, c0, c0, 7) +#define WSYS_ETMOSLAR(val) MCR(val, 14, 1, c1, c0, 4) +#define WSYS_ETMPRGCTLR(val) MCR(val, 14, 1, c0, c1, 0) +#define WSYS_ETMRSCTLR10(val) MCR(val, 14, 1, c1, c10, 0) +#define WSYS_ETMRSCTLR11(val) MCR(val, 14, 1, c1, c11, 0) +#define WSYS_ETMRSCTLR12(val) MCR(val, 14, 1, c1, c12, 0) +#define WSYS_ETMRSCTLR13(val) MCR(val, 14, 1, c1, c13, 0) +#define WSYS_ETMRSCTLR14(val) MCR(val, 14, 1, c1, c14, 0) +#define WSYS_ETMRSCTLR15(val) MCR(val, 14, 1, c1, c15, 0) +#define WSYS_ETMRSCTLR2(val) MCR(val, 14, 1, c1, c2, 0) +#define WSYS_ETMRSCTLR3(val) MCR(val, 14, 1, c1, c3, 0) +#define WSYS_ETMRSCTLR4(val) MCR(val, 14, 1, c1, c4, 0) +#define WSYS_ETMRSCTLR5(val) MCR(val, 14, 1, c1, c5, 0) +#define WSYS_ETMRSCTLR6(val) MCR(val, 14, 1, c1, c6, 0) +#define WSYS_ETMRSCTLR7(val) MCR(val, 14, 1, c1, c7, 0) +#define WSYS_ETMRSCTLR8(val) MCR(val, 14, 1, c1, c8, 0) +#define WSYS_ETMRSCTLR9(val) MCR(val, 14, 1, c1, c9, 0) +#define WSYS_ETMRSCTLR16(val) MCR(val, 14, 1, c1, c0, 1) +#define WSYS_ETMRSCTLR17(val) MCR(val, 14, 1, c1, c1, 1) +#define WSYS_ETMRSCTLR18(val) MCR(val, 14, 1, c1, c2, 1) +#define WSYS_ETMRSCTLR19(val) MCR(val, 14, 1, c1, c3, 1) +#define WSYS_ETMRSCTLR20(val) MCR(val, 14, 1, c1, c4, 1) +#define WSYS_ETMRSCTLR21(val) MCR(val, 14, 1, c1, c5, 1) +#define WSYS_ETMRSCTLR22(val) MCR(val, 14, 1, c1, c6, 1) +#define WSYS_ETMRSCTLR23(val) MCR(val, 14, 1, c1, c7, 1) +#define WSYS_ETMRSCTLR24(val) MCR(val, 14, 1, c1, c8, 1) +#define WSYS_ETMRSCTLR25(val) MCR(val, 14, 1, c1, c9, 1) +#define WSYS_ETMRSCTLR26(val) MCR(val, 14, 1, c1, c10, 1) +#define WSYS_ETMRSCTLR27(val) MCR(val, 14, 1, c1, c11, 1) +#define WSYS_ETMRSCTLR28(val) MCR(val, 14, 1, c1, c12, 1) +#define WSYS_ETMRSCTLR29(val) MCR(val, 14, 1, c1, c13, 1) +#define WSYS_ETMRSCTLR30(val) MCR(val, 14, 1, c1, c14, 1) +#define WSYS_ETMRSCTLR31(val) MCR(val, 14, 1, c1, c15, 1) +#define WSYS_ETMSEQEVR0(val) MCR(val, 14, 1, c0, c0, 4) +#define WSYS_ETMSEQEVR1(val) MCR(val, 14, 1, c0, c1, 4) +#define WSYS_ETMSEQEVR2(val) MCR(val, 14, 1, c0, c2, 4) +#define WSYS_ETMSEQRSTEVR(val) MCR(val, 14, 1, c0, c6, 4) +#define WSYS_ETMSEQSTR(val) MCR(val, 14, 1, c0, c7, 4) +#define WSYS_ETMSTALLCTLR(val) MCR(val, 14, 1, c0, c11, 0) +#define WSYS_ETMSYNCPR(val) MCR(val, 14, 1, c0, c13, 0) +#define WSYS_ETMTRACEIDR(val) MCR(val, 14, 1, c0, c0, 1) +#define WSYS_ETMTSCTLR(val) MCR(val, 14, 1, c0, c12, 0) +#define WSYS_ETMVICTLR(val) MCR(val, 14, 1, c0, c0, 2) +#define WSYS_ETMVIIECTLR(val) MCR(val, 14, 1, c0, c1, 2) +#define WSYS_ETMVISSCTLR(val) MCR(val, 14, 1, c0, c2, 2) +#define WSYS_ETMVMIDCVR0(val) MCR(val, 14, 1, c3, c0, 1) +#define WSYS_ETMVMIDCVR1(val) MCR(val, 14, 1, c3, c2, 1) +#define WSYS_ETMVMIDCVR2(val) MCR(val, 14, 1, c3, c4, 1) +#define WSYS_ETMVMIDCVR3(val) MCR(val, 14, 1, c3, c6, 1) +#define WSYS_ETMVMIDCVR4(val) MCR(val, 14, 1, c3, c8, 1) +#define WSYS_ETMVMIDCVR5(val) MCR(val, 14, 1, c3, c10, 1) +#define WSYS_ETMVMIDCVR6(val) MCR(val, 14, 1, c3, c12, 1) +#define WSYS_ETMVMIDCVR7(val) MCR(val, 14, 1, c3, c14, 1) +#define WSYS_ETMDVCVR0(val) MCR(val, 14, 1, c2, c0, 4) +#define WSYS_ETMDVCVR1(val) MCR(val, 14, 1, c2, c4, 4) +#define WSYS_ETMDVCVR2(val) MCR(val, 14, 1, c2, c8, 4) +#define WSYS_ETMDVCVR3(val) MCR(val, 14, 1, c2, c12, 4) +#define WSYS_ETMDVCVR4(val) MCR(val, 14, 1, c2, c0, 5) +#define WSYS_ETMDVCVR5(val) MCR(val, 14, 1, c2, c4, 5) +#define WSYS_ETMDVCVR6(val) MCR(val, 14, 1, c2, c8, 5) +#define WSYS_ETMDVCVR7(val) MCR(val, 14, 1, c2, c12, 5) +#define WSYS_ETMDVCMR0(val) MCR(val, 14, 1, c2, c0, 6) +#define WSYS_ETMDVCMR1(val) MCR(val, 14, 1, c2, c4, 6) +#define WSYS_ETMDVCMR2(val) MCR(val, 14, 1, c2, c8, 6) +#define WSYS_ETMDVCMR3(val) MCR(val, 14, 1, c2, c12, 6) +#define WSYS_ETMDVCMR4(val) MCR(val, 14, 1, c2, c0, 7) +#define WSYS_ETMDVCMR5(val) MCR(val, 14, 1, c2, c4, 7) +#define WSYS_ETMDVCMR6(val) MCR(val, 14, 1, c2, c8, 7) +#define WSYS_ETMDVCMR7(val) MCR(val, 14, 1, c2, c12, 7) +#define WSYS_ETMSSCCR0(val) MCR(val, 14, 1, c1, c0, 2) +#define WSYS_ETMSSCCR1(val) MCR(val, 14, 1, c1, c1, 2) +#define WSYS_ETMSSCCR2(val) MCR(val, 14, 1, c1, c2, 2) +#define WSYS_ETMSSCCR3(val) MCR(val, 14, 1, c1, c3, 2) +#define WSYS_ETMSSCCR4(val) MCR(val, 14, 1, c1, c4, 2) +#define WSYS_ETMSSCCR5(val) MCR(val, 14, 1, c1, c5, 2) +#define WSYS_ETMSSCCR6(val) MCR(val, 14, 1, c1, c6, 2) +#define WSYS_ETMSSCCR7(val) MCR(val, 14, 1, c1, c7, 2) +#define WSYS_ETMSSCSR0(val) MCR(val, 14, 1, c1, c8, 2) +#define WSYS_ETMSSCSR1(val) MCR(val, 14, 1, c1, c9, 2) +#define WSYS_ETMSSCSR2(val) MCR(val, 14, 1, c1, c10, 2) +#define WSYS_ETMSSCSR3(val) MCR(val, 14, 1, c1, c11, 2) +#define WSYS_ETMSSCSR4(val) MCR(val, 14, 1, c1, c12, 2) +#define WSYS_ETMSSCSR5(val) MCR(val, 14, 1, c1, c13, 2) +#define WSYS_ETMSSCSR6(val) MCR(val, 14, 1, c1, c14, 2) +#define WSYS_ETMSSCSR7(val) MCR(val, 14, 1, c1, c15, 2) +#define WSYS_ETMSSPCICR0(val) MCR(val, 14, 1, c1, c0, 3) +#define WSYS_ETMSSPCICR1(val) MCR(val, 14, 1, c1, c1, 3) +#define WSYS_ETMSSPCICR2(val) MCR(val, 14, 1, c1, c2, 3) +#define WSYS_ETMSSPCICR3(val) MCR(val, 14, 1, c1, c3, 3) +#define WSYS_ETMSSPCICR4(val) MCR(val, 14, 1, c1, c4, 3) +#define WSYS_ETMSSPCICR5(val) MCR(val, 14, 1, c1, c5, 3) +#define WSYS_ETMSSPCICR6(val) MCR(val, 14, 1, c1, c6, 3) +#define WSYS_ETMSSPCICR7(val) MCR(val, 14, 1, c1, c7, 3) + +#endif diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h index cab07f69382d..7a4893e61866 100644 --- a/arch/arm/include/asm/glue-cache.h +++ b/arch/arm/include/asm/glue-cache.h @@ -159,6 +159,14 @@ static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { } #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) #define dmac_flush_range __glue(_CACHE,_dma_flush_range) +#define dmac_inv_range __glue(_CACHE, _dma_inv_range) +#define dmac_clean_range __glue(_CACHE, _dma_clean_range) +#define dmac_map_area __glue(_CACHE, _dma_map_area) +#define dmac_unmap_area __glue(_CACHE, _dma_unmap_area) + +#define __dma_map_area dmac_map_area +#define __dma_unmap_area dmac_unmap_area +#define __dma_flush_range dmac_flush_range #endif #endif diff --git a/arch/arm/include/asm/hardware/debugv8.h b/arch/arm/include/asm/hardware/debugv8.h new file mode 100644 index 000000000000..054226cbe7ce --- /dev/null +++ b/arch/arm/include/asm/hardware/debugv8.h @@ -0,0 +1,247 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_HARDWARE_DEBUGV8_H +#define __ASM_HARDWARE_DEBUGV8_H + +#include <linux/types.h> + +/* Accessors for CP14 registers */ +#define dbg_read(reg) RCP14_##reg() +#define dbg_write(val, reg) WCP14_##reg(val) + +/* MRC14 registers */ +#define MRC14(op1, crn, crm, op2) \ +({ \ +uint32_t val; \ +asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \ +val; \ +}) + +/* MCR14 registers */ +#define MCR14(val, op1, crn, crm, op2) \ +({ \ +asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\ +}) + +/* + * Debug Registers + * + * Read only + * DBGDIDR, DBGDSCRint, DBGDTRRXint, DBGDRAR, DBGOSLSR, DBGOSSRR, DBGDSAR, + * DBGAUTHSTATUS, DBGDEVID2, DBGDEVID1, DBGDEVID + * + * Write only + * DBGDTRTXint, DBGOSLAR + */ +#define RCP14_DBGDIDR() MRC14(0, c0, c0, 0) +#define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0) +#define RCP14_DBGDCCINT() MRC14(0, c0, c2, 0) +#define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0) +#define RCP14_DBGWFAR() MRC14(0, c0, c6, 0) +#define RCP14_DBGVCR() MRC14(0, c0, c7, 0) +#define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2) +#define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2) +#define RCP14_DBGDTRTXext() MRC14(0, c0, c3, 2) +#define RCP14_DBGOSECCR() MRC14(0, c0, c6, 2) +#define RCP14_DBGBVR0() MRC14(0, c0, c0, 4) +#define RCP14_DBGBVR1() MRC14(0, c0, c1, 4) +#define RCP14_DBGBVR2() MRC14(0, c0, c2, 4) +#define RCP14_DBGBVR3() MRC14(0, c0, c3, 4) +#define RCP14_DBGBVR4() MRC14(0, c0, c4, 4) +#define RCP14_DBGBVR5() MRC14(0, c0, c5, 4) +#define RCP14_DBGBVR6() MRC14(0, c0, c6, 4) +#define RCP14_DBGBVR7() MRC14(0, c0, c7, 4) +#define RCP14_DBGBVR8() MRC14(0, c0, c8, 4) +#define RCP14_DBGBVR9() MRC14(0, c0, c9, 4) +#define RCP14_DBGBVR10() MRC14(0, c0, c10, 4) +#define RCP14_DBGBVR11() MRC14(0, c0, c11, 4) +#define RCP14_DBGBVR12() MRC14(0, c0, c12, 4) +#define RCP14_DBGBVR13() MRC14(0, c0, c13, 4) +#define RCP14_DBGBVR14() MRC14(0, c0, c14, 4) +#define RCP14_DBGBVR15() MRC14(0, c0, c15, 4) +#define RCP14_DBGBCR0() MRC14(0, c0, c0, 5) +#define RCP14_DBGBCR1() MRC14(0, c0, c1, 5) +#define RCP14_DBGBCR2() MRC14(0, c0, c2, 5) +#define RCP14_DBGBCR3() MRC14(0, c0, c3, 5) +#define RCP14_DBGBCR4() MRC14(0, c0, c4, 5) +#define RCP14_DBGBCR5() MRC14(0, c0, c5, 5) +#define RCP14_DBGBCR6() MRC14(0, c0, c6, 5) +#define RCP14_DBGBCR7() MRC14(0, c0, c7, 5) +#define RCP14_DBGBCR8() MRC14(0, c0, c8, 5) +#define RCP14_DBGBCR9() MRC14(0, c0, c9, 5) +#define RCP14_DBGBCR10() MRC14(0, c0, c10, 5) +#define RCP14_DBGBCR11() MRC14(0, c0, c11, 5) +#define RCP14_DBGBCR12() MRC14(0, c0, c12, 5) +#define RCP14_DBGBCR13() MRC14(0, c0, c13, 5) +#define RCP14_DBGBCR14() MRC14(0, c0, c14, 5) +#define RCP14_DBGBCR15() MRC14(0, c0, c15, 5) +#define RCP14_DBGWVR0() MRC14(0, c0, c0, 6) +#define RCP14_DBGWVR1() MRC14(0, c0, c1, 6) +#define RCP14_DBGWVR2() MRC14(0, c0, c2, 6) +#define RCP14_DBGWVR3() MRC14(0, c0, c3, 6) +#define RCP14_DBGWVR4() MRC14(0, c0, c4, 6) +#define RCP14_DBGWVR5() MRC14(0, c0, c5, 6) +#define RCP14_DBGWVR6() MRC14(0, c0, c6, 6) +#define RCP14_DBGWVR7() MRC14(0, c0, c7, 6) +#define RCP14_DBGWVR8() MRC14(0, c0, c8, 6) +#define RCP14_DBGWVR9() MRC14(0, c0, c9, 6) +#define RCP14_DBGWVR10() MRC14(0, c0, c10, 6) +#define RCP14_DBGWVR11() MRC14(0, c0, c11, 6) +#define RCP14_DBGWVR12() MRC14(0, c0, c12, 6) +#define RCP14_DBGWVR13() MRC14(0, c0, c13, 6) +#define RCP14_DBGWVR14() MRC14(0, c0, c14, 6) +#define RCP14_DBGWVR15() MRC14(0, c0, c15, 6) +#define RCP14_DBGWCR0() MRC14(0, c0, c0, 7) +#define RCP14_DBGWCR1() MRC14(0, c0, c1, 7) +#define RCP14_DBGWCR2() MRC14(0, c0, c2, 7) +#define RCP14_DBGWCR3() MRC14(0, c0, c3, 7) +#define RCP14_DBGWCR4() MRC14(0, c0, c4, 7) +#define RCP14_DBGWCR5() MRC14(0, c0, c5, 7) +#define RCP14_DBGWCR6() MRC14(0, c0, c6, 7) +#define RCP14_DBGWCR7() MRC14(0, c0, c7, 7) +#define RCP14_DBGWCR8() MRC14(0, c0, c8, 7) +#define RCP14_DBGWCR9() MRC14(0, c0, c9, 7) +#define RCP14_DBGWCR10() MRC14(0, c0, c10, 7) +#define RCP14_DBGWCR11() MRC14(0, c0, c11, 7) +#define RCP14_DBGWCR12() MRC14(0, c0, c12, 7) +#define RCP14_DBGWCR13() MRC14(0, c0, c13, 7) +#define RCP14_DBGWCR14() MRC14(0, c0, c14, 7) +#define RCP14_DBGWCR15() MRC14(0, c0, c15, 7) +#define RCP14_DBGDRAR() MRC14(0, c1, c0, 0) +#define RCP14_DBGBXVR0() MRC14(0, c1, c0, 1) +#define RCP14_DBGBXVR1() MRC14(0, c1, c1, 1) +#define RCP14_DBGBXVR2() MRC14(0, c1, c2, 1) +#define RCP14_DBGBXVR3() MRC14(0, c1, c3, 1) +#define RCP14_DBGBXVR4() MRC14(0, c1, c4, 1) +#define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1) +#define RCP14_DBGBXVR6() MRC14(0, c1, c6, 1) +#define RCP14_DBGBXVR7() MRC14(0, c1, c7, 1) +#define RCP14_DBGBXVR8() MRC14(0, c1, c8, 1) +#define RCP14_DBGBXVR9() MRC14(0, c1, c9, 1) +#define RCP14_DBGBXVR10() MRC14(0, c1, c10, 1) +#define RCP14_DBGBXVR11() MRC14(0, c1, c11, 1) +#define RCP14_DBGBXVR12() MRC14(0, c1, c12, 1) +#define RCP14_DBGBXVR13() MRC14(0, c1, c13, 1) +#define RCP14_DBGBXVR14() MRC14(0, c1, c14, 1) +#define RCP14_DBGBXVR15() MRC14(0, c1, c15, 1) +#define RCP14_DBGOSLSR() MRC14(0, c1, c1, 4) +#define RCP14_DBGOSSRR() MRC14(0, c1, c2, 4) +#define RCP14_DBGOSDLR() MRC14(0, c1, c3, 4) +#define RCP14_DBGPRCR() MRC14(0, c1, c4, 4) +#define RCP14_DBGPRSR() MRC14(0, c1, c5, 4) +#define RCP14_DBGDSAR() MRC14(0, c2, c0, 0) +#define RCP14_DBGITCTRL() MRC14(0, c7, c0, 4) +#define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6) +#define RCP14_DBGCLAIMCLR() MRC14(0, c7, c9, 6) +#define RCP14_DBGAUTHSTATUS() MRC14(0, c7, c14, 6) +#define RCP14_DBGDEVID2() MRC14(0, c7, c0, 7) +#define RCP14_DBGDEVID1() MRC14(0, c7, c1, 7) +#define RCP14_DBGDEVID() MRC14(0, c7, c2, 7) + +#define WCP14_DBGDCCINT(val) MCR14(val, 0, c0, c2, 0) +#define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) +#define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) +#define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) +#define WCP14_DBGDTRRXext(val) MCR14(val, 0, c0, c0, 2) +#define WCP14_DBGDSCRext(val) MCR14(val, 0, c0, c2, 2) +#define WCP14_DBGDTRTXext(val) MCR14(val, 0, c0, c3, 2) +#define WCP14_DBGOSECCR(val) MCR14(val, 0, c0, c6, 2) +#define WCP14_DBGBVR0(val) MCR14(val, 0, c0, c0, 4) +#define WCP14_DBGBVR1(val) MCR14(val, 0, c0, c1, 4) +#define WCP14_DBGBVR2(val) MCR14(val, 0, c0, c2, 4) +#define WCP14_DBGBVR3(val) MCR14(val, 0, c0, c3, 4) +#define WCP14_DBGBVR4(val) MCR14(val, 0, c0, c4, 4) +#define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4) +#define WCP14_DBGBVR6(val) MCR14(val, 0, c0, c6, 4) +#define WCP14_DBGBVR7(val) MCR14(val, 0, c0, c7, 4) +#define WCP14_DBGBVR8(val) MCR14(val, 0, c0, c8, 4) +#define WCP14_DBGBVR9(val) MCR14(val, 0, c0, c9, 4) +#define WCP14_DBGBVR10(val) MCR14(val, 0, c0, c10, 4) +#define WCP14_DBGBVR11(val) MCR14(val, 0, c0, c11, 4) +#define WCP14_DBGBVR12(val) MCR14(val, 0, c0, c12, 4) +#define WCP14_DBGBVR13(val) MCR14(val, 0, c0, c13, 4) +#define WCP14_DBGBVR14(val) MCR14(val, 0, c0, c14, 4) +#define WCP14_DBGBVR15(val) MCR14(val, 0, c0, c15, 4) +#define WCP14_DBGBCR0(val) MCR14(val, 0, c0, c0, 5) +#define WCP14_DBGBCR1(val) MCR14(val, 0, c0, c1, 5) +#define WCP14_DBGBCR2(val) MCR14(val, 0, c0, c2, 5) +#define WCP14_DBGBCR3(val) MCR14(val, 0, c0, c3, 5) +#define WCP14_DBGBCR4(val) MCR14(val, 0, c0, c4, 5) +#define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5) +#define WCP14_DBGBCR6(val) MCR14(val, 0, c0, c6, 5) +#define WCP14_DBGBCR7(val) MCR14(val, 0, c0, c7, 5) +#define WCP14_DBGBCR8(val) MCR14(val, 0, c0, c8, 5) +#define WCP14_DBGBCR9(val) MCR14(val, 0, c0, c9, 5) +#define WCP14_DBGBCR10(val) MCR14(val, 0, c0, c10, 5) +#define WCP14_DBGBCR11(val) MCR14(val, 0, c0, c11, 5) +#define WCP14_DBGBCR12(val) MCR14(val, 0, c0, c12, 5) +#define WCP14_DBGBCR13(val) MCR14(val, 0, c0, c13, 5) +#define WCP14_DBGBCR14(val) MCR14(val, 0, c0, c14, 5) +#define WCP14_DBGBCR15(val) MCR14(val, 0, c0, c15, 5) +#define WCP14_DBGWVR0(val) MCR14(val, 0, c0, c0, 6) +#define WCP14_DBGWVR1(val) MCR14(val, 0, c0, c1, 6) +#define WCP14_DBGWVR2(val) MCR14(val, 0, c0, c2, 6) +#define WCP14_DBGWVR3(val) MCR14(val, 0, c0, c3, 6) +#define WCP14_DBGWVR4(val) MCR14(val, 0, c0, c4, 6) +#define WCP14_DBGWVR5(val) MCR14(val, 0, c0, c5, 6) +#define WCP14_DBGWVR6(val) MCR14(val, 0, c0, c6, 6) +#define WCP14_DBGWVR7(val) MCR14(val, 0, c0, c7, 6) +#define WCP14_DBGWVR8(val) MCR14(val, 0, c0, c8, 6) +#define WCP14_DBGWVR9(val) MCR14(val, 0, c0, c9, 6) +#define WCP14_DBGWVR10(val) MCR14(val, 0, c0, c10, 6) +#define WCP14_DBGWVR11(val) MCR14(val, 0, c0, c11, 6) +#define WCP14_DBGWVR12(val) MCR14(val, 0, c0, c12, 6) +#define WCP14_DBGWVR13(val) MCR14(val, 0, c0, c13, 6) +#define WCP14_DBGWVR14(val) MCR14(val, 0, c0, c14, 6) +#define WCP14_DBGWVR15(val) MCR14(val, 0, c0, c15, 6) +#define WCP14_DBGWCR0(val) MCR14(val, 0, c0, c0, 7) +#define WCP14_DBGWCR1(val) MCR14(val, 0, c0, c1, 7) +#define WCP14_DBGWCR2(val) MCR14(val, 0, c0, c2, 7) +#define WCP14_DBGWCR3(val) MCR14(val, 0, c0, c3, 7) +#define WCP14_DBGWCR4(val) MCR14(val, 0, c0, c4, 7) +#define WCP14_DBGWCR5(val) MCR14(val, 0, c0, c5, 7) +#define WCP14_DBGWCR6(val) MCR14(val, 0, c0, c6, 7) +#define WCP14_DBGWCR7(val) MCR14(val, 0, c0, c7, 7) +#define WCP14_DBGWCR8(val) MCR14(val, 0, c0, c8, 7) +#define WCP14_DBGWCR9(val) MCR14(val, 0, c0, c9, 7) +#define WCP14_DBGWCR10(val) MCR14(val, 0, c0, c10, 7) +#define WCP14_DBGWCR11(val) MCR14(val, 0, c0, c11, 7) +#define WCP14_DBGWCR12(val) MCR14(val, 0, c0, c12, 7) +#define WCP14_DBGWCR13(val) MCR14(val, 0, c0, c13, 7) +#define WCP14_DBGWCR14(val) MCR14(val, 0, c0, c14, 7) +#define WCP14_DBGWCR15(val) MCR14(val, 0, c0, c15, 7) +#define WCP14_DBGBXVR0(val) MCR14(val, 0, c1, c0, 1) +#define WCP14_DBGBXVR1(val) MCR14(val, 0, c1, c1, 1) +#define WCP14_DBGBXVR2(val) MCR14(val, 0, c1, c2, 1) +#define WCP14_DBGBXVR3(val) MCR14(val, 0, c1, c3, 1) +#define WCP14_DBGBXVR4(val) MCR14(val, 0, c1, c4, 1) +#define WCP14_DBGBXVR5(val) MCR14(val, 0, c1, c5, 1) +#define WCP14_DBGBXVR6(val) MCR14(val, 0, c1, c6, 1) +#define WCP14_DBGBXVR7(val) MCR14(val, 0, c1, c7, 1) +#define WCP14_DBGBXVR8(val) MCR14(val, 0, c1, c8, 1) +#define WCP14_DBGBXVR9(val) MCR14(val, 0, c1, c9, 1) +#define WCP14_DBGBXVR10(val) MCR14(val, 0, c1, c10, 1) +#define WCP14_DBGBXVR11(val) MCR14(val, 0, c1, c11, 1) +#define WCP14_DBGBXVR12(val) MCR14(val, 0, c1, c12, 1) +#define WCP14_DBGBXVR13(val) MCR14(val, 0, c1, c13, 1) +#define WCP14_DBGBXVR14(val) MCR14(val, 0, c1, c14, 1) +#define WCP14_DBGBXVR15(val) MCR14(val, 0, c1, c15, 1) +#define WCP14_DBGOSLAR(val) MCR14(val, 0, c1, c0, 4) +#define WCP14_DBGOSSRR(val) MCR14(val, 0, c1, c2, 4) +#define WCP14_DBGOSDLR(val) MCR14(val, 0, c1, c3, 4) +#define WCP14_DBGPRCR(val) MCR14(val, 0, c1, c4, 4) +#define WCP14_DBGITCTRL(val) MCR14(val, 0, c7, c0, 4) +#define WCP14_DBGCLAIMSET(val) MCR14(val, 0, c7, c8, 6) +#define WCP14_DBGCLAIMCLR(val) MCR14(val, 0, c7, c9, 6) + +#endif diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 485982084fe9..c5d7c8b995eb 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -29,6 +29,7 @@ #include <asm/byteorder.h> #include <asm/memory.h> #include <asm-generic/pci_iomap.h> +#include <linux/msm_rtb.h> #include <xen/xen.h> /* @@ -62,23 +63,21 @@ void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen); * the bus. Rather than special-case the machine, just let the compiler * generate the access for CPUs prior to ARMv6. */ -#define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) -#define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))) +#define __raw_readw_no_log(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) +#define __raw_writew_no_log(v, a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))) #else /* * When running under a hypervisor, we want to avoid I/O accesses with * writeback addressing modes as these incur a significant performance * overhead (the address generation must be emulated in software). */ -#define __raw_writew __raw_writew -static inline void __raw_writew(u16 val, volatile void __iomem *addr) +static inline void __raw_writew_no_log(u16 val, volatile void __iomem *addr) { asm volatile("strh %1, %0" : : "Q" (*(volatile u16 __force *)addr), "r" (val)); } -#define __raw_readw __raw_readw -static inline u16 __raw_readw(const volatile void __iomem *addr) +static inline u16 __raw_readw_no_log(const volatile void __iomem *addr) { u16 val; asm volatile("ldrh %0, %1" @@ -88,22 +87,30 @@ static inline u16 __raw_readw(const volatile void __iomem *addr) } #endif -#define __raw_writeb __raw_writeb -static inline void __raw_writeb(u8 val, volatile void __iomem *addr) +static inline void __raw_writeb_no_log(u8 val, volatile void __iomem *addr) { asm volatile("strb %1, %0" : : "Qo" (*(volatile u8 __force *)addr), "r" (val)); } -#define __raw_writel __raw_writel -static inline void __raw_writel(u32 val, volatile void __iomem *addr) +static inline void __raw_writel_no_log(u32 val, volatile void __iomem *addr) { asm volatile("str %1, %0" : : "Qo" (*(volatile u32 __force *)addr), "r" (val)); } -#define __raw_readb __raw_readb -static inline u8 __raw_readb(const volatile void __iomem *addr) +static inline void __raw_writeq_no_log(u64 val, volatile void __iomem *addr) +{ + register u64 v asm ("r2"); + + v = val; + + asm volatile("strd %1, %0" + : "+Qo" (*(volatile u64 __force *)addr) + : "r" (v)); +} + +static inline u8 __raw_readb_no_log(const volatile void __iomem *addr) { u8 val; asm volatile("ldrb %0, %1" @@ -112,8 +119,7 @@ static inline u8 __raw_readb(const volatile void __iomem *addr) return val; } -#define __raw_readl __raw_readl -static inline u32 __raw_readl(const volatile void __iomem *addr) +static inline u32 __raw_readl_no_log(const volatile void __iomem *addr) { u32 val; asm volatile("ldr %0, %1" @@ -122,6 +128,58 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) return val; } +static inline u64 __raw_readq_no_log(const volatile void __iomem *addr) +{ + register u64 val asm ("r2"); + + asm volatile("ldrd %1, %0" + : "+Qo" (*(volatile u64 __force *)addr), + "=r" (val)); + return val; +} + +/* + * There may be cases when clients don't want to support or can't support the + * logging. The appropriate functions can be used but clients should carefully + * consider why they can't support the logging. + */ + +#define __raw_write_logged(v, a, _t) ({ \ + int _ret; \ + volatile void __iomem *_a = (a); \ + void *_addr = (void __force *)(_a); \ + _ret = uncached_logk(LOGK_WRITEL, _addr); \ + ETB_WAYPOINT; \ + __raw_write##_t##_no_log((v), _a); \ + if (_ret) \ + LOG_BARRIER; \ + }) + + +#define __raw_writeb(v, a) __raw_write_logged((v), (a), b) +#define __raw_writew(v, a) __raw_write_logged((v), (a), w) +#define __raw_writel(v, a) __raw_write_logged((v), (a), l) +#define __raw_writeq(v, a) __raw_write_logged((v), (a), q) + +#define __raw_read_logged(a, _l, _t) ({ \ + unsigned _t __a; \ + const volatile void __iomem *_a = (a); \ + void *_addr = (void __force *)(_a); \ + int _ret; \ + _ret = uncached_logk(LOGK_READL, _addr); \ + ETB_WAYPOINT; \ + __a = __raw_read##_l##_no_log(_a);\ + if (_ret) \ + LOG_BARRIER; \ + __a; \ + }) + + +#define __raw_readb(a) __raw_read_logged((a), b, char) +#define __raw_readw(a) __raw_read_logged((a), w, short) +#define __raw_readl(a) __raw_read_logged((a), l, int) +#define __raw_readq(a) __raw_read_logged((a), q, long long) + /* * Architecture ioremap implementation. */ @@ -291,18 +349,32 @@ extern void _memset_io(volatile void __iomem *, int, size_t); __raw_readw(c)); __r; }) #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ __raw_readl(c)); __r; }) - -#define writeb_relaxed(v,c) __raw_writeb(v,c) -#define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c) -#define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \ + __raw_readq(c)); __r; }) +#define readb_relaxed_no_log(c) ({ u8 __r = __raw_readb_no_log(c); __r; }) +#define readl_relaxed_no_log(c) ({ u32 __r = le32_to_cpu((__force __le32) \ + __raw_readl_no_log(c)); __r; }) +#define readq_relaxed_no_log(c) ({ u64 __r = le64_to_cpu((__force __le64) \ + __raw_readq_no_log(c)); __r; }) + + +#define writeb_relaxed(v, c) __raw_writeb(v, c) +#define writew_relaxed(v, c) __raw_writew((__force u16) cpu_to_le16(v), c) +#define writel_relaxed(v, c) __raw_writel((__force u32) cpu_to_le32(v), c) +#define writeq_relaxed(v, c) __raw_writeq((__force u64) cpu_to_le64(v), c) +#define writeb_relaxed_no_log(v, c) ((void)__raw_writeb_no_log((v), (c))) +#define writel_relaxed_no_log(v, c) __raw_writel_no_log((__force u32) cpu_to_le32(v), c) +#define writeq_relaxed_no_log(v, c) __raw_writeq_no_log((__force u64) cpu_to_le64(v), c) #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) +#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; }) #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); }) #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); }) #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); }) +#define writeq(v, c) ({ __iowmb(); writeq_relaxed(v, c); }) #define readsb(p,d,l) __raw_readsb(p,d,l) #define readsw(p,d,l) __raw_readsw(p,d,l) @@ -401,6 +473,23 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size); void iounmap(volatile void __iomem *iomem_cookie); #define iounmap iounmap +/* + * io{read,write}{8,16,32,64} macros + */ +#ifndef ioread8 +#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __iormb(); __v; }) +#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; }) +#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; }) +#define ioread64(p) ({ unsigned int __v = le64_to_cpu((__force __le64)__raw_readq(p)); __iormb(); __v; }) + +#define ioread64be(p) ({ unsigned int __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(); __v; }) + +#define iowrite8(v, p) ({ __iowmb(); __raw_writeb(v, p); }) +#define iowrite16(v, p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_le16(v), p); }) +#define iowrite32(v, p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_le32(v), p); }) +#define iowrite64(v, p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_le64(v), p); }) + +#define iowrite64be(v, p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); }) /* * io{read,write}{16,32}be() macros @@ -419,6 +508,7 @@ extern void __iomem *ioport_map(unsigned long port, unsigned int nr); #define ioport_unmap ioport_unmap extern void ioport_unmap(void __iomem *addr); #endif +#endif struct pci_dev; diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h index 14602e883509..98d6de177b7a 100644 --- a/arch/arm/include/asm/kvm_arm.h +++ b/arch/arm/include/asm/kvm_arm.h @@ -19,6 +19,7 @@ #ifndef __ARM_KVM_ARM_H__ #define __ARM_KVM_ARM_H__ +#include <linux/const.h> #include <linux/types.h> /* Hyp Configuration Register (HCR) bits */ @@ -132,10 +133,9 @@ * space. */ #define KVM_PHYS_SHIFT (40) -#define KVM_PHYS_SIZE (1ULL << KVM_PHYS_SHIFT) -#define KVM_PHYS_MASK (KVM_PHYS_SIZE - 1ULL) -#define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30)) -#define S2_PGD_ORDER get_order(PTRS_PER_S2_PGD * sizeof(pgd_t)) +#define KVM_PHYS_SIZE (_AC(1, ULL) << KVM_PHYS_SHIFT) +#define KVM_PHYS_MASK (KVM_PHYS_SIZE - _AC(1, ULL)) +#define PTRS_PER_S2_PGD (_AC(1, ULL) << (KVM_PHYS_SHIFT - 30)) /* Virtualization Translation Control Register (VTCR) bits */ #define VTCR_SH0 (3 << 12) @@ -161,17 +161,17 @@ #else #define VTTBR_X (5 - KVM_T0SZ) #endif -#define VTTBR_BADDR_MASK (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_X) -#define VTTBR_VMID_SHIFT (48LLU) -#define VTTBR_VMID_MASK (0xffLLU << VTTBR_VMID_SHIFT) +#define VTTBR_BADDR_MASK (((_AC(1, ULL) << (40 - VTTBR_X)) - 1) << VTTBR_X) +#define VTTBR_VMID_SHIFT _AC(48, ULL) +#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) /* Hyp Syndrome Register (HSR) bits */ #define HSR_EC_SHIFT (26) -#define HSR_EC (0x3fU << HSR_EC_SHIFT) -#define HSR_IL (1U << 25) +#define HSR_EC (_AC(0x3f, UL) << HSR_EC_SHIFT) +#define HSR_IL (_AC(1, UL) << 25) #define HSR_ISS (HSR_IL - 1) #define HSR_ISV_SHIFT (24) -#define HSR_ISV (1U << HSR_ISV_SHIFT) +#define HSR_ISV (_AC(1, UL) << HSR_ISV_SHIFT) #define HSR_SRT_SHIFT (16) #define HSR_SRT_MASK (0xf << HSR_SRT_SHIFT) #define HSR_FSC (0x3f) @@ -179,9 +179,9 @@ #define HSR_SSE (1 << 21) #define HSR_WNR (1 << 6) #define HSR_CV_SHIFT (24) -#define HSR_CV (1U << HSR_CV_SHIFT) +#define HSR_CV (_AC(1, UL) << HSR_CV_SHIFT) #define HSR_COND_SHIFT (20) -#define HSR_COND (0xfU << HSR_COND_SHIFT) +#define HSR_COND (_AC(0xf, UL) << HSR_COND_SHIFT) #define FSC_FAULT (0x04) #define FSC_ACCESS (0x08) @@ -210,13 +210,13 @@ #define HSR_EC_DABT_HYP (0x25) #define HSR_EC_MAX (0x3f) -#define HSR_WFI_IS_WFE (1U << 0) +#define HSR_WFI_IS_WFE (_AC(1, UL) << 0) -#define HSR_HVC_IMM_MASK ((1UL << 16) - 1) +#define HSR_HVC_IMM_MASK ((_AC(1, UL) << 16) - 1) -#define HSR_DABT_S1PTW (1U << 7) -#define HSR_DABT_CM (1U << 8) -#define HSR_DABT_EA (1U << 9) +#define HSR_DABT_S1PTW (_AC(1, UL) << 7) +#define HSR_DABT_CM (_AC(1, UL) << 8) +#define HSR_DABT_EA (_AC(1, UL) << 9) #define kvm_arm_exception_type \ {0, "RESET" }, \ diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index 6692982c9b57..bedaf65c0ff9 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -214,6 +214,19 @@ static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr, kvm_call_hyp((void*)hyp_stack_ptr, vector_ptr, pgd_ptr); } +static inline void __cpu_init_stage2(void) +{ +} + +static inline void __cpu_reset_hyp_mode(phys_addr_t boot_pgd_ptr, + phys_addr_t phys_idmap_start) +{ + /* + * TODO + * kvm_call_reset(boot_pgd_ptr, phys_idmap_start); + */ +} + static inline int kvm_arch_dev_ioctl_check_extension(long ext) { return 0; @@ -226,7 +239,6 @@ void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); -static inline void kvm_arch_hardware_disable(void) {} static inline void kvm_arch_hardware_unsetup(void) {} static inline void kvm_arch_sync_events(struct kvm *kvm) {} static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h index 23d5cad56ddc..ebf866a3a8c8 100644 --- a/arch/arm/include/asm/kvm_mmu.h +++ b/arch/arm/include/asm/kvm_mmu.h @@ -66,6 +66,7 @@ void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu); phys_addr_t kvm_mmu_get_httbr(void); phys_addr_t kvm_mmu_get_boot_httbr(void); phys_addr_t kvm_get_idmap_vector(void); +phys_addr_t kvm_get_idmap_start(void); int kvm_mmu_init(void); void kvm_clear_hyp_idmap(void); @@ -272,6 +273,11 @@ static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd, pgd_t *merged_hyp_pgd, unsigned long hyp_idmap_start) { } +static inline unsigned int kvm_get_vmid_bits(void) +{ + return 8; +} + #endif /* !__ASSEMBLY__ */ #endif /* __ARM_KVM_MMU_H__ */ diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h deleted file mode 100644 index 948178cc6ba8..000000000000 --- a/arch/arm/include/asm/mach-types.h +++ /dev/null @@ -1 +0,0 @@ -#include <generated/mach-types.h> diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h index 4f9dec489931..306c4f4e778e 100644 --- a/arch/arm/include/asm/perf_event.h +++ b/arch/arm/include/asm/perf_event.h @@ -26,4 +26,91 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs); (regs)->ARM_cpsr = SVC_MODE; \ } +static inline u32 armv8pmu_pmcr_read_reg(void) +{ + u32 val; + + asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); + return val; +} + +static inline u32 armv8pmu_pmccntr_read_reg(void) +{ + u32 val; + + asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); + return val; +} + +static inline u32 armv8pmu_pmxevcntr_read_reg(void) +{ + u32 val; + + asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); + return val; +} + +static inline u32 armv8pmu_pmovsclr_read_reg(void) +{ + u32 val; + + asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); + return val; +} + +static inline void armv8pmu_pmcr_write_reg(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val)); +} + +static inline void armv8pmu_pmselr_write_reg(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); +} + +static inline void armv8pmu_pmccntr_write_reg(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val)); +} + +static inline void armv8pmu_pmxevcntr_write_reg(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val)); +} + +static inline void armv8pmu_pmxevtyper_write_reg(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); +} + +static inline void armv8pmu_pmcntenset_write_reg(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val)); +} + +static inline void armv8pmu_pmcntenclr_write_reg(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val)); +} + +static inline void armv8pmu_pmintenset_write_reg(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val)); +} + +static inline void armv8pmu_pmintenclr_write_reg(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val)); +} + +static inline void armv8pmu_pmovsclr_write_reg(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); +} + +static inline void armv8pmu_pmuserenr_write_reg(u32 val) +{ + asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r" (val)); +} + #endif /* __ARM_PERF_EVENT_H__ */ diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h index 08509183c7df..f59a19607cb0 100644 --- a/arch/arm/include/asm/processor.h +++ b/arch/arm/include/asm/processor.h @@ -30,6 +30,9 @@ #define STACK_TOP_MAX TASK_SIZE #endif +extern unsigned int boot_reason; +extern unsigned int cold_boot; + struct debug_info { #ifdef CONFIG_HAVE_HW_BREAKPOINT struct perf_event *hbp[ARM_MAX_HBP_SLOTS]; diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 51622ba7c4a6..d3c0c23703b6 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -121,7 +121,6 @@ extern unsigned long profile_pc(struct pt_regs *regs); #define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0)) extern int regs_query_register_offset(const char *name); -extern const char *regs_query_register_name(unsigned int offset); extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr); extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n); diff --git a/arch/arm/include/asm/system_misc.h b/arch/arm/include/asm/system_misc.h index 1fed41440af9..84e65cb22c4b 100644 --- a/arch/arm/include/asm/system_misc.h +++ b/arch/arm/include/asm/system_misc.h @@ -36,6 +36,7 @@ static inline void harden_branch_predictor(void) #define UDBG_BUS (1 << 4) extern unsigned int user_debug; +extern char* (*arch_read_hardware_id)(void); #endif /* !__ASSEMBLY__ */ diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index df8420672c7e..cfbf32bb9fc4 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -148,6 +148,7 @@ extern int vfp_restore_user_hwstate(struct user_vfp *, #define TIF_USING_IWMMXT 17 #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ #define TIF_RESTORE_SIGMASK 20 +#define TIF_MM_RELEASED 21 /* task MM has been released */ #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h index d06064120694..5bf87c62a418 100644 --- a/arch/arm/include/asm/topology.h +++ b/arch/arm/include/asm/topology.h @@ -9,14 +9,14 @@ struct cputopo_arm { int thread_id; int core_id; - int socket_id; + int cluster_id; cpumask_t thread_sibling; cpumask_t core_sibling; }; extern struct cputopo_arm cpu_topology[NR_CPUS]; -#define topology_physical_package_id(cpu) (cpu_topology[cpu].socket_id) +#define topology_physical_package_id(cpu) (cpu_topology[cpu].cluster_id) #define topology_core_id(cpu) (cpu_topology[cpu].core_id) #define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) #define topology_sibling_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h index 683d9230984a..24a47af4d05f 100644 --- a/arch/arm/include/asm/traps.h +++ b/arch/arm/include/asm/traps.h @@ -39,6 +39,7 @@ static inline int in_exception_text(unsigned long ptr) return in ? : __in_irqentry_text(ptr); } +extern void get_pct_hook_init(void); extern void __init early_trap_init(void *); extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame); extern void ptrace_break(struct task_struct *tsk, struct pt_regs *regs); diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index 7b84657fba35..076090d2dbf5 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -14,12 +14,7 @@ #define __ASM_ARM_UNISTD_H #include <uapi/asm/unistd.h> - -/* - * This may need to be greater than __NR_last_syscall+1 in order to - * account for the padding in the syscall table - */ -#define __NR_syscalls (392) +#include <asm/unistd-nr.h> #define __ARCH_WANT_STAT64 #define __ARCH_WANT_SYS_GETHOSTNAME @@ -52,4 +47,23 @@ #define __IGNORE_fadvise64_64 #define __IGNORE_migrate_pages +#ifdef __ARM_EABI__ +/* + * The following syscalls are obsolete and no longer available for EABI: + * __NR_time + * __NR_umount + * __NR_stime + * __NR_alarm + * __NR_utime + * __NR_getrlimit + * __NR_select + * __NR_readdir + * __NR_mmap + * __NR_socketcall + * __NR_syscall + * __NR_ipc + */ +#define __IGNORE_getrlimit +#endif + #endif /* __ASM_ARM_UNISTD_H */ diff --git a/arch/arm/include/asm/vdso_datapage.h b/arch/arm/include/asm/vdso_datapage.h index 9be259442fca..0120852b6b12 100644 --- a/arch/arm/include/asm/vdso_datapage.h +++ b/arch/arm/include/asm/vdso_datapage.h @@ -24,21 +24,38 @@ #include <asm/page.h> +#ifndef _VDSO_WTM_CLOCK_SEC_T +#define _VDSO_WTM_CLOCK_SEC_T +typedef u32 vdso_wtm_clock_nsec_t; +#endif + +#ifndef _VDSO_XTIME_CLOCK_SEC_T +#define _VDSO_XTIME_CLOCK_SEC_T +typedef u32 vdso_xtime_clock_sec_t; +#endif + +#ifndef _VDSO_RAW_TIME_SEC_T +#define _VDSO_RAW_TIME_SEC_T +typedef u32 vdso_raw_time_sec_t; +#endif + /* Try to be cache-friendly on systems that don't implement the * generic timer: fit the unconditionally updated fields in the first * 32 bytes. */ struct vdso_data { - u32 seq_count; /* sequence count - odd during updates */ - u16 tk_is_cntvct; /* fall back to syscall if false */ + u32 tb_seq_count; /* sequence count - odd during updates */ + u16 use_syscall; /* fall back to syscall if true */ u16 cs_shift; /* clocksource shift */ u32 xtime_coarse_sec; /* coarse time */ u32 xtime_coarse_nsec; - u32 wtm_clock_sec; /* wall to monotonic offset */ - u32 wtm_clock_nsec; - u32 xtime_clock_sec; /* CLOCK_REALTIME - seconds */ - u32 cs_mult; /* clocksource multiplier */ + /* wall to monotonic offset */ + u32 wtm_clock_sec; + vdso_wtm_clock_nsec_t wtm_clock_nsec; + /* CLOCK_REALTIME - seconds */ + vdso_xtime_clock_sec_t xtime_clock_sec; + u32 cs_mono_mult; /* clocksource multiplier */ u64 cs_cycle_last; /* last cycle value */ u64 cs_mask; /* clocksource mask */ @@ -46,6 +63,14 @@ struct vdso_data { u64 xtime_clock_snsec; /* CLOCK_REALTIME sub-ns base */ u32 tz_minuteswest; /* timezone info for gettimeofday(2) */ u32 tz_dsttime; + + u32 btm_sec; /* monotonic to boot time */ + u32 btm_nsec; + /* Raw clocksource multipler */ + u32 cs_raw_mult; + /* Raw time */ + vdso_raw_time_sec_t raw_time_sec; + u32 raw_time_nsec; }; union vdso_data_store { diff --git a/arch/arm/include/asm/virt.h b/arch/arm/include/asm/virt.h index 4371f45c5784..d4ceaf5f299b 100644 --- a/arch/arm/include/asm/virt.h +++ b/arch/arm/include/asm/virt.h @@ -74,6 +74,15 @@ static inline bool is_hyp_mode_mismatched(void) { return !!(__boot_cpu_mode & BOOT_CPU_MODE_MISMATCH); } + +static inline bool is_kernel_in_hyp_mode(void) +{ + return false; +} + +/* The section containing the hypervisor text */ +extern char __hyp_text_start[]; +extern char __hyp_text_end[]; #endif #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/uapi/asm/Kbuild b/arch/arm/include/uapi/asm/Kbuild index a1c05f93d920..424935e4515d 100644 --- a/arch/arm/include/uapi/asm/Kbuild +++ b/arch/arm/include/uapi/asm/Kbuild @@ -1,20 +1,6 @@ # UAPI Header export list include include/uapi/asm-generic/Kbuild.asm -header-y += auxvec.h -header-y += byteorder.h -header-y += fcntl.h -header-y += hwcap.h -header-y += ioctls.h -header-y += kvm_para.h -header-y += mman.h -header-y += perf_regs.h -header-y += posix_types.h -header-y += ptrace.h -header-y += setup.h -header-y += sigcontext.h -header-y += signal.h -header-y += stat.h -header-y += statfs.h -header-y += swab.h -header-y += unistd.h +generated-y += unistd-common.h +generated-y += unistd-oabi.h +generated-y += unistd-eabi.h diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/uapi/asm/types.h index a53cdb8f068c..9435a42f575e 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/uapi/asm/types.h @@ -1,5 +1,5 @@ -#ifndef _ASM_TYPES_H -#define _ASM_TYPES_H +#ifndef _UAPI_ASM_TYPES_H +#define _UAPI_ASM_TYPES_H #include <asm-generic/int-ll64.h> @@ -37,4 +37,4 @@ #define __UINTPTR_TYPE__ unsigned long #endif -#endif /* _ASM_TYPES_H */ +#endif /* _UAPI_ASM_TYPES_H */ diff --git a/arch/arm/include/uapi/asm/unistd.h b/arch/arm/include/uapi/asm/unistd.h index ede692ffa32e..a9e85739a912 100644 --- a/arch/arm/include/uapi/asm/unistd.h +++ b/arch/arm/include/uapi/asm/unistd.h @@ -17,406 +17,14 @@ #if defined(__thumb__) || defined(__ARM_EABI__) #define __NR_SYSCALL_BASE 0 +#include <asm/unistd-eabi.h> #else #define __NR_SYSCALL_BASE __NR_OABI_SYSCALL_BASE +#include <asm/unistd-oabi.h> #endif -/* - * This file contains the system call numbers. - */ - -#define __NR_restart_syscall (__NR_SYSCALL_BASE+ 0) -#define __NR_exit (__NR_SYSCALL_BASE+ 1) -#define __NR_fork (__NR_SYSCALL_BASE+ 2) -#define __NR_read (__NR_SYSCALL_BASE+ 3) -#define __NR_write (__NR_SYSCALL_BASE+ 4) -#define __NR_open (__NR_SYSCALL_BASE+ 5) -#define __NR_close (__NR_SYSCALL_BASE+ 6) - /* 7 was sys_waitpid */ -#define __NR_creat (__NR_SYSCALL_BASE+ 8) -#define __NR_link (__NR_SYSCALL_BASE+ 9) -#define __NR_unlink (__NR_SYSCALL_BASE+ 10) -#define __NR_execve (__NR_SYSCALL_BASE+ 11) -#define __NR_chdir (__NR_SYSCALL_BASE+ 12) -#define __NR_time (__NR_SYSCALL_BASE+ 13) -#define __NR_mknod (__NR_SYSCALL_BASE+ 14) -#define __NR_chmod (__NR_SYSCALL_BASE+ 15) -#define __NR_lchown (__NR_SYSCALL_BASE+ 16) - /* 17 was sys_break */ - /* 18 was sys_stat */ -#define __NR_lseek (__NR_SYSCALL_BASE+ 19) -#define __NR_getpid (__NR_SYSCALL_BASE+ 20) -#define __NR_mount (__NR_SYSCALL_BASE+ 21) -#define __NR_umount (__NR_SYSCALL_BASE+ 22) -#define __NR_setuid (__NR_SYSCALL_BASE+ 23) -#define __NR_getuid (__NR_SYSCALL_BASE+ 24) -#define __NR_stime (__NR_SYSCALL_BASE+ 25) -#define __NR_ptrace (__NR_SYSCALL_BASE+ 26) -#define __NR_alarm (__NR_SYSCALL_BASE+ 27) - /* 28 was sys_fstat */ -#define __NR_pause (__NR_SYSCALL_BASE+ 29) -#define __NR_utime (__NR_SYSCALL_BASE+ 30) - /* 31 was sys_stty */ - /* 32 was sys_gtty */ -#define __NR_access (__NR_SYSCALL_BASE+ 33) -#define __NR_nice (__NR_SYSCALL_BASE+ 34) - /* 35 was sys_ftime */ -#define __NR_sync (__NR_SYSCALL_BASE+ 36) -#define __NR_kill (__NR_SYSCALL_BASE+ 37) -#define __NR_rename (__NR_SYSCALL_BASE+ 38) -#define __NR_mkdir (__NR_SYSCALL_BASE+ 39) -#define __NR_rmdir (__NR_SYSCALL_BASE+ 40) -#define __NR_dup (__NR_SYSCALL_BASE+ 41) -#define __NR_pipe (__NR_SYSCALL_BASE+ 42) -#define __NR_times (__NR_SYSCALL_BASE+ 43) - /* 44 was sys_prof */ -#define __NR_brk (__NR_SYSCALL_BASE+ 45) -#define __NR_setgid (__NR_SYSCALL_BASE+ 46) -#define __NR_getgid (__NR_SYSCALL_BASE+ 47) - /* 48 was sys_signal */ -#define __NR_geteuid (__NR_SYSCALL_BASE+ 49) -#define __NR_getegid (__NR_SYSCALL_BASE+ 50) -#define __NR_acct (__NR_SYSCALL_BASE+ 51) -#define __NR_umount2 (__NR_SYSCALL_BASE+ 52) - /* 53 was sys_lock */ -#define __NR_ioctl (__NR_SYSCALL_BASE+ 54) -#define __NR_fcntl (__NR_SYSCALL_BASE+ 55) - /* 56 was sys_mpx */ -#define __NR_setpgid (__NR_SYSCALL_BASE+ 57) - /* 58 was sys_ulimit */ - /* 59 was sys_olduname */ -#define __NR_umask (__NR_SYSCALL_BASE+ 60) -#define __NR_chroot (__NR_SYSCALL_BASE+ 61) -#define __NR_ustat (__NR_SYSCALL_BASE+ 62) -#define __NR_dup2 (__NR_SYSCALL_BASE+ 63) -#define __NR_getppid (__NR_SYSCALL_BASE+ 64) -#define __NR_getpgrp (__NR_SYSCALL_BASE+ 65) -#define __NR_setsid (__NR_SYSCALL_BASE+ 66) -#define __NR_sigaction (__NR_SYSCALL_BASE+ 67) - /* 68 was sys_sgetmask */ - /* 69 was sys_ssetmask */ -#define __NR_setreuid (__NR_SYSCALL_BASE+ 70) -#define __NR_setregid (__NR_SYSCALL_BASE+ 71) -#define __NR_sigsuspend (__NR_SYSCALL_BASE+ 72) -#define __NR_sigpending (__NR_SYSCALL_BASE+ 73) -#define __NR_sethostname (__NR_SYSCALL_BASE+ 74) -#define __NR_setrlimit (__NR_SYSCALL_BASE+ 75) -#define __NR_getrlimit (__NR_SYSCALL_BASE+ 76) /* Back compat 2GB limited rlimit */ -#define __NR_getrusage (__NR_SYSCALL_BASE+ 77) -#define __NR_gettimeofday (__NR_SYSCALL_BASE+ 78) -#define __NR_settimeofday (__NR_SYSCALL_BASE+ 79) -#define __NR_getgroups (__NR_SYSCALL_BASE+ 80) -#define __NR_setgroups (__NR_SYSCALL_BASE+ 81) -#define __NR_select (__NR_SYSCALL_BASE+ 82) -#define __NR_symlink (__NR_SYSCALL_BASE+ 83) - /* 84 was sys_lstat */ -#define __NR_readlink (__NR_SYSCALL_BASE+ 85) -#define __NR_uselib (__NR_SYSCALL_BASE+ 86) -#define __NR_swapon (__NR_SYSCALL_BASE+ 87) -#define __NR_reboot (__NR_SYSCALL_BASE+ 88) -#define __NR_readdir (__NR_SYSCALL_BASE+ 89) -#define __NR_mmap (__NR_SYSCALL_BASE+ 90) -#define __NR_munmap (__NR_SYSCALL_BASE+ 91) -#define __NR_truncate (__NR_SYSCALL_BASE+ 92) -#define __NR_ftruncate (__NR_SYSCALL_BASE+ 93) -#define __NR_fchmod (__NR_SYSCALL_BASE+ 94) -#define __NR_fchown (__NR_SYSCALL_BASE+ 95) -#define __NR_getpriority (__NR_SYSCALL_BASE+ 96) -#define __NR_setpriority (__NR_SYSCALL_BASE+ 97) - /* 98 was sys_profil */ -#define __NR_statfs (__NR_SYSCALL_BASE+ 99) -#define __NR_fstatfs (__NR_SYSCALL_BASE+100) - /* 101 was sys_ioperm */ -#define __NR_socketcall (__NR_SYSCALL_BASE+102) -#define __NR_syslog (__NR_SYSCALL_BASE+103) -#define __NR_setitimer (__NR_SYSCALL_BASE+104) -#define __NR_getitimer (__NR_SYSCALL_BASE+105) -#define __NR_stat (__NR_SYSCALL_BASE+106) -#define __NR_lstat (__NR_SYSCALL_BASE+107) -#define __NR_fstat (__NR_SYSCALL_BASE+108) - /* 109 was sys_uname */ - /* 110 was sys_iopl */ -#define __NR_vhangup (__NR_SYSCALL_BASE+111) - /* 112 was sys_idle */ -#define __NR_syscall (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */ -#define __NR_wait4 (__NR_SYSCALL_BASE+114) -#define __NR_swapoff (__NR_SYSCALL_BASE+115) -#define __NR_sysinfo (__NR_SYSCALL_BASE+116) -#define __NR_ipc (__NR_SYSCALL_BASE+117) -#define __NR_fsync (__NR_SYSCALL_BASE+118) -#define __NR_sigreturn (__NR_SYSCALL_BASE+119) -#define __NR_clone (__NR_SYSCALL_BASE+120) -#define __NR_setdomainname (__NR_SYSCALL_BASE+121) -#define __NR_uname (__NR_SYSCALL_BASE+122) - /* 123 was sys_modify_ldt */ -#define __NR_adjtimex (__NR_SYSCALL_BASE+124) -#define __NR_mprotect (__NR_SYSCALL_BASE+125) -#define __NR_sigprocmask (__NR_SYSCALL_BASE+126) - /* 127 was sys_create_module */ -#define __NR_init_module (__NR_SYSCALL_BASE+128) -#define __NR_delete_module (__NR_SYSCALL_BASE+129) - /* 130 was sys_get_kernel_syms */ -#define __NR_quotactl (__NR_SYSCALL_BASE+131) -#define __NR_getpgid (__NR_SYSCALL_BASE+132) -#define __NR_fchdir (__NR_SYSCALL_BASE+133) -#define __NR_bdflush (__NR_SYSCALL_BASE+134) -#define __NR_sysfs (__NR_SYSCALL_BASE+135) -#define __NR_personality (__NR_SYSCALL_BASE+136) - /* 137 was sys_afs_syscall */ -#define __NR_setfsuid (__NR_SYSCALL_BASE+138) -#define __NR_setfsgid (__NR_SYSCALL_BASE+139) -#define __NR__llseek (__NR_SYSCALL_BASE+140) -#define __NR_getdents (__NR_SYSCALL_BASE+141) -#define __NR__newselect (__NR_SYSCALL_BASE+142) -#define __NR_flock (__NR_SYSCALL_BASE+143) -#define __NR_msync (__NR_SYSCALL_BASE+144) -#define __NR_readv (__NR_SYSCALL_BASE+145) -#define __NR_writev (__NR_SYSCALL_BASE+146) -#define __NR_getsid (__NR_SYSCALL_BASE+147) -#define __NR_fdatasync (__NR_SYSCALL_BASE+148) -#define __NR__sysctl (__NR_SYSCALL_BASE+149) -#define __NR_mlock (__NR_SYSCALL_BASE+150) -#define __NR_munlock (__NR_SYSCALL_BASE+151) -#define __NR_mlockall (__NR_SYSCALL_BASE+152) -#define __NR_munlockall (__NR_SYSCALL_BASE+153) -#define __NR_sched_setparam (__NR_SYSCALL_BASE+154) -#define __NR_sched_getparam (__NR_SYSCALL_BASE+155) -#define __NR_sched_setscheduler (__NR_SYSCALL_BASE+156) -#define __NR_sched_getscheduler (__NR_SYSCALL_BASE+157) -#define __NR_sched_yield (__NR_SYSCALL_BASE+158) -#define __NR_sched_get_priority_max (__NR_SYSCALL_BASE+159) -#define __NR_sched_get_priority_min (__NR_SYSCALL_BASE+160) -#define __NR_sched_rr_get_interval (__NR_SYSCALL_BASE+161) -#define __NR_nanosleep (__NR_SYSCALL_BASE+162) -#define __NR_mremap (__NR_SYSCALL_BASE+163) -#define __NR_setresuid (__NR_SYSCALL_BASE+164) -#define __NR_getresuid (__NR_SYSCALL_BASE+165) - /* 166 was sys_vm86 */ - /* 167 was sys_query_module */ -#define __NR_poll (__NR_SYSCALL_BASE+168) -#define __NR_nfsservctl (__NR_SYSCALL_BASE+169) -#define __NR_setresgid (__NR_SYSCALL_BASE+170) -#define __NR_getresgid (__NR_SYSCALL_BASE+171) -#define __NR_prctl (__NR_SYSCALL_BASE+172) -#define __NR_rt_sigreturn (__NR_SYSCALL_BASE+173) -#define __NR_rt_sigaction (__NR_SYSCALL_BASE+174) -#define __NR_rt_sigprocmask (__NR_SYSCALL_BASE+175) -#define __NR_rt_sigpending (__NR_SYSCALL_BASE+176) -#define __NR_rt_sigtimedwait (__NR_SYSCALL_BASE+177) -#define __NR_rt_sigqueueinfo (__NR_SYSCALL_BASE+178) -#define __NR_rt_sigsuspend (__NR_SYSCALL_BASE+179) -#define __NR_pread64 (__NR_SYSCALL_BASE+180) -#define __NR_pwrite64 (__NR_SYSCALL_BASE+181) -#define __NR_chown (__NR_SYSCALL_BASE+182) -#define __NR_getcwd (__NR_SYSCALL_BASE+183) -#define __NR_capget (__NR_SYSCALL_BASE+184) -#define __NR_capset (__NR_SYSCALL_BASE+185) -#define __NR_sigaltstack (__NR_SYSCALL_BASE+186) -#define __NR_sendfile (__NR_SYSCALL_BASE+187) - /* 188 reserved */ - /* 189 reserved */ -#define __NR_vfork (__NR_SYSCALL_BASE+190) -#define __NR_ugetrlimit (__NR_SYSCALL_BASE+191) /* SuS compliant getrlimit */ -#define __NR_mmap2 (__NR_SYSCALL_BASE+192) -#define __NR_truncate64 (__NR_SYSCALL_BASE+193) -#define __NR_ftruncate64 (__NR_SYSCALL_BASE+194) -#define __NR_stat64 (__NR_SYSCALL_BASE+195) -#define __NR_lstat64 (__NR_SYSCALL_BASE+196) -#define __NR_fstat64 (__NR_SYSCALL_BASE+197) -#define __NR_lchown32 (__NR_SYSCALL_BASE+198) -#define __NR_getuid32 (__NR_SYSCALL_BASE+199) -#define __NR_getgid32 (__NR_SYSCALL_BASE+200) -#define __NR_geteuid32 (__NR_SYSCALL_BASE+201) -#define __NR_getegid32 (__NR_SYSCALL_BASE+202) -#define __NR_setreuid32 (__NR_SYSCALL_BASE+203) -#define __NR_setregid32 (__NR_SYSCALL_BASE+204) -#define __NR_getgroups32 (__NR_SYSCALL_BASE+205) -#define __NR_setgroups32 (__NR_SYSCALL_BASE+206) -#define __NR_fchown32 (__NR_SYSCALL_BASE+207) -#define __NR_setresuid32 (__NR_SYSCALL_BASE+208) -#define __NR_getresuid32 (__NR_SYSCALL_BASE+209) -#define __NR_setresgid32 (__NR_SYSCALL_BASE+210) -#define __NR_getresgid32 (__NR_SYSCALL_BASE+211) -#define __NR_chown32 (__NR_SYSCALL_BASE+212) -#define __NR_setuid32 (__NR_SYSCALL_BASE+213) -#define __NR_setgid32 (__NR_SYSCALL_BASE+214) -#define __NR_setfsuid32 (__NR_SYSCALL_BASE+215) -#define __NR_setfsgid32 (__NR_SYSCALL_BASE+216) -#define __NR_getdents64 (__NR_SYSCALL_BASE+217) -#define __NR_pivot_root (__NR_SYSCALL_BASE+218) -#define __NR_mincore (__NR_SYSCALL_BASE+219) -#define __NR_madvise (__NR_SYSCALL_BASE+220) -#define __NR_fcntl64 (__NR_SYSCALL_BASE+221) - /* 222 for tux */ - /* 223 is unused */ -#define __NR_gettid (__NR_SYSCALL_BASE+224) -#define __NR_readahead (__NR_SYSCALL_BASE+225) -#define __NR_setxattr (__NR_SYSCALL_BASE+226) -#define __NR_lsetxattr (__NR_SYSCALL_BASE+227) -#define __NR_fsetxattr (__NR_SYSCALL_BASE+228) -#define __NR_getxattr (__NR_SYSCALL_BASE+229) -#define __NR_lgetxattr (__NR_SYSCALL_BASE+230) -#define __NR_fgetxattr (__NR_SYSCALL_BASE+231) -#define __NR_listxattr (__NR_SYSCALL_BASE+232) -#define __NR_llistxattr (__NR_SYSCALL_BASE+233) -#define __NR_flistxattr (__NR_SYSCALL_BASE+234) -#define __NR_removexattr (__NR_SYSCALL_BASE+235) -#define __NR_lremovexattr (__NR_SYSCALL_BASE+236) -#define __NR_fremovexattr (__NR_SYSCALL_BASE+237) -#define __NR_tkill (__NR_SYSCALL_BASE+238) -#define __NR_sendfile64 (__NR_SYSCALL_BASE+239) -#define __NR_futex (__NR_SYSCALL_BASE+240) -#define __NR_sched_setaffinity (__NR_SYSCALL_BASE+241) -#define __NR_sched_getaffinity (__NR_SYSCALL_BASE+242) -#define __NR_io_setup (__NR_SYSCALL_BASE+243) -#define __NR_io_destroy (__NR_SYSCALL_BASE+244) -#define __NR_io_getevents (__NR_SYSCALL_BASE+245) -#define __NR_io_submit (__NR_SYSCALL_BASE+246) -#define __NR_io_cancel (__NR_SYSCALL_BASE+247) -#define __NR_exit_group (__NR_SYSCALL_BASE+248) -#define __NR_lookup_dcookie (__NR_SYSCALL_BASE+249) -#define __NR_epoll_create (__NR_SYSCALL_BASE+250) -#define __NR_epoll_ctl (__NR_SYSCALL_BASE+251) -#define __NR_epoll_wait (__NR_SYSCALL_BASE+252) -#define __NR_remap_file_pages (__NR_SYSCALL_BASE+253) - /* 254 for set_thread_area */ - /* 255 for get_thread_area */ -#define __NR_set_tid_address (__NR_SYSCALL_BASE+256) -#define __NR_timer_create (__NR_SYSCALL_BASE+257) -#define __NR_timer_settime (__NR_SYSCALL_BASE+258) -#define __NR_timer_gettime (__NR_SYSCALL_BASE+259) -#define __NR_timer_getoverrun (__NR_SYSCALL_BASE+260) -#define __NR_timer_delete (__NR_SYSCALL_BASE+261) -#define __NR_clock_settime (__NR_SYSCALL_BASE+262) -#define __NR_clock_gettime (__NR_SYSCALL_BASE+263) -#define __NR_clock_getres (__NR_SYSCALL_BASE+264) -#define __NR_clock_nanosleep (__NR_SYSCALL_BASE+265) -#define __NR_statfs64 (__NR_SYSCALL_BASE+266) -#define __NR_fstatfs64 (__NR_SYSCALL_BASE+267) -#define __NR_tgkill (__NR_SYSCALL_BASE+268) -#define __NR_utimes (__NR_SYSCALL_BASE+269) -#define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE+270) -#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271) -#define __NR_pciconfig_read (__NR_SYSCALL_BASE+272) -#define __NR_pciconfig_write (__NR_SYSCALL_BASE+273) -#define __NR_mq_open (__NR_SYSCALL_BASE+274) -#define __NR_mq_unlink (__NR_SYSCALL_BASE+275) -#define __NR_mq_timedsend (__NR_SYSCALL_BASE+276) -#define __NR_mq_timedreceive (__NR_SYSCALL_BASE+277) -#define __NR_mq_notify (__NR_SYSCALL_BASE+278) -#define __NR_mq_getsetattr (__NR_SYSCALL_BASE+279) -#define __NR_waitid (__NR_SYSCALL_BASE+280) -#define __NR_socket (__NR_SYSCALL_BASE+281) -#define __NR_bind (__NR_SYSCALL_BASE+282) -#define __NR_connect (__NR_SYSCALL_BASE+283) -#define __NR_listen (__NR_SYSCALL_BASE+284) -#define __NR_accept (__NR_SYSCALL_BASE+285) -#define __NR_getsockname (__NR_SYSCALL_BASE+286) -#define __NR_getpeername (__NR_SYSCALL_BASE+287) -#define __NR_socketpair (__NR_SYSCALL_BASE+288) -#define __NR_send (__NR_SYSCALL_BASE+289) -#define __NR_sendto (__NR_SYSCALL_BASE+290) -#define __NR_recv (__NR_SYSCALL_BASE+291) -#define __NR_recvfrom (__NR_SYSCALL_BASE+292) -#define __NR_shutdown (__NR_SYSCALL_BASE+293) -#define __NR_setsockopt (__NR_SYSCALL_BASE+294) -#define __NR_getsockopt (__NR_SYSCALL_BASE+295) -#define __NR_sendmsg (__NR_SYSCALL_BASE+296) -#define __NR_recvmsg (__NR_SYSCALL_BASE+297) -#define __NR_semop (__NR_SYSCALL_BASE+298) -#define __NR_semget (__NR_SYSCALL_BASE+299) -#define __NR_semctl (__NR_SYSCALL_BASE+300) -#define __NR_msgsnd (__NR_SYSCALL_BASE+301) -#define __NR_msgrcv (__NR_SYSCALL_BASE+302) -#define __NR_msgget (__NR_SYSCALL_BASE+303) -#define __NR_msgctl (__NR_SYSCALL_BASE+304) -#define __NR_shmat (__NR_SYSCALL_BASE+305) -#define __NR_shmdt (__NR_SYSCALL_BASE+306) -#define __NR_shmget (__NR_SYSCALL_BASE+307) -#define __NR_shmctl (__NR_SYSCALL_BASE+308) -#define __NR_add_key (__NR_SYSCALL_BASE+309) -#define __NR_request_key (__NR_SYSCALL_BASE+310) -#define __NR_keyctl (__NR_SYSCALL_BASE+311) -#define __NR_semtimedop (__NR_SYSCALL_BASE+312) -#define __NR_vserver (__NR_SYSCALL_BASE+313) -#define __NR_ioprio_set (__NR_SYSCALL_BASE+314) -#define __NR_ioprio_get (__NR_SYSCALL_BASE+315) -#define __NR_inotify_init (__NR_SYSCALL_BASE+316) -#define __NR_inotify_add_watch (__NR_SYSCALL_BASE+317) -#define __NR_inotify_rm_watch (__NR_SYSCALL_BASE+318) -#define __NR_mbind (__NR_SYSCALL_BASE+319) -#define __NR_get_mempolicy (__NR_SYSCALL_BASE+320) -#define __NR_set_mempolicy (__NR_SYSCALL_BASE+321) -#define __NR_openat (__NR_SYSCALL_BASE+322) -#define __NR_mkdirat (__NR_SYSCALL_BASE+323) -#define __NR_mknodat (__NR_SYSCALL_BASE+324) -#define __NR_fchownat (__NR_SYSCALL_BASE+325) -#define __NR_futimesat (__NR_SYSCALL_BASE+326) -#define __NR_fstatat64 (__NR_SYSCALL_BASE+327) -#define __NR_unlinkat (__NR_SYSCALL_BASE+328) -#define __NR_renameat (__NR_SYSCALL_BASE+329) -#define __NR_linkat (__NR_SYSCALL_BASE+330) -#define __NR_symlinkat (__NR_SYSCALL_BASE+331) -#define __NR_readlinkat (__NR_SYSCALL_BASE+332) -#define __NR_fchmodat (__NR_SYSCALL_BASE+333) -#define __NR_faccessat (__NR_SYSCALL_BASE+334) -#define __NR_pselect6 (__NR_SYSCALL_BASE+335) -#define __NR_ppoll (__NR_SYSCALL_BASE+336) -#define __NR_unshare (__NR_SYSCALL_BASE+337) -#define __NR_set_robust_list (__NR_SYSCALL_BASE+338) -#define __NR_get_robust_list (__NR_SYSCALL_BASE+339) -#define __NR_splice (__NR_SYSCALL_BASE+340) -#define __NR_arm_sync_file_range (__NR_SYSCALL_BASE+341) -#define __NR_sync_file_range2 __NR_arm_sync_file_range -#define __NR_tee (__NR_SYSCALL_BASE+342) -#define __NR_vmsplice (__NR_SYSCALL_BASE+343) -#define __NR_move_pages (__NR_SYSCALL_BASE+344) -#define __NR_getcpu (__NR_SYSCALL_BASE+345) -#define __NR_epoll_pwait (__NR_SYSCALL_BASE+346) -#define __NR_kexec_load (__NR_SYSCALL_BASE+347) -#define __NR_utimensat (__NR_SYSCALL_BASE+348) -#define __NR_signalfd (__NR_SYSCALL_BASE+349) -#define __NR_timerfd_create (__NR_SYSCALL_BASE+350) -#define __NR_eventfd (__NR_SYSCALL_BASE+351) -#define __NR_fallocate (__NR_SYSCALL_BASE+352) -#define __NR_timerfd_settime (__NR_SYSCALL_BASE+353) -#define __NR_timerfd_gettime (__NR_SYSCALL_BASE+354) -#define __NR_signalfd4 (__NR_SYSCALL_BASE+355) -#define __NR_eventfd2 (__NR_SYSCALL_BASE+356) -#define __NR_epoll_create1 (__NR_SYSCALL_BASE+357) -#define __NR_dup3 (__NR_SYSCALL_BASE+358) -#define __NR_pipe2 (__NR_SYSCALL_BASE+359) -#define __NR_inotify_init1 (__NR_SYSCALL_BASE+360) -#define __NR_preadv (__NR_SYSCALL_BASE+361) -#define __NR_pwritev (__NR_SYSCALL_BASE+362) -#define __NR_rt_tgsigqueueinfo (__NR_SYSCALL_BASE+363) -#define __NR_perf_event_open (__NR_SYSCALL_BASE+364) -#define __NR_recvmmsg (__NR_SYSCALL_BASE+365) -#define __NR_accept4 (__NR_SYSCALL_BASE+366) -#define __NR_fanotify_init (__NR_SYSCALL_BASE+367) -#define __NR_fanotify_mark (__NR_SYSCALL_BASE+368) -#define __NR_prlimit64 (__NR_SYSCALL_BASE+369) -#define __NR_name_to_handle_at (__NR_SYSCALL_BASE+370) -#define __NR_open_by_handle_at (__NR_SYSCALL_BASE+371) -#define __NR_clock_adjtime (__NR_SYSCALL_BASE+372) -#define __NR_syncfs (__NR_SYSCALL_BASE+373) -#define __NR_sendmmsg (__NR_SYSCALL_BASE+374) -#define __NR_setns (__NR_SYSCALL_BASE+375) -#define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) -#define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) -#define __NR_kcmp (__NR_SYSCALL_BASE+378) -#define __NR_finit_module (__NR_SYSCALL_BASE+379) -#define __NR_sched_setattr (__NR_SYSCALL_BASE+380) -#define __NR_sched_getattr (__NR_SYSCALL_BASE+381) -#define __NR_renameat2 (__NR_SYSCALL_BASE+382) -#define __NR_seccomp (__NR_SYSCALL_BASE+383) -#define __NR_getrandom (__NR_SYSCALL_BASE+384) -#define __NR_memfd_create (__NR_SYSCALL_BASE+385) -#define __NR_bpf (__NR_SYSCALL_BASE+386) -#define __NR_execveat (__NR_SYSCALL_BASE+387) -#define __NR_userfaultfd (__NR_SYSCALL_BASE+388) -#define __NR_membarrier (__NR_SYSCALL_BASE+389) -#define __NR_mlock2 (__NR_SYSCALL_BASE+390) +#include <asm/unistd-common.h> +#define __NR_sync_file_range2 __NR_arm_sync_file_range /* * The following SWIs are ARM private. @@ -428,24 +36,4 @@ #define __ARM_NR_usr32 (__ARM_NR_BASE+4) #define __ARM_NR_set_tls (__ARM_NR_BASE+5) -/* - * The following syscalls are obsolete and no longer available for EABI. - */ -#if !defined(__KERNEL__) -#if defined(__ARM_EABI__) -#undef __NR_time -#undef __NR_umount -#undef __NR_stime -#undef __NR_alarm -#undef __NR_utime -#undef __NR_getrlimit -#undef __NR_select -#undef __NR_readdir -#undef __NR_mmap -#undef __NR_socketcall -#undef __NR_syscall -#undef __NR_ipc -#endif -#endif - #endif /* _UAPI__ASM_ARM_UNISTD_H */ |