diff options
127 files changed, 7856 insertions, 1567 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt index 518cc6f85f95..c4d651e36d02 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt @@ -56,15 +56,17 @@ Properties: Usage: required Value type: <prop-encoded-array> Definition: Array which defines the frequency in Hertz, frequency, - PLL override data, and ACC level used by the OSM hardware - for each supported DCVS setpoint of the Power cluster. + PLL override data, ACC level, and virtual corner used + by the OSM hardware for each supported DCVS setpoint + of the Power cluster. - qcom,perfcl-speedbinX-v0 Usage: required Value type: <prop-encoded-array> Definition: Array which defines the frequency in Hertz, frequency, - PLL override data, and ACC level used by the OSM hardware - for each supported DCVS setpoint of the Performance cluster. + PLL override data, ACC level and virtual corner used + by the OSM hardware for each supported DCVS setpoint + of the Performance cluster. - qcom,osm-no-tz Usage: optional @@ -317,55 +319,55 @@ Example: interrupt-names = "pwrcl-irq", "perfcl-irq"; qcom,pwrcl-speedbin0-v0 = - < 300000000 0x0004000f 0x031e001e 0x1>, - < 345600000 0x05040012 0x04200020 0x1>, - < 422400000 0x05040016 0x04200020 0x1>, - < 499200000 0x0504001a 0x05200020 0x1>, - < 576000000 0x0504001e 0x06200020 0x1>, - < 633600000 0x04040021 0x07200020 0x1>, - < 710400000 0x04040025 0x07200020 0x1>, - < 806400000 0x0404002a 0x08220022 0x2>, - < 883200000 0x0404002e 0x09250025 0x2>, - < 960000000 0x04040032 0x0a280028 0x2>, - < 1036800000 0x04040036 0x0b2b002b 0x3>, - < 1113600000 0x0404003a 0x0c2e002e 0x3>, - < 1190400000 0x0404003e 0x0c320032 0x3>, - < 1248000000 0x04040041 0x0d340034 0x3>, - < 1324800000 0x04040045 0x0e370037 0x3>, - < 1401600000 0x04040049 0x0f3a003a 0x3>, - < 1478400000 0x0404004d 0x103e003e 0x3>, - < 1574400000 0x04040052 0x10420042 0x4>, - < 1651200000 0x04040056 0x11450045 0x4>, - < 1728000000 0x0404005a 0x12480048 0x4>, - < 1804800000 0x0404005e 0x134b004b 0x4>, - < 1881600000 0x04040062 0x144e004e 0x4>; + < 300000000 0x0004000f 0x031e001e 0x1 1 >, + < 345600000 0x05040012 0x04200020 0x1 2 >, + < 422400000 0x05040016 0x04200020 0x1 3 >, + < 499200000 0x0504001a 0x05200020 0x1 4 >, + < 576000000 0x0504001e 0x06200020 0x1 5 >, + < 633600000 0x04040021 0x07200020 0x1 6 >, + < 710400000 0x04040025 0x07200020 0x1 7 >, + < 806400000 0x0404002a 0x08220022 0x2 8 >, + < 883200000 0x0404002e 0x09250025 0x2 9 >, + < 960000000 0x04040032 0x0a280028 0x2 10 >, + < 1036800000 0x04040036 0x0b2b002b 0x3 11 >, + < 1113600000 0x0404003a 0x0c2e002e 0x3 12 >, + < 1190400000 0x0404003e 0x0c320032 0x3 13 >, + < 1248000000 0x04040041 0x0d340034 0x3 14 >, + < 1324800000 0x04040045 0x0e370037 0x3 15 >, + < 1401600000 0x04040049 0x0f3a003a 0x3 16 >, + < 1478400000 0x0404004d 0x103e003e 0x3 17 >, + < 1574400000 0x04040052 0x10420042 0x4 18 >, + < 1651200000 0x04040056 0x11450045 0x4 19 >, + < 1728000000 0x0404005a 0x12480048 0x4 20>, + < 1804800000 0x0404005e 0x134b004b 0x4 21 >, + < 1881600000 0x04040062 0x144e004e 0x4 22 >; qcom,perfcl-speedbin0-v0 = - < 300000000 0x0004000f 0x03200020 0x1>, - < 345600000 0x05040012 0x04200020 0x1>, - < 422400000 0x05040016 0x04200020 0x1>, - < 480000000 0x05040019 0x05200020 0x1>, - < 556800000 0x0504001d 0x06200020 0x1>, - < 633600000 0x04040021 0x07200020 0x1>, - < 710400000 0x04040025 0x07200020 0x1>, - < 787200000 0x04040029 0x08210021 0x1>, - < 844800000 0x0404002c 0x09240024 0x2>, - < 902400000 0x0404002f 0x09260026 0x2>, - < 979200000 0x04040033 0x0a290029 0x2>, - < 1056000000 0x04040037 0x0b2c002c 0x2>, - < 1171200000 0x0404003d 0x0c300030 0x3>, - < 1248000000 0x04040041 0x0d340034 0x3>, - < 1324800000 0x04040045 0x0e370037 0x3>, - < 1401600000 0x04040049 0x0f3b003b 0x3>, - < 1478400000 0x0404004d 0x0f3e003e 0x3>, - < 1536000000 0x04040050 0x10400040 0x3>, - < 1632000000 0x04040055 0x11440044 0x4>, - < 1708800000 0x04040059 0x12480048 0x4>, - < 1785600000 0x0404005d 0x134a004a 0x4>, - < 1862400000 0x04040061 0x134e004e 0x4>, - < 1939200000 0x04040065 0x14510051 0x4>, - < 2016000000 0x04040069 0x15540054 0x4>, - < 2092800000 0x0404006d 0x16570057 0x4>; + < 300000000 0x0004000f 0x03200020 0x1 1 >, + < 345600000 0x05040012 0x04200020 0x1 2 >, + < 422400000 0x05040016 0x04200020 0x1 3 >, + < 480000000 0x05040019 0x05200020 0x1 4 >, + < 556800000 0x0504001d 0x06200020 0x1 5 >, + < 633600000 0x04040021 0x07200020 0x1 6 >, + < 710400000 0x04040025 0x07200020 0x1 7 >, + < 787200000 0x04040029 0x08210021 0x1 8 >, + < 844800000 0x0404002c 0x09240024 0x2 9 >, + < 902400000 0x0404002f 0x09260026 0x2 10 >, + < 979200000 0x04040033 0x0a290029 0x2 11 >, + < 1056000000 0x04040037 0x0b2c002c 0x2 12 >, + < 1171200000 0x0404003d 0x0c300030 0x3 13 >, + < 1248000000 0x04040041 0x0d340034 0x3 14 >, + < 1324800000 0x04040045 0x0e370037 0x3 15 >, + < 1401600000 0x04040049 0x0f3b003b 0x3 16 >, + < 1478400000 0x0404004d 0x0f3e003e 0x3 17 >, + < 1536000000 0x04040050 0x10400040 0x3 18 >, + < 1632000000 0x04040055 0x11440044 0x4 19 >, + < 1708800000 0x04040059 0x12480048 0x4 20 >, + < 1785600000 0x0404005d 0x134a004a 0x4 21 >, + < 1862400000 0x04040061 0x134e004e 0x4 22 >, + < 1939200000 0x04040065 0x14510051 0x4 23 >, + < 2016000000 0x04040069 0x15540054 0x4 24 >, + < 2092800000 0x0404006d 0x16570057 0x4 25 >; qcom,osm-no-tz; qcom,osm-pll-setup; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 72f82f444091..1330d2bdc18d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -14,6 +14,7 @@ Required properties : "qcom,gcc-msm8974pro" "qcom,gcc-msm8974pro-ac" "qcom,gcc-msm8996" + "qcom,gcc-msmfalcon" - reg : shall contain base register location and length - #clock-cells : shall contain 1 diff --git a/Documentation/devicetree/bindings/platform/msm/ipa.txt b/Documentation/devicetree/bindings/platform/msm/ipa.txt index f3166d33f9e4..a8db893f6709 100644 --- a/Documentation/devicetree/bindings/platform/msm/ipa.txt +++ b/Documentation/devicetree/bindings/platform/msm/ipa.txt @@ -80,6 +80,8 @@ memory allocation over a PCIe bridge - qcom,rx-polling-sleep-ms: Receive Polling Timeout in millisecond, default is 1 millisecond. - qcom,ipa-polling-iteration: IPA Polling Iteration Count,default is 40. +- qcom,ipa-tz-unlock-reg: Register start addresses and ranges which + need to be unlocked by TZ. IPA pipe sub nodes (A2 static pipes configurations): diff --git a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt index bd236df6c056..199b5c0857f8 100644 --- a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt +++ b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt @@ -78,7 +78,9 @@ First Level Node - FG Gen3 device Definition: Battery current (in mA) at which the fuel gauge will try to scale towards 100%. When the charge current goes above this the SOC should be at 100%. If this property is not - specified, then the default value used will be 125mA. + specified, then the default value used will be -125mA. + This value has to be specified in negative values for + the charging current. - qcom,fg-delta-soc-thr Usage: optional diff --git a/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi b/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi index 6360b54b1013..ba27e3912ee6 100644 --- a/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi +++ b/arch/arm/boot/dts/qcom/msm-audio-lpass.dtsi @@ -370,4 +370,42 @@ compatible = "qcom,adsp-loader"; qcom,adsp-state = <0>; }; + + qcom,msm-dai-tdm-tert-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37152>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36896>; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + pinctrl-names = "default", "sleep"; + dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36896>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-tert-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37153>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36897 >; + qcom,msm-cpudai-tdm-clk-rate = <1536000>; + pinctrl-names = "default", "sleep"; + dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36897 >; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <1>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi new file mode 100644 index 000000000000..399892f52b6f --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi @@ -0,0 +1,377 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/msm/power-on.h> + +&spmi_bus { + qcom,pm2falcon@2 { + compatible = "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm2falcon_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + qcom,secondary-pon-reset; + qcom,hard-reset-poweroff-type = + <PON_POWER_OFF_SHUTDOWN>; + }; + + pm2falcon_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pm2falcon-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + status = "disabled"; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + status = "disabled"; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + status = "disabled"; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + status = "disabled"; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + status = "disabled"; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + status = "disabled"; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + status = "disabled"; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + status = "disabled"; + }; + + }; + }; + + qcom,pm2falcon@3 { + compatible ="qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm2falcon_pwm_1: pwm@b100 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb100 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <1>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <0>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pm2falcon_pwm_2: pwm@b200 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb200 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <2>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <1>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pm2falcon_pwm_3: pwm@b300 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb300 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <3>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <2>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pm2falcon_pwm_4: pwm@b400 { + compatible = "qcom,qpnp-pwm"; + reg = <0xb400 0x100>, + <0xb042 0x7e>; + reg-names = "qpnp-lpg-channel-base", + "qpnp-lpg-lut-base"; + qcom,channel-id = <4>; + qcom,supported-sizes = <6>, <9>; + qcom,ramp-index = <3>; + #pwm-cells = <2>; + status = "disabled"; + }; + + qcom,leds@d000 { + compatible = "qcom,leds-qpnp"; + reg = <0xd000 0x100>; + label = "rgb"; + status = "disabled"; + + red_led: qcom,rgb_0 { + label = "rgb"; + qcom,id = <3>; + qcom,mode = "pwm"; + pwms = <&pm2falcon_pwm_3 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "red"; + linux,default-trigger = + "battery-charging"; + }; + + green_led: qcom,rgb_1 { + label = "rgb"; + qcom,id = <4>; + qcom,mode = "pwm"; + pwms = <&pm2falcon_pwm_2 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "green"; + linux,default-trigger = "battery-full"; + }; + + blue_led: qcom,rgb_2 { + label = "rgb"; + qcom,id = <5>; + qcom,mode = "pwm"; + pwms = <&pm2falcon_pwm_1 0 0>; + qcom,pwm-us = <1000>; + qcom,max-current = <12>; + qcom,default-state = "off"; + linux,name = "blue"; + linux,default-trigger = "boot-indication"; + }; + }; + + pm2falcon_wled: qcom,leds@d800 { + compatible = "qcom,qpnp-wled"; + reg = <0xd800 0x100>, + <0xd900 0x100>, + <0xdc00 0x100>, + <0xde00 0x100>; + reg-names = "qpnp-wled-ctrl-base", + "qpnp-wled-sink-base", + "qpnp-wled-ibb-base", + "qpnp-wled-lab-base"; + interrupts = <0x3 0xd8 0x2>; + interrupt-names = "sc-irq"; + linux,name = "wled"; + linux,default-trigger = "bkl-trigger"; + qcom,fdbk-output = "auto"; + qcom,vref-mv = <350>; + qcom,switch-freq-khz = <800>; + qcom,ovp-mv = <29500>; + qcom,ilim-ma = <980>; + qcom,boost-duty-ns = <26>; + qcom,mod-freq-khz = <9600>; + qcom,dim-mode = "hybrid"; + qcom,hyb-thres = <625>; + qcom,sync-dly-us = <800>; + qcom,fs-curr-ua = <25000>; + qcom,cons-sync-write-delay-us = <1000>; + qcom,en-phase-stag; + qcom,led-strings-list = [00 01 02]; + qcom,en-ext-pfet-sc-pro; + status = "ok"; + }; + + flash_led: qcom,leds@d300 { + compatible = "qcom,qpnp-flash-led-v2"; + reg = <0xd300 0x100>; + label = "flash"; + interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "led-fault-irq", + "all-ramp-down-done-irq", + "all-ramp-up-done-irq"; + qcom,hdrm-auto-mode; + qcom,short-circuit-det; + qcom,open-circuit-det; + qcom,vph-droop-det; + qcom,thermal-derate-en; + qcom,thermal-derate-current = <200 500 1000>; + qcom,isc-delay = <192>; + status = "disabled"; + + pm2falcon_flash0: qcom,flash_0 { + label = "flash"; + qcom,led-name = "led:flash_0"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash0_trigger"; + qcom,id = <0>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm2falcon_flash1: qcom,flash_1 { + label = "flash"; + qcom,led-name = "led:flash_1"; + qcom,max-current = <1500>; + qcom,default-led-trigger = "flash1_trigger"; + qcom,id = <1>; + qcom,current-ma = <1000>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm2falcon_flash2: qcom,flash_2 { + label = "flash"; + qcom,led-name = "led:flash_2"; + qcom,max-current = <750>; + qcom,default-led-trigger = "flash2_trigger"; + qcom,id = <2>; + qcom,current-ma = <500>; + qcom,duration-ms = <1280>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + pinctrl-names = "led_enable","led_disable"; + pinctrl-0 = <&led_enable>; + pinctrl-1 = <&led_disable>; + }; + + pm2falcon_torch0: qcom,torch_0 { + label = "torch"; + qcom,led-name = "led:torch_0"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch0_trigger"; + qcom,id = <0>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm2falcon_torch1: qcom,torch_1 { + label = "torch"; + qcom,led-name = "led:torch_1"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch1_trigger"; + qcom,id = <1>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + }; + + pm2falcon_torch2: qcom,torch_2 { + label = "torch"; + qcom,led-name = "led:torch_2"; + qcom,max-current = <500>; + qcom,default-led-trigger = "torch2_trigger"; + qcom,id = <2>; + qcom,current-ma = <300>; + qcom,ires-ua = <12500>; + qcom,hdrm-voltage-mv = <325>; + qcom,hdrm-vol-hi-lo-win-mv = <100>; + pinctrl-names = "led_enable","led_disable"; + pinctrl-0 = <&led_enable>; + pinctrl-1 = <&led_disable>; + }; + + pm2falcon_switch0: qcom,led_switch_0 { + label = "switch"; + qcom,led-name = "led:switch_0"; + qcom,led-mask = <3>; + qcom,default-led-trigger = "switch0_trigger"; + reg0 { + regulator-name = "pmfalcon_bob"; + max-voltage-uv = <3600000>; + }; + }; + + pm2falcon_switch1: qcom,led_switch_1 { + label = "switch"; + qcom,led-name = "led:switch_1"; + qcom,led-mask = <4>; + qcom,default-led-trigger = "switch1_trigger"; + reg0 { + regulator-name = "pmfalcon_bob"; + max-voltage-uv = <3600000>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi new file mode 100644 index 000000000000..dec37881249c --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi @@ -0,0 +1,169 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/interrupt-controller/irq.h> + +&spmi_bus { + qcom,pmfalcon@0 { + compatible ="qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pmfalcon_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x4 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", + "resin-bark", "kpdpwr-resin-bark"; + qcom,pon-dbc-delay = <15625>; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = <0>; + qcom,pull-up = <1>; + linux,code = <116>; + }; + + qcom,pon_2 { + qcom,pon-type = <1>; + qcom,pull-up = <1>; + linux,code = <114>; + }; + }; + + pmfalcon_gpios: gpios { + compatible = "qcom,qpnp-pin"; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + label = "pmfalcon-gpio"; + + gpio@c000 { + reg = <0xc000 0x100>; + qcom,pin-num = <1>; + status = "disabled"; + }; + + gpio@c100 { + reg = <0xc100 0x100>; + qcom,pin-num = <2>; + status = "disabled"; + }; + + gpio@c200 { + reg = <0xc200 0x100>; + qcom,pin-num = <3>; + status = "disabled"; + }; + + gpio@c300 { + reg = <0xc300 0x100>; + qcom,pin-num = <4>; + status = "disabled"; + }; + + gpio@c400 { + reg = <0xc400 0x100>; + qcom,pin-num = <5>; + status = "disabled"; + }; + + gpio@c500 { + reg = <0xc500 0x100>; + qcom,pin-num = <6>; + status = "disabled"; + }; + + gpio@c600 { + reg = <0xc600 0x100>; + qcom,pin-num = <7>; + status = "disabled"; + }; + + gpio@c700 { + reg = <0xc700 0x100>; + qcom,pin-num = <8>; + status = "disabled"; + }; + + gpio@c800 { + reg = <0xc800 0x100>; + qcom,pin-num = <9>; + status = "disabled"; + }; + + gpio@c900 { + reg = <0xc900 0x100>; + qcom,pin-num = <10>; + status = "disabled"; + }; + + gpio@ca00 { + reg = <0xca00 0x100>; + qcom,pin-num = <11>; + status = "disabled"; + }; + + gpio@cb00 { + reg = <0xcb00 0x100>; + qcom,pin-num = <12>; + status = "disabled"; + }; + + gpio@cc00 { + reg = <0xcc00 0x100>; + qcom,pin-num = <13>; + status = "disabled"; + }; + }; + + pmfalcon_coincell: qcom,coincell@2800 { + compatible = "qcom,qpnp-coincell"; + reg = <0x2800 0x100>; + }; + + pmfalcon_rtc: qcom,pmfalcon_rtc { + compatible = "qcom,qpnp-rtc"; + #address-cells = <1>; + #size-cells = <1>; + qcom,qpnp-rtc-write = <0>; + qcom,qpnp-rtc-alarm-pwrup = <0>; + + qcom,pmfalcon_rtc_rw@6000 { + reg = <0x6000 0x100>; + }; + qcom,pmfalcon_rtc_alarm@6100 { + reg = <0x6100 0x100>; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + }; + }; + + qcom,pmfalcon@1 { + compatible ="qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi index ff4ea42cd767..445f32df8aa4 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi @@ -36,6 +36,18 @@ qcom,model = "msmcobalt-tasha-snd-card"; qcom,ext-disp-audio-rx; qcom,wcn-btfm; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + + reg = <0x1711a000 0x4>, + <0x1711b000 0x4>, + <0x1711c000 0x4>, + <0x1711d000 0x4>; + reg-names = "lpaif_pri_mode_muxsel", + "lpaif_sec_mode_muxsel", + "lpaif_tert_mode_muxsel", + "lpaif_quat_mode_muxsel"; qcom,audio-routing = "AIF4 VI", "MCLK", @@ -94,7 +106,8 @@ <&incall_record_tx>, <&incall_music_rx>, <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, - <&usb_audio_rx>, <&usb_audio_tx>; + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>; asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", @@ -112,7 +125,8 @@ "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673"; + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897"; asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; asoc-codec-names = "msm-stub-codec.1", "msm-ext-disp-audio-codec-rx"; @@ -128,6 +142,18 @@ qcom,model = "msmcobalt-tavil-snd-card"; qcom,ext-disp-audio-rx; qcom,wcn-btfm; + qcom,mi2s-audio-intf; + qcom,auxpcm-audio-intf; + qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; + + reg = <0x1711a000 0x4>, + <0x1711b000 0x4>, + <0x1711c000 0x4>, + <0x1711d000 0x4>; + reg-names = "lpaif_pri_mode_muxsel", + "lpaif_sec_mode_muxsel", + "lpaif_tert_mode_muxsel", + "lpaif_quat_mode_muxsel"; qcom,audio-routing = "RX_BIAS", "MCLK", @@ -184,7 +210,8 @@ <&incall_record_tx>, <&incall_music_rx>, <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>, <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, - <&usb_audio_rx>, <&usb_audio_tx>; + <&usb_audio_rx>, <&usb_audio_tx>, + <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>; asoc-cpu-names = "msm-dai-q6-hdmi.8", "msm-dai-q6-dp.24608", "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3", @@ -202,7 +229,8 @@ "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394", "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", - "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673"; + "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", + "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897"; asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>; asoc-codec-names = "msm-stub-codec.1", "msm-ext-disp-audio-codec-rx"; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi index 154bc5b092df..467b2cbfcd7d 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi @@ -28,7 +28,10 @@ reg-names = "csiphy"; interrupts = <0 78 0>; interrupt-names = "csiphy"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -42,7 +45,7 @@ <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, <&clock_mmss clk_csiphy_clk_src>, <&clock_mmss clk_mmss_camss_csiphy0_clk>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", @@ -60,7 +63,10 @@ reg-names = "csiphy"; interrupts = <0 79 0>; interrupt-names = "csiphy"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -74,7 +80,7 @@ <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, <&clock_mmss clk_csiphy_clk_src>, <&clock_mmss clk_mmss_camss_csiphy1_clk>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", @@ -92,7 +98,10 @@ reg-names = "csiphy"; interrupts = <0 80 0>; interrupt-names = "csiphy"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -106,7 +115,7 @@ <&clock_mmss clk_mmss_camss_ispif_ahb_clk>, <&clock_mmss clk_csiphy_clk_src>, <&clock_mmss clk_mmss_camss_csiphy2_clk>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", @@ -128,8 +137,9 @@ qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pmcobalt_l1>; - qcom,cam-vreg-name = "vdd_sec", "gdscr"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -144,7 +154,7 @@ <&clock_mmss clk_mmss_camss_csi0pix_clk>, <&clock_mmss clk_mmss_camss_cphy_csid0_clk>, <&clock_mmss clk_csiphy_clk_src>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", @@ -166,8 +176,9 @@ qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pmcobalt_l1>; - qcom,cam-vreg-name = "vdd_sec", "gdscr"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -182,7 +193,7 @@ <&clock_mmss clk_mmss_camss_csi1pix_clk>, <&clock_mmss clk_mmss_camss_cphy_csid1_clk>, <&clock_mmss clk_csiphy_clk_src>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", @@ -204,8 +215,9 @@ qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pmcobalt_l1>; - qcom,cam-vreg-name = "vdd_sec", "gdscr"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -220,7 +232,7 @@ <&clock_mmss clk_mmss_camss_csi2pix_clk>, <&clock_mmss clk_mmss_camss_cphy_csid2_clk>, <&clock_mmss clk_csiphy_clk_src>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", @@ -242,8 +254,9 @@ qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; gdscr-supply = <&gdsc_camss_top>; vdd_sec-supply = <&pmcobalt_l1>; - qcom,cam-vreg-name = "vdd_sec", "gdscr"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -257,7 +270,7 @@ <&clock_mmss clk_mmss_camss_csi3pix_clk>, <&clock_mmss clk_mmss_camss_cphy_csid1_clk>, <&clock_mmss clk_csiphy_clk_src>; - clock-names = "mnoc_maxi", "mnoc_ahb", + clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", @@ -687,7 +700,7 @@ mmagic-supply = <&gdsc_bimc_smmu>; gdscr-supply = <&gdsc_camss_top>; qcom,cam-vreg-name = "mmagic", "gdscr"; - clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>, + clocks = <&clock_gcc clk_mmssnoc_axi_clk>, <&clock_mmss clk_mmss_mnoc_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_ahb_clk>, <&clock_mmss clk_mmss_bimc_smmu_axi_clk>, @@ -696,7 +709,7 @@ <&clock_mmss clk_cci_clk_src>, <&clock_mmss clk_mmss_camss_cci_ahb_clk>, <&clock_mmss clk_mmss_camss_cci_clk>; - clock-names = "mnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi", + clock-names = "mmssnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "cci_src_clk", "cci_ahb_clk", "camss_cci_clk"; qcom,clock-rates = <0 0 0 0 0 0 19200000 0 0>, diff --git a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi index 1682a478f606..ad293d9827d1 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi @@ -31,9 +31,9 @@ qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ - qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ - qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ }; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi index 9b7d07c027e4..99402e3033ed 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi @@ -32,9 +32,9 @@ qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-core-current-level = <0>; /* LPM/PFM */ - qca,bt-vdd-pa-current-level = <0>; /* LPM/PFM */ - qca,bt-vdd-ldo-current-level = <0>; /* LPM/PFM */ + qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ + qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ }; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi index f4f47bc461fc..3975bc5d16f5 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi @@ -1779,6 +1779,66 @@ }; }; + tsif0_signals_active: tsif0_signals_active { + tsif1_clk { + pins = "gpio89"; /* TSIF0 CLK */ + function = "tsif1_clk"; + }; + tsif1_en { + pins = "gpio90"; /* TSIF0 Enable */ + function = "tsif1_en"; + }; + tsif1_data { + pins = "gpio91"; /* TSIF0 DATA */ + function = "tsif1_data"; + }; + signals_cfg { + pins = "gpio89", "gpio90", "gpio91"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif0_sync_active: tsif0_sync_active { + tsif1_sync { + pins = "gpio9"; /* TSIF0 SYNC */ + function = "tsif1_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + tsif1_signals_active: tsif1_signals_active { + tsif2_clk { + pins = "gpio93"; /* TSIF1 CLK */ + function = "tsif2_clk"; + }; + tsif2_en { + pins = "gpio94"; /* TSIF1 Enable */ + function = "tsif2_en"; + }; + tsif2_data { + pins = "gpio95"; /* TSIF1 DATA */ + function = "tsif2_data"; + }; + signals_cfg { + pins = "gpio93", "gpio94", "gpio95"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + + /* sync signal is only used if configured to mode-2 */ + tsif1_sync_active: tsif1_sync_active { + tsif2_sync { + pins = "gpio96"; /* TSIF1 SYNC */ + function = "tsif2_sync"; + drive_strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + }; + }; + pri_aux_pcm_clk { pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep { mux { diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi index 8a8d65887441..e19fb5f7c233 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi @@ -28,88 +28,89 @@ compatible = "qcom,cpu-clock-osm-msmcobalt-v2"; /delete-property/ qcom,llm-sw-overr; qcom,pwrcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 >, - < 364800000 0x05040013 0x01200020 0x1 >, - < 441600000 0x05040017 0x02200020 0x1 >, - < 518400000 0x0504001b 0x02200020 0x1 >, - < 595200000 0x0504001f 0x02200020 0x1 >, - < 672000000 0x05040023 0x03200020 0x1 >, - < 748800000 0x05040027 0x03200020 0x1 >, - < 825600000 0x0404002b 0x03220022 0x1 >, - < 883200000 0x0404002e 0x04250025 0x1 >, - < 960000000 0x04040032 0x04280028 0x1 >, - < 1036800000 0x04040036 0x042b002b 0x1 >, - < 1094400000 0x04040039 0x052e002e 0x2 >, - < 1171200000 0x0404003d 0x05310031 0x2 >, - < 1248000000 0x04040041 0x05340034 0x2 >, - < 1324800000 0x04040045 0x06370037 0x2 >, - < 1401600000 0x04040049 0x063a003a 0x2 >, - < 1478400000 0x0404004d 0x073e003e 0x2 >, - < 1555200000 0x04040051 0x07410041 0x2 >, - < 1670400000 0x04040057 0x08460046 0x2 >, - < 1747200000 0x0404005b 0x08490049 0x2 >, - < 1824000000 0x0404005f 0x084c004c 0x3 >, - < 1900800000 0x04040063 0x094f004f 0x3 >; + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 364800000 0x05040013 0x01200020 0x1 2 >, + < 441600000 0x05040017 0x02200020 0x1 3 >, + < 518400000 0x0504001b 0x02200020 0x1 4 >, + < 595200000 0x0504001f 0x02200020 0x1 5 >, + < 672000000 0x05040023 0x03200020 0x1 6 >, + < 748800000 0x05040027 0x03200020 0x1 7 >, + < 825600000 0x0404002b 0x03220022 0x1 8 >, + < 883200000 0x0404002e 0x04250025 0x1 9 >, + < 960000000 0x04040032 0x04280028 0x1 10 >, + < 1036800000 0x04040036 0x042b002b 0x1 11 >, + < 1094400000 0x04040039 0x052e002e 0x2 12 >, + < 1171200000 0x0404003d 0x05310031 0x2 13 >, + < 1248000000 0x04040041 0x05340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x063a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1555200000 0x04040051 0x07410041 0x2 18 >, + < 1670400000 0x04040057 0x08460046 0x2 19 >, + < 1747200000 0x0404005b 0x08490049 0x2 20 >, + < 1824000000 0x0404005f 0x084c004c 0x3 21 >, + < 1900800000 0x04040063 0x094f004f 0x3 22 >; qcom,perfcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 >, - < 345600000 0x05040012 0x01200020 0x1 >, - < 422400000 0x05040016 0x02200020 0x1 >, - < 499200000 0x0504001a 0x02200020 0x1 >, - < 576000000 0x0504001e 0x02200020 0x1 >, - < 652800000 0x05040022 0x03200020 0x1 >, - < 729600000 0x05040026 0x03200020 0x1 >, - < 806400000 0x0504002a 0x03220022 0x1 >, - < 902400000 0x0404002f 0x04260026 0x1 >, - < 979200000 0x04040033 0x04290029 0x1 >, - < 1056000000 0x04040037 0x052c002c 0x1 >, - < 1132800000 0x0404003b 0x052f002f 0x1 >, - < 1190400000 0x0404003e 0x05320032 0x2 >, - < 1267200000 0x04040042 0x06350035 0x2 >, - < 1344000000 0x04040046 0x06380038 0x2 >, - < 1420800000 0x0404004a 0x063b003b 0x2 >, - < 1497600000 0x0404004e 0x073e003e 0x2 >, - < 1574400000 0x04040052 0x07420042 0x2 >, - < 1651200000 0x04040056 0x07450045 0x2 >, - < 1728000000 0x0404005a 0x08480048 0x2 >, - < 1804800000 0x0404005e 0x084b004b 0x2 >, - < 1881600000 0x04040062 0x094e004e 0x2 >, - < 1958400000 0x04040066 0x09520052 0x2 >, - < 2035200000 0x0404006a 0x09550055 0x3 >, - < 2112000000 0x0404006e 0x0a580058 0x3 >, - < 2188800000 0x04040072 0x0a5b005b 0x3 >, - < 2265600000 0x04040076 0x0a5e005e 0x3 >, - < 2342400000 0x0404007a 0x0a620062 0x3 >, - < 2419200000 0x0404007e 0x0a650065 0x3 >, - < 2496000000 0x04040082 0x0a680068 0x3 >; + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2188800000 0x04040072 0x0a5b005b 0x3 26 >, + < 2265600000 0x04040076 0x0a5e005e 0x3 27 >, + < 2342400000 0x0404007a 0x0a620062 0x3 28 >, + < 2419200000 0x0404007e 0x0a650065 0x3 29 >, + < 2496000000 0x04040082 0x0a680068 0x3 30 >; qcom,perfcl-speedbin1-v0 = - < 300000000 0x0004000f 0x01200020 0x1 >, - < 345600000 0x05040012 0x01200020 0x1 >, - < 422400000 0x05040016 0x02200020 0x1 >, - < 499200000 0x0504001a 0x02200020 0x1 >, - < 576000000 0x0504001e 0x02200020 0x1 >, - < 652800000 0x05040022 0x03200020 0x1 >, - < 729600000 0x05040026 0x03200020 0x1 >, - < 806400000 0x0504002a 0x03220022 0x1 >, - < 902400000 0x0404002f 0x04260026 0x1 >, - < 979200000 0x04040033 0x04290029 0x1 >, - < 1056000000 0x04040037 0x052c002c 0x1 >, - < 1132800000 0x0404003b 0x052f002f 0x1 >, - < 1190400000 0x0404003e 0x05320032 0x2 >, - < 1267200000 0x04040042 0x06350035 0x2 >, - < 1344000000 0x04040046 0x06380038 0x2 >, - < 1420800000 0x0404004a 0x063b003b 0x2 >, - < 1497600000 0x0404004e 0x073e003e 0x2 >, - < 1574400000 0x04040052 0x07420042 0x2 >, - < 1651200000 0x04040056 0x07450045 0x2 >, - < 1728000000 0x0404005a 0x08480048 0x2 >, - < 1804800000 0x0404005e 0x084b004b 0x2 >, - < 1881600000 0x04040062 0x094e004e 0x2 >, - < 1958400000 0x04040066 0x09520052 0x2 >, - < 2035200000 0x0404006a 0x09550055 0x3 >, - < 2112000000 0x0404006e 0x0a580058 0x3 >, - < 2208000000 0x04040073 0x0a5c005c 0x3 >; + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x01200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x02200020 0x1 5 >, + < 652800000 0x05040022 0x03200020 0x1 6 >, + < 729600000 0x05040026 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x03220022 0x1 8 >, + < 902400000 0x0404002f 0x04260026 0x1 9 >, + < 979200000 0x04040033 0x04290029 0x1 10 >, + < 1056000000 0x04040037 0x052c002c 0x1 11 >, + < 1132800000 0x0404003b 0x052f002f 0x1 12 >, + < 1190400000 0x0404003e 0x05320032 0x2 13 >, + < 1267200000 0x04040042 0x06350035 0x2 14 >, + < 1344000000 0x04040046 0x06380038 0x2 15 >, + < 1420800000 0x0404004a 0x063b003b 0x2 16 >, + < 1497600000 0x0404004e 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x07420042 0x2 18 >, + < 1651200000 0x04040056 0x07450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x084b004b 0x2 21 >, + < 1881600000 0x04040062 0x094e004e 0x2 22 >, + < 1958400000 0x04040066 0x09520052 0x2 23 >, + < 2035200000 0x0404006a 0x09550055 0x3 24 >, + < 2112000000 0x0404006e 0x0a580058 0x3 25 >, + < 2208000000 0x04040073 0x0a5c005c 0x3 26 >, + < 2304000000 0x04010078 0x0a5c005c 0x3 26 >; }; &msm_cpufreq { @@ -202,8 +203,7 @@ < 414000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >, < 515000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >, < 596000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >, - < 710000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >; + < 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >; qcom,gfxfreq-mx-speedbin0 = < 0 0 >, < 180000000 RPM_SMD_REGULATOR_LEVEL_SVS >, @@ -212,8 +212,7 @@ < 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >, < 515000000 RPM_SMD_REGULATOR_LEVEL_NOM >, < 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >, - < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >, - < 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; + < 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >; }; &mdss_mdp { diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index d3f50aa267c5..27f9e2ace106 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -823,55 +823,55 @@ interrupt-names = "pwrcl-irq", "perfcl-irq"; qcom,pwrcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 >, - < 345600000 0x05040012 0x02200020 0x1 >, - < 422400000 0x05040016 0x02200020 0x1 >, - < 499200000 0x0504001a 0x02200020 0x1 >, - < 576000000 0x0504001e 0x03200020 0x1 >, - < 633600000 0x05040021 0x03200020 0x1 >, - < 710400000 0x05040025 0x03200020 0x1 >, - < 806400000 0x0504002a 0x04200020 0x1 >, - < 883200000 0x0404002e 0x04250025 0x1 >, - < 960000000 0x04040032 0x05280028 0x1 >, - < 1036800000 0x04040036 0x052b002b 0x2 >, - < 1113600000 0x0404003a 0x052e002e 0x2 >, - < 1190400000 0x0404003e 0x06320032 0x2 >, - < 1248000000 0x04040041 0x06340034 0x2 >, - < 1324800000 0x04040045 0x06370037 0x2 >, - < 1401600000 0x04040049 0x073a003a 0x2 >, - < 1478400000 0x0404004d 0x073e003e 0x2 >, - < 1574400000 0x04040052 0x08420042 0x2 >, - < 1651200000 0x04040056 0x08450045 0x2 >, - < 1728000000 0x0404005a 0x08480048 0x2 >, - < 1804800000 0x0404005e 0x094b004b 0x3 >, - < 1881600000 0x04040062 0x094e004e 0x3 >; + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x02200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 499200000 0x0504001a 0x02200020 0x1 4 >, + < 576000000 0x0504001e 0x03200020 0x1 5 >, + < 633600000 0x05040021 0x03200020 0x1 6 >, + < 710400000 0x05040025 0x03200020 0x1 7 >, + < 806400000 0x0504002a 0x04200020 0x1 8 >, + < 883200000 0x0404002e 0x04250025 0x1 9 >, + < 960000000 0x04040032 0x05280028 0x1 10 >, + < 1036800000 0x04040036 0x052b002b 0x2 11 >, + < 1113600000 0x0404003a 0x052e002e 0x2 12 >, + < 1190400000 0x0404003e 0x06320032 0x2 13 >, + < 1248000000 0x04040041 0x06340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x073a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1574400000 0x04040052 0x08420042 0x2 18 >, + < 1651200000 0x04040056 0x08450045 0x2 19 >, + < 1728000000 0x0404005a 0x08480048 0x2 20 >, + < 1804800000 0x0404005e 0x094b004b 0x3 21 >, + < 1881600000 0x04040062 0x094e004e 0x3 22 >; qcom,perfcl-speedbin0-v0 = - < 300000000 0x0004000f 0x01200020 0x1 >, - < 345600000 0x05040012 0x02200020 0x1 >, - < 422400000 0x05040016 0x02200020 0x1 >, - < 480000000 0x05040019 0x02200020 0x1 >, - < 556800000 0x0504001d 0x03200020 0x1 >, - < 633600000 0x05040021 0x03200020 0x1 >, - < 710400000 0x05040025 0x03200020 0x1 >, - < 787200000 0x05040029 0x04200020 0x1 >, - < 844800000 0x0404002c 0x04230023 0x1 >, - < 902400000 0x0404002f 0x04260026 0x1 >, - < 979200000 0x04040033 0x05290029 0x1 >, - < 1056000000 0x04040037 0x052c002c 0x1 >, - < 1171200000 0x0404003d 0x06310031 0x2 >, - < 1248000000 0x04040041 0x06340034 0x2 >, - < 1324800000 0x04040045 0x06370037 0x2 >, - < 1401600000 0x04040049 0x073a003a 0x2 >, - < 1478400000 0x0404004d 0x073e003e 0x2 >, - < 1536000000 0x04040050 0x07400040 0x2 >, - < 1632000000 0x04040055 0x08440044 0x2 >, - < 1708800000 0x04040059 0x08470047 0x2 >, - < 1785600000 0x0404005d 0x094a004a 0x2 >, - < 1862400000 0x04040061 0x094e004e 0x2 >, - < 1939200000 0x04040065 0x09510051 0x3 >, - < 2016000000 0x04040069 0x0a540054 0x3 >, - < 2092800000 0x0404006d 0x0a570057 0x3 >; + < 300000000 0x0004000f 0x01200020 0x1 1 >, + < 345600000 0x05040012 0x02200020 0x1 2 >, + < 422400000 0x05040016 0x02200020 0x1 3 >, + < 480000000 0x05040019 0x02200020 0x1 4 >, + < 556800000 0x0504001d 0x03200020 0x1 5 >, + < 633600000 0x05040021 0x03200020 0x1 6 >, + < 710400000 0x05040025 0x03200020 0x1 7 >, + < 787200000 0x05040029 0x04200020 0x1 8 >, + < 844800000 0x0404002c 0x04230023 0x1 9 >, + < 902400000 0x0404002f 0x04260026 0x1 10 >, + < 979200000 0x04040033 0x05290029 0x1 11 >, + < 1056000000 0x04040037 0x052c002c 0x1 12 >, + < 1171200000 0x0404003d 0x06310031 0x2 13 >, + < 1248000000 0x04040041 0x06340034 0x2 14 >, + < 1324800000 0x04040045 0x06370037 0x2 15 >, + < 1401600000 0x04040049 0x073a003a 0x2 16 >, + < 1478400000 0x0404004d 0x073e003e 0x2 17 >, + < 1536000000 0x04040050 0x07400040 0x2 18 >, + < 1632000000 0x04040055 0x08440044 0x2 19 >, + < 1708800000 0x04040059 0x08470047 0x2 20 >, + < 1785600000 0x0404005d 0x094a004a 0x2 21 >, + < 1862400000 0x04040061 0x094e004e 0x2 22 >, + < 1939200000 0x04040065 0x09510051 0x3 23 >, + < 2016000000 0x04040069 0x0a540054 0x3 24 >, + < 2092800000 0x0404006d 0x0a570057 0x3 25 >; qcom,up-timer = <1000 1000>; @@ -2886,6 +2886,57 @@ qcom,icnss-adc_tm = <&pmcobalt_adc_tm>; }; + tspp: msm_tspp@0c1e7000 { + compatible = "qcom,msm_tspp"; + reg = <0x0c1e7000 0x200>, /* MSM_TSIF0_PHYS */ + <0x0c1e8000 0x200>, /* MSM_TSIF1_PHYS */ + <0x0c1e9000 0x1000>, /* MSM_TSPP_PHYS */ + <0x0c1c4000 0x23000>; /* MSM_TSPP_BAM_PHYS */ + reg-names = "MSM_TSIF0_PHYS", + "MSM_TSIF1_PHYS", + "MSM_TSPP_PHYS", + "MSM_TSPP_BAM_PHYS"; + interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */ + <0 119 0>, /* TSIF0_IRQ */ + <0 120 0>, /* TSIF1_IRQ */ + <0 122 0>; /* TSIF_BAM_IRQ */ + interrupt-names = "TSIF_TSPP_IRQ", + "TSIF0_IRQ", + "TSIF1_IRQ", + "TSIF_BAM_IRQ"; + + clock-names = "iface_clk", "ref_clk"; + clocks = <&clock_gcc clk_gcc_tsif_ahb_clk>, + <&clock_gcc clk_gcc_tsif_ref_clk>; + + qcom,msm-bus,name = "tsif"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <82 512 0 0>, /* No vote */ + <82 512 12288 24576>; + /* Max. bandwidth, 2xTSIF, each max of 96Mbps */ + + pinctrl-names = "disabled", + "tsif0-mode1", "tsif0-mode2", + "tsif1-mode1", "tsif1-mode2", + "dual-tsif-mode1", "dual-tsif-mode2"; + + pinctrl-0 = <>; /* disabled */ + pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */ + pinctrl-2 = <&tsif0_signals_active + &tsif0_sync_active>; /* tsif0-mode2 */ + pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */ + pinctrl-4 = <&tsif1_signals_active + &tsif1_sync_active>; /* tsif1-mode2 */ + pinctrl-5 = <&tsif0_signals_active + &tsif1_signals_active>; /* dual-tsif-mode1 */ + pinctrl-6 = <&tsif0_signals_active + &tsif0_sync_active + &tsif1_signals_active + &tsif1_sync_active>; /* dual-tsif-mode2 */ + }; + wil6210: qcom,wil6210 { compatible = "qcom,wil6210"; qcom,pcie-parent = <&pcie0>; @@ -2933,16 +2984,10 @@ }; &gdsc_usb30 { - clock-names = "core_clk"; - clocks = <&clock_gcc clk_gcc_usb30_master_clk>; status = "ok"; }; &gdsc_pcie_0 { - clock-names = "master_bus_clk", "slave_bus_clk", "core_clk"; - clocks = <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>, - <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>, - <&clock_gcc clk_gcc_pcie_0_pipe_clk>; status = "ok"; }; @@ -3000,19 +3045,14 @@ }; &gdsc_mdss { - clock-names = "bus_clk", "rot_clk"; - clocks = <&clock_mmss clk_mmss_mdss_axi_clk>, - <&clock_mmss clk_mmss_mdss_rot_clk>; proxy-supply = <&gdsc_mdss>; qcom,proxy-consumer-enable; status = "ok"; }; &gdsc_gpu_gx { - clock-names = "bimc_core_clk", "core_clk", "core_root_clk"; - clocks = <&clock_gcc clk_gcc_gpu_bimc_gfx_clk>, - <&clock_gfx clk_gpucc_gfx3d_clk>, - <&clock_gfx clk_gfx3d_clk_src>; + clock-names = "core_root_clk"; + clocks = <&clock_gfx clk_gfx3d_clk_src>; qcom,force-enable-root-clk; parent-supply = <&gfx_vreg>; status = "ok"; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi index 352856965373..b60d4013dad8 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi @@ -26,6 +26,8 @@ arm,buffer-size = <0x400000>; arm,sg-enable; + coresight-ctis = <&cti0 &cti8>; + coresight-name = "coresight-tmc-etr"; clocks = <&clock_gcc RPM_QDSS_CLK>, @@ -76,6 +78,8 @@ coresight-name = "coresight-tmc-etf"; + coresight-ctis = <&cti0 &cti8>; + clocks = <&clock_gcc RPM_QDSS_CLK>, <&clock_gcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "core_a_clk"; @@ -161,6 +165,14 @@ <&funnel_merg_in_funnel_in0>; }; }; + port@3 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + slave-mode; + remote-endpoint = + <&funnel_qatb_out_funnel_in0>; + }; + }; port@4 { reg = <7>; funnel_in0_in_stm: endpoint { @@ -191,4 +203,294 @@ }; }; }; + + cti0: cti@6010000 { + compatible = "arm,coresight-cti"; + reg = <0x6010000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti0"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti1: cti@6011000 { + compatible = "arm,coresight-cti"; + reg = <0x6011000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti1"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti2: cti@6012000 { + compatible = "arm,coresight-cti"; + reg = <0x6012000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti2"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti3: cti@6013000 { + compatible = "arm,coresight-cti"; + reg = <0x6013000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti3"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti4: cti@6014000 { + compatible = "arm,coresight-cti"; + reg = <0x6014000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti4"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti5: cti@6015000 { + compatible = "arm,coresight-cti"; + reg = <0x6015000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti5"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti6: cti@6016000 { + compatible = "arm,coresight-cti"; + reg = <0x6016000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti6"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti7: cti@6017000 { + compatible = "arm,coresight-cti"; + reg = <0x6017000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti7"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti8: cti@6018000 { + compatible = "arm,coresight-cti"; + reg = <0x6018000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti8"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti9: cti@6019000 { + compatible = "arm,coresight-cti"; + reg = <0x6019000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti9"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti10: cti@601a000 { + compatible = "arm,coresight-cti"; + reg = <0x601a000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti10"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti11: cti@601b000 { + compatible = "arm,coresight-cti"; + reg = <0x601b000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti11"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti12: cti@601c000 { + compatible = "arm,coresight-cti"; + reg = <0x601c000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti12"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti13: cti@601d000 { + compatible = "arm,coresight-cti"; + reg = <0x601d000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti13"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti14: cti@601e000 { + compatible = "arm,coresight-cti"; + reg = <0x601e000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti14"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti15: cti@601f000 { + compatible = "arm,coresight-cti"; + reg = <0x601f000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti15"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + }; + + funnel_qatb: funnel@6005000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x0003b908>; + + reg = <0x6005000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel-qatb"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = + <&funnel_in0_in_funnel_qatb>; + }; + }; + port@1 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + slave-mode; + remote-endpoint = + <&tpda_out_funnel_qatb>; + }; + }; + }; + }; + + tpda: tpda@6004000 { + compatible = "qcom,coresight-tpda"; + reg = <0x6004000 0x1000>; + reg-names = "tpda-base"; + + coresight-name = "coresight-tpda"; + + qcom,tpda-atid = <65>; + qcom,bc-elem-size = <7 32>, + <9 32>; + qcom,tc-elem-size = <3 32>, + <6 32>, + <9 32>; + qcom,dsb-elem-size = <7 32>, + <9 32>; + qcom,cmb-elem-size = <3 32>, + <4 32>, + <5 32>, + <9 64>; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = + <&funnel_qatb_in_tpda>; + }; + }; + port@2 { + reg = <5>; + tpda_in_tpdm_dcc: endpoint { + slave-mode; + remote-endpoint = + <&tpdm_dcc_out_tpda>; + }; + }; + }; + }; + + tpdm_dcc: tpdm@7054000 { + compatible = "qcom,coresight-tpdm"; + reg = <0x7054000 0x1000>; + reg-names = "tpdm-base"; + + coresight-name = "coresight-tpdm-dcc"; + + clocks = <&clock_gcc RPM_QDSS_CLK>, + <&clock_gcc RPM_QDSS_A_CLK>; + clock-names = "core_clk", "core_a_clk"; + + port{ + tpdm_dcc_out_tpda: endpoint { + remote-endpoint = <&tpda_in_tpdm_dcc>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi index 6a000e4d4fd0..d28d09c2a527 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi @@ -32,5 +32,21 @@ bias-disable; }; }; + + led_enable: led_enable { + mux { + pins = "gpio40"; + drive_strength = <16>; + output-high; + }; + }; + + led_disable: led_disable { + mux { + pins = "gpio40"; + drive_strength = <2>; + output-low; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index 40045b522825..67748d6683c0 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -231,6 +231,39 @@ clock-frequency = <19200000>; }; + spmi_bus: qcom,spmi@800f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x800f000 0x1000>, + <0x8400000 0x1000000>, + <0x9400000 0x1000000>, + <0xa400000 0x220000>, + <0x800a000 0x3000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + qcom,not-wakeup; /* Needed until Full-boot-chain enabled */ + status = "ok"; + }; + + wdog: qcom,wdt@17817000 { + status = "disabled"; + compatible = "qcom,msm-watchdog"; + reg = <0x17817000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 3 0>, <0 4 0>; + qcom,bark-time = <11000>; + qcom,pet-time = <10000>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + qcom,sps { compatible = "qcom,msm_sps_4k"; qcom,pipe-attr-ee; @@ -359,6 +392,16 @@ qcom,mpu-enabled; }; + dcc: dcc@10b3000 { + compatible = "qcom,dcc"; + reg = <0x10b3000 0x1000>, + <0x10b4000 0x800>; + reg-names = "dcc-base", "dcc-ram-base"; + + clocks = <&clock_gcc RPM_QDSS_CLK>; + clock-names = "dcc_clk"; + }; + qcom,glink-smem-native-xprt-modem@86000000 { compatible = "qcom,glink-smem-native-xprt"; reg = <0x86000000 0x200000>, @@ -656,3 +699,5 @@ &gdsc_gpu_cx { status = "ok"; }; +#include "msm-pmfalcon.dtsi" +#include "msm-pm2falcon.dtsi" diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index 598323a1842e..e683d147816c 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -190,6 +190,13 @@ static int __init parse_cluster(struct device_node *cluster, int depth) return 0; } +static DEFINE_PER_CPU(unsigned long, cpu_efficiency) = SCHED_CAPACITY_SCALE; + +unsigned long arch_get_cpu_efficiency(int cpu) +{ + return per_cpu(cpu_efficiency, cpu); +} + #ifdef CONFIG_OF struct cpu_efficiency { const char *compatible; @@ -266,6 +273,7 @@ static int __init parse_dt_topology(void) for_each_possible_cpu(cpu) { const u32 *rate; int len; + u32 efficiency; /* too early to use cpu->of_node */ cn = of_get_cpu_node(cpu, NULL); @@ -274,12 +282,26 @@ static int __init parse_dt_topology(void) continue; } - for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++) - if (of_device_is_compatible(cn, cpu_eff->compatible)) - break; + /* + * The CPU efficiency value passed from the device tree + * overrides the value defined in the table_efficiency[] + */ + if (of_property_read_u32(cn, "efficiency", &efficiency) < 0) { + + for (cpu_eff = table_efficiency; + cpu_eff->compatible; cpu_eff++) - if (cpu_eff->compatible == NULL) - continue; + if (of_device_is_compatible(cn, + cpu_eff->compatible)) + break; + + if (cpu_eff->compatible == NULL) + continue; + + efficiency = cpu_eff->efficiency; + } + + per_cpu(cpu_efficiency, cpu) = efficiency; rate = of_get_property(cn, "clock-frequency", &len); if (!rate || len != 4) { @@ -288,7 +310,7 @@ static int __init parse_dt_topology(void) continue; } - capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency; + capacity = ((be32_to_cpup(rate)) >> 20) * efficiency; /* Save min capacity of the system */ if (capacity < min_capacity) diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig index d50144eed016..50c8848bc6f9 100644 --- a/arch/arm64/configs/msmcortex-perf_defconfig +++ b/arch/arm64/configs/msmcortex-perf_defconfig @@ -273,7 +273,6 @@ CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig index 689255d2f164..3d1a01491c0c 100644 --- a/arch/arm64/configs/msmcortex_defconfig +++ b/arch/arm64/configs/msmcortex_defconfig @@ -274,7 +274,6 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_JOYSTICK=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v21=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV_v21=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 3691553f218e..c3c6557eb083 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -19,6 +19,7 @@ #include <asm/cpu.h> #include <asm/cputype.h> #include <asm/cpufeature.h> +#include <asm/elf.h> #include <linux/bitops.h> #include <linux/bug.h> @@ -107,6 +108,8 @@ static int c_show(struct seq_file *m, void *v) { int i, j; + seq_printf(m, "Processor\t: AArch64 Processor rev %d (%s)\n", + read_cpuid_id() & 15, ELF_PLATFORM); for_each_present_cpu(i) { struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); u32 midr = cpuinfo->reg_midr; diff --git a/block/blk-mq-cpumap.c b/block/blk-mq-cpumap.c index 8764c241e5bb..8cf06af3036e 100644 --- a/block/blk-mq-cpumap.c +++ b/block/blk-mq-cpumap.c @@ -31,8 +31,8 @@ static int get_first_sibling(unsigned int cpu) return cpu; } -int blk_mq_update_queue_map(unsigned int *map, unsigned int nr_queues, - const struct cpumask *online_mask) +static int blk_mq_update_queue_map(unsigned int *map, + unsigned int nr_queues, const struct cpumask *online_mask) { unsigned int i, nr_cpus, nr_uniq_cpus, queue, first_sibling; cpumask_var_t cpus; @@ -52,18 +52,14 @@ int blk_mq_update_queue_map(unsigned int *map, unsigned int nr_queues, queue = 0; for_each_possible_cpu(i) { - if (!cpumask_test_cpu(i, online_mask)) { - map[i] = 0; - continue; - } - /* * Easy case - we have equal or more hardware queues. Or * there are no thread siblings to take into account. Do * 1:1 if enough, or sequential mapping if less. */ - if (nr_queues >= nr_cpus || nr_cpus == nr_uniq_cpus) { - map[i] = cpu_to_queue_index(nr_cpus, nr_queues, queue); + if (nr_queues >= nr_cpu_ids) { + map[i] = cpu_to_queue_index(nr_cpu_ids, nr_queues, + queue); queue++; continue; } @@ -75,7 +71,7 @@ int blk_mq_update_queue_map(unsigned int *map, unsigned int nr_queues, */ first_sibling = get_first_sibling(i); if (first_sibling == i) { - map[i] = cpu_to_queue_index(nr_uniq_cpus, nr_queues, + map[i] = cpu_to_queue_index(nr_cpu_ids, nr_queues, queue); queue++; } else diff --git a/block/blk-mq.c b/block/blk-mq.c index 6d6f8feb48c0..8398e18d4139 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -1783,10 +1783,6 @@ static void blk_mq_init_cpu_queues(struct request_queue *q, INIT_LIST_HEAD(&__ctx->rq_list); __ctx->queue = q; - /* If the cpu isn't online, the cpu is mapped to first hctx */ - if (!cpu_online(i)) - continue; - hctx = q->mq_ops->map_queue(q, i); /* @@ -1820,12 +1816,9 @@ static void blk_mq_map_swqueue(struct request_queue *q, * Map software to hardware queues */ queue_for_each_ctx(q, ctx, i) { - /* If the cpu isn't online, the cpu is mapped to first hctx */ - if (!cpumask_test_cpu(i, online_mask)) - continue; - hctx = q->mq_ops->map_queue(q, i); - cpumask_set_cpu(i, hctx->cpumask); + if (cpumask_test_cpu(i, online_mask)) + cpumask_set_cpu(i, hctx->cpumask); ctx->index_hw = hctx->nr_ctx; hctx->ctxs[hctx->nr_ctx++] = ctx; } @@ -1863,17 +1856,22 @@ static void blk_mq_map_swqueue(struct request_queue *q, /* * Initialize batch roundrobin counts + * Set next_cpu for only those hctxs that have an online CPU + * in their cpumask field. For hctxs that belong to few online + * and few offline CPUs, this will always provide one CPU from + * online ones. For hctxs belonging to all offline CPUs, their + * cpumask will be updated in reinit_notify. */ - hctx->next_cpu = cpumask_first(hctx->cpumask); - hctx->next_cpu_batch = BLK_MQ_CPU_WORK_BATCH; + if (cpumask_first(hctx->cpumask) < nr_cpu_ids) { + hctx->next_cpu = cpumask_first(hctx->cpumask); + hctx->next_cpu_batch = BLK_MQ_CPU_WORK_BATCH; + } } queue_for_each_ctx(q, ctx, i) { - if (!cpumask_test_cpu(i, online_mask)) - continue; - hctx = q->mq_ops->map_queue(q, i); - cpumask_set_cpu(i, hctx->tags->cpumask); + if (cpumask_test_cpu(i, online_mask)) + cpumask_set_cpu(i, hctx->tags->cpumask); } } @@ -2101,38 +2099,13 @@ void blk_mq_free_queue(struct request_queue *q) blk_mq_free_hw_queues(q, set); } -/* Basically redo blk_mq_init_queue with queue frozen */ -static void blk_mq_queue_reinit(struct request_queue *q, - const struct cpumask *online_mask) -{ - WARN_ON_ONCE(!atomic_read(&q->mq_freeze_depth)); - - blk_mq_sysfs_unregister(q); - - blk_mq_update_queue_map(q->mq_map, q->nr_hw_queues, online_mask); - - /* - * redo blk_mq_init_cpu_queues and blk_mq_init_hw_queues. FIXME: maybe - * we should change hctx numa_node according to new topology (this - * involves free and re-allocate memory, worthy doing?) - */ - - blk_mq_map_swqueue(q, online_mask); - - blk_mq_sysfs_register(q); -} - static int blk_mq_queue_reinit_notify(struct notifier_block *nb, unsigned long action, void *hcpu) { struct request_queue *q; + struct blk_mq_hw_ctx *hctx; + int i; int cpu = (unsigned long)hcpu; - /* - * New online cpumask which is going to be set in this hotplug event. - * Declare this cpumasks as global as cpu-hotplug operation is invoked - * one-by-one and dynamically allocating this could result in a failure. - */ - static struct cpumask online_new; /* * Before hotadded cpu starts handling requests, new mappings must @@ -2154,44 +2127,31 @@ static int blk_mq_queue_reinit_notify(struct notifier_block *nb, switch (action & ~CPU_TASKS_FROZEN) { case CPU_DEAD: case CPU_UP_CANCELED: - cpumask_copy(&online_new, cpu_online_mask); + mutex_lock(&all_q_mutex); + list_for_each_entry(q, &all_q_list, all_q_node) { + queue_for_each_hw_ctx(q, hctx, i) { + cpumask_clear_cpu(cpu, hctx->cpumask); + cpumask_clear_cpu(cpu, hctx->tags->cpumask); + } + } + mutex_unlock(&all_q_mutex); break; case CPU_UP_PREPARE: - cpumask_copy(&online_new, cpu_online_mask); - cpumask_set_cpu(cpu, &online_new); + /* Update hctx->cpumask for newly onlined CPUs */ + mutex_lock(&all_q_mutex); + list_for_each_entry(q, &all_q_list, all_q_node) { + queue_for_each_hw_ctx(q, hctx, i) { + cpumask_set_cpu(cpu, hctx->cpumask); + hctx->next_cpu_batch = BLK_MQ_CPU_WORK_BATCH; + cpumask_set_cpu(cpu, hctx->tags->cpumask); + } + } + mutex_unlock(&all_q_mutex); break; default: return NOTIFY_OK; } - mutex_lock(&all_q_mutex); - - /* - * We need to freeze and reinit all existing queues. Freezing - * involves synchronous wait for an RCU grace period and doing it - * one by one may take a long time. Start freezing all queues in - * one swoop and then wait for the completions so that freezing can - * take place in parallel. - */ - list_for_each_entry(q, &all_q_list, all_q_node) - blk_mq_freeze_queue_start(q); - list_for_each_entry(q, &all_q_list, all_q_node) { - blk_mq_freeze_queue_wait(q); - - /* - * timeout handler can't touch hw queue during the - * reinitialization - */ - del_timer_sync(&q->timeout); - } - - list_for_each_entry(q, &all_q_list, all_q_node) - blk_mq_queue_reinit(q, &online_new); - - list_for_each_entry(q, &all_q_list, all_q_node) - blk_mq_unfreeze_queue(q); - - mutex_unlock(&all_q_mutex); return NOTIFY_OK; } diff --git a/block/blk-mq.h b/block/blk-mq.h index 713820b47b31..7fd11bcaa409 100644 --- a/block/blk-mq.h +++ b/block/blk-mq.h @@ -48,8 +48,6 @@ void blk_mq_disable_hotplug(void); * CPU -> queue mappings */ extern unsigned int *blk_mq_make_queue_map(struct blk_mq_tag_set *set); -extern int blk_mq_update_queue_map(unsigned int *map, unsigned int nr_queues, - const struct cpumask *online_mask); extern int blk_mq_hw_queue_to_node(unsigned int *map, unsigned int); /* diff --git a/drivers/clk/msm/clock-gpu-cobalt.c b/drivers/clk/msm/clock-gpu-cobalt.c index 7cec9be1f42c..9d93351a083e 100644 --- a/drivers/clk/msm/clock-gpu-cobalt.c +++ b/drivers/clk/msm/clock-gpu-cobalt.c @@ -173,7 +173,6 @@ static struct clk_freq_tbl ftbl_gfx3d_clk_src_v2[] = { F_SLEW( 515000000, 1030000000, gpu_pll0_pll_out_even, 1, 0, 0), F_SLEW( 596000000, 1192000000, gpu_pll0_pll_out_even, 1, 0, 0), F_SLEW( 670000000, 1340000000, gpu_pll0_pll_out_even, 1, 0, 0), - F_SLEW( 710000000, 1420000000, gpu_pll0_pll_out_even, 1, 0, 0), F_END }; @@ -612,7 +611,7 @@ static void msm_gfxcc_hamster_fixup(void) static void msm_gfxcc_cobalt_v2_fixup(void) { - gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1420000500; + gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1340000500; gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_v2; } diff --git a/drivers/clk/msm/clock-mmss-cobalt.c b/drivers/clk/msm/clock-mmss-cobalt.c index 1a8083e74f5f..873dd40d3a44 100644 --- a/drivers/clk/msm/clock-mmss-cobalt.c +++ b/drivers/clk/msm/clock-mmss-cobalt.c @@ -240,6 +240,7 @@ static struct rcg_clk ahb_clk_src = { .set_rate = set_rate_hid, .freq_tbl = ftbl_ahb_clk_src, .current_freq = &rcg_dummy_freq, + .non_local_control_timeout = 1000, .base = &virt_base, .c = { .dbg_name = "ahb_clk_src", @@ -481,10 +482,9 @@ static struct clk_freq_tbl ftbl_video_core_clk_src[] = { }; static struct clk_freq_tbl ftbl_video_core_clk_src_vq[] = { - F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 269330000, mmpll0_pll_out, 3, 0, 0), - F_MM( 404000000, mmpll0_pll_out, 2, 0, 0), + F_MM( 355200000, mmpll6_pll_out, 2.5, 0, 0), F_MM( 444000000, mmpll6_pll_out, 2, 0, 0), F_MM( 533000000, mmpll3_pll_out, 2, 0, 0), F_END @@ -735,10 +735,9 @@ static struct clk_freq_tbl ftbl_video_subcore_clk_src[] = { }; static struct clk_freq_tbl ftbl_video_subcore_clk_src_vq[] = { - F_MM( 100000000, mmsscc_gpll0, 6, 0, 0), F_MM( 200000000, mmsscc_gpll0, 3, 0, 0), F_MM( 269330000, mmpll0_pll_out, 3, 0, 0), - F_MM( 404000000, mmpll0_pll_out, 2, 0, 0), + F_MM( 355200000, mmpll6_pll_out, 2.5, 0, 0), F_MM( 444000000, mmpll6_pll_out, 2, 0, 0), F_MM( 533000000, mmpll3_pll_out, 2, 0, 0), F_END @@ -2733,17 +2732,10 @@ static void msm_mmsscc_hamster_fixup(void) static void msm_mmsscc_v2_fixup(void) { - cpp_clk_src.c.fmax[VDD_DIG_LOW] = 200000000; - cpp_clk_src.c.fmax[VDD_DIG_LOW_L1] = 480000000; - csi0_clk_src.c.fmax[VDD_DIG_LOW] = 256000000; - csi0_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000; - csi1_clk_src.c.fmax[VDD_DIG_LOW] = 256000000; - csi1_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000; - csi2_clk_src.c.fmax[VDD_DIG_LOW] = 256000000; - csi2_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000; - csi3_clk_src.c.fmax[VDD_DIG_LOW] = 256000000; - csi3_clk_src.c.fmax[VDD_DIG_LOW_L1] = 300000000; - csiphy_clk_src.c.fmax[VDD_DIG_LOW] = 256000000; + csi0_clk_src.c.fmax[VDD_DIG_NOMINAL] = 480000000; + csi1_clk_src.c.fmax[VDD_DIG_NOMINAL] = 480000000; + csi2_clk_src.c.fmax[VDD_DIG_NOMINAL] = 480000000; + csi3_clk_src.c.fmax[VDD_DIG_NOMINAL] = 480000000; dp_pixel_clk_src.c.fmax[VDD_DIG_LOWER] = 148380000; } diff --git a/drivers/clk/msm/clock-osm.c b/drivers/clk/msm/clock-osm.c index 8ae6a4e994f0..68274765a6c1 100644 --- a/drivers/clk/msm/clock-osm.c +++ b/drivers/clk/msm/clock-osm.c @@ -57,6 +57,7 @@ enum clk_osm_lut_data { FREQ_DATA, PLL_OVERRIDES, SPARE_DATA, + VIRTUAL_CORNER, NUM_FIELDS, }; @@ -406,12 +407,24 @@ static long clk_osm_list_rate(struct clk *c, unsigned n) static long clk_osm_round_rate(struct clk *c, unsigned long rate) { int i; + unsigned long rrate = 0; - for (i = 0; i < c->num_fmax; i++) - if (rate <= c->fmax[i]) - return c->fmax[i]; + /* + * If the rate passed in is 0, return the first frequency in + * the FMAX table. + */ + if (!rate) + return c->fmax[0]; + + for (i = 0; i < c->num_fmax; i++) { + if (is_better_rate(rate, rrate, c->fmax[i])) { + rrate = c->fmax[i]; + if (rrate == rate) + break; + } + } - return c->fmax[i-1]; + return rrate; } static int clk_osm_search_table(struct osm_entry *table, int entries, long rate) @@ -581,19 +594,21 @@ static void clk_osm_print_osm_table(struct clk_osm *c) { int i; struct osm_entry *table = c->osm_table; - u32 pll_src, pll_div, lval; + u32 pll_src, pll_div, lval, core_count; - pr_debug("Index, Frequency, VC, OLV (mv), PLL Src, PLL Div, L-Val, ACC Level\n"); + pr_debug("Index, Frequency, VC, OLV (mv), Core Count, PLL Src, PLL Div, L-Val, ACC Level\n"); for (i = 0; i < c->num_entries; i++) { pll_src = (table[i].freq_data & GENMASK(27, 26)) >> 26; pll_div = (table[i].freq_data & GENMASK(25, 24)) >> 24; lval = table[i].freq_data & GENMASK(7, 0); + core_count = (table[i].freq_data & GENMASK(18, 16)) >> 16; - pr_debug("%3d, %11lu, %2u, %5u, %6u, %8u, %7u, %5u\n", + pr_debug("%3d, %11lu, %2u, %5u, %2u, %6u, %8u, %7u, %5u\n", i, table[i].frequency, table[i].virtual_corner, table[i].open_loop_volt, + core_count, pll_src, pll_div, lval, @@ -655,14 +670,17 @@ static int clk_osm_get_lut(struct platform_device *pdev, c->osm_table[j].freq_data = array[i + FREQ_DATA]; c->osm_table[j].override_data = array[i + PLL_OVERRIDES]; c->osm_table[j].spare_data = array[i + SPARE_DATA]; - pr_debug("index=%d freq=%ld freq_data=0x%x override_data=0x%x spare_data=0x%x\n", + /* Voltage corners are 0 based in the OSM LUT */ + c->osm_table[j].virtual_corner = array[i + VIRTUAL_CORNER] - 1; + pr_debug("index=%d freq=%ld virtual_corner=%d freq_data=0x%x override_data=0x%x spare_data=0x%x\n", j, c->osm_table[j].frequency, + c->osm_table[j].virtual_corner, c->osm_table[j].freq_data, c->osm_table[j].override_data, c->osm_table[j].spare_data); data = (array[i + FREQ_DATA] & GENMASK(18, 16)) >> 16; - if (!last_entry && data == MAX_CONFIG) { + if (!last_entry) { clk->fmax[k] = array[i]; k++; } @@ -1143,77 +1161,25 @@ static int clk_osm_setup_hw_table(struct clk_osm *c) static int clk_osm_resolve_open_loop_voltages(struct clk_osm *c) { struct regulator *regulator = c->vdd_reg; - struct dev_pm_opp *opp; - unsigned long freq; - u32 vc, mv, data; - int i, rc = 0; + u32 vc, mv; + int i; - /* - * Determine frequency -> virtual corner -> open-loop voltage - * mapping from the OPP table. - */ for (i = 0; i < OSM_TABLE_SIZE; i++) { - freq = c->osm_table[i].frequency; - /* - * Only frequencies that are supported across all configurations - * are present in the OPP table associated with the regulator - * device. - */ - data = (c->osm_table[i].freq_data & GENMASK(18, 16)) >> 16; - if (data != MAX_CONFIG) { - if (i < 1) { - pr_err("Invalid LUT entry at index 0\n"); - return -EINVAL; - } - c->osm_table[i].open_loop_volt = - c->osm_table[i-1].open_loop_volt; - c->osm_table[i].virtual_corner = - c->osm_table[i-1].virtual_corner; - continue; - } - - rcu_read_lock(); - opp = dev_pm_opp_find_freq_exact(&c->vdd_dev->dev, freq, true); - if (IS_ERR(opp)) { - rc = PTR_ERR(opp); - if (rc == -ERANGE) - pr_err("Frequency %lu not found\n", freq); - goto exit; - } - - vc = dev_pm_opp_get_voltage(opp); - if (!vc) { - pr_err("No virtual corner found for frequency %lu\n", - freq); - rc = -ERANGE; - goto exit; - } - - rcu_read_unlock(); - + vc = c->osm_table[i].virtual_corner + 1; /* Voltage is in uv. Convert to mv */ mv = regulator_list_corner_voltage(regulator, vc) / 1000; - - /* CPR virtual corners are zero-based numbered */ - vc--; c->osm_table[i].open_loop_volt = mv; - c->osm_table[i].virtual_corner = vc; } return 0; -exit: - rcu_read_unlock(); - return rc; } static int clk_osm_resolve_crossover_corners(struct clk_osm *c, struct platform_device *pdev) { struct regulator *regulator = c->vdd_reg; - struct dev_pm_opp *opp; - unsigned long freq = 0; - int vc, i, threshold, rc = 0; - u32 corner_volt, data; + int count, vc, i, threshold, rc = 0; + u32 corner_volt; rc = of_property_read_u32(pdev->dev.of_node, "qcom,apm-threshold-voltage", @@ -1224,70 +1190,26 @@ static int clk_osm_resolve_crossover_corners(struct clk_osm *c, } /* Determine crossover virtual corner */ - rcu_read_lock(); - opp = dev_pm_opp_find_freq_exact(&c->vdd_dev->dev, freq, true); - if (IS_ERR(opp)) { - rc = PTR_ERR(opp); - if (rc == -ERANGE) - pr_debug("APM placeholder frequency entry not found\n"); - goto exit; + count = regulator_count_voltages(regulator); + if (count < 0) { + pr_err("Failed to get the number of virtual corners supported\n"); + return count; } - vc = dev_pm_opp_get_voltage(opp); - if (!vc) { - pr_debug("APM crossover corner not found\n"); - rc = -ERANGE; - goto exit; - } - rcu_read_unlock(); - vc--; - c->apm_crossover_vc = vc; + + c->apm_crossover_vc = count - 1; /* Determine threshold virtual corner */ for (i = 0; i < OSM_TABLE_SIZE; i++) { - freq = c->osm_table[i].frequency; - /* - * Only frequencies that are supported across all configurations - * are present in the OPP table associated with the regulator - * device. - */ - data = (c->osm_table[i].freq_data & GENMASK(18, 16)) >> 16; - if (data != MAX_CONFIG) - continue; - - rcu_read_lock(); - opp = dev_pm_opp_find_freq_exact(&c->vdd_dev->dev, freq, true); - if (IS_ERR(opp)) { - rc = PTR_ERR(opp); - if (rc == -ERANGE) - pr_err("Frequency %lu not found\n", freq); - goto exit; - } - - vc = dev_pm_opp_get_voltage(opp); - if (!vc) { - pr_err("No virtual corner found for frequency %lu\n", - freq); - rc = -ERANGE; - goto exit; - } - - rcu_read_unlock(); - + vc = c->osm_table[i].virtual_corner + 1; corner_volt = regulator_list_corner_voltage(regulator, vc); - /* CPR virtual corners are zero-based numbered */ - vc--; - if (corner_volt >= threshold) { - c->apm_threshold_vc = vc; + c->apm_threshold_vc = c->osm_table[i].virtual_corner; break; } } return 0; -exit: - rcu_read_unlock(); - return rc; } static int clk_osm_set_cc_policy(struct platform_device *pdev) diff --git a/drivers/clk/msm/clock.h b/drivers/clk/msm/clock.h index bee769921ff7..b7aa946f1931 100644 --- a/drivers/clk/msm/clock.h +++ b/drivers/clk/msm/clock.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2014, 2016, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -38,7 +38,7 @@ int msm_clock_init(struct clock_init_data *data); int find_vdd_level(struct clk *clk, unsigned long rate); extern struct list_head orphan_clk_list; -#ifdef CONFIG_DEBUG_FS +#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_COMMON_CLK_MSM) int clock_debug_register(struct clk *clk); void clock_debug_print_enabled(void); #else diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ea6e4a1423af..5b9ce12c1e02 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -27,7 +27,7 @@ config QCOM_CLK_RPM config QCOM_CLK_SMD_RPM tristate "RPM over SMD based Clock Controller" - depends on COMMON_CLK_QCOM && QCOM_SMD_RPM + depends on COMMON_CLK_QCOM select QCOM_RPMCC help The RPM (Resource Power Manager) is a dedicated hardware engine for @@ -153,6 +153,15 @@ config MSM_MMCC_8996 Say Y if you want to support multimedia devices such as display, graphics, video encode/decode, camera, etc. +config MSM_GCC_FALCON + tristate "MSMFALCON Global Clock Controller" + depends on COMMON_CLK_QCOM + ---help--- + Support for the global clock controller on Qualcomm Technologies, Inc + MSMfalcon devices. + Say Y if you want to use peripheral devices such as UART, SPI, I2C, + USB, UFS, SD/eMMC, PCIe, etc. + config QCOM_HFPLL tristate "High-Frequency PLL (HFPLL) Clock Controller" depends on COMMON_CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index dc1b66f84af2..af58f206bc4a 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -13,7 +13,7 @@ clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o clk-qcom-y += clk-hfpll.o clk-qcom-y += reset.o clk-qcom-y += clk-dummy.o -clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o +clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o gdsc-regulator.o obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o @@ -25,6 +25,7 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o +obj-$(CONFIG_MSM_GCC_FALCON) += gcc-msmfalcon.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index b904c335cda4..e3760969848d 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2016, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -158,6 +158,8 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @freq_tbl: frequency table * @current_freq: last cached frequency when using branches with shared RCGs * @clkr: regmap clock handle + * @flags: set if RCG needs to be force enabled/disabled during + * power sequence. * */ struct clk_rcg2 { @@ -168,6 +170,9 @@ struct clk_rcg2 { const struct freq_tbl *freq_tbl; unsigned long current_freq; struct clk_regmap clkr; + +#define FORCE_ENABLE_RCGR BIT(0) + u8 flags; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index a071bba8018c..4d5081c2b6d1 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2016, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -60,6 +60,57 @@ static int clk_rcg2_is_enabled(struct clk_hw *hw) return (cmd & CMD_ROOT_OFF) == 0; } +static int clk_rcg_set_force_enable(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + const char *name = clk_hw_get_name(hw); + int ret = 0, count; + + /* force enable RCG */ + ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, + CMD_ROOT_EN, CMD_ROOT_EN); + if (ret) + return ret; + + /* wait for RCG to turn ON */ + for (count = 500; count > 0; count--) { + ret = clk_rcg2_is_enabled(hw); + if (ret) { + ret = 0; + break; + } + udelay(1); + } + if (!count) + pr_err("%s: RCG did not turn on after force enable\n", name); + + return ret; +} + +static int clk_rcg2_enable(struct clk_hw *hw) +{ + int ret = 0; + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + if (rcg->flags & FORCE_ENABLE_RCGR) + ret = clk_rcg_set_force_enable(hw); + + return ret; +} + +static void clk_rcg2_disable(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + if (rcg->flags & FORCE_ENABLE_RCGR) { + /* force disable RCG - clear CMD_ROOT_EN bit */ + regmap_update_bits(rcg->clkr.regmap, + rcg->cmd_rcgr + CMD_REG, CMD_ROOT_EN, 0); + /* Add a delay to disable the RCG */ + udelay(100); + } +} + static u8 clk_rcg2_get_parent(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); @@ -290,6 +341,8 @@ static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw, } const struct clk_ops clk_rcg2_ops = { + .enable = clk_rcg2_enable, + .disable = clk_rcg2_disable, .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, .set_parent = clk_rcg2_set_parent, @@ -801,6 +854,8 @@ static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate, } const struct clk_ops clk_gfx3d_ops = { + .enable = clk_rcg2_enable, + .disable = clk_rcg2_disable, .is_enabled = clk_rcg2_is_enabled, .get_parent = clk_rcg2_get_parent, .set_parent = clk_rcg2_set_parent, diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 06eb06009268..8ed5115efc3b 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Linaro Limited - * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -23,6 +23,8 @@ #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/soc/qcom/smd-rpm.h> +#include <soc/qcom/rpm-smd.h> +#include <linux/clk.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/mfd/qcom-rpm.h> @@ -37,6 +39,8 @@ #define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \ key) \ static struct clk_smd_rpm _platform##_##_active; \ + static unsigned long _name##_##last_active_set_vote; \ + static unsigned long _name##_##last_sleep_set_vote; \ static struct clk_smd_rpm _platform##_##_name = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ @@ -44,6 +48,8 @@ .rpm_key = (key), \ .peer = &_platform##_##_active, \ .rate = INT_MAX, \ + .last_active_set_vote = &_name##_##last_active_set_vote, \ + .last_sleep_set_vote = &_name##_##last_sleep_set_vote, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ .name = #_name, \ @@ -59,6 +65,8 @@ .rpm_key = (key), \ .peer = &_platform##_##_name, \ .rate = INT_MAX, \ + .last_active_set_vote = &_name##_##last_active_set_vote, \ + .last_sleep_set_vote = &_name##_##last_sleep_set_vote, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ .name = #_active, \ @@ -70,6 +78,8 @@ #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \ stat_id, r, key) \ static struct clk_smd_rpm _platform##_##_active; \ + static unsigned long _name##_##last_active_set_vote; \ + static unsigned long _name##_##last_sleep_set_vote; \ static struct clk_smd_rpm _platform##_##_name = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ @@ -78,6 +88,8 @@ .branch = true, \ .peer = &_platform##_##_active, \ .rate = (r), \ + .last_active_set_vote = &_name##_##last_active_set_vote, \ + .last_sleep_set_vote = &_name##_##last_sleep_set_vote, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ .name = #_name, \ @@ -94,6 +106,8 @@ .branch = true, \ .peer = &_platform##_##_name, \ .rate = (r), \ + .last_active_set_vote = &_name##_##last_active_set_vote, \ + .last_sleep_set_vote = &_name##_##last_sleep_set_vote, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ .name = #_active, \ @@ -137,7 +151,8 @@ struct clk_smd_rpm { struct clk_smd_rpm *peer; struct clk_hw hw; unsigned long rate; - struct qcom_smd_rpm *rpm; + unsigned long *last_active_set_vote; + unsigned long *last_sleep_set_vote; }; struct clk_smd_rpm_req { @@ -153,61 +168,81 @@ struct rpm_cc { }; struct rpm_smd_clk_desc { - struct clk_smd_rpm **clks; + struct clk_hw **clks; + size_t num_rpm_clks; size_t num_clks; }; static DEFINE_MUTEX(rpm_smd_clk_lock); -static int clk_smd_rpm_handoff(struct clk_smd_rpm *r) +static int clk_smd_rpm_handoff(struct clk_hw *hw) { - int ret; - struct clk_smd_rpm_req req = { + int ret = 0; + uint32_t value = cpu_to_le32(INT_MAX); + struct clk_smd_rpm *r = to_clk_smd_rpm(hw); + struct msm_rpm_kvp req = { .key = cpu_to_le32(r->rpm_key), - .nbytes = cpu_to_le32(sizeof(u32)), - .value = cpu_to_le32(INT_MAX), + .data = (void *)&value, + .length = sizeof(value), }; - ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE, - r->rpm_res_type, r->rpm_clk_id, &req, - sizeof(req)); + ret = msm_rpm_send_message(QCOM_SMD_RPM_ACTIVE_STATE, r->rpm_res_type, + r->rpm_clk_id, &req, 1); if (ret) return ret; - ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE, - r->rpm_res_type, r->rpm_clk_id, &req, - sizeof(req)); + + ret = msm_rpm_send_message(QCOM_SMD_RPM_SLEEP_STATE, r->rpm_res_type, + r->rpm_clk_id, &req, 1); if (ret) return ret; - return 0; + return ret; } static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r, - unsigned long rate) + uint32_t rate) { - struct clk_smd_rpm_req req = { + int ret = 0; + struct msm_rpm_kvp req = { .key = cpu_to_le32(r->rpm_key), - .nbytes = cpu_to_le32(sizeof(u32)), - .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ + .data = (void *)&rate, + .length = sizeof(rate), }; - return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE, - r->rpm_res_type, r->rpm_clk_id, &req, - sizeof(req)); + if (*r->last_active_set_vote == rate) + return ret; + + ret = msm_rpm_send_message(QCOM_SMD_RPM_ACTIVE_STATE, r->rpm_res_type, + r->rpm_clk_id, &req, 1); + if (ret) + return ret; + + *r->last_active_set_vote = rate; + + return ret; } static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r, - unsigned long rate) + uint32_t rate) { - struct clk_smd_rpm_req req = { + int ret = 0; + struct msm_rpm_kvp req = { .key = cpu_to_le32(r->rpm_key), - .nbytes = cpu_to_le32(sizeof(u32)), - .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ + .data = (void *)&rate, + .length = sizeof(rate), }; - return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE, - r->rpm_res_type, r->rpm_clk_id, &req, - sizeof(req)); + if (*r->last_sleep_set_vote == rate) + return ret; + + ret = msm_rpm_send_message(QCOM_SMD_RPM_SLEEP_STATE, r->rpm_res_type, + r->rpm_clk_id, &req, 1); + if (ret) + return ret; + + *r->last_sleep_set_vote = rate; + + return ret; } static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate, @@ -231,7 +266,7 @@ static int clk_smd_rpm_prepare(struct clk_hw *hw) struct clk_smd_rpm *peer = r->peer; unsigned long this_rate = 0, this_sleep_rate = 0; unsigned long peer_rate = 0, peer_sleep_rate = 0; - unsigned long active_rate, sleep_rate; + uint32_t active_rate, sleep_rate; int ret = 0; mutex_lock(&rpm_smd_clk_lock); @@ -279,7 +314,7 @@ static void clk_smd_rpm_unprepare(struct clk_hw *hw) struct clk_smd_rpm *r = to_clk_smd_rpm(hw); struct clk_smd_rpm *peer = r->peer; unsigned long peer_rate = 0, peer_sleep_rate = 0; - unsigned long active_rate, sleep_rate; + uint32_t active_rate, sleep_rate; int ret; mutex_lock(&rpm_smd_clk_lock); @@ -313,7 +348,7 @@ static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_smd_rpm *r = to_clk_smd_rpm(hw); struct clk_smd_rpm *peer = r->peer; - unsigned long active_rate, sleep_rate; + uint32_t active_rate, sleep_rate; unsigned long this_rate = 0, this_sleep_rate = 0; unsigned long peer_rate = 0, peer_sleep_rate = 0; int ret = 0; @@ -372,33 +407,55 @@ static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw, return r->rate; } -static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm) +static int clk_smd_rpm_enable_scaling(void) { - int ret; - struct clk_smd_rpm_req req = { + int ret = 0; + uint32_t value = cpu_to_le32(1); + struct msm_rpm_kvp req = { .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE), - .nbytes = cpu_to_le32(sizeof(u32)), - .value = cpu_to_le32(1), + .data = (void *)&value, + .length = sizeof(value), }; - ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE, - QCOM_SMD_RPM_MISC_CLK, - QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); + ret = msm_rpm_send_message_noirq(QCOM_SMD_RPM_SLEEP_STATE, + QCOM_SMD_RPM_MISC_CLK, + QCOM_RPM_SCALING_ENABLE_ID, &req, 1); if (ret) { pr_err("RPM clock scaling (sleep set) not enabled!\n"); return ret; } - ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE, - QCOM_SMD_RPM_MISC_CLK, - QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req)); + ret = msm_rpm_send_message_noirq(QCOM_SMD_RPM_ACTIVE_STATE, + QCOM_SMD_RPM_MISC_CLK, + QCOM_RPM_SCALING_ENABLE_ID, &req, 1); if (ret) { pr_err("RPM clock scaling (active set) not enabled!\n"); return ret; } pr_debug("%s: RPM clock scaling is enabled\n", __func__); - return 0; + return ret; +} + +static int clk_vote_bimc(struct clk_hw *hw, uint32_t rate) +{ + int ret = 0; + struct clk_smd_rpm *r = to_clk_smd_rpm(hw); + struct msm_rpm_kvp req = { + .key = r->rpm_key, + .data = (void *)&rate, + .length = sizeof(rate), + }; + + ret = msm_rpm_send_message_noirq(QCOM_SMD_RPM_ACTIVE_STATE, + r->rpm_res_type, r->rpm_clk_id, &req, 1); + if (ret < 0) { + if (ret != -EPROBE_DEFER) + WARN(1, "BIMC vote not sent!\n"); + return ret; + } + + return ret; } static const struct clk_ops clk_smd_rpm_ops = { @@ -430,40 +487,41 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5); -static struct clk_smd_rpm *msm8916_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, - [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, +static struct clk_hw *msm8916_clks[] = { + [RPM_PCNOC_CLK] = &msm8916_pcnoc_clk.hw, + [RPM_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk.hw, + [RPM_SNOC_CLK] = &msm8916_snoc_clk.hw, + [RPM_SNOC_A_CLK] = &msm8916_snoc_a_clk.hw, + [RPM_BIMC_CLK] = &msm8916_bimc_clk.hw, + [RPM_BIMC_A_CLK] = &msm8916_bimc_a_clk.hw, + [RPM_QDSS_CLK] = &msm8916_qdss_clk.hw, + [RPM_QDSS_A_CLK] = &msm8916_qdss_a_clk.hw, + [RPM_BB_CLK1] = &msm8916_bb_clk1.hw, + [RPM_BB_CLK1_A] = &msm8916_bb_clk1_a.hw, + [RPM_BB_CLK2] = &msm8916_bb_clk2.hw, + [RPM_BB_CLK2_A] = &msm8916_bb_clk2_a.hw, + [RPM_RF_CLK1] = &msm8916_rf_clk1.hw, + [RPM_RF_CLK1_A] = &msm8916_rf_clk1_a.hw, + [RPM_RF_CLK2] = &msm8916_rf_clk2.hw, + [RPM_RF_CLK2_A] = &msm8916_rf_clk2_a.hw, + [RPM_BB_CLK1_PIN] = &msm8916_bb_clk1_pin.hw, + [RPM_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin.hw, + [RPM_BB_CLK2_PIN] = &msm8916_bb_clk2_pin.hw, + [RPM_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin.hw, + [RPM_RF_CLK1_PIN] = &msm8916_rf_clk1_pin.hw, + [RPM_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin.hw, + [RPM_RF_CLK2_PIN] = &msm8916_rf_clk2_pin.hw, + [RPM_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin.hw, }; static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { .clks = msm8916_clks, + .num_rpm_clks = RPM_RF_CLK2_A_PIN, .num_clks = ARRAY_SIZE(msm8916_clks), }; /* msm8996 */ -DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8996, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); DEFINE_CLK_SMD_RPM(msm8996, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); DEFINE_CLK_SMD_RPM(msm8996, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); @@ -490,49 +548,50 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5); -static struct clk_smd_rpm *msm8996_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &msm8996_cxo, - [RPM_SMD_XO_A_CLK_SRC] = &msm8996_cxo_a, - [RPM_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk, - [RPM_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk, - [RPM_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk, - [RPM_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk, - [RPM_SMD_PCNOC_CLK] = &msm8996_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8996_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8996_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8996_snoc_a_clk, - [RPM_CNOC_CLK] = &msm8996_cnoc_clk, - [RPM_CNOC_A_CLK] = &msm8996_cnoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8996_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8996_bimc_a_clk, - [RPM_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, - [RPM_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk, - [RPM_IPA_CLK] = &msm8996_ipa_clk, - [RPM_IPA_A_CLK] = &msm8996_ipa_a_clk, - [RPM_CE1_CLK] = &msm8996_ce1_clk, - [RPM_CE1_A_CLK] = &msm8996_ce1_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8996_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8996_qdss_a_clk, - [RPM_LN_BB_CLK] = &msm8996_ln_bb_clk, - [RPM_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk, - [RPM_DIV_CLK1] = &msm8996_div_clk1, - [RPM_DIV_CLK1_AO] = &msm8996_div_clk1_ao, - [RPM_DIV_CLK2] = &msm8996_div_clk2, - [RPM_DIV_CLK2_AO] = &msm8996_div_clk2_ao, - [RPM_DIV_CLK3] = &msm8996_div_clk3, - [RPM_DIV_CLK3_AO] = &msm8996_div_clk3_ao, - [RPM_BB_CLK1_PIN] = &msm8996_bb_clk1_pin, - [RPM_BB_CLK1_A_PIN] = &msm8996_bb_clk1_a_pin, - [RPM_BB_CLK2_PIN] = &msm8996_bb_clk2_pin, - [RPM_BB_CLK2_A_PIN] = &msm8996_bb_clk2_a_pin, - [RPM_RF_CLK1_PIN] = &msm8996_rf_clk1_pin, - [RPM_RF_CLK1_A_PIN] = &msm8996_rf_clk1_a_pin, - [RPM_RF_CLK2_PIN] = &msm8996_rf_clk2_pin, - [RPM_RF_CLK2_A_PIN] = &msm8996_rf_clk2_a_pin, +static struct clk_hw *msm8996_clks[] = { + [RPM_XO_CLK_SRC] = &msm8996_cxo.hw, + [RPM_XO_A_CLK_SRC] = &msm8996_cxo_a.hw, + [RPM_PCNOC_CLK] = &msm8996_pnoc_clk.hw, + [RPM_PCNOC_A_CLK] = &msm8996_pnoc_a_clk.hw, + [RPM_SNOC_CLK] = &msm8996_snoc_clk.hw, + [RPM_SNOC_A_CLK] = &msm8996_snoc_a_clk.hw, + [RPM_BIMC_CLK] = &msm8996_bimc_clk.hw, + [RPM_BIMC_A_CLK] = &msm8996_bimc_a_clk.hw, + [RPM_QDSS_CLK] = &msm8996_qdss_clk.hw, + [RPM_QDSS_A_CLK] = &msm8996_qdss_a_clk.hw, + [RPM_BB_CLK1_PIN] = &msm8996_bb_clk1_pin.hw, + [RPM_BB_CLK1_A_PIN] = &msm8996_bb_clk1_a_pin.hw, + [RPM_BB_CLK2_PIN] = &msm8996_bb_clk2_pin.hw, + [RPM_BB_CLK2_A_PIN] = &msm8996_bb_clk2_a_pin.hw, + [RPM_RF_CLK1_PIN] = &msm8996_rf_clk1_pin.hw, + [RPM_RF_CLK1_A_PIN] = &msm8996_rf_clk1_a_pin.hw, + [RPM_RF_CLK2_PIN] = &msm8996_rf_clk2_pin.hw, + [RPM_RF_CLK2_A_PIN] = &msm8996_rf_clk2_a_pin.hw, + [RPM_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk.hw, + [RPM_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk.hw, + [RPM_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk.hw, + [RPM_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk.hw, + [RPM_CNOC_CLK] = &msm8996_cnoc_clk.hw, + [RPM_CNOC_A_CLK] = &msm8996_cnoc_a_clk.hw, + [RPM_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk.hw, + [RPM_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk.hw, + [RPM_IPA_CLK] = &msm8996_ipa_clk.hw, + [RPM_IPA_A_CLK] = &msm8996_ipa_a_clk.hw, + [RPM_CE1_CLK] = &msm8996_ce1_clk.hw, + [RPM_CE1_A_CLK] = &msm8996_ce1_a_clk.hw, + [RPM_DIV_CLK1] = &msm8996_div_clk1.hw, + [RPM_DIV_CLK1_AO] = &msm8996_div_clk1_ao.hw, + [RPM_DIV_CLK2] = &msm8996_div_clk2.hw, + [RPM_DIV_CLK2_AO] = &msm8996_div_clk2_ao.hw, + [RPM_DIV_CLK3] = &msm8996_div_clk3.hw, + [RPM_DIV_CLK3_AO] = &msm8996_div_clk3_ao.hw, + [RPM_LN_BB_CLK] = &msm8996_ln_bb_clk.hw, + [RPM_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk.hw, }; static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { .clks = msm8996_clks, + .num_rpm_clks = RPM_LN_BB_A_CLK, .num_clks = ARRAY_SIZE(msm8996_clks), }; @@ -549,23 +608,24 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) struct clk *clk; struct rpm_cc *rcc; struct clk_onecell_data *data; - int ret; + int ret, is_8996 = 0; size_t num_clks, i; - struct qcom_smd_rpm *rpm; - struct clk_smd_rpm **rpm_smd_clks; + struct clk_hw **hw_clks; const struct rpm_smd_clk_desc *desc; - rpm = dev_get_drvdata(pdev->dev.parent); - if (!rpm) { - dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n"); - return -ENODEV; + is_8996 = of_device_is_compatible(pdev->dev.of_node, + "qcom,rpmcc-msm8996"); + if (is_8996) { + ret = clk_vote_bimc(&msm8996_bimc_clk.hw, INT_MAX); + if (ret < 0) + return ret; } desc = of_device_get_match_data(&pdev->dev); if (!desc) return -EINVAL; - rpm_smd_clks = desc->clks; + hw_clks = desc->clks; num_clks = desc->num_clks; rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*clks) * num_clks, @@ -578,30 +638,28 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) data->clks = clks; data->clk_num = num_clks; - for (i = 0; i < num_clks; i++) { - if (!rpm_smd_clks[i]) { + for (i = 0; i <= desc->num_rpm_clks; i++) { + if (!hw_clks[i]) { clks[i] = ERR_PTR(-ENOENT); continue; } - rpm_smd_clks[i]->rpm = rpm; - - ret = clk_smd_rpm_handoff(rpm_smd_clks[i]); + ret = clk_smd_rpm_handoff(hw_clks[i]); if (ret) goto err; } - ret = clk_smd_rpm_enable_scaling(rpm); + ret = clk_smd_rpm_enable_scaling(); if (ret) goto err; for (i = 0; i < num_clks; i++) { - if (!rpm_smd_clks[i]) { + if (!hw_clks[i]) { clks[i] = ERR_PTR(-ENOENT); continue; } - clk = devm_clk_register(&pdev->dev, &rpm_smd_clks[i]->hw); + clk = devm_clk_register(&pdev->dev, hw_clks[i]); if (IS_ERR(clk)) { ret = PTR_ERR(clk); goto err; @@ -615,6 +673,12 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) if (ret) goto err; + /* Keep an active vote on CXO in case no other driver votes for it */ + if (is_8996) + clk_prepare_enable(msm8996_cxo_a.hw.clk); + + dev_info(&pdev->dev, "Registered RPM clocks\n"); + return 0; err: dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret); diff --git a/drivers/clk/qcom/gcc-msmfalcon.c b/drivers/clk/qcom/gcc-msmfalcon.c new file mode 100644 index 000000000000..d353cc9ade73 --- /dev/null +++ b/drivers/clk/qcom/gcc-msmfalcon.c @@ -0,0 +1,2800 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/bitops.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> +#include <dt-bindings/clock/qcom,gcc-msmfalcon.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "common.h" +#include "clk-pll.h" +#include "clk-regmap.h" +#include "clk-rcg.h" +#include "reset.h" +#include "vdd-level-falcon.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); +static DEFINE_VDD_REGULATORS(vdd_dig_ao, VDD_DIG_NUM, 1, vdd_corner, NULL); + +enum { + P_CORE_BI_PLL_TEST_SE, + P_GPLL0_OUT_MAIN, + P_GPLL1_OUT_MAIN, + P_GPLL4_OUT_MAIN, + P_PLL0_EARLY_DIV_CLK_SRC, + P_PLL1_EARLY_DIV_CLK_SRC, + P_SLEEP_CLK, + P_XO, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_0[] = { + "xo", + "gpll0_out_main", + "gpll0_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_1[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_1[] = { + "xo", + "gpll0_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_2[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_2[] = { + "xo", + "gpll0_out_main", + "core_pi_sleep_clk", + "gpll0_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_3[] = { + { P_XO, 0 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_3[] = { + "xo", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_4[] = { + { P_XO, 0 }, + { P_SLEEP_CLK, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_4[] = { + "xo", + "core_pi_sleep_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_5[] = { + { P_XO, 0 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_5[] = { + "xo", + "gpll4_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_6[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 3 }, + { P_GPLL1_OUT_MAIN, 4 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_PLL1_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_6[] = { + "xo", + "gpll0_out_main", + "gpll0_out_early_div", + "gpll1_out_main", + "gpll4_out_main", + "gpll1_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_7[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_7[] = { + "xo", + "gpll0_out_main", + "gpll4_out_main", + "gpll0_out_early_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map gcc_parent_map_8[] = { + { P_XO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_PLL0_EARLY_DIV_CLK_SRC, 2 }, + { P_GPLL4_OUT_MAIN, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const gcc_parent_names_8[] = { + "xo", + "gpll0_out_main", + "gpll0_out_early_div", + "gpll4_out_main", + "core_bi_pll_test_se", +}; + +static struct clk_fixed_factor xo = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "xo", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll0_out_main = { + .offset = 0x0, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll0_out_early_div = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_early_div", + .parent_names = (const char *[]){ "gpll0_out_main" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll1_out_main = { + .offset = 0x1000, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll1_out_early_div = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll1_out_early_div", + .parent_names = (const char *[]){ "gpll1_out_main" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll4_out_main = { + .offset = 0x77000, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { + .cmd_rcgr = 0x19020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { + F(960000, P_XO, 10, 1, 2), + F(4800000, P_XO, 4, 0, 0), + F(9600000, P_XO, 2, 0, 0), + F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4), + F(19200000, P_XO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), + F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { + .cmd_rcgr = 0x1900c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { + .cmd_rcgr = 0x1b020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { + .cmd_rcgr = 0x1b00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { + .cmd_rcgr = 0x1d020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { + .cmd_rcgr = 0x1d00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { + .cmd_rcgr = 0x1f020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { + .cmd_rcgr = 0x1f00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { + F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625), + F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625), + F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625), + F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15), + F(19200000, P_XO, 1, 0, 0), + F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), + F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), + F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), + F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), + F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), + F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), + F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_uart1_apps_clk_src = { + .cmd_rcgr = 0x1a00c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart1_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static struct clk_rcg2 blsp1_uart2_apps_clk_src = { + .cmd_rcgr = 0x1c00c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart2_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { + .cmd_rcgr = 0x26020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { + .cmd_rcgr = 0x2600c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup1_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { + .cmd_rcgr = 0x28020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { + .cmd_rcgr = 0x2800c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup2_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { + .cmd_rcgr = 0x2a020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { + .cmd_rcgr = 0x2a00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup3_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { + .cmd_rcgr = 0x2c020, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_i2c_apps_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { + .cmd_rcgr = 0x2c00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_qup4_spi_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 25000000, + NOMINAL, 50000000), + }, +}; + +static struct clk_rcg2 blsp2_uart1_apps_clk_src = { + .cmd_rcgr = 0x2700c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart1_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static struct clk_rcg2 blsp2_uart2_apps_clk_src = { + .cmd_rcgr = 0x2900c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp2_uart2_apps_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 31578947, + NOMINAL, 63157895), + }, +}; + +static const struct freq_tbl ftbl_gp1_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gp1_clk_src = { + .cmd_rcgr = 0x64004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp1_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static struct clk_rcg2 gp2_clk_src = { + .cmd_rcgr = 0x65004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp2_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static struct clk_rcg2 gp3_clk_src = { + .cmd_rcgr = 0x66004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp3_clk_src", + .parent_names = gcc_parent_names_2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_ahb_clk_src = { + .cmd_rcgr = 0x48014, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_hmss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_ahb_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3_AO( + LOWER, 19200000, + LOW, 50000000, + NOMINAL, 100000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { + F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_gpll0_clk_src = { + .cmd_rcgr = 0x4805c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_hmss_gpll0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll0_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1_AO( + LOWER, 600000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = { + F(384000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + F(768000000, P_GPLL4_OUT_MAIN, 2, 0, 0), + F(1536000000, P_GPLL4_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_gpll4_clk_src = { + .cmd_rcgr = 0x48074, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_hmss_gpll4_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_gpll4_clk_src", + .parent_names = gcc_parent_names_5, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3_AO( + LOWER, 400000000, + LOW, 800000000, + NOMINAL, 1600000000), + }, +}; + +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 hmss_rbcpr_clk_src = { + .cmd_rcgr = 0x48044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_hmss_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hmss_rbcpr_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + NOMINAL, 50000000), + }, +}; + +static const struct freq_tbl ftbl_pdm2_clk_src[] = { + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 pdm2_clk_src = { + .cmd_rcgr = 0x33010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_pdm2_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pdm2_clk_src", + .parent_names = gcc_parent_names_1, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 60000000), + }, +}; + +static const struct freq_tbl ftbl_qspi_ser_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(80200000, P_PLL1_EARLY_DIV_CLK_SRC, 5, 0, 0), + F(160400000, P_GPLL1_OUT_MAIN, 5, 0, 0), + F(320800000, P_GPLL1_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 qspi_ser_clk_src = { + .cmd_rcgr = 0x4d00c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_6, + .freq_tbl = ftbl_qspi_ser_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "qspi_ser_clk_src", + .parent_names = gcc_parent_names_6, + .num_parents = 7, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 80200000, + LOW, 160400000, + NOMINAL, 320800000), + }, +}; + +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_PLL0_EARLY_DIV_CLK_SRC, 5, 1, 3), + F(25000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 1, 2), + F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(192000000, P_GPLL4_OUT_MAIN, 8, 0, 0), + F(384000000, P_GPLL4_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_apps_clk_src = { + .cmd_rcgr = 0x1602c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_7, + .freq_tbl = ftbl_sdcc1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_apps_clk_src", + .parent_names = gcc_parent_names_7, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 400000000), + }, +}; + +static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = { + F(75000000, P_PLL0_EARLY_DIV_CLK_SRC, 4, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc1_ice_core_clk_src = { + .cmd_rcgr = 0x16010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_sdcc1_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_ice_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 75000000, + LOW, 150000000, + NOMINAL, 300000000), + }, +}; + +static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { + F(144000, P_XO, 16, 3, 25), + F(400000, P_XO, 12, 1, 4), + F(20000000, P_PLL0_EARLY_DIV_CLK_SRC, 5, 1, 3), + F(25000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 1, 2), + F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(192000000, P_GPLL4_OUT_MAIN, 8, 0, 0), + { } +}; + +static struct clk_rcg2 sdcc2_apps_clk_src = { + .cmd_rcgr = 0x14010, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_8, + .freq_tbl = ftbl_sdcc2_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc2_apps_clk_src", + .parent_names = gcc_parent_names_8, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { + F(50000000, P_PLL0_EARLY_DIV_CLK_SRC, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 ufs_axi_clk_src = { + .cmd_rcgr = 0x75018, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_ufs_axi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_axi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 50000000, + LOW, 100000000, + LOW_L1, 150000000, + NOMINAL, 200000000, + HIGH, 240000000), + }, +}; + +static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = { + F(75000000, P_PLL0_EARLY_DIV_CLK_SRC, 4, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 ufs_ice_core_clk_src = { + .cmd_rcgr = 0x76010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_ufs_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_ice_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 75000000, + LOW, 150000000, + NOMINAL, 300000000), + }, +}; + +static struct clk_rcg2 ufs_phy_aux_clk_src = { + .cmd_rcgr = 0x76044, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_hmss_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_phy_aux_clk_src", + .parent_names = gcc_parent_names_3, + .num_parents = 2, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { + F(37500000, P_PLL0_EARLY_DIV_CLK_SRC, 8, 0, 0), + F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 ufs_unipro_core_clk_src = { + .cmd_rcgr = 0x76028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_ufs_unipro_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ufs_unipro_core_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 37500000, + LOW, 75000000, + NOMINAL, 150000000), + }, +}; + +static const struct freq_tbl ftbl_usb20_master_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + { } +}; + +static struct clk_rcg2 usb20_master_clk_src = { + .cmd_rcgr = 0x2f010, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_usb20_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_master_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 60000000, + NOMINAL, 120000000), + }, +}; + +static struct clk_rcg2 usb20_mock_utmi_clk_src = { + .cmd_rcgr = 0x2f024, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_hmss_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb20_mock_utmi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 19200000, + LOW, 60000000), + }, +}; + +static const struct freq_tbl ftbl_usb30_master_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(66666667, P_PLL0_EARLY_DIV_CLK_SRC, 4.5, 0, 0), + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 usb30_master_clk_src = { + .cmd_rcgr = 0xf014, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_usb30_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_master_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4( + LOWER, 66666667, + LOW, 133333333, + NOMINAL, 200000000, + HIGH, 240000000), + }, +}; + +static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { + F(40000000, P_PLL0_EARLY_DIV_CLK_SRC, 7.5, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 usb30_mock_utmi_clk_src = { + .cmd_rcgr = 0xf028, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_usb30_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb30_mock_utmi_clk_src", + .parent_names = gcc_parent_names_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 40000000, + LOW, 60000000), + }, +}; + +static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { + F(1200000, P_XO, 16, 0, 0), + F(19200000, P_XO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 usb3_phy_aux_clk_src = { + .cmd_rcgr = 0x5000c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_usb3_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb3_phy_aux_clk_src", + .parent_names = gcc_parent_names_4, + .num_parents = 3, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static struct clk_branch gcc_aggre2_ufs_axi_clk = { + .halt_reg = 0x75034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x75034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre2_ufs_axi_clk", + .parent_names = (const char *[]){ + "ufs_axi_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre2_usb3_axi_clk = { + .halt_reg = 0xf03c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf03c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre2_usb3_axi_clk", + .parent_names = (const char *[]){ + "usb30_master_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_gfx_clk = { + .halt_reg = 0x7106c, + .halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, + .clkr = { + .enable_reg = 0x7106c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_hmss_axi_clk = { + .halt_reg = 0x48004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(22), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_hmss_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_bimc_mss_q6_axi_clk = { + .halt_reg = 0x4401c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4401c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_bimc_mss_q6_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_ahb_clk = { + .halt_reg = 0x17004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(17), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { + .halt_reg = 0x19008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x19008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup1_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { + .halt_reg = 0x19004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x19004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup1_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { + .halt_reg = 0x1b008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1b008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup2_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { + .halt_reg = 0x1b004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1b004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup2_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { + .halt_reg = 0x1d008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1d008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup3_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { + .halt_reg = 0x1d004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1d004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup3_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { + .halt_reg = 0x1f008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1f008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup4_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { + .halt_reg = 0x1f004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1f004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp1_qup4_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart1_apps_clk = { + .halt_reg = 0x1a004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart1_apps_clk", + .parent_names = (const char *[]){ + "blsp1_uart1_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart2_apps_clk = { + .halt_reg = 0x1c004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1c004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart2_apps_clk", + .parent_names = (const char *[]){ + "blsp1_uart2_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_ahb_clk = { + .halt_reg = 0x25004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = { + .halt_reg = 0x26008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x26008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup1_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup1_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = { + .halt_reg = 0x26004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x26004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup1_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup1_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = { + .halt_reg = 0x28008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x28008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup2_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup2_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = { + .halt_reg = 0x28004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x28004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup2_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup2_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = { + .halt_reg = 0x2a008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2a008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup3_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup3_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = { + .halt_reg = 0x2a004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup3_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup3_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = { + .halt_reg = 0x2c008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_i2c_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup4_i2c_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = { + .halt_reg = 0x2c004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_qup4_spi_apps_clk", + .parent_names = (const char *[]){ + "blsp2_qup4_spi_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_uart1_apps_clk = { + .halt_reg = 0x27004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x27004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart1_apps_clk", + .parent_names = (const char *[]){ + "blsp2_uart1_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp2_uart2_apps_clk = { + .halt_reg = 0x29004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x29004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp2_uart2_apps_clk", + .parent_names = (const char *[]){ + "blsp2_uart2_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x38004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb2_axi_clk = { + .halt_reg = 0x5058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb2_axi_clk", + .parent_names = (const char *[]){ + "usb20_master_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_axi_clk = { + .halt_reg = 0x5018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb3_axi_clk", + .parent_names = (const char *[]){ + "usb30_master_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_dcc_ahb_clk = { + .halt_reg = 0x84004, + .clkr = { + .enable_reg = 0x84004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_dcc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x64000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x64000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", + .parent_names = (const char *[]){ + "gp1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x65000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x65000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", + .parent_names = (const char *[]){ + "gp2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x66000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x66000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", + .parent_names = (const char *[]){ + "gp3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_bimc_gfx_clk = { + .halt_reg = 0x71010, + .halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, + .clkr = { + .enable_reg = 0x71010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_bimc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_bimc_gfx_src_clk = { + .halt_reg = 0x7100c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7100c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_bimc_gfx_src_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_cfg_ahb_clk = { + .halt_reg = 0x71004, + .halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, + .clkr = { + .enable_reg = 0x71004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_gate2 gpll0_out_msscc = { + .udelay = 1, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_msscc", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk", + .parent_names = (const char *[]){ + "gpll0_out_main", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_div_clk", + .parent_names = (const char *[]){ + "gpll0_out_early_div", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { + .halt_reg = 0x71018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x71018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_snoc_dvm_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_hmss_ahb_clk = { + .halt_reg = 0x48000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(21), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hmss_ahb_clk", + .parent_names = (const char *[]){ + "hmss_ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_hmss_dvm_bus_clk = { + .halt_reg = 0x4808c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4808c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hmss_dvm_bus_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_hmss_rbcpr_clk = { + .halt_reg = 0x48008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x48008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_hmss_rbcpr_clk", + .parent_names = (const char *[]){ + "hmss_rbcpr_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_gpll0_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_gpll0_clk", + .parent_names = (const char *[]){ + "gpll0_out_main", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_gpll0_div_clk = { + .halt_reg = 0x5200c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_gpll0_div_clk", + .parent_names = (const char *[]){ + "gpll0_out_early_div", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { + .halt_reg = 0x9004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_noc_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mmss_sys_noc_axi_clk = { + .halt_reg = 0x9000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mmss_sys_noc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_cfg_ahb_clk = { + .halt_reg = 0x8a000, + .clkr = { + .enable_reg = 0x8a000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { + .halt_reg = 0x8a004, + .clkr = { + .enable_reg = 0x8a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_mnoc_bimc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_q6_bimc_axi_clk = { + .halt_reg = 0x8a040, + .clkr = { + .enable_reg = 0x8a040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_q6_bimc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_snoc_axi_clk = { + .halt_reg = 0x8a03c, + .clkr = { + .enable_reg = 0x8a03c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_snoc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x3300c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3300c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk", + .parent_names = (const char *[]){ + "pdm2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x33004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x33004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x34004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qspi_ahb_clk = { + .halt_reg = 0x4d004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qspi_ser_clk = { + .halt_reg = 0x4d008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4d008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qspi_ser_clk", + .parent_names = (const char *[]){ + "qspi_ser_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx0_usb2_clkref_clk = { + .halt_reg = 0x88018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx0_usb2_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx1_usb2_clkref_clk = { + .halt_reg = 0x88014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx1_usb2_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_rx2_qlink_clkref_clk = { + .halt_reg = 0x88034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_rx2_qlink_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x16008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x16008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x16004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x16004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", + .parent_names = (const char *[]){ + "sdcc1_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk = { + .halt_reg = 0x1600c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1600c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk", + .parent_names = (const char *[]){ + "sdcc1_ice_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x14008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x14008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk = { + .halt_reg = 0x14004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x14004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk", + .parent_names = (const char *[]){ + "sdcc2_apps_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_ahb_clk = { + .halt_reg = 0x7500c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7500c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_axi_clk = { + .halt_reg = 0x75008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x75008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_axi_clk", + .parent_names = (const char *[]){ + "ufs_axi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_axi_hw_ctl_clk = { + .halt_reg = 0x75008, + .clkr = { + .enable_reg = 0x75008, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_axi_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_axi_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_clkref_clk = { + .halt_reg = 0x88008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x88008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_ice_core_clk = { + .halt_reg = 0x7600c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x7600c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ice_core_clk", + .parent_names = (const char *[]){ + "ufs_ice_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_ice_core_hw_ctl_clk = { + .halt_reg = 0x7600c, + .clkr = { + .enable_reg = 0x7600c, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_ice_core_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_ice_core_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_aux_clk = { + .halt_reg = 0x76040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x76040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_aux_clk", + .parent_names = (const char *[]){ + "ufs_phy_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_aux_hw_ctl_clk = { + .halt_reg = 0x76040, + .clkr = { + .enable_reg = 0x76040, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_aux_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_phy_aux_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_gate2 gcc_ufs_rx_symbol_0_clk = { + .udelay = 500, + .clkr = { + .enable_reg = 0x75014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_rx_symbol_0_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_gate2 gcc_ufs_rx_symbol_1_clk = { + .udelay = 500, + .clkr = { + .enable_reg = 0x7605c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_rx_symbol_1_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_gate2 gcc_ufs_tx_symbol_0_clk = { + .udelay = 500, + .clkr = { + .enable_reg = 0x75010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_tx_symbol_0_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_unipro_core_clk = { + .halt_reg = 0x76008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x76008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_unipro_core_clk", + .parent_names = (const char *[]){ + "ufs_unipro_core_clk_src", + }, + .flags = CLK_SET_RATE_PARENT, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_unipro_core_hw_ctl_clk = { + .halt_reg = 0x76008, + .clkr = { + .enable_reg = 0x76008, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_unipro_core_hw_ctl_clk", + .parent_names = (const char *[]){ + "gcc_ufs_unipro_core_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_hw_ctl_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_master_clk = { + .halt_reg = 0x2f004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2f004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_master_clk", + .parent_names = (const char *[]){ + "usb20_master_clk_src", + }, + .flags = CLK_SET_RATE_PARENT, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_mock_utmi_clk = { + .halt_reg = 0x2f00c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2f00c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_mock_utmi_clk", + .parent_names = (const char *[]){ + "usb20_mock_utmi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb20_sleep_clk = { + .halt_reg = 0x2f008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2f008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb20_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_master_clk = { + .halt_reg = 0xf008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_master_clk", + .parent_names = (const char *[]){ + "usb30_master_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mock_utmi_clk = { + .halt_reg = 0xf010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_mock_utmi_clk", + .parent_names = (const char *[]){ + "usb30_mock_utmi_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sleep_clk = { + .halt_reg = 0xf00c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf00c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_clkref_clk = { + .halt_reg = 0x8800c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8800c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_phy_aux_clk = { + .halt_reg = 0x50000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x50000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_aux_clk", + .parent_names = (const char *[]){ + "usb3_phy_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_gate2 gcc_usb3_phy_pipe_clk = { + .udelay = 50, + .clkr = { + .enable_reg = 0x50004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_pipe_clk", + .ops = &clk_gate2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { + .halt_reg = 0x6a004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x6a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb_phy_cfg_ahb2phy_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch hlos1_vote_lpass_adsp_smmu_clk = { + .halt_reg = 0x7d014, + .halt_check = BRANCH_HALT_NO_CHECK_ON_DISABLE, + .clkr = { + .enable_reg = 0x7d014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "hlos1_vote_lpass_adsp_smmu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_fixed_factor gcc_ce1_ahb_m_clk = { + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_ahb_m_clk", + .ops = &clk_dummy_ops, + }, +}; + +static struct clk_fixed_factor gcc_ce1_axi_m_clk = { + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_axi_m_clk", + .ops = &clk_dummy_ops, + }, +}; + +struct clk_hw *gcc_msmfalcon_hws[] = { + [GCC_XO] = &xo.hw, + [GCC_GPLL0_EARLY_DIV] = &gpll0_out_early_div.hw, + [GCC_GPLL1_EARLY_DIV] = &gpll1_out_early_div.hw, + [GCC_CE1_AHB_M_CLK] = &gcc_ce1_ahb_m_clk.hw, + [GCC_CE1_AXI_M_CLK] = &gcc_ce1_axi_m_clk.hw, +}; + +static struct clk_regmap *gcc_falcon_clocks[] = { + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, + [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr, + [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr, + [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr, + [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr, + [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr, + [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr, + [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr, + [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr, + [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr, + [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr, + [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr, + [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr, + [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, + [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr, + [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr, + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr, + [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr, + [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr, + [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr, + [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr, + [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr, + [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr, + [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr, + [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr, + [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr, + [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr, + [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, + [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr, + [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr, + [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr, + [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr, + [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr, + [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr, + [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr, + [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr, + [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, + [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, + [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr, + [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr, + [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr, + [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, + [GCC_RX2_QLINK_CLKREF_CLK] = &gcc_rx2_qlink_clkref_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr, + [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr, + [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr, + [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr, + [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr, + [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr, + [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr, + [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr, + [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr, + [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr, + [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr, + [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr, + [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, + [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, + [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, + [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, + [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, + [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, + [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, + [GP1_CLK_SRC] = &gp1_clk_src.clkr, + [GP2_CLK_SRC] = &gp2_clk_src.clkr, + [GP3_CLK_SRC] = &gp3_clk_src.clkr, + [GPLL0] = &gpll0_out_main.clkr, + [GPLL1] = &gpll1_out_main.clkr, + [GPLL4] = &gpll4_out_main.clkr, + [HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &hlos1_vote_lpass_adsp_smmu_clk.clkr, + [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr, + [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr, + [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr, + [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr, + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, + [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, + [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, + [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr, + [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr, + [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr, + [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr, + [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr, + [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr, + [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr, + [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr, + [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr, + [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, + [GCC_UFS_AXI_HW_CTL_CLK] = &gcc_ufs_axi_hw_ctl_clk.clkr, + [GCC_UFS_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_ice_core_hw_ctl_clk.clkr, + [GCC_UFS_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_aux_hw_ctl_clk.clkr, + [GCC_UFS_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_unipro_core_hw_ctl_clk.clkr, +}; + +static const struct qcom_reset_map gcc_falcon_resets[] = { + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, + [GCC_UFS_BCR] = { 0x75000 }, + [GCC_USB3_DP_PHY_BCR] = { 0x50028 }, + [GCC_USB3_PHY_BCR] = { 0x50020 }, + [GCC_USB3PHY_PHY_BCR] = { 0x50024 }, + [GCC_USB_20_BCR] = { 0x2f000 }, + [GCC_USB_30_BCR] = { 0xf000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, +}; + +static const struct regmap_config gcc_falcon_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x94000, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_falcon_desc = { + .config = &gcc_falcon_regmap_config, + .clks = gcc_falcon_clocks, + .num_clks = ARRAY_SIZE(gcc_falcon_clocks), + .resets = gcc_falcon_resets, + .num_resets = ARRAY_SIZE(gcc_falcon_resets), +}; + +static const struct of_device_id gcc_falcon_match_table[] = { + { .compatible = "qcom,gcc-msmfalcon" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_falcon_match_table); + +static int gcc_falcon_probe(struct platform_device *pdev) +{ + int ret = 0, i; + struct regmap *regmap; + struct clk *clk; + + regmap = qcom_cc_map(pdev, &gcc_falcon_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* + * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be + * turned off by hardware during certain apps low power modes. + */ + regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); + + /* register hardware clocks */ + for (i = 0; i < ARRAY_SIZE(gcc_msmfalcon_hws); i++) { + clk = devm_clk_register(&pdev->dev, gcc_msmfalcon_hws[i]); + if (IS_ERR(clk)) + return PTR_ERR(clk); + } + + vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); + if (IS_ERR(vdd_dig.regulator[0])) { + if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig regulator\n"); + return PTR_ERR(vdd_dig.regulator[0]); + } + + vdd_dig_ao.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_ao"); + if (IS_ERR(vdd_dig_ao.regulator[0])) { + if (!(PTR_ERR(vdd_dig_ao.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig_ao regulator\n"); + return PTR_ERR(vdd_dig_ao.regulator[0]); + } + + ret = qcom_cc_really_probe(pdev, &gcc_falcon_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register GCC clocks\n"); + return ret; + } + + /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ + regmap_update_bits(regmap, 0x0902c, 0x3, 0x3); + regmap_update_bits(regmap, 0x71028, 0x3, 0x3); + + /* This clock is used for all MMSSCC register access */ + clk_prepare_enable(gcc_mmss_noc_cfg_ahb_clk.clkr.hw.clk); + + /* This clock is used for all GPUCC register access */ + clk_prepare_enable(gcc_gpu_cfg_ahb_clk.clkr.hw.clk); + + dev_info(&pdev->dev, "Registered GCC clocks\n"); + + return ret; +} + +static struct platform_driver gcc_falcon_driver = { + .probe = gcc_falcon_probe, + .driver = { + .name = "gcc-msmfalcon", + .of_match_table = gcc_falcon_match_table, + }, +}; + +static int __init gcc_falcon_init(void) +{ + return platform_driver_register(&gcc_falcon_driver); +} +core_initcall_sync(gcc_falcon_init); + +static void __exit gcc_falcon_exit(void) +{ + platform_driver_unregister(&gcc_falcon_driver); +} +module_exit(gcc_falcon_exit); diff --git a/drivers/clk/qcom/gdsc-regulator.c b/drivers/clk/qcom/gdsc-regulator.c new file mode 100644 index 000000000000..e645354445cb --- /dev/null +++ b/drivers/clk/qcom/gdsc-regulator.c @@ -0,0 +1,745 @@ +/* + * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/of_regulator.h> +#include <linux/slab.h> +#include <linux/clk.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include <linux/mfd/syscon.h> + +#include "clk-branch.h" + +/* GDSCR */ +#define PWR_ON_MASK BIT(31) +#define CLK_DIS_WAIT_MASK (0xF << 12) +#define CLK_DIS_WAIT_SHIFT (12) +#define SW_OVERRIDE_MASK BIT(2) +#define HW_CONTROL_MASK BIT(1) +#define SW_COLLAPSE_MASK BIT(0) + +/* Domain Address */ +#define GMEM_CLAMP_IO_MASK BIT(0) +#define GMEM_RESET_MASK BIT(4) + +/* SW Reset */ +#define BCR_BLK_ARES_BIT BIT(0) + +/* Register Offset */ +#define REG_OFFSET 0x0 + +/* Timeout Delay */ +#define TIMEOUT_US 100 + +struct gdsc { + struct regulator_dev *rdev; + struct regulator_desc rdesc; + void __iomem *gdscr; + struct regmap *regmap; + struct regmap *domain_addr; + struct regmap *hw_ctrl; + struct regmap *sw_reset; + struct clk **clocks; + struct reset_control **reset_clocks; + bool toggle_mem; + bool toggle_periph; + bool toggle_logic; + bool resets_asserted; + bool root_en; + bool force_root_en; + bool no_status_check_on_disable; + bool is_gdsc_enabled; + bool allow_clear; + bool reset_aon; + int clock_count; + int reset_count; + int root_clk_idx; + u32 gds_timeout; +}; + +enum gdscr_status { + ENABLED, + DISABLED, +}; + +static DEFINE_MUTEX(gdsc_seq_lock); + +void gdsc_allow_clear_retention(struct regulator *regulator) +{ + struct gdsc *sc = regulator_get_drvdata(regulator); + + if (sc) + sc->allow_clear = true; +} + +static int poll_gdsc_status(struct gdsc *sc, enum gdscr_status status) +{ + struct regmap *regmap; + int count = sc->gds_timeout; + u32 val; + + if (sc->hw_ctrl) + regmap = sc->hw_ctrl; + else + regmap = sc->regmap; + + for (; count > 0; count--) { + regmap_read(regmap, REG_OFFSET, &val); + val &= PWR_ON_MASK; + + switch (status) { + case ENABLED: + if (val) + return 0; + break; + case DISABLED: + if (!val) + return 0; + break; + } + /* + * There is no guarantee about the delay needed for the enable + * bit in the GDSCR to be set or reset after the GDSC state + * changes. Hence, keep on checking for a reasonable number + * of times until the bit is set with the least possible delay + * between succeessive tries. + */ + udelay(1); + } + + return -ETIMEDOUT; +} + +static int gdsc_is_enabled(struct regulator_dev *rdev) +{ + struct gdsc *sc = rdev_get_drvdata(rdev); + uint32_t regval; + + if (!sc->toggle_logic) + return !sc->resets_asserted; + + regmap_read(sc->regmap, REG_OFFSET, ®val); + + if (regval & PWR_ON_MASK) { + /* + * The GDSC might be turned on due to TZ/HYP vote on the + * votable GDS registers. Check the SW_COLLAPSE_MASK to + * determine if HLOS has voted for it. + */ + if (!(regval & SW_COLLAPSE_MASK)) + return true; + } + + return false; +} + +static int gdsc_enable(struct regulator_dev *rdev) +{ + struct gdsc *sc = rdev_get_drvdata(rdev); + uint32_t regval, hw_ctrl_regval = 0x0; + int i, ret = 0; + + mutex_lock(&gdsc_seq_lock); + + if (sc->root_en || sc->force_root_en) + clk_prepare_enable(sc->clocks[sc->root_clk_idx]); + + regmap_read(sc->regmap, REG_OFFSET, ®val); + if (regval & HW_CONTROL_MASK) { + dev_warn(&rdev->dev, "Invalid enable while %s is under HW control\n", + sc->rdesc.name); + mutex_unlock(&gdsc_seq_lock); + return -EBUSY; + } + + if (sc->toggle_logic) { + if (sc->sw_reset) { + regmap_read(sc->sw_reset, REG_OFFSET, ®val); + regval |= BCR_BLK_ARES_BIT; + regmap_write(sc->sw_reset, REG_OFFSET, regval); + /* + * BLK_ARES should be kept asserted for 1us before + * being de-asserted. + */ + wmb(); + udelay(1); + + regval &= ~BCR_BLK_ARES_BIT; + regmap_write(sc->sw_reset, REG_OFFSET, regval); + /* Make sure de-assert goes through before continuing */ + wmb(); + } + + if (sc->domain_addr) { + if (sc->reset_aon) { + regmap_read(sc->domain_addr, REG_OFFSET, + ®val); + regval |= GMEM_RESET_MASK; + regmap_write(sc->domain_addr, REG_OFFSET, + regval); + /* + * Keep reset asserted for at-least 1us before + * continuing. + */ + wmb(); + udelay(1); + + regval &= ~GMEM_RESET_MASK; + regmap_write(sc->domain_addr, REG_OFFSET, + regval); + /* + * Make sure GMEM_RESET is de-asserted before + * continuing. + */ + wmb(); + } + + regmap_read(sc->domain_addr, REG_OFFSET, ®val); + regval &= ~GMEM_CLAMP_IO_MASK; + regmap_write(sc->domain_addr, REG_OFFSET, regval); + + /* + * Make sure CLAMP_IO is de-asserted before continuing. + */ + wmb(); + } + + regmap_read(sc->regmap, REG_OFFSET, ®val); + regval &= ~SW_COLLAPSE_MASK; + regmap_write(sc->regmap, REG_OFFSET, regval); + + /* Wait for 8 XO cycles before polling the status bit. */ + mb(); + udelay(1); + + ret = poll_gdsc_status(sc, ENABLED); + if (ret) { + regmap_read(sc->regmap, REG_OFFSET, ®val); + + if (sc->hw_ctrl) { + regmap_read(sc->hw_ctrl, REG_OFFSET, + &hw_ctrl_regval); + dev_warn(&rdev->dev, "%s state (after %d us timeout): 0x%x, GDS_HW_CTRL: 0x%x. Re-polling.\n", + sc->rdesc.name, sc->gds_timeout, + regval, hw_ctrl_regval); + + ret = poll_gdsc_status(sc, ENABLED); + if (ret) { + regmap_read(sc->regmap, REG_OFFSET, + ®val); + regmap_read(sc->hw_ctrl, REG_OFFSET, + &hw_ctrl_regval); + dev_err(&rdev->dev, "%s final state (after additional %d us timeout): 0x%x, GDS_HW_CTRL: 0x%x\n", + sc->rdesc.name, sc->gds_timeout, + regval, hw_ctrl_regval); + + mutex_unlock(&gdsc_seq_lock); + return ret; + } + } else { + dev_err(&rdev->dev, "%s enable timed out: 0x%x\n", + sc->rdesc.name, + regval); + udelay(sc->gds_timeout); + + regmap_read(sc->regmap, REG_OFFSET, ®val); + dev_err(&rdev->dev, "%s final state: 0x%x (%d us after timeout)\n", + sc->rdesc.name, regval, + sc->gds_timeout); + + mutex_unlock(&gdsc_seq_lock); + + return ret; + } + } + } else { + for (i = 0; i < sc->reset_count; i++) + reset_control_deassert(sc->reset_clocks[i]); + sc->resets_asserted = false; + } + + for (i = 0; i < sc->clock_count; i++) { + if (unlikely(i == sc->root_clk_idx)) + continue; + if (sc->toggle_mem) + clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_MEM); + if (sc->toggle_periph) + clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_PERIPH); + } + + /* + * If clocks to this power domain were already on, they will take an + * additional 4 clock cycles to re-enable after the rail is enabled. + * Delay to account for this. A delay is also needed to ensure clocks + * are not enabled within 400ns of enabling power to the memories. + */ + udelay(1); + + /* Delay to account for staggered memory powerup. */ + udelay(1); + + if (sc->force_root_en) + clk_disable_unprepare(sc->clocks[sc->root_clk_idx]); + + sc->is_gdsc_enabled = true; + + mutex_unlock(&gdsc_seq_lock); + + return ret; +} + +static int gdsc_disable(struct regulator_dev *rdev) +{ + struct gdsc *sc = rdev_get_drvdata(rdev); + uint32_t regval; + int i, ret = 0; + + mutex_lock(&gdsc_seq_lock); + + if (sc->force_root_en) + clk_prepare_enable(sc->clocks[sc->root_clk_idx]); + + for (i = sc->clock_count - 1; i >= 0; i--) { + if (unlikely(i == sc->root_clk_idx)) + continue; + if (sc->toggle_mem && sc->allow_clear) + clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_MEM); + if (sc->toggle_periph && sc->allow_clear) + clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_PERIPH); + } + + /* Delay to account for staggered memory powerdown. */ + udelay(1); + + if (sc->toggle_logic) { + regmap_read(sc->regmap, REG_OFFSET, ®val); + regval |= SW_COLLAPSE_MASK; + regmap_write(sc->regmap, REG_OFFSET, regval); + + /* Wait for 8 XO cycles before polling the status bit. */ + mb(); + udelay(1); + + if (sc->no_status_check_on_disable) { + /* + * Add a short delay here to ensure that gdsc_enable + * right after it was disabled does not put it in a + * weird state. + */ + udelay(TIMEOUT_US); + } else { + ret = poll_gdsc_status(sc, DISABLED); + if (ret) + dev_err(&rdev->dev, "%s disable timed out: 0x%x\n", + sc->rdesc.name, regval); + } + + if (sc->domain_addr) { + regmap_read(sc->domain_addr, REG_OFFSET, ®val); + regval |= GMEM_CLAMP_IO_MASK; + regmap_write(sc->domain_addr, REG_OFFSET, regval); + } + + } else { + for (i = sc->reset_count - 1; i >= 0; i--) + reset_control_assert(sc->reset_clocks[i]); + sc->resets_asserted = true; + } + + /* + * Check if gdsc_enable was called for this GDSC. If not, the root + * clock will not have been enabled prior to this. + */ + if ((sc->is_gdsc_enabled && sc->root_en) || sc->force_root_en) + clk_disable_unprepare(sc->clocks[sc->root_clk_idx]); + + sc->is_gdsc_enabled = false; + + mutex_unlock(&gdsc_seq_lock); + + return ret; +} + +static unsigned int gdsc_get_mode(struct regulator_dev *rdev) +{ + struct gdsc *sc = rdev_get_drvdata(rdev); + uint32_t regval; + + mutex_lock(&gdsc_seq_lock); + regmap_read(sc->regmap, REG_OFFSET, ®val); + mutex_unlock(&gdsc_seq_lock); + + if (regval & HW_CONTROL_MASK) + return REGULATOR_MODE_FAST; + + return REGULATOR_MODE_NORMAL; +} + +static int gdsc_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + struct gdsc *sc = rdev_get_drvdata(rdev); + uint32_t regval; + int ret = 0; + + mutex_lock(&gdsc_seq_lock); + + regmap_read(sc->regmap, REG_OFFSET, ®val); + + switch (mode) { + case REGULATOR_MODE_FAST: + /* Turn on HW trigger mode */ + regval |= HW_CONTROL_MASK; + regmap_write(sc->regmap, REG_OFFSET, regval); + /* + * There may be a race with internal HW trigger signal, + * that will result in GDSC going through a power down and + * up cycle. In case HW trigger signal is controlled by + * firmware that also poll same status bits as we do, FW + * might read an 'on' status before the GDSC can finish + * power cycle. We wait 1us before returning to ensure + * FW can't immediately poll the status bit. + */ + mb(); + udelay(1); + break; + case REGULATOR_MODE_NORMAL: + /* Turn off HW trigger mode */ + regval &= ~HW_CONTROL_MASK; + regmap_write(sc->regmap, REG_OFFSET, regval); + /* + * There may be a race with internal HW trigger signal, + * that will result in GDSC going through a power down and + * up cycle. If we poll too early, status bit will + * indicate 'on' before the GDSC can finish the power cycle. + * Account for this case by waiting 1us before polling. + */ + mb(); + udelay(1); + + ret = poll_gdsc_status(sc, ENABLED); + if (ret) + dev_err(&rdev->dev, "%s set_mode timed out: 0x%x\n", + sc->rdesc.name, regval); + break; + default: + ret = -EINVAL; + break; + } + + mutex_unlock(&gdsc_seq_lock); + + return ret; +} + +static struct regulator_ops gdsc_ops = { + .is_enabled = gdsc_is_enabled, + .enable = gdsc_enable, + .disable = gdsc_disable, + .set_mode = gdsc_set_mode, + .get_mode = gdsc_get_mode, +}; + +static const struct regmap_config gdsc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static int gdsc_probe(struct platform_device *pdev) +{ + static atomic_t gdsc_count = ATOMIC_INIT(-1); + struct regulator_config reg_config = {}; + struct regulator_init_data *init_data; + struct resource *res; + struct gdsc *sc; + uint32_t regval, clk_dis_wait_val = 0; + bool retain_mem, retain_periph, support_hw_trigger; + int i, ret; + u32 timeout; + + sc = devm_kzalloc(&pdev->dev, sizeof(struct gdsc), GFP_KERNEL); + if (sc == NULL) + return -ENOMEM; + + init_data = of_get_regulator_init_data(&pdev->dev, pdev->dev.of_node, + &sc->rdesc); + if (init_data == NULL) + return -ENOMEM; + + if (of_get_property(pdev->dev.of_node, "parent-supply", NULL)) + init_data->supply_regulator = "parent"; + + ret = of_property_read_string(pdev->dev.of_node, "regulator-name", + &sc->rdesc.name); + if (ret) + return ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "Failed to get resources\n"); + return -EINVAL; + } + + sc->gdscr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (sc->gdscr == NULL) + return -ENOMEM; + + sc->regmap = devm_regmap_init_mmio(&pdev->dev, sc->gdscr, + &gdsc_regmap_config); + if (!sc->regmap) { + dev_err(&pdev->dev, "Couldn't get regmap\n"); + return -EINVAL; + } + + if (of_find_property(pdev->dev.of_node, "domain-addr", NULL)) { + sc->domain_addr = syscon_regmap_lookup_by_phandle + (pdev->dev.of_node, "domain-addr"); + if (IS_ERR(sc->domain_addr)) + return -ENODEV; + } + + if (of_find_property(pdev->dev.of_node, "sw-reset", NULL)) { + sc->sw_reset = syscon_regmap_lookup_by_phandle + (pdev->dev.of_node, "sw-reset"); + if (IS_ERR(sc->sw_reset)) + return -ENODEV; + } + + if (of_find_property(pdev->dev.of_node, "hw-ctrl-addr", NULL)) { + sc->hw_ctrl = syscon_regmap_lookup_by_phandle( + pdev->dev.of_node, "hw-ctrl-addr"); + if (IS_ERR(sc->hw_ctrl)) + return -ENODEV; + } + + sc->gds_timeout = TIMEOUT_US; + + ret = of_property_read_u32(pdev->dev.of_node, "qcom,gds-timeout", + &timeout); + if (!ret) + sc->gds_timeout = timeout; + + sc->clock_count = of_property_count_strings(pdev->dev.of_node, + "clock-names"); + if (sc->clock_count == -EINVAL) { + sc->clock_count = 0; + } else if (IS_ERR_VALUE(sc->clock_count)) { + dev_err(&pdev->dev, "Failed to get clock names\n"); + return -EINVAL; + } + + sc->clocks = devm_kzalloc(&pdev->dev, + sizeof(struct clk *) * sc->clock_count, GFP_KERNEL); + if (!sc->clocks) + return -ENOMEM; + + sc->root_clk_idx = -1; + + sc->root_en = of_property_read_bool(pdev->dev.of_node, + "qcom,enable-root-clk"); + + sc->force_root_en = of_property_read_bool(pdev->dev.of_node, + "qcom,force-enable-root-clk"); + + for (i = 0; i < sc->clock_count; i++) { + const char *clock_name; + + of_property_read_string_index(pdev->dev.of_node, "clock-names", + i, &clock_name); + + sc->clocks[i] = devm_clk_get(&pdev->dev, clock_name); + if (IS_ERR(sc->clocks[i])) { + int rc = PTR_ERR(sc->clocks[i]); + + if (rc != -EPROBE_DEFER) + dev_err(&pdev->dev, "Failed to get %s\n", + clock_name); + return rc; + } + + if (!strcmp(clock_name, "core_root_clk")) + sc->root_clk_idx = i; + } + + if ((sc->root_en || sc->force_root_en) && (sc->root_clk_idx == -1)) { + dev_err(&pdev->dev, "Failed to get root clock name\n"); + return -EINVAL; + } + + sc->reset_aon = of_property_read_bool(pdev->dev.of_node, + "qcom,reset-aon-logic"); + + sc->rdesc.id = atomic_inc_return(&gdsc_count); + sc->rdesc.ops = &gdsc_ops; + sc->rdesc.type = REGULATOR_VOLTAGE; + sc->rdesc.owner = THIS_MODULE; + platform_set_drvdata(pdev, sc); + + /* + * Disable HW trigger: collapse/restore occur based on registers writes. + * Disable SW override: Use hardware state-machine for sequencing. + */ + regmap_read(sc->regmap, REG_OFFSET, ®val); + regval &= ~(HW_CONTROL_MASK | SW_OVERRIDE_MASK); + + if (!of_property_read_u32(pdev->dev.of_node, "qcom,clk-dis-wait-val", + &clk_dis_wait_val)) { + clk_dis_wait_val = clk_dis_wait_val << CLK_DIS_WAIT_SHIFT; + + /* Configure wait time between states. */ + regval &= ~(CLK_DIS_WAIT_MASK); + regval |= clk_dis_wait_val; + } + + regmap_write(sc->regmap, REG_OFFSET, regval); + + sc->no_status_check_on_disable = + of_property_read_bool(pdev->dev.of_node, + "qcom,no-status-check-on-disable"); + retain_mem = of_property_read_bool(pdev->dev.of_node, + "qcom,retain-mem"); + sc->toggle_mem = !retain_mem; + retain_periph = of_property_read_bool(pdev->dev.of_node, + "qcom,retain-periph"); + sc->toggle_periph = !retain_periph; + sc->toggle_logic = !of_property_read_bool(pdev->dev.of_node, + "qcom,skip-logic-collapse"); + support_hw_trigger = of_property_read_bool(pdev->dev.of_node, + "qcom,support-hw-trigger"); + if (support_hw_trigger) { + init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_MODE; + init_data->constraints.valid_modes_mask |= + REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST; + } + + if (!sc->toggle_logic) { + sc->reset_count = of_property_count_strings(pdev->dev.of_node, + "reset-names"); + if (sc->reset_count == -EINVAL) { + sc->reset_count = 0; + } else if (IS_ERR_VALUE(sc->reset_count)) { + dev_err(&pdev->dev, "Failed to get reset clock names\n"); + return -EINVAL; + } + + sc->reset_clocks = devm_kzalloc(&pdev->dev, + sizeof(struct reset_control *) * sc->reset_count, + GFP_KERNEL); + if (!sc->reset_clocks) + return -ENOMEM; + + for (i = 0; i < sc->reset_count; i++) { + const char *reset_name; + + of_property_read_string_index(pdev->dev.of_node, + "reset-names", i, &reset_name); + sc->reset_clocks[i] = devm_reset_control_get(&pdev->dev, + reset_name); + if (IS_ERR(sc->reset_clocks[i])) { + int rc = PTR_ERR(sc->reset_clocks[i]); + + if (rc != -EPROBE_DEFER) + dev_err(&pdev->dev, "Failed to get %s\n", + reset_name); + return rc; + } + } + + regval &= ~SW_COLLAPSE_MASK; + regmap_write(sc->regmap, REG_OFFSET, regval); + + ret = poll_gdsc_status(sc, ENABLED); + if (ret) { + dev_err(&pdev->dev, "%s enable timed out: 0x%x\n", + sc->rdesc.name, regval); + return ret; + } + } + + sc->allow_clear = of_property_read_bool(pdev->dev.of_node, + "qcom,disallow-clear"); + sc->allow_clear = !sc->allow_clear; + + for (i = 0; i < sc->clock_count; i++) { + if (retain_mem || (regval & PWR_ON_MASK) || !sc->allow_clear) + clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_MEM); + else + clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_MEM); + + if (retain_periph || (regval & PWR_ON_MASK) || !sc->allow_clear) + clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_PERIPH); + else + clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_PERIPH); + } + + reg_config.dev = &pdev->dev; + reg_config.init_data = init_data; + reg_config.driver_data = sc; + reg_config.of_node = pdev->dev.of_node; + reg_config.regmap = sc->regmap; + + sc->rdev = regulator_register(&sc->rdesc, ®_config); + if (IS_ERR(sc->rdev)) { + dev_err(&pdev->dev, "regulator_register(\"%s\") failed.\n", + sc->rdesc.name); + return PTR_ERR(sc->rdev); + } + + return 0; +} + +static int gdsc_remove(struct platform_device *pdev) +{ + struct gdsc *sc = platform_get_drvdata(pdev); + + regulator_unregister(sc->rdev); + + return 0; +} + +static const struct of_device_id gdsc_match_table[] = { + { .compatible = "qcom,gdsc" }, + {} +}; + +static struct platform_driver gdsc_driver = { + .probe = gdsc_probe, + .remove = gdsc_remove, + .driver = { + .name = "gdsc", + .of_match_table = gdsc_match_table, + .owner = THIS_MODULE, + }, +}; + +static int __init gdsc_init(void) +{ + return platform_driver_register(&gdsc_driver); +} +subsys_initcall(gdsc_init); + +static void __exit gdsc_exit(void) +{ + platform_driver_unregister(&gdsc_driver); +} +module_exit(gdsc_exit); diff --git a/drivers/clk/qcom/vdd-level-falcon.h b/drivers/clk/qcom/vdd-level-falcon.h new file mode 100644 index 000000000000..e8699358cf91 --- /dev/null +++ b/drivers/clk/qcom/vdd-level-falcon.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H +#define __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H + +#include <linux/regulator/rpm-smd-regulator.h> +#include <linux/regulator/consumer.h> + +#define VDD_DIG_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdd_dig, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_fmax = VDD_DIG_NUM +#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ + .vdd_class = &vdd_dig, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ + .vdd_class = &vdd_dig, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + }, \ + .num_fmax = VDD_DIG_NUM +#define VDD_DIG_FMAX_MAP4(l1, f1, l2, f2, l3, f3, l4, f4) \ + .vdd_class = &vdd_dig, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP5(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5) \ + .vdd_class = &vdd_dig, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + [VDD_DIG_##l5] = (f5), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP6(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6) \ + .vdd_class = &vdd_dig, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + [VDD_DIG_##l5] = (f5), \ + [VDD_DIG_##l6] = (f6), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP7(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6, \ + l7, f7) \ + .vdd_class = &vdd_dig, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + [VDD_DIG_##l5] = (f5), \ + [VDD_DIG_##l6] = (f6), \ + [VDD_DIG_##l7] = (f7), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP1_AO(l1, f1) \ + .vdd_class = &vdd_dig_ao, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_DIG_FMAX_MAP3_AO(l1, f1, l2, f2, l3, f3) \ + .vdd_class = &vdd_dig_ao, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + }, \ + .num_fmax = VDD_DIG_NUM + +#define VDD_GPU_PLL_FMAX_MAP6(l1, f1, l2, f2, l3, f3, l4, f4, l5, f5, l6, f6) \ + .vdd_class = &vdd_mx, \ + .fmax = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + [VDD_DIG_##l3] = (f3), \ + [VDD_DIG_##l4] = (f4), \ + [VDD_DIG_##l5] = (f5), \ + [VDD_DIG_##l6] = (f6), \ + }, \ + .num_fmax = VDD_DIG_NUM + +enum vdd_dig_levels { + VDD_DIG_NONE, + VDD_DIG_MIN, /* MIN SVS */ + VDD_DIG_LOWER, /* SVS2 */ + VDD_DIG_LOW, /* SVS */ + VDD_DIG_LOW_L1, /* SVSL1 */ + VDD_DIG_NOMINAL, /* NOM */ + VDD_DIG_NOMINAL_L1, /* NOM */ + VDD_DIG_HIGH, /* TURBO */ + VDD_DIG_NUM +}; + +static int vdd_corner[] = { + RPM_REGULATOR_LEVEL_NONE, /* VDD_DIG_NONE */ + RPM_REGULATOR_LEVEL_MIN_SVS, /* VDD_DIG_MIN */ + RPM_REGULATOR_LEVEL_LOW_SVS, /* VDD_DIG_LOWER */ + RPM_REGULATOR_LEVEL_SVS, /* VDD_DIG_LOW */ + RPM_REGULATOR_LEVEL_SVS_PLUS, /* VDD_DIG_LOW_L1 */ + RPM_REGULATOR_LEVEL_NOM, /* VDD_DIG_NOMINAL */ + RPM_REGULATOR_LEVEL_NOM_PLUS, /* VDD_DIG_NOMINAL */ + RPM_REGULATOR_LEVEL_TURBO, /* VDD_DIG_HIGH */ +}; + +#endif diff --git a/drivers/devfreq/bimc-bwmon.c b/drivers/devfreq/bimc-bwmon.c index 707a244e62e9..315d3a67e43e 100644 --- a/drivers/devfreq/bimc-bwmon.c +++ b/drivers/devfreq/bimc-bwmon.c @@ -377,7 +377,7 @@ static unsigned long mon_get_zone_stats(struct bwmon *m) zone = get_zone(m); - count = readl_relaxed(MON2_ZONE_MAX(m, zone)); + count = readl_relaxed(MON2_ZONE_MAX(m, zone)) + 1; count *= SZ_1M; dev_dbg(m->dev, "Zone%d Max byte count: %08lx\n", zone, count); diff --git a/drivers/gpu/msm/a4xx_reg.h b/drivers/gpu/msm/a4xx_reg.h index 4b69583a6ce1..8e658c1d54d2 100644 --- a/drivers/gpu/msm/a4xx_reg.h +++ b/drivers/gpu/msm/a4xx_reg.h @@ -197,6 +197,7 @@ enum a4xx_rb_perfctr_rb_sel { #define A4XX_RBBM_CFG_DEBBUS_CLRC 0x94 #define A4XX_RBBM_CFG_DEBBUS_LOADIVT 0x95 +#define A4XX_RBBM_CLOCK_CTL_IP 0x97 #define A4XX_RBBM_POWER_CNTL_IP 0x98 #define A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x99 #define A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x9a diff --git a/drivers/gpu/msm/adreno_a4xx.c b/drivers/gpu/msm/adreno_a4xx.c index 7a691667e59f..bfbdb0e7ac1f 100644 --- a/drivers/gpu/msm/adreno_a4xx.c +++ b/drivers/gpu/msm/adreno_a4xx.c @@ -26,6 +26,8 @@ #include "adreno_perfcounter.h" #define SP_TP_PWR_ON BIT(20) +/* A4XX_RBBM_CLOCK_CTL_IP */ +#define CNTL_IP_SW_COLLAPSE BIT(0) /* * Define registers for a4xx that contain addresses used by the @@ -201,6 +203,131 @@ static bool a4xx_is_sptp_idle(struct adreno_device *adreno_dev) } /* + * a4xx_enable_hwcg() - Program the clock control registers + * @device: The adreno device pointer + */ +static void a4xx_enable_hwcg(struct kgsl_device *device) +{ + struct adreno_device *adreno_dev = ADRENO_DEVICE(device); + + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_TP0, 0x02222202); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_TP1, 0x02222202); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_TP2, 0x02222202); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_TP3, 0x02222202); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_TP0, 0x00002222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_TP1, 0x00002222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_TP2, 0x00002222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_TP3, 0x00002222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_TP0, 0x0E739CE7); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_TP1, 0x0E739CE7); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_TP2, 0x0E739CE7); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_TP3, 0x0E739CE7); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_TP0, 0x00111111); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_TP1, 0x00111111); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_TP2, 0x00111111); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_TP3, 0x00111111); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP0, 0x22222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP1, 0x22222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP2, 0x22222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP3, 0x22222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP0, 0x00222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP1, 0x00222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP2, 0x00222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP3, 0x00222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_SP0, 0x00000104); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_SP1, 0x00000104); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_SP2, 0x00000104); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_SP3, 0x00000104); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_SP0, 0x00000081); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_SP1, 0x00000081); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_SP2, 0x00000081); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_SP3, 0x00000081); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_UCHE, 0x22222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_UCHE, 0x02222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL3_UCHE, 0x00000000); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL4_UCHE, 0x00000000); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_UCHE, 0x00004444); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_UCHE, 0x00001112); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_RB0, 0x22222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_RB1, 0x22222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_RB2, 0x22222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_RB3, 0x22222222); + /* Disable L1 clocking in A420 due to CCU issues with it */ + if (adreno_is_a420(adreno_dev)) { + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB0, 0x00002020); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB1, 0x00002020); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB2, 0x00002020); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB3, 0x00002020); + } else { + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB0, 0x00022020); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB1, 0x00022020); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB2, 0x00022020); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB3, 0x00022020); + } + /* No CCU for A405 */ + if (!adreno_is_a405(adreno_dev)) { + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_CTL_MARB_CCU0, 0x00000922); + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_CTL_MARB_CCU1, 0x00000922); + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_CTL_MARB_CCU2, 0x00000922); + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_CTL_MARB_CCU3, 0x00000922); + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU0, 0x00000000); + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU1, 0x00000000); + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU2, 0x00000000); + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU3, 0x00000000); + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_0, + 0x00000001); + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_1, + 0x00000001); + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_2, + 0x00000001); + kgsl_regwrite(device, + A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_3, + 0x00000001); + } + kgsl_regwrite(device, A4XX_RBBM_CLOCK_MODE_GPC, 0x02222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_GPC, 0x04100104); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_GPC, 0x00022222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_COM_DCOM, 0x00000022); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_COM_DCOM, 0x0000010F); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_COM_DCOM, 0x00000022); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM, 0x00222222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00004104); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000222); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_HLSQ, 0x00000000); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000); + /* + * Due to a HW timing issue, top level HW clock gating is causing + * register read/writes to be dropped in adreno a430. + * This timing issue started happening because of SP/TP power collapse. + * On targets that do not have SP/TP PC there is no timing issue. + * The HW timing issue could be fixed by + * a) disabling SP/TP power collapse + * b) or disabling HW clock gating. + * Disabling HW clock gating + NAP enabled combination has + * minimal power impact. So this option is chosen over disabling + * SP/TP power collapse. + * Revisions of A430 which chipid 2 and above do not have the issue. + */ + if (adreno_is_a430(adreno_dev) && + (ADRENO_CHIPID_PATCH(adreno_dev->chipid) < 2)) + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL, 0); + else + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA); + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2, 0); +} +/* * a4xx_regulator_enable() - Enable any necessary HW regulators * @adreno_dev: The adreno device pointer * @@ -212,8 +339,12 @@ static int a4xx_regulator_enable(struct adreno_device *adreno_dev) unsigned int reg; struct kgsl_device *device = KGSL_DEVICE(adreno_dev); - if (!(adreno_is_a430(adreno_dev) || adreno_is_a418(adreno_dev))) + if (!(adreno_is_a430(adreno_dev) || adreno_is_a418(adreno_dev))) { + /* Halt the sp_input_clk at HM level */ + kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL, 0x00000055); + a4xx_enable_hwcg(device); return 0; + } /* Set the default register values; set SW_COLLAPSE to 0 */ kgsl_regwrite(device, A4XX_RBBM_POWER_CNTL_IP, 0x778000); @@ -221,6 +352,13 @@ static int a4xx_regulator_enable(struct adreno_device *adreno_dev) udelay(5); kgsl_regread(device, A4XX_RBBM_POWER_STATUS, ®); } while (!(reg & SP_TP_PWR_ON)); + + /* Disable SP clock */ + kgsl_regrmw(device, A4XX_RBBM_CLOCK_CTL_IP, CNTL_IP_SW_COLLAPSE, 0); + /* Enable hardware clockgating */ + a4xx_enable_hwcg(device); + /* Enable SP clock */ + kgsl_regrmw(device, A4XX_RBBM_CLOCK_CTL_IP, CNTL_IP_SW_COLLAPSE, 1); return 0; } @@ -328,131 +466,6 @@ static void a4xx_pwrlevel_change_settings(struct adreno_device *adreno_dev, pre = 0; } -/* - * a4xx_enable_hwcg() - Program the clock control registers - * @device: The adreno device pointer - */ -static void a4xx_enable_hwcg(struct kgsl_device *device) -{ - struct adreno_device *adreno_dev = ADRENO_DEVICE(device); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_TP0, 0x02222202); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_TP1, 0x02222202); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_TP2, 0x02222202); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_TP3, 0x02222202); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_TP0, 0x00002222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_TP1, 0x00002222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_TP2, 0x00002222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_TP3, 0x00002222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_TP0, 0x0E739CE7); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_TP1, 0x0E739CE7); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_TP2, 0x0E739CE7); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_TP3, 0x0E739CE7); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_TP0, 0x00111111); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_TP1, 0x00111111); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_TP2, 0x00111111); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_TP3, 0x00111111); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP0, 0x22222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP1, 0x22222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP2, 0x22222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_SP3, 0x22222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP0, 0x00222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP1, 0x00222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP2, 0x00222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_SP3, 0x00222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_SP0, 0x00000104); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_SP1, 0x00000104); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_SP2, 0x00000104); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_SP3, 0x00000104); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_SP0, 0x00000081); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_SP1, 0x00000081); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_SP2, 0x00000081); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_SP3, 0x00000081); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_UCHE, 0x22222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_UCHE, 0x02222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL3_UCHE, 0x00000000); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL4_UCHE, 0x00000000); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_UCHE, 0x00004444); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_UCHE, 0x00001112); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_RB0, 0x22222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_RB1, 0x22222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_RB2, 0x22222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_RB3, 0x22222222); - /* Disable L1 clocking in A420 due to CCU issues with it */ - if (adreno_is_a420(adreno_dev)) { - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB0, 0x00002020); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB1, 0x00002020); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB2, 0x00002020); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB3, 0x00002020); - } else { - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB0, 0x00022020); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB1, 0x00022020); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB2, 0x00022020); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2_RB3, 0x00022020); - } - /* No CCU for A405 */ - if (!adreno_is_a405(adreno_dev)) { - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_CTL_MARB_CCU0, 0x00000922); - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_CTL_MARB_CCU1, 0x00000922); - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_CTL_MARB_CCU2, 0x00000922); - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_CTL_MARB_CCU3, 0x00000922); - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU0, 0x00000000); - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU1, 0x00000000); - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU2, 0x00000000); - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU3, 0x00000000); - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_0, - 0x00000001); - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_1, - 0x00000001); - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_2, - 0x00000001); - kgsl_regwrite(device, - A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_3, - 0x00000001); - } - kgsl_regwrite(device, A4XX_RBBM_CLOCK_MODE_GPC, 0x02222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_GPC, 0x04100104); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_GPC, 0x00022222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_COM_DCOM, 0x00000022); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_COM_DCOM, 0x0000010F); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_COM_DCOM, 0x00000022); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM, 0x00222222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00004104); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000222); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL_HLSQ , 0x00000000); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000); - /* - * Due to a HW timing issue, top level HW clock gating is causing - * register read/writes to be dropped in adreno a430. - * This timing issue started happening because of SP/TP power collapse. - * On targets that do not have SP/TP PC there is no timing issue. - * The HW timing issue could be fixed by - * a) disabling SP/TP power collapse - * b) or disabling HW clock gating. - * Disabling HW clock gating + NAP enabled combination has - * minimal power impact. So this option is chosen over disabling - * SP/TP power collapse. - * Revisions of A430 which chipid 2 and above do not have the issue. - */ - if (adreno_is_a430(adreno_dev) && - (ADRENO_CHIPID_PATCH(adreno_dev->chipid) < 2)) - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL, 0); - else - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA); - kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2, 0); -} - /** * a4xx_protect_init() - Initializes register protection on a4xx * @adreno_dev: Pointer to the device structure @@ -597,7 +610,6 @@ static void a4xx_start(struct adreno_device *adreno_dev) 0x00000441); } - a4xx_enable_hwcg(device); /* * For A420 set RBBM_CLOCK_DELAY_HLSQ.CGC_HLSQ_TP_EARLY_CYC >= 2 * due to timing issue with HLSQ_TP_CLK_EN diff --git a/drivers/gpu/msm/adreno_a5xx.c b/drivers/gpu/msm/adreno_a5xx.c index 0af11af851c3..1782d1d54946 100644 --- a/drivers/gpu/msm/adreno_a5xx.c +++ b/drivers/gpu/msm/adreno_a5xx.c @@ -440,7 +440,11 @@ static int a5xx_regulator_enable(struct adreno_device *adreno_dev) unsigned int ret; struct kgsl_device *device = KGSL_DEVICE(adreno_dev); if (!(adreno_is_a530(adreno_dev) || adreno_is_a540(adreno_dev))) { + /* Halt the sp_input_clk at HM level */ + kgsl_regwrite(device, A5XX_RBBM_CLOCK_CNTL, 0x00000055); a5xx_hwcg_set(adreno_dev, true); + /* Turn on sp_input_clk at HM level */ + kgsl_regrmw(device, A5XX_RBBM_CLOCK_CNTL, 3, 0); return 0; } diff --git a/drivers/gpu/msm/adreno_dispatch.c b/drivers/gpu/msm/adreno_dispatch.c index 5d3b2b8a7266..522c32743d3d 100644 --- a/drivers/gpu/msm/adreno_dispatch.c +++ b/drivers/gpu/msm/adreno_dispatch.c @@ -1814,7 +1814,7 @@ static int dispatcher_do_fault(struct adreno_device *adreno_dev) } } - if (!adreno_cmdqueue_is_empty(dispatch_q)) { + if (dispatch_q && !adreno_cmdqueue_is_empty(dispatch_q)) { cmdbatch = dispatch_q->cmd_q[dispatch_q->head]; trace_adreno_cmdbatch_fault(cmdbatch, fault); } diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index 6e9abc99bcc4..88581b079246 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -485,6 +485,7 @@ err_put_proc_priv: static void kgsl_mem_entry_detach_process(struct kgsl_mem_entry *entry) { unsigned int type; + int ret; if (entry == NULL) return; @@ -501,9 +502,14 @@ static void kgsl_mem_entry_detach_process(struct kgsl_mem_entry *entry) entry->priv->stats[type].cur -= entry->memdesc.size; spin_unlock(&entry->priv->mem_lock); - kgsl_mmu_unmap(entry->memdesc.pagetable, &entry->memdesc); - - kgsl_mem_entry_untrack_gpuaddr(entry->priv, entry); + ret = kgsl_mmu_unmap(entry->memdesc.pagetable, &entry->memdesc); + /* + * Do not free the gpuaddr/size if unmap fails. Because if we try + * to map this range in future, the iommu driver will throw + * a BUG_ON() because it feels we are overwriting a mapping. + */ + if (ret == 0) + kgsl_mem_entry_untrack_gpuaddr(entry->priv, entry); kgsl_process_private_put(entry->priv); diff --git a/drivers/gpu/msm/kgsl_mmu.c b/drivers/gpu/msm/kgsl_mmu.c index 4371c9a1b87e..ba564b2851f9 100644 --- a/drivers/gpu/msm/kgsl_mmu.c +++ b/drivers/gpu/msm/kgsl_mmu.c @@ -450,24 +450,23 @@ int kgsl_mmu_unmap(struct kgsl_pagetable *pagetable, struct kgsl_memdesc *memdesc) { + int ret = 0; + if (memdesc->size == 0) return -EINVAL; if (PT_OP_VALID(pagetable, mmu_unmap)) { - int ret; uint64_t size; size = kgsl_memdesc_footprint(memdesc); ret = pagetable->pt_ops->mmu_unmap(pagetable, memdesc); - if (ret) - return ret; atomic_dec(&pagetable->stats.entries); atomic_long_sub(size, &pagetable->stats.mapped); } - return 0; + return ret; } EXPORT_SYMBOL(kgsl_mmu_unmap); diff --git a/drivers/gpu/msm/kgsl_sharedmem.c b/drivers/gpu/msm/kgsl_sharedmem.c index 73edc3f7e146..72895c18119f 100644 --- a/drivers/gpu/msm/kgsl_sharedmem.c +++ b/drivers/gpu/msm/kgsl_sharedmem.c @@ -807,8 +807,16 @@ void kgsl_sharedmem_free(struct kgsl_memdesc *memdesc) return; if (memdesc->gpuaddr) { - kgsl_mmu_unmap(memdesc->pagetable, memdesc); - kgsl_mmu_put_gpuaddr(memdesc->pagetable, memdesc); + int ret = 0; + + ret = kgsl_mmu_unmap(memdesc->pagetable, memdesc); + /* + * Do not free the gpuaddr/size if unmap fails. Because if we + * try to map this range in future, the iommu driver will throw + * a BUG_ON() because it feels we are overwriting a mapping. + */ + if (ret == 0) + kgsl_mmu_put_gpuaddr(memdesc->pagetable, memdesc); } if (memdesc->ops && memdesc->ops->free) diff --git a/drivers/hid/hid-apple.c b/drivers/hid/hid-apple.c index 884d82f9190e..37e8b61b5c98 100644 --- a/drivers/hid/hid-apple.c +++ b/drivers/hid/hid-apple.c @@ -440,6 +440,9 @@ static const struct hid_device_id apple_devices[] = { .driver_data = APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_ANSI), .driver_data = APPLE_HAS_FN }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, + USB_DEVICE_ID_APPLE_ALU_ANSI), + .driver_data = APPLE_HAS_FN }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_ISO), .driver_data = APPLE_HAS_FN | APPLE_ISO_KEYBOARD }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_JIS), diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index ec791e169f8f..9dc9f93f4e36 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -1754,6 +1754,8 @@ static const struct hid_device_id hid_have_special_driver[] = { { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_MINI_ISO) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_MINI_JIS) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_ANSI) }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, + USB_DEVICE_ID_APPLE_ALU_ANSI) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_ISO) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_ALU_JIS) }, { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_GEYSER4_HF_ANSI) }, diff --git a/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c b/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c index e8229216fcd3..206941708141 100644 --- a/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c +++ b/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c @@ -492,33 +492,25 @@ static int synaptics_i2c_change_pipe_owner( static void synaptics_secure_touch_init(struct synaptics_rmi4_data *data) { - int ret = 0; data->st_initialized = 0; init_completion(&data->st_powerdown); init_completion(&data->st_irq_processed); /* Get clocks */ data->core_clk = clk_get(data->pdev->dev.parent, "core_clk"); if (IS_ERR(data->core_clk)) { - ret = PTR_ERR(data->core_clk); - dev_err(data->pdev->dev.parent, - "%s: error on clk_get(core_clk):%d\n", __func__, ret); - return; + data->core_clk = NULL; + dev_warn(data->pdev->dev.parent, + "%s: core_clk is not defined\n", __func__); } data->iface_clk = clk_get(data->pdev->dev.parent, "iface_clk"); if (IS_ERR(data->iface_clk)) { - ret = PTR_ERR(data->iface_clk); - dev_err(data->pdev->dev.parent, - "%s: error on clk_get(iface_clk):%d\n", __func__, ret); - goto err_iface_clk; + data->iface_clk = NULL; + dev_warn(data->pdev->dev.parent, + "%s: iface_clk is not defined\n", __func__); } data->st_initialized = 1; - return; - -err_iface_clk: - clk_put(data->core_clk); - data->core_clk = NULL; } static void synaptics_secure_touch_notify(struct synaptics_rmi4_data *rmi4_data) { diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c index 6a1b385c3d8b..e4cee1fa4ffc 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c @@ -1052,6 +1052,25 @@ static int msm_csiphy_init(struct csiphy_device *csiphy_dev) CDBG("%s:%d called\n", __func__, __LINE__); + rc = msm_camera_config_vreg(&csiphy_dev->pdev->dev, + csiphy_dev->csiphy_vreg, + csiphy_dev->regulator_count, NULL, 0, + &csiphy_dev->csiphy_reg_ptr[0], 1); + if (rc < 0) { + pr_err("%s:%d csiphy config_vreg failed\n", + __func__, __LINE__); + goto csiphy_resource_fail; + } + rc = msm_camera_enable_vreg(&csiphy_dev->pdev->dev, + csiphy_dev->csiphy_vreg, + csiphy_dev->regulator_count, NULL, 0, + &csiphy_dev->csiphy_reg_ptr[0], 1); + if (rc < 0) { + pr_err("%s:%d csiphy enable_vreg failed\n", + __func__, __LINE__); + goto top_vreg_enable_failed; + } + rc = msm_camera_clk_enable(&csiphy_dev->pdev->dev, csiphy_dev->csiphy_clk_info, csiphy_dev->csiphy_clk, csiphy_dev->num_clk, true); @@ -1088,6 +1107,11 @@ static int msm_csiphy_init(struct csiphy_device *csiphy_dev) csiphy_dev->csiphy_state = CSIPHY_POWER_UP; return 0; +top_vreg_enable_failed: + msm_camera_config_vreg(&csiphy_dev->pdev->dev, + csiphy_dev->csiphy_vreg, + csiphy_dev->regulator_count, NULL, 0, + &csiphy_dev->csiphy_reg_ptr[0], 0); csiphy_resource_fail: if (cam_config_ahb_clk(NULL, 0, CAM_AHB_CLIENT_CSIPHY, CAM_AHB_SUSPEND_VOTE) < 0) @@ -1128,6 +1152,24 @@ static int msm_csiphy_init(struct csiphy_device *csiphy_dev) pr_err("%s: failed to vote for AHB\n", __func__); return rc; } + rc = msm_camera_config_vreg(&csiphy_dev->pdev->dev, + csiphy_dev->csiphy_vreg, + csiphy_dev->regulator_count, NULL, 0, + &csiphy_dev->csiphy_reg_ptr[0], 1); + if (rc < 0) { + pr_err("%s:%d csiphy config_vreg failed\n", + __func__, __LINE__); + goto csiphy_resource_fail; + } + rc = msm_camera_enable_vreg(&csiphy_dev->pdev->dev, + csiphy_dev->csiphy_vreg, + csiphy_dev->regulator_count, NULL, 0, + &csiphy_dev->csiphy_reg_ptr[0], 1); + if (rc < 0) { + pr_err("%s:%d csiphy enable_vreg failed\n", + __func__, __LINE__); + goto top_vreg_enable_failed; + } rc = msm_camera_clk_enable(&csiphy_dev->pdev->dev, csiphy_dev->csiphy_clk_info, csiphy_dev->csiphy_clk, @@ -1139,7 +1181,7 @@ static int msm_csiphy_init(struct csiphy_device *csiphy_dev) csiphy_dev->ref_count--; goto csiphy_resource_fail; } - CDBG("%s:%d called\n", __func__, __LINE__); + CDBG("%s:%d clk enable success\n", __func__, __LINE__); if (csiphy_dev->csiphy_3phase == CSI_3PHASE_HW) msm_csiphy_3ph_reset(csiphy_dev); @@ -1161,7 +1203,11 @@ static int msm_csiphy_init(struct csiphy_device *csiphy_dev) csiphy_dev->hw_version); csiphy_dev->csiphy_state = CSIPHY_POWER_UP; return 0; - +top_vreg_enable_failed: + msm_camera_config_vreg(&csiphy_dev->pdev->dev, + csiphy_dev->csiphy_vreg, + csiphy_dev->regulator_count, NULL, 0, + &csiphy_dev->csiphy_reg_ptr[0], 0); csiphy_resource_fail: if (cam_config_ahb_clk(NULL, 0, CAM_AHB_CLIENT_CSIPHY, CAM_AHB_SUSPEND_VOTE) < 0) @@ -1275,6 +1321,14 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg) csiphy_dev->csiphy_3p_clk, 2, false); } + msm_camera_enable_vreg(&csiphy_dev->pdev->dev, + csiphy_dev->csiphy_vreg, + csiphy_dev->regulator_count, NULL, 0, + &csiphy_dev->csiphy_reg_ptr[0], 0); + msm_camera_config_vreg(&csiphy_dev->pdev->dev, + csiphy_dev->csiphy_vreg, csiphy_dev->regulator_count, + NULL, 0, &csiphy_dev->csiphy_reg_ptr[0], 0); + csiphy_dev->csiphy_state = CSIPHY_POWER_DOWN; if (cam_config_ahb_clk(NULL, 0, CAM_AHB_CLIENT_CSIPHY, @@ -1386,6 +1440,13 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg) csiphy_dev->csiphy_3p_clk, 2, false); } + msm_camera_enable_vreg(&csiphy_dev->pdev->dev, + csiphy_dev->csiphy_vreg, csiphy_dev->regulator_count, + NULL, 0, &csiphy_dev->csiphy_reg_ptr[0], 0); + msm_camera_config_vreg(&csiphy_dev->pdev->dev, + csiphy_dev->csiphy_vreg, csiphy_dev->regulator_count, + NULL, 0, &csiphy_dev->csiphy_reg_ptr[0], 0); + csiphy_dev->csiphy_state = CSIPHY_POWER_DOWN; if (cam_config_ahb_clk(NULL, 0, CAM_AHB_CLIENT_CSIPHY, @@ -1711,6 +1772,14 @@ static int csiphy_probe(struct platform_device *pdev) goto csiphy_no_resource; } + rc = msm_camera_get_dt_vreg_data(pdev->dev.of_node, + &(new_csiphy_dev->csiphy_vreg), + &(new_csiphy_dev->regulator_count)); + if (rc < 0) { + pr_err("%s: get vreg data from dtsi fail\n", __func__); + rc = -EFAULT; + goto csiphy_no_resource; + } /* ToDo: Enable 3phase clock for dynamic clock enable/disable */ rc = msm_csiphy_get_clk_info(new_csiphy_dev, pdev); if (rc < 0) { @@ -1781,7 +1850,7 @@ static int msm_csiphy_exit(struct platform_device *pdev) &csiphy_dev->csiphy_all_clk, csiphy_dev->num_all_clk); - msm_camera_put_reg_base(pdev, csiphy_dev->base, "csid", true); + msm_camera_put_reg_base(pdev, csiphy_dev->base, "csiphy", true); if (csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V30) { msm_camera_put_reg_base(pdev, csiphy_dev->clk_mux_base, "csiphy_clk_mux", true); diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h index aba88da1157e..70462dcd3b12 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h +++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h @@ -20,6 +20,7 @@ #include <media/msm_cam_sensor.h> #include "msm_sd.h" #include "msm_camera_io_util.h" +#include "msm_camera_dt_util.h" #include "cam_soc_api.h" #define MAX_CSIPHY 3 @@ -183,6 +184,9 @@ struct csiphy_device { uint8_t num_irq_registers; uint32_t csiphy_sof_debug; uint32_t csiphy_sof_debug_count; + struct camera_vreg_t *csiphy_vreg; + struct regulator *csiphy_reg_ptr[MAX_REGULATOR]; + int32_t regulator_count; }; #define VIDIOC_MSM_CSIPHY_RELEASE \ diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c index 041a8219e145..594bac6c5902 100644 --- a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c +++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c @@ -41,8 +41,12 @@ #define ROT_HW_ACQUIRE_TIMEOUT_IN_MS 100 /* default pixel per clock ratio */ -#define ROT_PIXEL_PER_CLK_NUMERATOR 4 -#define ROT_PIXEL_PER_CLK_DENOMINATOR 1 +#define ROT_PIXEL_PER_CLK_NUMERATOR 36 +#define ROT_PIXEL_PER_CLK_DENOMINATOR 10 +#define ROT_FUDGE_FACTOR_NUMERATOR 105 +#define ROT_FUDGE_FACTOR_DENOMINATOR 100 +#define ROT_OVERHEAD_NUMERATOR 27 +#define ROT_OVERHEAD_DENOMINATOR 10000 /* * Max rotator hw blocks possible. Used for upper array limits instead of @@ -998,12 +1002,33 @@ static u32 sde_rotator_calc_buf_bw(struct sde_mdp_format_params *fmt, return bw; } +static int sde_rotator_find_max_fps(struct sde_rot_mgr *mgr) +{ + struct sde_rot_file_private *priv; + struct sde_rot_perf *perf; + int max_fps = 0; + + list_for_each_entry(priv, &mgr->file_list, list) { + list_for_each_entry(perf, &priv->perf_list, list) { + if (perf->config.frame_rate > max_fps) + max_fps = perf->config.frame_rate; + } + } + + SDEROT_DBG("Max fps:%d\n", max_fps); + return max_fps; +} + static int sde_rotator_calc_perf(struct sde_rot_mgr *mgr, struct sde_rot_perf *perf) { struct sde_rotation_config *config = &perf->config; u32 read_bw, write_bw; struct sde_mdp_format_params *in_fmt, *out_fmt; + struct sde_rotator_device *rot_dev; + int max_fps; + + rot_dev = platform_get_drvdata(mgr->pdev); in_fmt = sde_get_format_params(config->input.format); if (!in_fmt) { @@ -1016,17 +1041,44 @@ static int sde_rotator_calc_perf(struct sde_rot_mgr *mgr, return -EINVAL; } + /* + * rotator processes 4 pixels per clock, but the actual throughtput + * is 3.6. We also need to take into account for overhead time. Final + * equation is: + * W x H / throughput / (1/fps - overhead) * fudge_factor + */ + max_fps = sde_rotator_find_max_fps(mgr); perf->clk_rate = config->input.width * config->input.height; - perf->clk_rate *= config->frame_rate; - /* rotator processes 4 pixels per clock */ perf->clk_rate = (perf->clk_rate * mgr->pixel_per_clk.denom) / mgr->pixel_per_clk.numer; + perf->clk_rate *= max_fps; + perf->clk_rate = (perf->clk_rate * mgr->fudge_factor.numer) / + mgr->fudge_factor.denom; + perf->clk_rate *= mgr->overhead.denom; + + /* + * check for override overhead default value + */ + if (rot_dev->min_overhead_us > (mgr->overhead.numer * 100)) + perf->clk_rate = DIV_ROUND_UP_ULL(perf->clk_rate, + (mgr->overhead.denom - max_fps * + (rot_dev->min_overhead_us / 100))); + else + perf->clk_rate = DIV_ROUND_UP_ULL(perf->clk_rate, + (mgr->overhead.denom - max_fps * + mgr->overhead.numer)); + + /* + * check for Override clock calcualtion + */ + if (rot_dev->min_rot_clk > perf->clk_rate) + perf->clk_rate = rot_dev->min_rot_clk; read_bw = sde_rotator_calc_buf_bw(in_fmt, config->input.width, - config->input.height, config->frame_rate); + config->input.height, max_fps); write_bw = sde_rotator_calc_buf_bw(out_fmt, config->output.width, - config->output.height, config->frame_rate); + config->output.height, max_fps); read_bw = sde_apply_comp_ratio_factor(read_bw, in_fmt, &config->input.comp_ratio); @@ -1035,13 +1087,22 @@ static int sde_rotator_calc_perf(struct sde_rot_mgr *mgr, perf->bw = read_bw + write_bw; + /* + * check for override bw calculation + */ + if (rot_dev->min_bw > perf->bw) + perf->bw = rot_dev->min_bw; + perf->rdot_limit = sde_mdp_get_ot_limit( config->input.width, config->input.height, - config->input.format, config->frame_rate, true); + config->input.format, max_fps, true); perf->wrot_limit = sde_mdp_get_ot_limit( config->input.width, config->input.height, - config->input.format, config->frame_rate, false); + config->input.format, max_fps, false); + SDEROT_DBG("clk:%lu, rdBW:%d, wrBW:%d, rdOT:%d, wrOT:%d\n", + perf->clk_rate, read_bw, write_bw, perf->rdot_limit, + perf->wrot_limit); return 0; } @@ -1747,16 +1808,9 @@ static int sde_rotator_open_session(struct sde_rot_mgr *mgr, config.session_id = session_id; perf->config = config; - perf->last_wb_idx = -1; + perf->last_wb_idx = 0; INIT_LIST_HEAD(&perf->list); - - ret = sde_rotator_calc_perf(mgr, perf); - if (ret) { - SDEROT_ERR("error setting the session %d\n", ret); - goto copy_user_err; - } - list_add(&perf->list, &private->perf_list); ret = sde_rotator_resource_ctrl(mgr, true); @@ -1777,25 +1831,17 @@ static int sde_rotator_open_session(struct sde_rot_mgr *mgr, goto enable_clk_err; } - ret = sde_rotator_update_perf(mgr); - if (ret) { - SDEROT_ERR("fail to open session, not enough clk/bw\n"); - goto perf_err; - } SDEROT_DBG("open session id=%u in{%u,%u}f:%u out{%u,%u}f:%u\n", config.session_id, config.input.width, config.input.height, config.input.format, config.output.width, config.output.height, config.output.format); goto done; -perf_err: - sde_rotator_clk_ctrl(mgr, false); enable_clk_err: update_clk_err: sde_rotator_resource_ctrl(mgr, false); resource_err: list_del_init(&perf->list); -copy_user_err: devm_kfree(&mgr->pdev->dev, perf->work_distribution); alloc_err: devm_kfree(&mgr->pdev->dev, perf); @@ -1867,11 +1913,23 @@ static int sde_rotator_config_session(struct sde_rot_mgr *mgr, } ret = sde_rotator_update_perf(mgr); + if (ret) { + SDEROT_ERR("error in updating perf: %d\n", ret); + goto done; + } + + ret = sde_rotator_update_clk(mgr); + if (ret) { + SDEROT_ERR("error in updating the rotator clk: %d\n", ret); + goto done; + } - SDEROT_DBG("reconfig session id=%u in{%u,%u}f:%u out{%u,%u}f:%u\n", + SDEROT_DBG( + "reconfig session id=%u in{%u,%u}f:%u out{%u,%u}f:%u fps:%d clk:%lu, bw:%llu\n", config->session_id, config->input.width, config->input.height, config->input.format, config->output.width, - config->output.height, config->output.format); + config->output.height, config->output.format, + config->frame_rate, perf->clk_rate, perf->bw); done: return ret; } @@ -2386,6 +2444,10 @@ int sde_rotator_core_init(struct sde_rot_mgr **pmgr, mgr->queue_count = 1; mgr->pixel_per_clk.numer = ROT_PIXEL_PER_CLK_NUMERATOR; mgr->pixel_per_clk.denom = ROT_PIXEL_PER_CLK_DENOMINATOR; + mgr->fudge_factor.numer = ROT_FUDGE_FACTOR_NUMERATOR; + mgr->fudge_factor.denom = ROT_FUDGE_FACTOR_DENOMINATOR; + mgr->overhead.numer = ROT_OVERHEAD_NUMERATOR; + mgr->overhead.denom = ROT_OVERHEAD_DENOMINATOR; mutex_init(&mgr->lock); atomic_set(&mgr->device_suspended, 0); diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.h b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.h index aa17341de7c2..781b03e1b974 100644 --- a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.h +++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.h @@ -281,6 +281,8 @@ struct sde_rot_mgr { u32 hwacquire_timeout; struct sde_mult_factor pixel_per_clk; + struct sde_mult_factor fudge_factor; + struct sde_mult_factor overhead; int (*ops_config_hw)(struct sde_rot_hw_resource *hw, struct sde_rot_entry *entry); diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_debug.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_debug.c index c609dbd2036e..94223b557990 100644 --- a/drivers/media/platform/msm/sde/rotator/sde_rotator_debug.c +++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_debug.c @@ -914,6 +914,34 @@ static int sde_rotator_evtlog_create_debugfs( return 0; } + +static int sde_rotator_perf_create_debugfs( + struct sde_rotator_device *rot_dev, + struct dentry *debugfs_root) +{ + rot_dev->perf_root = debugfs_create_dir("perf", debugfs_root); + if (IS_ERR_OR_NULL(rot_dev->perf_root)) { + pr_err("debugfs_create_dir for perf failed, error %ld\n", + PTR_ERR(rot_dev->perf_root)); + rot_dev->perf_root = NULL; + return -ENODEV; + } + + rot_dev->min_rot_clk = 0; + debugfs_create_u32("min_rot_clk", S_IRUGO | S_IWUSR, + rot_dev->perf_root, &rot_dev->min_rot_clk); + + rot_dev->min_bw = 0; + debugfs_create_u32("min_bw", S_IRUGO | S_IWUSR, + rot_dev->perf_root, &rot_dev->min_bw); + + rot_dev->min_overhead_us = 0; + debugfs_create_u32("min_overhead_us", S_IRUGO | S_IWUSR, + rot_dev->perf_root, &rot_dev->min_overhead_us); + + return 0; +} + /* * struct sde_rotator_stat_ops - processed statistics file operations */ @@ -1006,6 +1034,12 @@ struct dentry *sde_rotator_create_debugfs( return NULL; } + if (sde_rotator_perf_create_debugfs(rot_dev, debugfs_root)) { + SDEROT_ERR("fail create perf debugfs\n"); + debugfs_remove_recursive(debugfs_root); + return NULL; + } + return debugfs_root; } diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c index d34623a531ba..930b18abd71b 100644 --- a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c +++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c @@ -546,22 +546,8 @@ static struct vb2_mem_ops sde_rotator_vb2_mem_ops = { static int sde_rotator_s_ctx_ctrl(struct sde_rotator_ctx *ctx, s32 *ctx_ctrl, struct v4l2_ctrl *ctrl) { - struct sde_rotator_device *rot_dev = ctx->rot_dev; - struct sde_rotation_config config; - s32 prev_val; - int ret; - - prev_val = *ctx_ctrl; *ctx_ctrl = ctrl->val; - sde_rotator_get_config_from_ctx(ctx, &config); - ret = sde_rotator_session_config(rot_dev->mgr, ctx->private, &config); - if (ret) { - SDEDEV_WARN(rot_dev->dev, "fail %s:%d s:%d\n", - ctrl->name, ctrl->val, ctx->session_id); - *ctx_ctrl = prev_val; - } - - return ret; + return 0; } /* @@ -1213,7 +1199,6 @@ static int sde_rotator_s_fmt_vid_cap(struct file *file, { struct sde_rotator_ctx *ctx = sde_rotator_ctx_from_fh(fh); struct sde_rotator_device *rot_dev = ctx->rot_dev; - struct sde_rotation_config config; int ret; ret = sde_rotator_try_fmt_vid_cap(file, fh, f); @@ -1235,12 +1220,6 @@ static int sde_rotator_s_fmt_vid_cap(struct file *file, f->fmt.pix.field, f->fmt.pix.width, f->fmt.pix.height); - /* configure hal to current input/output setting */ - sde_rot_mgr_lock(rot_dev->mgr); - sde_rotator_get_config_from_ctx(ctx, &config); - sde_rotator_session_config(rot_dev->mgr, ctx->private, &config); - sde_rot_mgr_unlock(rot_dev->mgr); - return 0; } @@ -1524,7 +1503,6 @@ static int sde_rotator_s_crop(struct file *file, void *fh, { struct sde_rotator_ctx *ctx = sde_rotator_ctx_from_fh(fh); struct sde_rotator_device *rot_dev = ctx->rot_dev; - struct sde_rotation_config config; struct sde_rotation_item item; struct v4l2_rect rect; @@ -1597,12 +1575,6 @@ static int sde_rotator_s_crop(struct file *file, void *fh, return -EINVAL; } - /* configure hal to current input/output setting */ - sde_rot_mgr_lock(rot_dev->mgr); - sde_rotator_get_config_from_ctx(ctx, &config); - sde_rotator_session_config(rot_dev->mgr, ctx->private, &config); - sde_rot_mgr_unlock(rot_dev->mgr); - return 0; } @@ -2336,6 +2308,9 @@ static int sde_rotator_probe(struct platform_device *pdev) rot_dev->early_submit = SDE_ROTATOR_EARLY_SUBMIT; rot_dev->fence_timeout = SDE_ROTATOR_FENCE_TIMEOUT; rot_dev->streamoff_timeout = SDE_ROTATOR_STREAM_OFF_TIMEOUT; + rot_dev->min_rot_clk = 0; + rot_dev->min_bw = 0; + rot_dev->min_overhead_us = 0; rot_dev->drvdata = sde_rotator_get_drv_data(&pdev->dev); rot_dev->pdev = pdev; diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.h b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.h index fd247d10128c..f3c904817296 100644 --- a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.h +++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.h @@ -160,6 +160,9 @@ struct sde_rotator_statistics { * @session_id: Next context session identifier * @fence_timeout: Timeout value in msec for fence wait * @streamoff_timeout: Timeout value in msec for stream off + * @min_rot_clk: Override the minimum rotator clock from perf calculation + * @min_bw: Override the minimum bandwidth from perf calculation + * @min_overhead_us: Override the minimum overhead in us from perf calculation * @debugfs_root: Pointer to debugfs directory entry. * @stats: placeholder for rotator statistics */ @@ -177,8 +180,12 @@ struct sde_rotator_device { u32 session_id; u32 fence_timeout; u32 streamoff_timeout; + u32 min_rot_clk; + u32 min_bw; + u32 min_overhead_us; struct sde_rotator_statistics stats; struct dentry *debugfs_root; + struct dentry *perf_root; }; static inline diff --git a/drivers/media/platform/msm/vidc/msm_vidc_common.c b/drivers/media/platform/msm/vidc/msm_vidc_common.c index f0a3875a8f28..40643239712f 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_common.c +++ b/drivers/media/platform/msm/vidc/msm_vidc_common.c @@ -1737,19 +1737,6 @@ static struct vb2_buffer *get_vb_from_device_addr(struct buf_queue *bufq, return vb; } -static void msm_vidc_try_suspend(struct msm_vidc_inst *inst) -{ - bool batch_mode; - - batch_mode = msm_comm_g_ctrl_for_id(inst, V4L2_CID_VIDC_QBUF_MODE) - == V4L2_VIDC_QBUF_BATCHED; - if (batch_mode) { - dprintk(VIDC_DBG, - "Trying to suspend Venus after finishing Batch\n"); - msm_comm_suspend(inst->core->id); - } -} - static void handle_ebd(enum hal_command_response cmd, void *data) { struct msm_vidc_cb_data_done *response = data; @@ -1821,8 +1808,6 @@ static void handle_ebd(enum hal_command_response cmd, void *data) msm_vidc_debugfs_update(inst, MSM_VIDC_DEBUGFS_EVENT_EBD); } - msm_vidc_try_suspend(inst); - put_inst(inst); } @@ -2121,7 +2106,6 @@ static void handle_fbd(enum hal_command_response cmd, void *data) msm_vidc_debugfs_update(inst, MSM_VIDC_DEBUGFS_EVENT_FBD); } - msm_vidc_try_suspend(inst); err_handle_fbd: put_inst(inst); } diff --git a/drivers/mfd/wcd934x-regmap.c b/drivers/mfd/wcd934x-regmap.c index b102264ca8fd..02ddf3225af8 100644 --- a/drivers/mfd/wcd934x-regmap.c +++ b/drivers/mfd/wcd934x-regmap.c @@ -1872,6 +1872,10 @@ static bool wcd934x_is_volatile_register(struct device *dev, unsigned int reg) case WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_1: case WCD934X_CPE_SS_CPAR_CTL: case WCD934X_CPE_SS_STATUS: + case WCD934X_CODEC_RPM_RST_CTL: + case WCD934X_SIDO_NEW_VOUT_A_STARTUP: + case WCD934X_SIDO_NEW_VOUT_D_STARTUP: + case WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL: return true; } diff --git a/drivers/net/usb/cdc_ncm.c b/drivers/net/usb/cdc_ncm.c index 8c2bb77db049..b11fe09552bf 100644 --- a/drivers/net/usb/cdc_ncm.c +++ b/drivers/net/usb/cdc_ncm.c @@ -945,8 +945,6 @@ EXPORT_SYMBOL_GPL(cdc_ncm_select_altsetting); static int cdc_ncm_bind(struct usbnet *dev, struct usb_interface *intf) { - int ret; - /* MBIM backwards compatible function? */ if (cdc_ncm_select_altsetting(intf) != CDC_NCM_COMM_ALTSETTING_NCM) return -ENODEV; @@ -955,16 +953,7 @@ static int cdc_ncm_bind(struct usbnet *dev, struct usb_interface *intf) * Additionally, generic NCM devices are assumed to accept arbitrarily * placed NDP. */ - ret = cdc_ncm_bind_common(dev, intf, CDC_NCM_DATA_ALTSETTING_NCM, 0); - - /* - * We should get an event when network connection is "connected" or - * "disconnected". Set network connection in "disconnected" state - * (carrier is OFF) during attach, so the IP network stack does not - * start IPv6 negotiation and more. - */ - usbnet_link_change(dev, 0, 0); - return ret; + return cdc_ncm_bind_common(dev, intf, CDC_NCM_DATA_ALTSETTING_NCM, 0); } static void cdc_ncm_align_tail(struct sk_buff *skb, size_t modulus, size_t remainder, size_t max) @@ -1547,7 +1536,8 @@ static void cdc_ncm_status(struct usbnet *dev, struct urb *urb) static const struct driver_info cdc_ncm_info = { .description = "CDC NCM", - .flags = FLAG_POINTTOPOINT | FLAG_NO_SETINT | FLAG_MULTI_PACKET, + .flags = FLAG_POINTTOPOINT | FLAG_NO_SETINT | FLAG_MULTI_PACKET + | FLAG_LINK_INTR, .bind = cdc_ncm_bind, .unbind = cdc_ncm_unbind, .manage_power = usbnet_manage_power, @@ -1560,7 +1550,7 @@ static const struct driver_info cdc_ncm_info = { static const struct driver_info wwan_info = { .description = "Mobile Broadband Network Device", .flags = FLAG_POINTTOPOINT | FLAG_NO_SETINT | FLAG_MULTI_PACKET - | FLAG_WWAN, + | FLAG_LINK_INTR | FLAG_WWAN, .bind = cdc_ncm_bind, .unbind = cdc_ncm_unbind, .manage_power = usbnet_manage_power, @@ -1573,7 +1563,7 @@ static const struct driver_info wwan_info = { static const struct driver_info wwan_noarp_info = { .description = "Mobile Broadband Network Device (NO ARP)", .flags = FLAG_POINTTOPOINT | FLAG_NO_SETINT | FLAG_MULTI_PACKET - | FLAG_WWAN | FLAG_NOARP, + | FLAG_LINK_INTR | FLAG_WWAN | FLAG_NOARP, .bind = cdc_ncm_bind, .unbind = cdc_ncm_unbind, .manage_power = usbnet_manage_power, diff --git a/drivers/net/wireless/ath/wil6210/debugfs.c b/drivers/net/wireless/ath/wil6210/debugfs.c index ce115c98a72f..d3e420f1b26b 100644 --- a/drivers/net/wireless/ath/wil6210/debugfs.c +++ b/drivers/net/wireless/ath/wil6210/debugfs.c @@ -1583,6 +1583,32 @@ static const struct file_operations fops_fw_capabilities = { .llseek = seq_lseek, }; +/*---------FW version------------*/ +static int wil_fw_version_debugfs_show(struct seq_file *s, void *data) +{ + struct wil6210_priv *wil = s->private; + + if (wil->fw_version[0]) + seq_printf(s, "%s\n", wil->fw_version); + else + seq_puts(s, "N/A\n"); + + return 0; +} + +static int wil_fw_version_seq_open(struct inode *inode, struct file *file) +{ + return single_open(file, wil_fw_version_debugfs_show, + inode->i_private); +} + +static const struct file_operations fops_fw_version = { + .open = wil_fw_version_seq_open, + .release = single_release, + .read = seq_read, + .llseek = seq_lseek, +}; + /*----------------*/ static void wil6210_debugfs_init_blobs(struct wil6210_priv *wil, struct dentry *dbg) @@ -1634,6 +1660,7 @@ static const struct { {"led_cfg", S_IRUGO | S_IWUSR, &fops_led_cfg}, {"led_blink_time", S_IRUGO | S_IWUSR, &fops_led_blink_time}, {"fw_capabilities", S_IRUGO, &fops_fw_capabilities}, + {"fw_version", S_IRUGO, &fops_fw_version}, }; static void wil6210_debugfs_init_files(struct wil6210_priv *wil, @@ -1674,7 +1701,6 @@ static void wil6210_debugfs_init_isr(struct wil6210_priv *wil, static const struct dbg_off dbg_wil_off[] = { WIL_FIELD(privacy, S_IRUGO, doff_u32), WIL_FIELD(status[0], S_IRUGO | S_IWUSR, doff_ulong), - WIL_FIELD(fw_version, S_IRUGO, doff_u32), WIL_FIELD(hw_version, S_IRUGO, doff_x32), WIL_FIELD(recovery_count, S_IRUGO, doff_u32), WIL_FIELD(ap_isolate, S_IRUGO, doff_u32), diff --git a/drivers/net/wireless/ath/wil6210/fw.h b/drivers/net/wireless/ath/wil6210/fw.h index c3191c61832c..2f2b910501ba 100644 --- a/drivers/net/wireless/ath/wil6210/fw.h +++ b/drivers/net/wireless/ath/wil6210/fw.h @@ -102,6 +102,9 @@ struct wil_fw_record_verify { /* type == wil_fw_verify */ /* file header * First record of every file */ +/* the FW version prefix in the comment */ +#define WIL_FW_VERSION_PREFIX "FW version: " +#define WIL_FW_VERSION_PREFIX_LEN (sizeof(WIL_FW_VERSION_PREFIX) - 1) struct wil_fw_record_file_header { __le32 signature ; /* Wilocity signature */ __le32 reserved; diff --git a/drivers/net/wireless/ath/wil6210/fw_inc.c b/drivers/net/wireless/ath/wil6210/fw_inc.c index 3860238840ba..8f40eb301924 100644 --- a/drivers/net/wireless/ath/wil6210/fw_inc.c +++ b/drivers/net/wireless/ath/wil6210/fw_inc.c @@ -223,6 +223,13 @@ static int fw_handle_file_header(struct wil6210_priv *wil, const void *data, wil_hex_dump_fw("", DUMP_PREFIX_OFFSET, 16, 1, d->comment, sizeof(d->comment), true); + if (!memcmp(d->comment, WIL_FW_VERSION_PREFIX, + WIL_FW_VERSION_PREFIX_LEN)) + memcpy(wil->fw_version, + d->comment + WIL_FW_VERSION_PREFIX_LEN, + min(sizeof(d->comment) - WIL_FW_VERSION_PREFIX_LEN, + sizeof(wil->fw_version) - 1)); + return 0; } diff --git a/drivers/net/wireless/ath/wil6210/main.c b/drivers/net/wireless/ath/wil6210/main.c index 88dfb93d0f3d..a509841c3187 100644 --- a/drivers/net/wireless/ath/wil6210/main.c +++ b/drivers/net/wireless/ath/wil6210/main.c @@ -892,6 +892,7 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw) WIL_FW2_NAME); wil_halt_cpu(wil); + memset(wil->fw_version, 0, sizeof(wil->fw_version)); /* Loading f/w from the file */ rc = wil_request_firmware(wil, WIL_FW_NAME, true); if (rc) diff --git a/drivers/net/wireless/ath/wil6210/netdev.c b/drivers/net/wireless/ath/wil6210/netdev.c index 81a4c6a684f5..f4fca9d4eedf 100644 --- a/drivers/net/wireless/ath/wil6210/netdev.c +++ b/drivers/net/wireless/ath/wil6210/netdev.c @@ -222,6 +222,8 @@ int wil_if_add(struct wil6210_priv *wil) wil_dbg_misc(wil, "entered"); + strlcpy(wiphy->fw_version, wil->fw_version, sizeof(wiphy->fw_version)); + rc = wiphy_register(wiphy); if (rc < 0) { wil_err(wil, "failed to register wiphy, err %d\n", rc); diff --git a/drivers/net/wireless/ath/wil6210/wil6210.h b/drivers/net/wireless/ath/wil6210/wil6210.h index 1e0536adb6e7..ce33e919d321 100644 --- a/drivers/net/wireless/ath/wil6210/wil6210.h +++ b/drivers/net/wireless/ath/wil6210/wil6210.h @@ -17,6 +17,7 @@ #ifndef __WIL6210_H__ #define __WIL6210_H__ +#include <linux/etherdevice.h> #include <linux/netdevice.h> #include <linux/wireless.h> #include <net/cfg80211.h> @@ -579,7 +580,7 @@ struct wil6210_priv { struct wireless_dev *wdev; void __iomem *csr; DECLARE_BITMAP(status, wil_status_last); - u32 fw_version; + u8 fw_version[ETHTOOL_FWVERS_LEN]; u32 hw_version; const char *hw_name; DECLARE_BITMAP(hw_capabilities, hw_capability_last); diff --git a/drivers/net/wireless/ath/wil6210/wmi.c b/drivers/net/wireless/ath/wil6210/wmi.c index 0c5db9584159..6ec3ddc5b6f1 100644 --- a/drivers/net/wireless/ath/wil6210/wmi.c +++ b/drivers/net/wireless/ath/wil6210/wmi.c @@ -312,14 +312,14 @@ static void wmi_evt_ready(struct wil6210_priv *wil, int id, void *d, int len) struct wireless_dev *wdev = wil->wdev; struct wmi_ready_event *evt = d; - wil->fw_version = le32_to_cpu(evt->sw_version); wil->n_mids = evt->numof_additional_mids; - wil_info(wil, "FW ver. %d; MAC %pM; %d MID's\n", wil->fw_version, + wil_info(wil, "FW ver. %s(SW %d); MAC %pM; %d MID's\n", + wil->fw_version, le32_to_cpu(evt->sw_version), evt->mac, wil->n_mids); /* ignore MAC address, we already have it from the boot loader */ - snprintf(wdev->wiphy->fw_version, sizeof(wdev->wiphy->fw_version), - "%d", wil->fw_version); + strlcpy(wdev->wiphy->fw_version, wil->fw_version, + sizeof(wdev->wiphy->fw_version)); wil_set_recovery_state(wil, fw_recovery_idle); set_bit(wil_status_fwready, wil->status); diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c index 695c8bc4cbc0..16f50030b960 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c @@ -3152,7 +3152,7 @@ static int ipa_assign_policy_v2(struct ipa_sys_connect_params *in, } else if (in->client == IPA_CLIENT_APPS_WAN_CONS) { sys->pyld_hdlr = ipa_wan_rx_pyld_hdlr; - if (in->napi_enabled) { + if (in->recycle_enabled) { sys->repl_hdlr = ipa_replenish_rx_cache_recycle; sys->rx_pool_sz = diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_i.h b/drivers/platform/msm/ipa/ipa_v2/ipa_i.h index 581a5f9d8a2e..fec4d5484d28 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_i.h +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_i.h @@ -41,8 +41,6 @@ #define MTU_BYTE 1500 #define IPA_MAX_NUM_PIPES 0x14 -#define IPA_WAN_CONS_DESC_FIFO_SZ 0x5E80 -#define IPA_WAN_NAPI_CONS_RX_POOL_SZ 3000 #define IPA_SYS_DESC_FIFO_SZ 0x2000 #define IPA_SYS_TX_DATA_DESC_FIFO_SZ 0x1000 #define IPA_LAN_RX_HEADER_LENGTH (2) @@ -53,6 +51,8 @@ #define IPA_UC_FINISH_MAX 6 #define IPA_UC_WAIT_MIN_SLEEP 1000 #define IPA_UC_WAII_MAX_SLEEP 1200 +#define IPA_WAN_NAPI_CONS_RX_POOL_SZ (IPA_GENERIC_RX_POOL_SZ*3) +#define IPA_WAN_CONS_DESC_FIFO_SZ (IPA_SYS_DESC_FIFO_SZ*3) #define IPA_MAX_STATUS_STAT_NUM 30 diff --git a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c index 1be9a6745531..ebb93e246048 100644 --- a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c +++ b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c @@ -34,6 +34,8 @@ #include <linux/rmnet_ipa_fd_ioctl.h> #include <linux/ipa.h> #include <uapi/linux/net_map.h> +#include <uapi/linux/msm_rmnet.h> +#include <net/rmnet_config.h> #include "ipa_trace.h" @@ -1231,6 +1233,79 @@ static void apps_ipa_packet_receive_notify(void *priv, } +static int handle_ingress_format(struct net_device *dev, + struct rmnet_ioctl_extended_s *in) +{ + int ret = 0; + struct rmnet_phys_ep_conf_s *ep_cfg; + + IPAWANDBG("Get RMNET_IOCTL_SET_INGRESS_DATA_FORMAT\n"); + if ((in->u.data) & RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM) + ipa_to_apps_ep_cfg.ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_OFFLOAD_DL; + + if ((in->u.data) & RMNET_IOCTL_INGRESS_FORMAT_AGG_DATA) { + IPAWANERR("get AGG size %d count %d\n", + in->u.ingress_format.agg_size, + in->u.ingress_format.agg_count); + + ret = ipa_disable_apps_wan_cons_deaggr( + in->u.ingress_format.agg_size, + in->u.ingress_format.agg_count); + + if (!ret) { + ipa_to_apps_ep_cfg.ipa_ep_cfg.aggr.aggr_byte_limit = + in->u.ingress_format.agg_size; + ipa_to_apps_ep_cfg.ipa_ep_cfg.aggr.aggr_pkt_limit = + in->u.ingress_format.agg_count; + + ipa_to_apps_ep_cfg.recycle_enabled = true; + ep_cfg = (struct rmnet_phys_ep_conf_s *) + rcu_dereference(dev->rx_handler_data); + ep_cfg->recycle = ipa_recycle_wan_skb; + pr_info("Wan Recycle Enabled\n"); + } + } + + ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr.hdr_len = 4; + ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr.hdr_ofst_metadata_valid = 1; + ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr.hdr_ofst_metadata = 1; + ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid = 1; + ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr.hdr_ofst_pkt_size = 2; + + ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid = true; + ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad = 0; + ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding = + true; + ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset = 0; + ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext.hdr_little_endian = 0; + ipa_to_apps_ep_cfg.ipa_ep_cfg.metadata_mask.metadata_mask = 0xFF000000; + + ipa_to_apps_ep_cfg.client = IPA_CLIENT_APPS_WAN_CONS; + ipa_to_apps_ep_cfg.notify = apps_ipa_packet_receive_notify; + ipa_to_apps_ep_cfg.priv = dev; + + ipa_to_apps_ep_cfg.napi_enabled = ipa_rmnet_res.ipa_napi_enable; + if (ipa_to_apps_ep_cfg.napi_enabled) + ipa_to_apps_ep_cfg.desc_fifo_sz = IPA_WAN_CONS_DESC_FIFO_SZ; + else + ipa_to_apps_ep_cfg.desc_fifo_sz = IPA_SYS_DESC_FIFO_SZ; + + mutex_lock(&ipa_to_apps_pipe_handle_guard); + if (atomic_read(&is_ssr)) { + IPAWANDBG("In SSR sequence/recovery\n"); + mutex_unlock(&ipa_to_apps_pipe_handle_guard); + return -EFAULT; + } + ret = ipa2_setup_sys_pipe(&ipa_to_apps_ep_cfg, &ipa_to_apps_hdl); + mutex_unlock(&ipa_to_apps_pipe_handle_guard); + + if (ret) + IPAWANERR("failed to configure ingress\n"); + + return ret; +} + /** * ipa_wwan_ioctl() - I/O control for wwan network driver. * @@ -1531,83 +1606,7 @@ static int ipa_wwan_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) } break; case RMNET_IOCTL_SET_INGRESS_DATA_FORMAT:/* Set IDF */ - IPAWANDBG("get RMNET_IOCTL_SET_INGRESS_DATA_FORMAT\n"); - if ((extend_ioctl_data.u.data) & - RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM) - ipa_to_apps_ep_cfg.ipa_ep_cfg.cfg. - cs_offload_en = - IPA_ENABLE_CS_OFFLOAD_DL; - - if ((extend_ioctl_data.u.data) & - RMNET_IOCTL_INGRESS_FORMAT_AGG_DATA) { - IPAWANERR("get AGG size %d count %d\n", - extend_ioctl_data.u. - ingress_format.agg_size, - extend_ioctl_data.u. - ingress_format.agg_count); - if (!ipa_disable_apps_wan_cons_deaggr( - extend_ioctl_data.u. - ingress_format.agg_size, - extend_ioctl_data. - u.ingress_format.agg_count)) { - ipa_to_apps_ep_cfg.ipa_ep_cfg.aggr. - aggr_byte_limit = extend_ioctl_data. - u.ingress_format.agg_size; - ipa_to_apps_ep_cfg.ipa_ep_cfg.aggr. - aggr_pkt_limit = extend_ioctl_data. - u.ingress_format.agg_count; - } - } - - ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr.hdr_len = 4; - ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr. - hdr_ofst_metadata_valid = 1; - ipa_to_apps_ep_cfg.ipa_ep_cfg. - hdr.hdr_ofst_metadata = 1; - ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr. - hdr_ofst_pkt_size_valid = 1; - ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr. - hdr_ofst_pkt_size = 2; - - ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext. - hdr_total_len_or_pad_valid = true; - ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext. - hdr_total_len_or_pad = 0; - ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext. - hdr_payload_len_inc_padding = true; - ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext. - hdr_total_len_or_pad_offset = 0; - ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext. - hdr_little_endian = 0; - ipa_to_apps_ep_cfg.ipa_ep_cfg.metadata_mask. - metadata_mask = 0xFF000000; - - ipa_to_apps_ep_cfg.client = IPA_CLIENT_APPS_WAN_CONS; - ipa_to_apps_ep_cfg.notify = - apps_ipa_packet_receive_notify; - ipa_to_apps_ep_cfg.priv = dev; - - ipa_to_apps_ep_cfg.napi_enabled = - ipa_rmnet_res.ipa_napi_enable; - if (ipa_to_apps_ep_cfg.napi_enabled) - ipa_to_apps_ep_cfg.desc_fifo_sz = - IPA_WAN_CONS_DESC_FIFO_SZ; - else - ipa_to_apps_ep_cfg.desc_fifo_sz = - IPA_SYS_DESC_FIFO_SZ; - - mutex_lock(&ipa_to_apps_pipe_handle_guard); - if (atomic_read(&is_ssr)) { - IPAWANDBG("In SSR sequence/recovery\n"); - mutex_unlock(&ipa_to_apps_pipe_handle_guard); - rc = -EFAULT; - break; - } - rc = ipa2_setup_sys_pipe( - &ipa_to_apps_ep_cfg, &ipa_to_apps_hdl); - mutex_unlock(&ipa_to_apps_pipe_handle_guard); - if (rc) - IPAWANERR("failed to configure ingress\n"); + rc = handle_ingress_format(dev, &extend_ioctl_data); break; case RMNET_IOCTL_SET_XLAT_DEV_INFO: wan_msg = kzalloc(sizeof(struct ipa_wan_msg), diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index a7089f5e6c3c..24fbc5c738d8 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -38,6 +38,16 @@ #include <linux/hash.h> #include <soc/qcom/subsystem_restart.h> #include <soc/qcom/smem.h> +#include <soc/qcom/scm.h> + +#ifdef CONFIG_ARM64 + +/* Outer caches unsupported on ARM64 platforms */ +#define outer_flush_range(x, y) +#define __cpuc_flush_dcache_area __flush_dcache_area + +#endif + #define IPA_SUBSYSTEM_NAME "ipa_fws" #include "ipa_i.h" #include "../ipa_rm_i.h" @@ -199,6 +209,21 @@ struct ipa3_ioc_nat_alloc_mem32 { }; #endif +#define IPA_TZ_UNLOCK_ATTRIBUTE 0x0C0311 +#define TZ_MEM_PROTECT_REGION_ID 0x10 + +struct tz_smmu_ipa_protect_region_iovec_s { + u64 input_addr; + u64 output_addr; + u64 size; + u32 attr; +} __packed; + +struct tz_smmu_ipa_protect_region_s { + phys_addr_t iovec_buf; + u32 size_bytes; +} __packed; + static void ipa3_start_tag_process(struct work_struct *work); static DECLARE_WORK(ipa3_tag_work, ipa3_start_tag_process); @@ -4036,6 +4061,53 @@ static ssize_t ipa3_write(struct file *file, const char __user *buf, return count; } +static int ipa3_tz_unlock_reg(struct ipa3_context *ipa3_ctx) +{ + int i, size, ret, resp; + struct tz_smmu_ipa_protect_region_iovec_s *ipa_tz_unlock_vec; + struct tz_smmu_ipa_protect_region_s cmd_buf; + + if (ipa3_ctx && ipa3_ctx->ipa_tz_unlock_reg_num > 0) { + size = ipa3_ctx->ipa_tz_unlock_reg_num * + sizeof(struct tz_smmu_ipa_protect_region_iovec_s); + ipa_tz_unlock_vec = kzalloc(PAGE_ALIGN(size), GFP_KERNEL); + if (ipa_tz_unlock_vec == NULL) + return -ENOMEM; + + for (i = 0; i < ipa3_ctx->ipa_tz_unlock_reg_num; i++) { + ipa_tz_unlock_vec[i].input_addr = + ipa3_ctx->ipa_tz_unlock_reg[i].reg_addr ^ + (ipa3_ctx->ipa_tz_unlock_reg[i].reg_addr & + 0xFFF); + ipa_tz_unlock_vec[i].output_addr = + ipa3_ctx->ipa_tz_unlock_reg[i].reg_addr ^ + (ipa3_ctx->ipa_tz_unlock_reg[i].reg_addr & + 0xFFF); + ipa_tz_unlock_vec[i].size = + ipa3_ctx->ipa_tz_unlock_reg[i].size; + ipa_tz_unlock_vec[i].attr = IPA_TZ_UNLOCK_ATTRIBUTE; + } + + /* pass physical address of command buffer */ + cmd_buf.iovec_buf = virt_to_phys((void *)ipa_tz_unlock_vec); + cmd_buf.size_bytes = size; + + /* flush cache to DDR */ + __cpuc_flush_dcache_area((void *)ipa_tz_unlock_vec, size); + outer_flush_range(cmd_buf.iovec_buf, cmd_buf.iovec_buf + size); + + ret = scm_call(SCM_SVC_MP, TZ_MEM_PROTECT_REGION_ID, &cmd_buf, + sizeof(cmd_buf), &resp, sizeof(resp)); + if (ret) { + IPAERR("scm call SCM_SVC_MP failed: %d\n", ret); + kfree(ipa_tz_unlock_vec); + return -EFAULT; + } + kfree(ipa_tz_unlock_vec); + } + return 0; +} + /** * ipa3_pre_init() - Initialize the IPA Driver. * This part contains all initialization which doesn't require IPA HW, such @@ -4120,6 +4192,27 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, ipa3_ctx->apply_rg10_wa = resource_p->apply_rg10_wa; ipa3_ctx->gsi_ch20_wa = resource_p->gsi_ch20_wa; ipa3_ctx->ipa3_active_clients_logging.log_rdy = false; + if (resource_p->ipa_tz_unlock_reg) { + ipa3_ctx->ipa_tz_unlock_reg_num = + resource_p->ipa_tz_unlock_reg_num; + ipa3_ctx->ipa_tz_unlock_reg = kcalloc( + ipa3_ctx->ipa_tz_unlock_reg_num, + sizeof(*ipa3_ctx->ipa_tz_unlock_reg), + GFP_KERNEL); + if (ipa3_ctx->ipa_tz_unlock_reg == NULL) { + result = -ENOMEM; + goto fail_tz_unlock_reg; + } + for (i = 0; i < ipa3_ctx->ipa_tz_unlock_reg_num; i++) { + ipa3_ctx->ipa_tz_unlock_reg[i].reg_addr = + resource_p->ipa_tz_unlock_reg[i].reg_addr; + ipa3_ctx->ipa_tz_unlock_reg[i].size = + resource_p->ipa_tz_unlock_reg[i].size; + } + } + + /* unlock registers for uc */ + ipa3_tz_unlock_reg(ipa3_ctx); /* default aggregation parameters */ ipa3_ctx->aggregation_type = IPA_MBIM_16; @@ -4568,6 +4661,8 @@ fail_init_mem_partition: fail_bind: kfree(ipa3_ctx->ctrl); fail_mem_ctrl: + kfree(ipa3_ctx->ipa_tz_unlock_reg); +fail_tz_unlock_reg: ipc_log_context_destroy(ipa3_ctx->logbuf); fail_logbuf: kfree(ipa3_ctx); @@ -4579,8 +4674,10 @@ fail_mem_ctx: static int get_ipa_dts_configuration(struct platform_device *pdev, struct ipa3_plat_drv_res *ipa_drv_res) { - int result; + int i, result, pos; struct resource *resource; + u32 *ipa_tz_unlock_reg; + int elem_num; /* initialize ipa3_res */ ipa_drv_res->ipa_pipe_mem_start_ofst = IPA_PIPE_MEM_START_OFST; @@ -4595,6 +4692,8 @@ static int get_ipa_dts_configuration(struct platform_device *pdev, ipa_drv_res->lan_rx_ring_size = IPA_GENERIC_RX_POOL_SZ; ipa_drv_res->apply_rg10_wa = false; ipa_drv_res->gsi_ch20_wa = false; + ipa_drv_res->ipa_tz_unlock_reg_num = 0; + ipa_drv_res->ipa_tz_unlock_reg = NULL; smmu_info.disable_htw = of_property_read_bool(pdev->dev.of_node, "qcom,smmu-disable-htw"); @@ -4808,6 +4907,46 @@ static int get_ipa_dts_configuration(struct platform_device *pdev, ipa_drv_res->apply_rg10_wa ? "Needed" : "Not needed"); + elem_num = of_property_count_elems_of_size(pdev->dev.of_node, + "qcom,ipa-tz-unlock-reg", sizeof(u32)); + + if (elem_num > 0 && elem_num % 2 == 0) { + ipa_drv_res->ipa_tz_unlock_reg_num = elem_num / 2; + + ipa_tz_unlock_reg = kcalloc(elem_num, sizeof(u32), GFP_KERNEL); + if (ipa_tz_unlock_reg == NULL) + return -ENOMEM; + + ipa_drv_res->ipa_tz_unlock_reg = kcalloc( + ipa_drv_res->ipa_tz_unlock_reg_num, + sizeof(*ipa_drv_res->ipa_tz_unlock_reg), + GFP_KERNEL); + if (ipa_drv_res->ipa_tz_unlock_reg == NULL) { + kfree(ipa_tz_unlock_reg); + return -ENOMEM; + } + + if (of_property_read_u32_array(pdev->dev.of_node, + "qcom,ipa-tz-unlock-reg", ipa_tz_unlock_reg, + elem_num)) { + IPAERR("failed to read register addresses\n"); + kfree(ipa_tz_unlock_reg); + kfree(ipa_drv_res->ipa_tz_unlock_reg); + return -EFAULT; + } + + pos = 0; + for (i = 0; i < ipa_drv_res->ipa_tz_unlock_reg_num; i++) { + ipa_drv_res->ipa_tz_unlock_reg[i].reg_addr = + ipa_tz_unlock_reg[pos++]; + ipa_drv_res->ipa_tz_unlock_reg[i].size = + ipa_tz_unlock_reg[pos++]; + IPADBG("tz unlock reg %d: addr 0x%pa size %d\n", i, + &ipa_drv_res->ipa_tz_unlock_reg[i].reg_addr, + ipa_drv_res->ipa_tz_unlock_reg[i].size); + } + kfree(ipa_tz_unlock_reg); + } return 0; } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c index 9e346f12a108..643e40402499 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c @@ -3180,7 +3180,7 @@ static int ipa3_assign_policy(struct ipa_sys_connect_params *in, IPA_CLIENT_APPS_WAN_CONS) { sys->pyld_hdlr = ipa3_wan_rx_pyld_hdlr; sys->free_rx_wrapper = ipa3_free_rx_wrapper; - if (in->napi_enabled) { + if (in->recycle_enabled) { sys->repl_hdlr = ipa3_replenish_rx_cache_recycle; sys->rx_pool_sz = diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c index 8396e507a401..df413c991a53 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c @@ -1372,18 +1372,18 @@ void ipa3_install_dflt_flt_rules(u32 ipa_ep_idx) mutex_lock(&ipa3_ctx->lock); tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v4]; - tbl->sticky_rear = true; rule.action = IPA_PASS_TO_EXCEPTION; - __ipa_add_flt_rule(tbl, IPA_IP_v4, &rule, false, + __ipa_add_flt_rule(tbl, IPA_IP_v4, &rule, true, &ep->dflt_flt4_rule_hdl); ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v4); + tbl->sticky_rear = true; tbl = &ipa3_ctx->flt_tbl[ipa_ep_idx][IPA_IP_v6]; - tbl->sticky_rear = true; rule.action = IPA_PASS_TO_EXCEPTION; - __ipa_add_flt_rule(tbl, IPA_IP_v6, &rule, false, + __ipa_add_flt_rule(tbl, IPA_IP_v6, &rule, true, &ep->dflt_flt6_rule_hdl); ipa3_ctx->ctrl->ipa3_commit_flt(IPA_IP_v6); + tbl->sticky_rear = true; mutex_unlock(&ipa3_ctx->lock); } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h index 4309fbc3154f..6f86448319db 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h @@ -43,8 +43,6 @@ #define MTU_BYTE 1500 #define IPA3_MAX_NUM_PIPES 31 -#define IPA_WAN_CONS_DESC_FIFO_SZ 0x5E80 -#define IPA_WAN_NAPI_CONS_RX_POOL_SZ 3000 #define IPA_SYS_DESC_FIFO_SZ 0x800 #define IPA_SYS_TX_DATA_DESC_FIFO_SZ 0x1000 #define IPA_LAN_RX_HEADER_LENGTH (2) @@ -55,6 +53,8 @@ #define IPA_UC_FINISH_MAX 6 #define IPA_UC_WAIT_MIN_SLEEP 1000 #define IPA_UC_WAII_MAX_SLEEP 1200 +#define IPA_WAN_NAPI_CONS_RX_POOL_SZ (IPA_GENERIC_RX_POOL_SZ*3) +#define IPA_WAN_CONS_DESC_FIFO_SZ (IPA_SYS_DESC_FIFO_SZ*3) #define IPA_MAX_STATUS_STAT_NUM 30 @@ -1012,6 +1012,11 @@ struct ipa3_ready_cb_info { void *user_data; }; +struct ipa_tz_unlock_reg_info { + u64 reg_addr; + u32 size; +}; + /** * struct ipa3_context - IPA context * @class: pointer to the struct class @@ -1228,6 +1233,8 @@ struct ipa3_context { struct list_head ipa_ready_cb_list; struct completion init_completion_obj; struct ipa3_smp2p_info smp2p_info; + u32 ipa_tz_unlock_reg_num; + struct ipa_tz_unlock_reg_info *ipa_tz_unlock_reg; }; /** @@ -1266,6 +1273,8 @@ struct ipa3_plat_drv_res { bool apply_rg10_wa; bool gsi_ch20_wa; bool tethered_flow_control; + u32 ipa_tz_unlock_reg_num; + struct ipa_tz_unlock_reg_info *ipa_tz_unlock_reg; }; /** diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c index 2cd08d77df6e..a2fef45cc55f 100644 --- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c @@ -34,6 +34,8 @@ #include <linux/rmnet_ipa_fd_ioctl.h> #include <linux/ipa.h> #include <uapi/linux/net_map.h> +#include <uapi/linux/msm_rmnet.h> +#include <net/rmnet_config.h> #include "ipa_trace.h" @@ -1241,6 +1243,83 @@ static void apps_ipa_packet_receive_notify(void *priv, IPAWANERR("Invalid evt %d received in wan_ipa_receive\n", evt); } +static int handle3_ingress_format(struct net_device *dev, + struct rmnet_ioctl_extended_s *in) +{ + int ret = 0; + struct ipa_sys_connect_params *ipa_wan_ep_cfg; + struct rmnet_phys_ep_conf_s *ep_cfg; + + IPAWANDBG("Get RMNET_IOCTL_SET_INGRESS_DATA_FORMAT\n"); + ipa_wan_ep_cfg = &rmnet_ipa3_ctx->ipa_to_apps_ep_cfg; + if ((in->u.data) & RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM) + ipa_wan_ep_cfg->ipa_ep_cfg.cfg.cs_offload_en = + IPA_ENABLE_CS_OFFLOAD_DL; + + if ((in->u.data) & RMNET_IOCTL_INGRESS_FORMAT_AGG_DATA) { + IPAWANERR("get AGG size %d count %d\n", + in->u.ingress_format.agg_size, + in->u.ingress_format.agg_count); + + ret = ipa_disable_apps_wan_cons_deaggr( + in->u.ingress_format.agg_size, + in->u.ingress_format.agg_count); + + if (!ret) { + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_byte_limit = + in->u.ingress_format.agg_size; + ipa_wan_ep_cfg->ipa_ep_cfg.aggr.aggr_pkt_limit = + in->u.ingress_format.agg_count; + + ipa_wan_ep_cfg->recycle_enabled = true; + ep_cfg = (struct rmnet_phys_ep_conf_s *) + rcu_dereference(dev->rx_handler_data); + ep_cfg->recycle = ipa_recycle_wan_skb; + pr_info("Wan Recycle Enabled\n"); + } + } + + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_len = 4; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata_valid = 1; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_metadata = 1; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size_valid = 1; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr.hdr_ofst_pkt_size = 2; + + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_valid = true; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad = 0; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_payload_len_inc_padding = true; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_total_len_or_pad_offset = 0; + ipa_wan_ep_cfg->ipa_ep_cfg.hdr_ext.hdr_little_endian = 0; + ipa_wan_ep_cfg->ipa_ep_cfg.metadata_mask.metadata_mask = 0xFF000000; + + ipa_wan_ep_cfg->client = IPA_CLIENT_APPS_WAN_CONS; + ipa_wan_ep_cfg->notify = apps_ipa_packet_receive_notify; + ipa_wan_ep_cfg->priv = dev; + + ipa_wan_ep_cfg->napi_enabled = ipa3_rmnet_res.ipa_napi_enable; + if (ipa_wan_ep_cfg->napi_enabled) + ipa_wan_ep_cfg->desc_fifo_sz = IPA_WAN_CONS_DESC_FIFO_SZ; + else + ipa_wan_ep_cfg->desc_fifo_sz = IPA_SYS_DESC_FIFO_SZ; + + mutex_lock(&rmnet_ipa3_ctx->ipa_to_apps_pipe_handle_guard); + + if (atomic_read(&rmnet_ipa3_ctx->is_ssr)) { + IPAWANDBG("In SSR sequence/recovery\n"); + mutex_unlock(&rmnet_ipa3_ctx->ipa_to_apps_pipe_handle_guard); + return -EFAULT; + } + ret = ipa3_setup_sys_pipe(&rmnet_ipa3_ctx->ipa_to_apps_ep_cfg, + &rmnet_ipa3_ctx->ipa3_to_apps_hdl); + + mutex_unlock(&rmnet_ipa3_ctx->ipa_to_apps_pipe_handle_guard); + + if (ret) + IPAWANERR("failed to configure ingress\n"); + + return ret; +} + /** * ipa3_wwan_ioctl() - I/O control for wwan network driver. * @@ -1556,91 +1635,7 @@ static int ipa3_wwan_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) } break; case RMNET_IOCTL_SET_INGRESS_DATA_FORMAT:/* Set IDF */ - IPAWANDBG("get RMNET_IOCTL_SET_INGRESS_DATA_FORMAT\n"); - if ((extend_ioctl_data.u.data) & - RMNET_IOCTL_INGRESS_FORMAT_CHECKSUM) - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg. - ipa_ep_cfg.cfg.cs_offload_en = - IPA_ENABLE_CS_OFFLOAD_DL; - - if ((extend_ioctl_data.u.data) & - RMNET_IOCTL_INGRESS_FORMAT_AGG_DATA) { - IPAWANERR("get AGG size %d count %d\n", - extend_ioctl_data.u. - ingress_format.agg_size, - extend_ioctl_data.u. - ingress_format.agg_count); - if (!ipa_disable_apps_wan_cons_deaggr( - extend_ioctl_data.u. - ingress_format.agg_size, - extend_ioctl_data. - u.ingress_format.agg_count)) { - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg. - ipa_ep_cfg.aggr.aggr_byte_limit = - extend_ioctl_data.u.ingress_format. - agg_size; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg. - ipa_ep_cfg.aggr.aggr_pkt_limit = - extend_ioctl_data.u.ingress_format. - agg_count; - } - } - - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr. - hdr_len = 4; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr. - hdr_ofst_metadata_valid = 1; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.ipa_ep_cfg. - hdr.hdr_ofst_metadata = 1; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr. - hdr_ofst_pkt_size_valid = 1; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr. - hdr_ofst_pkt_size = 2; - - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext. - hdr_total_len_or_pad_valid = true; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext. - hdr_total_len_or_pad = 0; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext. - hdr_payload_len_inc_padding = true; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext. - hdr_total_len_or_pad_offset = 0; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.ipa_ep_cfg.hdr_ext. - hdr_little_endian = 0; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.ipa_ep_cfg. - metadata_mask.metadata_mask = 0xFF000000; - - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.client = - IPA_CLIENT_APPS_WAN_CONS; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.notify = - apps_ipa_packet_receive_notify; - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.priv = dev; - - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.napi_enabled = - ipa3_rmnet_res.ipa_napi_enable; - if (rmnet_ipa3_ctx->ipa_to_apps_ep_cfg.napi_enabled) - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg. - desc_fifo_sz = IPA_WAN_CONS_DESC_FIFO_SZ; - else - rmnet_ipa3_ctx->ipa_to_apps_ep_cfg. - desc_fifo_sz = IPA_SYS_DESC_FIFO_SZ; - - mutex_lock( - &rmnet_ipa3_ctx->ipa_to_apps_pipe_handle_guard); - if (atomic_read(&rmnet_ipa3_ctx->is_ssr)) { - IPAWANDBG("In SSR sequence/recovery\n"); - mutex_unlock(&rmnet_ipa3_ctx-> - ipa_to_apps_pipe_handle_guard); - rc = -EFAULT; - break; - } - rc = ipa3_setup_sys_pipe( - &rmnet_ipa3_ctx->ipa_to_apps_ep_cfg, - &rmnet_ipa3_ctx->ipa3_to_apps_hdl); - mutex_unlock(&rmnet_ipa3_ctx-> - ipa_to_apps_pipe_handle_guard); - if (rc) - IPAWANERR("failed to configure ingress\n"); + rc = handle3_ingress_format(dev, &extend_ioctl_data); break; case RMNET_IOCTL_SET_XLAT_DEV_INFO: wan_msg = kzalloc(sizeof(struct ipa_wan_msg), @@ -1972,6 +1967,12 @@ static int get_ipa_rmnet_dts_configuration(struct platform_device *pdev, "qcom,ipa-advertise-sg-support"); pr_info("IPA SG support = %s\n", ipa_rmnet_drv_res->ipa_advertise_sg_support ? "True" : "False"); + + ipa_rmnet_drv_res->ipa_napi_enable = + of_property_read_bool(pdev->dev.of_node, + "qcom,napi"); + pr_info("IPA napi = %s\n", + ipa_rmnet_drv_res->ipa_napi_enable ? "True" : "False"); return 0; } diff --git a/drivers/power/qcom-charger/fg-core.h b/drivers/power/qcom-charger/fg-core.h index a609d8fcd400..4feaaa0e0c4e 100644 --- a/drivers/power/qcom-charger/fg-core.h +++ b/drivers/power/qcom-charger/fg-core.h @@ -114,6 +114,7 @@ enum fg_sram_param_id { FG_SRAM_VOLTAGE_PRED, FG_SRAM_OCV, FG_SRAM_RSLOW, + FG_SRAM_ALG_FLAGS, /* Entries below here are configurable during initialization */ FG_SRAM_CUTOFF_VOLT, FG_SRAM_EMPTY_VOLT, @@ -143,6 +144,23 @@ struct fg_sram_param { int val); }; +enum fg_alg_flag_id { + ALG_FLAG_SOC_LT_OTG_MIN = 0, + ALG_FLAG_SOC_LT_RECHARGE, + ALG_FLAG_IBATT_LT_ITERM, + ALG_FLAG_IBATT_GT_HPM, + ALG_FLAG_IBATT_GT_UPM, + ALG_FLAG_VBATT_LT_RECHARGE, + ALG_FLAG_VBATT_GT_VFLOAT, + ALG_FLAG_MAX, +}; + +struct fg_alg_flag { + char *name; + u8 bit; + bool invalid; +}; + /* DT parameters for FG device */ struct fg_dt_props { int cutoff_volt_mv; @@ -179,7 +197,7 @@ struct fg_chip { struct device *dev; struct pmic_revid_data *pmic_rev_id; struct regmap *regmap; - struct dentry *dentry; + struct dentry *dfs_root; struct power_supply *fg_psy; struct power_supply *batt_psy; struct iio_channel *batt_id_chan; @@ -205,6 +223,7 @@ struct fg_chip { struct completion soc_ready; struct delayed_work profile_load_work; struct work_struct status_change_work; + struct fg_alg_flag *alg_flags; }; /* Debugfs data structures are below */ @@ -249,7 +268,7 @@ extern int fg_read(struct fg_chip *chip, int addr, u8 *val, int len); extern int fg_write(struct fg_chip *chip, int addr, u8 *val, int len); extern int fg_masked_write(struct fg_chip *chip, int addr, u8 mask, u8 val); extern int fg_ima_init(struct fg_chip *chip); -extern int fg_sram_debugfs_create(struct fg_chip *chip); +extern int fg_debugfs_create(struct fg_chip *chip); extern void fill_string(char *str, size_t str_len, u8 *buf, int buf_len); extern int64_t twos_compliment_extend(int64_t val, int s_bit_pos); extern s64 fg_float_decode(u16 val); diff --git a/drivers/power/qcom-charger/fg-util.c b/drivers/power/qcom-charger/fg-util.c index 0d52fb5ba9b8..bf5a446452a4 100644 --- a/drivers/power/qcom-charger/fg-util.c +++ b/drivers/power/qcom-charger/fg-util.c @@ -611,27 +611,23 @@ static const struct file_operations fg_sram_dfs_reg_fops = { * fg_debugfs_create: adds new fg_sram debugfs entry * @return zero on success */ -int fg_sram_debugfs_create(struct fg_chip *chip) +static int fg_sram_debugfs_create(struct fg_chip *chip) { - struct dentry *root; + struct dentry *dfs_sram; struct dentry *file; mode_t dfs_mode = S_IRUSR | S_IWUSR; pr_debug("Creating FG_SRAM debugfs file-system\n"); - root = debugfs_create_dir("fg_sram", NULL); - if (IS_ERR_OR_NULL(root)) { - pr_err("Error creating top level directory err:%ld", - (long)root); - if (PTR_ERR(root) == -ENODEV) - pr_err("debugfs is not enabled in the kernel"); - return -ENODEV; + dfs_sram = debugfs_create_dir("sram", chip->dfs_root); + if (!dfs_sram) { + pr_err("error creating fg sram dfs rc=%ld\n", + (long)dfs_sram); + return -ENOMEM; } - if (!root) - return -ENOENT; - dbgfs_data.help_msg.size = strlen(dbgfs_data.help_msg.data); - file = debugfs_create_blob("help", S_IRUGO, root, &dbgfs_data.help_msg); + file = debugfs_create_blob("help", S_IRUGO, dfs_sram, + &dbgfs_data.help_msg); if (!file) { pr_err("error creating help entry\n"); goto err_remove_fs; @@ -639,30 +635,106 @@ int fg_sram_debugfs_create(struct fg_chip *chip) dbgfs_data.chip = chip; - file = debugfs_create_u32("count", dfs_mode, root, &(dbgfs_data.cnt)); + file = debugfs_create_u32("count", dfs_mode, dfs_sram, + &(dbgfs_data.cnt)); if (!file) { pr_err("error creating 'count' entry\n"); goto err_remove_fs; } - file = debugfs_create_x32("address", dfs_mode, - root, &(dbgfs_data.addr)); + file = debugfs_create_x32("address", dfs_mode, dfs_sram, + &(dbgfs_data.addr)); if (!file) { pr_err("error creating 'address' entry\n"); goto err_remove_fs; } - file = debugfs_create_file("data", dfs_mode, root, &dbgfs_data, - &fg_sram_dfs_reg_fops); + file = debugfs_create_file("data", dfs_mode, dfs_sram, &dbgfs_data, + &fg_sram_dfs_reg_fops); if (!file) { pr_err("error creating 'data' entry\n"); goto err_remove_fs; } - chip->dentry = root; return 0; err_remove_fs: - debugfs_remove_recursive(root); + debugfs_remove_recursive(dfs_sram); + return -ENOMEM; +} + +static int fg_alg_flags_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static ssize_t fg_alg_flags_read(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct fg_chip *chip = file->private_data; + char buf[512]; + u8 alg_flags = 0; + int rc, i, len; + + rc = fg_sram_read(chip, chip->sp[FG_SRAM_ALG_FLAGS].addr_word, + chip->sp[FG_SRAM_ALG_FLAGS].addr_byte, &alg_flags, 1, + FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("failed to read algorithm flags rc=%d\n", rc); + return -EFAULT; + } + + len = 0; + for (i = 0; i < ALG_FLAG_MAX; ++i) { + if (len > ARRAY_SIZE(buf) - 1) + return -EFAULT; + if (chip->alg_flags[i].invalid) + continue; + + len += snprintf(buf + len, sizeof(buf) - sizeof(*buf) * len, + "%s = %d\n", chip->alg_flags[i].name, + (bool)(alg_flags & chip->alg_flags[i].bit)); + } + + return simple_read_from_buffer(userbuf, count, ppos, buf, len); +} + +static const struct file_operations fg_alg_flags_fops = { + .open = fg_alg_flags_open, + .read = fg_alg_flags_read, +}; + +int fg_debugfs_create(struct fg_chip *chip) +{ + int rc; + + pr_debug("Creating debugfs file-system\n"); + chip->dfs_root = debugfs_create_dir("fg", NULL); + if (IS_ERR_OR_NULL(chip->dfs_root)) { + if (PTR_ERR(chip->dfs_root) == -ENODEV) + pr_err("debugfs is not enabled in the kernel\n"); + else + pr_err("error creating fg dfs root rc=%ld\n", + (long)chip->dfs_root); + return -ENODEV; + } + + rc = fg_sram_debugfs_create(chip); + if (rc < 0) { + pr_err("failed to create sram dfs rc=%d\n", rc); + goto err_remove_fs; + } + + if (!debugfs_create_file("alg_flags", S_IRUSR, chip->dfs_root, chip, + &fg_alg_flags_fops)) { + pr_err("failed to create alg_flags file\n"); + goto err_remove_fs; + } + + return 0; + +err_remove_fs: + debugfs_remove_recursive(chip->dfs_root); return -ENOMEM; } diff --git a/drivers/power/qcom-charger/qpnp-fg-gen3.c b/drivers/power/qcom-charger/qpnp-fg-gen3.c index dda94bb3f932..a163061156ba 100644 --- a/drivers/power/qcom-charger/qpnp-fg-gen3.c +++ b/drivers/power/qcom-charger/qpnp-fg-gen3.c @@ -73,6 +73,8 @@ #define LAST_BATT_SOC_OFFSET 0 #define LAST_MONOTONIC_SOC_WORD 119 #define LAST_MONOTONIC_SOC_OFFSET 2 +#define ALG_FLAGS_WORD 120 +#define ALG_FLAGS_OFFSET 1 /* v2 SRAM address and offset in ascending order */ #define DELTA_SOC_THR_v2_WORD 13 @@ -82,7 +84,7 @@ #define CHG_TERM_CURR_v2_WORD 15 #define CHG_TERM_CURR_v2_OFFSET 1 #define EMPTY_VOLT_v2_WORD 15 -#define EMPTY_VOLT_v2_OFFSET 2 +#define EMPTY_VOLT_v2_OFFSET 3 #define VBATT_LOW_v2_WORD 16 #define VBATT_LOW_v2_OFFSET 0 @@ -119,6 +121,8 @@ static struct fg_sram_param pmicobalt_v1_sram_params[] = { fg_decode_value_16b), PARAM(RSLOW, RSLOW_WORD, RSLOW_OFFSET, 2, 244141, 1000, 0, NULL, fg_decode_value_16b), + PARAM(ALG_FLAGS, ALG_FLAGS_WORD, ALG_FLAGS_OFFSET, 1, 1, 1, 0, NULL, + fg_decode_default), /* Entries below here are configurable during initialization */ PARAM(CUTOFF_VOLT, CUTOFF_VOLT_WORD, CUTOFF_VOLT_OFFSET, 2, 1000000, 244141, 0, fg_encode_voltage, NULL), @@ -155,13 +159,15 @@ static struct fg_sram_param pmicobalt_v2_sram_params[] = { fg_decode_value_16b), PARAM(RSLOW, RSLOW_WORD, RSLOW_OFFSET, 2, 244141, 1000, 0, NULL, fg_decode_value_16b), + PARAM(ALG_FLAGS, ALG_FLAGS_WORD, ALG_FLAGS_OFFSET, 1, 1, 1, 0, NULL, + fg_decode_default), /* Entries below here are configurable during initialization */ PARAM(CUTOFF_VOLT, CUTOFF_VOLT_WORD, CUTOFF_VOLT_OFFSET, 2, 1000000, 244141, 0, fg_encode_voltage, NULL), - PARAM(EMPTY_VOLT, EMPTY_VOLT_v2_WORD, EMPTY_VOLT_v2_OFFSET, 1, 100000, - 390625, -2000, fg_encode_voltage, NULL), - PARAM(VBATT_LOW, VBATT_LOW_v2_WORD, VBATT_LOW_v2_OFFSET, 1, 100000, - 390625, -2000, fg_encode_voltage, NULL), + PARAM(EMPTY_VOLT, EMPTY_VOLT_v2_WORD, EMPTY_VOLT_v2_OFFSET, 1, 1000, + 15625, -2000, fg_encode_voltage, NULL), + PARAM(VBATT_LOW, VBATT_LOW_v2_WORD, VBATT_LOW_v2_OFFSET, 1, 1000, + 15625, -2000, fg_encode_voltage, NULL), PARAM(SYS_TERM_CURR, SYS_TERM_CURR_WORD, SYS_TERM_CURR_OFFSET, 3, 1000000, 122070, 0, fg_encode_current, NULL), PARAM(CHG_TERM_CURR, CHG_TERM_CURR_v2_WORD, CHG_TERM_CURR_v2_OFFSET, 1, @@ -183,6 +189,67 @@ static struct fg_sram_param pmicobalt_v2_sram_params[] = { ESR_TIMER_CHG_INIT_OFFSET, 2, 1, 1, 0, fg_encode_default, NULL), }; +static struct fg_alg_flag pmicobalt_v1_alg_flags[] = { + [ALG_FLAG_SOC_LT_OTG_MIN] = { + .name = "SOC_LT_OTG_MIN", + .bit = BIT(0), + }, + [ALG_FLAG_SOC_LT_RECHARGE] = { + .name = "SOC_LT_RECHARGE", + .bit = BIT(1), + }, + [ALG_FLAG_IBATT_LT_ITERM] = { + .name = "IBATT_LT_ITERM", + .bit = BIT(2), + }, + [ALG_FLAG_IBATT_GT_HPM] = { + .name = "IBATT_GT_HPM", + .bit = BIT(3), + }, + [ALG_FLAG_IBATT_GT_UPM] = { + .name = "IBATT_GT_UPM", + .bit = BIT(4), + }, + [ALG_FLAG_VBATT_LT_RECHARGE] = { + .name = "VBATT_LT_RECHARGE", + .bit = BIT(5), + }, + [ALG_FLAG_VBATT_GT_VFLOAT] = { + .invalid = true, + }, +}; + +static struct fg_alg_flag pmicobalt_v2_alg_flags[] = { + [ALG_FLAG_SOC_LT_OTG_MIN] = { + .name = "SOC_LT_OTG_MIN", + .bit = BIT(0), + }, + [ALG_FLAG_SOC_LT_RECHARGE] = { + .name = "SOC_LT_RECHARGE", + .bit = BIT(1), + }, + [ALG_FLAG_IBATT_LT_ITERM] = { + .name = "IBATT_LT_ITERM", + .bit = BIT(2), + }, + [ALG_FLAG_IBATT_GT_HPM] = { + .name = "IBATT_GT_HPM", + .bit = BIT(4), + }, + [ALG_FLAG_IBATT_GT_UPM] = { + .name = "IBATT_GT_UPM", + .bit = BIT(5), + }, + [ALG_FLAG_VBATT_LT_RECHARGE] = { + .name = "VBATT_LT_RECHARGE", + .bit = BIT(6), + }, + [ALG_FLAG_VBATT_GT_VFLOAT] = { + .name = "VBATT_GT_VFLOAT", + .bit = BIT(7), + }, +}; + static int fg_gen3_debug_mask; module_param_named( debug_mask, fg_gen3_debug_mask, int, S_IRUSR | S_IWUSR @@ -410,7 +477,7 @@ static void fg_encode_current(struct fg_sram_param *sp, int64_t temp; s64 current_ma; - current_ma = -val; + current_ma = val; temp = (int64_t)div_s64(current_ma * sp[id].numrtr, sp[id].denmtr); pr_debug("temp: %llx id: %d, val: %d, buf: [ ", temp, id, val); for (i = 0; i < sp[id].len; i++) { @@ -1276,7 +1343,7 @@ static int fg_register_interrupts(struct fg_chip *chip) #define DEFAULT_CUTOFF_VOLT_MV 3200 #define DEFAULT_EMPTY_VOLT_MV 3100 #define DEFAULT_CHG_TERM_CURR_MA 100 -#define DEFAULT_SYS_TERM_CURR_MA 125 +#define DEFAULT_SYS_TERM_CURR_MA -125 #define DEFAULT_DELTA_SOC_THR 1 #define DEFAULT_RECHARGE_SOC_THR 95 #define DEFAULT_BATT_TEMP_COLD 0 @@ -1318,12 +1385,15 @@ static int fg_parse_dt(struct fg_chip *chip) switch (chip->pmic_rev_id->pmic_subtype) { case PMICOBALT_SUBTYPE: - if (chip->pmic_rev_id->rev4 < PMICOBALT_V2P0_REV4) + if (chip->pmic_rev_id->rev4 < PMICOBALT_V2P0_REV4) { chip->sp = pmicobalt_v1_sram_params; - else if (chip->pmic_rev_id->rev4 == PMICOBALT_V2P0_REV4) + chip->alg_flags = pmicobalt_v1_alg_flags; + } else if (chip->pmic_rev_id->rev4 == PMICOBALT_V2P0_REV4) { chip->sp = pmicobalt_v2_sram_params; - else + chip->alg_flags = pmicobalt_v2_alg_flags; + } else { return -EINVAL; + } break; default: return -EINVAL; @@ -1465,7 +1535,7 @@ static int fg_parse_dt(struct fg_chip *chip) static void fg_cleanup(struct fg_chip *chip) { power_supply_unreg_notifier(&chip->nb); - debugfs_remove_recursive(chip->dentry); + debugfs_remove_recursive(chip->dfs_root); if (chip->awake_votable) destroy_votable(chip->awake_votable); @@ -1562,7 +1632,7 @@ static int fg_gen3_probe(struct platform_device *pdev) if (fg_irqs[SOC_UPDATE_IRQ].irq) disable_irq_nosync(fg_irqs[SOC_UPDATE_IRQ].irq); - rc = fg_sram_debugfs_create(chip); + rc = fg_debugfs_create(chip); if (rc < 0) { dev_err(chip->dev, "Error in creating debugfs entries, rc:%d\n", rc); diff --git a/drivers/power/qcom-charger/qpnp-smb2.c b/drivers/power/qcom-charger/qpnp-smb2.c index 32b374cbb67f..d19e7827ed83 100644 --- a/drivers/power/qcom-charger/qpnp-smb2.c +++ b/drivers/power/qcom-charger/qpnp-smb2.c @@ -596,14 +596,17 @@ static enum power_supply_property smb2_batt_props[] = { POWER_SUPPLY_PROP_CHARGER_TEMP, POWER_SUPPLY_PROP_CHARGER_TEMP_MAX, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMITED, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_CURRENT_NOW, + POWER_SUPPLY_PROP_TEMP, + POWER_SUPPLY_PROP_TECHNOLOGY, }; static int smb2_batt_get_prop(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) { - struct smb2 *chip = power_supply_get_drvdata(psy); - struct smb_charger *chg = &chip->chg; + struct smb_charger *chg = power_supply_get_drvdata(psy); int rc = 0; switch (psp) { @@ -637,14 +640,28 @@ static int smb2_batt_get_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMITED: rc = smblib_get_prop_input_current_limited(chg, val); break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + rc = smblib_get_prop_batt_voltage_now(chg, val); + break; + case POWER_SUPPLY_PROP_CURRENT_NOW: + rc = smblib_get_prop_batt_current_now(chg, val); + break; + case POWER_SUPPLY_PROP_TEMP: + rc = smblib_get_prop_batt_temp(chg, val); + break; + case POWER_SUPPLY_PROP_TECHNOLOGY: + val->intval = POWER_SUPPLY_TECHNOLOGY_LION; + break; default: pr_err("batt power supply prop %d not supported\n", psp); return -EINVAL; } + if (rc < 0) { pr_debug("Couldn't get prop %d rc = %d\n", psp, rc); return -ENODATA; } + return 0; } diff --git a/drivers/power/qcom-charger/smb-lib.c b/drivers/power/qcom-charger/smb-lib.c index 21b330127369..ed24e12e313d 100644 --- a/drivers/power/qcom-charger/smb-lib.c +++ b/drivers/power/qcom-charger/smb-lib.c @@ -1003,6 +1003,45 @@ int smblib_get_prop_input_current_limited(struct smb_charger *chg, return 0; } +int smblib_get_prop_batt_voltage_now(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + if (!chg->bms_psy) + return -EINVAL; + + rc = power_supply_get_property(chg->bms_psy, + POWER_SUPPLY_PROP_VOLTAGE_NOW, val); + return rc; +} + +int smblib_get_prop_batt_current_now(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + if (!chg->bms_psy) + return -EINVAL; + + rc = power_supply_get_property(chg->bms_psy, + POWER_SUPPLY_PROP_CURRENT_NOW, val); + return rc; +} + +int smblib_get_prop_batt_temp(struct smb_charger *chg, + union power_supply_propval *val) +{ + int rc; + + if (!chg->bms_psy) + return -EINVAL; + + rc = power_supply_get_property(chg->bms_psy, + POWER_SUPPLY_PROP_TEMP, val); + return rc; +} + /*********************** * BATTERY PSY SETTERS * ***********************/ diff --git a/drivers/power/qcom-charger/smb-lib.h b/drivers/power/qcom-charger/smb-lib.h index aeb1eb2c454f..289fb1706e97 100644 --- a/drivers/power/qcom-charger/smb-lib.h +++ b/drivers/power/qcom-charger/smb-lib.h @@ -222,6 +222,12 @@ int smblib_get_prop_system_temp_level(struct smb_charger *chg, union power_supply_propval *val); int smblib_get_prop_input_current_limited(struct smb_charger *chg, union power_supply_propval *val); +int smblib_get_prop_batt_voltage_now(struct smb_charger *chg, + union power_supply_propval *val); +int smblib_get_prop_batt_current_now(struct smb_charger *chg, + union power_supply_propval *val); +int smblib_get_prop_batt_temp(struct smb_charger *chg, + union power_supply_propval *val); int smblib_set_prop_input_suspend(struct smb_charger *chg, const union power_supply_propval *val); diff --git a/drivers/scsi/ufs/ufs-debugfs.c b/drivers/scsi/ufs/ufs-debugfs.c index d6e372fc7922..0547853c4f3a 100644 --- a/drivers/scsi/ufs/ufs-debugfs.c +++ b/drivers/scsi/ufs/ufs-debugfs.c @@ -1479,8 +1479,8 @@ void ufsdbg_add_debugfs(struct ufs_hba *hba) char root_name[sizeof("ufshcd00")]; if (!hba) { - dev_err(hba->dev, "%s: NULL hba, exiting", __func__); - goto err_no_root; + pr_err("%s: NULL hba, exiting", __func__); + return; } snprintf(root_name, ARRAY_SIZE(root_name), "%s%d", UFSHCD, diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c index ad4b6ffef36e..1a1dd804ffb3 100644 --- a/drivers/scsi/ufs/ufs-qcom.c +++ b/drivers/scsi/ufs/ufs-qcom.c @@ -1498,10 +1498,14 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, /* M-PHY RMMI interface clocks can be turned off */ ufs_qcom_phy_disable_iface_clk(host->generic_phy); - if (!ufs_qcom_is_link_active(hba)) { - if (!is_gating_context) - /* turn off UFS local PHY ref_clk */ - ufs_qcom_phy_disable_ref_clk(host->generic_phy); + /* + * If auto hibern8 is supported then the link will already + * be in hibern8 state and the ref clock can be gated. + */ + if (ufshcd_is_auto_hibern8_supported(hba) || + !ufs_qcom_is_link_active(hba)) { + /* turn off UFS local PHY ref_clk */ + ufs_qcom_phy_disable_ref_clk(host->generic_phy); /* disable device ref_clk */ ufs_qcom_dev_ref_clk_ctrl(host, false); } @@ -1956,13 +1960,6 @@ static int ufs_qcom_init(struct ufs_hba *hba) host->hba = hba; ufshcd_set_variant(hba, host); - /* - * voting/devoting device ref_clk source is time consuming hence - * skip devoting it during aggressive clock gating. This clock - * will still be gated off during runtime suspend. - */ - hba->no_ref_clk_gating = true; - err = ufs_qcom_ice_get_dev(host); if (err == -EPROBE_DEFER) { /* diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index d478767ad3dd..311a4ea24973 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -1346,7 +1346,12 @@ static void ufshcd_gate_work(struct work_struct *work) ufshcd_set_link_hibern8(hba); } - if (!ufshcd_is_link_active(hba) && !hba->no_ref_clk_gating) + /* + * If auto hibern8 is supported then the link will already + * be in hibern8 state and the ref clock can be gated. + */ + if ((ufshcd_is_auto_hibern8_supported(hba) || + !ufshcd_is_link_active(hba)) && !hba->no_ref_clk_gating) ufshcd_disable_clocks(hba, true); else /* If link is active, device ref_clk can't be switched off */ diff --git a/drivers/soc/qcom/icnss.c b/drivers/soc/qcom/icnss.c index f19bd784dbdc..edaaa0b2d3c8 100644 --- a/drivers/soc/qcom/icnss.c +++ b/drivers/soc/qcom/icnss.c @@ -244,9 +244,10 @@ enum icnss_debug_quirks { RECOVERY_DISABLE, SSR_ONLY, PDR_ONLY, + VBATT_DISABLE, }; -#define ICNSS_QUIRKS_DEFAULT 0 +#define ICNSS_QUIRKS_DEFAULT BIT(VBATT_DISABLE) unsigned long quirks = ICNSS_QUIRKS_DEFAULT; module_param(quirks, ulong, 0600); @@ -755,6 +756,9 @@ static int icnss_init_vph_monitor(struct icnss_priv *priv) { int ret = 0; + if (test_bit(VBATT_DISABLE, &quirks)) + goto out; + ret = icnss_get_phone_power(priv, &priv->vph_pwr); if (ret) goto out; @@ -2288,7 +2292,7 @@ static int icnss_driver_event_server_exit(void *data) icnss_pr_info("QMI Service Disconnected: 0x%lx\n", penv->state); - if (penv->adc_tm_dev) + if (!test_bit(VBATT_DISABLE, &quirks) && penv->adc_tm_dev) qpnp_adc_tm_disable_chan_meas(penv->adc_tm_dev, &penv->vph_monitor_params); diff --git a/drivers/soc/qcom/qdsp6v2/apr.c b/drivers/soc/qcom/qdsp6v2/apr.c index 5517f20f310c..ee9b054dcc24 100644 --- a/drivers/soc/qcom/qdsp6v2/apr.c +++ b/drivers/soc/qcom/qdsp6v2/apr.c @@ -304,6 +304,7 @@ int apr_send_pkt(void *handle, uint32_t *buf) uint16_t dest_id; uint16_t client_id; uint16_t w_len; + int rc; unsigned long flags; if (!handle || !buf) { @@ -345,14 +346,23 @@ int apr_send_pkt(void *handle, uint32_t *buf) APR_PKT_INFO("Tx: dest_svc[%d], opcode[0x%X], size[%d]", hdr->dest_svc, hdr->opcode, hdr->pkt_size); - w_len = apr_tal_write(clnt->handle, buf, + rc = apr_tal_write(clnt->handle, buf, (struct apr_pkt_priv *)&svc->pkt_owner, hdr->pkt_size); - if (w_len != hdr->pkt_size) - pr_err("Unable to write APR pkt successfully: %d\n", w_len); + if (rc >= 0) { + w_len = rc; + if (w_len != hdr->pkt_size) { + pr_err("%s: Unable to write whole APR pkt successfully: %d\n", + __func__, rc); + rc = -EINVAL; + } + } else { + pr_err("%s: Write APR pkt failed with error %d\n", + __func__, rc); + } spin_unlock_irqrestore(&svc->w_lock, flags); - return w_len; + return rc; } int apr_pkt_config(void *handle, struct apr_pkt_cfg *cfg) diff --git a/drivers/soc/qcom/secure_buffer.c b/drivers/soc/qcom/secure_buffer.c index e7dbcac064aa..d9ebc1edda9c 100644 --- a/drivers/soc/qcom/secure_buffer.c +++ b/drivers/soc/qcom/secure_buffer.c @@ -418,6 +418,8 @@ const char *msm_secure_vmid_to_string(int secure_vmid) return "VMID_WLAN"; case VMID_WLAN_CE: return "VMID_WLAN_CE"; + case VMID_CP_CAMERA_PREVIEW: + return "VMID_CP_CAMERA_PREVIEW"; case VMID_INVAL: return "VMID_INVAL"; default: diff --git a/drivers/staging/android/ion/msm/msm_ion.c b/drivers/staging/android/ion/msm/msm_ion.c index cd420c429031..592c603b1780 100644 --- a/drivers/staging/android/ion/msm/msm_ion.c +++ b/drivers/staging/android/ion/msm/msm_ion.c @@ -632,7 +632,8 @@ bool is_secure_vmid_valid(int vmid) vmid == VMID_CP_NON_PIXEL || vmid == VMID_CP_CAMERA || vmid == VMID_CP_SEC_DISPLAY || - vmid == VMID_CP_APP); + vmid == VMID_CP_APP || + vmid == VMID_CP_CAMERA_PREVIEW); } int get_secure_vmid(unsigned long flags) @@ -651,6 +652,8 @@ int get_secure_vmid(unsigned long flags) return VMID_CP_SEC_DISPLAY; if (flags & ION_FLAG_CP_APP) return VMID_CP_APP; + if (flags & ION_FLAG_CP_CAMERA_PREVIEW) + return VMID_CP_CAMERA_PREVIEW; return -EINVAL; } /* fix up the cases where the ioctl direction bits are incorrect */ diff --git a/drivers/staging/android/uapi/msm_ion.h b/drivers/staging/android/uapi/msm_ion.h index b3c29826834e..54a4672ff143 100644 --- a/drivers/staging/android/uapi/msm_ion.h +++ b/drivers/staging/android/uapi/msm_ion.h @@ -3,6 +3,8 @@ #include "ion.h" +#define ION_BIT(nr) (1UL << (nr)) + enum msm_ion_heap_types { ION_HEAP_TYPE_MSM_START = ION_HEAP_TYPE_CUSTOM + 1, ION_HEAP_TYPE_SECURE_DMA = ION_HEAP_TYPE_MSM_START, @@ -76,39 +78,41 @@ enum cp_mem_usage { * Flags to be used when allocating from the secure heap for * content protection */ -#define ION_FLAG_CP_TOUCH (1 << 17) -#define ION_FLAG_CP_BITSTREAM (1 << 18) -#define ION_FLAG_CP_PIXEL (1 << 19) -#define ION_FLAG_CP_NON_PIXEL (1 << 20) -#define ION_FLAG_CP_CAMERA (1 << 21) -#define ION_FLAG_CP_HLOS (1 << 22) -#define ION_FLAG_CP_HLOS_FREE (1 << 23) -#define ION_FLAG_CP_SEC_DISPLAY (1 << 25) -#define ION_FLAG_CP_APP (1 << 26) +#define ION_FLAG_CP_TOUCH ION_BIT(17) +#define ION_FLAG_CP_BITSTREAM ION_BIT(18) +#define ION_FLAG_CP_PIXEL ION_BIT(19) +#define ION_FLAG_CP_NON_PIXEL ION_BIT(20) +#define ION_FLAG_CP_CAMERA ION_BIT(21) +#define ION_FLAG_CP_HLOS ION_BIT(22) +#define ION_FLAG_CP_HLOS_FREE ION_BIT(23) +#define ION_FLAG_CP_SEC_DISPLAY ION_BIT(25) +#define ION_FLAG_CP_APP ION_BIT(26) +#define ION_FLAG_CP_CAMERA_PREVIEW ION_BIT(27) + /** * Flag to allow non continguous allocation of memory from secure * heap */ -#define ION_FLAG_ALLOW_NON_CONTIG (1 << 24) +#define ION_FLAG_ALLOW_NON_CONTIG ION_BIT(24) /** * Flag to use when allocating to indicate that a heap is secure. */ -#define ION_FLAG_SECURE (1 << ION_HEAP_ID_RESERVED) +#define ION_FLAG_SECURE ION_BIT(ION_HEAP_ID_RESERVED) /** * Flag for clients to force contiguous memort allocation * * Use of this flag is carefully monitored! */ -#define ION_FLAG_FORCE_CONTIGUOUS (1 << 30) +#define ION_FLAG_FORCE_CONTIGUOUS ION_BIT(30) /* * Used in conjunction with heap which pool memory to force an allocation * to come from the page allocator directly instead of from the pool allocation */ -#define ION_FLAG_POOL_FORCE_ALLOC (1 << 16) +#define ION_FLAG_POOL_FORCE_ALLOC ION_BIT(16) /** * Deprecated! Please use the corresponding ION_FLAG_* @@ -119,7 +123,7 @@ enum cp_mem_usage { /** * Macro should be used with ion_heap_ids defined above. */ -#define ION_HEAP(bit) (1 << (bit)) +#define ION_HEAP(bit) ION_BIT(bit) #define ION_ADSP_HEAP_NAME "adsp" #define ION_SYSTEM_HEAP_NAME "system" diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 9fb05bbf3e74..07867ead2413 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -123,6 +123,9 @@ static int dwc3_init_usb_phys(struct dwc3 *dwc) return ret; } + if (dwc->maximum_speed == USB_SPEED_HIGH) + goto generic_phy_init; + ret = usb_phy_init(dwc->usb3_phy); if (ret == -EBUSY) { /* @@ -135,6 +138,8 @@ static int dwc3_init_usb_phys(struct dwc3 *dwc) __func__, ret); return ret; } + +generic_phy_init: ret = phy_init(dwc->usb2_generic_phy); if (ret < 0) return ret; @@ -159,7 +164,9 @@ static int dwc3_core_reset(struct dwc3 *dwc) /* Reset PHYs */ usb_phy_reset(dwc->usb2_phy); - usb_phy_reset(dwc->usb3_phy); + + if (dwc->maximum_speed == USB_SPEED_SUPER) + usb_phy_reset(dwc->usb3_phy); /* Initialize PHYs */ ret = dwc3_init_usb_phys(dwc); diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index 7ce9ff925117..4a4f1083198c 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -1923,7 +1923,7 @@ static int dwc3_msm_suspend(struct dwc3_msm *mdwc) usb_phy_set_suspend(mdwc->hs_phy, 1); /* Suspend SS PHY */ - if (can_suspend_ssphy) { + if (dwc->maximum_speed == USB_SPEED_SUPER && can_suspend_ssphy) { /* indicate phy about SS mode */ if (dwc3_msm_is_superspeed(mdwc)) mdwc->ss_phy->flags |= DEVICE_IN_SS_MODE; @@ -2068,7 +2068,8 @@ static int dwc3_msm_resume(struct dwc3_msm *mdwc) clk_prepare_enable(mdwc->bus_aggr_clk); /* Resume SS PHY */ - if (mdwc->lpm_flags & MDWC3_SS_PHY_SUSPEND) { + if (dwc->maximum_speed == USB_SPEED_SUPER && + mdwc->lpm_flags & MDWC3_SS_PHY_SUSPEND) { mdwc->ss_phy->flags &= ~(PHY_LANE_A | PHY_LANE_B); if (mdwc->typec_orientation == ORIENTATION_CC1) mdwc->ss_phy->flags |= PHY_LANE_A; @@ -2422,9 +2423,11 @@ static int dwc3_msm_id_notifier(struct notifier_block *nb, unsigned long event, void *ptr) { struct dwc3_msm *mdwc = container_of(nb, struct dwc3_msm, id_nb); + struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); struct extcon_dev *edev = ptr; enum dwc3_id_state id; int cc_state; + int speed; if (!edev) { dev_err(mdwc->dev, "%s: edev null\n", __func__); @@ -2444,6 +2447,9 @@ static int dwc3_msm_id_notifier(struct notifier_block *nb, dbg_event(0xFF, "cc_state", mdwc->typec_orientation); + speed = extcon_get_cable_state_(edev, EXTCON_USB_SPEED); + dwc->maximum_speed = (speed == 0) ? USB_SPEED_HIGH : USB_SPEED_SUPER; + if (mdwc->id_state != id) { mdwc->id_state = id; dbg_event(0xFF, "id_state", mdwc->id_state); @@ -2461,6 +2467,7 @@ static int dwc3_msm_vbus_notifier(struct notifier_block *nb, struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); struct extcon_dev *edev = ptr; int cc_state; + int speed; if (!edev) { dev_err(mdwc->dev, "%s: edev null\n", __func__); @@ -2481,6 +2488,9 @@ static int dwc3_msm_vbus_notifier(struct notifier_block *nb, dbg_event(0xFF, "cc_state", mdwc->typec_orientation); + speed = extcon_get_cable_state_(edev, EXTCON_USB_SPEED); + dwc->maximum_speed = (speed == 0) ? USB_SPEED_HIGH : USB_SPEED_SUPER; + mdwc->vbus_active = event; if (dwc->is_drd && !mdwc->in_restart) { dbg_event(0xFF, "Q RW (vbus)", mdwc->vbus_active); @@ -3026,11 +3036,13 @@ static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on) if (on) { dev_dbg(mdwc->dev, "%s: turn on host\n", __func__); + mdwc->hs_phy->flags |= PHY_HOST_MODE; + if (dwc->maximum_speed == USB_SPEED_SUPER) + mdwc->ss_phy->flags |= PHY_HOST_MODE; + pm_runtime_get_sync(mdwc->dev); dbg_event(0xFF, "StrtHost gync", atomic_read(&mdwc->dev->power.usage_count)); - mdwc->hs_phy->flags |= PHY_HOST_MODE; - mdwc->ss_phy->flags |= PHY_HOST_MODE; usb_phy_notify_connect(mdwc->hs_phy, USB_SPEED_HIGH); if (!IS_ERR(mdwc->vbus_reg)) ret = regulator_enable(mdwc->vbus_reg); diff --git a/drivers/usb/gadget/function/f_cdev.c b/drivers/usb/gadget/function/f_cdev.c index b288a848aaa0..3b7b23cfde44 100644 --- a/drivers/usb/gadget/function/f_cdev.c +++ b/drivers/usb/gadget/function/f_cdev.c @@ -50,6 +50,9 @@ #define MODULE_NAME "msm_usb_bridge" #define NUM_INSTANCE 2 +#define MAX_CDEV_INST_NAME 15 +#define MAX_CDEV_FUNC_NAME 5 + #define BRIDGE_RX_QUEUE_SIZE 8 #define BRIDGE_RX_BUF_SIZE 2048 #define BRIDGE_TX_QUEUE_SIZE 8 @@ -823,6 +826,7 @@ static void cser_free_inst(struct usb_function_instance *fi) device_destroy(fcdev_classp, MKDEV(major, opts->port->minor)); cdev_del(&opts->port->fcdev_cdev); usb_cser_chardev_deinit(); + kfree(opts->func_name); kfree(opts->port); kfree(opts); } @@ -1647,16 +1651,6 @@ static struct configfs_item_operations cserial_item_ops = { .release = cserial_attr_release, }; -static ssize_t usb_cser_port_num_show(struct config_item *item, char *page) -{ - return sprintf(page, "%u\n", to_f_cdev_opts(item)->port_num); -} - -static ssize_t usb_cser_func_name_show(struct config_item *item, char *page) -{ - return sprintf(page, "%s\n", to_f_cdev_opts(item)->func_name); -} - static ssize_t usb_cser_status_show(struct config_item *item, char *page) { struct f_cdev *port = to_f_cdev_opts(item)->port; @@ -1722,12 +1716,8 @@ static ssize_t usb_cser_status_store(struct config_item *item, return len; } -CONFIGFS_ATTR_RO(usb_cser_, port_num); -CONFIGFS_ATTR_RO(usb_cser_, func_name); CONFIGFS_ATTR(usb_cser_, status); static struct configfs_attribute *cserial_attrs[] = { - &usb_cser_attr_port_num, - &usb_cser_attr_func_name, &usb_cser_attr_status, NULL, }; @@ -1748,7 +1738,7 @@ static int cser_set_inst_name(struct usb_function_instance *f, const char *name) struct f_cdev *port; name_len = strlen(name) + 1; - if (name_len > 15) + if (name_len > MAX_CDEV_INST_NAME) return -ENAMETOOLONG; /* expect name as cdev.<func>.<port_num> */ @@ -1760,6 +1750,9 @@ static int cser_set_inst_name(struct usb_function_instance *f, const char *name) /* get function name */ str_size = name_len - strlen(str); + if (str_size > MAX_CDEV_FUNC_NAME) + return -ENAMETOOLONG; + ptr = kstrndup(name, str_size - 1, GFP_KERNEL); if (!ptr) { pr_err("error:%ld\n", PTR_ERR(ptr)); diff --git a/drivers/usb/pd/policy_engine.c b/drivers/usb/pd/policy_engine.c index 82ae0b4fe135..a1451a2d4826 100644 --- a/drivers/usb/pd/policy_engine.c +++ b/drivers/usb/pd/policy_engine.c @@ -242,6 +242,12 @@ static void *usbpd_ipc_log; static int min_sink_current = 900; module_param(min_sink_current, int, S_IRUSR | S_IWUSR); +static bool ss_host; +module_param(ss_host, bool, S_IRUSR | S_IWUSR); + +static bool ss_dev = true; +module_param(ss_dev, bool, S_IRUSR | S_IWUSR); + static const u32 default_src_caps[] = { 0x36019096 }; /* VSafe5V @ 1.5A */ static const u32 default_snk_caps[] = { 0x2601905A, /* 5V @ 900mA */ @@ -318,6 +324,7 @@ static const unsigned int usbpd_extcon_cable[] = { EXTCON_USB, EXTCON_USB_HOST, EXTCON_USB_CC, + EXTCON_USB_SPEED, EXTCON_NONE, }; @@ -685,6 +692,10 @@ static void usbpd_set_state(struct usbpd *pd, enum usbpd_state next_state) SVDM_CMD_TYPE_INITIATOR, 0, NULL, 0); + extcon_set_cable_state_(pd->extcon, EXTCON_USB_CC, + is_cable_flipped(pd)); + extcon_set_cable_state_(pd->extcon, EXTCON_USB_SPEED, + ss_host); extcon_set_cable_state_(pd->extcon, EXTCON_USB_HOST, 1); } @@ -755,6 +766,8 @@ static void usbpd_set_state(struct usbpd *pd, enum usbpd_state next_state) EXTCON_USB_CC, is_cable_flipped(pd)); extcon_set_cable_state_(pd->extcon, + EXTCON_USB_SPEED, ss_dev); + extcon_set_cable_state_(pd->extcon, EXTCON_USB, 1); } } @@ -852,6 +865,8 @@ static void usbpd_set_state(struct usbpd *pd, enum usbpd_state next_state) pd->current_dr = DR_UFP; extcon_set_cable_state_(pd->extcon, EXTCON_USB_CC, is_cable_flipped(pd)); + extcon_set_cable_state_(pd->extcon, EXTCON_USB_SPEED, + ss_dev); extcon_set_cable_state_(pd->extcon, EXTCON_USB, 1); pd_phy_update_roles(pd->current_dr, pd->current_pr); } @@ -1194,12 +1209,14 @@ static void dr_swap(struct usbpd *pd) extcon_set_cable_state_(pd->extcon, EXTCON_USB_HOST, 0); extcon_set_cable_state_(pd->extcon, EXTCON_USB_CC, is_cable_flipped(pd)); + extcon_set_cable_state_(pd->extcon, EXTCON_USB_SPEED, ss_dev); extcon_set_cable_state_(pd->extcon, EXTCON_USB, 1); pd->current_dr = DR_UFP; } else if (pd->current_dr == DR_UFP) { extcon_set_cable_state_(pd->extcon, EXTCON_USB, 0); extcon_set_cable_state_(pd->extcon, EXTCON_USB_CC, is_cable_flipped(pd)); + extcon_set_cable_state_(pd->extcon, EXTCON_USB_SPEED, ss_host); extcon_set_cable_state_(pd->extcon, EXTCON_USB_HOST, 1); pd->current_dr = DR_DFP; @@ -1251,6 +1268,8 @@ static void usbpd_sm(struct work_struct *w) pd->caps_count = 0; pd->hard_reset_count = 0; pd->src_cap_id = 0; + pd->requested_voltage = 0; + pd->requested_current = 0; memset(&pd->received_pdos, 0, sizeof(pd->received_pdos)); val.intval = 0; @@ -1345,6 +1364,8 @@ static void usbpd_sm(struct work_struct *w) extcon_set_cable_state_(pd->extcon, EXTCON_USB_CC, is_cable_flipped(pd)); extcon_set_cable_state_(pd->extcon, + EXTCON_USB_SPEED, ss_host); + extcon_set_cable_state_(pd->extcon, EXTCON_USB_HOST, 1); } else if (pd->caps_count >= PD_CAPS_COUNT) { usbpd_dbg(&pd->dev, "Src CapsCounter exceeded, disabling PD\n"); @@ -1748,6 +1769,20 @@ static void usbpd_sm(struct work_struct *w) pd->rx_msg_type = pd->rx_msg_len = 0; } +static inline const char *src_current(enum power_supply_typec_mode typec_mode) +{ + switch (typec_mode) { + case POWER_SUPPLY_TYPEC_SOURCE_DEFAULT: + return "default"; + case POWER_SUPPLY_TYPEC_SOURCE_MEDIUM: + return "medium - 1.5A"; + case POWER_SUPPLY_TYPEC_SOURCE_HIGH: + return "high - 3.0A"; + default: + return ""; + } +} + static int psy_changed(struct notifier_block *nb, unsigned long evt, void *ptr) { struct usbpd *pd = container_of(nb, struct usbpd, psy_nb); @@ -1848,7 +1883,8 @@ static int psy_changed(struct notifier_block *nb, unsigned long evt, void *ptr) case POWER_SUPPLY_TYPEC_SOURCE_DEFAULT: case POWER_SUPPLY_TYPEC_SOURCE_MEDIUM: case POWER_SUPPLY_TYPEC_SOURCE_HIGH: - usbpd_info(&pd->dev, "Type-C Source connected\n"); + usbpd_info(&pd->dev, "Type-C Source (%s) connected\n", + src_current(typec_mode)); if (pd->current_pr != PR_SINK) { pd->current_pr = PR_SINK; queue_work(pd->wq, &pd->sm_work); @@ -1858,7 +1894,9 @@ static int psy_changed(struct notifier_block *nb, unsigned long evt, void *ptr) /* Source states */ case POWER_SUPPLY_TYPEC_SINK_POWERED_CABLE: case POWER_SUPPLY_TYPEC_SINK: - usbpd_info(&pd->dev, "Type-C Sink connected\n"); + usbpd_info(&pd->dev, "Type-C Sink%s connected\n", + typec_mode == POWER_SUPPLY_TYPEC_SINK ? + "" : " (powered)"); if (pd->current_pr != PR_SRC) { pd->current_pr = PR_SRC; queue_work(pd->wq, &pd->sm_work); diff --git a/fs/ecryptfs/kthread.c b/fs/ecryptfs/kthread.c index 866bb18efefe..e818f5ac7a26 100644 --- a/fs/ecryptfs/kthread.c +++ b/fs/ecryptfs/kthread.c @@ -25,6 +25,7 @@ #include <linux/slab.h> #include <linux/wait.h> #include <linux/mount.h> +#include <linux/file.h> #include "ecryptfs_kernel.h" struct ecryptfs_open_req { @@ -147,7 +148,7 @@ int ecryptfs_privileged_open(struct file **lower_file, flags |= IS_RDONLY(d_inode(lower_dentry)) ? O_RDONLY : O_RDWR; (*lower_file) = dentry_open(&req.path, flags, cred); if (!IS_ERR(*lower_file)) - goto out; + goto have_file; if ((flags & O_ACCMODE) == O_RDONLY) { rc = PTR_ERR((*lower_file)); goto out; @@ -165,8 +166,16 @@ int ecryptfs_privileged_open(struct file **lower_file, mutex_unlock(&ecryptfs_kthread_ctl.mux); wake_up(&ecryptfs_kthread_ctl.wait); wait_for_completion(&req.done); - if (IS_ERR(*lower_file)) + if (IS_ERR(*lower_file)) { rc = PTR_ERR(*lower_file); + goto out; + } +have_file: + if ((*lower_file)->f_op->mmap == NULL) { + fput(*lower_file); + *lower_file = NULL; + rc = -EMEDIUMTYPE; + } out: return rc; } diff --git a/fs/proc/root.c b/fs/proc/root.c index 361ab4ee42fc..ec649c92d270 100644 --- a/fs/proc/root.c +++ b/fs/proc/root.c @@ -121,6 +121,13 @@ static struct dentry *proc_mount(struct file_system_type *fs_type, if (IS_ERR(sb)) return ERR_CAST(sb); + /* + * procfs isn't actually a stacking filesystem; however, there is + * too much magic going on inside it to permit stacking things on + * top of it + */ + sb->s_stack_depth = FILESYSTEM_MAX_STACK_DEPTH; + if (!proc_parse_options(options, ns)) { deactivate_locked_super(sb); return ERR_PTR(-EINVAL); diff --git a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h index 6860d78e020e..0bbcbd28af33 100644 --- a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h +++ b/include/dt-bindings/clock/qcom,gcc-msmfalcon.h @@ -14,173 +14,189 @@ #ifndef _DT_BINDINGS_CLK_MSM_GCC_FALCON_H #define _DT_BINDINGS_CLK_MSM_GCC_FALCON_H -#define BIMC_HMSS_AXI_CLK_SRC 0 -#define BLSP1_QUP1_I2C_APPS_CLK_SRC 1 -#define BLSP1_QUP1_SPI_APPS_CLK_SRC 2 -#define BLSP1_QUP2_I2C_APPS_CLK_SRC 3 -#define BLSP1_QUP2_SPI_APPS_CLK_SRC 4 -#define BLSP1_QUP3_I2C_APPS_CLK_SRC 5 -#define BLSP1_QUP3_SPI_APPS_CLK_SRC 6 -#define BLSP1_QUP4_I2C_APPS_CLK_SRC 7 -#define BLSP1_QUP4_SPI_APPS_CLK_SRC 8 -#define BLSP1_UART1_APPS_CLK_SRC 9 -#define BLSP1_UART2_APPS_CLK_SRC 10 -#define BLSP2_QUP1_I2C_APPS_CLK_SRC 11 -#define BLSP2_QUP1_SPI_APPS_CLK_SRC 12 -#define BLSP2_QUP2_I2C_APPS_CLK_SRC 13 -#define BLSP2_QUP2_SPI_APPS_CLK_SRC 14 -#define BLSP2_QUP3_I2C_APPS_CLK_SRC 15 -#define BLSP2_QUP3_SPI_APPS_CLK_SRC 16 -#define BLSP2_QUP4_I2C_APPS_CLK_SRC 17 -#define BLSP2_QUP4_SPI_APPS_CLK_SRC 18 -#define BLSP2_UART1_APPS_CLK_SRC 19 -#define BLSP2_UART2_APPS_CLK_SRC 20 -#define GCC_AGGRE2_UFS_AXI_CLK 21 -#define GCC_AGGRE2_USB3_AXI_CLK 22 -#define GCC_BIMC_GFX_CLK 23 -#define GCC_BIMC_HMSS_AXI_CLK 24 -#define GCC_BIMC_MSS_Q6_AXI_CLK 25 -#define GCC_BLSP1_AHB_CLK 26 -#define GCC_BLSP1_QUP1_I2C_APPS_CLK 27 -#define GCC_BLSP1_QUP1_SPI_APPS_CLK 28 -#define GCC_BLSP1_QUP2_I2C_APPS_CLK 29 -#define GCC_BLSP1_QUP2_SPI_APPS_CLK 30 -#define GCC_BLSP1_QUP3_I2C_APPS_CLK 31 -#define GCC_BLSP1_QUP3_SPI_APPS_CLK 32 -#define GCC_BLSP1_QUP4_I2C_APPS_CLK 33 -#define GCC_BLSP1_QUP4_SPI_APPS_CLK 34 -#define GCC_BLSP1_UART1_APPS_CLK 35 -#define GCC_BLSP1_UART2_APPS_CLK 36 -#define GCC_BLSP2_AHB_CLK 37 -#define GCC_BLSP2_QUP1_I2C_APPS_CLK 38 -#define GCC_BLSP2_QUP1_SPI_APPS_CLK 39 -#define GCC_BLSP2_QUP2_I2C_APPS_CLK 40 -#define GCC_BLSP2_QUP2_SPI_APPS_CLK 41 -#define GCC_BLSP2_QUP3_I2C_APPS_CLK 42 -#define GCC_BLSP2_QUP3_SPI_APPS_CLK 43 -#define GCC_BLSP2_QUP4_I2C_APPS_CLK 44 -#define GCC_BLSP2_QUP4_SPI_APPS_CLK 45 -#define GCC_BLSP2_UART1_APPS_CLK 46 -#define GCC_BLSP2_UART2_APPS_CLK 47 -#define GCC_BOOT_ROM_AHB_CLK 48 -#define GCC_CFG_NOC_USB2_AXI_CLK 49 -#define GCC_CFG_NOC_USB3_AXI_CLK 50 -#define GCC_GLM_AHB_CLK 51 -#define GCC_GLM_CLK 52 -#define GCC_GP1_CLK 53 -#define GCC_GP2_CLK 54 -#define GCC_GP3_CLK 55 -#define GCC_GPU_BIMC_GFX_CLK 56 -#define GCC_GPU_BIMC_GFX_SRC_CLK 57 -#define GCC_GPU_CFG_AHB_CLK 58 -#define GCC_GPU_SNOC_DVM_GFX_CLK 59 -#define GCC_HMSS_AHB_CLK 60 -#define GCC_HMSS_DVM_BUS_CLK 61 -#define GCC_HMSS_RBCPR_CLK 62 -#define GCC_MMSS_NOC_CFG_AHB_CLK 63 -#define GCC_MMSS_QM_AHB_CLK 64 -#define GCC_MMSS_QM_CORE_CLK 65 -#define GCC_MMSS_SYS_NOC_AXI_CLK 66 -#define GCC_PDM2_CLK 67 -#define GCC_PDM_AHB_CLK 68 -#define GCC_PRNG_AHB_CLK 69 -#define GCC_QSPI_AHB_CLK 70 -#define GCC_QSPI_SER_CLK 71 -#define GCC_SDCC1_AHB_CLK 72 -#define GCC_SDCC1_APPS_CLK 73 -#define GCC_SDCC1_ICE_CORE_CLK 74 -#define GCC_SDCC2_AHB_CLK 75 -#define GCC_SDCC2_APPS_CLK 76 -#define GCC_UFS_AHB_CLK 77 -#define GCC_UFS_AXI_CLK 78 -#define GCC_UFS_ICE_CORE_CLK 79 -#define GCC_UFS_PHY_AUX_CLK 80 -#define GCC_UFS_RX_SYMBOL_0_CLK 81 -#define GCC_UFS_RX_SYMBOL_1_CLK 82 -#define GCC_UFS_TX_SYMBOL_0_CLK 83 -#define GCC_UFS_UNIPRO_CORE_CLK 84 -#define GCC_USB20_MASTER_CLK 85 -#define GCC_USB20_MOCK_UTMI_CLK 86 -#define GCC_USB20_SLEEP_CLK 87 -#define GCC_USB30_MASTER_CLK 88 -#define GCC_USB30_MOCK_UTMI_CLK 89 -#define GCC_USB30_SLEEP_CLK 90 -#define GCC_USB3_PHY_AUX_CLK 91 -#define GCC_USB3_PHY_PIPE_CLK 92 -#define GCC_USB_PHY_CFG_AHB2PHY_CLK 93 -#define GCC_WCSS_AHB_S0_CLK 94 -#define GCC_WCSS_AXI_M_CLK 95 -#define GCC_WCSS_ECAHB_CLK 96 -#define GCC_WCSS_SHDREG_AHB_CLK 97 -#define GLM_CLK_SRC 98 -#define GP1_CLK_SRC 99 -#define GP2_CLK_SRC 100 -#define GP3_CLK_SRC 101 -#define GPLL0 102 -#define GPLL0_OUT_AUX 103 -#define GPLL0_OUT_AUX2 104 -#define GPLL0_OUT_EARLY 105 -#define GPLL0_OUT_MAIN 106 -#define GPLL0_OUT_TEST 107 -#define GPLL1 108 -#define GPLL1_OUT_AUX 109 -#define GPLL1_OUT_AUX2 110 -#define GPLL1_OUT_EARLY 111 -#define GPLL1_OUT_MAIN 112 -#define GPLL1_OUT_TEST 113 -#define GPLL2 114 -#define GPLL2_OUT_AUX 115 -#define GPLL2_OUT_AUX2 116 -#define GPLL2_OUT_EARLY 117 -#define GPLL2_OUT_MAIN 118 -#define GPLL2_OUT_TEST 119 -#define GPLL3 120 -#define GPLL3_OUT_AUX 121 -#define GPLL3_OUT_AUX2 122 -#define GPLL3_OUT_EARLY 123 -#define GPLL3_OUT_MAIN 124 -#define GPLL3_OUT_TEST 125 -#define GPLL4 126 -#define GPLL4_OUT_AUX 127 -#define GPLL4_OUT_AUX2 128 -#define GPLL4_OUT_EARLY 129 -#define GPLL4_OUT_MAIN 130 -#define GPLL4_OUT_TEST 131 -#define GPLL5 132 -#define GPLL5_OUT_AUX 133 -#define GPLL5_OUT_AUX2 134 -#define GPLL5_OUT_EARLY 135 -#define GPLL5_OUT_MAIN 136 -#define GPLL5_OUT_TEST 137 -#define GPLL6 138 -#define GPLL6_OUT_AUX 139 -#define GPLL6_OUT_AUX2 140 -#define GPLL6_OUT_EARLY 141 -#define GPLL6_OUT_MAIN 142 -#define GPLL6_OUT_TEST 143 -#define HMSS_AHB_CLK_SRC 144 -#define HMSS_GPLL0_CLK_SRC 145 -#define HMSS_GPLL4_CLK_SRC 146 -#define HMSS_RBCPR_CLK_SRC 147 -#define MMSS_QM_CORE_CLK_SRC 148 -#define PDM2_CLK_SRC 149 -#define QSPI_SER_CLK_SRC 150 -#define SDCC1_APPS_CLK_SRC 151 -#define SDCC1_ICE_CORE_CLK_SRC 152 -#define SDCC2_APPS_CLK_SRC 153 -#define UFS_AXI_CLK_SRC 154 -#define UFS_ICE_CORE_CLK_SRC 155 -#define UFS_PHY_AUX_CLK_SRC 156 -#define UFS_UNIPRO_CORE_CLK_SRC 157 -#define USB20_MASTER_CLK_SRC 158 -#define USB20_MOCK_UTMI_CLK_SRC 159 -#define USB30_MASTER_CLK_SRC 160 -#define USB30_MOCK_UTMI_CLK_SRC 161 -#define USB3_PHY_AUX_CLK_SRC 162 +/* Hardware/Dummy/Voter clocks */ +#define GCC_XO 0 +#define GCC_GPLL0_EARLY_DIV 1 +#define GCC_GPLL1_EARLY_DIV 2 +#define GCC_CE1_AHB_M_CLK 3 +#define GCC_CE1_AXI_M_CLK 4 -#define UFS_GDSC 0 -#define USB_30_GDSC 1 +/* RCGs and Branches */ +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 10 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 11 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 12 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 13 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 14 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 15 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 16 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 17 +#define BLSP1_UART1_APPS_CLK_SRC 18 +#define BLSP1_UART2_APPS_CLK_SRC 19 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 20 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 21 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 22 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 23 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 24 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 25 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 26 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 27 +#define BLSP2_UART1_APPS_CLK_SRC 28 +#define BLSP2_UART2_APPS_CLK_SRC 29 +#define GCC_AGGRE2_UFS_AXI_CLK 30 +#define GCC_AGGRE2_USB3_AXI_CLK 31 +#define GCC_BIMC_GFX_CLK 32 +#define GCC_BIMC_HMSS_AXI_CLK 33 +#define GCC_BIMC_MSS_Q6_AXI_CLK 34 +#define GCC_BLSP1_AHB_CLK 35 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 36 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 37 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 38 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 39 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 40 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 41 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 42 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 43 +#define GCC_BLSP1_UART1_APPS_CLK 44 +#define GCC_BLSP1_UART2_APPS_CLK 45 +#define GCC_BLSP2_AHB_CLK 46 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 47 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 48 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 49 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 50 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 51 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 52 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 53 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 54 +#define GCC_BLSP2_UART1_APPS_CLK 55 +#define GCC_BLSP2_UART2_APPS_CLK 56 +#define GCC_BOOT_ROM_AHB_CLK 57 +#define GCC_CFG_NOC_USB2_AXI_CLK 58 +#define GCC_CFG_NOC_USB3_AXI_CLK 59 +#define GCC_DCC_AHB_CLK 60 +#define GCC_GP1_CLK 61 +#define GCC_GP2_CLK 62 +#define GCC_GP3_CLK 63 +#define GCC_GPU_BIMC_GFX_CLK 64 +#define GCC_GPU_BIMC_GFX_SRC_CLK 65 +#define GCC_GPU_CFG_AHB_CLK 66 +#define GCC_GPU_GPLL0_CLK 67 +#define GCC_GPU_GPLL0_DIV_CLK 68 +#define GCC_GPU_SNOC_DVM_GFX_CLK 69 +#define GCC_HMSS_AHB_CLK 70 +#define GCC_HMSS_DVM_BUS_CLK 71 +#define GCC_HMSS_RBCPR_CLK 72 +#define GCC_MMSS_GPLL0_CLK 73 +#define GCC_MMSS_GPLL0_DIV_CLK 74 +#define GCC_MMSS_NOC_CFG_AHB_CLK 75 +#define GCC_MMSS_SYS_NOC_AXI_CLK 76 +#define GCC_MSS_CFG_AHB_CLK 77 +#define GCC_MSS_GPLL0_DIV_CLK 78 +#define GCC_MSS_MNOC_BIMC_AXI_CLK 79 +#define GCC_MSS_Q6_BIMC_AXI_CLK 80 +#define GCC_MSS_SNOC_AXI_CLK 81 +#define GCC_PDM2_CLK 82 +#define GCC_PDM_AHB_CLK 83 +#define GCC_PRNG_AHB_CLK 84 +#define GCC_QSPI_AHB_CLK 85 +#define GCC_QSPI_SER_CLK 86 +#define GCC_RX0_USB2_CLKREF_CLK 87 +#define GCC_RX1_USB2_CLKREF_CLK 88 +#define GCC_RX2_QLINK_CLKREF_CLK 89 +#define GCC_SDCC1_AHB_CLK 90 +#define GCC_SDCC1_APPS_CLK 91 +#define GCC_SDCC1_ICE_CORE_CLK 92 +#define GCC_SDCC2_AHB_CLK 93 +#define GCC_SDCC2_APPS_CLK 94 +#define GCC_UFS_AHB_CLK 95 +#define GCC_UFS_AXI_CLK 96 +#define GCC_UFS_CLKREF_CLK 97 +#define GCC_UFS_ICE_CORE_CLK 98 +#define GCC_UFS_PHY_AUX_CLK 99 +#define GCC_UFS_RX_SYMBOL_0_CLK 100 +#define GCC_UFS_RX_SYMBOL_1_CLK 101 +#define GCC_UFS_TX_SYMBOL_0_CLK 102 +#define GCC_UFS_UNIPRO_CORE_CLK 103 +#define GCC_USB20_MASTER_CLK 104 +#define GCC_USB20_MOCK_UTMI_CLK 105 +#define GCC_USB20_SLEEP_CLK 106 +#define GCC_USB30_MASTER_CLK 107 +#define GCC_USB30_MOCK_UTMI_CLK 108 +#define GCC_USB30_SLEEP_CLK 109 +#define GCC_USB3_CLKREF_CLK 110 +#define GCC_USB3_PHY_AUX_CLK 111 +#define GCC_USB3_PHY_PIPE_CLK 112 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 113 +#define GP1_CLK_SRC 114 +#define GP2_CLK_SRC 115 +#define GP3_CLK_SRC 116 +#define GPLL0 117 +#define GPLL0_OUT_AUX 118 +#define GPLL0_OUT_AUX2 119 +#define GPLL0_OUT_EARLY 120 +#define GPLL0_OUT_MAIN 121 +#define GPLL0_OUT_TEST 122 +#define GPLL1 123 +#define GPLL1_OUT_AUX 124 +#define GPLL1_OUT_AUX2 125 +#define GPLL1_OUT_EARLY 126 +#define GPLL1_OUT_MAIN 127 +#define GPLL1_OUT_TEST 128 +#define GPLL2 129 +#define GPLL2_OUT_AUX 130 +#define GPLL2_OUT_AUX2 131 +#define GPLL2_OUT_EARLY 132 +#define GPLL2_OUT_MAIN 133 +#define GPLL2_OUT_TEST 134 +#define GPLL3 135 +#define GPLL3_OUT_AUX 136 +#define GPLL3_OUT_AUX2 137 +#define GPLL3_OUT_EARLY 138 +#define GPLL3_OUT_MAIN 139 +#define GPLL3_OUT_TEST 140 +#define GPLL4 141 +#define GPLL4_OUT_AUX 142 +#define GPLL4_OUT_AUX2 143 +#define GPLL4_OUT_EARLY 144 +#define GPLL4_OUT_MAIN 145 +#define GPLL4_OUT_TEST 146 +#define GPLL5 147 +#define GPLL5_OUT_AUX 148 +#define GPLL5_OUT_AUX2 149 +#define GPLL5_OUT_EARLY 150 +#define GPLL5_OUT_MAIN 151 +#define GPLL5_OUT_TEST 152 +#define GPLL6 153 +#define GPLL6_OUT_AUX 154 +#define GPLL6_OUT_AUX2 155 +#define GPLL6_OUT_EARLY 156 +#define GPLL6_OUT_MAIN 157 +#define GPLL6_OUT_TEST 158 +#define HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 159 +#define HMSS_AHB_CLK_SRC 160 +#define HMSS_GPLL0_CLK_SRC 161 +#define HMSS_GPLL4_CLK_SRC 162 +#define HMSS_RBCPR_CLK_SRC 163 +#define PDM2_CLK_SRC 164 +#define QSPI_SER_CLK_SRC 165 +#define SDCC1_APPS_CLK_SRC 166 +#define SDCC1_ICE_CORE_CLK_SRC 167 +#define SDCC2_APPS_CLK_SRC 168 +#define UFS_AXI_CLK_SRC 169 +#define UFS_ICE_CORE_CLK_SRC 170 +#define UFS_PHY_AUX_CLK_SRC 171 +#define UFS_UNIPRO_CORE_CLK_SRC 172 +#define USB20_MASTER_CLK_SRC 173 +#define USB20_MOCK_UTMI_CLK_SRC 174 +#define USB30_MASTER_CLK_SRC 175 +#define USB30_MOCK_UTMI_CLK_SRC 176 +#define USB3_PHY_AUX_CLK_SRC 177 +#define GPLL0_OUT_MSSCC 178 +#define GCC_UFS_AXI_HW_CTL_CLK 179 +#define GCC_UFS_ICE_CORE_HW_CTL_CLK 180 +#define GCC_UFS_PHY_AUX_HW_CTL_CLK 181 +#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 182 +/* Block resets */ #define GCC_QUSB2PHY_PRIM_BCR 0 #define GCC_QUSB2PHY_SEC_BCR 1 #define GCC_UFS_BCR 2 diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index ee37c5c22f5f..bcaa1a552e8e 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -1,5 +1,6 @@ /* * Copyright 2015 Linaro Limited + * Copyright (c) 2016, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -38,47 +39,31 @@ #define RPM_SFPB_CLK 20 #define RPM_SFPB_A_CLK 21 -/* msm8916 */ -#define RPM_SMD_XO_CLK_SRC 0 -#define RPM_SMD_XO_A_CLK_SRC 1 -#define RPM_SMD_PCNOC_CLK 2 -#define RPM_SMD_PCNOC_A_CLK 3 -#define RPM_SMD_SNOC_CLK 4 -#define RPM_SMD_SNOC_A_CLK 5 -#define RPM_SMD_BIMC_CLK 6 -#define RPM_SMD_BIMC_A_CLK 7 -#define RPM_SMD_QDSS_CLK 8 -#define RPM_SMD_QDSS_A_CLK 9 -#define RPM_SMD_BB_CLK1 10 -#define RPM_SMD_BB_CLK1_A 11 -#define RPM_SMD_BB_CLK2 12 -#define RPM_SMD_BB_CLK2_A 13 -#define RPM_SMD_RF_CLK1 14 -#define RPM_SMD_RF_CLK1_A 15 -#define RPM_SMD_RF_CLK2 16 -#define RPM_SMD_RF_CLK2_A 17 -#define RPM_SMD_BB_CLK1_PIN 18 -#define RPM_SMD_BB_CLK1_A_PIN 19 -#define RPM_SMD_BB_CLK2_PIN 20 -#define RPM_SMD_BB_CLK2_A_PIN 21 -#define RPM_SMD_RF_CLK1_PIN 22 -#define RPM_SMD_RF_CLK1_A_PIN 23 -#define RPM_SMD_RF_CLK2_PIN 24 -#define RPM_SMD_RF_CLK2_A_PIN 25 +/* msm8916 and msm8996 */ +#define RPM_XO_CLK_SRC 0 +#define RPM_XO_A_CLK_SRC 1 +#define RPM_PCNOC_CLK 2 +#define RPM_PCNOC_A_CLK 3 +#define RPM_SNOC_CLK 4 +#define RPM_SNOC_A_CLK 5 +#define RPM_BIMC_CLK 6 +#define RPM_BIMC_A_CLK 7 +#define RPM_QDSS_CLK 8 +#define RPM_QDSS_A_CLK 9 #define RPM_BB_CLK1 10 #define RPM_BB_CLK1_A 11 -#define RPM_BB_CLK2 12 -#define RPM_BB_CLK2_A 13 -#define RPM_RF_CLK1 14 -#define RPM_RF_CLK1_A 15 -#define RPM_RF_CLK2 16 -#define RPM_RF_CLK2_A 17 -#define RPM_BB_CLK1_PIN 18 -#define RPM_BB_CLK1_A_PIN 19 -#define RPM_BB_CLK2_PIN 20 -#define RPM_BB_CLK2_A_PIN 21 -#define RPM_RF_CLK1_PIN 22 -#define RPM_RF_CLK1_A_PIN 23 +#define RPM_BB_CLK1_PIN 12 +#define RPM_BB_CLK1_A_PIN 13 +#define RPM_BB_CLK2 14 +#define RPM_BB_CLK2_A 15 +#define RPM_BB_CLK2_PIN 16 +#define RPM_BB_CLK2_A_PIN 17 +#define RPM_RF_CLK1 18 +#define RPM_RF_CLK1_A 19 +#define RPM_RF_CLK1_PIN 20 +#define RPM_RF_CLK1_A_PIN 21 +#define RPM_RF_CLK2 22 +#define RPM_RF_CLK2_A 23 #define RPM_RF_CLK2_PIN 24 #define RPM_RF_CLK2_A_PIN 25 #define RPM_AGGR1_NOC_CLK 26 @@ -101,5 +86,47 @@ #define RPM_DIV_CLK3_AO 43 #define RPM_LN_BB_CLK 44 #define RPM_LN_BB_A_CLK 45 +#define RPM_LN_BB_CLK1 46 +#define RPM_LN_BB_CLK1_AO 47 +#define RPM_LN_BB_CLK1_PIN 48 +#define RPM_LN_BB_CLK1_PIN_AO 49 +#define RPM_LN_BB_CLK2 50 +#define RPM_LN_BB_CLK2_AO 51 +#define RPM_LN_BB_CLK2_PIN 52 +#define RPM_LN_BB_CLK2_PIN_AO 53 +#define RPM_LN_BB_CLK3 54 +#define RPM_LN_BB_CLK3_AO 55 +#define RPM_LN_BB_CLK3_PIN 56 +#define RPM_LN_BB_CLK3_PIN_AO 57 +#define RPM_CNOC_PERIPH_CLK 58 +#define RPM_CNOC_PERIPH_A_CLK 59 + +/* Voter clocks */ +#define MMSSNOC_AXI_CLK 60 +#define MMSSNOC_AXI_A_CLK 61 +#define MMSSNOC_GDS_CLK 62 +#define BIMC_MSMBUS_CLK 63 +#define BIMC_MSMBUS_A_CLK 64 +#define CNOC_MSMBUS_CLK 65 +#define CNOC_MSMBUS_A_CLK 66 +#define PNOC_KEEPALIVE_A_CLK 67 +#define PNOC_MSMBUS_CLK 68 +#define PNOC_MSMBUS_A_CLK 69 +#define PNOC_PM_CLK 70 +#define PNOC_SPS_CLK 71 +#define MCD_CE1_CLK 72 +#define QCEDEV_CE1_CLK 73 +#define QCRYPTO_CE1_CLK 74 +#define QSEECOM_CE1_CLK 75 +#define SCM_CE1_CLK 76 +#define SNOC_MSMBUS_CLK 77 +#define SNOC_MSMBUS_A_CLK 78 +#define CXO_DWC3_CLK 79 +#define CXO_LPM_CLK 80 +#define CXO_OTG_CLK 81 +#define CXO_PIL_LPASS_CLK 82 +#define CXO_PIL_SSC_CLK 83 +#define CXO_PIL_CDSP_CLK 84 +#define CNOC_PERIPH_KEEPALIVE_A_CLK 85 #endif diff --git a/include/linux/ipa.h b/include/linux/ipa.h index 81da2aaa01e5..e66d388651b8 100644 --- a/include/linux/ipa.h +++ b/include/linux/ipa.h @@ -551,6 +551,7 @@ struct ipa_sys_connect_params { bool skip_ep_cfg; bool keep_ipa_awake; bool napi_enabled; + bool recycle_enabled; }; /** diff --git a/include/linux/percpu-rwsem.h b/include/linux/percpu-rwsem.h index c2fa3ecb0dce..146efefde2a1 100644 --- a/include/linux/percpu-rwsem.h +++ b/include/linux/percpu-rwsem.h @@ -10,30 +10,96 @@ struct percpu_rw_semaphore { struct rcu_sync rss; - unsigned int __percpu *fast_read_ctr; + unsigned int __percpu *read_count; struct rw_semaphore rw_sem; - atomic_t slow_read_ctr; - wait_queue_head_t write_waitq; + wait_queue_head_t writer; + int readers_block; }; -extern void percpu_down_read(struct percpu_rw_semaphore *); -extern int percpu_down_read_trylock(struct percpu_rw_semaphore *); -extern void percpu_up_read(struct percpu_rw_semaphore *); +extern int __percpu_down_read(struct percpu_rw_semaphore *, int); +extern void __percpu_up_read(struct percpu_rw_semaphore *); + +static inline void percpu_down_read(struct percpu_rw_semaphore *sem) +{ + might_sleep(); + + rwsem_acquire_read(&sem->rw_sem.dep_map, 0, 0, _RET_IP_); + + preempt_disable(); + /* + * We are in an RCU-sched read-side critical section, so the writer + * cannot both change sem->state from readers_fast and start checking + * counters while we are here. So if we see !sem->state, we know that + * the writer won't be checking until we're past the preempt_enable() + * and that one the synchronize_sched() is done, the writer will see + * anything we did within this RCU-sched read-size critical section. + */ + __this_cpu_inc(*sem->read_count); + if (unlikely(!rcu_sync_is_idle(&sem->rss))) + __percpu_down_read(sem, false); /* Unconditional memory barrier */ + preempt_enable(); + /* + * The barrier() from preempt_enable() prevents the compiler from + * bleeding the critical section out. + */ +} + +static inline int percpu_down_read_trylock(struct percpu_rw_semaphore *sem) +{ + int ret = 1; + + preempt_disable(); + /* + * Same as in percpu_down_read(). + */ + __this_cpu_inc(*sem->read_count); + if (unlikely(!rcu_sync_is_idle(&sem->rss))) + ret = __percpu_down_read(sem, true); /* Unconditional memory barrier */ + preempt_enable(); + /* + * The barrier() from preempt_enable() prevents the compiler from + * bleeding the critical section out. + */ + + if (ret) + rwsem_acquire_read(&sem->rw_sem.dep_map, 0, 1, _RET_IP_); + + return ret; +} + +static inline void percpu_up_read(struct percpu_rw_semaphore *sem) +{ + /* + * The barrier() in preempt_disable() prevents the compiler from + * bleeding the critical section out. + */ + preempt_disable(); + /* + * Same as in percpu_down_read(). + */ + if (likely(rcu_sync_is_idle(&sem->rss))) + __this_cpu_dec(*sem->read_count); + else + __percpu_up_read(sem); /* Unconditional memory barrier */ + preempt_enable(); + + rwsem_release(&sem->rw_sem.dep_map, 1, _RET_IP_); +} extern void percpu_down_write(struct percpu_rw_semaphore *); extern void percpu_up_write(struct percpu_rw_semaphore *); extern int __percpu_init_rwsem(struct percpu_rw_semaphore *, const char *, struct lock_class_key *); + extern void percpu_free_rwsem(struct percpu_rw_semaphore *); -#define percpu_init_rwsem(brw) \ +#define percpu_init_rwsem(sem) \ ({ \ static struct lock_class_key rwsem_key; \ - __percpu_init_rwsem(brw, #brw, &rwsem_key); \ + __percpu_init_rwsem(sem, #sem, &rwsem_key); \ }) - #define percpu_rwsem_is_held(sem) lockdep_is_held(&(sem)->rw_sem) static inline void percpu_rwsem_release(struct percpu_rw_semaphore *sem, diff --git a/include/linux/rcu_sync.h b/include/linux/rcu_sync.h index a63a33e6196e..ece7ed9a4a70 100644 --- a/include/linux/rcu_sync.h +++ b/include/linux/rcu_sync.h @@ -59,6 +59,7 @@ static inline bool rcu_sync_is_idle(struct rcu_sync *rsp) } extern void rcu_sync_init(struct rcu_sync *, enum rcu_sync_type); +extern void rcu_sync_enter_start(struct rcu_sync *); extern void rcu_sync_enter(struct rcu_sync *); extern void rcu_sync_exit(struct rcu_sync *); extern void rcu_sync_dtor(struct rcu_sync *); diff --git a/include/soc/qcom/secure_buffer.h b/include/soc/qcom/secure_buffer.h index ffa65569ce18..59971c08ed74 100644 --- a/include/soc/qcom/secure_buffer.h +++ b/include/soc/qcom/secure_buffer.h @@ -37,6 +37,7 @@ enum vmid { VMID_CP_APP = 0x12, VMID_WLAN = 0x18, VMID_WLAN_CE = 0x19, + VMID_CP_CAMERA_PREVIEW = 0x1D, VMID_LAST, VMID_INVAL = -1 }; diff --git a/include/sound/apr_audio-v2.h b/include/sound/apr_audio-v2.h index e1bdca690cc9..1a58a146c3b0 100644 --- a/include/sound/apr_audio-v2.h +++ b/include/sound/apr_audio-v2.h @@ -2943,7 +2943,7 @@ struct asm_aac_enc_cfg_v2_t { * number of channels at the input. * The number of channels must not change during encoding. */ - uint32_t channel_cfg; + uint16_t channel_cfg; /* * Number of samples per second. diff --git a/include/sound/q6asm-v2.h b/include/sound/q6asm-v2.h index 8525f2e7f738..00129eb08888 100644 --- a/include/sound/q6asm-v2.h +++ b/include/sound/q6asm-v2.h @@ -339,6 +339,8 @@ int q6asm_stream_cmd_nowait(struct audio_client *ac, int cmd, void *q6asm_is_cpu_buf_avail(int dir, struct audio_client *ac, uint32_t *size, uint32_t *idx); +int q6asm_cpu_buf_release(int dir, struct audio_client *ac); + void *q6asm_is_cpu_buf_avail_nolock(int dir, struct audio_client *ac, uint32_t *size, uint32_t *idx); diff --git a/kernel/cgroup.c b/kernel/cgroup.c index ad4a12371069..cc6c7d0a6758 100644 --- a/kernel/cgroup.c +++ b/kernel/cgroup.c @@ -5376,6 +5376,12 @@ int __init cgroup_init(void) BUG_ON(cgroup_init_cftypes(NULL, cgroup_dfl_base_files)); BUG_ON(cgroup_init_cftypes(NULL, cgroup_legacy_base_files)); + /* + * The latency of the synchronize_sched() is too high for cgroups, + * avoid it at the cost of forcing all readers into the slow path. + */ + rcu_sync_enter_start(&cgroup_threadgroup_rwsem.rss); + mutex_lock(&cgroup_mutex); /* Add init_css_set to the hash table */ diff --git a/kernel/fork.c b/kernel/fork.c index c9eb86b646ab..e89d0bae6f20 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -1375,7 +1375,6 @@ static struct task_struct *copy_process(unsigned long clone_flags, p->real_start_time = ktime_get_boot_ns(); p->io_context = NULL; p->audit_context = NULL; - threadgroup_change_begin(current); cgroup_fork(p); #ifdef CONFIG_NUMA p->mempolicy = mpol_dup(p->mempolicy); @@ -1527,6 +1526,7 @@ static struct task_struct *copy_process(unsigned long clone_flags, INIT_LIST_HEAD(&p->thread_group); p->task_works = NULL; + threadgroup_change_begin(current); /* * Ensure that the cgroup subsystem policies allow the new process to be * forked. It should be noted the the new process's css_set can be changed @@ -1627,6 +1627,7 @@ static struct task_struct *copy_process(unsigned long clone_flags, bad_fork_cancel_cgroup: cgroup_cancel_fork(p, cgrp_ss_priv); bad_fork_free_pid: + threadgroup_change_end(current); if (pid != &init_struct_pid) free_pid(pid); bad_fork_cleanup_io: @@ -1657,7 +1658,6 @@ bad_fork_cleanup_policy: mpol_put(p->mempolicy); bad_fork_cleanup_threadgroup_lock: #endif - threadgroup_change_end(current); delayacct_tsk_free(p); bad_fork_cleanup_count: atomic_dec(&p->cred->user->processes); diff --git a/kernel/locking/percpu-rwsem.c b/kernel/locking/percpu-rwsem.c index f231e0bb311c..ce182599cf2e 100644 --- a/kernel/locking/percpu-rwsem.c +++ b/kernel/locking/percpu-rwsem.c @@ -8,151 +8,186 @@ #include <linux/sched.h> #include <linux/errno.h> -int __percpu_init_rwsem(struct percpu_rw_semaphore *brw, +int __percpu_init_rwsem(struct percpu_rw_semaphore *sem, const char *name, struct lock_class_key *rwsem_key) { - brw->fast_read_ctr = alloc_percpu(int); - if (unlikely(!brw->fast_read_ctr)) + sem->read_count = alloc_percpu(int); + if (unlikely(!sem->read_count)) return -ENOMEM; /* ->rw_sem represents the whole percpu_rw_semaphore for lockdep */ - __init_rwsem(&brw->rw_sem, name, rwsem_key); - rcu_sync_init(&brw->rss, RCU_SCHED_SYNC); - atomic_set(&brw->slow_read_ctr, 0); - init_waitqueue_head(&brw->write_waitq); + rcu_sync_init(&sem->rss, RCU_SCHED_SYNC); + __init_rwsem(&sem->rw_sem, name, rwsem_key); + init_waitqueue_head(&sem->writer); + sem->readers_block = 0; return 0; } EXPORT_SYMBOL_GPL(__percpu_init_rwsem); -void percpu_free_rwsem(struct percpu_rw_semaphore *brw) +void percpu_free_rwsem(struct percpu_rw_semaphore *sem) { /* * XXX: temporary kludge. The error path in alloc_super() * assumes that percpu_free_rwsem() is safe after kzalloc(). */ - if (!brw->fast_read_ctr) + if (!sem->read_count) return; - rcu_sync_dtor(&brw->rss); - free_percpu(brw->fast_read_ctr); - brw->fast_read_ctr = NULL; /* catch use after free bugs */ + rcu_sync_dtor(&sem->rss); + free_percpu(sem->read_count); + sem->read_count = NULL; /* catch use after free bugs */ } +EXPORT_SYMBOL_GPL(percpu_free_rwsem); -/* - * This is the fast-path for down_read/up_read. If it succeeds we rely - * on the barriers provided by rcu_sync_enter/exit; see the comments in - * percpu_down_write() and percpu_up_write(). - * - * If this helper fails the callers rely on the normal rw_semaphore and - * atomic_dec_and_test(), so in this case we have the necessary barriers. - */ -static bool update_fast_ctr(struct percpu_rw_semaphore *brw, unsigned int val) +int __percpu_down_read(struct percpu_rw_semaphore *sem, int try) { - bool success; + /* + * Due to having preemption disabled the decrement happens on + * the same CPU as the increment, avoiding the + * increment-on-one-CPU-and-decrement-on-another problem. + * + * If the reader misses the writer's assignment of readers_block, then + * the writer is guaranteed to see the reader's increment. + * + * Conversely, any readers that increment their sem->read_count after + * the writer looks are guaranteed to see the readers_block value, + * which in turn means that they are guaranteed to immediately + * decrement their sem->read_count, so that it doesn't matter that the + * writer missed them. + */ - preempt_disable(); - success = rcu_sync_is_idle(&brw->rss); - if (likely(success)) - __this_cpu_add(*brw->fast_read_ctr, val); - preempt_enable(); + smp_mb(); /* A matches D */ - return success; -} + /* + * If !readers_block the critical section starts here, matched by the + * release in percpu_up_write(). + */ + if (likely(!smp_load_acquire(&sem->readers_block))) + return 1; -/* - * Like the normal down_read() this is not recursive, the writer can - * come after the first percpu_down_read() and create the deadlock. - * - * Note: returns with lock_is_held(brw->rw_sem) == T for lockdep, - * percpu_up_read() does rwsem_release(). This pairs with the usage - * of ->rw_sem in percpu_down/up_write(). - */ -void percpu_down_read(struct percpu_rw_semaphore *brw) -{ - might_sleep(); - rwsem_acquire_read(&brw->rw_sem.dep_map, 0, 0, _RET_IP_); + /* + * Per the above comment; we still have preemption disabled and + * will thus decrement on the same CPU as we incremented. + */ + __percpu_up_read(sem); - if (likely(update_fast_ctr(brw, +1))) - return; + if (try) + return 0; - /* Avoid rwsem_acquire_read() and rwsem_release() */ - __down_read(&brw->rw_sem); - atomic_inc(&brw->slow_read_ctr); - __up_read(&brw->rw_sem); -} -EXPORT_SYMBOL_GPL(percpu_down_read); + /* + * We either call schedule() in the wait, or we'll fall through + * and reschedule on the preempt_enable() in percpu_down_read(). + */ + preempt_enable_no_resched(); -int percpu_down_read_trylock(struct percpu_rw_semaphore *brw) -{ - if (unlikely(!update_fast_ctr(brw, +1))) { - if (!__down_read_trylock(&brw->rw_sem)) - return 0; - atomic_inc(&brw->slow_read_ctr); - __up_read(&brw->rw_sem); - } - - rwsem_acquire_read(&brw->rw_sem.dep_map, 0, 1, _RET_IP_); + /* + * Avoid lockdep for the down/up_read() we already have them. + */ + __down_read(&sem->rw_sem); + this_cpu_inc(*sem->read_count); + __up_read(&sem->rw_sem); + + preempt_disable(); return 1; } +EXPORT_SYMBOL_GPL(__percpu_down_read); -void percpu_up_read(struct percpu_rw_semaphore *brw) +void __percpu_up_read(struct percpu_rw_semaphore *sem) { - rwsem_release(&brw->rw_sem.dep_map, 1, _RET_IP_); - - if (likely(update_fast_ctr(brw, -1))) - return; + smp_mb(); /* B matches C */ + /* + * In other words, if they see our decrement (presumably to aggregate + * zero, as that is the only time it matters) they will also see our + * critical section. + */ + __this_cpu_dec(*sem->read_count); - /* false-positive is possible but harmless */ - if (atomic_dec_and_test(&brw->slow_read_ctr)) - wake_up_all(&brw->write_waitq); + /* Prod writer to recheck readers_active */ + wake_up(&sem->writer); } -EXPORT_SYMBOL_GPL(percpu_up_read); +EXPORT_SYMBOL_GPL(__percpu_up_read); + +#define per_cpu_sum(var) \ +({ \ + typeof(var) __sum = 0; \ + int cpu; \ + compiletime_assert_atomic_type(__sum); \ + for_each_possible_cpu(cpu) \ + __sum += per_cpu(var, cpu); \ + __sum; \ +}) -static int clear_fast_ctr(struct percpu_rw_semaphore *brw) +/* + * Return true if the modular sum of the sem->read_count per-CPU variable is + * zero. If this sum is zero, then it is stable due to the fact that if any + * newly arriving readers increment a given counter, they will immediately + * decrement that same counter. + */ +static bool readers_active_check(struct percpu_rw_semaphore *sem) { - unsigned int sum = 0; - int cpu; + if (per_cpu_sum(*sem->read_count) != 0) + return false; + + /* + * If we observed the decrement; ensure we see the entire critical + * section. + */ - for_each_possible_cpu(cpu) { - sum += per_cpu(*brw->fast_read_ctr, cpu); - per_cpu(*brw->fast_read_ctr, cpu) = 0; - } + smp_mb(); /* C matches B */ - return sum; + return true; } -void percpu_down_write(struct percpu_rw_semaphore *brw) +void percpu_down_write(struct percpu_rw_semaphore *sem) { + /* Notify readers to take the slow path. */ + rcu_sync_enter(&sem->rss); + + down_write(&sem->rw_sem); + /* - * Make rcu_sync_is_idle() == F and thus disable the fast-path in - * percpu_down_read() and percpu_up_read(), and wait for gp pass. - * - * The latter synchronises us with the preceding readers which used - * the fast-past, so we can not miss the result of __this_cpu_add() - * or anything else inside their criticial sections. + * Notify new readers to block; up until now, and thus throughout the + * longish rcu_sync_enter() above, new readers could still come in. */ - rcu_sync_enter(&brw->rss); + WRITE_ONCE(sem->readers_block, 1); - /* exclude other writers, and block the new readers completely */ - down_write(&brw->rw_sem); + smp_mb(); /* D matches A */ - /* nobody can use fast_read_ctr, move its sum into slow_read_ctr */ - atomic_add(clear_fast_ctr(brw), &brw->slow_read_ctr); + /* + * If they don't see our writer of readers_block, then we are + * guaranteed to see their sem->read_count increment, and therefore + * will wait for them. + */ - /* wait for all readers to complete their percpu_up_read() */ - wait_event(brw->write_waitq, !atomic_read(&brw->slow_read_ctr)); + /* Wait for all now active readers to complete. */ + wait_event(sem->writer, readers_active_check(sem)); } EXPORT_SYMBOL_GPL(percpu_down_write); -void percpu_up_write(struct percpu_rw_semaphore *brw) +void percpu_up_write(struct percpu_rw_semaphore *sem) { - /* release the lock, but the readers can't use the fast-path */ - up_write(&brw->rw_sem); /* - * Enable the fast-path in percpu_down_read() and percpu_up_read() - * but only after another gp pass; this adds the necessary barrier - * to ensure the reader can't miss the changes done by us. + * Signal the writer is done, no fast path yet. + * + * One reason that we cannot just immediately flip to readers_fast is + * that new readers might fail to see the results of this writer's + * critical section. + * + * Therefore we force it through the slow path which guarantees an + * acquire and thereby guarantees the critical section's consistency. + */ + smp_store_release(&sem->readers_block, 0); + + /* + * Release the write lock, this will allow readers back in the game. + */ + up_write(&sem->rw_sem); + + /* + * Once this completes (at least one RCU-sched grace period hence) the + * reader fast path will be available again. Safe to use outside the + * exclusive write lock because its counting. */ - rcu_sync_exit(&brw->rss); + rcu_sync_exit(&sem->rss); } EXPORT_SYMBOL_GPL(percpu_up_write); diff --git a/kernel/rcu/sync.c b/kernel/rcu/sync.c index be922c9f3d37..e358313a0d6c 100644 --- a/kernel/rcu/sync.c +++ b/kernel/rcu/sync.c @@ -83,6 +83,18 @@ void rcu_sync_init(struct rcu_sync *rsp, enum rcu_sync_type type) } /** + * Must be called after rcu_sync_init() and before first use. + * + * Ensures rcu_sync_is_idle() returns false and rcu_sync_{enter,exit}() + * pairs turn into NO-OPs. + */ +void rcu_sync_enter_start(struct rcu_sync *rsp) +{ + rsp->gp_count++; + rsp->gp_state = GP_PASSED; +} + +/** * rcu_sync_enter() - Force readers onto slowpath * @rsp: Pointer to rcu_sync structure to use for synchronization * diff --git a/kernel/sched/core.c b/kernel/sched/core.c index f4379f106e16..4cdf967b67c1 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -1590,7 +1590,7 @@ static int select_fallback_rq(int cpu, struct task_struct *p, bool allow_iso) { int nid = cpu_to_node(cpu); const struct cpumask *nodemask = NULL; - enum { cpuset, possible, fail } state = cpuset; + enum { cpuset, possible, fail, bug } state = cpuset; int dest_cpu; int isolated_candidate = -1; @@ -1650,6 +1650,11 @@ static int select_fallback_rq(int cpu, struct task_struct *p, bool allow_iso) break; case fail: + allow_iso = true; + state = bug; + break; + + case bug: BUG(); break; } @@ -3224,7 +3229,8 @@ static noinline void __schedule_bug(struct task_struct *prev) static inline void schedule_debug(struct task_struct *prev) { #ifdef CONFIG_SCHED_STACK_END_CHECK - BUG_ON(task_stack_end_corrupted(prev)); + if (task_stack_end_corrupted(prev)) + panic("corrupted stack end detected inside scheduler\n"); #endif if (unlikely(in_atomic_preempt_off())) { diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 0a3d2e45daea..4489bec5d68a 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -7246,9 +7246,7 @@ bail_inter_cluster_balance(struct lb_env *env, struct sd_lb_stats *sds) local_pwr_cost = cpu_max_power_cost(local_cpu); busiest_pwr_cost = cpu_max_power_cost(busiest_cpu); - if (local_capacity < busiest_capacity || - (local_capacity == busiest_capacity && - local_pwr_cost <= busiest_pwr_cost)) + if (local_pwr_cost <= busiest_pwr_cost) return 0; if (local_capacity > busiest_capacity && @@ -8885,9 +8883,6 @@ static inline int find_new_hmp_ilb(int type) for_each_cpu_and(ilb, nohz.idle_cpus_mask, sched_domain_span(sd)) { if (idle_cpu(ilb) && (type != NOHZ_KICK_RESTRICT || - (hmp_capable() && - cpu_max_possible_capacity(ilb) <= - cpu_max_possible_capacity(call_cpu)) || cpu_max_power_cost(ilb) <= cpu_max_power_cost(call_cpu))) { rcu_read_unlock(); @@ -9241,8 +9236,7 @@ static inline int _nohz_kick_needed_hmp(struct rq *rq, int cpu, int *type) if (!sysctl_sched_restrict_cluster_spill || sched_boost()) return 1; - if (hmp_capable() && cpu_max_possible_capacity(cpu) == - max_possible_capacity) + if (cpu_max_power_cost(cpu) == max_power_cost) return 1; rcu_read_lock(); diff --git a/kernel/sched/hmp.c b/kernel/sched/hmp.c index fa1f7a503220..1e7b4cd4e64c 100644 --- a/kernel/sched/hmp.c +++ b/kernel/sched/hmp.c @@ -404,6 +404,8 @@ DECLARE_BITMAP(all_cluster_ids, NR_CPUS); struct sched_cluster *sched_cluster[NR_CPUS]; int num_clusters; +unsigned int max_power_cost = 1; + struct sched_cluster init_cluster = { .list = LIST_HEAD_INIT(init_cluster.list), .id = 0, @@ -513,6 +515,7 @@ static void sort_clusters(void) { struct sched_cluster *cluster; struct list_head new_head; + unsigned int tmp_max = 1; INIT_LIST_HEAD(&new_head); @@ -521,7 +524,11 @@ static void sort_clusters(void) max_task_load()); cluster->min_power_cost = power_cost(cluster_first_cpu(cluster), 0); + + if (cluster->max_power_cost > tmp_max) + tmp_max = cluster->max_power_cost; } + max_power_cost = tmp_max; move_list(&new_head, &cluster_head, true); diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 2480ea0c36fa..ada5e580e968 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -1039,6 +1039,7 @@ extern unsigned int min_capacity; extern unsigned int max_load_scale_factor; extern unsigned int max_possible_capacity; extern unsigned int min_max_possible_capacity; +extern unsigned int max_power_cost; extern unsigned int sched_upmigrate; extern unsigned int sched_downmigrate; extern unsigned int sched_init_task_load_windows; diff --git a/kernel/time/hrtimer.c b/kernel/time/hrtimer.c index 1b0117198a08..9e1349fc5bbe 100644 --- a/kernel/time/hrtimer.c +++ b/kernel/time/hrtimer.c @@ -1625,20 +1625,36 @@ static void init_hrtimers_cpu(int cpu) } #if defined(CONFIG_HOTPLUG_CPU) -static void migrate_hrtimer_list(struct hrtimer_clock_base *old_base, - struct hrtimer_clock_base *new_base, +static void migrate_hrtimer_list(struct hrtimer_cpu_base *old_base, + struct hrtimer_cpu_base *new_base, + unsigned int i, + bool wait, bool remove_pinned) { struct hrtimer *timer; struct timerqueue_node *node; struct timerqueue_head pinned; int is_pinned; + struct hrtimer_clock_base *old_c_base = &old_base->clock_base[i]; + struct hrtimer_clock_base *new_c_base = &new_base->clock_base[i]; timerqueue_init_head(&pinned); - while ((node = timerqueue_getnext(&old_base->active))) { + while ((node = timerqueue_getnext(&old_c_base->active))) { timer = container_of(node, struct hrtimer, node); - BUG_ON(hrtimer_callback_running(timer)); + if (wait) { + /* Ensure timers are done running before continuing */ + while (hrtimer_callback_running(timer)) { + raw_spin_unlock(&old_base->lock); + raw_spin_unlock(&new_base->lock); + cpu_relax(); + raw_spin_lock(&new_base->lock); + raw_spin_lock_nested(&old_base->lock, + SINGLE_DEPTH_NESTING); + } + } else { + BUG_ON(hrtimer_callback_running(timer)); + } debug_deactivate(timer); /* @@ -1646,7 +1662,7 @@ static void migrate_hrtimer_list(struct hrtimer_clock_base *old_base, * timer could be seen as !active and just vanish away * under us on another CPU */ - __remove_hrtimer(timer, old_base, HRTIMER_STATE_ENQUEUED, 0); + __remove_hrtimer(timer, old_c_base, HRTIMER_STATE_ENQUEUED, 0); is_pinned = timer->state & HRTIMER_STATE_PINNED; if (!remove_pinned && is_pinned) { @@ -1654,7 +1670,7 @@ static void migrate_hrtimer_list(struct hrtimer_clock_base *old_base, continue; } - timer->base = new_base; + timer->base = new_c_base; /* * Enqueue the timers on the new cpu. This does not * reprogram the event device in case the timer @@ -1663,7 +1679,7 @@ static void migrate_hrtimer_list(struct hrtimer_clock_base *old_base, * sort out already expired timers and reprogram the * event device. */ - enqueue_hrtimer(timer, new_base); + enqueue_hrtimer(timer, new_c_base); } /* Re-queue pinned timers for non-hotplug usecase */ @@ -1671,11 +1687,11 @@ static void migrate_hrtimer_list(struct hrtimer_clock_base *old_base, timer = container_of(node, struct hrtimer, node); timerqueue_del(&pinned, &timer->node); - enqueue_hrtimer(timer, old_base); + enqueue_hrtimer(timer, old_c_base); } } -static void __migrate_hrtimers(int scpu, bool remove_pinned) +static void __migrate_hrtimers(int scpu, bool wait, bool remove_pinned) { struct hrtimer_cpu_base *old_base, *new_base; unsigned long flags; @@ -1692,8 +1708,8 @@ static void __migrate_hrtimers(int scpu, bool remove_pinned) raw_spin_lock_nested(&old_base->lock, SINGLE_DEPTH_NESTING); for (i = 0; i < HRTIMER_MAX_CLOCK_BASES; i++) { - migrate_hrtimer_list(&old_base->clock_base[i], - &new_base->clock_base[i], remove_pinned); + migrate_hrtimer_list(old_base, new_base, i, wait, + remove_pinned); } raw_spin_unlock(&old_base->lock); @@ -1709,12 +1725,12 @@ static void migrate_hrtimers(int scpu) BUG_ON(cpu_online(scpu)); tick_cancel_sched_timer(scpu); - __migrate_hrtimers(scpu, true); + __migrate_hrtimers(scpu, false, true); } void hrtimer_quiesce_cpu(void *cpup) { - __migrate_hrtimers(*(int *)cpup, false); + __migrate_hrtimers(*(int *)cpup, true, false); } #endif /* CONFIG_HOTPLUG_CPU */ diff --git a/net/ipv4/netfilter/arp_tables.c b/net/ipv4/netfilter/arp_tables.c index 11dccba474b7..36a30fab8625 100644 --- a/net/ipv4/netfilter/arp_tables.c +++ b/net/ipv4/netfilter/arp_tables.c @@ -359,11 +359,12 @@ unsigned int arpt_do_table(struct sk_buff *skb, } /* All zeroes == unconditional rule. */ -static inline bool unconditional(const struct arpt_arp *arp) +static inline bool unconditional(const struct arpt_entry *e) { static const struct arpt_arp uncond; - return memcmp(arp, &uncond, sizeof(uncond)) == 0; + return e->target_offset == sizeof(struct arpt_entry) && + memcmp(&e->arp, &uncond, sizeof(uncond)) == 0; } /* Figures out from what hook each rule can be called: returns 0 if @@ -402,11 +403,10 @@ static int mark_source_chains(const struct xt_table_info *newinfo, |= ((1 << hook) | (1 << NF_ARP_NUMHOOKS)); /* Unconditional return/END. */ - if ((e->target_offset == sizeof(struct arpt_entry) && + if ((unconditional(e) && (strcmp(t->target.u.user.name, XT_STANDARD_TARGET) == 0) && - t->verdict < 0 && unconditional(&e->arp)) || - visited) { + t->verdict < 0) || visited) { unsigned int oldpos, size; if ((strcmp(t->target.u.user.name, @@ -474,14 +474,12 @@ next: return 1; } -static inline int check_entry(const struct arpt_entry *e, const char *name) +static inline int check_entry(const struct arpt_entry *e) { const struct xt_entry_target *t; - if (!arp_checkentry(&e->arp)) { - duprintf("arp_tables: arp check failed %p %s.\n", e, name); + if (!arp_checkentry(&e->arp)) return -EINVAL; - } if (e->target_offset + sizeof(struct xt_entry_target) > e->next_offset) return -EINVAL; @@ -522,10 +520,6 @@ find_check_entry(struct arpt_entry *e, const char *name, unsigned int size) struct xt_target *target; int ret; - ret = check_entry(e, name); - if (ret) - return ret; - e->counters.pcnt = xt_percpu_counter_alloc(); if (IS_ERR_VALUE(e->counters.pcnt)) return -ENOMEM; @@ -557,7 +551,7 @@ static bool check_underflow(const struct arpt_entry *e) const struct xt_entry_target *t; unsigned int verdict; - if (!unconditional(&e->arp)) + if (!unconditional(e)) return false; t = arpt_get_target_c(e); if (strcmp(t->u.user.name, XT_STANDARD_TARGET) != 0) @@ -576,9 +570,11 @@ static inline int check_entry_size_and_hooks(struct arpt_entry *e, unsigned int valid_hooks) { unsigned int h; + int err; if ((unsigned long)e % __alignof__(struct arpt_entry) != 0 || - (unsigned char *)e + sizeof(struct arpt_entry) >= limit) { + (unsigned char *)e + sizeof(struct arpt_entry) >= limit || + (unsigned char *)e + e->next_offset > limit) { duprintf("Bad offset %p\n", e); return -EINVAL; } @@ -590,6 +586,10 @@ static inline int check_entry_size_and_hooks(struct arpt_entry *e, return -EINVAL; } + err = check_entry(e); + if (err) + return err; + /* Check hooks & underflows */ for (h = 0; h < NF_ARP_NUMHOOKS; h++) { if (!(valid_hooks & (1 << h))) @@ -598,9 +598,9 @@ static inline int check_entry_size_and_hooks(struct arpt_entry *e, newinfo->hook_entry[h] = hook_entries[h]; if ((unsigned char *)e - base == underflows[h]) { if (!check_underflow(e)) { - pr_err("Underflows must be unconditional and " - "use the STANDARD target with " - "ACCEPT/DROP\n"); + pr_debug("Underflows must be unconditional and " + "use the STANDARD target with " + "ACCEPT/DROP\n"); return -EINVAL; } newinfo->underflow[h] = underflows[h]; @@ -1233,7 +1233,8 @@ check_compat_entry_size_and_hooks(struct compat_arpt_entry *e, duprintf("check_compat_entry_size_and_hooks %p\n", e); if ((unsigned long)e % __alignof__(struct compat_arpt_entry) != 0 || - (unsigned char *)e + sizeof(struct compat_arpt_entry) >= limit) { + (unsigned char *)e + sizeof(struct compat_arpt_entry) >= limit || + (unsigned char *)e + e->next_offset > limit) { duprintf("Bad offset %p, limit = %p\n", e, limit); return -EINVAL; } @@ -1246,7 +1247,7 @@ check_compat_entry_size_and_hooks(struct compat_arpt_entry *e, } /* For purposes of check_entry casting the compat entry is fine */ - ret = check_entry((struct arpt_entry *)e, name); + ret = check_entry((struct arpt_entry *)e); if (ret) return ret; diff --git a/net/ipv4/netfilter/ip_tables.c b/net/ipv4/netfilter/ip_tables.c index b99affad6ba1..99d46b0a4ead 100644 --- a/net/ipv4/netfilter/ip_tables.c +++ b/net/ipv4/netfilter/ip_tables.c @@ -168,11 +168,12 @@ get_entry(const void *base, unsigned int offset) /* All zeroes == unconditional rule. */ /* Mildly perf critical (only if packet tracing is on) */ -static inline bool unconditional(const struct ipt_ip *ip) +static inline bool unconditional(const struct ipt_entry *e) { static const struct ipt_ip uncond; - return memcmp(ip, &uncond, sizeof(uncond)) == 0; + return e->target_offset == sizeof(struct ipt_entry) && + memcmp(&e->ip, &uncond, sizeof(uncond)) == 0; #undef FWINV } @@ -229,11 +230,10 @@ get_chainname_rulenum(const struct ipt_entry *s, const struct ipt_entry *e, } else if (s == e) { (*rulenum)++; - if (s->target_offset == sizeof(struct ipt_entry) && + if (unconditional(s) && strcmp(t->target.u.kernel.target->name, XT_STANDARD_TARGET) == 0 && - t->verdict < 0 && - unconditional(&s->ip)) { + t->verdict < 0) { /* Tail of chains: STANDARD target (return/policy) */ *comment = *chainname == hookname ? comments[NF_IP_TRACE_COMMENT_POLICY] @@ -476,11 +476,10 @@ mark_source_chains(const struct xt_table_info *newinfo, e->comefrom |= ((1 << hook) | (1 << NF_INET_NUMHOOKS)); /* Unconditional return/END. */ - if ((e->target_offset == sizeof(struct ipt_entry) && + if ((unconditional(e) && (strcmp(t->target.u.user.name, XT_STANDARD_TARGET) == 0) && - t->verdict < 0 && unconditional(&e->ip)) || - visited) { + t->verdict < 0) || visited) { unsigned int oldpos, size; if ((strcmp(t->target.u.user.name, @@ -569,14 +568,12 @@ static void cleanup_match(struct xt_entry_match *m, struct net *net) } static int -check_entry(const struct ipt_entry *e, const char *name) +check_entry(const struct ipt_entry *e) { const struct xt_entry_target *t; - if (!ip_checkentry(&e->ip)) { - duprintf("ip check failed %p %s.\n", e, name); + if (!ip_checkentry(&e->ip)) return -EINVAL; - } if (e->target_offset + sizeof(struct xt_entry_target) > e->next_offset) @@ -666,10 +663,6 @@ find_check_entry(struct ipt_entry *e, struct net *net, const char *name, struct xt_mtchk_param mtpar; struct xt_entry_match *ematch; - ret = check_entry(e, name); - if (ret) - return ret; - e->counters.pcnt = xt_percpu_counter_alloc(); if (IS_ERR_VALUE(e->counters.pcnt)) return -ENOMEM; @@ -721,7 +714,7 @@ static bool check_underflow(const struct ipt_entry *e) const struct xt_entry_target *t; unsigned int verdict; - if (!unconditional(&e->ip)) + if (!unconditional(e)) return false; t = ipt_get_target_c(e); if (strcmp(t->u.user.name, XT_STANDARD_TARGET) != 0) @@ -741,9 +734,11 @@ check_entry_size_and_hooks(struct ipt_entry *e, unsigned int valid_hooks) { unsigned int h; + int err; if ((unsigned long)e % __alignof__(struct ipt_entry) != 0 || - (unsigned char *)e + sizeof(struct ipt_entry) >= limit) { + (unsigned char *)e + sizeof(struct ipt_entry) >= limit || + (unsigned char *)e + e->next_offset > limit) { duprintf("Bad offset %p\n", e); return -EINVAL; } @@ -755,6 +750,10 @@ check_entry_size_and_hooks(struct ipt_entry *e, return -EINVAL; } + err = check_entry(e); + if (err) + return err; + /* Check hooks & underflows */ for (h = 0; h < NF_INET_NUMHOOKS; h++) { if (!(valid_hooks & (1 << h))) @@ -763,9 +762,9 @@ check_entry_size_and_hooks(struct ipt_entry *e, newinfo->hook_entry[h] = hook_entries[h]; if ((unsigned char *)e - base == underflows[h]) { if (!check_underflow(e)) { - pr_err("Underflows must be unconditional and " - "use the STANDARD target with " - "ACCEPT/DROP\n"); + pr_debug("Underflows must be unconditional and " + "use the STANDARD target with " + "ACCEPT/DROP\n"); return -EINVAL; } newinfo->underflow[h] = underflows[h]; @@ -1493,7 +1492,8 @@ check_compat_entry_size_and_hooks(struct compat_ipt_entry *e, duprintf("check_compat_entry_size_and_hooks %p\n", e); if ((unsigned long)e % __alignof__(struct compat_ipt_entry) != 0 || - (unsigned char *)e + sizeof(struct compat_ipt_entry) >= limit) { + (unsigned char *)e + sizeof(struct compat_ipt_entry) >= limit || + (unsigned char *)e + e->next_offset > limit) { duprintf("Bad offset %p, limit = %p\n", e, limit); return -EINVAL; } @@ -1506,7 +1506,7 @@ check_compat_entry_size_and_hooks(struct compat_ipt_entry *e, } /* For purposes of check_entry casting the compat entry is fine */ - ret = check_entry((struct ipt_entry *)e, name); + ret = check_entry((struct ipt_entry *)e); if (ret) return ret; diff --git a/net/ipv6/netfilter/ip6_tables.c b/net/ipv6/netfilter/ip6_tables.c index 99425cf2819b..6198807e06f4 100644 --- a/net/ipv6/netfilter/ip6_tables.c +++ b/net/ipv6/netfilter/ip6_tables.c @@ -198,11 +198,12 @@ get_entry(const void *base, unsigned int offset) /* All zeroes == unconditional rule. */ /* Mildly perf critical (only if packet tracing is on) */ -static inline bool unconditional(const struct ip6t_ip6 *ipv6) +static inline bool unconditional(const struct ip6t_entry *e) { static const struct ip6t_ip6 uncond; - return memcmp(ipv6, &uncond, sizeof(uncond)) == 0; + return e->target_offset == sizeof(struct ip6t_entry) && + memcmp(&e->ipv6, &uncond, sizeof(uncond)) == 0; } static inline const struct xt_entry_target * @@ -258,11 +259,10 @@ get_chainname_rulenum(const struct ip6t_entry *s, const struct ip6t_entry *e, } else if (s == e) { (*rulenum)++; - if (s->target_offset == sizeof(struct ip6t_entry) && + if (unconditional(s) && strcmp(t->target.u.kernel.target->name, XT_STANDARD_TARGET) == 0 && - t->verdict < 0 && - unconditional(&s->ipv6)) { + t->verdict < 0) { /* Tail of chains: STANDARD target (return/policy) */ *comment = *chainname == hookname ? comments[NF_IP6_TRACE_COMMENT_POLICY] @@ -488,11 +488,10 @@ mark_source_chains(const struct xt_table_info *newinfo, e->comefrom |= ((1 << hook) | (1 << NF_INET_NUMHOOKS)); /* Unconditional return/END. */ - if ((e->target_offset == sizeof(struct ip6t_entry) && + if ((unconditional(e) && (strcmp(t->target.u.user.name, XT_STANDARD_TARGET) == 0) && - t->verdict < 0 && - unconditional(&e->ipv6)) || visited) { + t->verdict < 0) || visited) { unsigned int oldpos, size; if ((strcmp(t->target.u.user.name, @@ -581,14 +580,12 @@ static void cleanup_match(struct xt_entry_match *m, struct net *net) } static int -check_entry(const struct ip6t_entry *e, const char *name) +check_entry(const struct ip6t_entry *e) { const struct xt_entry_target *t; - if (!ip6_checkentry(&e->ipv6)) { - duprintf("ip_tables: ip check failed %p %s.\n", e, name); + if (!ip6_checkentry(&e->ipv6)) return -EINVAL; - } if (e->target_offset + sizeof(struct xt_entry_target) > e->next_offset) @@ -679,10 +676,6 @@ find_check_entry(struct ip6t_entry *e, struct net *net, const char *name, struct xt_mtchk_param mtpar; struct xt_entry_match *ematch; - ret = check_entry(e, name); - if (ret) - return ret; - e->counters.pcnt = xt_percpu_counter_alloc(); if (IS_ERR_VALUE(e->counters.pcnt)) return -ENOMEM; @@ -733,7 +726,7 @@ static bool check_underflow(const struct ip6t_entry *e) const struct xt_entry_target *t; unsigned int verdict; - if (!unconditional(&e->ipv6)) + if (!unconditional(e)) return false; t = ip6t_get_target_c(e); if (strcmp(t->u.user.name, XT_STANDARD_TARGET) != 0) @@ -753,9 +746,11 @@ check_entry_size_and_hooks(struct ip6t_entry *e, unsigned int valid_hooks) { unsigned int h; + int err; if ((unsigned long)e % __alignof__(struct ip6t_entry) != 0 || - (unsigned char *)e + sizeof(struct ip6t_entry) >= limit) { + (unsigned char *)e + sizeof(struct ip6t_entry) >= limit || + (unsigned char *)e + e->next_offset > limit) { duprintf("Bad offset %p\n", e); return -EINVAL; } @@ -767,6 +762,10 @@ check_entry_size_and_hooks(struct ip6t_entry *e, return -EINVAL; } + err = check_entry(e); + if (err) + return err; + /* Check hooks & underflows */ for (h = 0; h < NF_INET_NUMHOOKS; h++) { if (!(valid_hooks & (1 << h))) @@ -775,9 +774,9 @@ check_entry_size_and_hooks(struct ip6t_entry *e, newinfo->hook_entry[h] = hook_entries[h]; if ((unsigned char *)e - base == underflows[h]) { if (!check_underflow(e)) { - pr_err("Underflows must be unconditional and " - "use the STANDARD target with " - "ACCEPT/DROP\n"); + pr_debug("Underflows must be unconditional and " + "use the STANDARD target with " + "ACCEPT/DROP\n"); return -EINVAL; } newinfo->underflow[h] = underflows[h]; @@ -1505,7 +1504,8 @@ check_compat_entry_size_and_hooks(struct compat_ip6t_entry *e, duprintf("check_compat_entry_size_and_hooks %p\n", e); if ((unsigned long)e % __alignof__(struct compat_ip6t_entry) != 0 || - (unsigned char *)e + sizeof(struct compat_ip6t_entry) >= limit) { + (unsigned char *)e + sizeof(struct compat_ip6t_entry) >= limit || + (unsigned char *)e + e->next_offset > limit) { duprintf("Bad offset %p, limit = %p\n", e, limit); return -EINVAL; } @@ -1518,7 +1518,7 @@ check_compat_entry_size_and_hooks(struct compat_ip6t_entry *e, } /* For purposes of check_entry casting the compat entry is fine */ - ret = check_entry((struct ip6t_entry *)e, name); + ret = check_entry((struct ip6t_entry *)e); if (ret) return ret; diff --git a/security/keys/key.c b/security/keys/key.c index ab7997ded725..534808915371 100644 --- a/security/keys/key.c +++ b/security/keys/key.c @@ -578,7 +578,7 @@ int key_reject_and_link(struct key *key, mutex_unlock(&key_construction_mutex); - if (keyring) + if (keyring && link_ret == 0) __key_link_end(keyring, &key->index_key, edit); /* wake up anyone waiting for a key to be constructed */ diff --git a/sound/soc/codecs/wcd-mbhc-v2.c b/sound/soc/codecs/wcd-mbhc-v2.c index 5b6af14e1d94..d207d9ccda34 100644 --- a/sound/soc/codecs/wcd-mbhc-v2.c +++ b/sound/soc/codecs/wcd-mbhc-v2.c @@ -38,7 +38,7 @@ #define WCD_MBHC_JACK_BUTTON_MASK (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \ SND_JACK_BTN_2 | SND_JACK_BTN_3 | \ SND_JACK_BTN_4 | SND_JACK_BTN_5 ) -#define OCP_ATTEMPT 1 +#define OCP_ATTEMPT 20 #define HS_DETECT_PLUG_TIME_MS (3 * 1000) #define SPECIAL_HS_DETECT_TIME_MS (2 * 1000) #define MBHC_BUTTON_PRESS_THRESHOLD_MIN 250 @@ -226,6 +226,10 @@ static const char *wcd_mbhc_get_event_string(int event) return WCD_MBHC_STRINGIFY(WCD_EVENT_POST_DAPM_MICBIAS_2_OFF); case WCD_EVENT_PRE_DAPM_MICBIAS_2_OFF: return WCD_MBHC_STRINGIFY(WCD_EVENT_PRE_DAPM_MICBIAS_2_OFF); + case WCD_EVENT_OCP_OFF: + return WCD_MBHC_STRINGIFY(WCD_EVENT_OCP_OFF); + case WCD_EVENT_OCP_ON: + return WCD_MBHC_STRINGIFY(WCD_EVENT_OCP_ON); case WCD_EVENT_INVALID: default: return WCD_MBHC_STRINGIFY(WCD_EVENT_INVALID); @@ -394,6 +398,16 @@ out_micb_en: /* Disable micbias, enable pullup & cs */ wcd_enable_curr_micbias(mbhc, WCD_MBHC_EN_PULLUP); break; + case WCD_EVENT_OCP_OFF: + mbhc->mbhc_cb->irq_control(mbhc->codec, + mbhc->intr_ids->hph_left_ocp, + false); + break; + case WCD_EVENT_OCP_ON: + mbhc->mbhc_cb->irq_control(mbhc->codec, + mbhc->intr_ids->hph_left_ocp, + true); + break; default: break; } @@ -461,6 +475,7 @@ static void wcd_mbhc_clr_and_turnon_hph_padac(struct wcd_mbhc *mbhc) &mbhc->hph_pa_dac_state)) { pr_debug("%s: HPHR clear flag and enable PA\n", __func__); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_HPHR_PA_EN, 1); + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_HPHR_OCP_DET_EN, 1); pa_turned_on = true; } mutex_unlock(&mbhc->hphr_pa_lock); @@ -469,6 +484,7 @@ static void wcd_mbhc_clr_and_turnon_hph_padac(struct wcd_mbhc *mbhc) &mbhc->hph_pa_dac_state)) { pr_debug("%s: HPHL clear flag and enable PA\n", __func__); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_HPHL_PA_EN, 1); + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_HPHL_OCP_DET_EN, 1); pa_turned_on = true; } mutex_unlock(&mbhc->hphl_pa_lock); @@ -502,6 +518,8 @@ static void wcd_mbhc_set_and_turnoff_hph_padac(struct wcd_mbhc *mbhc) pr_debug("%s PA is on, setting PA_OFF_ACK\n", __func__); set_bit(WCD_MBHC_HPHL_PA_OFF_ACK, &mbhc->hph_pa_dac_state); set_bit(WCD_MBHC_HPHR_PA_OFF_ACK, &mbhc->hph_pa_dac_state); + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_HPHL_OCP_DET_EN, 0); + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_HPHR_OCP_DET_EN, 0); } else { pr_debug("%s PA is off\n", __func__); } @@ -2014,13 +2032,24 @@ exit: static irqreturn_t wcd_mbhc_hphl_ocp_irq(int irq, void *data) { struct wcd_mbhc *mbhc = data; + int val; pr_debug("%s: received HPHL OCP irq\n", __func__); if (mbhc) { - if ((mbhc->hphlocp_cnt < OCP_ATTEMPT) && - (!mbhc->hphrocp_cnt)) { - pr_debug("%s: retry\n", __func__); + if (mbhc->mbhc_cb->hph_register_recovery) { + if (mbhc->mbhc_cb->hph_register_recovery(mbhc)) { + WCD_MBHC_REG_READ(WCD_MBHC_HPHR_OCP_STATUS, + val); + if ((val != -EINVAL) && val) + mbhc->is_hph_ocp_pending = true; + goto done; + } + } + + if (mbhc->hphlocp_cnt < OCP_ATTEMPT) { mbhc->hphlocp_cnt++; + pr_debug("%s: retry, hphlocp_cnt: %d\n", __func__, + mbhc->hphlocp_cnt); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_OCP_FSM_EN, 0); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_OCP_FSM_EN, 1); } else { @@ -2035,6 +2064,7 @@ static irqreturn_t wcd_mbhc_hphl_ocp_irq(int irq, void *data) } else { pr_err("%s: Bad wcd9xxx_spmi private data\n", __func__); } +done: return IRQ_HANDLED; } @@ -2043,10 +2073,26 @@ static irqreturn_t wcd_mbhc_hphr_ocp_irq(int irq, void *data) struct wcd_mbhc *mbhc = data; pr_debug("%s: received HPHR OCP irq\n", __func__); - if ((mbhc->hphrocp_cnt < OCP_ATTEMPT) && - (!mbhc->hphlocp_cnt)) { - pr_debug("%s: retry\n", __func__); + + if (!mbhc) { + pr_err("%s: Bad mbhc private data\n", __func__); + goto done; + } + + if (mbhc->is_hph_ocp_pending) { + mbhc->is_hph_ocp_pending = false; + goto done; + } + + if (mbhc->mbhc_cb->hph_register_recovery) { + if (mbhc->mbhc_cb->hph_register_recovery(mbhc)) + /* register corruption, hence reset registers */ + goto done; + } + if (mbhc->hphrocp_cnt < OCP_ATTEMPT) { mbhc->hphrocp_cnt++; + pr_debug("%s: retry, hphrocp_cnt: %d\n", __func__, + mbhc->hphrocp_cnt); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_OCP_FSM_EN, 0); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_OCP_FSM_EN, 1); } else { @@ -2057,6 +2103,7 @@ static irqreturn_t wcd_mbhc_hphr_ocp_irq(int irq, void *data) wcd_mbhc_jack_report(mbhc, &mbhc->headset_jack, mbhc->hph_status, WCD_MBHC_JACK_MASK); } +done: return IRQ_HANDLED; } diff --git a/sound/soc/codecs/wcd-mbhc-v2.h b/sound/soc/codecs/wcd-mbhc-v2.h index ab42b3bb6e7d..676ec342a30a 100644 --- a/sound/soc/codecs/wcd-mbhc-v2.h +++ b/sound/soc/codecs/wcd-mbhc-v2.h @@ -66,6 +66,10 @@ enum wcd_mbhc_register_function { WCD_MBHC_ANC_DET_EN, WCD_MBHC_FSM_STATUS, WCD_MBHC_MUX_CTL, + WCD_MBHC_HPHL_OCP_DET_EN, + WCD_MBHC_HPHR_OCP_DET_EN, + WCD_MBHC_HPHL_OCP_STATUS, + WCD_MBHC_HPHR_OCP_STATUS, WCD_MBHC_REG_FUNC_MAX, }; @@ -127,6 +131,8 @@ enum wcd_notify_event { WCD_EVENT_POST_HPHR_PA_OFF, WCD_EVENT_PRE_HPHL_PA_OFF, WCD_EVENT_PRE_HPHR_PA_OFF, + WCD_EVENT_OCP_OFF, + WCD_EVENT_OCP_ON, WCD_EVENT_LAST, }; @@ -322,7 +328,9 @@ do { \ mbhc->wcd_mbhc_regs[function].reg)) & \ (mbhc->wcd_mbhc_regs[function].mask)) >> \ (mbhc->wcd_mbhc_regs[function].offset)); \ - } \ + } else { \ + val = -EINVAL; \ + } \ } while (0) struct wcd_mbhc_cb { @@ -365,6 +373,7 @@ struct wcd_mbhc_cb { void (*mbhc_gnd_det_ctrl)(struct snd_soc_codec *, bool); void (*hph_pull_down_ctrl)(struct snd_soc_codec *, bool); void (*mbhc_moisture_config)(struct wcd_mbhc *); + bool (*hph_register_recovery)(struct wcd_mbhc *); }; struct wcd_mbhc { @@ -430,6 +439,7 @@ struct wcd_mbhc { struct mutex hphr_pa_lock; unsigned long intr_status; + bool is_hph_ocp_pending; }; #define WCD_MBHC_CAL_SIZE(buttons, rload) ( \ sizeof(struct wcd_mbhc_general_cfg) + \ diff --git a/sound/soc/codecs/wcd934x/wcd934x-mbhc.c b/sound/soc/codecs/wcd934x/wcd934x-mbhc.c index 20f3043656e5..b3a30eb10b92 100644 --- a/sound/soc/codecs/wcd934x/wcd934x-mbhc.c +++ b/sound/soc/codecs/wcd934x/wcd934x-mbhc.c @@ -118,6 +118,14 @@ static struct wcd_mbhc_register WCD934X_MBHC_STATUS_SPARE_1, 0x01, 0, 0), WCD_MBHC_REGISTER("WCD_MBHC_MUX_CTL", WCD934X_MBHC_NEW_CTL_2, 0x70, 4, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HPHL_OCP_DET_EN", + WCD934X_HPH_L_TEST, 0x01, 0, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HPHR_OCP_DET_EN", + WCD934X_HPH_R_TEST, 0x01, 0, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HPHL_OCP_STATUS", + WCD934X_INTR_PIN1_STATUS0, 0x04, 2, 0), + WCD_MBHC_REGISTER("WCD_MBHC_HPHR_OCP_STATUS", + WCD934X_INTR_PIN1_STATUS0, 0x08, 3, 0), }; static const struct wcd_mbhc_intr intr_ids = { @@ -778,6 +786,26 @@ static void tavil_mbhc_moisture_config(struct wcd_mbhc *mbhc) 0x0C, TAVIL_MBHC_MOISTURE_RREF << 2); } +static bool tavil_hph_register_recovery(struct wcd_mbhc *mbhc) +{ + struct snd_soc_codec *codec = mbhc->codec; + struct wcd934x_mbhc *wcd934x_mbhc = tavil_soc_get_mbhc(codec); + + if (!wcd934x_mbhc) + return false; + + wcd934x_mbhc->is_hph_recover = false; + snd_soc_dapm_force_enable_pin(snd_soc_codec_get_dapm(codec), + "RESET_HPH_REGISTERS"); + snd_soc_dapm_sync(snd_soc_codec_get_dapm(codec)); + + snd_soc_dapm_disable_pin(snd_soc_codec_get_dapm(codec), + "RESET_HPH_REGISTERS"); + snd_soc_dapm_sync(snd_soc_codec_get_dapm(codec)); + + return wcd934x_mbhc->is_hph_recover; +} + static const struct wcd_mbhc_cb mbhc_cb = { .request_irq = tavil_mbhc_request_irq, .irq_control = tavil_mbhc_irq_control, @@ -800,6 +828,7 @@ static const struct wcd_mbhc_cb mbhc_cb = { .mbhc_gnd_det_ctrl = tavil_mbhc_gnd_det_ctrl, .hph_pull_down_ctrl = tavil_mbhc_hph_pull_down_ctrl, .mbhc_moisture_config = tavil_mbhc_moisture_config, + .hph_register_recovery = tavil_hph_register_recovery, }; static struct regulator *tavil_codec_find_ondemand_regulator( diff --git a/sound/soc/codecs/wcd934x/wcd934x-mbhc.h b/sound/soc/codecs/wcd934x/wcd934x-mbhc.h index b747b120b605..120a7b0f8177 100644 --- a/sound/soc/codecs/wcd934x/wcd934x-mbhc.h +++ b/sound/soc/codecs/wcd934x/wcd934x-mbhc.h @@ -32,6 +32,7 @@ struct wcd934x_mbhc { struct wcd9xxx *wcd9xxx; struct fw_info *fw_data; bool mbhc_started; + bool is_hph_recover; }; extern int tavil_mbhc_init(struct wcd934x_mbhc **mbhc, diff --git a/sound/soc/codecs/wcd934x/wcd934x.c b/sound/soc/codecs/wcd934x/wcd934x.c index 6341cf8a39e6..b4a73d17c322 100644 --- a/sound/soc/codecs/wcd934x/wcd934x.c +++ b/sound/soc/codecs/wcd934x/wcd934x.c @@ -123,6 +123,9 @@ static const struct snd_kcontrol_new name##_mux = \ #define WCD934X_DEC_PWR_LVL_DF 0x00 #define WCD934X_STRING_LEN 100 +#define WCD934X_DIG_CORE_REG_MIN WCD934X_CDC_ANC0_CLK_RESET_CTL +#define WCD934X_DIG_CORE_REG_MAX 0xFFF + #define WCD934X_MAX_MICBIAS 4 #define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone" #define DAPM_MICBIAS2_STANDALONE "MIC BIAS2 Standalone" @@ -141,6 +144,32 @@ static const struct snd_kcontrol_new name##_mux = \ #define TAVIL_VERSION_ENTRY_SIZE 17 +#define WCD934X_DIG_CORE_COLLAPSE_TIMER_MS (5 * 1000) + +enum { + POWER_COLLAPSE, + POWER_RESUME, +}; + +static int dig_core_collapse_enable = 1; +module_param(dig_core_collapse_enable, int, + S_IRUGO | S_IWUSR | S_IWGRP); +MODULE_PARM_DESC(dig_core_collapse_enable, "enable/disable power gating"); + +/* dig_core_collapse timer in seconds */ +static int dig_core_collapse_timer = (WCD934X_DIG_CORE_COLLAPSE_TIMER_MS/1000); +module_param(dig_core_collapse_timer, int, + S_IRUGO | S_IWUSR | S_IWGRP); +MODULE_PARM_DESC(dig_core_collapse_timer, "timer for power gating"); + +#define TAVIL_HPH_REG_RANGE_1 (WCD934X_HPH_R_DAC_CTL - WCD934X_HPH_CNP_EN + 1) +#define TAVIL_HPH_REG_RANGE_2 (WCD934X_HPH_NEW_ANA_HPH3 -\ + WCD934X_HPH_NEW_ANA_HPH2 + 1) +#define TAVIL_HPH_REG_RANGE_3 (WCD934X_HPH_NEW_INT_PA_RDAC_MISC3 -\ + WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL + 1) +#define TAVIL_HPH_TOTAL_REG (TAVIL_HPH_REG_RANGE_1 + TAVIL_HPH_REG_RANGE_2 +\ + TAVIL_HPH_REG_RANGE_3) + enum { VI_SENSE_1, VI_SENSE_2, @@ -418,6 +447,30 @@ static struct afe_param_cdc_reg_cfg audio_reg_cfg[] = { WCD934X_CDC_ANC0_FF_A_GAIN_CTL), AANC_GAIN_CONTROL, 0xFF, WCD934X_REG_BITS, 0 }, + { + 1, + (WCD934X_REGISTER_START_OFFSET + + SB_PGD_TX_PORT_MULTI_CHANNEL_0(0)), + SB_PGD_TX_PORTn_MULTI_CHNL_0, 0xFF, WCD934X_REG_BITS, 0x4 + }, + { + 1, + (WCD934X_REGISTER_START_OFFSET + + SB_PGD_TX_PORT_MULTI_CHANNEL_1(0)), + SB_PGD_TX_PORTn_MULTI_CHNL_1, 0xFF, WCD934X_REG_BITS, 0x4 + }, + { + 1, + (WCD934X_REGISTER_START_OFFSET + + SB_PGD_RX_PORT_MULTI_CHANNEL_0(0x180, 0)), + SB_PGD_RX_PORTn_MULTI_CHNL_0, 0xFF, WCD934X_REG_BITS, 0x4 + }, + { + 1, + (WCD934X_REGISTER_START_OFFSET + + SB_PGD_RX_PORT_MULTI_CHANNEL_0(0x181, 0)), + SB_PGD_RX_PORTn_MULTI_CHNL_1, 0xFF, WCD934X_REG_BITS, 0x4 + }, }; static struct afe_param_cdc_reg_cfg_data tavil_audio_reg_cfg = { @@ -530,6 +583,9 @@ struct tavil_priv { struct wcd934x_swr swr; struct mutex micb_lock; + struct delayed_work power_gate_work; + struct mutex power_lock; + struct clk *wcd_ext_clk; /* mbhc module */ @@ -563,6 +619,8 @@ struct tavil_priv { int main_clk_users[WCD934X_NUM_INTERPOLATORS]; struct tavil_dsd_config *dsd_config; struct tavil_idle_detect_config idle_det_cfg; + + int power_active_ref; }; static const struct tavil_reg_mask_val tavil_spkr_default[] = { @@ -1817,6 +1875,9 @@ static int tavil_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, usleep_range(7000, 7100); clear_bit(HPH_PA_DELAY, &tavil->status_mask); } + + snd_soc_update_bits(codec, WCD934X_HPH_R_TEST, 0x01, 0x01); + /* Remove mute */ snd_soc_update_bits(codec, WCD934X_CDC_RX2_RX_PATH_CTL, 0x10, 0x00); @@ -1839,18 +1900,27 @@ static int tavil_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, tavil_codec_override(codec, tavil->hph_mode, event); break; case SND_SOC_DAPM_PRE_PMD: + blocking_notifier_call_chain(&tavil->mbhc->notifier, + WCD_EVENT_PRE_HPHR_PA_OFF, + &tavil->mbhc->wcd_mbhc); /* Enable DSD Mute before PA disable */ if (dsd_conf && (snd_soc_read(codec, WCD934X_CDC_DSD1_PATH_CTL) & 0x01)) snd_soc_update_bits(codec, WCD934X_CDC_DSD1_CFG2, 0x04, 0x04); + snd_soc_update_bits(codec, WCD934X_HPH_R_TEST, 0x01, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_RX2_RX_PATH_CTL, + 0x10, 0x10); break; case SND_SOC_DAPM_POST_PMD: + /* 5ms sleep is required after PA disable */ + usleep_range(5000, 5100); tavil_codec_override(codec, tavil->hph_mode, event); + blocking_notifier_call_chain(&tavil->mbhc->notifier, + WCD_EVENT_POST_HPHR_PA_OFF, + &tavil->mbhc->wcd_mbhc); snd_soc_update_bits(codec, WCD934X_HPH_REFBUFF_LP_CTL, 0x06, 0x0); - /* 5ms sleep is required after PA disable */ - usleep_range(5000, 5100); break; }; @@ -1888,6 +1958,7 @@ static int tavil_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, usleep_range(7000, 7100); clear_bit(HPH_PA_DELAY, &tavil->status_mask); } + snd_soc_update_bits(codec, WCD934X_HPH_L_TEST, 0x01, 0x01); /* Remove Mute on primary path */ snd_soc_update_bits(codec, WCD934X_CDC_RX1_RX_PATH_CTL, 0x10, 0x00); @@ -1910,18 +1981,28 @@ static int tavil_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, tavil_codec_override(codec, tavil->hph_mode, event); break; case SND_SOC_DAPM_PRE_PMD: + blocking_notifier_call_chain(&tavil->mbhc->notifier, + WCD_EVENT_PRE_HPHL_PA_OFF, + &tavil->mbhc->wcd_mbhc); /* Enable DSD Mute before PA disable */ if (dsd_conf && (snd_soc_read(codec, WCD934X_CDC_DSD0_PATH_CTL) & 0x01)) snd_soc_update_bits(codec, WCD934X_CDC_DSD0_CFG2, 0x04, 0x04); + + snd_soc_update_bits(codec, WCD934X_HPH_L_TEST, 0x01, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_RX1_RX_PATH_CTL, + 0x10, 0x10); break; case SND_SOC_DAPM_POST_PMD: + /* 5ms sleep is required after PA disable */ + usleep_range(5000, 5100); tavil_codec_override(codec, tavil->hph_mode, event); + blocking_notifier_call_chain(&tavil->mbhc->notifier, + WCD_EVENT_POST_HPHL_PA_OFF, + &tavil->mbhc->wcd_mbhc); snd_soc_update_bits(codec, WCD934X_HPH_REFBUFF_LP_CTL, 0x06, 0x0); - /* 5ms sleep is required after PA disable */ - usleep_range(5000, 5100); break; }; @@ -4094,13 +4175,12 @@ int tavil_codec_enable_standalone_micbias(struct snd_soc_codec *codec, } if (enable) - rc = snd_soc_dapm_force_enable_pin_unlocked( + rc = snd_soc_dapm_force_enable_pin( snd_soc_codec_get_dapm(codec), micb_names[micb_index]); else - rc = snd_soc_dapm_disable_pin_unlocked( - snd_soc_codec_get_dapm(codec), - micb_names[micb_index]); + rc = snd_soc_dapm_disable_pin(snd_soc_codec_get_dapm(codec), + micb_names[micb_index]); if (!rc) snd_soc_dapm_sync(snd_soc_codec_get_dapm(codec)); @@ -4144,6 +4224,244 @@ static int tavil_codec_enable_micbias(struct snd_soc_dapm_widget *w, return __tavil_codec_enable_micbias(w, event); } + +static const struct reg_sequence tavil_hph_reset_tbl[] = { + { WCD934X_HPH_CNP_EN, 0x80 }, + { WCD934X_HPH_CNP_WG_CTL, 0x9A }, + { WCD934X_HPH_CNP_WG_TIME, 0x14 }, + { WCD934X_HPH_OCP_CTL, 0x28 }, + { WCD934X_HPH_AUTO_CHOP, 0x16 }, + { WCD934X_HPH_CHOP_CTL, 0x83 }, + { WCD934X_HPH_PA_CTL1, 0x46 }, + { WCD934X_HPH_PA_CTL2, 0x50 }, + { WCD934X_HPH_L_EN, 0x80 }, + { WCD934X_HPH_L_TEST, 0xE0 }, + { WCD934X_HPH_L_ATEST, 0x50 }, + { WCD934X_HPH_R_EN, 0x80 }, + { WCD934X_HPH_R_TEST, 0xE0 }, + { WCD934X_HPH_R_ATEST, 0x54 }, + { WCD934X_HPH_RDAC_CLK_CTL1, 0x99 }, + { WCD934X_HPH_RDAC_CLK_CTL2, 0x9B }, + { WCD934X_HPH_RDAC_LDO_CTL, 0x33 }, + { WCD934X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00 }, + { WCD934X_HPH_REFBUFF_UHQA_CTL, 0xA8 }, + { WCD934X_HPH_REFBUFF_LP_CTL, 0x0A }, + { WCD934X_HPH_L_DAC_CTL, 0x00 }, + { WCD934X_HPH_R_DAC_CTL, 0x00 }, + { WCD934X_HPH_NEW_ANA_HPH2, 0x00 }, + { WCD934X_HPH_NEW_ANA_HPH3, 0x00 }, + { WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x00 }, + { WCD934X_HPH_NEW_INT_RDAC_HD2_CTL, 0xA0 }, + { WCD934X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10 }, + { WCD934X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00 }, + { WCD934X_HPH_NEW_INT_RDAC_MISC1, 0x00 }, + { WCD934X_HPH_NEW_INT_PA_MISC1, 0x22 }, + { WCD934X_HPH_NEW_INT_PA_MISC2, 0x00 }, + { WCD934X_HPH_NEW_INT_PA_RDAC_MISC, 0x00 }, + { WCD934X_HPH_NEW_INT_HPH_TIMER1, 0xFE }, + { WCD934X_HPH_NEW_INT_HPH_TIMER2, 0x2 }, + { WCD934X_HPH_NEW_INT_HPH_TIMER3, 0x4e}, + { WCD934X_HPH_NEW_INT_HPH_TIMER4, 0x54 }, + { WCD934X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00 }, + { WCD934X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00 }, +}; + +static const struct tavil_reg_mask_val tavil_pa_disable[] = { + { WCD934X_CDC_RX1_RX_PATH_CTL, 0x30, 0x10 }, /* RX1 mute enable */ + { WCD934X_CDC_RX2_RX_PATH_CTL, 0x30, 0x10 }, /* RX2 mute enable */ + { WCD934X_HPH_CNP_WG_CTL, 0x80, 0x00 }, /* GM3 boost disable */ + { WCD934X_ANA_HPH, 0x80, 0x00 }, /* HPHL PA disable */ + { WCD934X_ANA_HPH, 0x40, 0x00 }, /* HPHR PA disable */ + { WCD934X_ANA_HPH, 0x20, 0x00 }, /* HPHL REF dsable */ + { WCD934X_ANA_HPH, 0x10, 0x00 }, /* HPHR REF disable */ +}; + +static const struct tavil_reg_mask_val tavil_ocp_en_seq[] = { + { WCD934X_RX_OCP_CTL, 0x0F, 0x01 }, /* OCP number of attempts is 1 */ + { WCD934X_HPH_OCP_CTL, 0xFA, 0x3A }, /* OCP current limit */ + { WCD934X_HPH_L_TEST, 0x01, 0x01 }, /* Enable HPHL OCP */ + { WCD934X_HPH_R_TEST, 0x01, 0x01 }, /* Enable HPHR OCP */ +}; + +static const struct tavil_reg_mask_val tavil_ocp_en_seq_1[] = { + { WCD934X_RX_OCP_CTL, 0x0F, 0x01 }, /* OCP number of attempts is 1 */ + { WCD934X_HPH_OCP_CTL, 0xFA, 0x3A }, /* OCP current limit */ +}; + +/* LO-HIFI */ +static const struct tavil_reg_mask_val tavil_pre_pa_en_lohifi[] = { + { WCD934X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00 }, + { WCD934X_HPH_NEW_INT_PA_MISC2, 0x20, 0x20 }, + { WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xf0, 0x40 }, + { WCD934X_HPH_CNP_WG_CTL, 0x80, 0x00 }, + { WCD934X_RX_BIAS_HPH_LOWPOWER, 0xf0, 0xc0 }, + { WCD934X_HPH_PA_CTL1, 0x0e, 0x02 }, + { WCD934X_HPH_REFBUFF_LP_CTL, 0x06, 0x06 }, +}; + +static const struct tavil_reg_mask_val tavil_pre_pa_en[] = { + { WCD934X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00 }, + { WCD934X_HPH_NEW_INT_PA_MISC2, 0x20, 0x0 }, + { WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xf0, 0x40 }, + { WCD934X_HPH_CNP_WG_CTL, 0x80, 0x00 }, + { WCD934X_RX_BIAS_HPH_LOWPOWER, 0xf0, 0x80 }, + { WCD934X_HPH_PA_CTL1, 0x0e, 0x06 }, + { WCD934X_HPH_REFBUFF_LP_CTL, 0x06, 0x06 }, +}; + +static const struct tavil_reg_mask_val tavil_post_pa_en[] = { + { WCD934X_HPH_L_TEST, 0x01, 0x01 }, /* Enable HPHL OCP */ + { WCD934X_HPH_R_TEST, 0x01, 0x01 }, /* Enable HPHR OCP */ + { WCD934X_CDC_RX1_RX_PATH_CTL, 0x30, 0x20 }, /* RX1 mute disable */ + { WCD934X_CDC_RX2_RX_PATH_CTL, 0x30, 0x20 }, /* RX2 mute disable */ + { WCD934X_HPH_CNP_WG_CTL, 0x80, 0x80 }, /* GM3 boost enable */ + { WCD934X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x02 }, +}; + +static void tavil_codec_hph_reg_range_read(struct regmap *map, u8 *buf) +{ + regmap_bulk_read(map, WCD934X_HPH_CNP_EN, buf, TAVIL_HPH_REG_RANGE_1); + regmap_bulk_read(map, WCD934X_HPH_NEW_ANA_HPH2, + buf + TAVIL_HPH_REG_RANGE_1, TAVIL_HPH_REG_RANGE_2); + regmap_bulk_read(map, WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL, + buf + TAVIL_HPH_REG_RANGE_1 + TAVIL_HPH_REG_RANGE_2, + TAVIL_HPH_REG_RANGE_3); +} + +static void tavil_codec_hph_reg_recover(struct tavil_priv *tavil, + struct regmap *map, int pa_status) +{ + int i; + + blocking_notifier_call_chain(&tavil->mbhc->notifier, + WCD_EVENT_OCP_OFF, + &tavil->mbhc->wcd_mbhc); + + if (pa_status & 0xC0) + goto pa_en_restore; + + dev_dbg(tavil->dev, "%s: HPH PA in disable state (0x%x)\n", + __func__, pa_status); + + regmap_write_bits(map, WCD934X_CDC_RX1_RX_PATH_CTL, 0x10, 0x10); + regmap_write_bits(map, WCD934X_CDC_RX2_RX_PATH_CTL, 0x10, 0x10); + regmap_write_bits(map, WCD934X_ANA_HPH, 0xC0, 0x00); + regmap_write_bits(map, WCD934X_ANA_HPH, 0x30, 0x00); + regmap_write_bits(map, WCD934X_CDC_RX1_RX_PATH_CTL, 0x10, 0x00); + regmap_write_bits(map, WCD934X_CDC_RX2_RX_PATH_CTL, 0x10, 0x00); + + /* Restore to HW defaults */ + regmap_multi_reg_write(map, tavil_hph_reset_tbl, + ARRAY_SIZE(tavil_hph_reset_tbl)); + + for (i = 0; i < ARRAY_SIZE(tavil_ocp_en_seq); i++) + regmap_write_bits(map, tavil_ocp_en_seq[i].reg, + tavil_ocp_en_seq[i].mask, + tavil_ocp_en_seq[i].val); + goto end; + + +pa_en_restore: + dev_dbg(tavil->dev, "%s: HPH PA in enable state (0x%x)\n", + __func__, pa_status); + + /* Disable PA and other registers before restoring */ + for (i = 0; i < ARRAY_SIZE(tavil_pa_disable); i++) + regmap_write_bits(map, tavil_pa_disable[i].reg, + tavil_pa_disable[i].mask, + tavil_pa_disable[i].val); + + regmap_multi_reg_write(map, tavil_hph_reset_tbl, + ARRAY_SIZE(tavil_hph_reset_tbl)); + + for (i = 0; i < ARRAY_SIZE(tavil_ocp_en_seq_1); i++) + regmap_write_bits(map, tavil_ocp_en_seq_1[i].reg, + tavil_ocp_en_seq_1[i].mask, + tavil_ocp_en_seq_1[i].val); + + if (tavil->hph_mode == CLS_H_LOHIFI) { + for (i = 0; i < ARRAY_SIZE(tavil_pre_pa_en_lohifi); i++) + regmap_write_bits(map, + tavil_pre_pa_en_lohifi[i].reg, + tavil_pre_pa_en_lohifi[i].mask, + tavil_pre_pa_en_lohifi[i].val); + } else { + for (i = 0; i < ARRAY_SIZE(tavil_pre_pa_en); i++) + regmap_write_bits(map, tavil_pre_pa_en[i].reg, + tavil_pre_pa_en[i].mask, + tavil_pre_pa_en[i].val); + } + regmap_write_bits(map, WCD934X_ANA_HPH, 0x0C, pa_status & 0x0C); + regmap_write_bits(map, WCD934X_ANA_HPH, 0x30, 0x30); + /* wait for 100usec after HPH DAC is enabled */ + usleep_range(100, 110); + regmap_write(map, WCD934X_ANA_HPH, pa_status); + /* Sleep for 7msec after PA is enabled */ + usleep_range(7000, 7100); + + for (i = 0; i < ARRAY_SIZE(tavil_post_pa_en); i++) + regmap_write_bits(map, tavil_post_pa_en[i].reg, + tavil_post_pa_en[i].mask, + tavil_post_pa_en[i].val); + +end: + tavil->mbhc->is_hph_recover = true; + blocking_notifier_call_chain( + &tavil->mbhc->notifier, + WCD_EVENT_OCP_ON, + &tavil->mbhc->wcd_mbhc); +} + +static int tavil_codec_reset_hph_registers(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct tavil_priv *tavil = snd_soc_codec_get_drvdata(codec); + struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent); + u8 cache_val[TAVIL_HPH_TOTAL_REG]; + u8 hw_val[TAVIL_HPH_TOTAL_REG]; + int pa_status; + int ret; + + dev_dbg(wcd9xxx->dev, "%s: event: %d\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + memset(cache_val, 0, TAVIL_HPH_TOTAL_REG); + memset(hw_val, 0, TAVIL_HPH_TOTAL_REG); + + regmap_read(wcd9xxx->regmap, WCD934X_ANA_HPH, &pa_status); + + tavil_codec_hph_reg_range_read(wcd9xxx->regmap, cache_val); + + /* Read register values from HW directly */ + regcache_cache_bypass(wcd9xxx->regmap, true); + tavil_codec_hph_reg_range_read(wcd9xxx->regmap, hw_val); + regcache_cache_bypass(wcd9xxx->regmap, false); + + /* compare both the registers to know if there is corruption */ + ret = memcmp(cache_val, hw_val, TAVIL_HPH_TOTAL_REG); + + /* If both the values are same, it means no corruption */ + if (ret) { + dev_dbg(codec->dev, "%s: cache and hw reg are not same\n", + __func__); + tavil_codec_hph_reg_recover(tavil, wcd9xxx->regmap, + pa_status); + } else { + dev_dbg(codec->dev, "%s: cache and hw reg are same\n", + __func__); + tavil->mbhc->is_hph_recover = false; + } + break; + default: + break; + }; + + return 0; +} + static int tavil_iir_enable_audio_mixer_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { @@ -4904,6 +5222,10 @@ static const struct snd_kcontrol_new tavil_snd_controls[] = { -84, 40, digital_gain), SOC_SINGLE_SX_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL, 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL, 0, + -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL, 0, + -84, 40, digital_gain), SOC_SINGLE_SX_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL, 0, -84, 40, digital_gain), SOC_SINGLE_SX_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL, 0, @@ -6174,6 +6496,14 @@ static const struct snd_soc_dapm_widget tavil_dapm_widgets[] = { tavil_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + /* + * Not supply widget, this is used to recover HPH registers. + * It is not connected to any other widgets + */ + SND_SOC_DAPM_SUPPLY("RESET_HPH_REGISTERS", SND_SOC_NOPM, + 0, 0, tavil_codec_reset_hph_registers, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MICBIAS_E(DAPM_MICBIAS1_STANDALONE, SND_SOC_NOPM, 0, 0, tavil_codec_force_enable_micbias, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), @@ -7067,6 +7397,136 @@ static struct snd_soc_dai_driver tavil_dai[] = { }, }; +static void tavil_codec_power_gate_digital_core(struct tavil_priv *tavil) +{ + struct snd_soc_codec *codec = tavil->codec; + + if (!codec) + return; + + mutex_lock(&tavil->power_lock); + dev_dbg(codec->dev, "%s: Entering power gating function, %d\n", + __func__, tavil->power_active_ref); + + if (tavil->power_active_ref > 0) + goto exit; + + wcd9xxx_set_power_state(tavil->wcd9xxx, + WCD_REGION_POWER_COLLAPSE_BEGIN, + WCD9XXX_DIG_CORE_REGION_1); + snd_soc_update_bits(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, + 0x04, 0x04); + snd_soc_update_bits(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, + 0x01, 0x00); + snd_soc_update_bits(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, + 0x02, 0x00); + wcd9xxx_set_power_state(tavil->wcd9xxx, WCD_REGION_POWER_DOWN, + WCD9XXX_DIG_CORE_REGION_1); +exit: + dev_dbg(codec->dev, "%s: Exiting power gating function, %d\n", + __func__, tavil->power_active_ref); + mutex_unlock(&tavil->power_lock); +} + +static void tavil_codec_power_gate_work(struct work_struct *work) +{ + struct tavil_priv *tavil; + struct delayed_work *dwork; + struct snd_soc_codec *codec; + + dwork = to_delayed_work(work); + tavil = container_of(dwork, struct tavil_priv, power_gate_work); + codec = tavil->codec; + + if (!codec) + return; + + tavil_codec_power_gate_digital_core(tavil); +} + +/* called under power_lock acquisition */ +static int tavil_dig_core_remove_power_collapse(struct snd_soc_codec *codec) +{ + struct tavil_priv *tavil = snd_soc_codec_get_drvdata(codec); + + snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); + snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); + snd_soc_write(codec, WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); + snd_soc_update_bits(codec, WCD934X_CODEC_RPM_RST_CTL, 0x02, 0x00); + snd_soc_update_bits(codec, WCD934X_CODEC_RPM_RST_CTL, 0x02, 0x02); + + wcd9xxx_set_power_state(tavil->wcd9xxx, + WCD_REGION_POWER_COLLAPSE_REMOVE, + WCD9XXX_DIG_CORE_REGION_1); + regcache_mark_dirty(codec->component.regmap); + regcache_sync_region(codec->component.regmap, + WCD934X_DIG_CORE_REG_MIN, + WCD934X_DIG_CORE_REG_MAX); + + return 0; +} + +static int tavil_dig_core_power_collapse(struct tavil_priv *tavil, + int req_state) +{ + struct snd_soc_codec *codec; + int cur_state; + + /* Exit if feature is disabled */ + if (!dig_core_collapse_enable) + return 0; + + mutex_lock(&tavil->power_lock); + if (req_state == POWER_COLLAPSE) + tavil->power_active_ref--; + else if (req_state == POWER_RESUME) + tavil->power_active_ref++; + else + goto unlock_mutex; + + if (tavil->power_active_ref < 0) { + dev_dbg(tavil->dev, "%s: power_active_ref is negative\n", + __func__); + goto unlock_mutex; + } + + codec = tavil->codec; + if (!codec) + goto unlock_mutex; + + if (req_state == POWER_COLLAPSE) { + if (tavil->power_active_ref == 0) { + schedule_delayed_work(&tavil->power_gate_work, + msecs_to_jiffies(dig_core_collapse_timer * 1000)); + } + } else if (req_state == POWER_RESUME) { + if (tavil->power_active_ref == 1) { + /* + * At this point, there can be two cases: + * 1. Core already in power collapse state + * 2. Timer kicked in and still did not expire or + * waiting for the power_lock + */ + cur_state = wcd9xxx_get_current_power_state( + tavil->wcd9xxx, + WCD9XXX_DIG_CORE_REGION_1); + if (cur_state == WCD_REGION_POWER_DOWN) { + tavil_dig_core_remove_power_collapse(codec); + } else { + mutex_unlock(&tavil->power_lock); + cancel_delayed_work_sync( + &tavil->power_gate_work); + mutex_lock(&tavil->power_lock); + } + } + } + +unlock_mutex: + mutex_unlock(&tavil->power_lock); + + return 0; +} + static int tavil_cdc_req_mclk_enable(struct tavil_priv *tavil, bool enable) { @@ -7108,15 +7568,15 @@ static int __tavil_cdc_mclk_enable_locked(struct tavil_priv *tavil, dev_dbg(tavil->dev, "%s: mclk_enable = %u\n", __func__, enable); if (enable) { + tavil_dig_core_power_collapse(tavil, POWER_RESUME); tavil_vote_svs(tavil, true); ret = tavil_cdc_req_mclk_enable(tavil, true); if (ret) goto done; - - set_bit(AUDIO_NOMINAL, &tavil->status_mask); } else { tavil_cdc_req_mclk_enable(tavil, false); tavil_vote_svs(tavil, false); + tavil_dig_core_power_collapse(tavil, POWER_COLLAPSE); } done: @@ -7362,6 +7822,10 @@ static const struct tavil_reg_mask_val tavil_codec_reg_defaults[] = { {WCD934X_CDC_TX6_TX_PATH_CFG1, 0x01, 0x00}, {WCD934X_CDC_TX7_TX_PATH_CFG1, 0x01, 0x00}, {WCD934X_CDC_TX8_TX_PATH_CFG1, 0x01, 0x00}, + {WCD934X_RX_OCP_CTL, 0x0F, 0x01}, /* OCP number of attempts is 1 */ + {WCD934X_HPH_OCP_CTL, 0xFF, 0x3A}, /* OCP current limit */ + {WCD934X_HPH_L_TEST, 0x01, 0x01}, + {WCD934X_HPH_R_TEST, 0x01, 0x01}, }; static const struct tavil_reg_mask_val tavil_codec_reg_init_common_val[] = { @@ -8050,6 +8514,9 @@ static int tavil_suspend(struct device *dev) return -EINVAL; } dev_dbg(dev, "%s: system suspend\n", __func__); + if (delayed_work_pending(&tavil->power_gate_work) && + cancel_delayed_work_sync(&tavil->power_gate_work)) + tavil_codec_power_gate_digital_core(tavil); return 0; } @@ -8551,6 +9018,7 @@ static int tavil_probe(struct platform_device *pdev) struct tavil_priv *tavil; struct clk *wcd_ext_clk; struct wcd9xxx_resmgr_v2 *resmgr; + struct wcd9xxx_power_region *cdc_pwr; tavil = devm_kzalloc(&pdev->dev, sizeof(struct tavil_priv), GFP_KERNEL); @@ -8561,6 +9029,8 @@ static int tavil_probe(struct platform_device *pdev) tavil->wcd9xxx = dev_get_drvdata(pdev->dev.parent); tavil->dev = &pdev->dev; + INIT_DELAYED_WORK(&tavil->power_gate_work, tavil_codec_power_gate_work); + mutex_init(&tavil->power_lock); INIT_WORK(&tavil->tavil_add_child_devices_work, tavil_add_child_devices); mutex_init(&tavil->micb_lock); @@ -8577,6 +9047,18 @@ static int tavil_probe(struct platform_device *pdev) */ tavil->svs_ref_cnt = 1; + cdc_pwr = devm_kzalloc(&pdev->dev, sizeof(struct wcd9xxx_power_region), + GFP_KERNEL); + if (!cdc_pwr) { + ret = -ENOMEM; + goto err_resmgr; + } + tavil->wcd9xxx->wcd9xxx_pwr[WCD9XXX_DIG_CORE_REGION_1] = cdc_pwr; + cdc_pwr->pwr_collapse_reg_min = WCD934X_DIG_CORE_REG_MIN; + cdc_pwr->pwr_collapse_reg_max = WCD934X_DIG_CORE_REG_MAX; + wcd9xxx_set_power_state(tavil->wcd9xxx, + WCD_REGION_POWER_COLLAPSE_REMOVE, + WCD9XXX_DIG_CORE_REGION_1); /* * Init resource manager so that if child nodes such as SoundWire * requests for clock, resource manager can honor the request diff --git a/sound/soc/codecs/wsa881x.c b/sound/soc/codecs/wsa881x.c index 46a073bac2e9..28fd8930adb2 100644 --- a/sound/soc/codecs/wsa881x.c +++ b/sound/soc/codecs/wsa881x.c @@ -1305,7 +1305,8 @@ static int wsa881x_swr_down(struct swr_device *pdev) dev_err(&pdev->dev, "%s: wsa881x is NULL\n", __func__); return -EINVAL; } - cancel_delayed_work_sync(&wsa881x->ocp_ctl_work); + if (delayed_work_pending(&wsa881x->ocp_ctl_work)) + cancel_delayed_work_sync(&wsa881x->ocp_ctl_work); ret = wsa881x_gpio_ctrl(wsa881x, false); if (ret) dev_err(&pdev->dev, "%s: Failed to disable gpio\n", __func__); diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig index 5660a12f3f12..64a1fa76604d 100644 --- a/sound/soc/msm/Kconfig +++ b/sound/soc/msm/Kconfig @@ -79,6 +79,15 @@ config QTI_PP tuning parameters of various modules such as equalizer, customized mixing. +config QTI_PP_AUDIOSPHERE + bool "Enable QTI AUDIOSPHERE PP" + depends on SND_SOC_MSM_QDSP6V2_INTF + help + To add support for QTI audio sphere post processing. + This support is to configure the post processing + parameters to DSP. The configuration includes sending + tuning parameters of audio sphere module. + config SND_SOC_CPE tristate "CPE drivers" depends on SND_SOC_WCD_CPE @@ -104,6 +113,7 @@ config SND_SOC_MSM8996 select SND_SOC_MSM_HDMI_CODEC_RX select DTS_SRS_TM select QTI_PP + select QTI_PP_AUDIOSPHERE select SND_SOC_CPE select MSM_ULTRASOUND select DOLBY_DS2 diff --git a/sound/soc/msm/msm-cpe-lsm.c b/sound/soc/msm/msm-cpe-lsm.c index 8270cfb98de8..ef4c9b01d91e 100644 --- a/sound/soc/msm/msm-cpe-lsm.c +++ b/sound/soc/msm/msm-cpe-lsm.c @@ -496,7 +496,7 @@ static int msm_cpe_lab_buf_alloc(struct snd_pcm_substream *substream, pcm_buf[count].mem = pcm_buf[0].mem + (count * bufsz); pcm_buf[count].phys = pcm_buf[0].phys + (count * bufsz); dev_dbg(rtd->dev, - "%s: pcm_buf[%d].mem %p pcm_buf[%d].phys %pa\n", + "%s: pcm_buf[%d].mem %pK pcm_buf[%d].phys %pK\n", __func__, count, (void *)pcm_buf[count].mem, count, &(pcm_buf[count].phys)); @@ -722,7 +722,7 @@ static int msm_cpe_lab_thread(void *data) cur_buf = &lab_d->pcm_buf[buf_count % prd_cnt]; next_buf = &lab_d->pcm_buf[(buf_count + 2) % prd_cnt]; dev_dbg(rtd->dev, - "%s: Cur buf.mem = %p Next Buf.mem = %p\n" + "%s: Cur buf.mem = %pK Next Buf.mem = %pK\n" " buf count = 0x%x\n", __func__, cur_buf->mem, next_buf->mem, buf_count); } else { @@ -1544,7 +1544,7 @@ static int msm_cpe_lsm_lab_start(struct snd_pcm_substream *substream, int rc; if (!substream || !substream->private_data) { - pr_err("%s: invalid substream (%p)\n", + pr_err("%s: invalid substream (%pK)\n", __func__, substream); return -EINVAL; } @@ -1634,7 +1634,7 @@ static bool msm_cpe_lsm_is_valid_stream(struct snd_pcm_substream *substream, struct wcd_cpe_lsm_ops *lsm_ops; if (!substream || !substream->private_data) { - pr_err("%s: invalid substream (%p)\n", + pr_err("%s: invalid substream (%pK)\n", func, substream); return false; } @@ -2075,7 +2075,7 @@ static int msm_cpe_lsm_ioctl(struct snd_pcm_substream *substream, struct wcd_cpe_lsm_ops *lsm_ops; if (!substream || !substream->private_data) { - pr_err("%s: invalid substream (%p)\n", + pr_err("%s: invalid substream (%pK)\n", __func__, substream); return -EINVAL; } @@ -2347,7 +2347,7 @@ static int msm_cpe_lsm_ioctl_compat(struct snd_pcm_substream *substream, struct wcd_cpe_lsm_ops *lsm_ops; if (!substream || !substream->private_data) { - pr_err("%s: invalid substream (%p)\n", + pr_err("%s: invalid substream (%pK)\n", __func__, substream); return -EINVAL; } @@ -2997,7 +2997,7 @@ static int msm_cpe_lsm_copy(struct snd_pcm_substream *substream, int a, if (lab_d->buf_idx >= (lsm_d->hw_params.period_count)) lab_d->buf_idx = 0; pcm_buf = (lab_d->pcm_buf[lab_d->buf_idx].mem); - pr_debug("%s: Buf IDX = 0x%x pcm_buf %p\n", + pr_debug("%s: Buf IDX = 0x%x pcm_buf %pK\n", __func__, lab_d->buf_idx, pcm_buf); if (pcm_buf) { if (copy_to_user(buf, pcm_buf, fbytes)) { diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c index 4e3745d4d976..4e93780c4da0 100644 --- a/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c +++ b/sound/soc/msm/qdsp6v2/msm-pcm-q6-v2.c @@ -57,6 +57,7 @@ struct snd_msm { #define CMD_EOS_MIN_TIMEOUT_LENGTH 50 #define CMD_EOS_TIMEOUT_MULTIPLIER (HZ * 50) +#define MAX_PB_COPY_RETRIES 3 static struct snd_pcm_hardware msm_pcm_hardware_capture = { .info = (SNDRV_PCM_INFO_MMAP | @@ -629,6 +630,7 @@ static int msm_pcm_playback_copy(struct snd_pcm_substream *substream, int a, void *data = NULL; uint32_t idx = 0; uint32_t size = 0; + uint32_t retries = 0; struct snd_pcm_runtime *runtime = substream->runtime; struct msm_audio *prtd = runtime->private_data; @@ -637,7 +639,7 @@ static int msm_pcm_playback_copy(struct snd_pcm_substream *substream, int a, pr_debug("%s: prtd->out_count = %d\n", __func__, atomic_read(&prtd->out_count)); - while (fbytes > 0) { + while ((fbytes > 0) && (retries < MAX_PB_COPY_RETRIES)) { if (prtd->reset_event) { pr_err("%s: In SSR return ENETRESET before wait\n", __func__); @@ -666,6 +668,13 @@ static int msm_pcm_playback_copy(struct snd_pcm_substream *substream, int a, data = q6asm_is_cpu_buf_avail(IN, prtd->audio_client, &size, &idx); + if (data == NULL) { + retries++; + continue; + } else { + retries = 0; + } + if (fbytes > size) xfer = size; else @@ -677,6 +686,9 @@ static int msm_pcm_playback_copy(struct snd_pcm_substream *substream, int a, __func__, fbytes, xfer, size); if (copy_from_user(bufptr, buf, xfer)) { ret = -EFAULT; + pr_err("%s: copy_from_user failed\n", + __func__); + q6asm_cpu_buf_release(IN, prtd->audio_client); goto fail; } buf += xfer; @@ -690,6 +702,8 @@ static int msm_pcm_playback_copy(struct snd_pcm_substream *substream, int a, 0, 0, NO_TIMESTAMP); if (ret < 0) { ret = -EFAULT; + q6asm_cpu_buf_release(IN, + prtd->audio_client); goto fail; } } else @@ -698,6 +712,9 @@ static int msm_pcm_playback_copy(struct snd_pcm_substream *substream, int a, } } fail: + if (retries >= MAX_PB_COPY_RETRIES) + ret = -ENOMEM; + return ret; } @@ -802,6 +819,7 @@ static int msm_pcm_capture_copy(struct snd_pcm_substream *substream, if (copy_to_user(buf, bufptr+offset, xfer)) { pr_err("Failed to copy buf to user\n"); ret = -EFAULT; + q6asm_cpu_buf_release(OUT, prtd->audio_client); goto fail; } fbytes -= xfer; @@ -817,6 +835,7 @@ static int msm_pcm_capture_copy(struct snd_pcm_substream *substream, if (ret < 0) { pr_err("q6asm read failed\n"); ret = -EFAULT; + q6asm_cpu_buf_release(OUT, prtd->audio_client); goto fail; } } else diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c index 7e3653955a64..5c40c55a4a0c 100644 --- a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c +++ b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c @@ -177,7 +177,10 @@ static void msm_pcm_routing_cfg_pp(int port_id, int copp_idx, int topology, break; case ADM_CMD_COPP_OPEN_TOPOLOGY_ID_AUDIOSPHERE: pr_debug("%s: TOPOLOGY_ID_AUDIOSPHERE\n", __func__); - msm_qti_pp_asphere_init(port_id, copp_idx); + rc = msm_qti_pp_asphere_init(port_id, copp_idx); + if (rc < 0) + pr_err("%s: topo_id 0x%x, port %d, copp %d, rc %d\n", + __func__, topology, port_id, copp_idx, rc); break; default: /* custom topology specific feature param handlers */ @@ -223,22 +226,27 @@ static void msm_pcm_routing_deinit_pp(int port_id, int topology) static void msm_pcm_routng_cfg_matrix_map_pp(struct route_payload payload, int path_type, int perf_mode) { - int itr = 0; + int itr = 0, rc = 0; if ((path_type == ADM_PATH_PLAYBACK) && (perf_mode == LEGACY_PCM_MODE) && is_custom_stereo_on) { for (itr = 0; itr < payload.num_copps; itr++) { - if ((payload.port_id[itr] == SLIMBUS_0_RX) || - (payload.port_id[itr] == RT_PROXY_PORT_001_RX)) { - msm_qti_pp_send_stereo_to_custom_stereo_cmd( - payload.port_id[itr], - payload.copp_idx[itr], - payload.session_id, - Q14_GAIN_ZERO_POINT_FIVE, - Q14_GAIN_ZERO_POINT_FIVE, - Q14_GAIN_ZERO_POINT_FIVE, - Q14_GAIN_ZERO_POINT_FIVE); + if ((payload.port_id[itr] != SLIMBUS_0_RX) && + (payload.port_id[itr] != RT_PROXY_PORT_001_RX)) { + continue; } + + rc = msm_qti_pp_send_stereo_to_custom_stereo_cmd( + payload.port_id[itr], + payload.copp_idx[itr], + payload.session_id, + Q14_GAIN_ZERO_POINT_FIVE, + Q14_GAIN_ZERO_POINT_FIVE, + Q14_GAIN_ZERO_POINT_FIVE, + Q14_GAIN_ZERO_POINT_FIVE); + if (rc < 0) + pr_err("%s: err setting custom stereo\n", + __func__); } } } @@ -8899,6 +8907,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia5 Mixer", "MI2S_TX", "MI2S_TX"}, {"MultiMedia1 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, {"MultiMedia2 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia6 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, {"MultiMedia1 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, {"MultiMedia2 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, {"MultiMedia1 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, diff --git a/sound/soc/msm/qdsp6v2/msm-qti-pp-config.c b/sound/soc/msm/qdsp6v2/msm-qti-pp-config.c index d4d22d3587ba..7c8af09a8793 100644 --- a/sound/soc/msm/qdsp6v2/msm-qti-pp-config.c +++ b/sound/soc/msm/qdsp6v2/msm-qti-pp-config.c @@ -241,6 +241,7 @@ static int msm_qti_pp_put_eq_band_audio_mixer(struct snd_kcontrol *kcontrol, return 0; } +#ifdef CONFIG_QTI_PP void msm_qti_pp_send_eq_values(int fedai_id) { if (eq_data[fedai_id].enable) @@ -325,6 +326,7 @@ skip_send_cmd: kfree(params_value); return -ENOMEM; } +#endif /* CONFIG_QTI_PP */ /* RMS */ static int msm_qti_pp_get_rms_value_control(struct snd_kcontrol *kcontrol, @@ -682,6 +684,7 @@ static int msm_qti_pp_asphere_send_params(int port_id, int copp_idx, bool force) return 0; } +#if defined(CONFIG_QTI_PP) && defined(CONFIG_QTI_PP_AUDIOSPHERE) int msm_qti_pp_asphere_init(int port_id, int copp_idx) { int index = adm_validate_and_get_port_index(port_id); @@ -719,6 +722,7 @@ void msm_qti_pp_asphere_deinit(int port_id) asphere_state.copp_idx[index] = -1; } } +#endif static int msm_qti_pp_asphere_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) @@ -976,6 +980,7 @@ static const struct snd_kcontrol_new asphere_mixer_controls[] = { 0xFFFFFFFF, 0, 2, msm_qti_pp_asphere_get, msm_qti_pp_asphere_set), }; +#ifdef CONFIG_QTI_PP void msm_qti_pp_add_controls(struct snd_soc_platform *platform) { snd_soc_add_platform_controls(platform, int_fm_vol_mixer_controls, @@ -1023,3 +1028,4 @@ void msm_qti_pp_add_controls(struct snd_soc_platform *platform) snd_soc_add_platform_controls(platform, asphere_mixer_controls, ARRAY_SIZE(asphere_mixer_controls)); } +#endif /* CONFIG_QTI_PP */ diff --git a/sound/soc/msm/qdsp6v2/msm-qti-pp-config.h b/sound/soc/msm/qdsp6v2/msm-qti-pp-config.h index 5c600f0ae866..f8a1da5e7702 100644 --- a/sound/soc/msm/qdsp6v2/msm-qti-pp-config.h +++ b/sound/soc/msm/qdsp6v2/msm-qti-pp-config.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. @@ -15,7 +15,6 @@ #include <sound/soc.h> #ifdef CONFIG_QTI_PP - void msm_qti_pp_send_eq_values(int fedai_id); int msm_qti_pp_send_stereo_to_custom_stereo_cmd(int port_id, int copp_idx, unsigned int session_id, @@ -24,32 +23,22 @@ int msm_qti_pp_send_stereo_to_custom_stereo_cmd(int port_id, int copp_idx, uint16_t op_FR_ip_FL_weight, uint16_t op_FR_ip_FR_weight); void msm_qti_pp_add_controls(struct snd_soc_platform *platform); +#else /* CONFIG_QTI_PP */ +#define msm_qti_pp_send_eq_values(fedai_id) do {} while (0) +#define msm_qti_pp_send_stereo_to_custom_stereo_cmd(port_id, copp_idx, \ + session_id, op_FL_ip_FL_weight, op_FL_ip_FR_weight, \ + op_FR_ip_FL_weight, op_FR_ip_FR_weight) (0) +#define msm_qti_pp_add_controls(platform) do {} while (0) +#endif /* CONFIG_QTI_PP */ + +#if defined(CONFIG_QTI_PP) && defined(CONFIG_QTI_PP_AUDIOSPHERE) int msm_qti_pp_asphere_init(int port_id, int copp_idx); void msm_qti_pp_asphere_deinit(int port_id); - #else - -void msm_qti_pp_send_eq_values(int fedai_id) { } -int msm_qti_pp_send_stereo_to_custom_stereo_cmd(int port_id, int copp_idx, - unsigned int session_id, - uint16_t op_FL_ip_FL_weight, - uint16_t op_FL_ip_FR_weight, - uint16_t op_FR_ip_FL_weight, - uint16_t op_FR_ip_FR_weight) -{ - return 0; -} - -void msm_qti_pp_add_controls(struct snd_soc_platform *platform) { } - -int msm_qti_pp_asphere_init(int port_id, int copp_idx) -{ - return 0; -} -void msm_qti_pp_asphere_deinit(int port_id) { } - +#define msm_qti_pp_asphere_init(port_id, copp_idx) (0) +#define msm_qti_pp_asphere_deinit(port_id) do {} while (0) #endif -#endif +#endif /* _MSM_QTI_PP_H_ */ diff --git a/sound/soc/msm/qdsp6v2/q6asm.c b/sound/soc/msm/qdsp6v2/q6asm.c index 206fbec249fa..b4257f990aa5 100644 --- a/sound/soc/msm/qdsp6v2/q6asm.c +++ b/sound/soc/msm/qdsp6v2/q6asm.c @@ -1996,6 +1996,40 @@ void *q6asm_is_cpu_buf_avail(int dir, struct audio_client *ac, uint32_t *size, return NULL; } +int q6asm_cpu_buf_release(int dir, struct audio_client *ac) +{ + struct audio_port_data *port; + int ret = 0; + int idx; + + if (!ac || ((dir != IN) && (dir != OUT))) { + pr_err("%s: ac %pK dir %d\n", __func__, ac, dir); + ret = -EINVAL; + goto exit; + } + + if (ac->io_mode & SYNC_IO_MODE) { + port = &ac->port[dir]; + mutex_lock(&port->lock); + idx = port->cpu_buf; + if (port->cpu_buf == 0) { + port->cpu_buf = port->max_buf_cnt - 1; + } else if (port->cpu_buf < port->max_buf_cnt) { + port->cpu_buf = port->cpu_buf - 1; + } else { + pr_err("%s: buffer index(%d) out of range\n", + __func__, port->cpu_buf); + ret = -EINVAL; + mutex_unlock(&port->lock); + goto exit; + } + port->buf[port->cpu_buf].used = dir ^ 1; + mutex_unlock(&port->lock); + } +exit: + return ret; +} + void *q6asm_is_cpu_buf_avail_nolock(int dir, struct audio_client *ac, uint32_t *size, uint32_t *index) { diff --git a/sound/soc/soc-dapm.c b/sound/soc/soc-dapm.c index 94806ad6437b..0700b4c00aeb 100644 --- a/sound/soc/soc-dapm.c +++ b/sound/soc/soc-dapm.c @@ -4034,10 +4034,8 @@ int snd_soc_dapm_force_enable_pin_unlocked(struct snd_soc_dapm_context *dapm, { struct snd_soc_dapm_widget *w = dapm_find_widget(dapm, pin, true); - mutex_lock_nested(&dapm->card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); if (!w) { dev_err(dapm->dev, "ASoC: unknown pin %s\n", pin); - mutex_unlock(&dapm->card->dapm_mutex); return -EINVAL; } @@ -4053,7 +4051,6 @@ int snd_soc_dapm_force_enable_pin_unlocked(struct snd_soc_dapm_context *dapm, } w->force = 1; dapm_mark_dirty(w, "force enable"); - mutex_unlock(&dapm->card->dapm_mutex); return 0; } |