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-rw-r--r--Documentation/devicetree/bindings/drm/msm/hdmi-display.txt2
-rw-r--r--arch/arm/boot/dts/qcom/Makefile3
-rw-r--r--arch/arm/boot/dts/qcom/msm8996-auto-mizar.dts328
-rw-r--r--arch/arm/boot/dts/qcom/sdm660-mtp.dts9
-rw-r--r--arch/arm/boot/dts/qcom/sdm660-qrd.dts9
-rw-r--r--drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c5
-rw-r--r--drivers/gpu/drm/msm/sde/sde_plane.c4
-rw-r--r--drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c21
-rw-r--r--drivers/net/wireless/ath/ath10k/htc.c3
-rw-r--r--drivers/power/supply/qcom/qpnp-fg-gen3.c55
-rw-r--r--drivers/soc/qcom/service-locator.c11
-rw-r--r--security/pfe/pfk_ice.c65
12 files changed, 470 insertions, 45 deletions
diff --git a/Documentation/devicetree/bindings/drm/msm/hdmi-display.txt b/Documentation/devicetree/bindings/drm/msm/hdmi-display.txt
index aaa3722659ab..9329fb74dea0 100644
--- a/Documentation/devicetree/bindings/drm/msm/hdmi-display.txt
+++ b/Documentation/devicetree/bindings/drm/msm/hdmi-display.txt
@@ -50,7 +50,7 @@ Example:
qcom,mode-v-pulse-width = <10>;
qcom,mode-v-back-porch = <72>;
qcom,mode-v-active-high;
- qcom,mode-refersh-rate = <30>;
+ qcom,mode-refresh-rate = <30>;
qcom,mode-clock-in-khz = <297000>;
};
};
diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile
index 8829ef5fd221..f7ba268b233e 100644
--- a/arch/arm/boot/dts/qcom/Makefile
+++ b/arch/arm/boot/dts/qcom/Makefile
@@ -113,7 +113,8 @@ dtb-$(CONFIG_ARCH_MSM8996) += msm8996-v2-pmi8994-cdp.dtb \
apq8096-v3-pmi8994-mdm9x55-slimbus-mtp.dtb \
apq8096-v3-pmi8996-mdm9x55-i2s-mtp.dtb \
apq8096-v3-pmi8996-mdm9x55-slimbus-mtp.dtb \
- apq8096-v3-pmi8996-dragonboard.dtb
+ apq8096-v3-pmi8996-dragonboard.dtb \
+ msm8996-auto-mizar.dtb
dtb-$(CONFIG_MSM_GVM_QUIN) += vplatform-lfv-msm8996-telematics.dtb \
vplatform-lfv-msm8996-ivi.dtb
diff --git a/arch/arm/boot/dts/qcom/msm8996-auto-mizar.dts b/arch/arm/boot/dts/qcom/msm8996-auto-mizar.dts
new file mode 100644
index 000000000000..3a7d009c12a4
--- /dev/null
+++ b/arch/arm/boot/dts/qcom/msm8996-auto-mizar.dts
@@ -0,0 +1,328 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include "msm8996pro.dtsi"
+#include "msm8996-pm8994.dtsi"
+#include "msm8996-agave-adp.dtsi"
+#include "msm8996pro-auto.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM 8996pro AUTO ADP";
+ compatible = "qcom,msm8996-adp", "qcom,msm8996", "qcom,adp";
+ qcom,msm-id = <315 0x10001>;
+ qcom,board-id = <0x06010019 0>, <0x00010001 0>;
+};
+
+&spi_9 {
+ status = "ok";
+ can-controller@0 {
+ compatible = "renesas,rh850";
+ reg = <0>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <122 0>;
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&soc {
+ qcom,msm-ssc-sensors {
+ status = "disabled";
+ };
+
+ qcom,msm-thermal {
+ qcom,hotplug-temp = <115>;
+ qcom,hotplug-temp-hysteresis = <25>;
+ qcom,therm-reset-temp = <119>;
+ };
+
+ qcom,adv7481@70 {
+ status = "disabled";
+ };
+
+ qcom,ntn_avb {
+ qcom,ntn-rc-num = <2>;
+ };
+
+ i2c@75b6000 { /* BLSP8 */
+ /* ADV7533 HDMI Bridge Chip removed on ADP Lite */
+ adv7533@39 {
+ status = "disabled";
+ };
+
+ adv7533@3d {
+ status = "disabled";
+ };
+ };
+
+};
+
+&cci {
+ qcom,camera@0 {
+ pinctrl-names = "cam_default", "cam_suspend","default";
+ pinctrl-2 = <&mx9296_pwr>;
+ qcom,cci-master = <0>;
+ };
+};
+
+&tlmm {
+ pcie2 {
+ pcie2_perst_default: pcie2_perst_default {
+ mux {
+ pins = "gpio90";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio90";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie2_wake_default: pcie2_wake_default {
+ mux {
+ pins = "gpio54";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ mx9296_pwr: mx9296_pwr {
+ mux {
+ pins = "gpio21";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio21";
+ drive-strength = <2>;
+ bias-pull-up;
+ output-high;
+ };
+ };
+};
+
+&pil_modem {
+ pinctrl-names = "default";
+ pinctrl-0 = <&modem_mux>;
+};
+
+&slim_msm {
+ status = "disabled";
+};
+
+&pm8994_mpps {
+ mpp@a500 { /* MPP 6 */
+ qcom,mode = <1>; /* Digital output */
+ qcom,output-type = <0>; /* CMOS logic */
+ qcom,vin-sel = <2>; /* S4 1.8V */
+ qcom,src-sel = <0>; /* Constant */
+ qcom,master-en = <1>; /* Enable GPIO */
+ status = "okay";
+ };
+};
+
+&sdhc_2 {
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on_sbc>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off
+ &sdc2_cd_on_sbc>;
+};
+
+&i2c_7 {
+ silabs4705@11 { /* SiLabs FM chip, slave id 0x11*/
+ status = "disabled";
+ };
+};
+
+&pcie0 {
+ qcom,phy-sequence = <0x404 0x01 0x00
+ 0x034 0x1c 0x00
+ 0x038 0x10 0x00
+ 0x174 0x33 0x00
+ 0x194 0x06 0x00
+ 0x0c8 0x42 0x00
+ 0x128 0x00 0x00
+ 0x144 0xff 0x00
+ 0x148 0x1f 0x00
+ 0x178 0x01 0x00
+ 0x19c 0x01 0x00
+ 0x18c 0x00 0x00
+ 0x184 0x0a 0x00
+ 0x00c 0x09 0x00
+ 0x0d0 0x82 0x00
+ 0x0e4 0x03 0x00
+ 0x0e0 0x55 0x00
+ 0x0dc 0x55 0x00
+ 0x054 0x00 0x00
+ 0x050 0x1a 0x00
+ 0x04c 0x0a 0x00
+ 0x174 0x33 0x00
+ 0x03c 0x02 0x00
+ 0x040 0x1f 0x00
+ 0x0ac 0x04 0x00
+ 0x078 0x0b 0x00
+ 0x084 0x16 0x00
+ 0x090 0x28 0x00
+ 0x10c 0x00 0x00
+ 0x108 0x80 0x00
+ 0x010 0x00 0x00
+ 0x01c 0x31 0x00
+ 0x020 0x01 0x00
+ 0x014 0x02 0x00
+ 0x018 0x00 0x00
+ 0x024 0x2f 0x00
+ 0x028 0x19 0x00
+ 0x0c4 0x15 0x00
+ 0x070 0x0f 0x00
+ 0x048 0x0f 0x00
+ 0x074 0x19 0x00
+ 0x038 0x10 0x00
+ 0x178 0x00 0x00
+ 0x0c4 0x40 0x00
+ 0x400 0x00 0x00
+ 0x408 0x03 0x00>;
+
+ qcom,port-phy-sequence = <0x1068 0x45 0x00
+ 0x1094 0x06 0x00
+ 0x1310 0x1c 0x00
+ 0x1318 0x17 0x00
+ 0x12d8 0x01 0x00
+ 0x12dc 0x00 0x00
+ 0x12e0 0xdb 0x00
+ 0x1320 0x18 0x00
+ 0x121c 0x04 0x00
+ 0x1210 0x04 0x00
+ 0x1458 0x4c 0x00
+ 0x14a0 0x00 0x00
+ 0x14a4 0x01 0x00
+ 0x14a8 0x05 0x00
+ 0x1248 0x4b 0x00
+ 0x131c 0x14 0x00
+ 0x1454 0x05 0x00
+ 0x1404 0x02 0x00
+ 0x146c 0x00 0x00
+ 0x1460 0xa3 0x00
+ 0x1318 0x19 0x00
+ 0x1428 0x0e 0x00
+ 0x1054 0x08 0x00
+ 0x14f8 0x04 0x00
+ 0x14ec 0x06 0x00
+ 0x104c 0x2e 0x00
+ 0x1404 0x03 0x0a
+ 0x1400 0x00 0x00
+ 0x1408 0x0a 0x00>;
+
+ /delete-property/qcom,l1-supported;
+ /delete-property/qcom,l1ss-supported;
+ qcom,aux-clk-sync;
+ qcom,boot-option = <0x0>;
+};
+
+&pcie1 {
+ qcom,phy-sequence = <0x404 0x01 0x00
+ 0x034 0x1c 0x00
+ 0x038 0x10 0x00
+ 0x174 0x33 0x00
+ 0x194 0x06 0x00
+ 0x0c8 0x42 0x00
+ 0x128 0x00 0x00
+ 0x144 0xff 0x00
+ 0x148 0x1f 0x00
+ 0x178 0x01 0x00
+ 0x19c 0x01 0x00
+ 0x18c 0x00 0x00
+ 0x184 0x0a 0x00
+ 0x00c 0x09 0x00
+ 0x0d0 0x82 0x00
+ 0x0e4 0x03 0x00
+ 0x0e0 0x55 0x00
+ 0x0dc 0x55 0x00
+ 0x054 0x00 0x00
+ 0x050 0x1a 0x00
+ 0x04c 0x0a 0x00
+ 0x174 0x33 0x00
+ 0x03c 0x02 0x00
+ 0x040 0x1f 0x00
+ 0x0ac 0x04 0x00
+ 0x078 0x0b 0x00
+ 0x084 0x16 0x00
+ 0x090 0x28 0x00
+ 0x10c 0x00 0x00
+ 0x108 0x80 0x00
+ 0x010 0x00 0x00
+ 0x01c 0x31 0x00
+ 0x020 0x01 0x00
+ 0x014 0x02 0x00
+ 0x018 0x00 0x00
+ 0x024 0x2f 0x00
+ 0x028 0x19 0x00
+ 0x0c4 0x15 0x00
+ 0x070 0x0f 0x00
+ 0x048 0x0f 0x00
+ 0x074 0x19 0x00
+ 0x038 0x10 0x00
+ 0x178 0x00 0x00
+ 0x0c4 0x40 0x00
+ 0x400 0x00 0x00
+ 0x408 0x03 0x00>;
+
+ qcom,port-phy-sequence = <0x2068 0x45 0x00
+ 0x2094 0x06 0x00
+ 0x2310 0x1c 0x00
+ 0x2318 0x17 0x00
+ 0x22d8 0x01 0x00
+ 0x22dc 0x00 0x00
+ 0x22e0 0xdb 0x00
+ 0x2320 0x18 0x00
+ 0x221c 0x04 0x00
+ 0x2210 0x04 0x00
+ 0x2458 0x4c 0x00
+ 0x24a0 0x00 0x00
+ 0x24a4 0x01 0x00
+ 0x24a8 0x05 0x00
+ 0x2248 0x4b 0x00
+ 0x231c 0x14 0x00
+ 0x2454 0x05 0x00
+ 0x2404 0x02 0x00
+ 0x246c 0x00 0x00
+ 0x2460 0xa3 0x00
+ 0x2318 0x19 0x00
+ 0x2428 0x0e 0x00
+ 0x2054 0x08 0x00
+ 0x24f8 0x04 0x00
+ 0x24ec 0x06 0x00
+ 0x204c 0x2e 0x00
+ 0x2404 0x03 0x0a
+ 0x2400 0x00 0x00
+ 0x2408 0x0a 0x00>;
+
+ /delete-property/qcom,l1-supported;
+ /delete-property/qcom,l1ss-supported;
+ /delete-property/qcom,aux-clk-sync;
+ qcom,boot-option = <0x0>;
+};
+
+&pcie2 {
+ qcom,boot-option = <0x0>;
+ perst-gpio = <&tlmm 90 0>;
+ wake-gpio = <&tlmm 54 0>;
+};
diff --git a/arch/arm/boot/dts/qcom/sdm660-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-mtp.dts
index 32b294ee6883..68e4491193d5 100644
--- a/arch/arm/boot/dts/qcom/sdm660-mtp.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-mtp.dts
@@ -29,3 +29,12 @@
&tavil_snd {
qcom,msm-mbhc-moist-cfg = <0>, <0>, <3>;
};
+
+&slim_aud {
+ /delete-node/tasha_codec;
+};
+
+&soc {
+ /delete-node/sound-9335;
+};
+
diff --git a/arch/arm/boot/dts/qcom/sdm660-qrd.dts b/arch/arm/boot/dts/qcom/sdm660-qrd.dts
index 3284e805a093..4e7cc547e6cd 100644
--- a/arch/arm/boot/dts/qcom/sdm660-qrd.dts
+++ b/arch/arm/boot/dts/qcom/sdm660-qrd.dts
@@ -86,3 +86,12 @@
qcom,afe-power-off-delay-us = <6>;
};
};
+
+&slim_aud {
+ /delete-node/wcd934x_cdc;
+};
+
+&soc {
+ /delete-node/sound-tavil;
+};
+
diff --git a/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c b/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c
index 0f77e35ef287..35ba396e1cd1 100644
--- a/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi-staging/sde_hdmi.c
@@ -2799,7 +2799,6 @@ static int _sde_hdmi_parse_dt_modes(struct device_node *np,
u32 v_front_porch, v_pulse_width, v_back_porch;
bool h_active_high, v_active_high;
u32 flags = 0;
-
root_node = of_get_child_by_name(np, "qcom,customize-modes");
if (!root_node) {
root_node = of_parse_phandle(np, "qcom,customize-modes", 0);
@@ -2887,10 +2886,10 @@ static int _sde_hdmi_parse_dt_modes(struct device_node *np,
v_active_high = of_property_read_bool(node,
"qcom,mode-v-active-high");
- rc = of_property_read_u32(node, "qcom,mode-refersh-rate",
+ rc = of_property_read_u32(node, "qcom,mode-refresh-rate",
&mode->vrefresh);
if (rc) {
- SDE_ERROR("failed to read refersh-rate, rc=%d\n", rc);
+ SDE_ERROR("failed to read refresh-rate, rc=%d\n", rc);
goto fail;
}
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index 9cbee5243e6d..f5f125c3f71c 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -1808,8 +1808,8 @@ static void _sde_plane_install_properties(struct drm_plane *plane,
char feature_name[256];
struct sde_phy_plane *pp;
uint32_t features = 0xFFFFFFFF, nformats = 64;
- u32 maxlinewidth = -1, maxupscale = -1, maxdwnscale = -1;
- u32 maxhdeciexp = -1, maxvdeciexp = -1;
+ u32 maxlinewidth = 0, maxupscale = 0, maxdwnscale = 0;
+ u32 maxhdeciexp = 0, maxvdeciexp = 0;
if (!plane || !psde) {
SDE_ERROR("invalid plane\n");
diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
index 8d091320cbca..a8d7c1f8b489 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
+++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
@@ -437,6 +437,11 @@ static int msm_csiphy_2phase_lane_config(
csiphybase = csiphy_dev->base;
lane_mask = csiphy_params->lane_mask & 0x1f;
+
+ lane_enable = msm_camera_io_r(csiphybase +
+ csiphy_dev->ctrl_reg->csiphy_3ph_reg.
+ mipi_csiphy_3ph_cmn_ctrl5.addr);
+
for (i = 0; i < MAX_DPHY_DATA_LN; i++) {
if (mask == 0x2) {
if (lane_mask & mask)
@@ -474,7 +479,11 @@ static int msm_csiphy_2phase_lane_config(
clk_lane = 0;
}
- if (csiphy_params->combo_mode == 1) {
+ /* In combo mode setting the 4th lane
+ * as clk_lane for 1 lane sensor, checking
+ * the lane_mask == 0x18 for one lane sensor
+ */
+ if ((csiphy_params->combo_mode == 1) && (lane_mask == 0x18)) {
val |= 0xA;
if (mask == csiphy_dev->ctrl_reg->
csiphy_reg.combo_clk_mask) {
@@ -520,6 +529,12 @@ static int msm_csiphy_2phase_lane_config(
mipi_csiphy_2ph_lnn_cfg4.data, csiphybase +
csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg4.addr + offset);
+ if (lane_mask == 0x18)
+ msm_camera_io_w(0x80,
+ csiphybase +
+ csiphy_dev->ctrl_reg->csiphy_3ph_reg.
+ mipi_csiphy_2ph_lnn_cfg1.addr + offset);
+
} else {
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg1.data,
@@ -540,8 +555,8 @@ static int msm_csiphy_2phase_lane_config(
csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg5.addr + offset);
}
- if (clk_lane == 1 &&
- csiphy_dev->hw_version == CSIPHY_VERSION_V342) {
+ if (clk_lane == 1 && lane_mask != 0x18 &&
+ (csiphy_dev->hw_version == CSIPHY_VERSION_V342)) {
msm_camera_io_w(0x1f,
csiphybase +
csiphy_dev->ctrl_reg->csiphy_3ph_reg.
diff --git a/drivers/net/wireless/ath/ath10k/htc.c b/drivers/net/wireless/ath/ath10k/htc.c
index c01f59955797..aa20ebbefe94 100644
--- a/drivers/net/wireless/ath/ath10k/htc.c
+++ b/drivers/net/wireless/ath/ath10k/htc.c
@@ -86,7 +86,8 @@ static void ath10k_htc_prepare_tx_skb(struct ath10k_htc_ep *ep,
hdr->eid = ep->eid;
hdr->len = __cpu_to_le16(skb->len - sizeof(*hdr));
hdr->flags = 0;
- hdr->flags |= ATH10K_HTC_FLAG_NEED_CREDIT_UPDATE;
+ if (ep->tx_credit_flow_enabled)
+ hdr->flags |= ATH10K_HTC_FLAG_NEED_CREDIT_UPDATE;
spin_lock_bh(&ep->htc->tx_lock);
hdr->seq_no = ep->seq_no++;
diff --git a/drivers/power/supply/qcom/qpnp-fg-gen3.c b/drivers/power/supply/qcom/qpnp-fg-gen3.c
index 491dda6ff7e8..b1a57d8853e8 100644
--- a/drivers/power/supply/qcom/qpnp-fg-gen3.c
+++ b/drivers/power/supply/qcom/qpnp-fg-gen3.c
@@ -2733,6 +2733,49 @@ static bool is_profile_load_required(struct fg_chip *chip)
return true;
}
+static void fg_update_batt_profile(struct fg_chip *chip)
+{
+ int rc, offset;
+ u8 val;
+
+ rc = fg_sram_read(chip, PROFILE_INTEGRITY_WORD,
+ SW_CONFIG_OFFSET, &val, 1, FG_IMA_DEFAULT);
+ if (rc < 0) {
+ pr_err("Error in reading SW_CONFIG_OFFSET, rc=%d\n", rc);
+ return;
+ }
+
+ /*
+ * If the RCONN had not been updated, no need to update battery
+ * profile. Else, update the battery profile so that the profile
+ * modified by bootloader or HLOS matches with the profile read
+ * from device tree.
+ */
+
+ if (!(val & RCONN_CONFIG_BIT))
+ return;
+
+ rc = fg_sram_read(chip, ESR_RSLOW_CHG_WORD,
+ ESR_RSLOW_CHG_OFFSET, &val, 1, FG_IMA_DEFAULT);
+ if (rc < 0) {
+ pr_err("Error in reading ESR_RSLOW_CHG_OFFSET, rc=%d\n", rc);
+ return;
+ }
+ offset = (ESR_RSLOW_CHG_WORD - PROFILE_LOAD_WORD) * 4
+ + ESR_RSLOW_CHG_OFFSET;
+ chip->batt_profile[offset] = val;
+
+ rc = fg_sram_read(chip, ESR_RSLOW_DISCHG_WORD,
+ ESR_RSLOW_DISCHG_OFFSET, &val, 1, FG_IMA_DEFAULT);
+ if (rc < 0) {
+ pr_err("Error in reading ESR_RSLOW_DISCHG_OFFSET, rc=%d\n", rc);
+ return;
+ }
+ offset = (ESR_RSLOW_DISCHG_WORD - PROFILE_LOAD_WORD) * 4
+ + ESR_RSLOW_DISCHG_OFFSET;
+ chip->batt_profile[offset] = val;
+}
+
static void clear_battery_profile(struct fg_chip *chip)
{
u8 val = 0;
@@ -2816,6 +2859,8 @@ static void profile_load_work(struct work_struct *work)
if (!chip->profile_available)
goto out;
+ fg_update_batt_profile(chip);
+
if (!is_profile_load_required(chip))
goto done;
@@ -2877,6 +2922,10 @@ done:
rc);
}
+ rc = fg_rconn_config(chip);
+ if (rc < 0)
+ pr_err("Error in configuring Rconn, rc=%d\n", rc);
+
batt_psy_initialized(chip);
fg_notify_charger(chip);
chip->profile_loaded = true;
@@ -4076,12 +4125,6 @@ static int fg_hw_init(struct fg_chip *chip)
return rc;
}
- rc = fg_rconn_config(chip);
- if (rc < 0) {
- pr_err("Error in configuring Rconn, rc=%d\n", rc);
- return rc;
- }
-
fg_encode(chip->sp, FG_SRAM_ESR_TIGHT_FILTER,
chip->dt.esr_tight_flt_upct, buf);
rc = fg_sram_write(chip, chip->sp[FG_SRAM_ESR_TIGHT_FILTER].addr_word,
diff --git a/drivers/soc/qcom/service-locator.c b/drivers/soc/qcom/service-locator.c
index f19db5fe99b3..52355699e4f3 100644
--- a/drivers/soc/qcom/service-locator.c
+++ b/drivers/soc/qcom/service-locator.c
@@ -149,11 +149,10 @@ static void service_locator_recv_msg(struct work_struct *work)
do {
pr_debug("Notified about a Receive event\n");
- ret = qmi_recv_msg(service_locator.clnt_handle);
- if (ret < 0)
- pr_err("Error receiving message rc:%d. Retrying...\n",
- ret);
- } while (ret == 0);
+ } while ((ret = qmi_recv_msg(service_locator.clnt_handle)) == 0);
+
+ if (ret != -ENOMSG)
+ pr_err("Error receiving message rc:%d\n", ret);
}
@@ -190,7 +189,7 @@ static int servreg_loc_send_msg(struct msg_desc *req_desc,
*/
rc = qmi_send_req_wait(service_locator.clnt_handle, req_desc, req,
sizeof(*req), resp_desc, resp, sizeof(*resp),
- msecs_to_jiffies(QMI_SERVREG_LOC_SERVER_TIMEOUT));
+ QMI_SERVREG_LOC_SERVER_TIMEOUT);
if (rc < 0) {
pr_err("QMI send req failed for client %s, ret - %d\n",
pd->client_name, rc);
diff --git a/security/pfe/pfk_ice.c b/security/pfe/pfk_ice.c
index facecedc3827..2bf18b74bfd5 100644
--- a/security/pfe/pfk_ice.c
+++ b/security/pfe/pfk_ice.c
@@ -68,25 +68,34 @@ int qti_pfk_ice_set_key(uint32_t index, uint8_t *key, uint8_t *salt,
char *storage_type)
{
struct scm_desc desc = {0};
- int ret;
+ int ret, ret1;
char *tzbuf_key = (char *)ice_key;
char *tzbuf_salt = (char *)ice_salt;
+ char *s_type = storage_type;
uint32_t smc_id = 0;
u32 tzbuflen_key = sizeof(ice_key);
u32 tzbuflen_salt = sizeof(ice_salt);
- if (index < MIN_ICE_KEY_INDEX || index > MAX_ICE_KEY_INDEX)
+ if (index < MIN_ICE_KEY_INDEX || index > MAX_ICE_KEY_INDEX) {
+ pr_err("%s Invalid index %d\n", __func__, index);
return -EINVAL;
+ }
- if (!key || !salt)
+ if (!key || !salt) {
+ pr_err("%s Invalid key/salt\n", __func__);
return -EINVAL;
+ }
- if (!tzbuf_key || !tzbuf_salt)
+ if (!tzbuf_key || !tzbuf_salt) {
+ pr_err("%s No Memory\n", __func__);
return -ENOMEM;
+ }
- if (storage_type == NULL)
+ if (s_type == NULL) {
+ pr_err("%s Invalid storage\n", __func__);
return -EINVAL;
+ }
memset(tzbuf_key, 0, tzbuflen_key);
memset(tzbuf_salt, 0, tzbuflen_salt);
@@ -98,7 +107,6 @@ int qti_pfk_ice_set_key(uint32_t index, uint8_t *key, uint8_t *salt,
dmac_flush_range(tzbuf_salt, tzbuf_salt + tzbuflen_salt);
smc_id = TZ_ES_SET_ICE_KEY_ID;
- pr_debug(" %s , smc_id = 0x%x\n", __func__, smc_id);
desc.arginfo = TZ_ES_SET_ICE_KEY_PARAM_ID;
desc.args[0] = index;
@@ -107,27 +115,36 @@ int qti_pfk_ice_set_key(uint32_t index, uint8_t *key, uint8_t *salt,
desc.args[3] = virt_to_phys(tzbuf_salt);
desc.args[4] = tzbuflen_salt;
- ret = qcom_ice_setup_ice_hw((const char *)storage_type, true);
+ ret = qcom_ice_setup_ice_hw((const char *)s_type, true);
if (ret) {
- pr_err("%s: could not enable clocks: 0x%x\n", __func__, ret);
- return ret;
+ pr_err("%s: could not enable clocks: %d\n", __func__, ret);
+ goto out;
}
ret = scm_call2(smc_id, &desc);
- ret = qcom_ice_setup_ice_hw((const char *)storage_type, false);
-
pr_debug(" %s , ret = %d\n", __func__, ret);
- if (ret) {
- pr_err("%s: Error: 0x%x\n", __func__, ret);
+ if (ret) {
+ pr_err("%s: Set key Error: %d\n", __func__, ret);
+ if (ret == -EBUSY) {
+ if (qcom_ice_setup_ice_hw((const char *)s_type, false))
+ pr_err("%s: disable clock failed\n", __func__);
+ goto out;
+ }
+ /*Try to invalidate the key to keep ICE in proper state*/
smc_id = TZ_ES_INVALIDATE_ICE_KEY_ID;
desc.arginfo = TZ_ES_INVALIDATE_ICE_KEY_PARAM_ID;
desc.args[0] = index;
- scm_call2(smc_id, &desc);
+ ret1 = scm_call2(smc_id, &desc);
+ if (ret1)
+ pr_err("%s:Invalidate key Error: %d\n", __func__,
+ ret1);
}
+ ret = qcom_ice_setup_ice_hw((const char *)s_type, false);
+out:
return ret;
}
@@ -139,14 +156,17 @@ int qti_pfk_ice_invalidate_key(uint32_t index, char *storage_type)
uint32_t smc_id = 0;
- if (index < MIN_ICE_KEY_INDEX || index > MAX_ICE_KEY_INDEX)
+ if (index < MIN_ICE_KEY_INDEX || index > MAX_ICE_KEY_INDEX) {
+ pr_err("%s Invalid index %d\n", __func__, index);
return -EINVAL;
+ }
- if (storage_type == NULL)
+ if (storage_type == NULL) {
+ pr_err("%s Invalid storage\n", __func__);
return -EINVAL;
+ }
smc_id = TZ_ES_INVALIDATE_ICE_KEY_ID;
- pr_debug(" %s , smc_id = 0x%x\n", __func__, smc_id);
desc.arginfo = TZ_ES_INVALIDATE_ICE_KEY_PARAM_ID;
desc.args[0] = index;
@@ -160,12 +180,13 @@ int qti_pfk_ice_invalidate_key(uint32_t index, char *storage_type)
ret = scm_call2(smc_id, &desc);
- ret = qcom_ice_setup_ice_hw((const char *)storage_type, false);
-
- pr_debug(" %s , ret = %d\n", __func__, ret);
- if (ret)
+ if (ret) {
pr_err("%s: Error: 0x%x\n", __func__, ret);
+ if (qcom_ice_setup_ice_hw((const char *)storage_type, false))
+ pr_err("%s: could not disable clocks\n", __func__);
+ } else {
+ ret = qcom_ice_setup_ice_hw((const char *)storage_type, false);
+ }
return ret;
-
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-24 16:59:37 +0000