diff options
416 files changed, 15026 insertions, 8500 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt index 9a96f74a8603..4fadd0ccbcf7 100644 --- a/Documentation/devicetree/bindings/arm/msm/msm.txt +++ b/Documentation/devicetree/bindings/arm/msm/msm.txt @@ -89,14 +89,23 @@ SoCs: - MSMHAMSTER compatible = "qcom,msmhamster" -- MSMFALCON - compatible = "qcom,msmfalcon" +- SDM658 + compatible = "qcom,sdm658" -- APQFALCON - compatible = "qcom,apqfalcon" +- SDM660 + compatible = "qcom,sdm660" -- MSMTRITON - compatible = "qcom,msmtriton" +- SDA658 + compatible = "qcom,sda658" + +- SDA660 + compatible = "qcom,sda660" + +- SDM630 + compatible = "qcom,sdm630" + +- SDA630 + compatible = "qcom,sda630" - MSM8952 compatible = "qcom,msm8952" @@ -263,14 +272,23 @@ compatible = "qcom,msm8998-qrd" compatible = "qcom,msmhamster-rumi" compatible = "qcom,msmhamster-cdp" compatible = "qcom,msmhamster-mtp" -compatible = "qcom,msmfalcon-sim" -compatible = "qcom,msmfalcon-rumi" -compatible = "qcom,msmfalcon-cdp" -compatible = "qcom,msmfalcon-mtp" -compatible = "qcom,msmfalcon-qrd" -compatible = "qcom,apqfalcon-mtp" -compatible = "qcom,apqfalcon-cdp" -compatible = "qcom,msmtriton-rumi" +compatible = "qcom,sdm658-cdp" +compatible = "qcom,sdm658-mtp" +compatible = "qcom,sdm658-qrd" +compatible = "qcom,sdm660-sim" +compatible = "qcom,sdm660-rumi" +compatible = "qcom,sdm660-cdp" +compatible = "qcom,sdm660-mtp" +compatible = "qcom,sdm660-qrd" +compatible = "qcom,sda658-mtp" +compatible = "qcom,sda658-cdp" +compatible = "qcom,sda660-mtp" +compatible = "qcom,sda660-cdp" +compatible = "qcom,sdm630-rumi" +compatible = "qcom,sdm630-mtp" +compatible = "qcom,sdm630-cdp" +compatible = "qcom,sda630-mtp" +compatible = "qcom,sda630-cdp" compatible = "qcom,msm8952-rumi" compatible = "qcom,msm8952-sim" compatible = "qcom,msm8952-qrd" diff --git a/Documentation/devicetree/bindings/arm/msm/spss_utils.txt b/Documentation/devicetree/bindings/arm/msm/spss_utils.txt index 21b96377e5e4..61d3865b73d5 100644 --- a/Documentation/devicetree/bindings/arm/msm/spss_utils.txt +++ b/Documentation/devicetree/bindings/arm/msm/spss_utils.txt @@ -15,13 +15,15 @@ Required properties: -qcom,spss-fuse-bit: fuse relevant bit -qcom,spss-test-firmware-name: test firmware file name -qcom,spss-prod-firmware-name: production firmware file name +-qcom,spss-debug-reg-addr: debug register physical address Example: qcom,spss_utils { compatible = "qcom,spss-utils"; - qcom,spss-fuse-addr = <0x007841c4 0x4>; /* spss test fuse physical address */ + qcom,spss-fuse-addr = <0x007841c4>; /* spss test fuse physical address */ qcom,spss-fuse-bit = <27>; qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */ qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ + qcom,spss-debug-reg-addr = <0x01d06020>; }; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt b/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt index e1ccf69b751b..5c770864898a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-dbg.txt @@ -3,7 +3,7 @@ Qualcomm Technologies Inc Global Clock Debug Controller Binding Required properties : - compatible: shall contain the following: - "qcom,gcc-debug-msmfalcon" + "qcom,gcc-debug-sdm660" - reg: shall contain global clock controller base register offset location and length. @@ -24,7 +24,7 @@ In the case where "qcom,cc-count" is > 1, the below needs to be defined. Example: clock_gcc: clock-controller@100000 { - compatible = "qcom,gcc-msmfalcon", "syscon"; + compatible = "qcom,gcc-sdm660", "syscon"; .... }; @@ -44,7 +44,7 @@ Example: }; clock_debug: qcom,cc-debug@62000 { - compatible = "qcom,gcc-debug-msmfalcon"; + compatible = "qcom,gcc-debug-sdm660"; reg = <0x62000 0x4>; reg-names = "cc_offset"; clocks = <&clock_rpmcc RPM_XO_CLK_SRC>; diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 1330d2bdc18d..479a83df3808 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -14,7 +14,7 @@ Required properties : "qcom,gcc-msm8974pro" "qcom,gcc-msm8974pro-ac" "qcom,gcc-msm8996" - "qcom,gcc-msmfalcon" + "qcom,gcc-sdm660" - reg : shall contain base register location and length - #clock-cells : shall contain 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt index 4d8f87225230..12e0164a8bcc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -4,8 +4,8 @@ Qualcomm Technologies, Inc Graphics Clock & Reset Controller Binding Required properties : - compatible : shall contain only one of the following: - "qcom,gpucc-msmfalcon", - "qcom,gpucc-msmtriton" + "qcom,gpucc-sdm660", + "qcom,gpucc-sdm630" - reg : shall contain base register location and length - #clock-cells : shall contain 1 @@ -16,7 +16,7 @@ Optional properties : Example: clock-controller@4000000 { - compatible = "qcom,gpucc-msmfalcon"; + compatible = "qcom,gpucc-sdm660"; reg = <<0x5065000 0x10000>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt index 6aaf89c47781..4b1057288b2f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt @@ -10,7 +10,7 @@ Required properties : "qcom,mmcc-msm8960" "qcom,mmcc-msm8974" "qcom,mmcc-msm8996" - "qcom,mmcc-msmfalcon" + "qcom,mmcc-sdm660" - reg : shall contain base register location and length - #clock-cells : shall contain 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt index f825a44e5911..685fb3aa2e61 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt @@ -13,7 +13,7 @@ Required properties : "qcom,rpmcc-msm8916", "qcom,rpmcc" "qcom,rpmcc-apq8064", "qcom,rpmcc" "qcom,rpmcc-msm8996", "qcom,rpmcc" - "qcom,rpmcc-msmfalcon", "qcom,rpmcc" + "qcom,rpmcc-sdm660", "qcom,rpmcc" - #clock-cells : shall contain 1 @@ -38,7 +38,7 @@ Example: }; }; - The below are applicable for MSM8996 & MSMFalcon. + The below are applicable for MSM8996 & SDM660. rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; diff --git a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt index 0299b1aef2b6..52ffbe5c7207 100644 --- a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt +++ b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt @@ -37,8 +37,8 @@ Required properties: "display_2" = DISPLAY_2 - qcom,mdss-dsi-panel-timings: An array of length 12 that specifies the PHY timing settings for the panel. -- qcom,mdss-dsi-panel-timings-8996: An array of length 40 char that specifies the 8996 PHY lane - timing settings for the panel. +- qcom,mdss-dsi-panel-timings-phy-v2: An array of length 40 char that specifies the PHY version 2 + lane timing settings for the panel. - qcom,mdss-dsi-on-command: A byte stream formed by multiple dcs packets base on qcom dsi controller protocol. byte 0: dcs data type @@ -638,7 +638,7 @@ Example: qcom,mdss-mdp-transfer-time-us = <12500>; qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 22 27 1e 03 04 00]; - qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [23 20 06 09 05 03 04 a0 23 20 06 09 05 03 04 a0 23 20 06 09 05 03 04 a0 23 20 06 09 05 03 04 a0 diff --git a/Documentation/devicetree/bindings/fb/mdss-pll.txt b/Documentation/devicetree/bindings/fb/mdss-pll.txt index e9e4a9af381b..5d9a703c4823 100644 --- a/Documentation/devicetree/bindings/fb/mdss-pll.txt +++ b/Documentation/devicetree/bindings/fb/mdss-pll.txt @@ -15,7 +15,7 @@ Required properties: "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2", "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8", "qcom,mdss_dsi_pll_8998", "qcom,mdss_dp_pll_8998", - "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dsi_pll_msmfalcon" + "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dsi_pll_sdm660" - cell-index: Specifies the controller used - reg: offset and length of the register set for the device. - reg-names : names to refer to register sets related to this device diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt index 581f1128355c..da54fb11ffd4 100644 --- a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt +++ b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt @@ -98,7 +98,7 @@ Optional properties: used if qcom,thermal-derate-en is specified. Allowed values are: 0, 15, 30, 45 for pmi8998. - 0, 20, 40, 60 for pm2falcon. + 0, 20, 40, 60 for pm660l. - qcom,thermal-thrsh1 : Integer property to specify OTST1 threshold for thermal mitigation. Unit is in Celsius. Accepted values are: diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt index 74cee0d6ba0d..a77a291a99da 100644 --- a/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt +++ b/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt @@ -28,13 +28,13 @@ Optional properties for WLED: - qcom,vref-uv : maximum reference voltage in uV. For pmi8994/8952/8996, supported values are from 300000 to 675000 with a step size of 25000, the default value is 350000. - For pmi8998/pm2falcon, supported values are from 60000 to 397500 + For pmi8998/pm660l, supported values are from 60000 to 397500 with a step size of 22500, the default value is 127500. - qcom,switch-freq-khz : switch frequency in khz. default is 800. - qcom,ovp-mv : Over voltage protection threshold in mV. Default is 29500. Supported values are: - 31000, 29500, 19400, 17800 for pmi8994/8952/8996. - - 31100, 29600, 19600, 18100 for pmi8998/pm2falcon. + - 31100, 29600, 19600, 18100 for pmi8998/pm660l. Should only be used if qcom,disp-type-amoled is not specified. - qcom,ilim-ma : Current limit threshold in mA. @@ -42,7 +42,7 @@ Optional properties for WLED: and AMOLED is 385mA. Supported values are: - 105, 385, 660, 980, 1150, 1420, 1700, 1980. - For pmi8998/pm2falcon, default value for LCD is + For pmi8998/pm660l, default value for LCD is 970mA and AMOLED is 620mA. Supported values are: - 105, 280, 450, 620, 970, 1150, 1300, 1500. @@ -81,7 +81,7 @@ Optional properties if 'qcom,disp-type-amoled' is mentioned in DT: - qcom,vref-psm-mv : reference psm voltage in mv. default for amoled is 450. - qcom,avdd-mode-spmi: Boolean property to enable AMOLED_VOUT programming via SPMI. If not specified, AMOLED_VOUT is programmed via S-wire. This can be specified only for newer - PMICs like pmi8998/pm2falcon. + PMICs like pmi8998/pm660l. - qcom,avdd-target-voltage-mv: The voltage required for AMOLED_VOUT. Accepted values are in the range of 5650 to 7900 in steps of 150. Default value is 7600. Unit is in mV. For old revisions, accepted values are: 7900, 7600, 7300, 6400, 6100, diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msmfalcon-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt index 929ba3ee688b..dbd4baf0825a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msmfalcon-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-pinctrl.txt @@ -1,12 +1,12 @@ -Qualcomm Technologies, Inc. MSMFALCON TLMM block +Qualcomm Technologies, Inc. SDM660 TLMM block This binding describes the Top Level Mode Multiplexer block found in the -MSMFALCON platform. +SDM660 platform. - compatible: Usage: required Value type: <string> - Definition: must be "qcom,msmfalcon-pinctrl" + Definition: must be "qcom,sdm660-pinctrl" - reg: Usage: required @@ -176,7 +176,7 @@ to specify in a pin configuration subnode: Example: tlmm: pinctrl@01010000 { - compatible = "qcom,msmfalcon-pinctrl"; + compatible = "qcom,sdm660-pinctrl"; reg = <0x01010000 0x300000>; interrupts = <0 208 0>; gpio-controller; diff --git a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt index ac63b3c3bf01..35d8d0d7d50b 100644 --- a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt +++ b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt @@ -273,6 +273,45 @@ First Level Node - FG Gen3 device is specified, then ESR to Rslow scaling factors will be updated to account it for an accurate ESR. +- qcom,fg-esr-filter-switch-temp + Usage: optional + Value type: <u32> + Definition: Battery temperature threshold below which low temperature + ESR filter coefficients will be switched to normal + temperature ESR filter coefficients. If this is not + specified, then the default value used will be 100. Unit is + in decidegC. + +- qcom,fg-esr-tight-filter-micro-pct + Usage: optional + Value type: <u32> + Definition: Value in micro percentage for ESR tight filter. If this is + not specified, then a default value of 3907 (0.39 %) will + be used. Lowest possible value is 1954 (0.19 %). + +- qcom,fg-esr-broad-filter-micro-pct + Usage: optional + Value type: <u32> + Definition: Value in micro percentage for ESR broad filter. If this is + not specified, then a default value of 99610 (9.96 %) will + be used. Lowest possible value is 1954 (0.19 %). + +- qcom,fg-esr-tight-lt-filter-micro-pct + Usage: optional + Value type: <u32> + Definition: Value in micro percentage for low temperature ESR tight + filter. If this is not specified, then a default value of + 48829 (4.88 %) will be used. Lowest possible value is 1954 + (0.19 %). + +- qcom,fg-esr-broad-lt-filter-micro-pct + Usage: optional + Value type: <u32> + Definition: Value in micro percentage for low temperature ESR broad + filter. If this is not specified, then a default value of + 148438 (14.84 %) will be used. Lowest possible value is + 1954 (0.19 %). + ========================================================== Second Level Nodes - Peripherals managed by FG Gen3 driver ========================================================== diff --git a/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt b/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt index 41cec67b7627..851528517f4c 100644 --- a/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/cpr4-mmss-ldo-regulator.txt @@ -28,7 +28,7 @@ MMSS LDO specific properties: Usage: required Value type: <string> Definition: should be the following: - "qcom,cpr4-msmfalcon-mmss-ldo-regulator". + "qcom,cpr4-sdm660-mmss-ldo-regulator". - clocks Usage: required @@ -71,7 +71,7 @@ MMSS specific properties: Usage: required Value type: <u32> Definition: Specifies the number of fuse corners. This value must be 6 - for msmfalcon GFX LDO. These fuse corners are: MinSVS, + for sdm660 GFX LDO. These fuse corners are: MinSVS, LowSVS, SVS, SVSP, NOM and NOMP. The open-loop voltage fuses are allocated for LowSVS, SVS, NOM and NOMP corners. The open-loop voltages for MinSVS and SVSP are derived by @@ -217,7 +217,7 @@ Example ======= gfx_cpr: cpr4-ctrl@05061000 { - compatible = "qcom,cpr4-msmfalcon-mmss-ldo-regulator"; + compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator"; reg = <0x05061000 0x4000>, <0x00784000 0x1000>; reg-names = "cpr_ctrl", "fuse_base"; interrupts = <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>; @@ -233,7 +233,7 @@ gfx_cpr: cpr4-ctrl@05061000 { vdd-supply = <&gfx_stub_vreg>; mem-acc-supply = <&gfx_mem_acc_vreg>; - system-supply = <&pm2falcon_s3_level>; /* vdd_cx */ + system-supply = <&pm660l_s3_level>; /* vdd_cx */ qcom,voltage-step = <5000>; vdd-thread0-ldo-supply = <&gfx_ldo_vreg>; diff --git a/Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt b/Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt index 5b0770785dbe..ff800352cc05 100644 --- a/Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt @@ -33,7 +33,8 @@ KBSS specific properties: Definition: should be one of the following: "qcom,cprh-msm8998-v1-kbss-regulator", "qcom,cprh-msm8998-v2-kbss-regulator", - "qcom,cprh-msm8998-kbss-regulator". + "qcom,cprh-msm8998-kbss-regulator", + "qcom,cprh-sdm660-kbss-regulator". If the SoC revision is not specified, then it is assumed to be the most recent revision of MSM8998, i.e. v2. diff --git a/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt b/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt index 42c735e26d66..dcbb120eea2a 100644 --- a/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt +++ b/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt @@ -9,7 +9,7 @@ This document describes the bindings that apply for the GFX LDO regulator. Usage: required Value type: <string> Definition: should be "qcom,msm8953-gfx-ldo" for MSM8953 and - "qcom,msmfalcon-gfx-ldo" for MSMFALCON + "qcom,sdm660-gfx-ldo" for SDM660 - reg Usage: required diff --git a/Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt b/Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt index c039caca22c8..3e22f178aa82 100644 --- a/Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt @@ -26,7 +26,7 @@ Main node optional properties: in LAB and IBB modules. Make sure the hardware has needed support before enabling this property. -- qcom,swire-control: A bool property which indicates if the LAB/IBB is +- qcom,swire-control: A boolean property which indicates if the LAB/IBB is controlled by the SWIRE interface. Enable only if qcom,qpnp-labibb-mode = "amoled". - qcom,labibb-ttw-force-lab-on: A boolean property which forces LAB to be @@ -53,6 +53,15 @@ Main node optional properties: needed when LAB and IBB are operating in standalone mode to vote for MBG. +Following properties are available only for PM660A: + +- qcom,pbs-control: A boolean property which indicates if + the LAB/IBB is controlled by the PBS + sequencer. If this mode is enabled the + PBS sequencer does the SWIRE remapping + and program the voltages based on the + SWIRE count. + LAB subnode required properties: - reg: Specifies the SPMI address and size for this peripheral. @@ -72,29 +81,9 @@ LAB subnode required properties: is configured in amoled mode. - qcom,qpnp-lab-init-lcd-voltage: The default output voltage when LAB regulator is configured in lcd mode. -- qcom,qpnp-lab-soft-start: The soft start time in us of LAB regulator. - Supported value are 200, 400, 600 and 800. - - qcom,qpnp-lab-ps-threshold: The threshold in mA of Pulse Skip Mode for LAB regulator. Supported values are 20, 30, 40 and 50. -- qcom,qpnp-lab-pfet-size: PFET size in percentage. Supported values - are 25, 50, 75 and 100. -- qcom,qpnp-lab-nfet-size: NFET size in percentage. Supported values - are 25, 50, 75 and 100. -- qcom,qpnp-lab-max-precharge-time: Precharge time in uS for LAB regulator. - Supported values are 200, 300, 400 and 500. - Suggested values for LCD and AMOLED mode - are 500 and 300uS respectively. -- qcom,qpnp-lab-switching-clock-frequency: The PWM switching clock frequency in - kHz of Lab regulator, Supported values - are: 3200, 2740, 2400, 2130, 1920, - 1750, 1600, 1480, 1370, 1280, 1200, - 1130, 1070, 1010, 960, 910. -- qcom,qpnp-lab-limit-maximum-current: The maximum inductor current limit in - mA of LAB regulator. Supported values - are 200, 400, 600, 800, 1000, 1200, - 1400 and 1600. - interrupts: Specify the interrupts as per the interrupt encoding. Currently "lab-vreg-ok" is required for @@ -125,9 +114,9 @@ LAB subnode optional properties: - qcom,qpnp-lab-pull-down-enable: A boolean property which upon set will enable the pull down for LAB regulator. Otherwise, it is disabled. -- qcom,qpnp-lab-max-precharge-enable: A boolean property which upon set will - enable fast precharge. Otherwise, it is - disabled. +- qcom,qpnp-lab-max-precharge-enable: A boolean property which upon set will + enable fast precharge. Otherwise, it is + disabled. - qcom,qpnp-lab-ring-suppression-enable: A boolean property which upon set will enable ring suppression for LAB regulator. Otherwise, it is disabled. @@ -135,14 +124,65 @@ LAB subnode optional properties: enforce maximum inductor current constraint for LAB regulator. Otherwise, there is no maximum current constraint. -- qcom,qpnp-lab-use-default-voltage: A boolean property which upon set will - use the value specified in - qcom,qpnp-lab-init-voltage property. - This will be used only if the bootloader - doesn't configure the output voltage - already. If it it not specified, then - output voltage can be configured to - any value in the allowed limit. +- qcom,qpnp-lab-switching-clock-frequency: The PWM switching clock frequency in + kHz of Lab regulator, Supported values + are: 3200, 2740, 2400, 2130, 1920, + 1750, 1600, 1480, 1370, 1280, 1200, + 1130, 1070, 1010, 960, 910. +- qcom,qpnp-lab-limit-maximum-current: The maximum inductor current limit in + mA of LAB regulator. Supported values + are 200, 400, 600, 800, 1000, 1200, + 1400 and 1600. +- qcom,qpnp-lab-pfet-size: PFET size in percentage. Supported values + are 25, 50, 75 and 100. +- qcom,qpnp-lab-nfet-size: NFET size in percentage. Supported values + are 25, 50, 75 and 100. +- qcom,qpnp-lab-max-precharge-time: Precharge time in uS for LAB regulator. + Supported values are 200, 300, 400 and 500. + Suggested values for LCD and AMOLED mode + are 500 and 300uS respectively. +- qcom,qpnp-lab-use-default-voltage: A boolean property which upon set will + use the value specified in + qcom,qpnp-lab-init-voltage property. + This will be used only if the bootloader + doesn't configure the output voltage + already. If it it not specified, then + output voltage can be configured to + any value in the allowed limit. + +Following properties are available only for PM660A: + +- qcom,qpnp-lab-soft-start: The soft start time in us of LAB regulator. + Supported value are 200, 400, 600 and 800. +- qcom,qpnp-lab-ldo-pulldown-enable: This property is used to enable/disable + the LDO pull down. + 1 - enable pulldown + 0 - disable pulldown +- qcom,qpnp-lab-enable-sw-high-psrr: A boolean property to enable the + software high psrr + (Power Suppy Rejection Rate) mode. +- qcom,qpnp-lab-high-psrr-src-select: This property is used to select the LAB + HW high psrr source. + The supported values are: + 0 = Either vph_high or high_psrr enable + 1 = vph_high only + 2 = high_psrr enable only + 3 = Either vph_high or high_psrr enable + This property is not valid if the + qcom,qpnp-lab-enable-sw-high-psrr property + is specified. +- qcom,qpnp-lab-vref-high-psrr-select: This property is required if the + qcom,qpnp-lab-high-psrr-src-select is + specified. The supported values (in mV) + are 350, 400, 450 and 500. Once the + rejection rate crosses the selected + high-psrr voltage the LDO is enabled + based on the value specified under + qcom,qpnp-lab-high-psrr-src-select + property. + This property is not valid if the + qcom,qpnp-lab-enable-sw-high-psrr property + is specified. IBB subnode required properties: @@ -154,8 +194,6 @@ IBB subnode required properties: - qcom,qpnp-ibb-min-voltage: The minimum voltage in microvolts IBB regulator can support. - qcom,qpnp-ibb-step-size: The step size in microvolts of IBB regulator. -- qcom,qpnp-ibb-slew-rate: The time in us taken by the regulator to change - voltage value in one step. - qcom,qpnp-ibb-soft-start: The soft start time in us of IBB regulator. - qcom,qpnp-ibb-init-voltage: The default initial voltage when the bootloader does @@ -168,13 +206,41 @@ IBB subnode required properties: - qcom,qpnp-ibb-discharge-resistor: The discharge resistor in Kilo Ohms which controls the soft start time. Supported values are 300, 64, 32 and 16. +IBB subnode optional properties: + +- qcom,qpnp-ibb-slew-rate: The time (in us) taken by the regulator to change + voltage value in one step. This property is not + applicable to PM660A. + The following properties can be used as an + alternate. + qcom,qpnp-ibb-slew-rate-config + qcom,qpnp-ibb-fast-slew-rate + qcom,qpnp-ibb-slow-slew-rate +- qcom,qpnp-ibb-ps-enable: A boolean property which upon set will enable + pulse skip mode for IBB regulator. Otherwise, + it is disabled. +- qcom,qpnp-ibb-num-swire-trans: The number of SWIRE transactions + after which the pulse skipping is + enabled. This property is required when + qpnp-ibb-smart-ps-enable property is + set. +- qcom,qpnp-ibb-neg-curr-limit: This property must be set when the + qpnp-ibb-smart-ps-enable is specified. + The supported values in mA are 1, 2, 3, + 4, 5, 6 and 7. The recommended value is +- qcom,qpnp-ibb-full-pull-down: A boolean property which upon set will + enable the pull down strength of IBB + regulator to full. Otherwise, the pull + down strength is configured to half. +- qcom,qpnp-ibb-pull-down-enable: A boolean property which upon set will enable + the pull down for IBB regulator. Otherwise, + it is disabled. - qcom,qpnp-ibb-lab-pwrup-delay: Power up delay (in us) for IBB regulator when it is enabled or turned on. Supported values are 1000, 2000, 4000 and 8000. - qcom,qpnp-ibb-lab-pwrdn-delay: Power down delay (in us) for IBB regulator when it is disabled or turned off. Supported values are 1000, 2000, 4000 and 8000. - - qcom,qpnp-ibb-switching-clock-frequency: The PWM switching clock frequency in kHz of IBB regulator. Supported values are: 3200, 2740, 2400, 2130, 1920, @@ -182,26 +248,13 @@ IBB subnode required properties: 1130, 1070, 1010, 960, 910. - qcom,qpnp-ibb-limit-maximum-current: The maximum inductor current limit in mA of IBB regulator. Supported values - are: 0, 50, 100, 150, 200, 250, 300, + are: 0, 50, 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700, 750, 800, 850, 900, 950, 1000, 1050, - 1100, 1150, 1200, 1250, 1300, 1350, + 1100, 1150, 1200, 1250, 1300, 1350, 1400, 1450, 1500 and 1550. - qcom,qpnp-ibb-debounce-cycle: The debounce cycle of IBB regulator. Supported values are 8, 16, 32 and 64. - -IBB subnode optional properties: - -- qcom,qpnp-ibb-ps-enable: A boolean property which upon set will enable - pulse skip mode for IBB regulator. Otherwise, - it is disabled. -- qcom,qpnp-ibb-full-pull-down: A boolean property which upon set will enable - the pull down strength of IBB regulator to - full. Otherwise, the pull down strength is - configured to half. -- qcom,qpnp-ibb-pull-down-enable: A boolean property which upon set will enable - the pull down for IBB regulator. Otherwise, - it is disabled. - qcom,qpnp-ibb-en-discharge: A boolean property which upon set will enable discharge for IBB regulator. Otherwise, it is kept disabled. @@ -220,12 +273,58 @@ IBB subnode optional properties: already. If it it not specified, then output voltage can be configured to any value in the allowed limit. -- qcom,output-voltage-one-pulse The expected voltage (in mV) of VDISN signal +- qcom,output-voltage-one-pulse: The expected voltage (in mV) of VDISN signal on the first SWIRE pulse. This property can be specified only if 'qcom,swire-control' is defined. The minimum and maximum values are 1400mV and 7700mV. +Following properties are available only for PM660A: + +- qcom,qpnp-ibb-smart-ps-enable: A boolean property which upon set + enables smart pulse skip mode for IBB + regulator. Otherwise, it is disabled. + This property is only applicable to + PM660A. +- qcom,qpnp-ibb-enable-pfm-mode: A boolean property which enables the IBB to work + in pfm mode. +- qcom,qpnp-ibb-pfm-peak-curr: The PFM peak current limit settings in mA. + Supported values are 150, 200, 250, 300, + 350, 400, 450 and 500. This property is + required if the qcom,qpnp-ibb-enable-pfm-mode + is true. +- qcom,qpnp-ibb-pfm-hysteresis: The PFM hysteresis voltage threshold in mV. + Supported values are 0, 25 and 50. + This property is required if the + qcom,qpnp-ibb-enable-pfm-mode is specified. +- qcom,qpnp-ibb-overload-blank: A boolean property which upon set enables + the IBB overload blanking. +- qcom,qpnp-ibb-overload-debounce: The expected overload debounce time (in ms) + values are 1, 2, 4 and 8. + This property is required only when the + qcom,qpnp-ibb-overload-blank is set. +- qcom,qpnp-ibb-vreg-ok-debounce: The expected vreg-ok-debounce time (us) + values are 4, 8, 16 and 32. + This property is required only when the + qcom,qpnp-ibb-overload-blank is set. +- qcom,qpnp-ibb-slew-rate-config: A boolean property to configure the + ibb fast/slow slew rate. + Either qcom,qpnp-ibb-fast-slew-rate or + qcom,qpnp-ibb-slow-slew-rate has to be + specified. Otherwise the + qcom,qpnp-ibb-slow-slew-rate takes precedence + over the qcom,qpnp-ibb-fast-slew-rate. +- qcom,qpnp-ibb-fast-slew-rate: This property is required if the qcom, + qpnp-ibb-slew-rate-config property is + specified. Supported values (in us) are + 100, 200, 500, 1000, 2000, 10000, 12000 + and 15000. +- qcom,qpnp-ibb-slow-slew-rate: This property is required if the qcom, + qpnp-ibb-slew-rate-config property is + specified. Supported values (in us) are + 100, 200, 500, 1000, 2000, 10000, 12000 + and 15000. + Example: qcom,pmi8994@3 { qpnp-labibb-regulator { diff --git a/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt b/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt index 68d23d0f5523..8b3a38da0834 100644 --- a/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qpnp-lcdb-regulator.txt @@ -209,7 +209,7 @@ Properties below are specific to BOOST subnode only. Example ======= -pm2falcon_lcdb: qpnp-lcdb@ec00 { +pm660l_lcdb: qpnp-lcdb@ec00 { compatible = "qcom,qpnp-lcdb-regulator"; #address-cells = <1>; #size-cells = <1>; diff --git a/Documentation/devicetree/bindings/regulator/qpnp-oledb-regulator.txt b/Documentation/devicetree/bindings/regulator/qpnp-oledb-regulator.txt new file mode 100644 index 000000000000..5d80a04c0b88 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/qpnp-oledb-regulator.txt @@ -0,0 +1,230 @@ +QPNP OLEDB (AMOLED AVDD Bias) Regulator + +QPNP OLEDB module provides AVDD voltage bias to the AMOLED display panel. +The supported voltage range is 5V to 8.1V. + +This document describes the bindings for QPNP OLEDB module. + +======================= +Required Node Structure +======================= + +- compatible + Usage: required + Value type: <string> + Definition: should be "qcom,qpnp-oledb-regulator". + +- reg + Usage: required + Value type: <prop-encoded-array> + Definition: Base address of the OLEDB SPMI peripheral. + +- label + Usage: required + Value type: <string> + Definition: A string used to describe the bias type(oledb). + +- regulator-name + Usage: required + Value type: <string> + Definition: A string used to describe the regulator. + +- regulator-min-microvolt + Usage: required + Value type: <u32> + Definition: Minimum voltage (in uV) supported by the bias (5000000uV). + +- regulator-max-microvolt + Usage: required + Value type: <u32> + Definition: Maximum voltage (in uV) supported by the bias (8100000uV). + +- qcom,swire-control + Usage: optional + Value type: <bool> + Definition: Enables the voltage programming through SWIRE signal. + + qcom,ext-pin-control + Usage: optional + Value type: <bool> + Definition: Configures the OLED module to be enabled by a external pin. + + qcom,dynamic-ext-pinctl-config + Usage: optional + Value type: <bool> + Definition: Used to dynamically enable/disable the OLEDB module + using external pin to avoid the glitches on the voltage + rail. This property is applicable only if qcom,ext-pin-ctl + property is specified and it is specific to PM660A. + + qcom,pbs-control + Usage: optional + Value type: <bool> + Definition: PMIC PBS logic directly configures the output voltage update + and pull down control. + + qcom,oledb-init-voltage-mv + Usage: optional + Value type: <u32> + Definition: Sets the AVDD bias voltage (in mV) when the module is + already enabled. Applicable only if the qcom,swire-control + property is not specified. Supported values are from 5.0V + to 8.1V with a step of 100mV. + +qcom,oledb-default-voltage-mv + Usage: optional + Value type: <u32> + Definition: Sets the default AVDD bias voltage (in mV) before module + enable. Supported values are from 5.0V to 8.1V with the + step of 100mV. + +qcom,bias-gen-warmup-delay-ns + Usage: optional + Value type: <u32> + Definition: Bias generator warm-up time (ns). Supported values are + 6700, 13300, 267000, 534000. + +qcom,peak-curr-limit-ma + Usage: optional + Value type: <u32> + Definition: Peak current limit (in mA). Supported values are 115, 265, + 415, 570, 720, 870, 1020, 1170. + +qcom,pull-down-enable + Usage: optional + Value type: <u32> + Definition: Pull down configuration of OLEDB. + 1 - Enable pull-down + 0 - Disable pull-down + +qcom,negative-curr-limit-enable + Usage: optional + Value type: <u32> + Definition: negative current limit enable/disable. + 1 = enable negative current limit + 0 = disable negative current limit + +qcom,negative-curr-limit-ma + Usage: optional + Value type: <u32> + Definition: Negative current limit (in mA). Supported values are + 170, 300, 420, 550. + +qcom,enable-short-circuit + Usage: optional + Value type: <u32> + Definition: Short circuit protection enable/disable. + 1 = enable short circuit protection + 0 = disable short circuit protection + +qcom,short-circuit-dbnc-time + usage: optional + Value type: <u32> + Definitioan: Short circuit debounce time (in Fsw). Supported + values are 2, 4, 8, 16. + +Fast precharge properties: +------------------------- + +qcom,fast-precharge-ppulse-enable + usage: optional + Value type: <u32> + Definitioan: Fast precharge pfet pulsing enable/disable. + 1 = enable fast precharge pfet pulsing + 0 = disable fast precharge pfet pulsing + +qcom,precharge-debounce-time-ms + usage: optional + Value type: <u32> + Definitioan: Fast precharge debounce time (in ms). Supported + values are 1, 2, 4, 8. + +qcom,precharge-pulse-period-us + usage: optional + Value type: <u32> + Definitioan: Fast precharge pulse period (in us). Supported + values are 3, 6, 9, 12. + +qcom,precharge-pulse-on-time-us + usage: optional + Value type: <u32> + Definitioan: Fast precharge pulse on time (in ns). Supported + values are 1200, 1800, 2400, 3000. + +Pulse Skip Modulation (PSM) properties: +-------------------------------------- + +qcom,psm-enable + Usage: optional + Value type: <u32> + Definition: Pulse Skip Modulation mode. + 1 - Enable PSM mode + 0 - Disable PSM mode + +qcom,psm-hys-mv + Usage: optional + Value type: <u32> + Definition: PSM hysterysis voltage (in mV). + Supported values are 13mV and 26mV. + +qcom,psm-vref-mv + Usage: optional + Value type: <u32> + Definition: Reference voltage(in mV) control for PSM comparator. + Supported values are 440, 510, 580, 650, 715, 780, 850, + and 920. + +Pulse Frequency Modulation (PFM) properties: +------------------------------------------- + +qcom,pfm-enable + Usage: optional + Value type: <u32> + Definition: Pulse Frequency Modulation mode. + 1 - Enable PFM mode + 0 - Disable PFM mode + +qcom,pfm-hys-mv + Usage: optional + Value type: <u32> + Definition: PFM hysterysis voltage (in mV). + Supported values are 13mV and 26mV. + +qcom,pfm-curr-limit-ma + Usage: optional + Value type: <u32> + Definition: PFM current limit (in mA). + Supported values are 130, 200, 270, 340. + +qcom,pfm-off-time-ns + Usage: optional + Value type: <u32> + Definition: NFET off time at PFM (in ns). + Supported values are 110, 240, 350, 480. + +======= +Example +======= + +pm660a_oledb: qpnp-oledb@e000 { + compatible = "qcom,qpnp-oledb-regulator"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xe000 0x100>; + + label = "oledb"; + regulator-name = "regulator-oledb"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <8100000>; + + qcom,swire-control; + qcom,ext-pin-control; + + qcom,oledb-default-voltage-mv = <5000>; + qcom,bias-gen-warmup-delay-ns = <6700>; + qcom,pull-down-enable = <1>; + qcom,peak-curr-limit-ma = <570>; + + qcom, enable-psm = <1>; + qcom,psm-hys-mv = <13>; +}; diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt index 8957ff9dc9ee..e8177c3a0952 100644 --- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt +++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt @@ -1610,10 +1610,10 @@ Example: asoc-wsa-codec-prefixes = "SpkrMono"; }; -* MSMFALCON ASoC Machine driver +* SDM660 ASoC Machine driver Required properties: -- compatible : "qcom,msmfalcon-asoc-snd" +- compatible : "qcom,sdm660-asoc-snd" - qcom,model : The user-visible name of this sound card. - qcom,msm-hs-micbias-type : This property is used to recognize the headset micbias type, internal or external. @@ -1666,8 +1666,8 @@ mclk frequency needs to be configured for internal and external PA. Example: sound { - compatible = "qcom,msmfalcon-asoc-snd"; - qcom,model = "msmfalcon-snd-card"; + compatible = "qcom,sdm660-asoc-snd"; + qcom,model = "sdm660-snd-card"; qcom,msm-mclk-freq = <9600000>; qcom,msm-mbhc-hphl-swh = <0>; qcom,msm-mbhc-gnd-swh = <0>; @@ -1772,6 +1772,10 @@ Optional Properties: - qcom,msm-mi2s-master: This property is used to inform machine driver if MSM is the clock master of mi2s. 1 means master and 0 means slave. The first entry is primary mi2s; the second entry is secondary mi2s, and so on. +- qcom,msm-mi2s-ext-mclk: This property is used to inform machine driver + if MCLK from MSM is used for any external audio connections. 1 means used + as external mclk source and 0 indicate not used. The first entry is + primary mclk; the second entry is secondary mclk, and so on. - reg: This property provides the AUX PCM/MI2S mux select register addresses and size. - reg_names: This property provides the name of the AUX PCM/MI2S mux select @@ -1812,6 +1816,7 @@ Example: qcom,mi2s-audio-intf; qcom,auxpcm-audio-intf; qcom,msm-mi2s-master = <1>, <0>, <1>, <1>; + qcom,msm-mi2s-ext-mclk = <1>, <1>, <0>, <1>; reg = <0x1711a000 0x4>, <0x1711b000 0x4>, <0x1711c000 0x4>, @@ -2151,11 +2156,11 @@ Example: asoc-codec-names = "msm-stub-codec.1"; }; -* MSMFALCON ASoC Slimbus Machine driver +* SDM660 ASoC Slimbus Machine driver Required properties: -- compatible : "qcom,msmfalcon-asoc-snd-tasha" for tasha codec, - "qcom,msmfalcon-asoc-snd-tavil" for tavil codec. +- compatible : "qcom,sdm660-asoc-snd-tasha" for tasha codec, + "qcom,sdm660-asoc-snd-tavil" for tavil codec. - qcom,model : The user-visible name of this sound card. - qcom,msm-mclk-freq : MCLK frequency value for external codec - qcom,msm-gpios : Lists down all the gpio sets that are supported. @@ -2195,8 +2200,8 @@ Optional properties: Example: sound-9335 { - compatible = "qcom,msmfalcon-asoc-snd-tasha"; - qcom,model = "msmfalcon-tasha-snd-card"; + compatible = "qcom,sdm660-asoc-snd-tasha"; + qcom,model = "sdm660-tasha-snd-card"; qcom,audio-routing = "RX_BIAS", "MCLK", diff --git a/Documentation/devicetree/bindings/thermal/tsens.txt b/Documentation/devicetree/bindings/thermal/tsens.txt index ada060d19a9b..53b2463a79dd 100644 --- a/Documentation/devicetree/bindings/thermal/tsens.txt +++ b/Documentation/devicetree/bindings/thermal/tsens.txt @@ -31,8 +31,8 @@ Required properties: should be "qcom,msmgold-tsens" for gold TSENS driver. should be "qcom,msm8998-tsens" for 8998 TSENS driver. should be "qcom,msmhamster-tsens" for hamster TSENS driver. - should be "qcom,msmfalcon-tsens" for falcon TSENS driver. - should be "qcom,msmtriton-tsens" for triton TSENS driver. + should be "qcom,sdm660-tsens" for 660 TSENS driver. + should be "qcom,sdm630-tsens" for 630 TSENS driver. The compatible property is used to identify the respective fusemap to use for the corresponding SoC. - reg : offset and length of the TSENS registers with associated property in reg-names diff --git a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt index 66142b4cd880..f836fc7ab439 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-qcom.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-qcom.txt @@ -10,7 +10,7 @@ Required properties: - compatible : compatible list, contains "qcom,ufs-phy-qmp-20nm" or "qcom,ufs-phy-qmp-14nm" or "qcom,ufs-phy-qmp-v3" or "qcom,ufs-phy-qrbtc-v2" or - "qcom,ufs-phy-qmp-v3-falcon" + "qcom,ufs-phy-qmp-v3-660" according to the relevant phy in use. - reg : should contain PHY register address space (mandatory), - reg-names : indicates various resources passed to driver (via reg proptery) by name. diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 9b702a7bf08e..65c42b8de30c 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -130,38 +130,77 @@ dtb-$(CONFIG_ARCH_MSM8998) += msm8998-sim.dtb \ apq8998-v2.1-cdp.dtb \ apq8998-v2.1-qrd.dtb \ apq8998-v2.1-mediabox.dtb \ - msm8998-v2.1-interposer-msmfalcon-cdp.dtb \ - msm8998-v2.1-interposer-msmfalcon-mtp.dtb \ - msm8998-v2.1-interposer-msmfalcon-qrd.dtb + msm8998-v2.1-interposer-sdm660-cdp.dtb \ + msm8998-v2.1-interposer-sdm660-mtp.dtb \ + msm8998-v2.1-interposer-sdm660-qrd.dtb dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb -dtb-$(CONFIG_ARCH_MSMFALCON) += msmfalcon-sim.dtb \ - msmfalcon-internal-codec-cdp.dtb \ - msmfalcon-internal-codec-mtp.dtb \ - msmfalcon-internal-codec-rcm.dtb \ - msmfalcon-cdp.dtb \ - msmfalcon-mtp.dtb \ - msmfalcon-qrd.dtb \ - msmfalcon-rcm.dtb \ - msmfalcon-rumi.dtb \ - msmfalcon-pm3falcon-cdp.dtb \ - msmfalcon-pm3falcon-mtp.dtb \ - msmfalcon-pm3falcon-qrd.dtb \ - msmfalcon-pm3falcon-rcm.dtb \ - msmfalcon-pm3falcon-rumi.dtb \ - msmfalcon-internal-codec-pm3falcon-cdp.dtb \ - msmfalcon-internal-codec-pm3falcon-mtp.dtb \ - msmfalcon-internal-codec-pm3falcon-rcm.dtb \ - msmfalcon-pm3falcon-sim.dtb \ - apqfalcon-cdp.dtb \ - apqfalcon-mtp.dtb \ - apqfalcon-rcm.dtb \ - apqfalcon-pm3falcon-cdp.dtb \ - apqfalcon-pm3falcon-mtp.dtb \ - apqfalcon-pm3falcon-rcm.dtb +dtb-$(CONFIG_ARCH_SDM660) += sdm660-sim.dtb \ + sdm660-internal-codec-cdp.dtb \ + sdm660-internal-codec-mtp.dtb \ + sdm660-internal-codec-rcm.dtb \ + sdm660-cdp.dtb \ + sdm660-mtp.dtb \ + sdm660-qrd.dtb \ + sdm660-rcm.dtb \ + sdm660-rumi.dtb \ + sdm660-pm660a-cdp.dtb \ + sdm660-pm660a-mtp.dtb \ + sdm660-pm660a-qrd.dtb \ + sdm660-pm660a-rcm.dtb \ + sdm660-pm660a-rumi.dtb \ + sdm660-internal-codec-pm660a-cdp.dtb \ + sdm660-internal-codec-pm660a-mtp.dtb \ + sdm660-internal-codec-pm660a-rcm.dtb \ + sdm660-pm660a-sim.dtb \ + sda660-cdp.dtb \ + sda660-mtp.dtb \ + sda660-rcm.dtb \ + sda660-pm660a-cdp.dtb \ + sda660-pm660a-mtp.dtb \ + sda660-pm660a-rcm.dtb \ + sdm658-mtp.dtb \ + sdm658-cdp.dtb \ + sdm658-rcm.dtb \ + sdm658-qrd.dtb \ + sdm658-pm660a-mtp.dtb \ + sdm658-pm660a-cdp.dtb \ + sdm658-pm660a-rcm.dtb \ + sdm658-pm660a-qrd.dtb \ + sdm658-internal-codec-mtp.dtb \ + sdm658-internal-codec-cdp.dtb \ + sdm658-internal-codec-rcm.dtb \ + sdm658-internal-codec-pm660a-mtp.dtb \ + sdm658-internal-codec-pm660a-cdp.dtb \ + sdm658-internal-codec-pm660a-rcm.dtb \ + sda658-cdp.dtb \ + sda658-mtp.dtb \ + sda658-rcm.dtb \ + sda658-pm660a-mtp.dtb \ + sda658-pm660a-cdp.dtb \ + sda658-pm660a-rcm.dtb -dtb-$(CONFIG_ARCH_MSMTRITON) += msmtriton-rumi.dtb +dtb-$(CONFIG_ARCH_SDM630) += sdm630-rumi.dtb \ + sdm630-pm660a-rumi.dtb \ + sdm630-mtp.dtb \ + sdm630-cdp.dtb \ + sdm630-rcm.dtb \ + sdm630-internal-codec-mtp.dtb \ + sdm630-internal-codec-cdp.dtb \ + sdm630-internal-codec-rcm.dtb \ + sdm630-pm660a-cdp.dtb \ + sdm630-pm660a-mtp.dtb \ + sdm630-pm660a-rcm.dtb \ + sdm630-internal-codec-pm660a-cdp.dtb \ + sdm630-internal-codec-pm660a-mtp.dtb \ + sdm630-internal-codec-pm660a-rcm.dtb \ + sda630-mtp.dtb \ + sda630-cdp.dtb \ + sda630-rcm.dtb \ + sda630-pm660a-mtp.dtb \ + sda630-pm660a-cdp.dtb \ + sda630-pm660a-rcm.dtb ifeq ($(CONFIG_ARM64),y) always := $(dtb-y) diff --git a/arch/arm/boot/dts/qcom/dsi-adv7533-1080p.dtsi b/arch/arm/boot/dts/qcom/dsi-adv7533-1080p.dtsi index d67922a865fb..7994285f13f1 100644 --- a/arch/arm/boot/dts/qcom/dsi-adv7533-1080p.dtsi +++ b/arch/arm/boot/dts/qcom/dsi-adv7533-1080p.dtsi @@ -64,7 +64,7 @@ qcom,mdss-pan-physical-height-dimension = <90>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-always-on; - qcom,mdss-dsi-panel-timings-8996 = [1d 1a 03 05 01 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [1d 1a 03 05 01 03 04 a0 1d 1a 03 05 01 03 04 a0 1d 1a 03 05 01 03 04 a0 1d 1a 03 05 01 03 04 a0 diff --git a/arch/arm/boot/dts/qcom/dsi-adv7533-720p.dtsi b/arch/arm/boot/dts/qcom/dsi-adv7533-720p.dtsi index f6a42b430b58..b84488c0cef3 100644 --- a/arch/arm/boot/dts/qcom/dsi-adv7533-720p.dtsi +++ b/arch/arm/boot/dts/qcom/dsi-adv7533-720p.dtsi @@ -63,7 +63,7 @@ dsi_adv7533_720p: qcom,mdss_dsi_adv7533_720p { qcom,mdss-pan-physical-height-dimension = <90>; qcom,mdss-dsi-force-clock-lane-hs; qcom,mdss-dsi-always-on; - qcom,mdss-dsi-panel-timings-8996 = [1c 19 02 03 01 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [1c 19 02 03 01 03 04 a0 1c 19 02 03 01 03 04 a0 1c 19 02 03 01 03 04 a0 1c 19 02 03 01 03 04 a0 diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi new file mode 100644 index 000000000000..7a3660a3b480 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi @@ -0,0 +1,266 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_nt35597_truly_dsc_video: qcom,mdss_dsi_nt35597_dsc_cmd_truly { + qcom,mdss-dsi-panel-name = + "nt35597 cmd mode dsi truly panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 10 00 02 ff 20 + 15 01 00 00 10 00 02 fb 01 + 15 01 00 00 10 00 02 00 01 + 15 01 00 00 10 00 02 01 55 + 15 01 00 00 10 00 02 02 45 + 15 01 00 00 10 00 02 05 40 + 15 01 00 00 10 00 02 06 19 + 15 01 00 00 10 00 02 07 1e + 15 01 00 00 10 00 02 0b 73 + 15 01 00 00 10 00 02 0c 73 + 15 01 00 00 10 00 02 0e b0 + 15 01 00 00 10 00 02 0f ae + 15 01 00 00 10 00 02 11 b8 + 15 01 00 00 10 00 02 13 00 + 15 01 00 00 10 00 02 58 80 + 15 01 00 00 10 00 02 59 01 + 15 01 00 00 10 00 02 5a 00 + 15 01 00 00 10 00 02 5b 01 + 15 01 00 00 10 00 02 5c 80 + 15 01 00 00 10 00 02 5d 81 + 15 01 00 00 10 00 02 5e 00 + 15 01 00 00 10 00 02 5f 01 + 15 01 00 00 10 00 02 72 31 + 15 01 00 00 10 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 10 00 02 ff 24 + 15 01 00 00 10 00 02 fb 01 + 15 01 00 00 10 00 02 00 1c + 15 01 00 00 10 00 02 01 0b + 15 01 00 00 10 00 02 02 0c + 15 01 00 00 10 00 02 03 01 + 15 01 00 00 10 00 02 04 0f + 15 01 00 00 10 00 02 05 10 + 15 01 00 00 10 00 02 06 10 + 15 01 00 00 10 00 02 07 10 + 15 01 00 00 10 00 02 08 89 + 15 01 00 00 10 00 02 09 8a + 15 01 00 00 10 00 02 0a 13 + 15 01 00 00 10 00 02 0b 13 + 15 01 00 00 10 00 02 0c 15 + 15 01 00 00 10 00 02 0d 15 + 15 01 00 00 10 00 02 0e 17 + 15 01 00 00 10 00 02 0f 17 + 15 01 00 00 10 00 02 10 1c + 15 01 00 00 10 00 02 11 0b + 15 01 00 00 10 00 02 12 0c + 15 01 00 00 10 00 02 13 01 + 15 01 00 00 10 00 02 14 0f + 15 01 00 00 10 00 02 15 10 + 15 01 00 00 10 00 02 16 10 + 15 01 00 00 10 00 02 17 10 + 15 01 00 00 10 00 02 18 89 + 15 01 00 00 10 00 02 19 8a + 15 01 00 00 10 00 02 1a 13 + 15 01 00 00 10 00 02 1b 13 + 15 01 00 00 10 00 02 1c 15 + 15 01 00 00 10 00 02 1d 15 + 15 01 00 00 10 00 02 1e 17 + 15 01 00 00 10 00 02 1f 17 + /* STV */ + 15 01 00 00 10 00 02 20 40 + 15 01 00 00 10 00 02 21 01 + 15 01 00 00 10 00 02 22 00 + 15 01 00 00 10 00 02 23 40 + 15 01 00 00 10 00 02 24 40 + 15 01 00 00 10 00 02 25 6d + 15 01 00 00 10 00 02 26 40 + 15 01 00 00 10 00 02 27 40 + /* Vend */ + 15 01 00 00 10 00 02 e0 00 + 15 01 00 00 10 00 02 dc 21 + 15 01 00 00 10 00 02 dd 22 + 15 01 00 00 10 00 02 de 07 + 15 01 00 00 10 00 02 df 07 + 15 01 00 00 10 00 02 e3 6D + 15 01 00 00 10 00 02 e1 07 + 15 01 00 00 10 00 02 e2 07 + /* UD */ + 15 01 00 00 10 00 02 29 d8 + 15 01 00 00 10 00 02 2a 2a + /* CLK */ + 15 01 00 00 10 00 02 4b 03 + 15 01 00 00 10 00 02 4c 11 + 15 01 00 00 10 00 02 4d 10 + 15 01 00 00 10 00 02 4e 01 + 15 01 00 00 10 00 02 4f 01 + 15 01 00 00 10 00 02 50 10 + 15 01 00 00 10 00 02 51 00 + 15 01 00 00 10 00 02 52 80 + 15 01 00 00 10 00 02 53 00 + 15 01 00 00 10 00 02 56 00 + 15 01 00 00 10 00 02 54 07 + 15 01 00 00 10 00 02 58 07 + 15 01 00 00 10 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 10 00 02 5b 43 + 15 01 00 00 10 00 02 5c 00 + 15 01 00 00 10 00 02 5f 73 + 15 01 00 00 10 00 02 60 73 + 15 01 00 00 10 00 02 63 22 + 15 01 00 00 10 00 02 64 00 + 15 01 00 00 10 00 02 67 08 + 15 01 00 00 10 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 10 00 02 72 02 + /* mux */ + 15 01 00 00 10 00 02 7a 80 + 15 01 00 00 10 00 02 7b 91 + 15 01 00 00 10 00 02 7c D8 + 15 01 00 00 10 00 02 7d 60 + 15 01 00 00 10 00 02 7f 15 + 15 01 00 00 10 00 02 75 15 + /* ABOFF */ + 15 01 00 00 10 00 02 b3 C0 + 15 01 00 00 10 00 02 b4 00 + 15 01 00 00 10 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 10 00 02 78 00 + 15 01 00 00 10 00 02 79 00 + 15 01 00 00 10 00 02 80 00 + 15 01 00 00 10 00 02 83 00 + /* FP BP */ + 15 01 00 00 10 00 02 93 0a + 15 01 00 00 10 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 10 00 02 8a 00 + 15 01 00 00 10 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 10 00 02 9d b0 + 15 01 00 00 10 00 02 9f 63 + 15 01 00 00 10 00 02 98 10 + /* FRM */ + 15 01 00 00 10 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 10 00 02 ff 10 + /* VESA DSC PPS settings(1440x2560 slide 16H) */ + 39 01 00 00 10 00 11 c1 09 20 00 10 02 00 02 68 + 01 bb 00 0a 06 67 04 c5 + 39 01 00 00 10 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC)0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 10 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 10 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 10 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 10 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 10 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 10 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 a0 00 02 11 00 + 05 01 00 00 a0 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = [cd 32 22 00 60 64 26 34 29 03 + 04 00]; + qcom,mdss-dsi-t-clk-post = <0x0b>; + qcom,mdss-dsi-t-clk-pre = <0x23>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,ulps-enabled; + + qcom,compression-mode = "dsc"; + qcom,config-select = <&dsi_nt35597_truly_dsc_cmd_config0>; + + dsi_nt35597_truly_dsc_cmd_config0: config0 { + qcom,mdss-dsc-encoders = <1>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + dsi_nt35597_truly_dsc_cmd_config1: config1 { + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <1>; /* 3D Mux */ + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + dsi_nt35597_truly_dsc_cmd_config2: config2 { + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <2>; /* DSC Merge */ + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi new file mode 100644 index 000000000000..ca2ff6eb4924 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi @@ -0,0 +1,252 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_nt35597_truly_dsc_video: qcom,mdss_dsi_nt35597_dsc_video_truly { + qcom,mdss-dsi-panel-name = + "nt35597 video mode dsi truly panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 10 00 02 ff 20 + 15 01 00 00 10 00 02 fb 01 + 15 01 00 00 10 00 02 00 01 + 15 01 00 00 10 00 02 01 55 + 15 01 00 00 10 00 02 02 45 + 15 01 00 00 10 00 02 05 40 + 15 01 00 00 10 00 02 06 19 + 15 01 00 00 10 00 02 07 1e + 15 01 00 00 10 00 02 0b 73 + 15 01 00 00 10 00 02 0c 73 + 15 01 00 00 10 00 02 0e b0 + 15 01 00 00 10 00 02 0f aE + 15 01 00 00 10 00 02 11 b8 + 15 01 00 00 10 00 02 13 00 + 15 01 00 00 10 00 02 58 80 + 15 01 00 00 10 00 02 59 01 + 15 01 00 00 10 00 02 5a 00 + 15 01 00 00 10 00 02 5b 01 + 15 01 00 00 10 00 02 5c 80 + 15 01 00 00 10 00 02 5d 81 + 15 01 00 00 10 00 02 5e 00 + 15 01 00 00 10 00 02 5f 01 + 15 01 00 00 10 00 02 72 31 + 15 01 00 00 10 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 10 00 02 ff 24 + 15 01 00 00 10 00 02 fb 01 + 15 01 00 00 10 00 02 00 1c + 15 01 00 00 10 00 02 01 0b + 15 01 00 00 10 00 02 02 0c + 15 01 00 00 10 00 02 03 01 + 15 01 00 00 10 00 02 04 0f + 15 01 00 00 10 00 02 05 10 + 15 01 00 00 10 00 02 06 10 + 15 01 00 00 10 00 02 07 10 + 15 01 00 00 10 00 02 08 89 + 15 01 00 00 10 00 02 09 8a + 15 01 00 00 10 00 02 0a 13 + 15 01 00 00 10 00 02 0b 13 + 15 01 00 00 10 00 02 0c 15 + 15 01 00 00 10 00 02 0d 15 + 15 01 00 00 10 00 02 0e 17 + 15 01 00 00 10 00 02 0f 17 + 15 01 00 00 10 00 02 10 1c + 15 01 00 00 10 00 02 11 0b + 15 01 00 00 10 00 02 12 0c + 15 01 00 00 10 00 02 13 01 + 15 01 00 00 10 00 02 14 0f + 15 01 00 00 10 00 02 15 10 + 15 01 00 00 10 00 02 16 10 + 15 01 00 00 10 00 02 17 10 + 15 01 00 00 10 00 02 18 89 + 15 01 00 00 10 00 02 19 8a + 15 01 00 00 10 00 02 1a 13 + 15 01 00 00 10 00 02 1b 13 + 15 01 00 00 10 00 02 1c 15 + 15 01 00 00 10 00 02 1d 15 + 15 01 00 00 10 00 02 1e 17 + 15 01 00 00 10 00 02 1f 17 + /* STV */ + 15 01 00 00 10 00 02 20 40 + 15 01 00 00 10 00 02 21 01 + 15 01 00 00 10 00 02 22 00 + 15 01 00 00 10 00 02 23 40 + 15 01 00 00 10 00 02 24 40 + 15 01 00 00 10 00 02 25 6d + 15 01 00 00 10 00 02 26 40 + 15 01 00 00 10 00 02 27 40 + /* Vend */ + 15 01 00 00 10 00 02 e0 00 + 15 01 00 00 10 00 02 dc 21 + 15 01 00 00 10 00 02 dd 22 + 15 01 00 00 10 00 02 de 07 + 15 01 00 00 10 00 02 df 07 + 15 01 00 00 10 00 02 e3 6d + 15 01 00 00 10 00 02 e1 07 + 15 01 00 00 10 00 02 e2 07 + /* UD */ + 15 01 00 00 10 00 02 29 d8 + 15 01 00 00 10 00 02 2a 2a + /* CLK */ + 15 01 00 00 10 00 02 4b 03 + 15 01 00 00 10 00 02 4c 11 + 15 01 00 00 10 00 02 4d 10 + 15 01 00 00 10 00 02 4e 01 + 15 01 00 00 10 00 02 4f 01 + 15 01 00 00 10 00 02 50 10 + 15 01 00 00 10 00 02 51 00 + 15 01 00 00 10 00 02 52 80 + 15 01 00 00 10 00 02 53 00 + 15 01 00 00 10 00 02 56 00 + 15 01 00 00 10 00 02 54 07 + 15 01 00 00 10 00 02 58 07 + 15 01 00 00 10 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 10 00 02 5b 43 + 15 01 00 00 10 00 02 5c 00 + 15 01 00 00 10 00 02 5f 73 + 15 01 00 00 10 00 02 60 73 + 15 01 00 00 10 00 02 63 22 + 15 01 00 00 10 00 02 64 00 + 15 01 00 00 10 00 02 67 08 + 15 01 00 00 10 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 10 00 02 72 02 + /* mux */ + 15 01 00 00 10 00 02 7a 80 + 15 01 00 00 10 00 02 7b 91 + 15 01 00 00 10 00 02 7c d8 + 15 01 00 00 10 00 02 7d 60 + 15 01 00 00 10 00 02 7f 15 + 15 01 00 00 10 00 02 75 15 + /* ABOFF */ + 15 01 00 00 10 00 02 b3 c0 + 15 01 00 00 10 00 02 b4 00 + 15 01 00 00 10 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 10 00 02 78 00 + 15 01 00 00 10 00 02 79 00 + 15 01 00 00 10 00 02 80 00 + 15 01 00 00 10 00 02 83 00 + /* FP BP */ + 15 01 00 00 10 00 02 93 0a + 15 01 00 00 10 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 10 00 02 8a 00 + 15 01 00 00 10 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 10 00 02 9d b0 + 15 01 00 00 10 00 02 9f 63 + 15 01 00 00 10 00 02 98 10 + /* FRM */ + 15 01 00 00 10 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 10 00 02 ff 10 + /* VESA DSC PPS settings(1440x2560 slide 16H) */ + 39 01 00 00 10 00 11 c1 09 20 00 10 02 00 02 68 01 + bb 00 0a 06 67 04 c5 + 39 01 00 00 10 00 03 c2 10 f0 + /* C0h = 0x00(2 Port SDC); 0x01(1 PortA FBC); + * 0x02(MTK); 0x03(1 PortA VESA) + */ + 15 01 00 00 10 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 39 01 00 00 10 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 10 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 10 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 10 00 02 bb 03 + /* Non Reload MTP */ + 15 01 00 00 10 00 02 fb 01 + /* SlpOut + DispOn */ + 05 01 00 00 a0 00 02 11 00 + 05 01 00 00 a0 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-panel-timings = [00 11 04 04 07 0c 04 04 03 03 + 04 00]; + qcom,mdss-dsi-t-clk-post = <0xb>; + qcom,mdss-dsi-t-clk-pre = <0x23>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <131>; + + qcom,compression-mode = "dsc"; + qcom,config-select = <&dsi_nt35597_truly_dsc_video_config0>; + + dsi_nt35597_truly_dsc_video_config0: config0 { + qcom,mdss-dsc-encoders = <1>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + dsi_nt35597_truly_dsc_video_config1: config1 { + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <1>; /* 3D Mux */ + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + dsi_nt35597_truly_dsc_video_config2: config2 { + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <2>; /* DSC Merge */ + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi b/arch/arm/boot/dts/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi new file mode 100644 index 000000000000..7774a28ff495 --- /dev/null +++ b/arch/arm/boot/dts/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi @@ -0,0 +1,416 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_dual_nt36850_truly_cmd: qcom,mdss_dsi_nt36850_truly_wqhd_cmd{ + qcom,mdss-dsi-panel-name = + "Dual nt36850 cmd mode dsi truly panel without DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <140>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 19 + 15 01 00 00 00 00 02 01 03 + 15 01 00 00 00 00 02 02 04 + 15 01 00 00 00 00 02 03 1b + 15 01 00 00 00 00 02 04 1d + 15 01 00 00 00 00 02 05 01 + 15 01 00 00 00 00 02 06 0c + 15 01 00 00 00 00 02 07 0f + 15 01 00 00 00 00 02 08 1f + 15 01 00 00 00 00 02 09 00 + 15 01 00 00 00 00 02 0a 00 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 16 + 15 01 00 00 00 00 02 0d 14 + 15 01 00 00 00 00 02 0e 15 + 15 01 00 00 00 00 02 0f 00 + 15 01 00 00 00 00 02 10 19 + 15 01 00 00 00 00 02 11 03 + 15 01 00 00 00 00 02 12 04 + 15 01 00 00 00 00 02 13 1b + 15 01 00 00 00 00 02 14 1d + 15 01 00 00 00 00 02 15 01 + 15 01 00 00 00 00 02 16 0c + 15 01 00 00 00 00 02 17 0f + 15 01 00 00 00 00 02 18 1f + 15 01 00 00 00 00 02 19 00 + 15 01 00 00 00 00 02 1a 00 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 16 + 15 01 00 00 00 00 02 1d 14 + 15 01 00 00 00 00 02 1e 15 + 15 01 00 00 00 00 02 1f 00 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 10 + 15 01 00 00 00 00 02 23 28 + 15 01 00 00 00 00 02 24 28 + 15 01 00 00 00 00 02 25 5d + 15 01 00 00 00 00 02 26 28 + 15 01 00 00 00 00 02 27 28 + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 15 + 15 01 00 00 00 00 02 2b 00 + 15 01 00 00 00 00 02 2d 00 + 15 01 00 00 00 00 02 2f 02 + 15 01 00 00 00 00 02 30 02 + 15 01 00 00 00 00 02 31 00 + 15 01 00 00 00 00 02 32 23 + 15 01 00 00 00 00 02 33 01 + 15 01 00 00 00 00 02 34 03 + 15 01 00 00 00 00 02 35 49 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 37 1d + 15 01 00 00 00 00 02 38 08 + 15 01 00 00 00 00 02 39 03 + 15 01 00 00 00 00 02 3a 49 + 15 01 00 00 00 00 02 42 01 + 15 01 00 00 00 00 02 43 8c + 15 01 00 00 00 00 02 44 a3 + 15 01 00 00 00 00 02 48 8c + 15 01 00 00 00 00 02 49 a3 + 15 01 00 00 00 00 02 5b 00 + 15 01 00 00 00 00 02 5f 4d + 15 01 00 00 00 00 02 63 00 + 15 01 00 00 00 00 02 67 04 + 15 01 00 00 00 00 02 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b8 40 + 15 01 00 00 00 00 02 ba 22 + 15 01 00 00 00 00 02 bb 00 + 15 01 00 00 00 00 02 c2 01 + 15 01 00 00 00 00 02 c3 01 + 15 01 00 00 00 00 02 c4 01 + 15 01 00 00 00 00 02 c5 01 + 15 01 00 00 00 00 02 c6 01 + 15 01 00 00 00 00 02 c8 00 + 15 01 00 00 00 00 02 c9 00 + 15 01 00 00 00 00 02 ca 00 + 15 01 00 00 00 00 02 cd 00 + 15 01 00 00 00 00 02 ce 00 + 15 01 00 00 00 00 02 d6 04 + 15 01 00 00 00 00 02 d7 00 + 15 01 00 00 00 00 02 d8 0d + 15 01 00 00 00 00 02 d9 00 + 15 01 00 00 00 00 02 da 00 + 15 01 00 00 00 00 02 db 00 + 15 01 00 00 00 00 02 dc 00 + 15 01 00 00 00 00 02 dd 00 + 15 01 00 00 00 00 02 de 00 + 15 01 00 00 00 00 02 df 01 + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 e1 00 + 15 01 00 00 00 00 02 e2 19 + 15 01 00 00 00 00 02 e3 04 + 15 01 00 00 00 00 02 e4 00 + 15 01 00 00 00 00 02 e5 04 + 15 01 00 00 00 00 02 e6 00 + 15 01 00 00 00 00 02 e7 12 + 15 01 00 00 00 00 02 e8 00 + 15 01 00 00 00 00 02 e9 50 + 15 01 00 00 00 00 02 ea 10 + 15 01 00 00 00 00 02 eb 02 + 15 01 00 00 00 00 02 ff 27 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 ff 28 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 60 0a + 15 01 00 00 00 00 02 63 32 + 15 01 00 00 00 00 02 64 01 + 15 01 00 00 00 00 02 68 da + 15 01 00 00 00 00 02 69 00 + 15 01 00 00 00 00 02 ff 29 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 60 0a + 15 01 00 00 00 00 02 63 32 + 15 01 00 00 00 00 02 64 01 + 15 01 00 00 00 00 02 68 da + 15 01 00 00 00 00 02 69 00 + 15 01 00 00 00 00 02 ff e0 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 35 40 + 15 01 00 00 00 00 02 36 40 + 15 01 00 00 00 00 02 37 00 + 15 01 00 00 00 00 02 89 c6 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 ea 40 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 44 03 e8 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 2c + 15 01 00 00 00 00 02 55 01 + 05 01 00 00 0a 00 02 20 00 + 15 01 00 00 00 00 02 bb 10 + 05 01 00 00 78 00 02 11 00 + 05 01 00 00 14 00 02 29 00]; + qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-tx-eot-append; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-timings = + [da 34 24 00 64 68 28 38 2a 03 04 00]; + qcom,mdss-dsi-t-clk-pre = <0x29>; + qcom,mdss-dsi-t-clk-post = <0x03>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-triton.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-630.dtsi index f4bf275dcc3c..4ab200d6b89d 100644 --- a/arch/arm/boot/dts/qcom/msm-arm-smmu-triton.dtsi +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-630.dtsi @@ -10,8 +10,8 @@ * GNU General Public License for more details. */ -#include "msm-arm-smmu-falcon.dtsi" -#include "msm-arm-smmu-impl-defs-falcon.dtsi" +#include "msm-arm-smmu-660.dtsi" +#include "msm-arm-smmu-impl-defs-660.dtsi" &soc { /delete-node/ arm,smmu-turing_q6@5180000; diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-660.dtsi index 713e1b1bc66a..874b97a3c965 100644 --- a/arch/arm/boot/dts/qcom/msm-arm-smmu-falcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-660.dtsi @@ -10,8 +10,8 @@ * GNU General Public License for more details. */ -#include <dt-bindings/clock/qcom,gcc-msmfalcon.h> -#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h> +#include <dt-bindings/clock/qcom,gcc-sdm660.h> +#include <dt-bindings/clock/qcom,mmcc-sdm660.h> #include <dt-bindings/msm/msm-bus-ids.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-falcon.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-660.dtsi index f060f2d7008c..f060f2d7008c 100644 --- a/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-falcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-660.dtsi diff --git a/arch/arm/boot/dts/qcom/msm-audio.dtsi b/arch/arm/boot/dts/qcom/msm-audio.dtsi index 7a96e19c62c5..d86e77e2c7ee 100644 --- a/arch/arm/boot/dts/qcom/msm-audio.dtsi +++ b/arch/arm/boot/dts/qcom/msm-audio.dtsi @@ -571,8 +571,8 @@ }; tasha_snd: sound-9335 { - compatible = "qcom,msmfalcon-asoc-snd-tasha"; - qcom,model = "msmfalcon-tasha-snd-card"; + compatible = "qcom,sdm660-asoc-snd-tasha"; + qcom,model = "sdm660-tasha-snd-card"; qcom,wcn-btfm; qcom,mi2s-audio-intf; qcom,auxpcm-audio-intf; @@ -683,8 +683,8 @@ }; tavil_snd: sound-tavil { - compatible = "qcom,msmfalcon-asoc-snd-tavil"; - qcom,model = "msmfalcon-tavil-snd-card"; + compatible = "qcom,sdm660-asoc-snd-tavil"; + qcom,model = "sdm660-tavil-snd-card"; qcom,wcn-btfm; qcom,mi2s-audio-intf; qcom,auxpcm-audio-intf; @@ -792,8 +792,8 @@ int_codec: sound { status = "disabled"; - compatible = "qcom,msmfalcon-asoc-snd"; - qcom,model = "msmfalcon-snd-card"; + compatible = "qcom,sdm660-asoc-snd"; + qcom,model = "sdm660-snd-card"; qcom,wcn-btfm; qcom,mi2s-audio-intf; qcom,auxpcm-audio-intf; @@ -913,7 +913,7 @@ clock_audio: audio_ext_clk { compatible = "qcom,audio-ref-clk"; - qcom,audio-ref-clk-gpio = <&pmfalcon_gpios 3 0>; + qcom,audio-ref-clk-gpio = <&pm660_gpios 3 0>; clock-names = "osr_clk"; clocks = <&clock_rpmcc AUDIO_PMI_CLK>; qcom,node_has_rpm_clock; diff --git a/arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi b/arch/arm/boot/dts/qcom/msm-gdsc-660.dtsi index 6550ddcad86c..6550ddcad86c 100644 --- a/arch/arm/boot/dts/qcom/msm-gdsc-falcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm-gdsc-660.dtsi diff --git a/arch/arm/boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/msm-pm660-rpm-regulator.dtsi index 0b625bf04ef5..0f87d1390d5c 100644 --- a/arch/arm/boot/dts/qcom/msm-pmfalcon-rpm-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pm660-rpm-regulator.dtsi @@ -20,7 +20,7 @@ regulator-s4 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_s4"; + regulator-name = "pm660_s4"; qcom,set = <3>; status = "disabled"; }; @@ -35,7 +35,7 @@ regulator-s5 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_s5"; + regulator-name = "pm660_s5"; qcom,set = <3>; status = "disabled"; }; @@ -50,7 +50,7 @@ regulator-s6 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_s6"; + regulator-name = "pm660_s6"; qcom,set = <3>; status = "disabled"; }; @@ -65,7 +65,7 @@ regulator-l1 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l1"; + regulator-name = "pm660_l1"; qcom,set = <3>; status = "disabled"; }; @@ -80,7 +80,7 @@ regulator-l2 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l2"; + regulator-name = "pm660_l2"; qcom,set = <3>; status = "disabled"; }; @@ -95,7 +95,7 @@ regulator-l3 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l3"; + regulator-name = "pm660_l3"; qcom,set = <3>; status = "disabled"; }; @@ -110,7 +110,7 @@ regulator-l5 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l5"; + regulator-name = "pm660_l5"; qcom,set = <3>; status = "disabled"; }; @@ -125,7 +125,7 @@ regulator-l6 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l6"; + regulator-name = "pm660_l6"; qcom,set = <3>; status = "disabled"; }; @@ -140,7 +140,7 @@ regulator-l7 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l7"; + regulator-name = "pm660_l7"; qcom,set = <3>; status = "disabled"; }; @@ -155,7 +155,7 @@ regulator-l8 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l8"; + regulator-name = "pm660_l8"; qcom,set = <3>; status = "disabled"; }; @@ -170,7 +170,7 @@ regulator-l9 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l9"; + regulator-name = "pm660_l9"; qcom,set = <3>; status = "disabled"; }; @@ -185,7 +185,7 @@ regulator-l10 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l10"; + regulator-name = "pm660_l10"; qcom,set = <3>; status = "disabled"; }; @@ -200,7 +200,7 @@ regulator-l11 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l11"; + regulator-name = "pm660_l11"; qcom,set = <3>; status = "disabled"; }; @@ -215,7 +215,7 @@ regulator-l12 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l12"; + regulator-name = "pm660_l12"; qcom,set = <3>; status = "disabled"; }; @@ -230,7 +230,7 @@ regulator-l13 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l13"; + regulator-name = "pm660_l13"; qcom,set = <3>; status = "disabled"; }; @@ -245,7 +245,7 @@ regulator-l14 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l14"; + regulator-name = "pm660_l14"; qcom,set = <3>; status = "disabled"; }; @@ -260,7 +260,7 @@ regulator-l15 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l15"; + regulator-name = "pm660_l15"; qcom,set = <3>; status = "disabled"; }; @@ -275,7 +275,7 @@ regulator-l17 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l17"; + regulator-name = "pm660_l17"; qcom,set = <3>; status = "disabled"; }; @@ -290,7 +290,7 @@ regulator-l19 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l19"; + regulator-name = "pm660_l19"; qcom,set = <3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm660.dtsi index 0168cb2cddb3..e8e773a33622 100644 --- a/arch/arm/boot/dts/qcom/msm-pmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pm660.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,13 +14,13 @@ #include <dt-bindings/interrupt-controller/irq.h> &spmi_bus { - qcom,pmfalcon@0 { + qcom,pm660@0 { compatible ="qcom,spmi-pmic"; reg = <0x0 SPMI_USID>; #address-cells = <2>; #size-cells = <0>; - pmfalcon_revid: qcom,revid@100 { + pm660_revid: qcom,revid@100 { compatible = "qcom,qpnp-revid"; reg = <0x100 0x100>; }; @@ -55,18 +55,18 @@ compatible = "qcom,qpnp-temp-alarm"; reg = <0x2400 0x100>; interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - label = "pmfalcon_tz"; + label = "pm660_tz"; qcom,channel-num = <6>; - qcom,temp_alarm-vadc = <&pmfalcon_vadc>; + qcom,temp_alarm-vadc = <&pm660_vadc>; }; - pmfalcon_gpios: gpios { + pm660_gpios: gpios { compatible = "qcom,qpnp-pin"; gpio-controller; #gpio-cells = <2>; #address-cells = <1>; #size-cells = <1>; - label = "pmfalcon-gpio"; + label = "pm660-gpio"; gpio@c000 { reg = <0xc000 0x100>; @@ -147,28 +147,28 @@ }; }; - pmfalcon_coincell: qcom,coincell@2800 { + pm660_coincell: qcom,coincell@2800 { compatible = "qcom,qpnp-coincell"; reg = <0x2800 0x100>; }; - pmfalcon_rtc: qcom,pmfalcon_rtc { + pm660_rtc: qcom,pm660_rtc { compatible = "qcom,qpnp-rtc"; #address-cells = <1>; #size-cells = <1>; qcom,qpnp-rtc-write = <0>; qcom,qpnp-rtc-alarm-pwrup = <0>; - qcom,pmfalcon_rtc_rw@6000 { + qcom,pm660_rtc_rw@6000 { reg = <0x6000 0x100>; }; - qcom,pmfalcon_rtc_alarm@6100 { + qcom,pm660_rtc_alarm@6100 { reg = <0x6100 0x100>; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; }; - pmfalcon_vadc: vadc@3100 { + pm660_vadc: vadc@3100 { compatible = "qcom,qpnp-vadc-hc"; reg = <0x3100 0x100>; #address-cells = <1>; @@ -282,17 +282,17 @@ }; }; - pmfalcon_charger: qcom,qpnp-smb2 { + pm660_charger: qcom,qpnp-smb2 { compatible = "qcom,qpnp-smb2"; #address-cells = <1>; #size-cells = <1>; - qcom,pmic-revid = <&pmfalcon_revid>; + qcom,pmic-revid = <&pm660_revid>; - io-channels = <&pmfalcon_rradc 8>, - <&pmfalcon_rradc 10>, - <&pmfalcon_rradc 3>, - <&pmfalcon_rradc 4>; + io-channels = <&pm660_rradc 8>, + <&pm660_rradc 10>, + <&pm660_rradc 3>, + <&pm660_rradc 4>; io-channel-names = "charger_temp", "charger_temp_max", "usbin_i", @@ -411,10 +411,10 @@ }; }; - pmfalcon_pdphy: qcom,usb-pdphy@1700 { + pm660_pdphy: qcom,usb-pdphy@1700 { compatible = "qcom,qpnp-pdphy"; reg = <0x1700 0x100>; - vdd-pdphy-supply = <&pm2falcon_l7>; + vdd-pdphy-supply = <&pm660l_l7>; vbus-supply = <&smb2_vbus>; vconn-supply = <&smb2_vconn>; interrupts = <0x0 0x17 0x0 IRQ_TYPE_EDGE_RISING>, @@ -434,7 +434,7 @@ "msg-rx-discarded"; }; - pmfalcon_adc_tm: vadc@3400 { + pm660_adc_tm: vadc@3400 { compatible = "qcom,qpnp-adc-tm-hc"; reg = <0x3400 0x100>; #address-cells = <1>; @@ -443,7 +443,7 @@ interrupt-names = "eoc-int-en-set"; qcom,adc-bit-resolution = <15>; qcom,adc-vdd-reference = <1875>; - qcom,adc_tm-vadc = <&pmfalcon_vadc>; + qcom,adc_tm-vadc = <&pm660_vadc>; qcom,decimation = <0>; qcom,fast-avg-setup = <0>; @@ -491,7 +491,7 @@ }; }; - pmfalcon_rradc: rradc@4500 { + pm660_rradc: rradc@4500 { compatible = "qcom,rradc"; reg = <0x4500 0x100>; #address-cells = <1>; @@ -499,12 +499,12 @@ #io-channel-cells = <1>; }; - pmfalcon_fg: qpnp,fg { + pm660_fg: qpnp,fg { compatible = "qcom,fg-gen3"; #address-cells = <1>; #size-cells = <1>; - qcom,pmic-revid = <&pmfalcon_revid>; - io-channels = <&pmfalcon_rradc 0>; + qcom,pmic-revid = <&pm660_revid>; + io-channels = <&pm660_rradc 0>; io-channel-names = "rradc_batt_id"; qcom,rradc-base = <0x4500>; qcom,fg-esr-timer-awake = <96>; @@ -576,17 +576,17 @@ }; }; - qcom,pmfalcon@1 { + qcom,pm660@1 { compatible ="qcom,spmi-pmic"; reg = <0x1 SPMI_USID>; #address-cells = <2>; #size-cells = <0>; - pmfalcon_haptics: qcom,haptic@c000 { + pm660_haptics: qcom,haptic@c000 { compatible = "qcom,qpnp-haptic"; reg = <0xc000 0x100>; - interrupts = <0x1 0xc0 0x0>, - <0x1 0xc0 0x1>; + interrupts = <0x1 0xc0 0x0 IRQ_TYPE_NONE>, + <0x1 0xc0 0x1 IRQ_TYPE_NONE>; interrupt-names = "sc-irq", "play-irq"; qcom,actuator-type = "lra"; qcom,play-mode = "direct"; diff --git a/arch/arm/boot/dts/qcom/msm-pm3falcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm660a.dtsi index f9a33fdc3e85..c43aa5425aae 100644 --- a/arch/arm/boot/dts/qcom/msm-pm3falcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pm660a.dtsi @@ -11,11 +11,11 @@ */ /* Disable WLED */ -&pm2falcon_wled { +&pm660l_wled { status = "disabled"; }; /* disable LCDB */ -&pm2falcon_lcdb { +&pm660l_lcdb { status = "disabled"; }; diff --git a/arch/arm/boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/msm-pm660l-rpm-regulator.dtsi index bc0793fec990..b10f8e559090 100644 --- a/arch/arm/boot/dts/qcom/msm-pm2falcon-rpm-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pm660l-rpm-regulator.dtsi @@ -20,7 +20,7 @@ regulator-s1 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s1"; + regulator-name = "pm660l_s1"; qcom,set = <3>; status = "disabled"; }; @@ -35,7 +35,7 @@ regulator-s2 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s2"; + regulator-name = "pm660l_s2"; qcom,set = <3>; status = "disabled"; }; @@ -50,7 +50,7 @@ regulator-s3 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3"; + regulator-name = "pm660l_s3"; qcom,set = <3>; status = "disabled"; }; @@ -65,7 +65,7 @@ regulator-s5 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5"; + regulator-name = "pm660l_s5"; qcom,set = <3>; status = "disabled"; }; @@ -80,7 +80,7 @@ regulator-l1 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l1"; + regulator-name = "pm660l_l1"; qcom,set = <3>; status = "disabled"; }; @@ -95,7 +95,7 @@ regulator-l2 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l2"; + regulator-name = "pm660l_l2"; qcom,set = <3>; status = "disabled"; }; @@ -110,7 +110,7 @@ regulator-l3 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l3"; + regulator-name = "pm660l_l3"; qcom,set = <3>; status = "disabled"; }; @@ -125,7 +125,7 @@ regulator-l4 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l4"; + regulator-name = "pm660l_l4"; qcom,set = <3>; status = "disabled"; }; @@ -140,7 +140,7 @@ regulator-l5 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l5"; + regulator-name = "pm660l_l5"; qcom,set = <3>; status = "disabled"; }; @@ -155,7 +155,7 @@ regulator-l6 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l6"; + regulator-name = "pm660l_l6"; qcom,set = <3>; status = "disabled"; }; @@ -170,7 +170,7 @@ regulator-l7 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l7"; + regulator-name = "pm660l_l7"; qcom,set = <3>; status = "disabled"; }; @@ -185,7 +185,7 @@ regulator-l8 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l8"; + regulator-name = "pm660l_l8"; qcom,set = <3>; status = "disabled"; }; @@ -200,7 +200,7 @@ regulator-l9 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l9"; + regulator-name = "pm660l_l9"; qcom,set = <3>; status = "disabled"; }; @@ -215,7 +215,7 @@ regulator-l10 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l10"; + regulator-name = "pm660l_l10"; qcom,set = <3>; status = "disabled"; }; @@ -230,7 +230,7 @@ regulator-bob { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob"; + regulator-name = "pm660l_bob"; qcom,set = <3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi b/arch/arm/boot/dts/qcom/msm-pm660l.dtsi index d3a920fff82e..d0033d5bf3bc 100644 --- a/arch/arm/boot/dts/qcom/msm-pm2falcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pm660l.dtsi @@ -15,13 +15,13 @@ #include <dt-bindings/msm/power-on.h> &spmi_bus { - qcom,pm2falcon@2 { + qcom,pm660l@2 { compatible = "qcom,spmi-pmic"; reg = <0x2 SPMI_USID>; #address-cells = <2>; #size-cells = <0>; - pm2falcon_revid: qcom,revid@100 { + pm660l_revid: qcom,revid@100 { compatible = "qcom,qpnp-revid"; reg = <0x100 0x100>; }; @@ -38,16 +38,16 @@ compatible = "qcom,qpnp-temp-alarm"; reg = <0x2400 0x100>; interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - label = "pm2falcon_tz"; + label = "pm660l_tz"; }; - pm2falcon_gpios: gpios { + pm660l_gpios: gpios { compatible = "qcom,qpnp-pin"; gpio-controller; #gpio-cells = <2>; #address-cells = <1>; #size-cells = <1>; - label = "pm2falcon-gpio"; + label = "pm660l-gpio"; gpio@c000 { reg = <0xc000 0x100>; @@ -124,13 +124,13 @@ }; }; - pm2falcon_3: qcom,pm2falcon@3 { + pm660l_3: qcom,pm660l@3 { compatible ="qcom,spmi-pmic"; reg = <0x3 SPMI_USID>; #address-cells = <2>; #size-cells = <0>; - pm2falcon_pwm_1: pwm@b100 { + pm660l_pwm_1: pwm@b100 { compatible = "qcom,qpnp-pwm"; reg = <0xb100 0x100>, <0xb042 0x7e>; @@ -143,7 +143,7 @@ #pwm-cells = <2>; }; - pm2falcon_pwm_2: pwm@b200 { + pm660l_pwm_2: pwm@b200 { compatible = "qcom,qpnp-pwm"; reg = <0xb200 0x100>, <0xb042 0x7e>; @@ -156,7 +156,7 @@ #pwm-cells = <2>; }; - pm2falcon_pwm_3: pwm@b300 { + pm660l_pwm_3: pwm@b300 { compatible = "qcom,qpnp-pwm"; reg = <0xb300 0x100>, <0xb042 0x7e>; @@ -167,9 +167,20 @@ qcom,supported-sizes = <6>, <9>; qcom,ramp-index = <2>; #pwm-cells = <2>; + qcom,period = <6000000>; + + qcom,lpg { + label = "lpg"; + cell-index = <0>; + qcom,duty-percents = + <0x01 0x0a 0x14 0x1e 0x28 0x32 0x3c + 0x46 0x50 0x5a 0x64 + 0x64 0x5a 0x50 0x46 0x3c 0x32 0x28 0x1e + 0x14 0x0a 0x01>; + }; }; - pm2falcon_pwm_4: pwm@b400 { + pm660l_pwm_4: pwm@b400 { compatible = "qcom,qpnp-pwm"; reg = <0xb400 0x100>, <0xb042 0x7e>; @@ -192,41 +203,43 @@ label = "rgb"; qcom,id = <3>; qcom,mode = "pwm"; - pwms = <&pm2falcon_pwm_3 0 0>; + pwms = <&pm660l_pwm_3 0 0>; qcom,pwm-us = <1000>; qcom,max-current = <12>; qcom,default-state = "off"; linux,name = "red"; - linux,default-trigger = - "battery-charging"; + qcom,start-idx = <0>; + qcom,idx-len = <22>; + qcom,duty-pcts = + [01 0a 14 1e 28 32 3c 46 50 5a 64 + 64 5a 50 46 3c 32 28 1e 14 0a 01]; + qcom,use-blink; }; green_led: qcom,rgb_1 { label = "rgb"; qcom,id = <4>; qcom,mode = "pwm"; - pwms = <&pm2falcon_pwm_2 0 0>; + pwms = <&pm660l_pwm_2 0 0>; qcom,pwm-us = <1000>; qcom,max-current = <12>; qcom,default-state = "off"; linux,name = "green"; - linux,default-trigger = "battery-full"; }; blue_led: qcom,rgb_2 { label = "rgb"; qcom,id = <5>; qcom,mode = "pwm"; - pwms = <&pm2falcon_pwm_1 0 0>; + pwms = <&pm660l_pwm_1 0 0>; qcom,pwm-us = <1000>; qcom,max-current = <12>; qcom,default-state = "off"; linux,name = "blue"; - linux,default-trigger = "boot-indication"; }; }; - pm2falcon_wled: qcom,leds@d800 { + pm660l_wled: qcom,leds@d800 { compatible = "qcom,qpnp-wled"; reg = <0xd800 0x100>, <0xd900 0x100>; @@ -252,7 +265,7 @@ qcom,led-strings-list = [00 01 02]; qcom,en-ext-pfet-sc-pro; qcom,loop-auto-gm-en; - qcom,pmic-revid = <&pm2falcon_revid>; + qcom,pmic-revid = <&pm660l_revid>; status = "ok"; }; @@ -273,9 +286,9 @@ qcom,thermal-derate-en; qcom,thermal-derate-current = <200 500 1000>; qcom,isc-delay = <192>; - qcom,pmic-revid = <&pm2falcon_revid>; + qcom,pmic-revid = <&pm660l_revid>; - pm2falcon_flash0: qcom,flash_0 { + pm660l_flash0: qcom,flash_0 { label = "flash"; qcom,led-name = "led:flash_0"; qcom,max-current = <1500>; @@ -288,7 +301,7 @@ qcom,hdrm-vol-hi-lo-win-mv = <100>; }; - pm2falcon_flash1: qcom,flash_1 { + pm660l_flash1: qcom,flash_1 { label = "flash"; qcom,led-name = "led:flash_1"; qcom,max-current = <1500>; @@ -301,7 +314,7 @@ qcom,hdrm-vol-hi-lo-win-mv = <100>; }; - pm2falcon_flash2: qcom,flash_2 { + pm660l_flash2: qcom,flash_2 { label = "flash"; qcom,led-name = "led:flash_2"; qcom,max-current = <750>; @@ -317,7 +330,7 @@ pinctrl-1 = <&led_disable>; }; - pm2falcon_torch0: qcom,torch_0 { + pm660l_torch0: qcom,torch_0 { label = "torch"; qcom,led-name = "led:torch_0"; qcom,max-current = <500>; @@ -329,7 +342,7 @@ qcom,hdrm-vol-hi-lo-win-mv = <100>; }; - pm2falcon_torch1: qcom,torch_1 { + pm660l_torch1: qcom,torch_1 { label = "torch"; qcom,led-name = "led:torch_1"; qcom,max-current = <500>; @@ -341,7 +354,7 @@ qcom,hdrm-vol-hi-lo-win-mv = <100>; }; - pm2falcon_torch2: qcom,torch_2 { + pm660l_torch2: qcom,torch_2 { label = "torch"; qcom,led-name = "led:torch_2"; qcom,max-current = <500>; @@ -356,14 +369,14 @@ pinctrl-1 = <&led_disable>; }; - pm2falcon_switch0: qcom,led_switch_0 { + pm660l_switch0: qcom,led_switch_0 { label = "switch"; qcom,led-name = "led:switch_0"; qcom,led-mask = <3>; qcom,default-led-trigger = "switch0_trigger"; }; - pm2falcon_switch1: qcom,led_switch_1 { + pm660l_switch1: qcom,led_switch_1 { label = "switch"; qcom,led-name = "led:switch_1"; qcom,led-mask = <4>; @@ -371,7 +384,7 @@ }; }; - pm2falcon_lcdb: qpnp-lcdb@ec00 { + pm660l_lcdb: qpnp-lcdb@ec00 { compatible = "qcom,qpnp-lcdb-regulator"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi b/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi index 99f3f58cc20e..b1880c076e1c 100644 --- a/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -618,8 +618,8 @@ status = "disabled"; compatible = "qcom,qpnp-haptic"; reg = <0xc000 0x100>; - interrupts = <0x3 0xc0 0x0>, - <0x3 0xc0 0x1>; + interrupts = <0x3 0xc0 0x0 IRQ_TYPE_NONE>, + <0x3 0xc0 0x1 IRQ_TYPE_NONE>; interrupt-names = "sc-irq", "play-irq"; qcom,actuator-type = "lra"; qcom,play-mode = "direct"; diff --git a/arch/arm/boot/dts/qcom/msm8996-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/msm8996-mdss-panels.dtsi index e62c7fbcc1af..bfb85274846f 100644 --- a/arch/arm/boot/dts/qcom/msm8996-mdss-panels.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-mdss-panels.dtsi @@ -131,7 +131,7 @@ }; &dsi_nt35950_4k_dsc_cmd { - qcom,mdss-dsi-panel-timings-8996 = [21 1e 06 08 04 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [21 1e 06 08 04 03 04 a0 21 1e 06 08 04 03 04 a0 21 1e 06 08 04 03 04 a0 21 1e 06 08 04 03 04 a0 @@ -139,7 +139,7 @@ }; &dsi_sharp_4k_dsc_video { - qcom,mdss-dsi-panel-timings-8996 = [21 1e 06 08 04 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [21 1e 06 08 04 03 04 a0 21 1e 06 08 04 03 04 a0 21 1e 06 08 04 03 04 a0 21 1e 06 08 04 03 04 a0 @@ -147,7 +147,7 @@ }; &dsi_sharp_4k_dsc_cmd { - qcom,mdss-dsi-panel-timings-8996 = [21 1e 06 08 04 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [21 1e 06 08 04 03 04 a0 21 1e 06 08 04 03 04 a0 21 1e 06 08 04 03 04 a0 21 1e 06 08 04 03 04 a0 @@ -155,7 +155,7 @@ }; &dsi_dual_sharp_video { - qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [23 20 06 09 05 03 04 a0 23 20 06 09 05 03 04 a0 23 20 06 09 05 03 04 a0 23 20 06 09 05 03 04 a0 @@ -163,7 +163,7 @@ }; &dsi_dual_jdi_cmd { - qcom,mdss-dsi-panel-timings-8996 = [22 1e 06 08 04 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [22 1e 06 08 04 03 04 a0 22 1e 06 08 04 03 04 a0 22 1e 06 08 04 03 04 a0 22 1e 06 08 04 03 04 a0 @@ -173,7 +173,7 @@ }; &dsi_dual_jdi_video { - qcom,mdss-dsi-panel-timings-8996 = [22 1e 06 08 04 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [22 1e 06 08 04 03 04 a0 22 1e 06 08 04 03 04 a0 22 1e 06 08 04 03 04 a0 22 1e 06 08 04 03 04 a0 @@ -181,7 +181,7 @@ }; &dsi_dual_sharp_1080_120hz_cmd { - qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 @@ -189,7 +189,7 @@ }; &dsi_dual_nt35597_video { - qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 @@ -199,7 +199,7 @@ }; &dsi_dual_nt35597_cmd { - qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 @@ -209,7 +209,7 @@ }; &dsi_nt35597_dsc_video { - qcom,mdss-dsi-panel-timings-8996 = [20 1d 05 07 03 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [20 1d 05 07 03 03 04 a0 20 1d 05 07 03 03 04 a0 20 1d 05 07 03 03 04 a0 20 1d 05 07 03 03 04 a0 @@ -219,7 +219,7 @@ }; &dsi_nt35597_dsc_cmd { - qcom,mdss-dsi-panel-timings-8996 = [20 1d 05 07 03 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [20 1d 05 07 03 03 04 a0 20 1d 05 07 03 03 04 a0 20 1d 05 07 03 03 04 a0 20 1d 05 07 03 03 04 a0 @@ -229,7 +229,7 @@ }; &dsi_dual_jdi_4k_nofbc_video { - qcom,mdss-dsi-panel-timings-8996 = [ + qcom,mdss-dsi-panel-timings-phy-v2 = [ 2c 27 0e 10 0a 03 04 a0 2c 27 0e 10 0a 03 04 a0 2c 27 0e 10 0a 03 04 a0 @@ -238,14 +238,14 @@ }; &dsi_hx8379a_fwvga_truly_vid { - qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [23 20 06 09 05 03 04 a0 23 20 06 09 05 03 04 a0 23 20 06 09 05 03 04 a0 23 20 06 09 05 03 04 a0 23 2e 06 08 05 03 04 a0]; }; &dsi_r69007_wqxga_cmd { - qcom,mdss-dsi-panel-timings-8996 = [23 1f 07 09 05 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [23 1f 07 09 05 03 04 a0 23 1f 07 09 05 03 04 a0 23 1f 07 09 05 03 04 a0 23 1f 07 09 05 03 04 a0 @@ -253,7 +253,7 @@ }; &dsi_sharp_1080_cmd { - qcom,mdss-dsi-panel-timings-8996 = [23 1f 07 09 05 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [23 1f 07 09 05 03 04 a0 23 1f 07 09 05 03 04 a0 23 1f 07 09 05 03 04 a0 23 1f 07 09 05 03 04 a0 diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi index 2735cfb93be0..f69c388fbbef 100644 --- a/arch/arm/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996.dtsi @@ -3901,6 +3901,7 @@ clock-names = "core_clk"; clocks = <&clock_mmss clk_camss_cpp_clk>; parent-supply = <&gdsc_camss_top>; + qcom,support-hw-trigger; status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom/msm8998-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-cdp.dtsi index 61fc31a17e52..2cb08e1709a5 100644 --- a/arch/arm/boot/dts/qcom/msm8998-camera-sensor-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-cdp.dtsi @@ -254,6 +254,7 @@ qcom,csid-sd-index = <1>; qcom,mount-angle = <90>; qcom,eeprom-src = <&eeprom1>; + qcom,actuator-src = <&actuator1>; cam_vdig-supply = <&pm8998_lvs1>; cam_vio-supply = <&pm8998_lvs1>; cam_vana-supply = <&pmi8998_bob>; diff --git a/arch/arm/boot/dts/qcom/msm8998-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-mtp.dtsi index 0bd9ab40e8f1..0a41383ba874 100644 --- a/arch/arm/boot/dts/qcom/msm8998-camera-sensor-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-mtp.dtsi @@ -254,6 +254,7 @@ qcom,csid-sd-index = <1>; qcom,mount-angle = <90>; qcom,eeprom-src = <&eeprom1>; + qcom,actuator-src = <&actuator1>; cam_vdig-supply = <&pm8998_lvs1>; cam_vio-supply = <&pm8998_lvs1>; cam_vana-supply = <&pmi8998_bob>; diff --git a/arch/arm/boot/dts/qcom/msm8998-camera.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera.dtsi index 976750d6a26f..799455a0de2e 100644 --- a/arch/arm/boot/dts/qcom/msm8998-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera.dtsi @@ -574,9 +574,9 @@ 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9>; - vbif-entries = <3>; - vbif-regs = <0x124 0xac 0xd0>; - vbif-settings = <0x3 0x40 0x1010>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; ds-entries = <17>; ds-regs = <0x424 0x428 0x42c 0x430 0x434 0x438 0x43c 0x440 0x444 0x448 0x44c @@ -654,9 +654,9 @@ 0xaaa9aaa9 0xaaa9aaa9 0xaaa9aaa9>; - vbif-entries = <3>; - vbif-regs = <0x124 0xac 0xd0>; - vbif-settings = <0x3 0x40 0x1010>; + vbif-entries = <1>; + vbif-regs = <0x124>; + vbif-settings = <0x3>; ds-entries = <17>; ds-regs = <0x424 0x428 0x42c 0x430 0x434 0x438 0x43c 0x440 0x444 0x448 0x44c diff --git a/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi b/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi index 75a90b0499e1..4b81d2754255 100644 --- a/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi @@ -1132,6 +1132,8 @@ <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; + qcom,msr-fix-req; + port{ tpdm_qm_out_tpda: endpoint { remote-endpoint = <&tpda_in_tpdm_qm>; @@ -1151,6 +1153,8 @@ <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; + qcom,msr-fix-req; + port{ tpdm_pimem_out_tpda: endpoint { remote-endpoint = <&tpda_in_tpdm_pimem>; @@ -1205,6 +1209,8 @@ <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; + qcom,msr-fix-req; + port{ tpdm_apss_out_tpda_apss: endpoint { remote-endpoint = <&tpda_apss_in_tpdm_apss>; @@ -1259,6 +1265,8 @@ <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; + qcom,msr-fix-req; + port{ tpdm_mss_out_tpda_mss: endpoint { remote-endpoint = <&tpda_mss_in_tpdm_mss>; @@ -1453,6 +1461,8 @@ <&clock_gcc clk_qdss_a_clk>; clock-names = "core_clk", "core_a_clk"; + qcom,msr-fix-req; + port{ tpdm_spss_out_tpda_spss: endpoint { remote-endpoint = <&tpda_spss_in_tpdm_spss>; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi index 78ba56b3e3c2..52d0fdb4a523 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-cdp.dtsi @@ -45,18 +45,18 @@ led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>; - qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>; - qcom,switch-source = <&pm2falcon_switch0>; + qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>; + qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>; + qcom,switch-source = <&pm660l_switch0>; status = "ok"; }; led_flash1: qcom,camera-flash@1 { cell-index = <1>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash2>; - qcom,torch-source = <&pm2falcon_torch2>; - qcom,switch-source = <&pm2falcon_switch1>; + qcom,flash-source = <&pm660l_flash2>; + qcom,torch-source = <&pm660l_torch2>; + qcom,switch-source = <&pm660l_switch1>; status = "ok"; }; @@ -77,9 +77,9 @@ qcom,csid@ca30000 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -91,9 +91,9 @@ qcom,csid@ca30400 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -105,9 +105,9 @@ qcom,csid@ca30800 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -119,9 +119,9 @@ qcom,csid@ca30c00 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -195,9 +195,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -212,7 +212,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -240,9 +240,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -257,7 +257,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmfalcon_gpios 3 0>, + <&pm660_gpios 3 0>, <&tlmm 29 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -292,9 +292,9 @@ qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -307,7 +307,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -335,9 +335,9 @@ qcom,csiphy-sd-index = <1>; qcom,csid-sd-index = <2>; qcom,mount-angle = <90>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -350,7 +350,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 15 0>, <&tlmm 9 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -381,9 +381,9 @@ qcom,actuator-src = <&actuator1>; qcom,led-flash-src = <&led_flash1>; qcom,eeprom-src = <&eeprom2>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -396,7 +396,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -418,7 +418,7 @@ }; }; -&pm2falcon_gpios { +&pm660l_gpios { gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi index 78ba56b3e3c2..52d0fdb4a523 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-mtp.dtsi @@ -45,18 +45,18 @@ led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>; - qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>; - qcom,switch-source = <&pm2falcon_switch0>; + qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>; + qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>; + qcom,switch-source = <&pm660l_switch0>; status = "ok"; }; led_flash1: qcom,camera-flash@1 { cell-index = <1>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash2>; - qcom,torch-source = <&pm2falcon_torch2>; - qcom,switch-source = <&pm2falcon_switch1>; + qcom,flash-source = <&pm660l_flash2>; + qcom,torch-source = <&pm660l_torch2>; + qcom,switch-source = <&pm660l_switch1>; status = "ok"; }; @@ -77,9 +77,9 @@ qcom,csid@ca30000 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -91,9 +91,9 @@ qcom,csid@ca30400 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -105,9 +105,9 @@ qcom,csid@ca30800 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -119,9 +119,9 @@ qcom,csid@ca30c00 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -195,9 +195,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -212,7 +212,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -240,9 +240,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -257,7 +257,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmfalcon_gpios 3 0>, + <&pm660_gpios 3 0>, <&tlmm 29 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -292,9 +292,9 @@ qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -307,7 +307,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -335,9 +335,9 @@ qcom,csiphy-sd-index = <1>; qcom,csid-sd-index = <2>; qcom,mount-angle = <90>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -350,7 +350,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 15 0>, <&tlmm 9 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -381,9 +381,9 @@ qcom,actuator-src = <&actuator1>; qcom,led-flash-src = <&led_flash1>; qcom,eeprom-src = <&eeprom2>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -396,7 +396,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -418,7 +418,7 @@ }; }; -&pm2falcon_gpios { +&pm660l_gpios { gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi index d10c2a25b301..87b1146bd361 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-camera-sensor-qrd.dtsi @@ -115,9 +115,9 @@ qcom,csid@ca30000 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -129,9 +129,9 @@ qcom,csid@ca30400 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -143,9 +143,9 @@ qcom,csid@ca30800 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -157,9 +157,9 @@ qcom,csid@ca30c00 { qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -233,9 +233,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1750000 3300000 1352000>; qcom,cam-vreg-max-voltage = <1980000 3600000 1352000>; @@ -248,7 +248,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 9 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -273,9 +273,9 @@ cell-index = <1>; reg = <0x1>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1750000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1980000 3600000 1350000>; @@ -288,7 +288,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 15 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -316,9 +316,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 33000000 1352000>; qcom,cam-vreg-max-voltage = <1950000 36000000 1352000>; @@ -331,7 +331,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -362,9 +362,9 @@ qcom,actuator-src = <&actuator0>; /*qcom,ois-src = <&ois0>;*/ qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -377,7 +377,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 9 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -407,9 +407,9 @@ qcom,mount-angle = <90>; qcom,actuator-src = <&actuator1>; qcom,eeprom-src = <&eeprom1>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -422,7 +422,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 15 0>, <&tlmm 30 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -451,9 +451,9 @@ qcom,csid-sd-index = <2>; qcom,mount-angle = <270>; /*qcom,eeprom-src = <&eeprom2>;*/ - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -466,7 +466,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 8 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -488,7 +488,7 @@ }; }; -&pm2falcon_gpios { +&pm660l_gpios { gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-pm660.dtsi index 74f43c15dd72..a13475085e58 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-pm660.dtsi @@ -234,8 +234,14 @@ }; }; -#include "msm-pmfalcon.dtsi" -#include "msm-pm2falcon.dtsi" -#include "msm-pmfalcon-rpm-regulator.dtsi" -#include "msm-pm2falcon-rpm-regulator.dtsi" -#include "msmfalcon-regulator.dtsi" +#include "msm-pm660.dtsi" +#include "msm-pm660l.dtsi" +#include "msm-pm660-rpm-regulator.dtsi" +#include "msm-pm660l-rpm-regulator.dtsi" +#include "sdm660-regulator.dtsi" + +&soc { + /* remove sdm660 MMSS CPR Controller node */ + /delete-node/cpr4-ctrl@05061000; + /delete-node/regulator@01fcf004; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-audio.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-audio.dtsi index b05707c6c585..c117bdbf5578 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-audio.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-audio.dtsi @@ -11,9 +11,9 @@ */ #include "msm-audio.dtsi" -#include "msmfalcon-audio.dtsi" +#include "sdm660-audio.dtsi" -&pm2falcon_3 { +&pm660l_3 { /delete-node/analog-codec; }; @@ -43,7 +43,7 @@ }; &clock_audio { - qcom,audio-ref-clk-gpio = <&pmfalcon_gpios 3 0>; + qcom,audio-ref-clk-gpio = <&pm660_gpios 3 0>; clocks = <&clock_gcc clk_div_clk1>; pinctrl-0 = <&spkr_i2s_clk_sleep>; pinctrl-1 = <&spkr_i2s_clk_active>; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi index 292bc07c679a..4bf3dc08ab3e 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-cdp.dtsi @@ -18,9 +18,9 @@ }; &ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l1>; - vddp-ref-clk-supply = <&pmfalcon_l1>; + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l1>; + vddp-ref-clk-supply = <&pm660_l1>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; @@ -31,8 +31,8 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; vcc-max-microamp = <500000>; vccq2-max-microamp = <600000>; status = "ok"; @@ -43,11 +43,11 @@ }; &sdhc_2 { - vdd-supply = <&pm2falcon_l5>; + vdd-supply = <&pm660l_l5>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pm2falcon_l2>; + vdd-io-supply = <&pm660l_l2>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 22000>; @@ -185,13 +185,13 @@ &mdss_dsi { hw-config = "split_dsi"; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; }; &mdss_dsi0 { qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; + wqhd-vddio-supply = <&pm660_l11>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; pinctrl-names = "mdss_default", "mdss_sleep"; @@ -204,7 +204,7 @@ &mdss_dsi1 { qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; + wqhd-vddio-supply = <&pm660_l11>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; pinctrl-names = "mdss_default", "mdss_sleep"; @@ -342,8 +342,8 @@ }; &mdss_dp_ctrl { - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>; pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi index 9a1e148c46a0..a9306475e24e 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660-mtp.dtsi @@ -19,9 +19,9 @@ }; &ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l1>; - vddp-ref-clk-supply = <&pmfalcon_l1>; + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l1>; + vddp-ref-clk-supply = <&pm660_l1>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; @@ -32,8 +32,8 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; vcc-max-microamp = <500000>; vccq2-max-microamp = <600000>; status = "ok"; @@ -44,11 +44,11 @@ }; &sdhc_2 { - vdd-supply = <&pm2falcon_l5>; + vdd-supply = <&pm660l_l5>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pm2falcon_l2>; + vdd-io-supply = <&pm660l_l2>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 22000>; @@ -196,8 +196,8 @@ }; &mdss_dp_ctrl { - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>; pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>; @@ -212,13 +212,13 @@ &mdss_dsi { hw-config = "split_dsi"; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; }; &mdss_dsi0 { qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; + wqhd-vddio-supply = <&pm660_l11>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; pinctrl-names = "mdss_default", "mdss_sleep"; @@ -231,7 +231,7 @@ &mdss_dsi1 { qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; + wqhd-vddio-supply = <&pm660_l11>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; pinctrl-names = "mdss_default", "mdss_sleep"; diff --git a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660.dtsi index 347b924749fd..cfb71e3b1cb3 100644 --- a/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-sdm660.dtsi @@ -343,10 +343,10 @@ bluetooth: bt_wcn3990 { compatible = "qca,wcn3990"; - qca,bt-vdd-core-supply = <&pmfalcon_l9_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmfalcon_l6_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmfalcon_l19_pin_ctrl>; - qca,bt-chip-pwd-supply = <&pm2falcon_bob_pin1>; + qca,bt-vdd-core-supply = <&pm660_l9_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pm660_l6_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pm660_l19_pin_ctrl>; + qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>; clocks = <&clock_gcc clk_rf_clk1>; clock-names = "rf_clk1"; @@ -1872,7 +1872,7 @@ <61 512 240000 800000>; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; - extcon = <&pmfalcon_pdphy>; + extcon = <&pm660_pdphy>; clocks = <&clock_gcc clk_gcc_usb30_master_clk>, <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>, @@ -1940,9 +1940,9 @@ <0x01fcb24c 0x4>; reg-names = "qusb_phy_base", "tcsr_clamp_dig_n_1p8"; - vdd-supply = <&pm2falcon_l1>; - vdda18-supply = <&pm2falcon_l10>; - vdda33-supply = <&pm2falcon_l7>; + vdd-supply = <&pm660l_l1>; + vdda18-supply = <&pm660l_l10>; + vdda33-supply = <&pm660l_l7>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,qusb-phy-init-seq = /* <value reg_offset> */ @@ -1970,8 +1970,8 @@ reg-names = "qmp_phy_base", "vls_clamp_reg", "tcsr_usb3_dp_phymode"; - vdd-supply = <&pm2falcon_l1>; - core-supply = <&pmfalcon_l1>; + vdd-supply = <&pm660l_l1>; + core-supply = <&pm660_l1>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,vbus-valid-override; qcom,qmp-phy-init-seq = @@ -2140,7 +2140,7 @@ reg = <0x17300000 0x00100>; interrupts = <0 162 1>; - vdd_cx-supply = <&pm2falcon_s3_level>; + vdd_cx-supply = <&pm660l_s3_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; @@ -2195,9 +2195,9 @@ "mnoc_axi_clk"; interrupts = <0 448 1>; - vdd_cx-supply = <&pm2falcon_s3_level>; + vdd_cx-supply = <&pm660l_s3_level>; vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - vdd_mx-supply = <&pm2falcon_s5_level>; + vdd_mx-supply = <&pm660l_s5_level>; vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; qcom,firmware-name = "modem"; qcom,pil-self-auth; @@ -2606,7 +2606,7 @@ reg = <0x5c00000 0x4000>; interrupts = <0 390 1>; - vdd_cx-supply = <&pm2falcon_l9_level>; + vdd_cx-supply = <&pm660l_l9_level>; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 0>; qcom,proxy-reg-names = "vdd_cx"; qcom,keep-proxy-regs-on; @@ -2908,8 +2908,8 @@ <0 424 0 /* CE10 */ >, <0 425 0 /* CE11 */ >; qcom,wlan-msa-memory = <0x100000>; - qcom,icnss-vadc = <&pmfalcon_vadc>; - qcom,icnss-adc_tm = <&pmfalcon_adc_tm>; + qcom,icnss-vadc = <&pm660_vadc>; + qcom,icnss-adc_tm = <&pm660_adc_tm>; }; tspp: msm_tspp@0c1e7000 { @@ -3067,6 +3067,7 @@ &gdsc_cpp { parent-supply = <&gdsc_camss_top>; + qcom,support-hw-trigger; status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom/msm8998-mdss.dtsi b/arch/arm/boot/dts/qcom/msm8998-mdss.dtsi index dd2efefe264f..845c96eb5ef4 100644 --- a/arch/arm/boot/dts/qcom/msm8998-mdss.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-mdss.dtsi @@ -170,6 +170,9 @@ <0x4a000 0x4a2bc>, <0x55000 0x5522c>, <0x57000 0x5722c>, + <0x61000 0x61014>, + <0x61800 0x61888>, + <0x62000 0x62088>, <0x66000 0x662c0>, <0x6b000 0x6b268>, <0x6b800 0x6ba68>, @@ -191,6 +194,7 @@ "LAYER_0", "LAYER_1", "LAYER_2", "LAYER_3", "LAYER_4", "LAYER_5", "DSPP_0", "DSPP_1", + "DEST_SCALER_OP", "DEST_SCALER_0", "DEST_SCALER_1", "WB_2", "INTF_0", "INTF_1", "INTF_2", "INTF_3", "PP_0", "PP_1", "PP_4", diff --git a/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi index 7c3bb4101de7..068fd0901ca5 100644 --- a/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi @@ -700,13 +700,13 @@ spi_4_active: spi_4_active { mux { pins = "gpio8", "gpio9", - "gpio10", "gpio1"; + "gpio10", "gpio11"; function = "blsp_spi4"; }; config { pins = "gpio8", "gpio9", - "gpio10", "gpio1"; + "gpio10", "gpio11"; drive-strength = <6>; bias-disable; }; @@ -715,13 +715,13 @@ spi_4_sleep: spi_4_sleep { mux { pins = "gpio8", "gpio9", - "gpio10", "gpio1"; + "gpio10", "gpio11"; function = "blsp_spi4"; }; config { pins = "gpio8", "gpio9", - "gpio10", "gpio1"; + "gpio10", "gpio11"; drive-strength = <6>; bias-disable; }; @@ -758,8 +758,8 @@ spi_5 { spi_5_active: spi_5_active { mux { - pins = "gpio0", "gpio", - "gpio2", "gpio3"; + pins = "gpio85", "gpio86", + "gpio87", "gpio88"; function = "blsp_spi5"; }; diff --git a/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi b/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi index 07a0e6e6d5ad..420f78b442b9 100644 --- a/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -457,3 +457,7 @@ &blue_led { /delete-property/ linux,default-trigger; }; + +&wil6210 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2-interposer-sdm660.dtsi index dc548f8f499b..4edcd964f0b3 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2-interposer-sdm660.dtsi @@ -16,7 +16,7 @@ * msm8998.dtsi file. */ -#include "msm8998-interposer-msmfalcon.dtsi" +#include "msm8998-interposer-sdm660.dtsi" #include "msm8998-v2-camera.dtsi" / { diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-cdp.dts index 5ea248f6f2dc..6884397bf0ba 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-cdp.dts @@ -13,41 +13,41 @@ /dts-v1/; -#include "msm8998-v2.1-interposer-msmfalcon.dtsi" -#include "msm8998-interposer-msmfalcon-cdp.dtsi" -#include "msm8998-interposer-pmfalcon.dtsi" -#include "msm8998-interposer-msmfalcon-audio.dtsi" +#include "msm8998-v2.1-interposer-sdm660.dtsi" +#include "msm8998-interposer-sdm660-cdp.dtsi" +#include "msm8998-interposer-pm660.dtsi" +#include "msm8998-interposer-sdm660-audio.dtsi" #include "msm8998-interposer-camera-sensor-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer CDP"; + model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 SDM 660 Interposer CDP"; compatible = "qcom,msm8998-cdp", "qcom,msm8998", "qcom,cdp"; qcom,board-id = <1 1>; }; -&pmfalcon_charger { +&pm660_charger { qcom,batteryless-platform; }; &clock_gcc { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; + vdd_dig-supply = <&pm660l_s3_level>; + vdd_dig_ao-supply = <&pm660l_s3_level_ao>; }; &clock_mmss { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>; + vdd_dig-supply = <&pm660l_s3_level>; + vdd_mmsscc_mx-supply = <&pm660l_s5_level>; }; &clock_gpu { - vdd_dig-supply = <&pm2falcon_s3_level>; + vdd_dig-supply = <&pm660l_s3_level>; }; &clock_gfx { /* GFX Rail = CX */ - vdd_gpucc-supply = <&pm2falcon_s3_level>; - vdd_mx-supply = <&pm2falcon_s5_level>; - vdd_gpu_mx-supply = <&pm2falcon_s5_level>; + vdd_gpucc-supply = <&pm660l_s3_level>; + vdd_mx-supply = <&pm660l_s5_level>; + vdd_gpu_mx-supply = <&pm660l_s5_level>; qcom,gfxfreq-speedbin0 = < 0 0 0 >, < 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS @@ -83,31 +83,31 @@ clocks = <&clock_gfx clk_gfx3d_clk_src>; qcom,force-enable-root-clk; /* GFX Rail = CX */ - parent-supply = <&pm2falcon_s3_level>; + parent-supply = <&pm660l_s3_level>; status = "ok"; }; &usb3 { - extcon = <&pmfalcon_pdphy>; + extcon = <&pm660_pdphy>; }; &qusb_phy0 { - vdd-supply = <&pm2falcon_l1>; - vdda18-supply = <&pmfalcon_l10>; + vdd-supply = <&pm660l_l1>; + vdda18-supply = <&pm660_l10>; qcom,vdd-voltage-level = <0 925000 925000>; - vdda33-supply = <&pm2falcon_l7>; + vdda33-supply = <&pm660l_l7>; }; &ssphy { - vdd-supply = <&pm2falcon_l1>; + vdd-supply = <&pm660l_l1>; qcom,vdd-voltage-level = <0 925000 925000>; - core-supply = <&pmfalcon_l1>; + core-supply = <&pm660_l1>; }; &mdss_dsi { hw-config = "split_dsi"; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; qcom,ctrl-supply-entries { qcom,ctrl-supply-entry@0 { @@ -126,7 +126,7 @@ &mdss_dsi0 { qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; + wqhd-vddio-supply = <&pm660_l11>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; pinctrl-names = "mdss_default", "mdss_sleep"; @@ -139,7 +139,7 @@ &mdss_dsi1 { qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; + wqhd-vddio-supply = <&pm660_l11>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; pinctrl-names = "mdss_default", "mdss_sleep"; @@ -150,6 +150,6 @@ qcom,panel-mode-gpio = <&tlmm 91 0>; }; -&pm2falcon_wled { +&pm660l_wled { qcom,led-strings-list = [01 02]; }; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-mtp.dts index 7c0c53033a44..2e5de95de0c5 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-mtp.dts @@ -13,41 +13,41 @@ /dts-v1/; -#include "msm8998-v2.1-interposer-msmfalcon.dtsi" -#include "msm8998-interposer-msmfalcon-mtp.dtsi" -#include "msm8998-interposer-pmfalcon.dtsi" -#include "msm8998-interposer-msmfalcon-audio.dtsi" +#include "msm8998-v2.1-interposer-sdm660.dtsi" +#include "msm8998-interposer-sdm660-mtp.dtsi" +#include "msm8998-interposer-pm660.dtsi" +#include "msm8998-interposer-sdm660-audio.dtsi" #include "msm8998-interposer-camera-sensor-mtp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer MTP"; + model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 SDM 660 Interposer MTP"; compatible = "qcom,msm8998-mtp", "qcom,msm8998", "qcom,mtp"; qcom,board-id = <8 2>; }; -&pmfalcon_fg { +&pm660_fg { qcom,battery-data = <&mtp_batterydata>; }; &clock_gcc { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; + vdd_dig-supply = <&pm660l_s3_level>; + vdd_dig_ao-supply = <&pm660l_s3_level_ao>; }; &clock_mmss { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>; + vdd_dig-supply = <&pm660l_s3_level>; + vdd_mmsscc_mx-supply = <&pm660l_s5_level>; }; &clock_gpu { - vdd_dig-supply = <&pm2falcon_s3_level>; + vdd_dig-supply = <&pm660l_s3_level>; }; &clock_gfx { /* GFX Rail = CX */ - vdd_gpucc-supply = <&pm2falcon_s3_level>; - vdd_mx-supply = <&pm2falcon_s5_level>; - vdd_gpu_mx-supply = <&pm2falcon_s5_level>; + vdd_gpucc-supply = <&pm660l_s3_level>; + vdd_mx-supply = <&pm660l_s5_level>; + vdd_gpu_mx-supply = <&pm660l_s5_level>; qcom,gfxfreq-speedbin0 = < 0 0 0 >, < 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS @@ -83,14 +83,14 @@ clocks = <&clock_gfx clk_gfx3d_clk_src>; qcom,force-enable-root-clk; /* GFX Rail = CX */ - parent-supply = <&pm2falcon_s3_level>; + parent-supply = <&pm660l_s3_level>; status = "ok"; }; &mdss_dsi { hw-config = "split_dsi"; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; qcom,ctrl-supply-entries { qcom,ctrl-supply-entry@0 { @@ -109,7 +109,7 @@ &mdss_dsi0 { qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; + wqhd-vddio-supply = <&pm660_l11>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; pinctrl-names = "mdss_default", "mdss_sleep"; @@ -122,7 +122,7 @@ &mdss_dsi1 { qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>; - wqhd-vddio-supply = <&pmfalcon_l11>; + wqhd-vddio-supply = <&pm660_l11>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; pinctrl-names = "mdss_default", "mdss_sleep"; @@ -134,23 +134,23 @@ }; &usb3 { - extcon = <&pmfalcon_pdphy>; + extcon = <&pm660_pdphy>; }; &qusb_phy0 { - vdd-supply = <&pm2falcon_l1>; - vdda18-supply = <&pmfalcon_l10>; + vdd-supply = <&pm660l_l1>; + vdda18-supply = <&pm660_l10>; qcom,vdd-voltage-level = <0 925000 925000>; - vdda33-supply = <&pm2falcon_l7>; + vdda33-supply = <&pm660l_l7>; }; &ssphy { - vdd-supply = <&pm2falcon_l1>; + vdd-supply = <&pm660l_l1>; qcom,vdd-voltage-level = <0 925000 925000>; - core-supply = <&pmfalcon_l1>; + core-supply = <&pm660_l1>; }; -&pm2falcon_gpios { +&pm660l_gpios { /* GPIO 7 for VOL_UP */ gpio@c600 { status = "okay"; @@ -170,7 +170,7 @@ vol_up { label = "volume_up"; - gpios = <&pm2falcon_gpios 7 0x1>; + gpios = <&pm660l_gpios 7 0x1>; linux,input-type = <1>; linux,code = <115>; gpio-key,wakeup; @@ -179,6 +179,6 @@ }; }; -&pm2falcon_wled { +&pm660l_wled { qcom,led-strings-list = [01 02]; }; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dts index 3de548ed1446..9957adcc2336 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dts @@ -13,14 +13,14 @@ /dts-v1/; -#include "msm8998-v2.1-interposer-msmfalcon-qrd.dtsi" -#include "msm8998-interposer-pmfalcon.dtsi" -#include "msm8998-interposer-msmfalcon-audio.dtsi" +#include "msm8998-v2.1-interposer-sdm660-qrd.dtsi" +#include "msm8998-interposer-pm660.dtsi" +#include "msm8998-interposer-sdm660-audio.dtsi" #include "msm8998-interposer-camera-sensor-qrd.dtsi" / { model = - "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer QRD"; + "Qualcomm Technologies, Inc. MSM 8998 v2.1 SDM 660 Interposer QRD"; compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd"; qcom,board-id = <0x03000b 0x80>; }; @@ -44,24 +44,24 @@ }; &clock_gcc { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; + vdd_dig-supply = <&pm660l_s3_level>; + vdd_dig_ao-supply = <&pm660l_s3_level_ao>; }; &clock_mmss { - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_mmsscc_mx-supply = <&pm2falcon_s5_level>; + vdd_dig-supply = <&pm660l_s3_level>; + vdd_mmsscc_mx-supply = <&pm660l_s5_level>; }; &clock_gpu { - vdd_dig-supply = <&pm2falcon_s3_level>; + vdd_dig-supply = <&pm660l_s3_level>; }; &clock_gfx { /* GFX Rail = CX */ - vdd_gpucc-supply = <&pm2falcon_s3_level>; - vdd_mx-supply = <&pm2falcon_s5_level>; - vdd_gpu_mx-supply = <&pm2falcon_s5_level>; + vdd_gpucc-supply = <&pm660l_s3_level>; + vdd_mx-supply = <&pm660l_s5_level>; + vdd_gpu_mx-supply = <&pm660l_s5_level>; qcom,gfxfreq-speedbin0 = < 0 0 0 >, < 180000000 RPM_SMD_REGULATOR_LEVEL_MIN_SVS @@ -97,33 +97,33 @@ clocks = <&clock_gfx clk_gfx3d_clk_src>; qcom,force-enable-root-clk; /* GFX Rail = CX */ - parent-supply = <&pm2falcon_s3_level>; + parent-supply = <&pm660l_s3_level>; status = "ok"; }; &usb3 { - extcon = <&pmfalcon_pdphy>; + extcon = <&pm660_pdphy>; }; &qusb_phy0 { - vdd-supply = <&pm2falcon_l1>; - vdda18-supply = <&pmfalcon_l10>; + vdd-supply = <&pm660l_l1>; + vdda18-supply = <&pm660_l10>; qcom,vdd-voltage-level = <0 925000 925000>; - vdda33-supply = <&pm2falcon_l7>; + vdda33-supply = <&pm660l_l7>; }; &ssphy { - vdd-supply = <&pm2falcon_l1>; + vdd-supply = <&pm660l_l1>; qcom,vdd-voltage-level = <0 925000 925000>; - core-supply = <&pmfalcon_l1>; + core-supply = <&pm660_l1>; }; &sdhc_2 { - vdd-supply = <&pm2falcon_l5>; - vdd-io-supply = <&pm2falcon_l2>; + vdd-supply = <&pm660l_l5>; + vdd-io-supply = <&pm660l_l2>; }; -&pm2falcon_gpios { +&pm660l_gpios { /* GPIO 7 for VOL_UP */ gpio@c600 { status = "ok"; @@ -143,7 +143,7 @@ vol_up { label = "volume_up"; - gpios = <&pm2falcon_gpios 7 0x1>; + gpios = <&pm660l_gpios 7 0x1>; linux,input-type = <1>; linux,code = <115>; gpio-key,wakeup; @@ -160,10 +160,10 @@ }; }; -&pmfalcon_fg { +&pm660_fg { qcom,battery-data = <&qrd_batterydata>; }; -&pm2falcon_wled { +&pm660l_wled { qcom,led-strings-list = [00 01]; }; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dtsi index 9740e9c1b168..5a882c7eb27f 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660-qrd.dtsi @@ -11,16 +11,16 @@ */ #include <dt-bindings/interrupt-controller/irq.h> -#include "msm8998-v2.1-interposer-msmfalcon.dtsi" +#include "msm8998-v2.1-interposer-sdm660.dtsi" #include "msm8998-camera-sensor-mtp.dtsi" / { bluetooth: bt_wcn3990 { compatible = "qca,wcn3990"; - qca,bt-vdd-core-supply = <&pmfalcon_l9_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmfalcon_l6_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmfalcon_l19_pin_ctrl>; - qca,bt-chip-pwd-supply = <&pm2falcon_bob_pin1>; + qca,bt-vdd-core-supply = <&pm660_l9_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pm660_l6_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pm660_l19_pin_ctrl>; + qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>; clocks = <&clock_gcc clk_rf_clk1>; clock-names = "rf_clk1"; @@ -46,9 +46,9 @@ }; &ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l1>; - vddp-ref-clk-supply = <&pmfalcon_l1>; + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l1>; + vddp-ref-clk-supply = <&pm660_l1>; vdda-phy-max-uv = <925000>; vdda-phy-min-uv = <800000>; vdda-phy-max-microamp = <51400>; @@ -61,8 +61,8 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; vcc-max-microamp = <500000>; vccq2-max-microamp = <600000>; status = "ok"; @@ -73,11 +73,11 @@ }; &sdhc_2 { - vdd-supply = <&pm2falcon_l5>; + vdd-supply = <&pm660l_l5>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pm2falcon_l2>; + vdd-io-supply = <&pm660l_l2>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 22000>; @@ -102,8 +102,8 @@ reg = <0x20>; interrupt-parent = <&tlmm>; interrupts = <125 0x2008>; - avdd-supply = <&pm2falcon_l3>; - vdd-supply = <&pmfalcon_l11>; + avdd-supply = <&pm660l_l3>; + vdd-supply = <&pm660_l11>; synaptics,vdd-voltage = <1880000 1880000>; synaptics,avdd-voltage = <3000000 3008000>; synaptics,vdd-current = <40000>; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660.dtsi index c2a393bd019d..8adbff55fead 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-sdm660.dtsi @@ -10,7 +10,7 @@ * GNU General Public License for more details. */ -#include "msm8998-v2-interposer-msmfalcon.dtsi" +#include "msm8998-v2-interposer-sdm660.dtsi" / { model = "Qualcomm Technologies, Inc. MSM8998 v2.1"; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.dtsi index 99975877658d..fa7cdd5194a3 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016 The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -298,6 +298,7 @@ &devfreq_memlat_0 { qcom,core-dev-table = + < 300000 1525 >, < 595200 3143 >, < 1324800 4173 >, < 1555200 5859 >, diff --git a/arch/arm/boot/dts/qcom/msm8998.dtsi b/arch/arm/boot/dts/qcom/msm8998.dtsi index ab835bf3aba1..6a11e7c51ca5 100644 --- a/arch/arm/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998.dtsi @@ -1487,10 +1487,11 @@ spss_utils: qcom,spss_utils { compatible = "qcom,spss-utils"; /* spss test fuse physical address */ - qcom,spss-fuse-addr = <0x007841c4 0x4>; + qcom,spss-fuse-addr = <0x007841c4>; qcom,spss-fuse-bit = <27>; qcom,spss-test-firmware-name = "spss"; /* default name */ qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ + qcom,spss-debug-reg-addr = <0x01d06020>; status = "ok"; }; @@ -3152,6 +3153,7 @@ &gdsc_cpp { parent-supply = <&gdsc_camss_top>; + qcom,support-hw-trigger; status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi deleted file mode 100644 index 02e61bcdd95c..000000000000 --- a/arch/arm/boot/dts/qcom/msmfalcon-regulator.dtsi +++ /dev/null @@ -1,498 +0,0 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -&rpm_bus { - rpm-regulator-smpa4 { - status = "okay"; - pmfalcon_s4: regulator-s4 { - regulator-min-microvolt = <1805000>; - regulator-max-microvolt = <2040000>; - status = "okay"; - }; - }; - - rpm-regulator-smpa5 { - status = "okay"; - pmfalcon_s5: regulator-s5 { - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - status = "okay"; - }; - }; - - rpm-regulator-smpa6 { - status = "okay"; - pmfalcon_s6: regulator-s6 { - regulator-min-microvolt = <504000>; - regulator-max-microvolt = <992000>; - status = "okay"; - }; - }; - - rpm-regulator-smpb1 { - status = "okay"; - pm2falcon_s1: regulator-s1 { - regulator-min-microvolt = <1125000>; - regulator-max-microvolt = <1125000>; - status = "okay"; - }; - }; - - rpm-regulator-smpb2 { - status = "okay"; - pm2falcon_s2: regulator-s2 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - status = "okay"; - }; - }; - - /* PM2FALCON S3 + S4 - VDD_CX supply */ - rpm-regulator-smpb3 { - status = "okay"; - pm2falcon_s3_level: regulator-s3-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_level"; - qcom,set = <3>; - regulator-min-microvolt = - <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = - <RPM_SMD_REGULATOR_LEVEL_TURBO>; - qcom,use-voltage-level; - }; - - pm2falcon_s3_floor_level: regulator-s3-floor-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_floor_level"; - qcom,set = <3>; - regulator-min-microvolt = - <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = - <RPM_SMD_REGULATOR_LEVEL_TURBO>; - qcom,use-voltage-floor-level; - qcom,always-send-voltage; - }; - - pm2falcon_s3_level_ao: regulator-s3-level-ao { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_level_ao"; - qcom,set = <1>; - regulator-min-microvolt = - <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = - <RPM_SMD_REGULATOR_LEVEL_TURBO>; - qcom,use-voltage-level; - }; - }; - - /* PM2FALCON S5 - VDD_MX supply */ - rpm-regulator-smpb5 { - status = "okay"; - pm2falcon_s5_level: regulator-s5-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_level"; - qcom,set = <3>; - regulator-min-microvolt = - <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = - <RPM_SMD_REGULATOR_LEVEL_TURBO>; - qcom,use-voltage-level; - }; - - pm2falcon_s5_floor_level: regulator-s5-floor-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_floor_level"; - qcom,set = <3>; - regulator-min-microvolt = - <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = - <RPM_SMD_REGULATOR_LEVEL_TURBO>; - qcom,use-voltage-floor-level; - qcom,always-send-voltage; - }; - - pm2falcon_s5_level_ao: regulator-s5-level-ao { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_level_ao"; - qcom,set = <1>; - regulator-min-microvolt = - <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = - <RPM_SMD_REGULATOR_LEVEL_TURBO>; - qcom,use-voltage-level; - }; - }; - - rpm-regulator-ldoa1 { - status = "okay"; - pmfalcon_l1: regulator-l1 { - regulator-min-microvolt = <1150000>; - regulator-max-microvolt = <1250000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa2 { - status = "okay"; - pmfalcon_l2: regulator-l2 { - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1010000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa3 { - status = "okay"; - pmfalcon_l3: regulator-l3 { - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1010000>; - status = "okay"; - }; - }; - - /* TODO: remove if ADRASTEA CX/MX not voted from APPS */ - rpm-regulator-ldoa5 { - status = "okay"; - pmfalcon_l5: regulator-l5 { - regulator-min-microvolt = <525000>; - regulator-max-microvolt = <950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa6 { - status = "okay"; - pmfalcon_l6: regulator-l6 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1370000>; - status = "okay"; - }; - - pmfalcon_l6_pin_ctrl: regulator-l6-pin-ctrl { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l6_pin_ctrl"; - qcom,set = <3>; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1370000>; - /* Force NPM follows HW_EN1 */ - qcom,init-pin-ctrl-mode = <2>; - /* Enable follows HW_EN1 */ - qcom,enable-with-pin-ctrl = <0 2>; - }; - }; - - rpm-regulator-ldoa7 { - status = "okay"; - pmfalcon_l7: regulator-l7 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa8 { - status = "okay"; - pmfalcon_l8: regulator-l8 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1900000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa9 { - status = "okay"; - pmfalcon_l9: regulator-l9 { - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1900000>; - status = "okay"; - }; - - pmfalcon_l9_pin_ctrl: regulator-l9-pin-ctrl { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l9_pin_ctrl"; - qcom,set = <3>; - regulator-min-microvolt = <1750000>; - regulator-max-microvolt = <1900000>; - /* Force NPM follows HW_EN1 */ - qcom,init-pin-ctrl-mode = <2>; - /* Enable follows HW_EN1 */ - qcom,enable-with-pin-ctrl = <0 2>; - }; - }; - - rpm-regulator-ldoa10 { - status = "okay"; - pmfalcon_l10: regulator-l10 { - regulator-min-microvolt = <1780000>; - regulator-max-microvolt = <1950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa11 { - status = "okay"; - pmfalcon_l11: regulator-l11 { - regulator-min-microvolt = <1780000>; - regulator-max-microvolt = <1950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa12 { - status = "okay"; - pmfalcon_l12: regulator-l12 { - regulator-min-microvolt = <1780000>; - regulator-max-microvolt = <1950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa13 { - status = "okay"; - pmfalcon_l13: regulator-l13 { - regulator-min-microvolt = <1780000>; - regulator-max-microvolt = <1950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa14 { - status = "okay"; - pmfalcon_l14: regulator-l14 { - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1900000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa15 { - status = "okay"; - pmfalcon_l15: regulator-l15 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa17 { - status = "okay"; - pmfalcon_l17: regulator-l17 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldoa19 { - status = "okay"; - pmfalcon_l19: regulator-l19 { - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; - status = "okay"; - }; - - pmfalcon_l19_pin_ctrl: regulator-l19-pin-ctrl { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l19_pin_ctrl"; - qcom,set = <3>; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; - /* Force NPM follows HW_EN1 */ - qcom,init-pin-ctrl-mode = <2>; - /* Enable follows HW_EN1 */ - qcom,enable-with-pin-ctrl = <0 2>; - }; - }; - - rpm-regulator-ldob1 { - status = "okay"; - pm2falcon_l1: regulator-l1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <925000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob2 { - status = "okay"; - pm2falcon_l2: regulator-l2 { - regulator-min-microvolt = <350000>; - regulator-max-microvolt = <3100000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob3 { - status = "okay"; - pm2falcon_l3: regulator-l3 { - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <3600000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob4 { - status = "okay"; - pm2falcon_l4: regulator-l4 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <2950000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob5 { - status = "okay"; - pm2falcon_l5: regulator-l5 { - regulator-min-microvolt = <1721000>; - regulator-max-microvolt = <3600000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob6 { - status = "okay"; - pm2falcon_l6: regulator-l6 { - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <3300000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob7 { - status = "okay"; - pm2falcon_l7: regulator-l7 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3125000>; - status = "okay"; - }; - }; - - rpm-regulator-ldob8 { - status = "okay"; - pm2falcon_l8: regulator-l8 { - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; - status = "okay"; - }; - }; - - /* PM2FALCON L9 = VDD_SSC_CX supply */ - rpm-regulator-ldob9 { - status = "okay"; - pm2falcon_l9_level: regulator-l9-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l9_level"; - qcom,set = <3>; - regulator-min-microvolt = - <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = - <RPM_SMD_REGULATOR_LEVEL_TURBO>; - qcom,use-voltage-level; - }; - - pm2falcon_l9_floor_level: regulator-l9-floor-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l9_floor_level"; - qcom,set = <3>; - regulator-min-microvolt = - <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = - <RPM_SMD_REGULATOR_LEVEL_TURBO>; - qcom,use-voltage-floor-level; - qcom,always-send-voltage; - }; - }; - - /* PM2FALCON L10 = VDD_SSC_MX supply */ - rpm-regulator-ldob10 { - status = "okay"; - pm2falcon_l10_level: regulator-l10-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l10_level"; - qcom,set = <3>; - regulator-min-microvolt = - <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = - <RPM_SMD_REGULATOR_LEVEL_TURBO>; - qcom,use-voltage-level; - }; - - pm2falcon_l10_floor_level: regulator-l10-floor-level { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l10_floor_level"; - qcom,set = <3>; - regulator-min-microvolt = - <RPM_SMD_REGULATOR_LEVEL_RETENTION>; - regulator-max-microvolt = - <RPM_SMD_REGULATOR_LEVEL_TURBO>; - qcom,use-voltage-floor-level; - qcom,always-send-voltage; - }; - }; - - rpm-regulator-bobb { - status = "okay"; - pm2falcon_bob: regulator-bob { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - status = "okay"; - }; - - pm2falcon_bob_pin1: regulator-bob-pin1 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin1"; - qcom,set = <3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - qcom,use-pin-ctrl-voltage1; - }; - - pm2falcon_bob_pin2: regulator-bob-pin2 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin2"; - qcom,set = <3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - qcom,use-pin-ctrl-voltage2; - }; - - pm2falcon_bob_pin3: regulator-bob-pin3 { - compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin3"; - qcom,set = <3>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3600000>; - qcom,use-pin-ctrl-voltage3; - }; - }; -}; - -&pmfalcon_charger { - smb2_vbus: qcom,smb2-vbus { - regulator-name = "smb2-vbus"; - }; - - smb2_vconn: qcom,smb2-vconn { - regulator-name = "smb2-vconn"; - }; -}; - -/* Stub regulators */ -/ { - /* GFX Supply */ - gfx_vreg_corner: regulator-gfx-corner { - compatible = "qcom,stub-regulator"; - regulator-name = "gfx_corner"; - regulator-min-microvolt = <1>; - regulator-max-microvolt = <7>; - }; -}; diff --git a/arch/arm/boot/dts/qcom/sda630-cdp.dts b/arch/arm/boot/dts/qcom/sda630-cdp.dts new file mode 100644 index 000000000000..8db5a9e76126 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda630-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda630.dtsi" +#include "sdm630-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 630 PM660 + PM660L CDP"; + compatible = "qcom,sda630-cdp", "qcom,sda630", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda630-mtp.dts b/arch/arm/boot/dts/qcom/sda630-mtp.dts new file mode 100644 index 000000000000..5c4372600ad7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda630-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda630.dtsi" +#include "sdm630-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 630 PM660 + PM660L MTP"; + compatible = "qcom,sda630-mtp", "qcom,sda630", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda630-pm660a-cdp.dts b/arch/arm/boot/dts/qcom/sda630-pm660a-cdp.dts new file mode 100644 index 000000000000..9afa16ff920d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda630-pm660a-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda630.dtsi" +#include "sdm630-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 630 PM660 + PM660A CDP"; + compatible = "qcom,sda630-cdp", "qcom,sda630", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda630-pm660a-mtp.dts b/arch/arm/boot/dts/qcom/sda630-pm660a-mtp.dts new file mode 100644 index 000000000000..8bfd54e46e72 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda630-pm660a-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda630.dtsi" +#include "sdm630-mtp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 630 PM660 + PM660A MTP"; + compatible = "qcom,sda630-mtp", "qcom,sda630", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda630-pm660a-rcm.dts b/arch/arm/boot/dts/qcom/sda630-pm660a-rcm.dts new file mode 100644 index 000000000000..04f2c3726a05 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda630-pm660a-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda630.dtsi" +#include "sdm630-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 630 PM660 + PM660A RCM"; + compatible = "qcom,sda630-cdp", "qcom,sda630", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda630-rcm.dts b/arch/arm/boot/dts/qcom/sda630-rcm.dts new file mode 100644 index 000000000000..4a2ed2624a0d --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda630-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sda630.dtsi" +#include "sdm630-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 630 PM660 + PM660L RCM"; + compatible = "qcom,sda630-cdp", "qcom,sda630", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sda630.dtsi b/arch/arm/boot/dts/qcom/sda630.dtsi new file mode 100644 index 000000000000..87af4de959af --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda630.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm630.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 630"; + compatible = "qcom,sda630"; + qcom,msm-id = <327 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/apqfalcon-cdp.dts b/arch/arm/boot/dts/qcom/sda658-cdp.dts index fc449860da0d..9992963b8705 100644 --- a/arch/arm/boot/dts/qcom/apqfalcon-cdp.dts +++ b/arch/arm/boot/dts/qcom/sda658-cdp.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "apqfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" +#include "sda658.dtsi" +#include "sdm660-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON CDP"; - compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDA 658 PM660 + PM660L CDP"; + compatible = "qcom,sda658-cdp", "qcom,sda658", "qcom,cdp"; qcom,board-id = <1 0>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; diff --git a/arch/arm/boot/dts/qcom/apqfalcon-mtp.dts b/arch/arm/boot/dts/qcom/sda658-mtp.dts index c4f6e9fb30b9..f4322ecfd701 100644 --- a/arch/arm/boot/dts/qcom/apqfalcon-mtp.dts +++ b/arch/arm/boot/dts/qcom/sda658-mtp.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "apqfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" +#include "sda658.dtsi" +#include "sdm660-mtp.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON MTP"; - compatible = "qcom,apqfalcon-mtp", "qcom,apqfalcon", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. SDA 658 PM660 + PM660L MTP"; + compatible = "qcom,sda658-mtp", "qcom,sda658", "qcom,mtp"; qcom,board-id = <8 0>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-cdp.dts b/arch/arm/boot/dts/qcom/sda658-pm660a-cdp.dts index 3d3f8682941f..c280c4afda51 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-cdp.dts +++ b/arch/arm/boot/dts/qcom/sda658-pm660a-cdp.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sda658.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON CDP"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDA 658 PM660 + PM660A CDP"; + compatible = "qcom,sda658-cdp", "qcom,sda658", "qcom,cdp"; qcom,board-id = <1 0>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-mtp.dts b/arch/arm/boot/dts/qcom/sda658-pm660a-mtp.dts index e7e8aeb9c2aa..ba8741e2a068 100644 --- a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-mtp.dts +++ b/arch/arm/boot/dts/qcom/sda658-pm660a-mtp.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "apqfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sda658.dtsi" +#include "sdm660-mtp.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON MTP"; - compatible = "qcom,apqfalcon-mtp", "qcom,apqfalcon", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. SDA 658 PM660 + PM660A MTP"; + compatible = "qcom,sda658-mtp", "qcom,sda658", "qcom,mtp"; qcom,board-id = <8 0>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rcm.dts b/arch/arm/boot/dts/qcom/sda658-pm660a-rcm.dts index c48124120d61..f3edc9a5d29f 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rcm.dts +++ b/arch/arm/boot/dts/qcom/sda658-pm660a-rcm.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sda658.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON RCM"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDA 658 PM660 + PM660A RCM"; + compatible = "qcom,sda658-cdp", "qcom,sda658", "qcom,cdp"; qcom,board-id = <21 0>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rcm.dts b/arch/arm/boot/dts/qcom/sda658-rcm.dts index e4f59c735e70..9fafd9632c8d 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-rcm.dts +++ b/arch/arm/boot/dts/qcom/sda658-rcm.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" +#include "sda658.dtsi" +#include "sdm660-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON RCM"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDA 658 PM660 + PM660L RCM"; + compatible = "qcom,sda658-cdp", "qcom,sda658", "qcom,cdp"; qcom,board-id = <21 0>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; diff --git a/arch/arm/boot/dts/qcom/sda658.dtsi b/arch/arm/boot/dts/qcom/sda658.dtsi new file mode 100644 index 000000000000..33018a177b41 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sda658.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm658.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDA 658"; + compatible = "qcom,sda658"; + qcom,msm-id = <326 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dts b/arch/arm/boot/dts/qcom/sda660-cdp.dts index ddcea8653983..43e43f7f7125 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dts +++ b/arch/arm/boot/dts/qcom/sda660-cdp.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" +#include "sda660.dtsi" +#include "sdm660-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON CDP"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L CDP"; + compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp"; qcom,board-id = <1 0>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dts b/arch/arm/boot/dts/qcom/sda660-mtp.dts index cefe0d7c275b..0e14f3df9d8b 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dts +++ b/arch/arm/boot/dts/qcom/sda660-mtp.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" +#include "sda660.dtsi" +#include "sdm660-mtp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON MTP"; - compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L MTP"; + compatible = "qcom,sda660-mtp", "qcom,sda660", "qcom,mtp"; qcom,board-id = <8 0>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; diff --git a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-cdp.dts b/arch/arm/boot/dts/qcom/sda660-pm660a-cdp.dts index 851533931a61..bfccd541e4b6 100644 --- a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-cdp.dts +++ b/arch/arm/boot/dts/qcom/sda660-pm660a-cdp.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "apqfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sda660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON CDP"; - compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A CDP"; + compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp"; qcom,board-id = <1 0>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-mtp.dts b/arch/arm/boot/dts/qcom/sda660-pm660a-mtp.dts index 4e6bb7336f2b..1b7cfe1e1077 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-mtp.dts +++ b/arch/arm/boot/dts/qcom/sda660-pm660a-mtp.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sda660.dtsi" +#include "sdm660-mtp.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON MTP"; - compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A MTP"; + compatible = "qcom,sda660-mtp", "qcom,sda660", "qcom,mtp"; qcom,board-id = <8 0>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-rcm.dts b/arch/arm/boot/dts/qcom/sda660-pm660a-rcm.dts index 68c4bd724ccd..aa7a890fbe39 100644 --- a/arch/arm/boot/dts/qcom/apqfalcon-pm3falcon-rcm.dts +++ b/arch/arm/boot/dts/qcom/sda660-pm660a-rcm.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "apqfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sda660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM3FALCON RCM"; - compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A RCM"; + compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp"; qcom,board-id = <21 0>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/apqfalcon-rcm.dts b/arch/arm/boot/dts/qcom/sda660-rcm.dts index 8f4b164c55ca..73ea188c5221 100644 --- a/arch/arm/boot/dts/qcom/apqfalcon-rcm.dts +++ b/arch/arm/boot/dts/qcom/sda660-rcm.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "apqfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" +#include "sda660.dtsi" +#include "sdm660-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ FALCON PMFALCON + PM2FALCON RCM"; - compatible = "qcom,apqfalcon-cdp", "qcom,apqfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L RCM"; + compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp"; qcom,board-id = <21 0>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; diff --git a/arch/arm/boot/dts/qcom/apqfalcon.dtsi b/arch/arm/boot/dts/qcom/sda660.dtsi index d4dc066f6a79..d2919a9467dd 100644 --- a/arch/arm/boot/dts/qcom/apqfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/sda660.dtsi @@ -10,10 +10,10 @@ * GNU General Public License for more details. */ -#include "msmfalcon.dtsi" +#include "sdm660.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ FALCON"; - compatible = "qcom,apqfalcon"; + model = "Qualcomm Technologies, Inc. SDA 660"; + compatible = "qcom,sda660"; qcom,msm-id = <324 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/sdm630-cdp.dts b/arch/arm/boot/dts/qcom/sdm630-cdp.dts new file mode 100644 index 000000000000..9ad4322f2af0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660L CDP"; + compatible = "qcom,sdm630-cdp", "qcom,sdm630", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dtsi b/arch/arm/boot/dts/qcom/sdm630-cdp.dtsi index 3ec991b82bba..6779d80d76cf 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dtsi +++ b/arch/arm/boot/dts/qcom/sdm630-cdp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -10,7 +10,7 @@ * GNU General Public License for more details. */ -#include "msmfalcon-pinctrl.dtsi" +#include "sdm660-pinctrl.dtsi" / { }; diff --git a/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi b/arch/arm/boot/dts/qcom/sdm630-coresight.dtsi index 796235ffd1be..e035cf85b9df 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-coresight.dtsi +++ b/arch/arm/boot/dts/qcom/sdm630-coresight.dtsi @@ -10,7 +10,7 @@ * GNU General Public License for more details. */ -#include "msmfalcon-coresight.dtsi" +#include "sdm660-coresight.dtsi" &etm0 { cpu = <&CPU4>; diff --git a/arch/arm/boot/dts/qcom/sdm630-internal-codec-cdp.dts b/arch/arm/boot/dts/qcom/sdm630-internal-codec-cdp.dts new file mode 100644 index 000000000000..c15abc5ffa39 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-internal-codec-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660L Int. Audio Codec CDP"; + compatible = "qcom,sdm630-cdp", "qcom,sdm630", "qcom,cdp"; + qcom,board-id = <1 1>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm630-internal-codec-mtp.dts b/arch/arm/boot/dts/qcom/sdm630-internal-codec-mtp.dts new file mode 100644 index 000000000000..0e180392e9de --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-internal-codec-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660L Int. Audio Codec MTP"; + compatible = "qcom,sdm630-mtp", "qcom,sdm630", "qcom,mtp"; + qcom,board-id = <8 1>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm630-internal-codec-pm660a-cdp.dts b/arch/arm/boot/dts/qcom/sdm630-internal-codec-pm660a-cdp.dts new file mode 100644 index 000000000000..fc4c216b2b57 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-internal-codec-pm660a-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660A Int. Audio Codec CDP"; + compatible = "qcom,sdm630-cdp", "qcom,sdm630", "qcom,cdp"; + qcom,board-id = <1 1>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm630-internal-codec-pm660a-mtp.dts b/arch/arm/boot/dts/qcom/sdm630-internal-codec-pm660a-mtp.dts new file mode 100644 index 000000000000..aab0eda3448b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-internal-codec-pm660a-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-mtp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660A Int. Audio Codec MTP"; + compatible = "qcom,sdm630-mtp", "qcom,sdm630", "qcom,mtp"; + qcom,board-id = <8 1>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm630-internal-codec-pm660a-rcm.dts b/arch/arm/boot/dts/qcom/sdm630-internal-codec-pm660a-rcm.dts new file mode 100644 index 000000000000..f6e2d180ccb6 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-internal-codec-pm660a-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660A Int. Audio Codec RCM"; + compatible = "qcom,sdm630-cdp", "qcom,sdm630", "qcom,cdp"; + qcom,board-id = <21 1>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm630-internal-codec-rcm.dts b/arch/arm/boot/dts/qcom/sdm630-internal-codec-rcm.dts new file mode 100644 index 000000000000..a6d318cea8e0 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-internal-codec-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660L Int. Audio Codec RCM"; + compatible = "qcom,sdm630-cdp", "qcom,sdm630", "qcom,cdp"; + qcom,board-id = <21 1>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-ion.dtsi b/arch/arm/boot/dts/qcom/sdm630-ion.dtsi index 00b9e61d01b8..00b9e61d01b8 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-ion.dtsi +++ b/arch/arm/boot/dts/qcom/sdm630-ion.dtsi diff --git a/arch/arm/boot/dts/qcom/sdm630-mtp.dts b/arch/arm/boot/dts/qcom/sdm630-mtp.dts new file mode 100644 index 000000000000..4933fcb8fce3 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660L MTP"; + compatible = "qcom,sdm630-mtp", "qcom,sdm630", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm630-mtp.dtsi b/arch/arm/boot/dts/qcom/sdm630-mtp.dtsi new file mode 100644 index 000000000000..16d6c1bf9500 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-mtp.dtsi @@ -0,0 +1,28 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm660-pinctrl.dtsi" +/ { +}; + +&uartblsp1dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&mem_client_3_size { + qcom,peripheral-size = <0x500000>; +}; + +&soc { +}; diff --git a/arch/arm/boot/dts/qcom/sdm630-pm660a-cdp.dts b/arch/arm/boot/dts/qcom/sdm630-pm660a-cdp.dts new file mode 100644 index 000000000000..478f3acde81e --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-pm660a-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660A CDP"; + compatible = "qcom,sdm630-cdp", "qcom,sdm630", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm630-pm660a-mtp.dts b/arch/arm/boot/dts/qcom/sdm630-pm660a-mtp.dts new file mode 100644 index 000000000000..3da1116c4352 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-pm660a-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-mtp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660A MTP"; + compatible = "qcom,sdm630-mtp", "qcom,sdm630", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm630-pm660a-rcm.dts b/arch/arm/boot/dts/qcom/sdm630-pm660a-rcm.dts new file mode 100644 index 000000000000..49938fa254cb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-pm660a-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660A RCM"; + compatible = "qcom,sdm630-cdp", "qcom,sdm630", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts b/arch/arm/boot/dts/qcom/sdm630-pm660a-rumi.dts index a27ee2ac1ed5..398496a943ac 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts +++ b/arch/arm/boot/dts/qcom/sdm630-pm660a-rumi.dts @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -13,13 +13,15 @@ /dts-v1/; -#include "msmtriton.dtsi" -#include "msmfalcon-pinctrl.dtsi" +#include "sdm630.dtsi" +#include "sdm660-pinctrl.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM TRITON RUMI"; - compatible = "qcom,msmtriton-rumi", "qcom,msmtriton", "qcom,rumi"; + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660A RUMI"; + compatible = "qcom,sdm630-rumi", "qcom,sdm630", "qcom,rumi"; qcom,board-id = <15 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; chosen { bootargs = "lpm_levels.sleep_disabled=1"; diff --git a/arch/arm/boot/dts/qcom/sdm630-rcm.dts b/arch/arm/boot/dts/qcom/sdm630-rcm.dts new file mode 100644 index 000000000000..79b3f8edfcc2 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm630-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660L RCM"; + compatible = "qcom,sdm630-cdp", "qcom,sdm630", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi b/arch/arm/boot/dts/qcom/sdm630-regulator.dtsi index 2201a04cfbc1..73735159101d 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/sdm630-regulator.dtsi @@ -13,7 +13,7 @@ &rpm_bus { rpm-regulator-smpa4 { status = "okay"; - pmfalcon_s4: regulator-s4 { + pm660_s4: regulator-s4 { regulator-min-microvolt = <1805000>; regulator-max-microvolt = <2040000>; status = "okay"; @@ -22,7 +22,7 @@ rpm-regulator-smpa5 { status = "okay"; - pmfalcon_s5: regulator-s5 { + pm660_s5: regulator-s5 { regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; status = "okay"; @@ -31,7 +31,7 @@ rpm-regulator-smpa6 { status = "okay"; - pmfalcon_s6: regulator-s6 { + pm660_s6: regulator-s6 { regulator-min-microvolt = <504000>; regulator-max-microvolt = <992000>; status = "okay"; @@ -40,7 +40,7 @@ rpm-regulator-smpb1 { status = "okay"; - pm2falcon_s1: regulator-s1 { + pm660l_s1: regulator-s1 { regulator-min-microvolt = <1125000>; regulator-max-microvolt = <1125000>; status = "okay"; @@ -49,19 +49,19 @@ rpm-regulator-smpb2 { status = "okay"; - pm2falcon_s2: regulator-s2 { + pm660l_s2: regulator-s2 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; status = "okay"; }; }; - /* PM2FALCON S3 + S4 - VDD_CX supply */ + /* PM660L S3 + S4 - VDD_CX supply */ rpm-regulator-smpb3 { status = "okay"; - pm2falcon_s3_level: regulator-s3-level { + pm660l_s3_level: regulator-s3-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_level"; + regulator-name = "pm660l_s3_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -70,9 +70,9 @@ qcom,use-voltage-level; }; - pm2falcon_s3_floor_level: regulator-s3-floor-level { + pm660l_s3_floor_level: regulator-s3-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_floor_level"; + regulator-name = "pm660l_s3_floor_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -82,9 +82,9 @@ qcom,always-send-voltage; }; - pm2falcon_s3_level_ao: regulator-s3-level-ao { + pm660l_s3_level_ao: regulator-s3-level-ao { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s3_level_ao"; + regulator-name = "pm660l_s3_level_ao"; qcom,set = <1>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -94,12 +94,12 @@ }; }; - /* PM2FALCON S5 - VDD_MX supply */ + /* PM660L S5 - VDD_MX supply */ rpm-regulator-smpb5 { status = "okay"; - pm2falcon_s5_level: regulator-s5-level { + pm660l_s5_level: regulator-s5-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_level"; + regulator-name = "pm660l_s5_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -108,9 +108,9 @@ qcom,use-voltage-level; }; - pm2falcon_s5_floor_level: regulator-s5-floor-level { + pm660l_s5_floor_level: regulator-s5-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_floor_level"; + regulator-name = "pm660l_s5_floor_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -120,9 +120,9 @@ qcom,always-send-voltage; }; - pm2falcon_s5_level_ao: regulator-s5-level-ao { + pm660l_s5_level_ao: regulator-s5-level-ao { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_s5_level_ao"; + regulator-name = "pm660l_s5_level_ao"; qcom,set = <1>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -134,7 +134,7 @@ rpm-regulator-ldoa1 { status = "okay"; - pmfalcon_l1: regulator-l1 { + pm660_l1: regulator-l1 { regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1250000>; status = "okay"; @@ -143,7 +143,7 @@ rpm-regulator-ldoa2 { status = "okay"; - pmfalcon_l2: regulator-l2 { + pm660_l2: regulator-l2 { regulator-min-microvolt = <950000>; regulator-max-microvolt = <1010000>; status = "okay"; @@ -152,7 +152,7 @@ rpm-regulator-ldoa3 { status = "okay"; - pmfalcon_l3: regulator-l3 { + pm660_l3: regulator-l3 { regulator-min-microvolt = <950000>; regulator-max-microvolt = <1010000>; status = "okay"; @@ -161,7 +161,7 @@ rpm-regulator-ldoa5 { status = "okay"; - pmfalcon_l5: regulator-l5 { + pm660_l5: regulator-l5 { regulator-min-microvolt = <525000>; regulator-max-microvolt = <950000>; status = "okay"; @@ -170,15 +170,15 @@ rpm-regulator-ldoa6 { status = "okay"; - pmfalcon_l6: regulator-l6 { + pm660_l6: regulator-l6 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1370000>; status = "okay"; }; - pmfalcon_l6_pin_ctrl: regulator-l6-pin-ctrl { + pm660_l6_pin_ctrl: regulator-l6-pin-ctrl { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l6_pin_ctrl"; + regulator-name = "pm660_l6_pin_ctrl"; qcom,set = <3>; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1370000>; @@ -191,7 +191,7 @@ rpm-regulator-ldoa7 { status = "okay"; - pmfalcon_l7: regulator-l7 { + pm660_l7: regulator-l7 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; status = "okay"; @@ -200,7 +200,7 @@ rpm-regulator-ldoa8 { status = "okay"; - pmfalcon_l8: regulator-l8 { + pm660_l8: regulator-l8 { regulator-min-microvolt = <1750000>; regulator-max-microvolt = <1900000>; status = "okay"; @@ -209,15 +209,15 @@ rpm-regulator-ldoa9 { status = "okay"; - pmfalcon_l9: regulator-l9 { + pm660_l9: regulator-l9 { regulator-min-microvolt = <1750000>; regulator-max-microvolt = <1900000>; status = "okay"; }; - pmfalcon_l9_pin_ctrl: regulator-l9-pin-ctrl { + pm660_l9_pin_ctrl: regulator-l9-pin-ctrl { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l9_pin_ctrl"; + regulator-name = "pm660_l9_pin_ctrl"; qcom,set = <3>; regulator-min-microvolt = <1750000>; regulator-max-microvolt = <1900000>; @@ -230,7 +230,7 @@ rpm-regulator-ldoa10 { status = "okay"; - pmfalcon_l10: regulator-l10 { + pm660_l10: regulator-l10 { regulator-min-microvolt = <1780000>; regulator-max-microvolt = <1950000>; status = "okay"; @@ -239,7 +239,7 @@ rpm-regulator-ldoa11 { status = "okay"; - pmfalcon_l11: regulator-l11 { + pm660_l11: regulator-l11 { regulator-min-microvolt = <1780000>; regulator-max-microvolt = <1950000>; status = "okay"; @@ -248,7 +248,7 @@ rpm-regulator-ldoa12 { status = "okay"; - pmfalcon_l12: regulator-l12 { + pm660_l12: regulator-l12 { regulator-min-microvolt = <1780000>; regulator-max-microvolt = <1950000>; status = "okay"; @@ -257,7 +257,7 @@ rpm-regulator-ldoa13 { status = "okay"; - pmfalcon_l13: regulator-l13 { + pm660_l13: regulator-l13 { regulator-min-microvolt = <1780000>; regulator-max-microvolt = <1950000>; status = "okay"; @@ -266,7 +266,7 @@ rpm-regulator-ldoa14 { status = "okay"; - pmfalcon_l14: regulator-l14 { + pm660_l14: regulator-l14 { regulator-min-microvolt = <1710000>; regulator-max-microvolt = <1900000>; status = "okay"; @@ -275,7 +275,7 @@ rpm-regulator-ldoa15 { status = "okay"; - pmfalcon_l15: regulator-l15 { + pm660_l15: regulator-l15 { regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2950000>; status = "okay"; @@ -284,7 +284,7 @@ rpm-regulator-ldoa17 { status = "okay"; - pmfalcon_l17: regulator-l17 { + pm660_l17: regulator-l17 { regulator-min-microvolt = <1650000>; regulator-max-microvolt = <2950000>; status = "okay"; @@ -293,15 +293,15 @@ rpm-regulator-ldoa19 { status = "okay"; - pmfalcon_l19: regulator-l19 { + pm660_l19: regulator-l19 { regulator-min-microvolt = <3200000>; regulator-max-microvolt = <3400000>; status = "okay"; }; - pmfalcon_l19_pin_ctrl: regulator-l19-pin-ctrl { + pm660_l19_pin_ctrl: regulator-l19-pin-ctrl { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmfalcon_l19_pin_ctrl"; + regulator-name = "pm660_l19_pin_ctrl"; qcom,set = <3>; regulator-min-microvolt = <3200000>; regulator-max-microvolt = <3400000>; @@ -314,7 +314,7 @@ rpm-regulator-ldob1 { status = "okay"; - pm2falcon_l1: regulator-l1 { + pm660l_l1: regulator-l1 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <925000>; status = "okay"; @@ -323,7 +323,7 @@ rpm-regulator-ldob2 { status = "okay"; - pm2falcon_l2: regulator-l2 { + pm660l_l2: regulator-l2 { regulator-min-microvolt = <350000>; regulator-max-microvolt = <3100000>; status = "okay"; @@ -332,7 +332,7 @@ rpm-regulator-ldob3 { status = "okay"; - pm2falcon_l3: regulator-l3 { + pm660l_l3: regulator-l3 { regulator-min-microvolt = <1710000>; regulator-max-microvolt = <3600000>; status = "okay"; @@ -341,7 +341,7 @@ rpm-regulator-ldob4 { status = "okay"; - pm2falcon_l4: regulator-l4 { + pm660l_l4: regulator-l4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2950000>; status = "okay"; @@ -350,7 +350,7 @@ rpm-regulator-ldob5 { status = "okay"; - pm2falcon_l5: regulator-l5 { + pm660l_l5: regulator-l5 { regulator-min-microvolt = <1721000>; regulator-max-microvolt = <3600000>; status = "okay"; @@ -359,7 +359,7 @@ rpm-regulator-ldob6 { status = "okay"; - pm2falcon_l6: regulator-l6 { + pm660l_l6: regulator-l6 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <3300000>; status = "okay"; @@ -368,7 +368,7 @@ rpm-regulator-ldob7 { status = "okay"; - pm2falcon_l7: regulator-l7 { + pm660l_l7: regulator-l7 { regulator-min-microvolt = <2700000>; regulator-max-microvolt = <3125000>; status = "okay"; @@ -377,19 +377,19 @@ rpm-regulator-ldob8 { status = "okay"; - pm2falcon_l8: regulator-l8 { + pm660l_l8: regulator-l8 { regulator-min-microvolt = <3200000>; regulator-max-microvolt = <3400000>; status = "okay"; }; }; - /* PM2FALCON L9 = VDD_SSC_CX supply */ + /* PM660L L9 = VDD_SSC_CX supply */ rpm-regulator-ldob9 { status = "okay"; - pm2falcon_l9_level: regulator-l9-level { + pm660l_l9_level: regulator-l9-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l9_level"; + regulator-name = "pm660l_l9_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -398,9 +398,9 @@ qcom,use-voltage-level; }; - pm2falcon_l9_floor_level: regulator-l9-floor-level { + pm660l_l9_floor_level: regulator-l9-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l9_floor_level"; + regulator-name = "pm660l_l9_floor_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -411,12 +411,12 @@ }; }; - /* PM2FALCON L10 = VDD_SSC_MX supply */ + /* PM660L L10 = VDD_SSC_MX supply */ rpm-regulator-ldob10 { status = "okay"; - pm2falcon_l10_level: regulator-l10-level { + pm660l_l10_level: regulator-l10-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l10_level"; + regulator-name = "pm660l_l10_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -425,9 +425,9 @@ qcom,use-voltage-level; }; - pm2falcon_l10_floor_level: regulator-l10-floor-level { + pm660l_l10_floor_level: regulator-l10-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_l10_floor_level"; + regulator-name = "pm660l_l10_floor_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -440,33 +440,33 @@ rpm-regulator-bobb { status = "okay"; - pm2falcon_bob: regulator-bob { + pm660l_bob: regulator-bob { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3600000>; status = "okay"; }; - pm2falcon_bob_pin1: regulator-bob-pin1 { + pm660l_bob_pin1: regulator-bob-pin1 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin1"; + regulator-name = "pm660l_bob_pin1"; qcom,set = <3>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3600000>; qcom,use-pin-ctrl-voltage1; }; - pm2falcon_bob_pin2: regulator-bob-pin2 { + pm660l_bob_pin2: regulator-bob-pin2 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin2"; + regulator-name = "pm660l_bob_pin2"; qcom,set = <3>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3600000>; qcom,use-pin-ctrl-voltage2; }; - pm2falcon_bob_pin3: regulator-bob-pin3 { + pm660l_bob_pin3: regulator-bob-pin3 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pm2falcon_bob_pin3"; + regulator-name = "pm660l_bob_pin3"; qcom,set = <3>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3600000>; @@ -475,7 +475,7 @@ }; }; -&pmfalcon_charger { +&pm660_charger { smb2_vbus: qcom,smb2-vbus { regulator-name = "smb2-vbus"; }; diff --git a/arch/arm/boot/dts/qcom/sdm630-rumi.dts b/arch/arm/boot/dts/qcom/sdm630-rumi.dts new file mode 100644 index 000000000000..ddf954f9f6ff --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm630-rumi.dts @@ -0,0 +1,88 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm630.dtsi" +#include "sdm660-pinctrl.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 630 PM660 + PM660L RUMI"; + compatible = "qcom,sdm630-rumi", "qcom,sdm630", "qcom,rumi"; + qcom,board-id = <15 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; + + chosen { + bootargs = "lpm_levels.sleep_disabled=1"; + }; +}; + +&usb3 { + /delete-property/ USB3_GDSC-supply; + /delete-property/ extcon; + dwc3@a800000 { + maximum-speed = "high-speed"; + }; +}; + +&ssphy { + compatible = "usb-nop-xceiv"; +}; + +&qusb_phy0 { + reg = <0x0a928000 0x8000>, + <0x0a8f8800 0x400>, + <0x0a920000 0x100>; + reg-names = "qusb_phy_base", + "qscratch_base", + "emu_phy_base"; + qcom,emulation; + qcom,qusb-phy-init-seq = <0x19 0x1404 + 0x20 0x1414 + 0x79 0x1410 + 0x00 0x1418 + 0x99 0x1404 + 0x04 0x1408 + 0xd9 0x1404>; + qcom,emu-dcm-reset-seq = <0x100000 0x20 + 0x0 0x20 + 0x1a0 0x20 + 0x5 0x14>; +}; + +&uartblsp1dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&clock_gcc { + compatible = "qcom,dummycc"; + clock-output-names = "gcc_clocks"; +}; + +&clock_gfx { + compatible = "qcom,dummycc"; + clock-output-names = "gfx_clocks"; +}; + +&clock_mmss { + compatible = "qcom,dummycc"; + clock-output-names = "mmss_clocks"; +}; + +&clock_debug { + compatible = "qcom,dummycc"; + clock-output-names = "debug_clocks"; +}; diff --git a/arch/arm/boot/dts/qcom/msmtriton-smp2p.dtsi b/arch/arm/boot/dts/qcom/sdm630-smp2p.dtsi index b458bbb08dc2..b458bbb08dc2 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-smp2p.dtsi +++ b/arch/arm/boot/dts/qcom/sdm630-smp2p.dtsi diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/sdm630.dtsi index 4ef236d52911..2ebabab84f11 100644 --- a/arch/arm/boot/dts/qcom/msmtriton.dtsi +++ b/arch/arm/boot/dts/qcom/sdm630.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -11,16 +11,16 @@ */ #include "skeleton64.dtsi" -#include <dt-bindings/clock/qcom,gcc-msmfalcon.h> -#include <dt-bindings/clock/qcom,gpu-msmfalcon.h> -#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h> +#include <dt-bindings/clock/qcom,gcc-sdm660.h> +#include <dt-bindings/clock/qcom,gpu-sdm660.h> +#include <dt-bindings/clock/qcom,mmcc-sdm660.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> / { - model = "Qualcomm Technologies, Inc. MSMTRITON"; - compatible = "qcom,msmtriton"; + model = "Qualcomm Technologies, Inc. SDM630"; + compatible = "qcom,sdm630"; qcom,msm-id = <318 0x0>; interrupt-parent = <&intc>; @@ -48,7 +48,7 @@ reg = <0x0 0x100>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile0>; - efficiency = <1024>; + efficiency = <1126>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -72,7 +72,7 @@ reg = <0x0 0x101>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile1>; - efficiency = <1024>; + efficiency = <1126>; next-level-cache = <&L2_1>; L1_I_101: l1-icache { compatible = "arm,arch-cache"; @@ -90,7 +90,7 @@ reg = <0x0 0x102>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile2>; - efficiency = <1024>; + efficiency = <1126>; next-level-cache = <&L2_1>; L1_I_102: l1-icache { compatible = "arm,arch-cache"; @@ -108,7 +108,7 @@ reg = <0x0 0x103>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile3>; - efficiency = <1024>; + efficiency = <1126>; next-level-cache = <&L2_1>; L1_I_103: l1-icache { compatible = "arm,arch-cache"; @@ -312,8 +312,8 @@ }; }; -#include "msmtriton-smp2p.dtsi" -#include "msmtriton-coresight.dtsi" +#include "sdm630-smp2p.dtsi" +#include "sdm630-coresight.dtsi" &soc { #address-cells = <1>; #size-cells = <1>; @@ -450,7 +450,7 @@ }; tsens: tsens@10ad000 { - compatible = "qcom,msmtriton-tsens"; + compatible = "qcom,sdm630-tsens"; reg = <0x10ad000 0x2000>; reg-names = "tsens_physical"; interrupts = <0 184 0>, <0 430 0>; @@ -523,7 +523,7 @@ }; sensor_information12: qcom,sensor-information-12 { qcom,sensor-type = "alarm"; - qcom,sensor-name = "pmfalcon_tz"; + qcom,sensor-name = "pm660_tz"; qcom,scaling-factor = <1000>; }; sensor_information13: qcom,sensor-information-13 { @@ -598,7 +598,7 @@ qcom,vdd-restriction-temp = <5>; qcom,vdd-restriction-temp-hysteresis = <10>; - vdd-dig-supply = <&pm2falcon_s3_floor_level>; + vdd-dig-supply = <&pm660l_s3_floor_level>; vdd-gfx-supply = <&gfx_vreg_corner>; qcom,vdd-dig-rstr{ @@ -734,34 +734,34 @@ }; clock_rpmcc: qcom,rpmcc { - compatible = "qcom,rpmcc-msmfalcon", "qcom,rpmcc"; + compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; #clock-cells = <1>; }; clock_gcc: clock-controller@100000 { - compatible = "qcom,gcc-msmfalcon", "syscon"; + compatible = "qcom,gcc-sdm660", "syscon"; reg = <0x100000 0x94000>; - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; + vdd_dig-supply = <&pm660l_s3_level>; + vdd_dig_ao-supply = <&pm660l_s3_level_ao>; #clock-cells = <1>; #reset-cells = <1>; }; clock_mmss: clock-controller@c8c0000 { - compatible = "qcom,mmcc-msmfalcon"; + compatible = "qcom,mmcc-sdm660"; reg = <0xc8c0000 0x40000>; - vdd_mx_mmss-supply = <&pm2falcon_s5_level>; - vdd_dig_mmss-supply = <&pm2falcon_s3_level>; - vdda-supply = <&pmfalcon_l10>; + vdd_mx_mmss-supply = <&pm660l_s5_level>; + vdd_dig_mmss-supply = <&pm660l_s3_level>; + vdda-supply = <&pm660_l10>; #clock-cells = <1>; #reset-cells = <1>; }; clock_gfx: clock-controller@5065000 { - compatible = "qcom,gpucc-msmtriton"; + compatible = "qcom,gpucc-sdm630"; reg = <0x5065000 0x10000>; - vdd_dig_gfx-supply = <&pm2falcon_s3_level>; - vdd_mx_gfx-supply = <&pm2falcon_s5_level>; + vdd_dig_gfx-supply = <&pm660l_s3_level>; + vdd_mx_gfx-supply = <&pm660l_s5_level>; vdd_gfx-supply = <&gfx_vreg_corner>; qcom,gfxfreq-corner = < 0 0>, @@ -793,7 +793,7 @@ }; clock_debug: qcom,cc-debug@62000 { - compatible = "qcom,gcc-debug-msmfalcon"; + compatible = "qcom,gcc-debug-sdm660"; reg = <0x62000 0x4>; reg-names = "dbg_offset"; clocks = <&clock_rpmcc RPM_XO_CLK_SRC>; @@ -875,6 +875,35 @@ label = "rpm"; }; + glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp { + compatible = "qcom,glink-spi-xprt"; + label = "wdsp"; + qcom,remote-fifo-config = <&glink_fifo_wdsp>; + qcom,qos-config = <&glink_qos_wdsp>; + qcom,ramp-time = <0x10>, + <0x20>, + <0x30>, + <0x40>; + }; + + glink_fifo_wdsp: qcom,glink-fifo-config-wdsp { + compatible = "qcom,glink-fifo-config"; + qcom,out-read-idx-reg = <0x12000>; + qcom,out-write-idx-reg = <0x12004>; + qcom,in-read-idx-reg = <0x1200c>; + qcom,in-write-idx-reg = <0x12010>; + }; + + glink_qos_wdsp: qcom,glink-qos-config-wdsp { + compatible = "qcom,glink-qos-config"; + qcom,flow-info = <0x80 0x0>, + <0x70 0x1>, + <0x60 0x2>, + <0x50 0x3>; + qcom,mtu-size = <0x800>; + qcom,tput-stats-cycle = <0xa>; + }; + qcom,glink_pkt { compatible = "qcom,glinkpkt"; @@ -1017,7 +1046,7 @@ reg = <0x15700000 0x00100>; interrupts = <0 162 1>; - vdd_cx-supply = <&pm2falcon_l9_level>; + vdd_cx-supply = <&pm660l_l9_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; @@ -1103,9 +1132,9 @@ "mnoc_axi_clk"; interrupts = <0 448 1>; - vdd_cx-supply = <&pm2falcon_s3_level>; + vdd_cx-supply = <&pm660l_s3_level>; vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - vdd_mx-supply = <&pm2falcon_s5_level>; + vdd_mx-supply = <&pm660l_s5_level>; vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; qcom,firmware-name = "modem"; qcom,pil-self-auth; @@ -1239,15 +1268,16 @@ }; }; -#include "msmtriton-ion.dtsi" -#include "msm-pmfalcon.dtsi" -#include "msm-pm2falcon.dtsi" -#include "msm-pmfalcon-rpm-regulator.dtsi" -#include "msm-pm2falcon-rpm-regulator.dtsi" -#include "msmtriton-regulator.dtsi" -#include "msm-gdsc-falcon.dtsi" -#include "msmfalcon-common.dtsi" -#include "msm-arm-smmu-triton.dtsi" +#include "sdm630-ion.dtsi" +#include "msm-pm660.dtsi" +#include "msm-pm660l.dtsi" +#include "msm-pm660-rpm-regulator.dtsi" +#include "msm-pm660l-rpm-regulator.dtsi" +#include "sdm660-bus.dtsi" +#include "sdm630-regulator.dtsi" +#include "msm-gdsc-660.dtsi" +#include "sdm660-common.dtsi" +#include "msm-arm-smmu-630.dtsi" &gdsc_usb30 { status = "ok"; @@ -1294,6 +1324,7 @@ &gdsc_cpp { parent-supply = <&gdsc_camss_top>; + qcom,support-hw-trigger; status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom/sdm658-cdp.dts b/arch/arm/boot/dts/qcom/sdm658-cdp.dts new file mode 100644 index 000000000000..8569af157049 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm658-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm658.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660L CDP"; + compatible = "qcom,sdm658-cdp", "qcom,sdm658", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-cdp.dts b/arch/arm/boot/dts/qcom/sdm658-internal-codec-cdp.dts index ee3255ebe9f8..d0f5c14223ff 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-cdp.dts +++ b/arch/arm/boot/dts/qcom/sdm658-internal-codec-cdp.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" +#include "sdm658.dtsi" +#include "sdm660-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec CDP"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660L Int. Audio Codec CDP"; + compatible = "qcom,sdm658-cdp", "qcom,sdm658", "qcom,cdp"; qcom,board-id = <1 1>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-mtp.dts b/arch/arm/boot/dts/qcom/sdm658-internal-codec-mtp.dts index 59611ab3e5ff..acec15e0615f 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-mtp.dts +++ b/arch/arm/boot/dts/qcom/sdm658-internal-codec-mtp.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" +#include "sdm658.dtsi" +#include "sdm660-mtp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec MTP"; - compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660L Int. Audio Codec MTP"; + compatible = "qcom,sdm658-mtp", "qcom,sdm658", "qcom,mtp"; qcom,board-id = <8 1>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; @@ -61,7 +61,7 @@ }; &int_codec { - qcom,model = "msmfalcon-snd-card-mtp"; + qcom,model = "sdm660-snd-card-mtp"; status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-cdp.dts b/arch/arm/boot/dts/qcom/sdm658-internal-codec-pm660a-cdp.dts index fe91109a4a07..b7f2e70ce962 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-cdp.dts +++ b/arch/arm/boot/dts/qcom/sdm658-internal-codec-pm660a-cdp.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sdm658.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec CDP"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660A Int. Audio Codec CDP"; + compatible = "qcom,sdm658-cdp", "qcom,sdm658", "qcom,cdp"; qcom,board-id = <1 1>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-mtp.dts b/arch/arm/boot/dts/qcom/sdm658-internal-codec-pm660a-mtp.dts index 0653e898ec7d..949d7ae7faa5 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-mtp.dts +++ b/arch/arm/boot/dts/qcom/sdm658-internal-codec-pm660a-mtp.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-mtp.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sdm658.dtsi" +#include "sdm660-mtp.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec MTP"; - compatible = "qcom,msmfalcon-mtp", "qcom,msmfalcon", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660A Int. Audio Codec MTP"; + compatible = "qcom,sdm658-mtp", "qcom,sdm658", "qcom,mtp"; qcom,board-id = <8 1>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-rcm.dts b/arch/arm/boot/dts/qcom/sdm658-internal-codec-pm660a-rcm.dts index cb2b2239588d..c0b3e3a6b34f 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-pm3falcon-rcm.dts +++ b/arch/arm/boot/dts/qcom/sdm658-internal-codec-pm660a-rcm.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sdm658.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON Int. Audio Codec RCM"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660A Int. Audio Codec RCM"; + compatible = "qcom,sdm658-cdp", "qcom,sdm658", "qcom,cdp"; qcom,board-id = <21 1>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-rcm.dts b/arch/arm/boot/dts/qcom/sdm658-internal-codec-rcm.dts index 1d67fe1129c7..69a089c41c32 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-internal-codec-rcm.dts +++ b/arch/arm/boot/dts/qcom/sdm658-internal-codec-rcm.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-cdp.dtsi" +#include "sdm658.dtsi" +#include "sdm660-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON Int. Audio Codec RCM"; - compatible = "qcom,msmfalcon-cdp", "qcom,msmfalcon", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660L Int. Audio Codec RCM"; + compatible = "qcom,sdm658-cdp", "qcom,sdm658", "qcom,cdp"; qcom,board-id = <21 1>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; diff --git a/arch/arm/boot/dts/qcom/sdm658-mtp.dts b/arch/arm/boot/dts/qcom/sdm658-mtp.dts new file mode 100644 index 000000000000..2fbe9b0a6201 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm658-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm658.dtsi" +#include "sdm660-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660L MTP"; + compatible = "qcom,sdm658-mtp", "qcom,sdm658", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm658-pm660a-cdp.dts b/arch/arm/boot/dts/qcom/sdm658-pm660a-cdp.dts new file mode 100644 index 000000000000..39e2df958347 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm658-pm660a-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm658.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660A CDP"; + compatible = "qcom,sdm658-cdp", "qcom,sdm658", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm658-pm660a-mtp.dts b/arch/arm/boot/dts/qcom/sdm658-pm660a-mtp.dts new file mode 100644 index 000000000000..4d205ef403f4 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm658-pm660a-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm658.dtsi" +#include "sdm660-mtp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660A MTP"; + compatible = "qcom,sdm658-mtp", "qcom,sdm658", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-qrd.dts b/arch/arm/boot/dts/qcom/sdm658-pm660a-qrd.dts index e2d45f0d151e..f1edf6b244a8 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-qrd.dts +++ b/arch/arm/boot/dts/qcom/sdm658-pm660a-qrd.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-qrd.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sdm658.dtsi" +#include "sdm660-qrd.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON QRD"; - compatible = "qcom,msmfalcon-qrd", "qcom,msmfalcon", "qcom,qrd"; + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660A QRD"; + compatible = "qcom,sdm658-qrd", "qcom,sdm658", "qcom,qrd"; qcom,board-id = <0x1000b 0>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; }; diff --git a/arch/arm/boot/dts/qcom/sdm658-pm660a-rcm.dts b/arch/arm/boot/dts/qcom/sdm658-pm660a-rcm.dts new file mode 100644 index 000000000000..e0ab5725dcd7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm658-pm660a-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm658.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660A RCM"; + compatible = "qcom,sdm658-cdp", "qcom,sdm658", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dts b/arch/arm/boot/dts/qcom/sdm658-qrd.dts index b97fdd18e229..bd7d76ee1f6c 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-qrd.dts +++ b/arch/arm/boot/dts/qcom/sdm658-qrd.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-qrd.dtsi" +#include "sdm658.dtsi" +#include "sdm660-qrd.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON QRD"; - compatible = "qcom,msmfalcon-qrd", "qcom,msmfalcon", "qcom,qrd"; + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660L QRD"; + compatible = "qcom,sdm658-qrd", "qcom,sdm658", "qcom,qrd"; qcom,board-id = <0x1000b 0>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; diff --git a/arch/arm/boot/dts/qcom/sdm658-rcm.dts b/arch/arm/boot/dts/qcom/sdm658-rcm.dts new file mode 100644 index 000000000000..67e03f2e2adb --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm658-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm658.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 658 PM660 + PM660L RCM"; + compatible = "qcom,sdm658-cdp", "qcom,sdm658", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm658.dtsi b/arch/arm/boot/dts/qcom/sdm658.dtsi new file mode 100644 index 000000000000..3eca3dc30e50 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm658.dtsi @@ -0,0 +1,19 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm660.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 658"; + compatible = "qcom,sdm658"; + qcom,msm-id = <325 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-audio.dtsi b/arch/arm/boot/dts/qcom/sdm660-audio.dtsi index df42ba124641..13ee40c71228 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-audio.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-audio.dtsi @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ -#include "msmfalcon-wsa881x.dtsi" -#include "msmfalcon-lpi.dtsi" +#include "sdm660-wsa881x.dtsi" +#include "sdm660-lpi.dtsi" &slim_aud { status = "okay"; @@ -36,7 +36,7 @@ clocks = <&clock_audio AUDIO_PMI_CLK>, <&clock_audio AUDIO_AP_CLK2>; - cdc-vdd-mic-bias-supply = <&pm2falcon_bob>; + cdc-vdd-mic-bias-supply = <&pm660l_bob>; qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>; qcom,cdc-vdd-mic-bias-current = <30400>; @@ -68,7 +68,7 @@ clock-names = "wcd_clk"; clocks = <&clock_audio_lnbb AUDIO_PMIC_LNBB_CLK>; - cdc-vdd-mic-bias-supply = <&pm2falcon_bob>; + cdc-vdd-mic-bias-supply = <&pm660l_bob>; qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>; qcom,cdc-vdd-mic-bias-current = <30400>; @@ -97,7 +97,7 @@ }; }; -&pm2falcon_3 { +&pm660l_3 { pmic_analog_codec: analog-codec@f000 { status = "disabled"; compatible = "qcom,pmic-analog-codec"; @@ -120,15 +120,15 @@ "ins_rem_det", "mbhc_int"; - cdc-vdda-cp-supply = <&pmfalcon_s4>; + cdc-vdda-cp-supply = <&pm660_s4>; qcom,cdc-vdda-cp-voltage = <1900000 2050000>; qcom,cdc-vdda-cp-current = <50000>; - cdc-vdd-pa-supply = <&pmfalcon_s4>; + cdc-vdd-pa-supply = <&pm660_s4>; qcom,cdc-vdd-pa-voltage = <2040000 2040000>; qcom,cdc-vdd-pa-current = <260000>; - cdc-vdd-mic-bias-supply = <&pm2falcon_l7>; + cdc-vdd-mic-bias-supply = <&pm660l_l7>; qcom,cdc-vdd-mic-bias-voltage = <3125000 3125000>; qcom,cdc-vdd-mic-bias-current = <5000>; @@ -235,7 +235,7 @@ }; }; -&pmfalcon_gpios { +&pm660_gpios { gpio@c200 { status = "ok"; qcom,mode = <1>; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi b/arch/arm/boot/dts/qcom/sdm660-blsp.dtsi index c401d364409b..023c34d65680 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-blsp.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-blsp.dtsi @@ -10,7 +10,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include "msmfalcon-pinctrl.dtsi" +#include "sdm660-pinctrl.dtsi" / { aliases { diff --git a/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi b/arch/arm/boot/dts/qcom/sdm660-bus.dtsi index 93c615639be9..93c615639be9 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-bus.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-bus.dtsi diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-cdp.dtsi index 63528e23160a..e31a863ae22d 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-cdp.dtsi @@ -15,18 +15,18 @@ led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>; - qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>; - qcom,switch-source = <&pm2falcon_switch0>; + qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>; + qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>; + qcom,switch-source = <&pm660l_switch0>; status = "ok"; }; led_flash1: qcom,camera-flash@1 { cell-index = <1>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash2>; - qcom,torch-source = <&pm2falcon_torch2>; - qcom,switch-source = <&pm2falcon_switch1>; + qcom,flash-source = <&pm660l_flash2>; + qcom,torch-source = <&pm660l_torch2>; + qcom,switch-source = <&pm660l_switch1>; status = "ok"; }; }; @@ -97,9 +97,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -114,7 +114,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 32 0>, <&tlmm 46 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 51 0>, <&tlmm 50 0>; qcom,gpio-reset = <1>; @@ -142,9 +142,9 @@ cell-index = <1>; reg = <0x1>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -157,7 +157,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 34 0>, <&tlmm 48 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 51 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -182,9 +182,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -199,7 +199,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 33 0>, <&tlmm 47 0>, - <&pmfalcon_gpios 3 0>, + <&pm660_gpios 3 0>, <&tlmm 44 0>, <&tlmm 50 0>; qcom,gpio-reset = <1>; @@ -234,9 +234,9 @@ qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -249,7 +249,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 32 0>, <&tlmm 46 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 51 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -279,9 +279,9 @@ qcom,mount-angle = <90>; qcom,actuator-src = <&actuator1>; qcom,eeprom-src = <&eeprom1>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -294,7 +294,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 34 0>, <&tlmm 48 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 51 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -324,9 +324,9 @@ qcom,mount-angle = <90>; qcom,actuator-src = <&actuator2>; qcom,eeprom-src = <&eeprom2>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -339,7 +339,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 33 0>, <&tlmm 47 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 51 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -361,7 +361,7 @@ }; }; -&pm2falcon_gpios { +&pm660l_gpios { gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-mtp.dtsi index 384807c4ef60..416cd99a81cb 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-mtp.dtsi @@ -15,18 +15,18 @@ led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>; - qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>; - qcom,switch-source = <&pm2falcon_switch0>; + qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>; + qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>; + qcom,switch-source = <&pm660l_switch0>; status = "ok"; }; led_flash1: qcom,camera-flash@1 { cell-index = <1>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pm2falcon_flash2>; - qcom,torch-source = <&pm2falcon_torch2>; - qcom,switch-source = <&pm2falcon_switch1>; + qcom,flash-source = <&pm660l_flash2>; + qcom,torch-source = <&pm660l_torch2>; + qcom,switch-source = <&pm660l_switch1>; status = "ok"; }; }; @@ -97,9 +97,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -114,7 +114,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 32 0>, <&tlmm 46 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 51 0>, <&tlmm 50 0>; qcom,gpio-reset = <1>; @@ -142,9 +142,9 @@ cell-index = <1>; reg = <0x1>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -157,7 +157,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 34 0>, <&tlmm 48 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 51 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -182,9 +182,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -199,7 +199,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 33 0>, <&tlmm 47 0>, - <&pmfalcon_gpios 3 0>, + <&pm660_gpios 3 0>, <&tlmm 44 0>, <&tlmm 50 0>; qcom,gpio-reset = <1>; @@ -234,9 +234,9 @@ qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -249,7 +249,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 32 0>, <&tlmm 46 0>, - <&pm2falcon_gpios 4 0>, + <&pm660l_gpios 4 0>, <&tlmm 51 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -279,9 +279,9 @@ qcom,mount-angle = <90>; qcom,actuator-src = <&actuator1>; qcom,eeprom-src = <&eeprom1>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -294,7 +294,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 34 0>, <&tlmm 48 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 51 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -324,9 +324,9 @@ qcom,mount-angle = <90>; qcom,actuator-src = <&actuator2>; qcom,eeprom-src = <&eeprom2>; - cam_vio-supply = <&pmfalcon_l11>; - cam_vana-supply = <&pm2falcon_bob>; - cam_vdig-supply = <&pmfalcon_s5>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&pm660l_bob>; + cam_vdig-supply = <&pm660_s5>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; @@ -339,7 +339,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 33 0>, <&tlmm 47 0>, - <&pm2falcon_gpios 3 0>, + <&pm660l_gpios 3 0>, <&tlmm 51 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -361,7 +361,7 @@ }; }; -&pm2falcon_gpios { +&pm660l_gpios { gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/sdm660-camera-sensor-qrd.dtsi b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-qrd.dtsi new file mode 100644 index 000000000000..ae8da056d12b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-camera-sensor-qrd.dtsi @@ -0,0 +1,426 @@ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash0: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>; + qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>; + qcom,switch-source = <&pm660l_switch0>; + status = "ok"; + }; + + cam_avdd_gpio_regulator:fixed_regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "cam_vadd_gpio_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&tlmm 51 0>; + vin-supply = <&pm660l_bob>; + }; + + cam_dvdd_gpio_regulator:fixed_regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "cam_vadd_gpio_regulator"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + enable-active-high; + gpio = <&pm660l_gpios 4>; + vin-supply = <&pm660_s5>; + }; + + cam_vaf_gpio_regulator:fixed_regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "cam_vaf_gpio_regulator"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&tlmm 50 0>; + vin-supply = <&pm660l_bob>; + }; +}; + +&tlmm { + cam_sensor_rear_active: cam_sensor_rear_active { + /* RESET */ + mux { + pins = "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio46"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + /* RESET */ + mux { + pins = "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio46"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_active: cam_sensor_rear2_active { + /* RESET */ + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio48"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { + /* RESET */ + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio48"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_active: cam_sensor_front_active { + /* RESET */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_suspend: cam_sensor_front_suspend { + /* RESET */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; + +&cci { + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + cam_vaf-supply = <&cam_vaf_gpio_regulator>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000>; + qcom,cam-vreg-max-voltage = <2800000>; + qcom,cam-vreg-op-mode = <0>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + cam_vaf-supply = <&cam_vaf_gpio_regulator>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000>; + qcom,cam-vreg-max-voltage = <2800000>; + qcom,cam-vreg-op-mode = <0>; + }; + + ois0: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + qcom,cci-master = <0>; + cam_vaf-supply = <&cam_vaf_gpio_regulator>; + qcom,cam-vreg-name = "cam_vaf"; + qcom,cam-vreg-min-voltage = <2800000>; + qcom,cam-vreg-max-voltage = <2800000>; + qcom,cam-vreg-op-mode = <0>; + status = "disabled"; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&cam_avdd_gpio_regulator>; + cam_vdig-supply = <&cam_dvdd_gpio_regulator>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1750000 0 0>; + qcom,cam-vreg-max-voltage = <1980000 0 0>; + qcom,cam-vreg-op-mode = <105000 0 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 46 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&cam_avdd_gpio_regulator>; + cam_vdig-supply = <&cam_dvdd_gpio_regulator>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1750000 0 0>; + qcom,cam-vreg-max-voltage = <1980000 0 0>; + qcom,cam-vreg-op-mode = <105000 0 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK2_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom2: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&cam_avdd_gpio_regulator>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 0 1352000>; + qcom,cam-vreg-max-voltage = <1950000 0 1352000>; + qcom,cam-vreg-op-mode = <105000 0 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 33 0>, + <&tlmm 47 0>, + <&pm660l_gpios 3 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <90>; + qcom,led-flash-src = <&led_flash0>; + qcom,actuator-src = <&actuator0>; + qcom,ois-src = <&ois0>; + qcom,eeprom-src = <&eeprom0>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&cam_avdd_gpio_regulator>; + cam_vdig-supply = <&cam_dvdd_gpio_regulator>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 0 0>; + qcom,cam-vreg-max-voltage = <1950000 0 0>; + qcom,cam-vreg-op-mode = <105000 0 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 46 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET0"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <1>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator1>; + qcom,eeprom-src = <&eeprom1>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&cam_avdd_gpio_regulator>; + cam_vdig-supply = <&cam_dvdd_gpio_regulator>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 0 0>; + qcom,cam-vreg-max-voltage = <1950000 0 0>; + qcom,cam-vreg-op-mode = <105000 0 0>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>; + qcom,gpio-reset = <1>; + qcom,gpio-req-tbl-num = <0 1>; + qcom,gpio-req-tbl-flags = <1 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK2_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <270>; + qcom,eeprom-src = <&eeprom2>; + cam_vio-supply = <&pm660_l11>; + cam_vana-supply = <&cam_avdd_gpio_regulator>; + cam_vdig-supply = <&pm660_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 0 1350000>; + qcom,cam-vreg-max-voltage = <1950000 0 1350000>; + qcom,cam-vreg-op-mode = <105000 0 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 33 0>, + <&tlmm 47 0>, + <&pm660l_gpios 3 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-req-tbl-num = <0 1 2>; + qcom,gpio-req-tbl-flags = <1 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; + +&pm660l_gpios { + gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; + + gpio@c200 { /* GPIO3 -CAMERA SENSOR 2 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera.dtsi b/arch/arm/boot/dts/qcom/sdm660-camera.dtsi index c16794550d88..747729d158a8 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-camera.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-camera.dtsi @@ -12,13 +12,13 @@ */ &soc { - qcom,msm-cam@8c0000 { + qcom,msm-cam@ca00000 { compatible = "qcom,msm-cam"; - reg = <0x8c0000 0x40000>; + reg = <0xca00000 0x4000>; reg-names = "msm-cam"; status = "ok"; bus-vectors = "suspend", "svs", "nominal", "turbo"; - qcom,bus-votes = <0 300000000 640000000 640000000>; + qcom,bus-votes = <0 150000000 320000000 320000000>; }; qcom,csiphy@c824000 { @@ -44,15 +44,17 @@ <&clock_mmss MMSS_CAMSS_CSI0PHYTIMER_CLK>, <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, <&clock_mmss CSIPHY_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSIPHY0_CLK>; + <&clock_mmss MMSS_CAMSS_CSIPHY0_CLK>, + <&clock_mmss MMSS_CSIPHY_AHB2CRIF_CLK>; clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", - "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", + "csiphy_ahb2crif"; qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 - 0 384000000 0>; + 0 384000000 0 0>; status = "ok"; }; @@ -79,15 +81,17 @@ <&clock_mmss MMSS_CAMSS_CSI1PHYTIMER_CLK>, <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, <&clock_mmss CSIPHY_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSIPHY1_CLK>; + <&clock_mmss MMSS_CAMSS_CSIPHY1_CLK>, + <&clock_mmss MMSS_CSIPHY_AHB2CRIF_CLK>; clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", - "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", + "csiphy_ahb2crif"; qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 - 0 384000000 0>; + 0 384000000 0 0>; status = "ok"; }; @@ -114,15 +118,17 @@ <&clock_mmss MMSS_CAMSS_CSI2PHYTIMER_CLK>, <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, <&clock_mmss CSIPHY_CLK_SRC>, - <&clock_mmss MMSS_CAMSS_CSIPHY2_CLK>; + <&clock_mmss MMSS_CAMSS_CSIPHY2_CLK>, + <&clock_mmss MMSS_CSIPHY_AHB2CRIF_CLK>; clock-names = "mmssnoc_axi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", - "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk", + "csiphy_ahb2crif"; qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 - 0 384000000 0>; + 0 384000000 0 0>; status = "ok"; }; @@ -134,9 +140,9 @@ interrupts = <0 296 0>; interrupt-names = "csid"; qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -175,9 +181,9 @@ interrupts = <0 297 0>; interrupt-names = "csid"; qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -216,9 +222,9 @@ interrupts = <0 298 0>; interrupt-names = "csid"; qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -257,9 +263,9 @@ interrupts = <0 299 0>; interrupt-names = "csid"; qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + qcom,mipi-csi-vdd-supply = <&pm660_l1>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pm2falcon_l1>; + vdd_sec-supply = <&pm660l_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; qcom,cam-vreg-min-voltage = <925000 0 0>; @@ -310,12 +316,6 @@ label = "cpp"; }; - msm_cam_smmu_cb3 { - compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&mmss_bimc_smmu 0xa01>; - label = "camera_fd"; - }; - msm_cam_smmu_cb4 { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&mmss_bimc_smmu 0x800>; @@ -364,10 +364,6 @@ qcom,clock-rates = <0 0 0 0 200000000 200000000 0 0 0 0 0>; qcom,min-clock-rate = <200000000>; qcom,bus-master = <1>; - qcom,vbif-qos-setting = <0x20 0x10000000>, - <0x24 0x10000000>, - <0x28 0x10000000>, - <0x2C 0x10000000>; status = "ok"; qcom,msm-bus,name = "msm_camera_cpp"; qcom,msm-bus,num-cases = <2>; @@ -378,8 +374,8 @@ qcom,msm-bus-vector-dyn-vote; resets = <&clock_mmss CAMSS_MICRO_BCR>; reset-names = "micro_iface_reset"; - qcom,src-clock-rates = <100000000 200000000 576000000 - 600000000>; + qcom,src-clock-rates = <120000000 256000000 384000000 + 480000000 540000000 576000000>; qcom,cpp-fw-payload-info { qcom,stripe-base = <790>; qcom,plane-base = <715>; @@ -514,9 +510,9 @@ "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", "camss_vfe_vbif_axi_clk", "vfe_clk_src", "camss_csi_vfe_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 384000000 0 - 0 0 0 0 0 0 0 0 0 0 0 576000000 0 - 0 0 0 0 0 0 0 0 0 0 0 600000000 0>; + qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 256000000 0 + 0 0 0 0 0 0 0 0 0 0 0 480000000 0 + 0 0 0 0 0 0 0 0 0 0 0 576000000 0>; status = "ok"; qos-entries = <8>; qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 @@ -594,9 +590,9 @@ "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", "camss_vfe_vbif_axi_clk", "vfe_clk_src", "camss_csi_vfe_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 384000000 0 - 0 0 0 0 0 0 0 0 0 0 0 576000000 0 - 0 0 0 0 0 0 0 0 0 0 0 600000000 0>; + qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 256000000 0 + 0 0 0 0 0 0 0 0 0 0 0 480000000 0 + 0 0 0 0 0 0 0 0 0 0 0 576000000 0>; status = "ok"; qos-entries = <8>; qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 @@ -727,7 +723,7 @@ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, <&clock_mmss MMSS_CAMSS_AHB_CLK>, <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_JPEG0_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG0_VOTE_CLK>, <&clock_mmss MMSS_CAMSS_JPEG_AHB_CLK>, <&clock_mmss MMSS_CAMSS_JPEG_AXI_CLK >; qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; @@ -771,7 +767,7 @@ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, <&clock_mmss MMSS_CAMSS_AHB_CLK>, <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, - <&clock_mmss MMSS_CAMSS_JPEG0_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG0_DMA_VOTE_CLK>, <&clock_mmss MMSS_CAMSS_JPEG_AHB_CLK>, <&clock_mmss MMSS_CAMSS_JPEG_AXI_CLK>; qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; diff --git a/arch/arm/boot/dts/qcom/sdm660-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-cdp.dts new file mode 100644 index 000000000000..8d338660a14a --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L CDP"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi b/arch/arm/boot/dts/qcom/sdm660-cdp.dtsi index e1306bd78837..a3654c21f2db 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-cdp.dtsi @@ -10,8 +10,8 @@ * GNU General Public License for more details. */ -#include "msmfalcon-pinctrl.dtsi" -#include "msmfalcon-camera-sensor-cdp.dtsi" +#include "sdm660-pinctrl.dtsi" +#include "sdm660-camera-sensor-cdp.dtsi" / { }; @@ -22,9 +22,9 @@ }; &ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14200>; vddp-ref-clk-max-microamp = <100>; @@ -35,8 +35,8 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; vcc-max-microamp = <500000>; vccq2-max-microamp = <600000>; status = "ok"; @@ -68,7 +68,7 @@ qcom,platform-te-gpio = <&tlmm 59 0>; }; -&pm2falcon_wled { +&pm660l_wled { qcom,led-strings-list = [01 02]; }; @@ -88,6 +88,65 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; }; +&sdhc_1 { + /* device core power supply */ + vdd-supply = <&pm660l_l4>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <200 570000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660_l8>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 + 384000000>; + + qcom,nonremovable; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&sdhc_2 { + /* device core power supply */ + vdd-supply = <&pm660l_l5>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 900000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660l_l2>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &tlmm 54 0>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&tlmm 54 0x1>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + status = "ok"; +}; + &soc { qcom,msm-ssc-sensors { compatible = "qcom,msm-ssc-sensors"; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi b/arch/arm/boot/dts/qcom/sdm660-common.dtsi index 1a7ec9fea452..a6bc326a6508 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-common.dtsi @@ -35,7 +35,7 @@ <61 512 240000 800000>; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; - extcon = <&pmfalcon_pdphy>; + extcon = <&pm660_pdphy>; qcom,pm-qos-latency = <41>; /* CPU-CLUSTER-WFI-LVL latency +1 */ clocks = <&clock_gcc GCC_USB30_MASTER_CLK>, @@ -140,9 +140,9 @@ reg-names = "qusb_phy_base", "tcsr_clamp_dig_n_1p8", "ref_clk_addr"; - vdd-supply = <&pm2falcon_l1>; - vdda18-supply = <&pmfalcon_l10>; - vdda33-supply = <&pm2falcon_l7>; + vdd-supply = <&pm660l_l1>; + vdda18-supply = <&pm660_l10>; + vdda33-supply = <&pm660l_l7>; qcom,vdd-voltage-level = <0 925000 925000>; qcom,qusb-phy-init-seq = <0xf8 0x80 0xb3 0x84 @@ -176,8 +176,8 @@ reg-names = "qmp_phy_base", "vls_clamp_reg", "tcsr_usb3_dp_phymode"; - vdd-supply = <&pm2falcon_l1>; - core-supply = <&pmfalcon_l10>; + vdd-supply = <&pm660l_l1>; + core-supply = <&pm660_l10>; qcom,vdd-voltage-level = <0 925000 925000>; vdd-core-voltage-level = <0 1800000 1800000>; qcom,vbus-valid-override; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi b/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi index 07f3743e8d1c..be625a15f4ec 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-coresight.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-coresight.dtsi @@ -10,9 +10,9 @@ * GNU General Public License for more details. */ -#include <dt-bindings/clock/qcom,gcc-msmfalcon.h> -#include <dt-bindings/clock/qcom,gpu-msmfalcon.h> -#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h> +#include <dt-bindings/clock/qcom,gcc-sdm660.h> +#include <dt-bindings/clock/qcom,gpu-sdm660.h> +#include <dt-bindings/clock/qcom,mmcc-sdm660.h> &soc { tmc_etr: tmc@6048000 { diff --git a/arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi b/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi index 5c11131b9ddf..5c11131b9ddf 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-cdp.dts new file mode 100644 index 000000000000..2a338d2ed07b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-cdp.dts @@ -0,0 +1,73 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio Codec CDP"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <1 1>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; + +&slim_aud { + status = "disabled"; +}; + +&dai_slim { + status = "disabled"; +}; + +&wcd9335 { + status = "disabled"; +}; + +&wcd934x_cdc { + status = "disabled"; +}; + +&clock_audio { + status = "disabled"; +}; + +&wcd_rst_gpio { + status = "disabled"; +}; + +&wcd9xxx_intc { + status = "disabled"; +}; + +&tasha_snd { + status = "disabled"; +}; + +&tavil_snd { + status = "disabled"; +}; + +&int_codec { + status = "okay"; +}; + +&pmic_analog_codec { + status = "okay"; +}; + +&msm_sdw_codec { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-mtp.dts new file mode 100644 index 000000000000..3518402bd0dc --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-mtp.dts @@ -0,0 +1,74 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio Codec MTP"; + compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp"; + qcom,board-id = <8 1>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; + +&slim_aud { + status = "disabled"; +}; + +&dai_slim { + status = "disabled"; +}; + +&wcd9335 { + status = "disabled"; +}; + +&wcd934x_cdc { + status = "disabled"; +}; + +&clock_audio { + status = "disabled"; +}; + +&wcd_rst_gpio { + status = "disabled"; +}; + +&wcd9xxx_intc { + status = "disabled"; +}; + +&tasha_snd { + status = "disabled"; +}; + +&tavil_snd { + status = "disabled"; +}; + +&int_codec { + qcom,model = "sdm660-snd-card-mtp"; + status = "okay"; +}; + +&pmic_analog_codec { + status = "okay"; +}; + +&msm_sdw_codec { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-cdp.dts new file mode 100644 index 000000000000..af0467cb3278 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio Codec CDP"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <1 1>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-mtp.dts new file mode 100644 index 000000000000..c9e37963146c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-mtp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio Codec MTP"; + compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp"; + qcom,board-id = <8 1>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-rcm.dts new file mode 100644 index 000000000000..d38f16d4f628 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-pm660a-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio Codec RCM"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <21 1>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-internal-codec-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-internal-codec-rcm.dts new file mode 100644 index 000000000000..eb171c66849b --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-internal-codec-rcm.dts @@ -0,0 +1,73 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio Codec RCM"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <21 1>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; + +&slim_aud { + status = "disabled"; +}; + +&dai_slim { + status = "disabled"; +}; + +&wcd9335 { + status = "disabled"; +}; + +&wcd934x_cdc { + status = "disabled"; +}; + +&clock_audio { + status = "disabled"; +}; + +&wcd_rst_gpio { + status = "disabled"; +}; + +&wcd9xxx_intc { + status = "disabled"; +}; + +&tasha_snd { + status = "disabled"; +}; + +&tavil_snd { + status = "disabled"; +}; + +&int_codec { + status = "okay"; +}; + +&pmic_analog_codec { + status = "okay"; +}; + +&msm_sdw_codec { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/msmtriton-ion.dtsi b/arch/arm/boot/dts/qcom/sdm660-ion.dtsi index 00b9e61d01b8..00b9e61d01b8 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-ion.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-ion.dtsi diff --git a/arch/arm/boot/dts/qcom/msmfalcon-lpi.dtsi b/arch/arm/boot/dts/qcom/sdm660-lpi.dtsi index 34946c07074b..34946c07074b 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-lpi.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-lpi.dtsi diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/sdm660-mdss-panels.dtsi index 28e5f6ba8b45..84a99be7371e 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-mdss-panels.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-mdss-panels.dtsi @@ -67,7 +67,7 @@ }; &dsi_dual_nt35597_truly_video { - qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 @@ -75,7 +75,7 @@ }; &dsi_dual_nt35597_truly_cmd { - qcom,mdss-dsi-panel-timings-8996 = [23 1e 07 08 05 03 04 a0 + qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 23 1e 07 08 05 03 04 a0 diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mdss-pll.dtsi b/arch/arm/boot/dts/qcom/sdm660-mdss-pll.dtsi index 61baf6aff4b1..d2134c56541e 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-mdss-pll.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-mdss-pll.dtsi @@ -12,7 +12,7 @@ &soc { mdss_dsi0_pll: qcom,mdss_dsi_pll@c994400 { - compatible = "qcom,mdss_dsi_pll_msmfalcon"; + compatible = "qcom,mdss_dsi_pll_sdm660"; status = "ok"; label = "MDSS DSI 0 PLL"; cell-index = <0>; @@ -47,7 +47,7 @@ }; mdss_dsi1_pll: qcom,mdss_dsi_pll@c996400 { - compatible = "qcom,mdss_dsi_pll_msmfalcon"; + compatible = "qcom,mdss_dsi_pll_sdm660"; status = "ok"; label = "MDSS DSI 1 PLL"; cell-index = <1>; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mdss.dtsi b/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi index f7e1b053dbb2..ec14815a4be6 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-mdss.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi @@ -265,8 +265,8 @@ #address-cells = <1>; #size-cells = <1>; gdsc-supply = <&gdsc_mdss>; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; ranges = <0xc994000 0xc994000 0x400 0xc994400 0xc994400 0x588 0xc828000 0xc828000 0xac @@ -351,7 +351,7 @@ reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; qcom,timing-db-mode; - wqhd-vddio-supply = <&pmfalcon_l11>; + wqhd-vddio-supply = <&pm660_l11>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; qcom,mdss-mdp = <&mdss_mdp>; @@ -391,7 +391,7 @@ reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; qcom,timing-db-mode; - wqhd-vddio-supply = <&pmfalcon_l11>; + wqhd-vddio-supply = <&pm660_l11>; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; qcom,mdss-mdp = <&mdss_mdp>; @@ -446,8 +446,8 @@ qcom,mdss-fb-map = <&mdss_fb2>; gdsc-supply = <&gdsc_mdss>; - vdda-1p2-supply = <&pmfalcon_l1>; - vdda-0p9-supply = <&pm2falcon_l1>; + vdda-1p2-supply = <&pm660_l1>; + vdda-0p9-supply = <&pm660l_l1>; reg = <0xc990000 0xa84>, <0xc011000 0x910>, @@ -576,4 +576,4 @@ }; -#include "msmfalcon-mdss-panels.dtsi" +#include "sdm660-mdss-panels.dtsi" diff --git a/arch/arm/boot/dts/qcom/sdm660-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-mtp.dts new file mode 100644 index 000000000000..3e5a6e1a38b9 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L MTP"; + compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi b/arch/arm/boot/dts/qcom/sdm660-mtp.dtsi index a9d77583b590..fbf44f8350bd 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-mtp.dtsi @@ -10,8 +10,8 @@ * GNU General Public License for more details. */ -#include "msmfalcon-pinctrl.dtsi" -#include "msmfalcon-camera-sensor-mtp.dtsi" +#include "sdm660-pinctrl.dtsi" +#include "sdm660-camera-sensor-mtp.dtsi" / { }; @@ -22,9 +22,9 @@ }; &ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14200>; vddp-ref-clk-max-microamp = <100>; @@ -35,8 +35,8 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; vcc-max-microamp = <500000>; vccq2-max-microamp = <600000>; status = "ok"; @@ -68,7 +68,7 @@ qcom,platform-te-gpio = <&tlmm 59 0>; }; -&pm2falcon_wled { +&pm660l_wled { qcom,led-strings-list = [01 02]; }; @@ -88,6 +88,65 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; }; +&sdhc_1 { + /* device core power supply */ + vdd-supply = <&pm660l_l4>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <200 570000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660_l8>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 + 384000000>; + + qcom,nonremovable; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&sdhc_2 { + /* device core power supply */ + vdd-supply = <&pm660l_l5>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 900000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660l_l2>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &tlmm 54 0>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&tlmm 54 0x1>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + status = "ok"; +}; + &soc { qcom,msm-ssc-sensors { compatible = "qcom,msm-ssc-sensors"; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi b/arch/arm/boot/dts/qcom/sdm660-pinctrl.dtsi index a54079413e7c..172668f7ec0b 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-pinctrl.dtsi @@ -12,7 +12,7 @@ &soc { tlmm: pinctrl@03000000 { - compatible = "qcom,msmfalcon-pinctrl"; + compatible = "qcom,sdm660-pinctrl"; reg = <0x03000000 0xc00000>; interrupts = <0 208 0>; gpio-controller; @@ -126,6 +126,80 @@ }; }; + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + drive-strength = <16>; /* 16 MA */ + bias-disable; /* NO pull */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <10>; /* 10 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio54"; + function = "gpio"; + }; + + config { + pins = "gpio54"; + drive-strength = <2>; + bias-disable; + }; + }; + /* I2C CONFIGURATION */ i2c_1 { i2c_1_active: i2c_1_active { diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi b/arch/arm/boot/dts/qcom/sdm660-pm.dtsi index 6a9fc5bde361..6a9fc5bde361 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-pm.dtsi diff --git a/arch/arm/boot/dts/qcom/sdm660-pm660a-cdp.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-cdp.dts new file mode 100644 index 000000000000..7621c8aef432 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-cdp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A CDP"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <1 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-pm660a-mtp.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-mtp.dts new file mode 100644 index 000000000000..1ea6dbde11ce --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-mtp.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-mtp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A MTP"; + compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp"; + qcom,board-id = <8 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-pm660a-qrd.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-qrd.dts new file mode 100644 index 000000000000..48e02bbdfbfe --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-qrd.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-qrd.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A QRD"; + compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd"; + qcom,board-id = <0x0012000b 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-pm660a-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-rcm.dts new file mode 100644 index 000000000000..0b65b4a3631c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A RCM"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rumi.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-rumi.dts index b81a92a4aa7c..16f1efb92f74 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-rumi.dts +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-rumi.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-pinctrl.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sdm660.dtsi" +#include "sdm660-pinctrl.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON RUMI"; - compatible = "qcom,msmfalcon-rumi", "qcom,msmfalcon", "qcom,rumi"; + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A RUMI"; + compatible = "qcom,sdm660-rumi", "qcom,sdm660", "qcom,rumi"; qcom,board-id = <15 0>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; @@ -69,12 +69,12 @@ &sdhc_1 { /* device core power supply */ - vdd-supply = <&pm2falcon_l4>; + vdd-supply = <&pm660l_l4>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ - vdd-io-supply = <&pmfalcon_l8>; + vdd-io-supply = <&pm660_l8>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; @@ -98,11 +98,11 @@ clock-output-names = "gcc_clocks"; }; -&pmfalcon_charger { +&pm660_charger { status = "disabled"; }; -&pmfalcon_fg { +&pm660_fg { status = "disabled"; }; @@ -111,7 +111,7 @@ clock-output-names = "gfx_clocks"; }; -&pmfalcon_pdphy { +&pm660_pdphy { status = "disabled"; }; @@ -121,9 +121,9 @@ }; &ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14200>; vddp-ref-clk-max-microamp = <100>; @@ -133,8 +133,8 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; vcc-max-microamp = <500000>; vccq2-max-microamp = <600000>; qcom,disable-lpm; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-sim.dts b/arch/arm/boot/dts/qcom/sdm660-pm660a-sim.dts index b47c1d328201..2e2e1ac3993c 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-pm3falcon-sim.dts +++ b/arch/arm/boot/dts/qcom/sdm660-pm660a-sim.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-pinctrl.dtsi" -#include "msm-pm3falcon.dtsi" +#include "sdm660.dtsi" +#include "sdm660-pinctrl.dtsi" +#include "msm-pm660a.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM3FALCON SIM"; - compatible = "qcom,msmfalcon-sim", "qcom,msmfalcon", "qcom,sim"; + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A SIM"; + compatible = "qcom,sdm660-sim", "qcom,sdm660", "qcom,sim"; qcom,board-id = <16 0>; qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>; @@ -53,12 +53,12 @@ &sdhc_1 { /* device core power supply */ - vdd-supply = <&pm2falcon_l4>; + vdd-supply = <&pm660l_l4>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ - vdd-io-supply = <&pmfalcon_l8>; + vdd-io-supply = <&pm660_l8>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; @@ -77,22 +77,22 @@ status = "ok"; }; -&pmfalcon_charger { +&pm660_charger { status = "disabled"; }; -&pmfalcon_fg { +&pm660_fg { status = "disabled"; }; -&pmfalcon_pdphy { +&pm660_pdphy { status = "disabled"; }; &ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14200>; vddp-ref-clk-max-microamp = <100>; @@ -103,8 +103,8 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; vcc-max-microamp = <500000>; vccq2-max-microamp = <600000>; status = "ok"; diff --git a/arch/arm/boot/dts/qcom/sdm660-qrd.dts b/arch/arm/boot/dts/qcom/sdm660-qrd.dts new file mode 100644 index 000000000000..a8fde35ba49c --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-qrd.dts @@ -0,0 +1,29 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L QRD"; + compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd"; + qcom,board-id = <0x1000b 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; + +&pm660l_wled { + qcom,led-strings-list = [00 01]; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi b/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi new file mode 100644 index 000000000000..d3d6bf6ca10e --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-qrd.dtsi @@ -0,0 +1,148 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "sdm660-pinctrl.dtsi" +#include "sdm660-camera-sensor-qrd.dtsi" +/ { +}; + +&uartblsp1dm1 { + status = "ok"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&sdhc_1 { + /* device core power supply */ + vdd-supply = <&pm660l_l4>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <200 570000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660_l8>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <200 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 + 384000000>; + + qcom,nonremovable; + qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; + + status = "ok"; +}; + +&sdhc_2 { + /* device core power supply */ + vdd-supply = <&pm660l_l5>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 900000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660l_l2>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &tlmm 54 0>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&tlmm 54 0x1>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + status = "ok"; +}; + +&ufsphy1 { + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + status = "ok"; +}; + +&ufs1 { + vdd-hba-supply = <&gdsc_ufs>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; + vcc-max-microamp = <500000>; + vccq2-max-microamp = <600000>; + status = "ok"; +}; + +&soc { +}; + +&pm660l_gpios { + /* GPIO 7 for VOL_UP */ + gpio@c600 { + status = "ok"; + qcom,mode = <0>; + qcom,pull = <0>; + qcom,vin-sel = <0>; + qcom,src-sel = <0>; + qcom,out-strength = <1>; + }; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + status = "ok"; + + vol_up { + label = "volume_up"; + gpios = <&pm660l_gpios 7 0x1>; + linux,input-type = <1>; + linux,code = <115>; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; +}; + +/ { + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + + #include "fg-gen3-batterydata-qrd-skuk-4v4-3000mah.dtsi" + }; +}; + +&pm660_fg { + qcom,battery-data = <&qrd_batterydata>; + qcom,fg-jeita-thresholds = <0 5 55 55>; + qcom,fg-cutoff-voltage = <3700>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-rcm.dts b/arch/arm/boot/dts/qcom/sdm660-rcm.dts new file mode 100644 index 000000000000..a3f9445d4164 --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-rcm.dts @@ -0,0 +1,25 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L RCM"; + compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp"; + qcom,board-id = <21 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, + <0x0001001b 0x0201011a 0x0 0x0>; +}; diff --git a/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi b/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi new file mode 100644 index 000000000000..479a9fdd91ca --- /dev/null +++ b/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi @@ -0,0 +1,791 @@ +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/clock/qcom,gcc-sdm660.h> +#include <dt-bindings/clock/qcom,gpu-sdm660.h> +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +&rpm_bus { + rpm-regulator-smpa4 { + status = "okay"; + pm660_s4: regulator-s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa5 { + status = "okay"; + pm660_s5: regulator-s5 { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa6 { + status = "okay"; + pm660_s6: regulator-s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + status = "okay"; + }; + }; + + rpm-regulator-smpb1 { + status = "okay"; + pm660l_s1: regulator-s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + status = "okay"; + }; + }; + + rpm-regulator-smpb2 { + status = "okay"; + pm660l_s2: regulator-s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + status = "okay"; + }; + }; + + /* PM660L S3 + S4 - VDD_CX supply */ + rpm-regulator-smpb3 { + status = "okay"; + pm660l_s3_level: regulator-s3-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s3_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + pm660l_s3_floor_level: regulator-s3-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s3_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm660l_s3_level_ao: regulator-s3-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s3_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + }; + + /* PM660L S5 - VDD_MX supply */ + rpm-regulator-smpb5 { + status = "okay"; + pm660l_s5_level: regulator-s5-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s5_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + pm660l_s5_floor_level: regulator-s5-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s5_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + pm660l_s5_level_ao: regulator-s5-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_s5_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa1 { + status = "okay"; + pm660_l1: regulator-l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + pm660_l2: regulator-l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + pm660_l3: regulator-l3 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + status = "okay"; + }; + }; + + /* TODO: remove if ADRASTEA CX/MX not voted from APPS */ + rpm-regulator-ldoa5 { + status = "okay"; + pm660_l5: regulator-l5 { + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + pm660_l6: regulator-l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + status = "okay"; + }; + + pm660_l6_pin_ctrl: regulator-l6-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l6_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + /* Force NPM follows HW_EN1 */ + qcom,init-pin-ctrl-mode = <2>; + /* Enable follows HW_EN1 */ + qcom,enable-with-pin-ctrl = <0 2>; + }; + }; + + rpm-regulator-ldoa7 { + status = "okay"; + pm660_l7: regulator-l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa8 { + status = "okay"; + pm660_l8: regulator-l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa9 { + status = "okay"; + pm660_l9: regulator-l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + status = "okay"; + }; + + pm660_l9_pin_ctrl: regulator-l9-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l9_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + /* Force NPM follows HW_EN1 */ + qcom,init-pin-ctrl-mode = <2>; + /* Enable follows HW_EN1 */ + qcom,enable-with-pin-ctrl = <0 2>; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + pm660_l10: regulator-l10 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + pm660_l11: regulator-l11 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + pm660_l12: regulator-l12 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + pm660_l13: regulator-l13 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + pm660_l14: regulator-l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1900000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + pm660_l15: regulator-l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + pm660_l17: regulator-l17 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + pm660_l19: regulator-l19 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + status = "okay"; + }; + + pm660_l19_pin_ctrl: regulator-l19-pin-ctrl { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660_l19_pin_ctrl"; + qcom,set = <3>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + /* Force NPM follows HW_EN1 */ + qcom,init-pin-ctrl-mode = <2>; + /* Enable follows HW_EN1 */ + qcom,enable-with-pin-ctrl = <0 2>; + }; + }; + + rpm-regulator-ldob1 { + status = "okay"; + pm660l_l1: regulator-l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob2 { + status = "okay"; + pm660l_l2: regulator-l2 { + regulator-min-microvolt = <350000>; + regulator-max-microvolt = <3100000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob3 { + status = "okay"; + pm660l_l3: regulator-l3 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <3600000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob4 { + status = "okay"; + pm660l_l4: regulator-l4 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob5 { + status = "okay"; + pm660l_l5: regulator-l5 { + regulator-min-microvolt = <1721000>; + regulator-max-microvolt = <3600000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob6 { + status = "okay"; + pm660l_l6: regulator-l6 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob7 { + status = "okay"; + pm660l_l7: regulator-l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + status = "okay"; + }; + }; + + rpm-regulator-ldob8 { + status = "okay"; + pm660l_l8: regulator-l8 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + status = "okay"; + }; + }; + + /* PM660L L9 = VDD_SSC_CX supply */ + rpm-regulator-ldob9 { + status = "okay"; + pm660l_l9_level: regulator-l9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l9_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + pm660l_l9_floor_level: regulator-l9-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l9_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + /* PM660L L10 = VDD_SSC_MX supply */ + rpm-regulator-ldob10 { + status = "okay"; + pm660l_l10_level: regulator-l10-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l10_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-level; + }; + + pm660l_l10_floor_level: regulator-l10-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_l10_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + <RPM_SMD_REGULATOR_LEVEL_RETENTION>; + regulator-max-microvolt = + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + }; + + rpm-regulator-bobb { + status = "okay"; + pm660l_bob: regulator-bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + status = "okay"; + }; + + pm660l_bob_pin1: regulator-bob-pin1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_bob_pin1"; + qcom,set = <3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + qcom,use-pin-ctrl-voltage1; + }; + + pm660l_bob_pin2: regulator-bob-pin2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_bob_pin2"; + qcom,set = <3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + qcom,use-pin-ctrl-voltage2; + }; + + pm660l_bob_pin3: regulator-bob-pin3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm660l_bob_pin3"; + qcom,set = <3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + qcom,use-pin-ctrl-voltage3; + }; + }; +}; + +&pm660_charger { + smb2_vbus: qcom,smb2-vbus { + regulator-name = "smb2-vbus"; + }; + + smb2_vconn: qcom,smb2-vconn { + regulator-name = "smb2-vconn"; + }; +}; + +/* Stub regulators */ +/ { + /* GFX Supply */ + gfx_stub_vreg: regulator-gfx-stub { + compatible = "qcom,stub-regulator"; + regulator-name = "gfx_stub_corner"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1070000>; + }; +}; + +&soc { + /* MEM ACC regulators */ + gfx_mem_acc_vreg: regulator@01fcf004 { + compatible = "qcom,mem-acc-regulator"; + reg = <0x01fcf004 0x4>; + reg-names = "acc-sel-l1"; + regulator-name = "gfx_mem_acc_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <2>; + + qcom,corner-acc-map = <0x1 0x0>; + qcom,acc-sel-l1-bit-pos = <0>; + qcom,acc-sel-l1-bit-size = <1>; + }; + + gfx_ldo_vreg: ldo@0506e000 { + compatible = "qcom,sdm660-gfx-ldo"; + reg = <0x0506e000 0x34>; + reg-names = "ldo_addr"; + regulator-name = "msm_gfx_ldo"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <925000>; + }; + +/* CPR controller regulators */ + /* MMSS CPR Controller node */ + gfx_cpr: cpr4-ctrl@05061000 { + compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator"; + reg = <0x05061000 0x4000>, <0x00784000 0x1000>; + reg-names = "cpr_ctrl", "fuse_base"; + clocks = <&clock_gfx GPUCC_RBCPR_CLK>, + <&clock_rpmcc RPM_CNOC_CLK>; + clock-names = "core_clk", "bus_clk"; + interrupts = <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "cpr"; + qcom,cpr-ctrl-name = "gfx"; + + + qcom,cpr-sensor-time = <1000>; + qcom,cpr-loop-time = <5000000>; + qcom,cpr-idle-cycles = <15>; + qcom,cpr-step-quot-init-min = <12>; + qcom,cpr-step-quot-init-max = <14>; + qcom,cpr-count-mode = <0>; /* All at once */ + qcom,cpr-count-repeat = <14>; + + vdd-supply = <&gfx_stub_vreg>; + mem-acc-supply = <&gfx_mem_acc_vreg>; + system-supply = <&pm660l_s3_level>; /* vdd_cx */ + qcom,voltage-step = <5000>; + vdd-thread0-ldo-supply = <&gfx_ldo_vreg>; + + thread@0 { + qcom,cpr-thread-id = <0>; + qcom,cpr-consecutive-up = <0>; + qcom,cpr-consecutive-down = <2>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <2>; + + gfx_vreg_corner: regulator { + regulator-name = "gfx_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + + qcom,cpr-fuse-corners = <6>; + qcom,cpr-fuse-combos = <8>; + qcom,cpr-corners = <7>; + + qcom,cpr-corner-fmax-map = <1 2 3 4 5 6>; + + qcom,cpr-voltage-ceiling = + <585000 645000 725000 790000 + 870000 925000 1070000>; + qcom,cpr-voltage-floor = + <504000 504000 596000 652000 + 712000 744000 1070000>; + + qcom,mem-acc-voltage = <1 1 1 2 2 2 2>; + qcom,system-voltage = + <RPM_SMD_REGULATOR_LEVEL_LOW_SVS>, + <RPM_SMD_REGULATOR_LEVEL_LOW_SVS>, + <RPM_SMD_REGULATOR_LEVEL_SVS>, + <RPM_SMD_REGULATOR_LEVEL_SVS_PLUS>, + <RPM_SMD_REGULATOR_LEVEL_NOM>, + <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS>, + <RPM_SMD_REGULATOR_LEVEL_TURBO>; + + qcom,corner-frequencies = + <160000000 266000000 370000000 + 465000000 588000000 647000000 + 800000000>; + + qcom,cpr-target-quotients = + <0 0 0 0 0 0 202 193 + 331 326 337 345 0 0 0 0>, + <0 0 0 0 0 0 202 193 + 331 326 337 345 0 0 0 0>, + <0 0 0 0 0 0 317 300 + 476 463 489 489 0 0 0 0>, + <0 0 0 0 0 0 411 387 + 595 572 611 602 0 0 0 0>, + <0 0 0 0 0 0 522 489 + 727 696 748 732 0 0 0 0>, + <0 0 0 0 0 0 606 568 + 818 786 848 826 0 0 0 0>, + <0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0>; + + qcom,cpr-ro-scaling-factor = + < 0 0 0 0 0 0 1740 1620 + 2040 1960 2160 2040 0 0 0 0>, + < 0 0 0 0 0 0 1740 1620 + 2040 1960 2160 2040 0 0 0 0>, + < 0 0 0 0 0 0 1740 1620 + 2040 1960 2160 2040 0 0 0 0>, + < 0 0 0 0 0 0 1740 1620 + 2040 1960 2160 2040 0 0 0 0>, + < 0 0 0 0 0 0 1740 1620 + 2040 1960 2160 2040 0 0 0 0>, + < 0 0 0 0 0 0 1740 1620 + 2040 1960 2160 2040 0 0 0 0>, + < 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0>; + + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + qcom,cpr-corner-allow-ldo-mode = + <0 0 0 0 0 0 0>; + qcom,cpr-corner-allow-closed-loop = + <0 0 0 0 0 0 0>; + }; + }; + }; + + /* APC0 CPR Controller node for Silver cluster */ + apc0_cpr: cprh-ctrl@179c8000 { + compatible = "qcom,cprh-sdm660-kbss-regulator"; + reg = <0x179c8000 0x4000>, <0x00784000 0x1000>; + reg-names = "cpr_ctrl", "fuse_base"; + clocks = <&clock_gcc GCC_HMSS_RBCPR_CLK>; + clock-names = "core_clk"; + qcom,cpr-ctrl-name = "apc0"; + qcom,cpr-controller-id = <0>; + + qcom,cpr-sensor-time = <1000>; + qcom,cpr-loop-time = <5000000>; + qcom,cpr-idle-cycles = <15>; + qcom,cpr-up-down-delay-time = <3000>; + qcom,cpr-step-quot-init-min = <12>; + qcom,cpr-step-quot-init-max = <14>; + qcom,cpr-count-mode = <0>; /* All at once */ + qcom,cpr-count-repeat = <14>; + qcom,cpr-down-error-step-limit = <1>; + qcom,cpr-up-error-step-limit = <1>; + qcom,cpr-corner-switch-delay-time = <1042>; + qcom,cpr-voltage-settling-time = <1760>; + + qcom,apm-threshold-voltage = <872000>; + qcom,apm-crossover-voltage = <872000>; + qcom,apm-hysteresis-voltage = <20000>; + qcom,voltage-step = <4000>; + qcom,voltage-base = <400000>; + qcom,cpr-saw-use-unit-mV; + + qcom,cpr-panic-reg-addr-list = + <0x179cbaa4 0x17912c18>; + qcom,cpr-panic-reg-name-list = + "PWR_CPRH_STATUS", "APCLUS0_L2_SAW4_PMIC_STS"; + + thread@0 { + qcom,cpr-thread-id = <0>; + qcom,cpr-consecutive-up = <0>; + qcom,cpr-consecutive-down = <2>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <2>; + + apc0_pwrcl_vreg: regulator { + regulator-name = "apc0_pwrcl_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <8>; + + qcom,cpr-fuse-corners = <5>; + qcom,cpr-fuse-combos = <16>; + qcom,cpr-speed-bins = <2>; + qcom,cpr-speed-bin-corners = <8 8>; + qcom,cpr-corners = <8>; + qcom,cpr-corner-fmax-map = <2 3 4 5 8>; + + qcom,cpr-voltage-ceiling = + <724000 724000 724000 788000 868000 + 924000 988000 1068000>; + + qcom,cpr-voltage-floor = + <588000 588000 596000 652000 712000 + 744000 784000 844000>; + + qcom,corner-frequencies = + <300000000 633600000 902400000 + 1113600000 1401600000 1536000000 + 1747200000 1843200000>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + }; + }; + }; + + /* APC1 CPR Controller node for Gold cluster */ + apc1_cpr: cprh-ctrl@179c4000 { + compatible = "qcom,cprh-sdm660-kbss-regulator"; + reg = <0x179c4000 0x4000>, <0x00784000 0x1000>; + reg-names = "cpr_ctrl", "fuse_base"; + clocks = <&clock_gcc GCC_HMSS_RBCPR_CLK>; + clock-names = "core_clk"; + qcom,cpr-ctrl-name = "apc1"; + qcom,cpr-controller-id = <1>; + + qcom,cpr-sensor-time = <1000>; + qcom,cpr-loop-time = <5000000>; + qcom,cpr-idle-cycles = <15>; + qcom,cpr-up-down-delay-time = <3000>; + qcom,cpr-step-quot-init-min = <12>; + qcom,cpr-step-quot-init-max = <14>; + qcom,cpr-count-mode = <0>; /* All at once */ + qcom,cpr-count-repeat = <14>; + qcom,cpr-down-error-step-limit = <1>; + qcom,cpr-up-error-step-limit = <1>; + qcom,cpr-corner-switch-delay-time = <1042>; + qcom,cpr-voltage-settling-time = <1760>; + + qcom,apm-threshold-voltage = <872000>; + qcom,apm-crossover-voltage = <872000>; + qcom,apm-hysteresis-voltage = <20000>; + qcom,voltage-step = <4000>; + qcom,voltage-base = <400000>; + qcom,cpr-saw-use-unit-mV; + + qcom,cpr-panic-reg-addr-list = + <0x179c7aa4 0x17812c18>; + qcom,cpr-panic-reg-name-list = + "PERF_CPRH_STATUS", "APCLUS1_L2_SAW4_PMIC_STS"; + + thread@0 { + qcom,cpr-thread-id = <0>; + qcom,cpr-consecutive-up = <0>; + qcom,cpr-consecutive-down = <2>; + qcom,cpr-up-threshold = <2>; + qcom,cpr-down-threshold = <2>; + + apc1_perfcl_vreg: regulator { + regulator-name = "apc1_perfcl_corner"; + regulator-min-microvolt = <1>; + regulator-max-microvolt = <7>; + + qcom,cpr-fuse-corners = <5>; + qcom,cpr-fuse-combos = <16>; + qcom,cpr-speed-bins = <2>; + qcom,cpr-speed-bin-corners = <7 7>; + qcom,cpr-corners = <7>; + qcom,cpr-corner-fmax-map = <2 3 4 6 7>; + + qcom,cpr-voltage-ceiling = + <724000 724000 788000 868000 + 924000 988000 1068000>; + + qcom,cpr-voltage-floor = + <588000 596000 652000 712000 + 744000 784000 844000>; + + qcom,corner-frequencies = + /* Speed bin 0 */ + <300000000 1113600000 1401600000 + 1747200000 1958400000 2150400000 + 2457600000>, + + /* Speed bin 1 */ + <300000000 1113600000 1401600000 + 1747200000 1958400000 2150400000 + 2208000000>; + + qcom,allow-voltage-interpolation; + qcom,allow-quotient-interpolation; + qcom,cpr-scaled-open-loop-voltage-as-ceiling; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts b/arch/arm/boot/dts/qcom/sdm660-rumi.dts index c371ddeda563..80202cc87322 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts +++ b/arch/arm/boot/dts/qcom/sdm660-rumi.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-pinctrl.dtsi" +#include "sdm660.dtsi" +#include "sdm660-pinctrl.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON RUMI"; - compatible = "qcom,msmfalcon-rumi", "qcom,msmfalcon", "qcom,rumi"; + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L RUMI"; + compatible = "qcom,sdm660-rumi", "qcom,sdm660", "qcom,rumi"; qcom,board-id = <15 0>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; @@ -69,12 +69,12 @@ &sdhc_1 { /* device core power supply */ - vdd-supply = <&pm2falcon_l4>; + vdd-supply = <&pm660l_l4>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ - vdd-io-supply = <&pmfalcon_l8>; + vdd-io-supply = <&pm660_l8>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; @@ -84,7 +84,7 @@ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; - qcom,clk-rates = <400000 20000000 25000000 50000000 192000000 + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>; qcom,nonremovable; @@ -93,16 +93,49 @@ status = "ok"; }; +&sdhc_2 { + /* device core power supply */ + vdd-supply = <&pm660l_l5>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 900000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660l_l2>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &tlmm 54 0>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&tlmm 54 0x1>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + status = "ok"; +}; + &clock_gcc { compatible = "qcom,dummycc"; clock-output-names = "gcc_clocks"; }; -&pmfalcon_charger { +&pm660_charger { status = "disabled"; }; -&pmfalcon_fg { +&pm660_fg { status = "disabled"; }; @@ -111,7 +144,7 @@ clock-output-names = "gfx_clocks"; }; -&pmfalcon_pdphy { +&pm660_pdphy { status = "disabled"; }; @@ -121,9 +154,9 @@ }; &ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14200>; vddp-ref-clk-max-microamp = <100>; @@ -133,8 +166,8 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; vcc-max-microamp = <500000>; vccq2-max-microamp = <600000>; qcom,disable-lpm; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts b/arch/arm/boot/dts/qcom/sdm660-sim.dts index 596aae818fab..a3ee70d0bed0 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts +++ b/arch/arm/boot/dts/qcom/sdm660-sim.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmfalcon.dtsi" -#include "msmfalcon-pinctrl.dtsi" +#include "sdm660.dtsi" +#include "sdm660-pinctrl.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM FALCON PMFALCON + PM2FALCON SIM"; - compatible = "qcom,msmfalcon-sim", "qcom,msmfalcon", "qcom,sim"; + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L SIM"; + compatible = "qcom,sdm660-sim", "qcom,sdm660", "qcom,sim"; qcom,board-id = <16 0>; qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>; @@ -53,12 +53,12 @@ &sdhc_1 { /* device core power supply */ - vdd-supply = <&pm2falcon_l4>; + vdd-supply = <&pm660l_l4>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <200 570000>; /* device communication power supply */ - vdd-io-supply = <&pmfalcon_l8>; + vdd-io-supply = <&pm660_l8>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 1800000>; @@ -68,7 +68,7 @@ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; - qcom,clk-rates = <400000 20000000 25000000 50000000 192000000 + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 384000000>; qcom,nonremovable; @@ -77,22 +77,55 @@ status = "ok"; }; -&pmfalcon_charger { +&sdhc_2 { + /* device core power supply */ + vdd-supply = <&pm660l_l5>; + qcom,vdd-voltage-level = <2950000 2950000>; + qcom,vdd-current-level = <15000 900000>; + + /* device communication power supply */ + vdd-io-supply = <&pm660l_l2>; + qcom,vdd-io-voltage-level = <1800000 2950000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + #address-cells = <0>; + interrupt-parent = <&sdhc_2>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 125 0 + 1 &intc 0 221 0 + 2 &tlmm 54 0>; + interrupt-names = "hc_irq", "pwr_irq", "status_irq"; + cd-gpios = <&tlmm 54 0x1>; + + qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 + 200000000>; + qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; + + status = "ok"; +}; + +&pm660_charger { status = "disabled"; }; -&pmfalcon_fg { +&pm660_fg { status = "disabled"; }; -&pmfalcon_pdphy { +&pm660_pdphy { status = "disabled"; }; &ufsphy1 { - vdda-phy-supply = <&pm2falcon_l1>; - vdda-pll-supply = <&pmfalcon_l10>; - vddp-ref-clk-supply = <&pmfalcon_l1>; + vdda-phy-supply = <&pm660l_l1>; + vdda-pll-supply = <&pm660_l10>; + vddp-ref-clk-supply = <&pm660_l1>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14200>; vddp-ref-clk-max-microamp = <100>; @@ -103,8 +136,8 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pm2falcon_l4>; - vccq2-supply = <&pmfalcon_l8>; + vcc-supply = <&pm660l_l4>; + vccq2-supply = <&pm660_l8>; vcc-max-microamp = <500000>; vccq2-max-microamp = <600000>; status = "ok"; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-smp2p.dtsi b/arch/arm/boot/dts/qcom/sdm660-smp2p.dtsi index b43fae954ec2..b43fae954ec2 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-smp2p.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-smp2p.dtsi diff --git a/arch/arm/boot/dts/qcom/msmfalcon-vidc.dtsi b/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi index 9a9c96f5181d..10cf4de2a8e0 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-vidc.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-vidc.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -12,8 +12,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/msm/msm-bus-ids.h> -#include <dt-bindings/clock/qcom,gcc-msmfalcon.h> -#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h> +#include <dt-bindings/clock/qcom,gcc-sdm660.h> +#include <dt-bindings/clock/qcom,mmcc-sdm660.h> #include <dt-bindings/clock/qcom,rpmcc.h> @@ -28,9 +28,9 @@ qcom,firmware-name = "venus"; qcom,sw-power-collapse; qcom,reg-presets = - <0x80010 0x00000003>, - <0x80018 0x05555556>, - <0x8001c 0x05555556>; + <0x80010 0x001f001f>, + <0x80018 0x00000156>, + <0x8001c 0x00000156>; qcom,max-hw-load = <1036800>; /* Full 4k @ 30 */ qcom,allowed-clock-rates = diff --git a/arch/arm/boot/dts/qcom/msmfalcon-wcd.dtsi b/arch/arm/boot/dts/qcom/sdm660-wcd.dtsi index 006bf0175874..006bf0175874 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-wcd.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-wcd.dtsi diff --git a/arch/arm/boot/dts/qcom/msmfalcon-wsa881x.dtsi b/arch/arm/boot/dts/qcom/sdm660-wsa881x.dtsi index 123f922facdd..a71aa7ded60b 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-wsa881x.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-wsa881x.dtsi @@ -10,7 +10,7 @@ * GNU General Public License for more details. */ -#include "msmfalcon-wcd.dtsi" +#include "sdm660-wcd.dtsi" &slim_aud { tasha_codec { diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/sdm660.dtsi index b57e7d033c70..54aa729352a3 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -11,23 +11,25 @@ */ #include "skeleton64.dtsi" -#include <dt-bindings/clock/qcom,gcc-msmfalcon.h> -#include <dt-bindings/clock/qcom,gpu-msmfalcon.h> -#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h> +#include <dt-bindings/clock/qcom,gcc-sdm660.h> +#include <dt-bindings/clock/qcom,gpu-sdm660.h> +#include <dt-bindings/clock/qcom,mmcc-sdm660.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/clock/audio-ext-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> +#include <dt-bindings/clock/qcom,cpu-osm.h> / { - model = "Qualcomm Technologies, Inc. MSM FALCON"; - compatible = "qcom,msmfalcon"; + model = "Qualcomm Technologies, Inc. SDM 660"; + compatible = "qcom,sdm660"; qcom,msm-id = <317 0x0>; interrupt-parent = <&intc>; aliases { serial0 = &uartblsp1dm1; sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ + sdhc2 = &sdhc_2; /* SDC2 for SD card */ }; chosen { @@ -327,10 +329,10 @@ bluetooth: bt_wcn3990 { compatible = "qca,wcn3990"; - qca,bt-vdd-core-supply = <&pmfalcon_l9_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmfalcon_l6_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmfalcon_l19_pin_ctrl>; - qca,bt-chip-pwd-supply = <&pm2falcon_bob_pin1>; + qca,bt-vdd-core-supply = <&pm660_l9_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pm660_l6_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pm660_l19_pin_ctrl>; + qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>; clocks = <&clock_rpmcc RPM_RF_CLK1>; clock-names = "rf_clk1"; @@ -345,8 +347,8 @@ }; }; -#include "msmfalcon-smp2p.dtsi" -#include "msmfalcon-coresight.dtsi" +#include "sdm660-smp2p.dtsi" +#include "sdm660-coresight.dtsi" &soc { #address-cells = <1>; #size-cells = <1>; @@ -532,7 +534,7 @@ }; tsens: tsens@10ad000 { - compatible = "qcom,msmfalcon-tsens"; + compatible = "qcom,sdm660-tsens"; reg = <0x10ad000 0x2000>, <0x784240 0x1000>; reg-names = "tsens_physical", "tsens_eeprom_physical"; @@ -628,7 +630,7 @@ }; sensor_information14: qcom,sensor-information-14 { qcom,sensor-type = "alarm"; - qcom,sensor-name = "pmfalcon_tz"; + qcom,sensor-name = "pm660_tz"; qcom,scaling-factor = <1000>; }; sensor_information15: qcom,sensor-information-15 { @@ -703,7 +705,7 @@ qcom,vdd-restriction-temp = <5>; qcom,vdd-restriction-temp-hysteresis = <10>; - vdd-dig-supply = <&pm2falcon_s3_floor_level>; + vdd-dig-supply = <&pm660l_s3_floor_level>; vdd-gfx-supply = <&gfx_vreg_corner>; qcom,vdd-dig-rstr{ @@ -881,34 +883,34 @@ }; clock_rpmcc: qcom,rpmcc { - compatible = "qcom,rpmcc-msmfalcon", "qcom,rpmcc"; + compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; #clock-cells = <1>; }; clock_gcc: clock-controller@100000 { - compatible = "qcom,gcc-msmfalcon", "syscon"; + compatible = "qcom,gcc-sdm660", "syscon"; reg = <0x100000 0x94000>; - vdd_dig-supply = <&pm2falcon_s3_level>; - vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>; + vdd_dig-supply = <&pm660l_s3_level>; + vdd_dig_ao-supply = <&pm660l_s3_level_ao>; #clock-cells = <1>; #reset-cells = <1>; }; clock_mmss: clock-controller@c8c0000 { - compatible = "qcom,mmcc-msmfalcon"; + compatible = "qcom,mmcc-sdm660"; reg = <0xc8c0000 0x40000>; - vdd_mx_mmss-supply = <&pm2falcon_s5_level>; - vdd_dig_mmss-supply = <&pm2falcon_s3_level>; - vdda-supply = <&pmfalcon_l10>; + vdd_mx_mmss-supply = <&pm660l_s5_level>; + vdd_dig_mmss-supply = <&pm660l_s3_level>; + vdda-supply = <&pm660_l10>; #clock-cells = <1>; #reset-cells = <1>; }; clock_gfx: clock-controller@5065000 { - compatible = "qcom,gpucc-msmfalcon"; + compatible = "qcom,gpucc-sdm660"; reg = <0x5065000 0x10000>; - vdd_dig_gfx-supply = <&pm2falcon_s3_level>; - vdd_mx_gfx-supply = <&pm2falcon_s5_level>; + vdd_dig_gfx-supply = <&pm660l_s3_level>; + vdd_mx_gfx-supply = <&pm660l_s5_level>; vdd_gfx-supply = <&gfx_vreg_corner>; qcom,gfxfreq-corner = < 0 0>, @@ -940,7 +942,7 @@ }; clock_debug: qcom,cc-debug@62000 { - compatible = "qcom,gcc-debug-msmfalcon"; + compatible = "qcom,gcc-debug-sdm660"; reg = <0x62000 0x4>; reg-names = "dbg_offset"; clocks = <&clock_rpmcc RPM_XO_CLK_SRC>; @@ -1083,7 +1085,7 @@ }; }; - clock_cpu: qcom,clk-cpu-falcon@179c0000 { + clock_cpu: qcom,clk-cpu-660@179c0000 { compatible = "qcom,clk-cpu-osm"; status = "disabled"; reg = <0x179c0000 0x4000>, <0x17916000 0x1000>, @@ -1092,7 +1094,8 @@ reg-names = "osm", "pwrcl_pll", "perfcl_pll", "apcs_common", "perfcl_efuse"; - /* ToDo: Add power and perf supply rails */ + vdd-pwrcl-supply = <&apc0_pwrcl_vreg>; + vdd-perfcl-supply = <&apc1_perfcl_vreg>; interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; @@ -1100,31 +1103,31 @@ qcom,pwrcl-speedbin0-v0 = < 300000000 0x0004000f 0x01200020 0x1 1 >, - < 633600000 0x05040021 0x03200020 0x1 1 >, - < 902400000 0x0404002f 0x04260026 0x1 2 >, - < 1113600000 0x0404003a 0x052e002e 0x2 3 >, - < 1401600000 0x04040049 0x073a003a 0x2 4 >, - < 1536000000 0x04040050 0x08400040 0x3 5 >, - < 1747200000 0x0404005b 0x09480048 0x3 6 >, - < 1843200000 0x04040060 0x094c004c 0x3 7 >; + < 633600000 0x05040021 0x03200020 0x1 2 >, + < 902400000 0x0404002f 0x04260026 0x1 3 >, + < 1113600000 0x0404003a 0x052e002e 0x2 4 >, + < 1401600000 0x04040049 0x073a003a 0x2 5 >, + < 1536000000 0x04040050 0x08400040 0x3 6 >, + < 1747200000 0x0404005b 0x09480048 0x3 7 >, + < 1843200000 0x04040060 0x094c004c 0x3 8 >; qcom,perfcl-speedbin0-v0 = < 300000000 0x0004000f 0x01200020 0x1 1 >, - < 1113600000 0x0404003a 0x052e002e 0x1 1 >, - < 1401600000 0x04040049 0x073a003a 0x2 2 >, - < 1747200000 0x0404005b 0x09480048 0x2 3 >, - < 1958400000 0x04040066 0x0a510051 0x3 4 >, - < 2150400000 0x04040070 0x0b590059 0x3 5 >, - < 2457600000 0x04040080 0x0c660066 0x3 6 >; + < 1113600000 0x0404003a 0x052e002e 0x1 2 >, + < 1401600000 0x04040049 0x073a003a 0x2 3 >, + < 1747200000 0x0404005b 0x09480048 0x2 4 >, + < 1958400000 0x04040066 0x0a510051 0x3 5 >, + < 2150400000 0x04040070 0x0b590059 0x3 6 >, + < 2457600000 0x04040080 0x0c660066 0x3 7 >; qcom,perfcl-speedbin1-v0 = < 300000000 0x0004000f 0x01200020 0x1 1 >, - < 1113600000 0x0404003a 0x052e002e 0x1 1 >, - < 1401600000 0x04040049 0x073a003a 0x2 2 >, - < 1747200000 0x0404005b 0x09480048 0x2 3 >, - < 1958400000 0x04040066 0x0a510051 0x3 4 >, - < 2150400000 0x04040070 0x0b590059 0x3 5 >, - < 2208000000 0x04040073 0x0b5c005c 0x3 6 >; + < 1113600000 0x0404003a 0x052e002e 0x1 2 >, + < 1401600000 0x04040049 0x073a003a 0x2 3 >, + < 1747200000 0x0404005b 0x09480048 0x2 4 >, + < 1958400000 0x04040066 0x0a510051 0x3 5 >, + < 2150400000 0x04040070 0x0b590059 0x3 6 >, + < 2208000000 0x04040073 0x0b5c005c 0x3 7 >; qcom,up-timer = <1000 1000>; qcom,down-timer = <1000 1000>; @@ -1158,19 +1161,6 @@ qcom,wfx-fsm-en; qcom,pc-fsm-en; - qcom,pwrcl-apcs-mem-acc-cfg = - <0x179d1360 0x179d1364 0x179d1364>; - qcom,perfcl-apcs-mem-acc-cfg = - <0x179d1368 0x179d136C 0x179d1370>; - qcom,pwrcl-apcs-mem-acc-val = - <0x00000000 0x80000000 0x80000000>, - <0x00000000 0x00000000 0x00000000>, - <0x00000000 0x00000001 0x00000001>; - qcom,perfcl-apcs-mem-acc-val = - <0x00000000 0x00000000 0x80000000>, - <0x00000000 0x00000000 0x00000000>, - <0x00000000 0x00000000 0x00000001>; - clock-names = "aux_clk", "xo_a"; clocks = <&clock_gcc HMSS_GPLL0_CLK_SRC>, <&clock_rpmcc RPM_XO_A_CLK_SRC>; @@ -1178,12 +1168,49 @@ #clock-cells = <1>; }; + msm_cpufreq: qcom,msm-cpufreq { + compatible = "qcom,msm-cpufreq"; + clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk", + "cpu3_clk", "cpu4_clk", "cpu5_clk", + "cpu6_clk", "cpu7_clk"; + clocks = <&clock_cpu PWRCL_CLK>, + <&clock_cpu PWRCL_CLK>, + <&clock_cpu PWRCL_CLK>, + <&clock_cpu PWRCL_CLK>, + <&clock_cpu PERFCL_CLK>, + <&clock_cpu PERFCL_CLK>, + <&clock_cpu PERFCL_CLK>, + <&clock_cpu PERFCL_CLK>; + + qcom,governor-per-policy; + + qcom,cpufreq-table-0 = + < 300000 >, + < 633600 >, + < 902400 >, + < 1113600 >, + < 1401600 >, + < 1536000 >, + < 1747200 >, + < 1843200 >; + + qcom,cpufreq-table-4 = + < 300000 >, + < 1113600 >, + < 1401600 >, + < 1747200 >, + < 1958400 >, + < 2150400 >, + < 2208000 >, + < 2457600 >; + }; + sdhc_1: sdhci@c0c4000 { compatible = "qcom,sdhci-msm-v5"; reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>; reg-names = "hc_mem", "cmdq_mem"; - interrupts = <0 129 0>, <0 227 0>; + interrupts = <0 110 0>, <0 112 0>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <8>; @@ -1191,6 +1218,21 @@ qcom,devfreq,freq-table = <50000000 200000000>; + qcom,msm-bus,name = "sdhc1"; + qcom,msm-bus,num-cases = <9>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ + <78 512 1046 3200>, /* 400 KB/s*/ + <78 512 52286 160000>, /* 20 MB/s */ + <78 512 65360 200000>, /* 25 MB/s */ + <78 512 130718 400000>, /* 50 MB/s */ + <78 512 130718 400000>, /* 100 MB/s */ + <78 512 261438 800000>, /* 200 MB/s */ + <78 512 261438 800000>, /* 400 MB/s */ + <78 512 1338562 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 400000000 4294967295>; + clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>; clock-names = "iface_clk", "core_clk"; @@ -1198,6 +1240,39 @@ status = "disabled"; }; + sdhc_2: sdhci@c084000 { + compatible = "qcom,sdhci-msm-v5"; + reg = <0xc084000 0x1000>; + reg-names = "hc_mem"; + + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + + qcom,bus-width = <4>; + qcom,large-address-bus; + + qcom,msm-bus,name = "sdhc2"; + qcom,msm-bus,num-cases = <8>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */ + <81 512 1046 3200>, /* 400 KB/s */ + <81 512 52286 160000>, /* 20 MB/s */ + <81 512 65360 200000>, /* 25 MB/s */ + <81 512 130718 400000>, /* 50 MB/s */ + <81 512 261438 800000>, /* 100 MB/s */ + <81 512 261438 800000>, /* 200 MB/s */ + <81 512 1338562 4096000>; /* Max. bandwidth */ + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 + 100000000 200000000 4294967295>; + + qcom,devfreq,freq-table = <50000000 200000000>; + clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, + <&clock_gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface_clk", "core_clk"; + + status = "disabled"; + }; + ipa_hw: qcom,ipa@14780000 { compatible = "qcom,ipa"; reg = <0x14780000 0x4effc>, <0x14784000 0x26934>; @@ -1478,6 +1553,35 @@ qcom,xprt = "smem"; }; + glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp { + compatible = "qcom,glink-spi-xprt"; + label = "wdsp"; + qcom,remote-fifo-config = <&glink_fifo_wdsp>; + qcom,qos-config = <&glink_qos_wdsp>; + qcom,ramp-time = <0x10>, + <0x20>, + <0x30>, + <0x40>; + }; + + glink_fifo_wdsp: qcom,glink-fifo-config-wdsp { + compatible = "qcom,glink-fifo-config"; + qcom,out-read-idx-reg = <0x12000>; + qcom,out-write-idx-reg = <0x12004>; + qcom,in-read-idx-reg = <0x1200c>; + qcom,in-write-idx-reg = <0x12010>; + }; + + glink_qos_wdsp: qcom,glink-qos-config-wdsp { + compatible = "qcom,glink-qos-config"; + qcom,flow-info = <0x80 0x0>, + <0x70 0x1>, + <0x60 0x2>, + <0x50 0x3>; + qcom,mtu-size = <0x800>; + qcom,tput-stats-cycle = <0xa>; + }; + qcom,glink_pkt { compatible = "qcom,glinkpkt"; @@ -1636,7 +1740,7 @@ reg = <0x15700000 0x00100>; interrupts = <0 162 1>; - vdd_cx-supply = <&pm2falcon_l9_level>; + vdd_cx-supply = <&pm660l_l9_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; @@ -1668,7 +1772,7 @@ reg = <0x1a300000 0x00100>; interrupts = <0 518 1>; - vdd_cx-supply = <&pm2falcon_s3_level>; + vdd_cx-supply = <&pm660l_s3_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; @@ -1725,9 +1829,9 @@ "mnoc_axi_clk"; interrupts = <0 448 1>; - vdd_cx-supply = <&pm2falcon_s3_level>; + vdd_cx-supply = <&pm660l_s3_level>; vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - vdd_mx-supply = <&pm2falcon_s5_level>; + vdd_mx-supply = <&pm660l_s5_level>; vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; qcom,firmware-name = "modem"; qcom,pil-self-auth; @@ -1951,7 +2055,7 @@ }; ufsphy1: ufsphy@1da7000 { - compatible = "qcom,ufs-phy-qmp-v3-falcon"; + compatible = "qcom,ufs-phy-qmp-v3-660"; reg = <0x1da7000 0xdb8>; reg-names = "phy_mem"; #phy-cells = <0>; @@ -2092,7 +2196,7 @@ <&clock_rpmcc RPM_QDSS_A_CLK>; clock-names = "core_clk", "core_a_clk"; - qcom,coresight-jtagmm-cpu = <&CPU0>; + qcom,coresight-jtagmm-cpu = <&CPU4>; }; jtag_mm5: jtagmm@7d40000 { @@ -2104,7 +2208,7 @@ <&clock_rpmcc RPM_QDSS_A_CLK>; clock-names = "core_clk", "core_a_clk"; - qcom,coresight-jtagmm-cpu = <&CPU1>; + qcom,coresight-jtagmm-cpu = <&CPU5>; }; jtag_mm6: jtagmm@7e40000 { @@ -2116,7 +2220,7 @@ <&clock_rpmcc RPM_QDSS_A_CLK>; clock-names = "core_clk", "core_a_clk"; - qcom,coresight-jtagmm-cpu = <&CPU2>; + qcom,coresight-jtagmm-cpu = <&CPU6>; }; jtag_mm7: jtagmm@7f40000 { @@ -2128,22 +2232,22 @@ <&clock_rpmcc RPM_QDSS_A_CLK>; clock-names = "core_clk", "core_a_clk"; - qcom,coresight-jtagmm-cpu = <&CPU3>; + qcom,coresight-jtagmm-cpu = <&CPU7>; }; }; -#include "msmfalcon-ion.dtsi" -#include "msmfalcon-bus.dtsi" -#include "msm-pmfalcon.dtsi" -#include "msm-pm2falcon.dtsi" -#include "msm-pmfalcon-rpm-regulator.dtsi" -#include "msm-pm2falcon-rpm-regulator.dtsi" -#include "msmfalcon-regulator.dtsi" -#include "msm-gdsc-falcon.dtsi" -#include "msmfalcon-gpu.dtsi" -#include "msmfalcon-pm.dtsi" +#include "sdm660-ion.dtsi" +#include "sdm660-bus.dtsi" +#include "msm-pm660.dtsi" +#include "msm-pm660l.dtsi" +#include "msm-pm660-rpm-regulator.dtsi" +#include "msm-pm660l-rpm-regulator.dtsi" +#include "sdm660-regulator.dtsi" +#include "msm-gdsc-660.dtsi" +#include "sdm660-gpu.dtsi" +#include "sdm660-pm.dtsi" #include "msm-audio.dtsi" -#include "msmfalcon-audio.dtsi" +#include "sdm660-audio.dtsi" &gdsc_usb30 { status = "ok"; @@ -2198,6 +2302,7 @@ &gdsc_cpp { parent-supply = <&gdsc_camss_top>; + qcom,support-hw-trigger; status = "ok"; }; @@ -2219,14 +2324,14 @@ status = "ok"; }; -#include "msm-arm-smmu-falcon.dtsi" -#include "msm-arm-smmu-impl-defs-falcon.dtsi" -#include "msmfalcon-common.dtsi" -#include "msmfalcon-blsp.dtsi" -#include "msmfalcon-camera.dtsi" -#include "msmfalcon-vidc.dtsi" +#include "msm-arm-smmu-660.dtsi" +#include "msm-arm-smmu-impl-defs-660.dtsi" +#include "sdm660-common.dtsi" +#include "sdm660-blsp.dtsi" +#include "sdm660-camera.dtsi" +#include "sdm660-vidc.dtsi" -&pm2falcon_gpios { +&pm660l_gpios { /* GPIO 7 for VOL_UP */ gpio@c600 { status = "okay"; @@ -2265,7 +2370,7 @@ vol_up { label = "volume_up"; - gpios = <&pm2falcon_gpios 7 0x1>; + gpios = <&pm660l_gpios 7 0x1>; linux,input-type = <1>; linux,code = <115>; gpio-key,wakeup; @@ -2274,5 +2379,5 @@ }; }; -#include "msmfalcon-mdss.dtsi" -#include "msmfalcon-mdss-pll.dtsi" +#include "sdm660-mdss.dtsi" +#include "sdm660-mdss-pll.dtsi" diff --git a/arch/arm/configs/msmcortex_defconfig b/arch/arm/configs/msmcortex_defconfig index 5e9afadeb7ae..9cf5a15e80eb 100644 --- a/arch/arm/configs/msmcortex_defconfig +++ b/arch/arm/configs/msmcortex_defconfig @@ -38,7 +38,7 @@ CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMFALCON=y +CONFIG_ARCH_SDM660=y CONFIG_SMP=y CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 @@ -254,7 +254,6 @@ CONFIG_PPPOPNS=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_ATH_CARDS=y CONFIG_CLD_LL_CORE=y -CONFIG_QPNP_POWER_ON=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_KEYRESET=y CONFIG_KEYBOARD_GPIO=y @@ -266,6 +265,7 @@ CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_SECURE_TOUCH=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_KEYCHORD=y CONFIG_INPUT_UINPUT=y CONFIG_INPUT_GPIO=y @@ -289,7 +289,7 @@ CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_MSMFALCON=y +CONFIG_PINCTRL_SDM660=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y CONFIG_APSS_CORE_EA=y diff --git a/arch/arm/configs/msmfalcon-perf_defconfig b/arch/arm/configs/sdm660-perf_defconfig index 211ec1c6cabc..d555a1b179d8 100644 --- a/arch/arm/configs/msmfalcon-perf_defconfig +++ b/arch/arm/configs/sdm660-perf_defconfig @@ -46,8 +46,8 @@ CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMFALCON=y -CONFIG_ARCH_MSMTRITON=y +CONFIG_ARCH_SDM660=y +CONFIG_ARCH_SDM630=y CONFIG_ARM_KERNMEM_PERMS=y CONFIG_SMP=y CONFIG_SCHED_MC=y @@ -280,7 +280,6 @@ CONFIG_USB_USBNET=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_ATH_CARDS=y CONFIG_CLD_LL_CORE=y -CONFIG_QPNP_POWER_ON=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_KEYRESET=y CONFIG_KEYBOARD_GPIO=y @@ -292,6 +291,7 @@ CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_SECURE_TOUCH=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_KEYCHORD=y CONFIG_INPUT_UINPUT=y CONFIG_INPUT_GPIO=y @@ -315,7 +315,7 @@ CONFIG_SPI=y CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PINCTRL_MSMFALCON=y +CONFIG_PINCTRL_SDM660=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y CONFIG_POWER_RESET=y @@ -352,6 +352,7 @@ CONFIG_REGULATOR_MSM_GFX_LDO=y CONFIG_REGULATOR_RPM_SMD=y CONFIG_REGULATOR_QPNP=y CONFIG_REGULATOR_QPNP_LABIBB=y +CONFIG_REGULATOR_QPNP_OLEDB=y CONFIG_REGULATOR_SPM=y CONFIG_REGULATOR_CPR3_HMSS=y CONFIG_REGULATOR_CPR3_MMSS=y @@ -389,7 +390,7 @@ CONFIG_SND=y CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_AUDIO_QMI=y CONFIG_SND_SOC=y -CONFIG_SND_SOC_FALCON=y +CONFIG_SND_SOC_660=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y @@ -444,6 +445,7 @@ CONFIG_MMC_TEST=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_CQ_HCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_QPNP=y @@ -481,7 +483,9 @@ CONFIG_GPIO_USB_DETECT=y CONFIG_SEEMP_CORE=y CONFIG_USB_BAM=y CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_MSM_GCC_FALCON=y +CONFIG_MSM_GPUCC_660=y +CONFIG_MSM_MMCC_660=y +CONFIG_CLOCK_CPU_OSM=y CONFIG_QCOM_MDSS_PLL=y CONFIG_REMOTE_SPINLOCK_MSM=y CONFIG_ARM_SMMU=y diff --git a/arch/arm/configs/msmfalcon_defconfig b/arch/arm/configs/sdm660_defconfig index 10981157afc3..2c94274b0637 100644 --- a/arch/arm/configs/msmfalcon_defconfig +++ b/arch/arm/configs/sdm660_defconfig @@ -46,8 +46,8 @@ CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMFALCON=y -CONFIG_ARCH_MSMTRITON=y +CONFIG_ARCH_SDM660=y +CONFIG_ARCH_SDM630=y CONFIG_ARM_KERNMEM_PERMS=y CONFIG_SMP=y CONFIG_SCHED_MC=y @@ -279,7 +279,6 @@ CONFIG_USB_USBNET=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_ATH_CARDS=y CONFIG_CLD_LL_CORE=y -CONFIG_QPNP_POWER_ON=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_KEYRESET=y CONFIG_KEYBOARD_GPIO=y @@ -291,6 +290,7 @@ CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_SECURE_TOUCH=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_KEYCHORD=y CONFIG_INPUT_UINPUT=y CONFIG_INPUT_GPIO=y @@ -313,7 +313,7 @@ CONFIG_SPI=y CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PINCTRL_MSMFALCON=y +CONFIG_PINCTRL_SDM660=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y CONFIG_POWER_RESET=y @@ -351,6 +351,7 @@ CONFIG_REGULATOR_RPM_SMD=y CONFIG_REGULATOR_QPNP=y CONFIG_REGULATOR_QPNP_LABIBB=y CONFIG_REGULATOR_QPNP_LCDB=y +CONFIG_REGULATOR_QPNP_OLEDB=y CONFIG_REGULATOR_SPM=y CONFIG_REGULATOR_CPR3_HMSS=y CONFIG_REGULATOR_CPR3_MMSS=y @@ -391,7 +392,7 @@ CONFIG_SND=y CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_AUDIO_QMI=y CONFIG_SND_SOC=y -CONFIG_SND_SOC_FALCON=y +CONFIG_SND_SOC_660=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y @@ -445,6 +446,7 @@ CONFIG_MMC_TEST=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_CQ_HCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_QPNP=y @@ -482,8 +484,8 @@ CONFIG_GPIO_USB_DETECT=y CONFIG_SEEMP_CORE=y CONFIG_USB_BAM=y CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_MSM_GPUCC_FALCON=y -CONFIG_MSM_MMCC_FALCON=y +CONFIG_MSM_GPUCC_660=y +CONFIG_MSM_MMCC_660=y CONFIG_CLOCK_CPU_OSM=y CONFIG_QCOM_MDSS_PLL=y CONFIG_REMOTE_SPINLOCK_MSM=y diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig index a4fba1af7744..4ffb9b34e315 100644 --- a/arch/arm/mach-qcom/Kconfig +++ b/arch/arm/mach-qcom/Kconfig @@ -1,8 +1,8 @@ if ARCH_QCOM menu "QCOM SoC Type" -config ARCH_MSMFALCON - bool "Enable Support for MSMFALCON" +config ARCH_SDM660 + bool "Enable Support for SDM660" select CLKDEV_LOOKUP select HAVE_CLK select HAVE_CLK_PREPARE @@ -36,11 +36,11 @@ config ARCH_MSMFALCON select GENERIC_IRQ_MIGRATION select MSM_JTAGV8 if CORESIGHT_ETMV4 help - This enables support for the MSMFALCON chipset. If you do not + This enables support for the SDM660 chipset. If you do not wish to build a kernel that runs on this chipset, say 'N' here. -config ARCH_MSMTRITON - bool "Enable Support for MSMTRITON" +config ARCH_SDM630 + bool "Enable Support for SDM630" select CLKDEV_LOOKUP select HAVE_CLK select HAVE_CLK_PREPARE @@ -68,7 +68,7 @@ config ARCH_MSMTRITON select MSM_RPM_SMD select MSM_JTAGV8 if CORESIGHT_ETMV4 help - This enables support for the MSMTRITON chipset. If you do not + This enables support for the SDM630 chipset. If you do not wish to build a kernel that runs on this chipset, say 'N' here. config ARCH_MSM8X60 diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile index c5e30fff2b1e..c79ab416701c 100644 --- a/arch/arm/mach-qcom/Makefile +++ b/arch/arm/mach-qcom/Makefile @@ -1,4 +1,4 @@ obj-y := board.o obj-$(CONFIG_USE_OF) += board-dt.o -obj-$(CONFIG_ARCH_MSMFALCON) += board-falcon.o +obj-$(CONFIG_ARCH_SDM660) += board-660.o obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-qcom/board-660.c b/arch/arm/mach-qcom/board-660.c new file mode 100644 index 000000000000..5cd11f09e3a4 --- /dev/null +++ b/arch/arm/mach-qcom/board-660.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <asm/mach/arch.h> +#include "board-dt.h" + +static const char *sdm660_dt_match[] __initconst = { + "qcom,sdm660", + "qcom,sda660", + NULL +}; + +static void __init sdm660_init(void) +{ + board_dt_populate(NULL); +} + +DT_MACHINE_START(SDM660_DT, + "Qualcomm Technologies, Inc. SDM 660 (Flattened Device Tree)") + .init_machine = sdm660_init, + .dt_compat = sdm660_dt_match, +MACHINE_END + +static const char *sdm630_dt_match[] __initconst = { + "qcom,sdm630", + "qcom,sda630", + NULL +}; + +static void __init sdm630_init(void) +{ + board_dt_populate(NULL); +} + +DT_MACHINE_START(SDM630_DT, + "Qualcomm Technologies, Inc. SDM 630 (Flattened Device Tree)") + .init_machine = sdm630_init, + .dt_compat = sdm630_dt_match, +MACHINE_END + +static const char *sdm658_dt_match[] __initconst = { + "qcom,sdm658", + "qcom,sda658", + NULL +}; + +static void __init sdm658_init(void) +{ + board_dt_populate(NULL); +} + +DT_MACHINE_START(SDM658_DT, + "Qualcomm Technologies, Inc. SDM 658 (Flattened Device Tree)") + .init_machine = sdm658_init, + .dt_compat = sdm658_dt_match, +MACHINE_END diff --git a/arch/arm/mach-qcom/board-falcon.c b/arch/arm/mach-qcom/board-falcon.c deleted file mode 100644 index aec16886308d..000000000000 --- a/arch/arm/mach-qcom/board-falcon.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/kernel.h> -#include <asm/mach/arch.h> -#include "board-dt.h" - -static const char *msmfalcon_dt_match[] __initconst = { - "qcom,msmfalcon", - "qcom,apqfalcon", - NULL -}; - -static void __init msmfalcon_init(void) -{ - board_dt_populate(NULL); -} - -DT_MACHINE_START(MSMFALCON_DT, - "Qualcomm Technologies, Inc. MSM FALCON (Flattened Device Tree)") - .init_machine = msmfalcon_init, - .dt_compat = msmfalcon_dt_match, -MACHINE_END - -static const char *msmtriton_dt_match[] __initconst = { - "qcom,msmtriton", - "qcom,apqtriton", - NULL -}; - -static void __init msmtriton_init(void) -{ - board_dt_populate(NULL); -} - -DT_MACHINE_START(MSMTRITON_DT, - "Qualcomm Technologies, Inc. MSM TRITON (Flattened Device Tree)") - .init_machine = msmtriton_init, - .dt_compat = msmtriton_dt_match, -MACHINE_END diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 56b7f310ddbc..b6e5fa37f976 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -86,25 +86,25 @@ config ARCH_MSMHAMSTER If you do not wish to build a kernel that runs on this chipset,say 'N' here. -config ARCH_MSMFALCON - bool "Enable Support for Qualcomm Technologies Inc MSMFALCON" +config ARCH_SDM660 + bool "Enable Support for Qualcomm Technologies Inc SDM660" depends on ARCH_QCOM select COMMON_CLK select COMMON_CLK_QCOM select QCOM_GDSC help - This enables support for the MSMFALCON chipset. + This enables support for the SDM660 chipset. If you do not wish to build a kernel that runs on this chipset,say 'N' here. -config ARCH_MSMTRITON - bool "Enable Support for Qualcomm Technologies Inc MSMTRITON" +config ARCH_SDM630 + bool "Enable Support for Qualcomm Technologies Inc SDM630" depends on ARCH_QCOM select COMMON_CLK select COMMON_CLK_QCOM select QCOM_GDSC help - This enables support for the MSMTRITON chipset. + This enables support for the SDM630 chipset. If you do not wish to build a kernel that runs on this chipset,say 'N' here. diff --git a/arch/arm64/configs/msm-perf_defconfig b/arch/arm64/configs/msm-perf_defconfig index 08dccf8e5022..07e413e31234 100644 --- a/arch/arm64/configs/msm-perf_defconfig +++ b/arch/arm64/configs/msm-perf_defconfig @@ -279,7 +279,6 @@ CONFIG_WIL6210=m CONFIG_CNSS=y CONFIG_CLD_LL_CORE=y CONFIG_BUS_AUTO_SUSPEND=y -CONFIG_QPNP_POWER_ON=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_KEYRESET=y CONFIG_KEYBOARD_GPIO=y @@ -293,6 +292,7 @@ CONFIG_SECURE_TOUCH=y CONFIG_TOUCHSCREEN_GEN_VKEYS=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_KEYCHORD=y CONFIG_INPUT_UINPUT=y CONFIG_INPUT_GPIO=y diff --git a/arch/arm64/configs/msm_defconfig b/arch/arm64/configs/msm_defconfig index 4620e74de5bc..76d949319dfa 100644 --- a/arch/arm64/configs/msm_defconfig +++ b/arch/arm64/configs/msm_defconfig @@ -265,7 +265,6 @@ CONFIG_WIL6210=m CONFIG_CNSS=y CONFIG_CLD_LL_CORE=y CONFIG_BUS_AUTO_SUSPEND=y -CONFIG_QPNP_POWER_ON=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_KEYRESET=y CONFIG_KEYBOARD_GPIO=y @@ -280,6 +279,7 @@ CONFIG_SECURE_TOUCH=y CONFIG_TOUCHSCREEN_GEN_VKEYS=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_UINPUT=y CONFIG_INPUT_GPIO=y # CONFIG_SERIO_SERPORT is not set diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig index 97a082dd4fcd..07d24ea6b707 100644 --- a/arch/arm64/configs/msmcortex-perf_defconfig +++ b/arch/arm64/configs/msmcortex-perf_defconfig @@ -275,7 +275,6 @@ CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_ATH_CARDS=y CONFIG_WIL6210=m CONFIG_CLD_LL_CORE=y -CONFIG_QPNP_POWER_ON=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_KEYRESET=y CONFIG_KEYBOARD_GPIO=y @@ -286,6 +285,7 @@ CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_SECURE_TOUCH=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_UINPUT=y # CONFIG_SERIO_SERPORT is not set # CONFIG_VT is not set @@ -308,7 +308,7 @@ CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_MSMFALCON=y +CONFIG_PINCTRL_SDM660=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig index 965a13caaeb5..25b5c206e1ae 100644 --- a/arch/arm64/configs/msmcortex_defconfig +++ b/arch/arm64/configs/msmcortex_defconfig @@ -275,7 +275,6 @@ CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_ATH_CARDS=y CONFIG_WIL6210=m CONFIG_CLD_LL_CORE=y -CONFIG_QPNP_POWER_ON=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_KEYRESET=y CONFIG_KEYBOARD_GPIO=y @@ -287,6 +286,7 @@ CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_SECURE_TOUCH=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_KEYCHORD=y CONFIG_INPUT_UINPUT=y CONFIG_INPUT_GPIO=y @@ -311,7 +311,7 @@ CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_MSMFALCON=y +CONFIG_PINCTRL_SDM660=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y diff --git a/arch/arm64/configs/msmfalcon-perf_defconfig b/arch/arm64/configs/sdm660-perf_defconfig index b84168e18478..7d203e49d595 100644 --- a/arch/arm64/configs/msmfalcon-perf_defconfig +++ b/arch/arm64/configs/sdm660-perf_defconfig @@ -46,8 +46,8 @@ CONFIG_MODULE_SIG_FORCE=y CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMFALCON=y -CONFIG_ARCH_MSMTRITON=y +CONFIG_ARCH_SDM660=y +CONFIG_ARCH_SDM630=y CONFIG_PCI=y CONFIG_PCI_MSM=y CONFIG_SCHED_MC=y @@ -278,7 +278,6 @@ CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_ATH_CARDS=y CONFIG_WIL6210=m CONFIG_CLD_LL_CORE=y -CONFIG_QPNP_POWER_ON=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_KEYRESET=y CONFIG_KEYBOARD_GPIO=y @@ -289,6 +288,7 @@ CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_SECURE_TOUCH=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_UINPUT=y # CONFIG_SERIO_SERPORT is not set # CONFIG_VT is not set @@ -310,7 +310,7 @@ CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_MSM8998=y -CONFIG_PINCTRL_MSMFALCON=y +CONFIG_PINCTRL_SDM660=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y @@ -351,6 +351,7 @@ CONFIG_REGULATOR_RPM_SMD=y CONFIG_REGULATOR_QPNP=y CONFIG_REGULATOR_QPNP_LABIBB=y CONFIG_REGULATOR_QPNP_LCDB=y +CONFIG_REGULATOR_QPNP_OLEDB=y CONFIG_REGULATOR_SPM=y CONFIG_REGULATOR_CPR3_HMSS=y CONFIG_REGULATOR_CPR3_MMSS=y @@ -396,9 +397,9 @@ CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y CONFIG_MSMB_JPEG=y CONFIG_MSM_FD=y CONFIG_MSM_JPEGDMA=y -CONFIG_MSM_VIDC_V4L2=m -CONFIG_MSM_VIDC_VMEM=m -CONFIG_MSM_VIDC_GOVERNORS=m +CONFIG_MSM_VIDC_V4L2=y +CONFIG_MSM_VIDC_VMEM=y +CONFIG_MSM_VIDC_GOVERNORS=y CONFIG_MSM_SDE_ROTATOR=y CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y CONFIG_QCOM_KGSL=y @@ -419,7 +420,7 @@ CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_AUDIO_QMI=y CONFIG_SND_SOC=y CONFIG_SND_SOC_MSM8998=y -CONFIG_SND_SOC_FALCON=y +CONFIG_SND_SOC_660=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y @@ -473,6 +474,7 @@ CONFIG_MMC_TEST=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_CQ_HCI=y CONFIG_LEDS_QPNP=y CONFIG_LEDS_QPNP_FLASH_V2=y CONFIG_LEDS_QPNP_WLED=y @@ -504,8 +506,8 @@ CONFIG_GPIO_USB_DETECT=y CONFIG_SEEMP_CORE=y CONFIG_USB_BAM=y CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_MSM_GPUCC_FALCON=y -CONFIG_MSM_MMCC_FALCON=y +CONFIG_MSM_GPUCC_660=y +CONFIG_MSM_MMCC_660=y CONFIG_CLOCK_CPU_OSM=y CONFIG_QCOM_MDSS_PLL=y CONFIG_REMOTE_SPINLOCK_MSM=y diff --git a/arch/arm64/configs/msmfalcon_defconfig b/arch/arm64/configs/sdm660_defconfig index ce91e8992b46..c295ba7e0d70 100644 --- a/arch/arm64/configs/msmfalcon_defconfig +++ b/arch/arm64/configs/sdm660_defconfig @@ -47,8 +47,8 @@ CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMFALCON=y -CONFIG_ARCH_MSMTRITON=y +CONFIG_ARCH_SDM660=y +CONFIG_ARCH_SDM630=y CONFIG_PCI=y CONFIG_PCI_MSM=y CONFIG_SCHED_MC=y @@ -278,7 +278,6 @@ CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_ATH_CARDS=y CONFIG_WIL6210=m CONFIG_CLD_LL_CORE=y -CONFIG_QPNP_POWER_ON=y CONFIG_INPUT_EVDEV=y CONFIG_INPUT_KEYRESET=y CONFIG_KEYBOARD_GPIO=y @@ -290,6 +289,7 @@ CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_v21=y CONFIG_SECURE_TOUCH=y CONFIG_INPUT_MISC=y CONFIG_INPUT_HBTP_INPUT=y +CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_KEYCHORD=y CONFIG_INPUT_UINPUT=y CONFIG_INPUT_GPIO=y @@ -312,7 +312,7 @@ CONFIG_SPI=y CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PINCTRL_MSMFALCON=y +CONFIG_PINCTRL_SDM660=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y @@ -353,6 +353,7 @@ CONFIG_REGULATOR_RPM_SMD=y CONFIG_REGULATOR_QPNP=y CONFIG_REGULATOR_QPNP_LABIBB=y CONFIG_REGULATOR_QPNP_LCDB=y +CONFIG_REGULATOR_QPNP_OLEDB=y CONFIG_REGULATOR_SPM=y CONFIG_REGULATOR_CPR3_HMSS=y CONFIG_REGULATOR_CPR3_MMSS=y @@ -398,9 +399,9 @@ CONFIG_MSM_V4L2_VIDEO_OVERLAY_DEVICE=y CONFIG_MSMB_JPEG=y CONFIG_MSM_FD=y CONFIG_MSM_JPEGDMA=y -CONFIG_MSM_VIDC_V4L2=m -CONFIG_MSM_VIDC_VMEM=m -CONFIG_MSM_VIDC_GOVERNORS=m +CONFIG_MSM_VIDC_V4L2=y +CONFIG_MSM_VIDC_VMEM=y +CONFIG_MSM_VIDC_GOVERNORS=y CONFIG_MSM_SDE_ROTATOR=y CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y CONFIG_QCOM_KGSL=y @@ -421,7 +422,7 @@ CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_AUDIO_QMI=y CONFIG_SND_SOC=y CONFIG_SND_SOC_MSM8998=y -CONFIG_SND_SOC_FALCON=y +CONFIG_SND_SOC_660=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y @@ -475,6 +476,7 @@ CONFIG_MMC_TEST=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_CQ_HCI=y CONFIG_LEDS_QPNP=y CONFIG_LEDS_QPNP_FLASH_V2=y CONFIG_LEDS_QPNP_WLED=y @@ -513,8 +515,8 @@ CONFIG_GPIO_USB_DETECT=y CONFIG_SEEMP_CORE=y CONFIG_USB_BAM=y CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_MSM_GPUCC_FALCON=y -CONFIG_MSM_MMCC_FALCON=y +CONFIG_MSM_GPUCC_660=y +CONFIG_MSM_MMCC_660=y CONFIG_CLOCK_CPU_OSM=y CONFIG_QCOM_MDSS_PLL=y CONFIG_REMOTE_SPINLOCK_MSM=y diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 7326be306618..68cd3bb8eb89 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -39,6 +39,7 @@ #include <asm/pgtable.h> #include <asm/tlbflush.h> #include <asm/edac.h> +#include <soc/qcom/scm.h> #include <trace/events/exception.h> @@ -408,6 +409,23 @@ no_context: return 0; } +static int do_tlb_conf_fault(unsigned long addr, + unsigned int esr, + struct pt_regs *regs) +{ +#define SCM_TLB_CONFLICT_CMD 0x1B + struct scm_desc desc = { + .args[0] = addr, + .arginfo = SCM_ARGS(1), + }; + + if (scm_call2_atomic(SCM_SIP_FNID(SCM_SVC_MP, SCM_TLB_CONFLICT_CMD), + &desc)) + return 1; + + return 0; +} + /* * First Level Translation Fault Handler * @@ -499,7 +517,7 @@ static struct fault_info { { do_bad, SIGBUS, 0, "unknown 45" }, { do_bad, SIGBUS, 0, "unknown 46" }, { do_bad, SIGBUS, 0, "unknown 47" }, - { do_bad, SIGBUS, 0, "TLB conflict abort" }, + { do_tlb_conf_fault, SIGBUS, 0, "TLB conflict abort" }, { do_bad, SIGBUS, 0, "unknown 49" }, { do_bad, SIGBUS, 0, "unknown 50" }, { do_bad, SIGBUS, 0, "unknown 51" }, diff --git a/drivers/char/diag/diag_usb.c b/drivers/char/diag/diag_usb.c index ca54b24ec604..0a0fc4400de5 100644 --- a/drivers/char/diag/diag_usb.c +++ b/drivers/char/diag/diag_usb.c @@ -14,6 +14,7 @@ #include <linux/init.h> #include <linux/module.h> #include <linux/device.h> +#include <linux/kernel.h> #include <linux/err.h> #include <linux/sched.h> #include <linux/ratelimit.h> @@ -218,7 +219,8 @@ static void usb_disconnect(struct diag_usb_info *ch) if (!ch) return; - if (!atomic_read(&ch->connected) && driver->usb_connected) + if (!atomic_read(&ch->connected) && + driver->usb_connected && diag_mask_param()) diag_clear_masks(NULL); if (ch && ch->ops && ch->ops->close) diff --git a/drivers/char/diag/diagchar.h b/drivers/char/diag/diagchar.h index 67db49badf21..409d2724042c 100644 --- a/drivers/char/diag/diagchar.h +++ b/drivers/char/diag/diagchar.h @@ -473,6 +473,7 @@ struct diagchar_dev { int ref_count; int mask_clear; struct mutex diag_maskclear_mutex; + struct mutex diag_notifier_mutex; struct mutex diagchar_mutex; struct mutex diag_file_mutex; wait_queue_head_t wait_q; @@ -632,6 +633,7 @@ void diag_cmd_remove_reg(struct diag_cmd_reg_entry_t *entry, uint8_t proc); void diag_cmd_remove_reg_by_pid(int pid); void diag_cmd_remove_reg_by_proc(int proc); int diag_cmd_chk_polling(struct diag_cmd_reg_entry_t *entry); +int diag_mask_param(void); void diag_clear_masks(struct diag_md_session_t *info); void diag_record_stats(int type, int flag); diff --git a/drivers/char/diag/diagchar_core.c b/drivers/char/diag/diagchar_core.c index 76559633f387..7e63b7277d80 100644 --- a/drivers/char/diag/diagchar_core.c +++ b/drivers/char/diag/diagchar_core.c @@ -144,6 +144,14 @@ module_param(max_clients, uint, 0); static struct timer_list drain_timer; static int timer_in_progress; +/* + * Diag Mask clear variable + * Used for clearing masks upon + * USB disconnection and stopping ODL + */ +static int diag_mask_clear_param = 1; +module_param(diag_mask_clear_param, int, 0644); + struct diag_apps_data_t { void *buf; uint32_t len; @@ -390,7 +398,10 @@ static uint32_t diag_translate_kernel_to_user_mask(uint32_t peripheral_mask) return ret; } - +int diag_mask_param(void) +{ + return diag_mask_clear_param; +} void diag_clear_masks(struct diag_md_session_t *info) { int ret; @@ -423,7 +434,8 @@ static void diag_close_logging_process(const int pid) if (!session_info) return; - diag_clear_masks(session_info); + if (diag_mask_clear_param) + diag_clear_masks(session_info); mutex_lock(&driver->diag_maskclear_mutex); driver->mask_clear = 1; @@ -3400,6 +3412,7 @@ static int __init diagchar_init(void) mutex_init(&driver->hdlc_disable_mutex); mutex_init(&driver->diagchar_mutex); mutex_init(&driver->diag_maskclear_mutex); + mutex_init(&driver->diag_notifier_mutex); mutex_init(&driver->diag_file_mutex); mutex_init(&driver->delayed_rsp_mutex); mutex_init(&apps_data_mutex); diff --git a/drivers/char/diag/diagfwd.c b/drivers/char/diag/diagfwd.c index 876b455624b2..a7069bc0edf3 100644 --- a/drivers/char/diag/diagfwd.c +++ b/drivers/char/diag/diagfwd.c @@ -1232,6 +1232,8 @@ static int diagfwd_mux_open(int id, int mode) static int diagfwd_mux_close(int id, int mode) { + uint8_t i; + switch (mode) { case DIAG_USB_MODE: driver->usb_connected = 0; @@ -1252,10 +1254,22 @@ static int diagfwd_mux_close(int id, int mode) */ } else { /* - * With clearing of masks on ODL exit and - * USB disconnection, closing of the channel is - * not needed.This enables read and drop of stale packets. - */ + * With sysfs parameter to clear masks set, + * peripheral masks are cleared on ODL exit and + * USB disconnection and buffers are not marked busy. + * This enables read and drop of stale packets. + * + * With sysfs parameter to clear masks cleared, + * masks are not cleared and buffers are to be marked + * busy to ensure traffic generated by peripheral + * are not read + */ + if (!(diag_mask_param())) { + for (i = 0; i < NUM_PERIPHERALS; i++) { + diagfwd_close(i, TYPE_DATA); + diagfwd_close(i, TYPE_CMD); + } + } /* Re enable HDLC encoding */ pr_debug("diag: In %s, re-enabling HDLC encoding\n", __func__); diff --git a/drivers/char/diag/diagfwd_cntl.c b/drivers/char/diag/diagfwd_cntl.c index 9f43cb5427f0..62c8d0028af9 100644 --- a/drivers/char/diag/diagfwd_cntl.c +++ b/drivers/char/diag/diagfwd_cntl.c @@ -358,6 +358,8 @@ static void process_incoming_feature_mask(uint8_t *buf, uint32_t len, feature_mask_len = FEATURE_MASK_LEN; } + diag_cmd_remove_reg_by_proc(peripheral); + driver->feature[peripheral].rcvd_feature_mask = 1; for (i = 0; i < feature_mask_len && read_len < len; i++) { diff --git a/drivers/char/diag/diagfwd_socket.c b/drivers/char/diag/diagfwd_socket.c index 217d20f72344..1b19e014af63 100644 --- a/drivers/char/diag/diagfwd_socket.c +++ b/drivers/char/diag/diagfwd_socket.c @@ -34,6 +34,9 @@ #include "diagfwd_socket.h" #include "diag_ipc_logging.h" +#include <soc/qcom/subsystem_notif.h> +#include <soc/qcom/subsystem_restart.h> + #define DIAG_SVC_ID 0x1001 #define MODEM_INST_BASE 0 @@ -50,6 +53,7 @@ #define INST_ID_DCI 4 struct diag_cntl_socket_info *cntl_socket; +static uint64_t bootup_req[NUM_SOCKET_SUBSYSTEMS]; struct diag_socket_info socket_data[NUM_PERIPHERALS] = { { @@ -416,7 +420,7 @@ static void socket_open_client(struct diag_socket_info *info) return; } __socket_open_channel(info); - DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s exiting\n", info->name); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s opened client\n", info->name); } static void socket_open_server(struct diag_socket_info *info) @@ -492,6 +496,13 @@ static void __socket_close_channel(struct diag_socket_info *info) if (!atomic_read(&info->opened)) return; + if (bootup_req[info->peripheral] == PEPIPHERAL_SSR_UP) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s is up, stopping cleanup: bootup_req = %d\n", + info->name, (int)bootup_req[info->peripheral]); + return; + } + memset(&info->remote_addr, 0, sizeof(struct sockaddr_msm_ipc)); diagfwd_channel_close(info->fwd_ctxt); @@ -610,7 +621,9 @@ static int cntl_socket_process_msg_client(uint32_t cmd, uint32_t node_id, case CNTL_CMD_REMOVE_CLIENT: DIAG_LOG(DIAG_DEBUG_PERIPHERALS, "%s received remove client\n", info->name); + mutex_lock(&driver->diag_notifier_mutex); socket_close_channel(info); + mutex_unlock(&driver->diag_notifier_mutex); break; default: return -EINVAL; @@ -619,6 +632,25 @@ static int cntl_socket_process_msg_client(uint32_t cmd, uint32_t node_id, return 0; } +static int restart_notifier_cb(struct notifier_block *this, + unsigned long code, + void *data); + +struct restart_notifier_block { + unsigned processor; + char *name; + struct notifier_block nb; +}; + +static struct restart_notifier_block restart_notifiers[] = { + {SOCKET_MODEM, "modem", .nb.notifier_call = restart_notifier_cb}, + {SOCKET_ADSP, "adsp", .nb.notifier_call = restart_notifier_cb}, + {SOCKET_WCNSS, "wcnss", .nb.notifier_call = restart_notifier_cb}, + {SOCKET_SLPI, "slpi", .nb.notifier_call = restart_notifier_cb}, + {SOCKET_CDSP, "cdsp", .nb.notifier_call = restart_notifier_cb}, +}; + + static void cntl_socket_read_work_fn(struct work_struct *work) { union cntl_port_msg msg; @@ -626,7 +658,6 @@ static void cntl_socket_read_work_fn(struct work_struct *work) struct kvec iov = { 0 }; struct msghdr read_msg = { 0 }; - if (!cntl_socket) return; @@ -845,8 +876,11 @@ static int __diag_cntl_socket_init(void) int diag_socket_init(void) { int err = 0; + int i; int peripheral = 0; + void *handle; struct diag_socket_info *info = NULL; + struct restart_notifier_block *nb; for (peripheral = 0; peripheral < NUM_PERIPHERALS; peripheral++) { info = &socket_cntl[peripheral]; @@ -867,6 +901,17 @@ int diag_socket_init(void) goto fail; } + for (i = 0; i < ARRAY_SIZE(restart_notifiers); i++) { + nb = &restart_notifiers[i]; + if (nb) { + handle = subsys_notif_register_notifier(nb->name, + &nb->nb); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s: registering notifier for '%s', handle=%p\n", + __func__, nb->name, handle); + } + } + register_ipcrtr_af_init_notifier(&socket_notify); fail: return err; @@ -902,6 +947,65 @@ static int socket_ready_notify(struct notifier_block *nb, return 0; } +static int restart_notifier_cb(struct notifier_block *this, unsigned long code, + void *_cmd) +{ + struct restart_notifier_block *notifier; + + notifier = container_of(this, + struct restart_notifier_block, nb); + if (!notifier) { + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s: invalid notifier block\n", __func__); + return NOTIFY_DONE; + } + + mutex_lock(&driver->diag_notifier_mutex); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "%s: ssr for processor %d ('%s')\n", + __func__, notifier->processor, notifier->name); + + switch (code) { + + case SUBSYS_BEFORE_SHUTDOWN: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s: SUBSYS_BEFORE_SHUTDOWN\n", __func__); + bootup_req[notifier->processor] = PEPIPHERAL_SSR_DOWN; + break; + + case SUBSYS_AFTER_SHUTDOWN: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s: SUBSYS_AFTER_SHUTDOWN\n", __func__); + break; + + case SUBSYS_BEFORE_POWERUP: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s: SUBSYS_BEFORE_POWERUP\n", __func__); + break; + + case SUBSYS_AFTER_POWERUP: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: %s: SUBSYS_AFTER_POWERUP\n", __func__); + if (!bootup_req[notifier->processor]) { + bootup_req[notifier->processor] = PEPIPHERAL_SSR_DOWN; + break; + } + bootup_req[notifier->processor] = PEPIPHERAL_SSR_UP; + break; + + default: + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: code: %lu\n", code); + break; + } + mutex_unlock(&driver->diag_notifier_mutex); + DIAG_LOG(DIAG_DEBUG_PERIPHERALS, + "diag: bootup_req[%s] = %d\n", + notifier->name, (int)bootup_req[notifier->processor]); + + return NOTIFY_DONE; +} + int diag_socket_init_peripheral(uint8_t peripheral) { struct diag_socket_info *info = NULL; diff --git a/drivers/char/diag/diagfwd_socket.h b/drivers/char/diag/diagfwd_socket.h index a2b922aa157c..a9487b1b3ac1 100644 --- a/drivers/char/diag/diagfwd_socket.h +++ b/drivers/char/diag/diagfwd_socket.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -24,10 +24,24 @@ #define PORT_TYPE_SERVER 0 #define PORT_TYPE_CLIENT 1 +#define PEPIPHERAL_AFTER_BOOT 0 +#define PEPIPHERAL_SSR_DOWN 1 +#define PEPIPHERAL_SSR_UP 2 + #define CNTL_CMD_NEW_SERVER 4 #define CNTL_CMD_REMOVE_SERVER 5 #define CNTL_CMD_REMOVE_CLIENT 6 +enum { + SOCKET_MODEM, + SOCKET_ADSP, + SOCKET_WCNSS, + SOCKET_SLPI, + SOCKET_CDSP, + SOCKET_APPS, + NUM_SOCKET_SUBSYSTEMS, +}; + struct diag_socket_info { uint8_t peripheral; uint8_t type; diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index ac815c6dbac0..6493b59dac01 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -188,6 +188,9 @@ static bool clk_core_is_enabled(struct clk_core *core) return core->ops->is_enabled(core->hw); } +static void clk_core_unprepare(struct clk_core *core); +static void clk_core_disable(struct clk_core *core); + static void clk_unprepare_unused_subtree(struct clk_core *core) { struct clk_core *child; @@ -207,7 +210,7 @@ static void clk_unprepare_unused_subtree(struct clk_core *core) */ if (core->need_handoff_prepare) { core->need_handoff_prepare = false; - core->prepare_count--; + clk_core_unprepare(core); } if (core->prepare_count) @@ -246,7 +249,9 @@ static void clk_disable_unused_subtree(struct clk_core *core) */ if (core->need_handoff_enable) { core->need_handoff_enable = false; - core->enable_count--; + flags = clk_enable_lock(); + clk_core_disable(core); + clk_enable_unlock(flags); } flags = clk_enable_lock(); diff --git a/drivers/clk/msm/Kconfig b/drivers/clk/msm/Kconfig index bfb697347ec5..3829f6aec124 100644 --- a/drivers/clk/msm/Kconfig +++ b/drivers/clk/msm/Kconfig @@ -7,7 +7,7 @@ config COMMON_CLK_MSM This support clock controller used by MSM devices which support global, mmss and gpu clock controller. Say Y if you want to support the clocks exposed by the MSM on - platforms such as msm8996, msm8998, msmfalcon etc. + platforms such as msm8996, msm8998 etc. config MSM_CLK_CONTROLLER_V2 bool "QTI clock driver" diff --git a/drivers/clk/msm/clock-gcc-8998.c b/drivers/clk/msm/clock-gcc-8998.c index b1d767a4cb6f..87cf6cc5631e 100644 --- a/drivers/clk/msm/clock-gcc-8998.c +++ b/drivers/clk/msm/clock-gcc-8998.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2799,6 +2799,9 @@ static int msm_gcc_8998_probe(struct platform_device *pdev) /* This clock is used for all MMSSCC register access */ clk_prepare_enable(&gcc_mmss_noc_cfg_ahb_clk.c); + /* Keep bimc gfx clock port on all the time */ + clk_prepare_enable(&gcc_bimc_gfx_clk.c); + /* This clock is used for all GPUCC register access */ clk_prepare_enable(&gcc_gpu_cfg_ahb_clk.c); diff --git a/drivers/clk/msm/clock-osm.c b/drivers/clk/msm/clock-osm.c index 9e1036c19760..79e8a7d8eb00 100644 --- a/drivers/clk/msm/clock-osm.c +++ b/drivers/clk/msm/clock-osm.c @@ -231,6 +231,8 @@ enum clk_osm_trace_packet_id { #define MSM8998V2_PWRCL_BOOT_RATE 1555200000 #define MSM8998V2_PERFCL_BOOT_RATE 1728000000 +#define DEBUG_REG_NUM 3 + /* ACD registers */ #define ACD_HW_VERSION 0x0 #define ACDCR 0x4 @@ -340,6 +342,12 @@ struct osm_entry { long frequency; }; +const char *clk_panic_reg_names[] = {"WDOG_DOMAIN_PSTATE_STATUS", + "WDOG_PROGRAM_COUNTER", + "APM_STATUS"}; +const int clk_panic_reg_offsets[] = {WDOG_DOMAIN_PSTATE_STATUS, + WDOG_PROGRAM_COUNTER}; + static struct dentry *osm_debugfs_base; struct clk_osm { @@ -350,6 +358,7 @@ struct clk_osm { struct platform_device *vdd_dev; void *vbases[NUM_BASES]; unsigned long pbases[NUM_BASES]; + void __iomem *debug_regs[DEBUG_REG_NUM]; spinlock_t lock; u32 cpu_reg_mask; @@ -1371,6 +1380,64 @@ static int clk_osm_resources_init(struct platform_device *pdev) perfcl_clk.acd_init = false; } + pwrcl_clk.debug_regs[0] = devm_ioremap(&pdev->dev, + pwrcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[0], + 0x4); + if (!pwrcl_clk.debug_regs[0]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[0]); + return -ENOMEM; + } + + pwrcl_clk.debug_regs[1] = devm_ioremap(&pdev->dev, + pwrcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[1], + 0x4); + if (!pwrcl_clk.debug_regs[1]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[1]); + return -ENOMEM; + } + + pwrcl_clk.debug_regs[2] = devm_ioremap(&pdev->dev, + pwrcl_clk.apm_ctrl_status, + 0x4); + if (!pwrcl_clk.debug_regs[2]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[2]); + return -ENOMEM; + } + + perfcl_clk.debug_regs[0] = devm_ioremap(&pdev->dev, + perfcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[0], + 0x4); + if (!perfcl_clk.debug_regs[0]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[0]); + return -ENOMEM; + } + + perfcl_clk.debug_regs[1] = devm_ioremap(&pdev->dev, + perfcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[1], + 0x4); + if (!perfcl_clk.debug_regs[1]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[1]); + return -ENOMEM; + } + + perfcl_clk.debug_regs[2] = devm_ioremap(&pdev->dev, + perfcl_clk.apm_ctrl_status, + 0x4); + if (!perfcl_clk.debug_regs[2]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[2]); + return -ENOMEM; + } + vdd_pwrcl = devm_regulator_get(&pdev->dev, "vdd-pwrcl"); if (IS_ERR(vdd_pwrcl)) { rc = PTR_ERR(vdd_pwrcl); @@ -2976,36 +3043,16 @@ static int clk_osm_panic_callback(struct notifier_block *nfb, unsigned long event, void *data) { - void __iomem *virt_addr; - u32 value, reg; + int i; + u32 value; struct clk_osm *c = container_of(nfb, struct clk_osm, panic_notifier); - reg = c->pbases[OSM_BASE] + WDOG_DOMAIN_PSTATE_STATUS; - virt_addr = ioremap(reg, 0x4); - if (virt_addr != NULL) { - value = readl_relaxed(virt_addr); - pr_err("DOM%d_PSTATE_STATUS[0x%08x]=0x%08x\n", c->cluster_num, - reg, value); - iounmap(virt_addr); - } - - reg = c->pbases[OSM_BASE] + WDOG_PROGRAM_COUNTER; - virt_addr = ioremap(reg, 0x4); - if (virt_addr != NULL) { - value = readl_relaxed(virt_addr); - pr_err("DOM%d_PROGRAM_COUNTER[0x%08x]=0x%08x\n", c->cluster_num, - reg, value); - iounmap(virt_addr); - } - - virt_addr = ioremap(c->apm_ctrl_status, 0x4); - if (virt_addr != NULL) { - value = readl_relaxed(virt_addr); - pr_err("APM_CTLER_STATUS_%d[0x%08x]=0x%08x\n", c->cluster_num, - c->apm_ctrl_status, value); - iounmap(virt_addr); + for (i = 0; i < DEBUG_REG_NUM; i++) { + value = readl_relaxed(c->debug_regs[i]); + pr_err("%s_%d=0x%08x\n", clk_panic_reg_names[i], + c->cluster_num, value); } return NOTIFY_OK; @@ -3108,17 +3155,17 @@ static int cpu_clock_osm_driver_probe(struct platform_device *pdev) msm8998_v2 = true; } - rc = clk_osm_resources_init(pdev); + rc = clk_osm_parse_dt_configs(pdev); if (rc) { - if (rc != -EPROBE_DEFER) - dev_err(&pdev->dev, "resources init failed, rc=%d\n", - rc); + dev_err(&pdev->dev, "Unable to parse device tree configurations\n"); return rc; } - rc = clk_osm_parse_dt_configs(pdev); + rc = clk_osm_resources_init(pdev); if (rc) { - dev_err(&pdev->dev, "Unable to parse device tree configurations\n"); + if (rc != -EPROBE_DEFER) + dev_err(&pdev->dev, "resources init failed, rc=%d\n", + rc); return rc; } diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index b5dd556b3f96..5a6b62892328 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -153,33 +153,33 @@ config MSM_MMCC_8996 Say Y if you want to support multimedia devices such as display, graphics, video encode/decode, camera, etc. -config MSM_GCC_FALCON - tristate "MSMFALCON Global Clock Controller" +config MSM_GCC_660 + tristate "SDM660 Global Clock Controller" select QCOM_GDSC depends on COMMON_CLK_QCOM ---help--- Support for the global clock controller on Qualcomm Technologies, Inc - MSMfalcon devices. + SDM660 devices. Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SD/eMMC, PCIe, etc. -config MSM_GPUCC_FALCON - tristate "MSMFALCON Graphics Clock Controller" - select MSM_GCC_FALCON +config MSM_GPUCC_660 + tristate "SDM660 Graphics Clock Controller" + select MSM_GCC_660 depends on COMMON_CLK_QCOM help Support for the graphics clock controller on Qualcomm Technologies, Inc - MSMfalcon devices. + SDM660 devices. Say Y if you want to support graphics controller devices which will be required to enable those device. -config MSM_MMCC_FALCON - tristate "MSMFALCON Multimedia Clock Controller" - select MSM_GCC_FALCON +config MSM_MMCC_660 + tristate "SDM660 Multimedia Clock Controller" + select MSM_GCC_660 depends on COMMON_CLK_QCOM help Support for the multimedia clock controller on Qualcomm Technologies, Inc - MSMfalcon devices. + SDM660 devices. Say Y if you want to support multimedia devices such as display, video encode/decode, camera, etc. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index a63065c97319..481cda67974b 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -25,12 +25,12 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o -obj-$(CONFIG_MSM_GCC_FALCON) += gcc-msmfalcon.o +obj-$(CONFIG_MSM_GCC_660) += gcc-sdm660.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o -obj-$(CONFIG_MSM_GPUCC_FALCON) += gpucc-msmfalcon.o -obj-$(CONFIG_MSM_MMCC_FALCON) += mmcc-msmfalcon.o +obj-$(CONFIG_MSM_GPUCC_660) += gpucc-sdm660.o +obj-$(CONFIG_MSM_MMCC_660) += mmcc-sdm660.o obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) += hfpll.o obj-$(CONFIG_KRAITCC) += krait-cc.o diff --git a/drivers/clk/qcom/clk-cpu-osm.c b/drivers/clk/qcom/clk-cpu-osm.c index ab6a1384ffbd..5ed0dba189f7 100644 --- a/drivers/clk/qcom/clk-cpu-osm.c +++ b/drivers/clk/qcom/clk-cpu-osm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -88,6 +88,7 @@ enum clk_osm_trace_packet_id { #define CORE_COUNT_VAL(val) ((val & GENMASK(18, 16)) >> 16) #define SINGLE_CORE 1 #define MAX_CORE_COUNT 4 +#define DEBUG_REG_NUM 3 #define ENABLE_REG 0x1004 #define INDEX_REG 0x1150 @@ -321,6 +322,13 @@ static struct dentry *osm_debugfs_base; static struct regulator *vdd_pwrcl; static struct regulator *vdd_perfcl; +const char *clk_panic_reg_names[] = {"WDOG_DOMAIN_PSTATE_STATUS", + "WDOG_PROGRAM_COUNTER", + "APM_STATUS"}; + +const int clk_panic_reg_offsets[] = {WDOG_DOMAIN_PSTATE_STATUS, + WDOG_PROGRAM_COUNTER}; + static const struct regmap_config osm_qcom_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -336,6 +344,7 @@ struct clk_osm { struct platform_device *vdd_dev; void *vbases[NUM_BASES]; unsigned long pbases[NUM_BASES]; + void __iomem *debug_regs[DEBUG_REG_NUM]; spinlock_t lock; u32 cpu_reg_mask; @@ -1366,6 +1375,64 @@ static int clk_osm_resources_init(struct platform_device *pdev) perfcl_clk.acd_init = false; } + pwrcl_clk.debug_regs[0] = devm_ioremap(&pdev->dev, + pwrcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[0], + 0x4); + if (!pwrcl_clk.debug_regs[0]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[0]); + return -ENOMEM; + } + + pwrcl_clk.debug_regs[1] = devm_ioremap(&pdev->dev, + pwrcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[1], + 0x4); + if (!pwrcl_clk.debug_regs[1]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[1]); + return -ENOMEM; + } + + pwrcl_clk.debug_regs[2] = devm_ioremap(&pdev->dev, + pwrcl_clk.apm_ctrl_status, + 0x4); + if (!pwrcl_clk.debug_regs[2]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[2]); + return -ENOMEM; + }; + + perfcl_clk.debug_regs[0] = devm_ioremap(&pdev->dev, + perfcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[0], + 0x4); + if (!perfcl_clk.debug_regs[0]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[0]); + return -ENOMEM; + } + + perfcl_clk.debug_regs[1] = devm_ioremap(&pdev->dev, + perfcl_clk.pbases[OSM_BASE] + + clk_panic_reg_offsets[1], + 0x4); + if (!perfcl_clk.debug_regs[1]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[1]); + return -ENOMEM; + } + + perfcl_clk.debug_regs[2] = devm_ioremap(&pdev->dev, + perfcl_clk.apm_ctrl_status, + 0x4); + if (!perfcl_clk.debug_regs[2]) { + dev_err(&pdev->dev, "Failed to map %s debug register\n", + clk_panic_reg_names[2]); + return -ENOMEM; + }; + vdd_pwrcl = devm_regulator_get(&pdev->dev, "vdd-pwrcl"); if (IS_ERR(vdd_pwrcl)) { rc = PTR_ERR(vdd_pwrcl); @@ -2859,36 +2926,16 @@ static int clk_osm_panic_callback(struct notifier_block *nfb, unsigned long event, void *data) { - void __iomem *virt_addr; - u32 value, reg; + int i; + u32 value; struct clk_osm *c = container_of(nfb, struct clk_osm, panic_notifier); - reg = c->pbases[OSM_BASE] + WDOG_DOMAIN_PSTATE_STATUS; - virt_addr = ioremap(reg, 0x4); - if (virt_addr != NULL) { - value = readl_relaxed(virt_addr); - pr_err("DOM%d_PSTATE_STATUS[0x%08x]=0x%08x\n", c->cluster_num, - reg, value); - iounmap(virt_addr); - } - - reg = c->pbases[OSM_BASE] + WDOG_PROGRAM_COUNTER; - virt_addr = ioremap(reg, 0x4); - if (virt_addr != NULL) { - value = readl_relaxed(virt_addr); - pr_err("DOM%d_PROGRAM_COUNTER[0x%08x]=0x%08x\n", c->cluster_num, - reg, value); - iounmap(virt_addr); - } - - virt_addr = ioremap(c->apm_ctrl_status, 0x4); - if (virt_addr != NULL) { - value = readl_relaxed(virt_addr); - pr_err("APM_CTLER_STATUS_%d[0x%08x]=0x%08x\n", c->cluster_num, - c->apm_ctrl_status, value); - iounmap(virt_addr); + for (i = 0; i < DEBUG_REG_NUM; i++) { + value = readl_relaxed(c->debug_regs[i]); + pr_err("%s_%d=0x%08x\n", clk_panic_reg_names[i], + c->cluster_num, value); } return NOTIFY_OK; @@ -3020,17 +3067,17 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) clk_data->clk_num = num_clks; - rc = clk_osm_resources_init(pdev); + rc = clk_osm_parse_dt_configs(pdev); if (rc) { - if (rc != -EPROBE_DEFER) - dev_err(&pdev->dev, "resources init failed, rc=%d\n", - rc); + dev_err(&pdev->dev, "Unable to parse device tree configurations\n"); return rc; } - rc = clk_osm_parse_dt_configs(pdev); + rc = clk_osm_resources_init(pdev); if (rc) { - dev_err(&pdev->dev, "Unable to parse device tree configurations\n"); + if (rc != -EPROBE_DEFER) + dev_err(&pdev->dev, "resources init failed, rc=%d\n", + rc); return rc; } diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index accdac9fb964..58fbd07e6f15 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -159,6 +159,7 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @parent_map: map from software's parent index to hardware's src_sel field * @freq_tbl: frequency table * @current_freq: last cached frequency when using branches with shared RCGs + * @enable_safe_config: When set, the RCG is parked at CXO when it's disabled * @clkr: regmap clock handle * @flags: set if RCG needs to be force enabled/disabled during * power sequence. @@ -173,6 +174,7 @@ struct clk_rcg2 { unsigned long current_freq; u32 new_index; u32 curr_index; + bool enable_safe_config; struct clk_regmap clkr; u8 flags; diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 653722f9c4b0..c37716e8273d 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -22,6 +22,7 @@ #include <linux/regmap.h> #include <linux/rational.h> #include <linux/math64.h> +#include <linux/clk.h> #include <asm/div64.h> @@ -49,6 +50,14 @@ #define N_REG 0xc #define D_REG 0x10 +static struct freq_tbl cxo_f = { + .freq = 19200000, + .src = 0, + .pre_div = 1, + .m = 0, + .n = 0, +}; + static int clk_rcg2_is_enabled(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); @@ -153,6 +162,17 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) return update_config(rcg); } +static void clk_rcg_clear_force_enable(struct clk_hw *hw) +{ + struct clk_rcg2 *rcg = to_clk_rcg2(hw); + + /* force disable RCG - clear CMD_ROOT_EN bit */ + regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, + CMD_ROOT_EN, 0); + /* Add a hardware mandate delay to disable the RCG */ + udelay(100); +} + /* * Calculate m/n:d rate * @@ -184,6 +204,12 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) struct clk_rcg2 *rcg = to_clk_rcg2(hw); u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask; + if (rcg->enable_safe_config && !clk_hw_is_prepared(hw)) { + if (!rcg->current_freq) + rcg->current_freq = cxo_f.freq; + return rcg->current_freq; + } + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); if (rcg->mnd_width) { @@ -425,14 +451,6 @@ static void disable_unprepare_rcg_srcs(struct clk_hw *hw, struct clk *curr, clk_unprepare(new); } -static struct freq_tbl cxo_f = { - .freq = 19200000, - .src = 0, - .pre_div = 1, - .m = 0, - .n = 0, -}; - static int clk_enable_disable_prepare_unprepare(struct clk_hw *hw, int cindex, int nindex, bool enable) { @@ -452,6 +470,7 @@ static int clk_rcg2_enable(struct clk_hw *hw) { int ret = 0; const struct freq_tbl *f; + unsigned long rate; struct clk_rcg2 *rcg = to_clk_rcg2(hw); if (rcg->flags & FORCE_ENABLE_RCGR) { @@ -477,9 +496,31 @@ static int clk_rcg2_enable(struct clk_hw *hw) clk_enable_disable_prepare_unprepare(hw, rcg->curr_index, rcg->new_index, false); + + return ret; } - return ret; + if (!rcg->enable_safe_config) + return 0; + + /* + * Switch from CXO to the stashed mux selection. Force enable and + * disable the RCG while configuring it to safeguard against any update + * signal coming from the downstream clock. The current parent has + * already been prepared and enabled at this point, and the CXO source + * is always on while APPS is online. Therefore, the RCG can safely be + * switched. + */ + rate = clk_get_rate(hw->clk); + f = qcom_find_freq(rcg->freq_tbl, rate); + if (!f) + return -EINVAL; + + clk_rcg_set_force_enable(hw); + clk_rcg2_configure(rcg, f); + clk_rcg_clear_force_enable(hw); + + return 0; } static void clk_rcg2_disable(struct clk_hw *hw) @@ -487,12 +528,31 @@ static void clk_rcg2_disable(struct clk_hw *hw) struct clk_rcg2 *rcg = to_clk_rcg2(hw); if (rcg->flags & FORCE_ENABLE_RCGR) { - /* force disable RCG - clear CMD_ROOT_EN bit */ - regmap_update_bits(rcg->clkr.regmap, - rcg->cmd_rcgr + CMD_REG, CMD_ROOT_EN, 0); - /* Add a delay to disable the RCG */ - udelay(100); + clk_rcg_clear_force_enable(hw); + return; } + + if (!rcg->enable_safe_config) + return; + /* + * Park the RCG at a safe configuration - sourced off the CXO. This is + * needed for 2 reasons: In the case of RCGs sourcing PSCBCs, due to a + * default HW behavior, the RCG will turn on when its corresponding + * GDSC is enabled. We might also have cases when the RCG might be left + * enabled without the overlying SW knowing about it. This results from + * hard to track cases of downstream clocks being left enabled. In both + * these cases, scaling the RCG will fail since it's enabled but with + * its sources cut off. + * + * Save mux select and switch to CXO. Force enable and disable the RCG + * while configuring it to safeguard against any update signal coming + * from the downstream clock. The current parent is still prepared and + * enabled at this point, and the CXO source is always on while APPS is + * online. Therefore, the RCG can safely be switched. + */ + clk_rcg_set_force_enable(hw); + clk_rcg2_configure(rcg, &cxo_f); + clk_rcg_clear_force_enable(hw); } @@ -506,6 +566,15 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate) if (rcg->flags & FORCE_ENABLE_RCGR) rcg->current_freq = clk_get_rate(hw->clk); + /* + * Return if the RCG is currently disabled. This configuration update + * will happen as part of the RCG enable sequence. + */ + if (rcg->enable_safe_config && !clk_hw_is_prepared(hw)) { + rcg->current_freq = rate; + return 0; + } + f = qcom_find_freq(rcg->freq_tbl, rate); if (!f) return -EINVAL; diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index d14c32bffe14..79db93ac5ae1 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Linaro Limited - * Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2014, 2016-2017, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -55,6 +55,7 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ .name = #_name, \ + .flags = CLK_ENABLE_HAND_OFF, \ .parent_names = (const char *[]){ "xo_board" }, \ .num_parents = 1, \ }, \ @@ -72,6 +73,7 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ .name = #_active, \ + .flags = CLK_ENABLE_HAND_OFF, \ .parent_names = (const char *[]){ "xo_board" }, \ .num_parents = 1, \ }, \ @@ -95,6 +97,7 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ .name = #_name, \ + .flags = CLK_ENABLE_HAND_OFF, \ .parent_names = (const char *[]){ "xo_board" }, \ .num_parents = 1, \ }, \ @@ -113,6 +116,7 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ .name = #_active, \ + .flags = CLK_ENABLE_HAND_OFF, \ .parent_names = (const char *[]){ "xo_board" }, \ .num_parents = 1, \ }, \ @@ -177,6 +181,8 @@ struct rpm_smd_clk_desc { static DEFINE_MUTEX(rpm_smd_clk_lock); +static int clk_smd_rpm_prepare(struct clk_hw *hw); + static int clk_smd_rpm_handoff(struct clk_hw *hw) { int ret = 0; @@ -198,6 +204,8 @@ static int clk_smd_rpm_handoff(struct clk_hw *hw) if (ret) return ret; + ret = clk_smd_rpm_prepare(hw); + return ret; } @@ -323,7 +331,7 @@ static void clk_smd_rpm_unprepare(struct clk_hw *hw) mutex_lock(&rpm_smd_clk_lock); if (!r->rate) - goto out; + goto enable; /* Take peer clock's rate into account only if it's enabled. */ if (peer->enabled) @@ -340,6 +348,7 @@ static void clk_smd_rpm_unprepare(struct clk_hw *hw) if (ret) goto out; +enable: r->enabled = false; out: @@ -461,12 +470,20 @@ static int clk_vote_bimc(struct clk_hw *hw, uint32_t rate) return ret; } +static int clk_smd_rpm_is_enabled(struct clk_hw *hw) +{ + struct clk_smd_rpm *r = to_clk_smd_rpm(hw); + + return r->enabled; +} + static const struct clk_ops clk_smd_rpm_ops = { .prepare = clk_smd_rpm_prepare, .unprepare = clk_smd_rpm_unprepare, .set_rate = clk_smd_rpm_set_rate, .round_rate = clk_smd_rpm_round_rate, .recalc_rate = clk_smd_rpm_recalc_rate, + .is_enabled = clk_smd_rpm_is_enabled, }; static const struct clk_ops clk_smd_rpm_branch_ops = { @@ -474,6 +491,7 @@ static const struct clk_ops clk_smd_rpm_branch_ops = { .unprepare = clk_smd_rpm_unprepare, .round_rate = clk_smd_rpm_round_rate, .recalc_rate = clk_smd_rpm_recalc_rate, + .is_enabled = clk_smd_rpm_is_enabled, }; /* msm8916 */ @@ -573,7 +591,7 @@ static DEFINE_CLK_VOTER(pnoc_msmbus_clk, pnoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, pnoc_a_clk, LONG_MAX); static DEFINE_CLK_VOTER(pnoc_pm_clk, pnoc_clk, LONG_MAX); static DEFINE_CLK_VOTER(pnoc_sps_clk, pnoc_clk, 0); -static DEFINE_CLK_VOTER(mmssnoc_a_clk_cpu_vote, mmssnoc_axi_rpm_a_clk, +static DEFINE_CLK_VOTER(mmssnoc_a_cpu_clk, mmssnoc_axi_a_clk, 19200000); /* Voter Branch clocks */ @@ -647,7 +665,6 @@ static struct clk_hw *msm8996_clks[] = { [CXO_OTG_CLK] = &cxo_otg_clk.hw, [CXO_PIL_LPASS_CLK] = &cxo_pil_lpass_clk.hw, [CXO_PIL_SSC_CLK] = &cxo_pil_ssc_clk.hw, - [MMSSNOC_A_CLK_CPU_VOTE] = &mmssnoc_a_clk_cpu_vote.hw }; static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { @@ -656,75 +673,75 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { .num_clks = ARRAY_SIZE(msm8996_clks), }; -/* msmfalcon */ -DEFINE_CLK_SMD_RPM_BRANCH(msmfalcon, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0, +/* sdm660 */ +DEFINE_CLK_SMD_RPM_BRANCH(sdm660, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); -DEFINE_CLK_SMD_RPM(msmfalcon, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msmfalcon, cnoc_periph_clk, cnoc_periph_a_clk, +DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, mmssnoc_axi_clk, mmssnoc_axi_a_clk, +DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); -DEFINE_CLK_SMD_RPM(msmfalcon, aggre2_noc_clk, aggre2_noc_a_clk, +DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); +DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_QDSS(msmfalcon, qdss_clk, qdss_a_clk, +DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, rf_clk1, rf_clk1_ao, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, div_clk1, div_clk1_ao, 0xb); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk1, ln_bb_clk1_ao, 0x1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk2, ln_bb_clk2_ao, 0x2); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk3, ln_bb_clk3_ao, 0x3); - -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, rf_clk1_pin, rf_clk1_ao_pin, 4); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk1_pin, +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_ao, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_ao, 0xb); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_ao, 0x1); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_ao, 0x2); +DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_ao, 0x3); + +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_ao_pin, 4); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin, ln_bb_clk1_pin_ao, 0x1); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk2_pin, +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin, ln_bb_clk2_pin_ao, 0x2); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk3_pin, +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_ao, 0x3); -static struct clk_hw *msmfalcon_clks[] = { - [RPM_XO_CLK_SRC] = &msmfalcon_cxo.hw, - [RPM_XO_A_CLK_SRC] = &msmfalcon_cxo_a.hw, - [RPM_SNOC_CLK] = &msmfalcon_snoc_clk.hw, - [RPM_SNOC_A_CLK] = &msmfalcon_snoc_a_clk.hw, - [RPM_BIMC_CLK] = &msmfalcon_bimc_clk.hw, - [RPM_BIMC_A_CLK] = &msmfalcon_bimc_a_clk.hw, - [RPM_QDSS_CLK] = &msmfalcon_qdss_clk.hw, - [RPM_QDSS_A_CLK] = &msmfalcon_qdss_a_clk.hw, - [RPM_RF_CLK1] = &msmfalcon_rf_clk1.hw, - [RPM_RF_CLK1_A] = &msmfalcon_rf_clk1_ao.hw, - [RPM_RF_CLK1_PIN] = &msmfalcon_rf_clk1_pin.hw, - [RPM_RF_CLK1_A_PIN] = &msmfalcon_rf_clk1_ao_pin.hw, - [RPM_AGGR2_NOC_CLK] = &msmfalcon_aggre2_noc_clk.hw, - [RPM_AGGR2_NOC_A_CLK] = &msmfalcon_aggre2_noc_a_clk.hw, - [RPM_CNOC_CLK] = &msmfalcon_cnoc_clk.hw, - [RPM_CNOC_A_CLK] = &msmfalcon_cnoc_a_clk.hw, - [RPM_IPA_CLK] = &msmfalcon_ipa_clk.hw, - [RPM_IPA_A_CLK] = &msmfalcon_ipa_a_clk.hw, - [RPM_CE1_CLK] = &msmfalcon_ce1_clk.hw, - [RPM_CE1_A_CLK] = &msmfalcon_ce1_a_clk.hw, - [RPM_DIV_CLK1] = &msmfalcon_div_clk1.hw, - [RPM_DIV_CLK1_AO] = &msmfalcon_div_clk1_ao.hw, - [RPM_LN_BB_CLK1] = &msmfalcon_ln_bb_clk1.hw, - [RPM_LN_BB_CLK1] = &msmfalcon_ln_bb_clk1_ao.hw, - [RPM_LN_BB_CLK1_PIN] = &msmfalcon_ln_bb_clk1_pin.hw, - [RPM_LN_BB_CLK1_PIN_AO] = &msmfalcon_ln_bb_clk1_pin_ao.hw, - [RPM_LN_BB_CLK2] = &msmfalcon_ln_bb_clk2.hw, - [RPM_LN_BB_CLK2_AO] = &msmfalcon_ln_bb_clk2_ao.hw, - [RPM_LN_BB_CLK2_PIN] = &msmfalcon_ln_bb_clk2_pin.hw, - [RPM_LN_BB_CLK2_PIN_AO] = &msmfalcon_ln_bb_clk2_pin_ao.hw, - [RPM_LN_BB_CLK3] = &msmfalcon_ln_bb_clk3.hw, - [RPM_LN_BB_CLK3_AO] = &msmfalcon_ln_bb_clk3_ao.hw, - [RPM_LN_BB_CLK3_PIN] = &msmfalcon_ln_bb_clk3_pin.hw, - [RPM_LN_BB_CLK3_PIN_AO] = &msmfalcon_ln_bb_clk3_pin_ao.hw, - [RPM_CNOC_PERIPH_CLK] = &msmfalcon_cnoc_periph_clk.hw, - [RPM_CNOC_PERIPH_A_CLK] = &msmfalcon_cnoc_periph_a_clk.hw, - [MMSSNOC_AXI_CLK] = &msmfalcon_mmssnoc_axi_clk.hw, - [MMSSNOC_AXI_A_CLK] = &msmfalcon_mmssnoc_axi_a_clk.hw, +static struct clk_hw *sdm660_clks[] = { + [RPM_XO_CLK_SRC] = &sdm660_cxo.hw, + [RPM_XO_A_CLK_SRC] = &sdm660_cxo_a.hw, + [RPM_SNOC_CLK] = &sdm660_snoc_clk.hw, + [RPM_SNOC_A_CLK] = &sdm660_snoc_a_clk.hw, + [RPM_BIMC_CLK] = &sdm660_bimc_clk.hw, + [RPM_BIMC_A_CLK] = &sdm660_bimc_a_clk.hw, + [RPM_QDSS_CLK] = &sdm660_qdss_clk.hw, + [RPM_QDSS_A_CLK] = &sdm660_qdss_a_clk.hw, + [RPM_RF_CLK1] = &sdm660_rf_clk1.hw, + [RPM_RF_CLK1_A] = &sdm660_rf_clk1_ao.hw, + [RPM_RF_CLK1_PIN] = &sdm660_rf_clk1_pin.hw, + [RPM_RF_CLK1_A_PIN] = &sdm660_rf_clk1_ao_pin.hw, + [RPM_AGGR2_NOC_CLK] = &sdm660_aggre2_noc_clk.hw, + [RPM_AGGR2_NOC_A_CLK] = &sdm660_aggre2_noc_a_clk.hw, + [RPM_CNOC_CLK] = &sdm660_cnoc_clk.hw, + [RPM_CNOC_A_CLK] = &sdm660_cnoc_a_clk.hw, + [RPM_IPA_CLK] = &sdm660_ipa_clk.hw, + [RPM_IPA_A_CLK] = &sdm660_ipa_a_clk.hw, + [RPM_CE1_CLK] = &sdm660_ce1_clk.hw, + [RPM_CE1_A_CLK] = &sdm660_ce1_a_clk.hw, + [RPM_DIV_CLK1] = &sdm660_div_clk1.hw, + [RPM_DIV_CLK1_AO] = &sdm660_div_clk1_ao.hw, + [RPM_LN_BB_CLK1] = &sdm660_ln_bb_clk1.hw, + [RPM_LN_BB_CLK1] = &sdm660_ln_bb_clk1_ao.hw, + [RPM_LN_BB_CLK1_PIN] = &sdm660_ln_bb_clk1_pin.hw, + [RPM_LN_BB_CLK1_PIN_AO] = &sdm660_ln_bb_clk1_pin_ao.hw, + [RPM_LN_BB_CLK2] = &sdm660_ln_bb_clk2.hw, + [RPM_LN_BB_CLK2_AO] = &sdm660_ln_bb_clk2_ao.hw, + [RPM_LN_BB_CLK2_PIN] = &sdm660_ln_bb_clk2_pin.hw, + [RPM_LN_BB_CLK2_PIN_AO] = &sdm660_ln_bb_clk2_pin_ao.hw, + [RPM_LN_BB_CLK3] = &sdm660_ln_bb_clk3.hw, + [RPM_LN_BB_CLK3_AO] = &sdm660_ln_bb_clk3_ao.hw, + [RPM_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin.hw, + [RPM_LN_BB_CLK3_PIN_AO] = &sdm660_ln_bb_clk3_pin_ao.hw, + [RPM_CNOC_PERIPH_CLK] = &sdm660_cnoc_periph_clk.hw, + [RPM_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk.hw, + [MMSSNOC_AXI_CLK] = &sdm660_mmssnoc_axi_clk.hw, + [MMSSNOC_AXI_A_CLK] = &sdm660_mmssnoc_axi_a_clk.hw, /* Voter Clocks */ [BIMC_MSMBUS_CLK] = &bimc_msmbus_clk.hw, @@ -744,18 +761,19 @@ static struct clk_hw *msmfalcon_clks[] = { [CXO_PIL_LPASS_CLK] = &cxo_pil_lpass_clk.hw, [CXO_PIL_CDSP_CLK] = &cxo_pil_cdsp_clk.hw, [CNOC_PERIPH_KEEPALIVE_A_CLK] = &cnoc_periph_keepalive_a_clk.hw, + [MMSSNOC_A_CLK_CPU_VOTE] = &mmssnoc_a_cpu_clk.hw }; -static const struct rpm_smd_clk_desc rpm_clk_msmfalcon = { - .clks = msmfalcon_clks, - .num_rpm_clks = RPM_CNOC_PERIPH_A_CLK, - .num_clks = ARRAY_SIZE(msmfalcon_clks), +static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { + .clks = sdm660_clks, + .num_rpm_clks = MMSSNOC_AXI_A_CLK, + .num_clks = ARRAY_SIZE(sdm660_clks), }; static const struct of_device_id rpm_smd_clk_match_table[] = { { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916}, { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996}, - { .compatible = "qcom,rpmcc-msmfalcon", .data = &rpm_clk_msmfalcon}, + { .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660}, { } }; MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); @@ -766,21 +784,21 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) struct clk *clk; struct rpm_cc *rcc; struct clk_onecell_data *data; - int ret, is_8996 = 0, is_falcon = 0; + int ret, is_8996 = 0, is_660 = 0; size_t num_clks, i; struct clk_hw **hw_clks; const struct rpm_smd_clk_desc *desc; is_8996 = of_device_is_compatible(pdev->dev.of_node, "qcom,rpmcc-msm8996"); - is_falcon = of_device_is_compatible(pdev->dev.of_node, - "qcom,rpmcc-msmfalcon"); + is_660 = of_device_is_compatible(pdev->dev.of_node, + "qcom,rpmcc-sdm660"); if (is_8996) { ret = clk_vote_bimc(&msm8996_bimc_clk.hw, INT_MAX); if (ret < 0) return ret; - } else if (is_falcon) { - ret = clk_vote_bimc(&msmfalcon_bimc_clk.hw, INT_MAX); + } else if (is_660) { + ret = clk_vote_bimc(&sdm660_bimc_clk.hw, INT_MAX); if (ret < 0) return ret; } @@ -813,6 +831,17 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) goto err; } + for (i = (desc->num_rpm_clks + 1); i < num_clks; i++) { + if (!hw_clks[i]) { + clks[i] = ERR_PTR(-ENOENT); + continue; + } + + ret = voter_clk_handoff(hw_clks[i]); + if (ret) + goto err; + } + ret = clk_smd_rpm_enable_scaling(); if (ret) goto err; @@ -847,14 +876,13 @@ static int rpm_smd_clk_probe(struct platform_device *pdev) /* Hold an active set vote for the pnoc_keepalive_a_clk */ clk_set_rate(pnoc_keepalive_a_clk.hw.clk, 19200000); clk_prepare_enable(pnoc_keepalive_a_clk.hw.clk); - - clk_prepare_enable(mmssnoc_a_clk_cpu_vote.hw.clk); - } else if (is_falcon) { - clk_prepare_enable(msmfalcon_cxo_a.hw.clk); + } else if (is_660) { + clk_prepare_enable(sdm660_cxo_a.hw.clk); /* Hold an active set vote for the cnoc_periph resource */ clk_set_rate(cnoc_periph_keepalive_a_clk.hw.clk, 19200000); clk_prepare_enable(cnoc_periph_keepalive_a_clk.hw.clk); + clk_prepare_enable(mmssnoc_a_cpu_clk.hw.clk); } dev_info(&pdev->dev, "Registered RPM clocks\n"); diff --git a/drivers/clk/qcom/clk-voter.c b/drivers/clk/qcom/clk-voter.c index d3409b9e6b64..60e319620e1b 100644 --- a/drivers/clk/qcom/clk-voter.c +++ b/drivers/clk/qcom/clk-voter.c @@ -123,6 +123,16 @@ static unsigned long voter_clk_recalc_rate(struct clk_hw *hw, return v->rate; } +int voter_clk_handoff(struct clk_hw *hw) +{ + struct clk_voter *v = to_clk_voter(hw); + + v->enabled = true; + + return 0; +} +EXPORT_SYMBOL(voter_clk_handoff); + struct clk_ops clk_ops_voter = { .prepare = voter_clk_prepare, .unprepare = voter_clk_unprepare, diff --git a/drivers/clk/qcom/clk-voter.h b/drivers/clk/qcom/clk-voter.h index 27092ae7d131..abc26cd94cd5 100644 --- a/drivers/clk/qcom/clk-voter.h +++ b/drivers/clk/qcom/clk-voter.h @@ -36,6 +36,7 @@ extern struct clk_ops clk_ops_voter; .hw.init = &(struct clk_init_data){ \ .ops = &clk_ops_voter, \ .name = #clk_name, \ + .flags = CLK_ENABLE_HAND_OFF, \ .parent_names = (const char *[]){ #_parent_name }, \ .num_parents = 1, \ }, \ @@ -47,4 +48,6 @@ extern struct clk_ops clk_ops_voter; #define DEFINE_CLK_BRANCH_VOTER(clk_name, _parent_name) \ __DEFINE_CLK_VOTER(clk_name, _parent_name, 1000, 1) +int voter_clk_handoff(struct clk_hw *hw); + #endif diff --git a/drivers/clk/qcom/gcc-msmfalcon.c b/drivers/clk/qcom/gcc-sdm660.c index 1e1c871ef22c..1ae71a6ee93b 100644 --- a/drivers/clk/qcom/gcc-msmfalcon.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -23,7 +23,7 @@ #include <linux/of_device.h> #include <linux/regmap.h> #include <linux/reset-controller.h> -#include <dt-bindings/clock/qcom,gcc-msmfalcon.h> +#include <dt-bindings/clock/qcom,gcc-sdm660.h> #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -32,7 +32,7 @@ #include "clk-regmap.h" #include "clk-rcg.h" #include "reset.h" -#include "vdd-level-falcon.h" +#include "vdd-level-660.h" #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } @@ -2580,7 +2580,7 @@ static struct clk_fixed_factor gcc_ce1_axi_m_clk = { }, }; -struct clk_hw *gcc_msmfalcon_hws[] = { +struct clk_hw *gcc_sdm660_hws[] = { [GCC_XO] = &xo.hw, [GCC_GPLL0_EARLY_DIV] = &gpll0_out_early_div.hw, [GCC_GPLL1_EARLY_DIV] = &gpll1_out_early_div.hw, @@ -2588,7 +2588,7 @@ struct clk_hw *gcc_msmfalcon_hws[] = { [GCC_CE1_AXI_M_CLK] = &gcc_ce1_axi_m_clk.hw, }; -static struct clk_regmap *gcc_falcon_clocks[] = { +static struct clk_regmap *gcc_660_clocks[] = { [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, @@ -2728,7 +2728,7 @@ static struct clk_regmap *gcc_falcon_clocks[] = { &hlos2_vote_turing_adsp_smmu_clk.clkr, }; -static const struct qcom_reset_map gcc_falcon_resets[] = { +static const struct qcom_reset_map gcc_660_resets[] = { [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, [GCC_UFS_BCR] = { 0x75000 }, @@ -2740,7 +2740,7 @@ static const struct qcom_reset_map gcc_falcon_resets[] = { [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, }; -static const struct regmap_config gcc_falcon_regmap_config = { +static const struct regmap_config gcc_660_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, @@ -2748,28 +2748,28 @@ static const struct regmap_config gcc_falcon_regmap_config = { .fast_io = true, }; -static const struct qcom_cc_desc gcc_falcon_desc = { - .config = &gcc_falcon_regmap_config, - .clks = gcc_falcon_clocks, - .num_clks = ARRAY_SIZE(gcc_falcon_clocks), - .hwclks = gcc_msmfalcon_hws, - .num_hwclks = ARRAY_SIZE(gcc_msmfalcon_hws), - .resets = gcc_falcon_resets, - .num_resets = ARRAY_SIZE(gcc_falcon_resets), +static const struct qcom_cc_desc gcc_660_desc = { + .config = &gcc_660_regmap_config, + .clks = gcc_660_clocks, + .num_clks = ARRAY_SIZE(gcc_660_clocks), + .hwclks = gcc_sdm660_hws, + .num_hwclks = ARRAY_SIZE(gcc_sdm660_hws), + .resets = gcc_660_resets, + .num_resets = ARRAY_SIZE(gcc_660_resets), }; -static const struct of_device_id gcc_falcon_match_table[] = { - { .compatible = "qcom,gcc-msmfalcon" }, +static const struct of_device_id gcc_660_match_table[] = { + { .compatible = "qcom,gcc-sdm660" }, { } }; -MODULE_DEVICE_TABLE(of, gcc_falcon_match_table); +MODULE_DEVICE_TABLE(of, gcc_660_match_table); -static int gcc_falcon_probe(struct platform_device *pdev) +static int gcc_660_probe(struct platform_device *pdev) { int ret = 0; struct regmap *regmap; - regmap = qcom_cc_map(pdev, &gcc_falcon_desc); + regmap = qcom_cc_map(pdev, &gcc_660_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); @@ -2795,7 +2795,7 @@ static int gcc_falcon_probe(struct platform_device *pdev) return PTR_ERR(vdd_dig_ao.regulator[0]); } - ret = qcom_cc_really_probe(pdev, &gcc_falcon_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gcc_660_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register GCC clocks\n"); return ret; @@ -2816,25 +2816,25 @@ static int gcc_falcon_probe(struct platform_device *pdev) return ret; } -static struct platform_driver gcc_falcon_driver = { - .probe = gcc_falcon_probe, +static struct platform_driver gcc_660_driver = { + .probe = gcc_660_probe, .driver = { - .name = "gcc-msmfalcon", - .of_match_table = gcc_falcon_match_table, + .name = "gcc-sdm660", + .of_match_table = gcc_660_match_table, }, }; -static int __init gcc_falcon_init(void) +static int __init gcc_660_init(void) { - return platform_driver_register(&gcc_falcon_driver); + return platform_driver_register(&gcc_660_driver); } -core_initcall_sync(gcc_falcon_init); +core_initcall_sync(gcc_660_init); -static void __exit gcc_falcon_exit(void) +static void __exit gcc_660_exit(void) { - platform_driver_unregister(&gcc_falcon_driver); + platform_driver_unregister(&gcc_660_driver); } -module_exit(gcc_falcon_exit); +module_exit(gcc_660_exit); /* Debug Mux for measure */ static struct measure_clk_data debug_mux_priv = { @@ -3028,7 +3028,7 @@ static struct clk_debug_mux gcc_debug_mux = { { "snoc_clk", 0x000 }, { "cnoc_clk", 0x00E }, { "cnoc_periph_clk", 0x198 }, - { "bimc_clk", 0x14E }, + { "bimc_clk", 0x19D }, { "ce1_clk", 0x097 }, { "ipa_clk", 0x11b }, { "gcc_aggre2_ufs_axi_clk", 0x10B }, @@ -3210,11 +3210,11 @@ static struct clk_debug_mux gcc_debug_mux = { }; static const struct of_device_id clk_debug_match_table[] = { - { .compatible = "qcom,gcc-debug-msmfalcon" }, + { .compatible = "qcom,gcc-debug-sdm660" }, {} }; -static int clk_debug_falcon_probe(struct platform_device *pdev) +static int clk_debug_660_probe(struct platform_device *pdev) { struct resource *res; struct clk *clk; @@ -3307,16 +3307,16 @@ static int clk_debug_falcon_probe(struct platform_device *pdev) } static struct platform_driver clk_debug_driver = { - .probe = clk_debug_falcon_probe, + .probe = clk_debug_660_probe, .driver = { - .name = "gcc-debug-msmfalcon", + .name = "gcc-debug-sdm660", .of_match_table = clk_debug_match_table, .owner = THIS_MODULE, }, }; -int __init clk_debug_falcon_init(void) +int __init clk_debug_660_init(void) { return platform_driver_register(&clk_debug_driver); } -fs_initcall(clk_debug_falcon_init); +fs_initcall(clk_debug_660_init); diff --git a/drivers/clk/qcom/gpucc-msmfalcon.c b/drivers/clk/qcom/gpucc-sdm660.c index 9b7dd907a6f3..fee5e73a1f88 100644 --- a/drivers/clk/qcom/gpucc-msmfalcon.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -22,7 +22,7 @@ #include <linux/of_device.h> #include <linux/regmap.h> #include <linux/reset-controller.h> -#include <dt-bindings/clock/qcom,gpu-msmfalcon.h> +#include <dt-bindings/clock/qcom,gpu-sdm660.h> #include "clk-alpha-pll.h" #include "common.h" @@ -30,7 +30,7 @@ #include "clk-pll.h" #include "clk-rcg.h" #include "clk-branch.h" -#include "vdd-level-falcon.h" +#include "vdd-level-660.h" #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } #define F_GFX(f, s, h, m, n, sf) { (f), (s), (2 * (h) - 1), (m), (n), (sf) } @@ -187,7 +187,7 @@ static const struct freq_tbl ftbl_gfx3d_clk_src[] = { { } }; -static const struct freq_tbl ftbl_gfx3d_clk_src_triton[] = { +static const struct freq_tbl ftbl_gfx3d_clk_src_630[] = { F_GFX( 19200000, 0, 1, 0, 0, 0), F_GFX(160000000, 0, 2, 0, 0, 640000000), F_GFX(240000000, 0, 2, 0, 0, 480000000), @@ -316,7 +316,7 @@ static struct clk_branch gpucc_rbcpr_clk = { }, }; -static struct clk_regmap *gpucc_falcon_clocks[] = { +static struct clk_regmap *gpucc_660_clocks[] = { [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, [GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr, [GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr, @@ -328,7 +328,7 @@ static struct clk_regmap *gpucc_falcon_clocks[] = { [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, }; -static const struct regmap_config gpucc_falcon_regmap_config = { +static const struct regmap_config gpucc_660_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, @@ -336,18 +336,18 @@ static const struct regmap_config gpucc_falcon_regmap_config = { .fast_io = true, }; -static const struct qcom_cc_desc gpucc_falcon_desc = { - .config = &gpucc_falcon_regmap_config, - .clks = gpucc_falcon_clocks, - .num_clks = ARRAY_SIZE(gpucc_falcon_clocks), +static const struct qcom_cc_desc gpucc_660_desc = { + .config = &gpucc_660_regmap_config, + .clks = gpucc_660_clocks, + .num_clks = ARRAY_SIZE(gpucc_660_clocks), }; -static const struct of_device_id gpucc_falcon_match_table[] = { - { .compatible = "qcom,gpucc-msmfalcon" }, - { .compatible = "qcom,gpucc-msmtriton" }, +static const struct of_device_id gpucc_660_match_table[] = { + { .compatible = "qcom,gpucc-sdm660" }, + { .compatible = "qcom,gpucc-sdm630" }, { } }; -MODULE_DEVICE_TABLE(of, gpucc_falcon_match_table); +MODULE_DEVICE_TABLE(of, gpucc_660_match_table); static int of_get_fmax_vdd_class(struct platform_device *pdev, struct clk_hw *hw, char *prop_name, u32 index) @@ -407,13 +407,13 @@ static int of_get_fmax_vdd_class(struct platform_device *pdev, return 0; } -static int gpucc_falcon_probe(struct platform_device *pdev) +static int gpucc_660_probe(struct platform_device *pdev) { int ret = 0; struct regmap *regmap; - bool is_triton = 0; + bool is_630 = 0; - regmap = qcom_cc_map(pdev, &gpucc_falcon_desc); + regmap = qcom_cc_map(pdev, &gpucc_660_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); @@ -444,15 +444,15 @@ static int gpucc_falcon_probe(struct platform_device *pdev) return PTR_ERR(vdd_gfx.regulator[0]); } - is_triton = of_device_is_compatible(pdev->dev.of_node, - "qcom,gpucc-msmtriton"); - if (is_triton) { + is_630 = of_device_is_compatible(pdev->dev.of_node, + "qcom,gpucc-sdm630"); + if (is_630) { gpu_pll0_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1] = 1550000000; gpu_pll1_pll_out_main.clkr.hw.init->rate_max[VDD_DIG_LOW_L1] = 1550000000; /* Add new frequency table */ - gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_triton; + gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_630; } /* GFX rail fmax data linked to branch clock */ @@ -464,7 +464,7 @@ static int gpucc_falcon_probe(struct platform_device *pdev) clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, &gpu_pll0_config); - ret = qcom_cc_really_probe(pdev, &gpucc_falcon_desc, regmap); + ret = qcom_cc_really_probe(pdev, &gpucc_660_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register GPUCC clocks\n"); return ret; @@ -477,22 +477,22 @@ static int gpucc_falcon_probe(struct platform_device *pdev) return ret; } -static struct platform_driver gpucc_falcon_driver = { - .probe = gpucc_falcon_probe, +static struct platform_driver gpucc_660_driver = { + .probe = gpucc_660_probe, .driver = { - .name = "gpucc-msmfalcon", - .of_match_table = gpucc_falcon_match_table, + .name = "gpucc-sdm660", + .of_match_table = gpucc_660_match_table, }, }; -static int __init gpucc_falcon_init(void) +static int __init gpucc_660_init(void) { - return platform_driver_register(&gpucc_falcon_driver); + return platform_driver_register(&gpucc_660_driver); } -core_initcall_sync(gpucc_falcon_init); +core_initcall_sync(gpucc_660_init); -static void __exit gpucc_falcon_exit(void) +static void __exit gpucc_660_exit(void) { - platform_driver_unregister(&gpucc_falcon_driver); + platform_driver_unregister(&gpucc_660_driver); } -module_exit(gpucc_falcon_exit); +module_exit(gpucc_660_exit); diff --git a/drivers/clk/qcom/mdss/mdss-pll.c b/drivers/clk/qcom/mdss/mdss-pll.c index b51ab4f21561..f356be38a25c 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.c +++ b/drivers/clk/qcom/mdss/mdss-pll.c @@ -133,9 +133,9 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, pll_res->pll_interface_type = MDSS_DSI_PLL_8996; pll_res->target_id = MDSS_PLL_TARGET_8996; pll_res->revision = 2; - } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_msmfalcon")) { + } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_sdm660")) { pll_res->pll_interface_type = MDSS_DSI_PLL_8996; - pll_res->target_id = MDSS_PLL_TARGET_MSMFALCON; + pll_res->target_id = MDSS_PLL_TARGET_SDM660; pll_res->revision = 2; } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) { pll_res->pll_interface_type = MDSS_DSI_PLL_8998; @@ -382,7 +382,7 @@ static const struct of_device_id mdss_pll_dt_match[] = { {.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"}, {.compatible = "qcom,mdss_dp_pll_8998"}, {.compatible = "qcom,mdss_hdmi_pll_8998"}, - {.compatible = "qcom,mdss_dsi_pll_msmfalcon"}, + {.compatible = "qcom,mdss_dsi_pll_sdm660"}, {} }; diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h index 01664eaa815c..e0e62a0f379b 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.h +++ b/drivers/clk/qcom/mdss/mdss-pll.h @@ -51,7 +51,7 @@ enum { enum { MDSS_PLL_TARGET_8996, - MDSS_PLL_TARGET_MSMFALCON, + MDSS_PLL_TARGET_SDM660, }; #define DFPS_MAX_NUM_OF_FRAME_RATES 20 diff --git a/drivers/clk/qcom/mmcc-msmfalcon.c b/drivers/clk/qcom/mmcc-sdm660.c index 59dbebd825fd..daece455454c 100644 --- a/drivers/clk/qcom/mmcc-msmfalcon.c +++ b/drivers/clk/qcom/mmcc-sdm660.c @@ -21,7 +21,7 @@ #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/reset-controller.h> -#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h> +#include <dt-bindings/clock/qcom,mmcc-sdm660.h> #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -32,7 +32,7 @@ #include "clk-regmap-divider.h" #include "clk-voter.h" #include "reset.h" -#include "vdd-level-falcon.h" +#include "vdd-level-660.h" #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } #define F_SLEW(f, s, h, m, n, src_freq) { (f), (s), (2 * (h) - 1), (m), (n), \ @@ -2816,12 +2816,12 @@ static struct clk_branch mmss_video_subcore0_clk = { }, }; -struct clk_hw *mmcc_msmfalcon_hws[] = { +struct clk_hw *mmcc_sdm660_hws[] = { [MMSS_CAMSS_JPEG0_VOTE_CLK] = &mmss_camss_jpeg0_vote_clk.hw, [MMSS_CAMSS_JPEG0_DMA_VOTE_CLK] = &mmss_camss_jpeg0_dma_vote_clk.hw, }; -static struct clk_regmap *mmcc_falcon_clocks[] = { +static struct clk_regmap *mmcc_660_clocks[] = { [AHB_CLK_SRC] = &ahb_clk_src.clkr, [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, @@ -2954,11 +2954,11 @@ static struct clk_regmap *mmcc_falcon_clocks[] = { [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, }; -static const struct qcom_reset_map mmcc_falcon_resets[] = { +static const struct qcom_reset_map mmcc_660_resets[] = { [CAMSS_MICRO_BCR] = { 0x3490 }, }; -static const struct regmap_config mmcc_falcon_regmap_config = { +static const struct regmap_config mmcc_660_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, @@ -2966,28 +2966,28 @@ static const struct regmap_config mmcc_falcon_regmap_config = { .fast_io = true, }; -static const struct qcom_cc_desc mmcc_falcon_desc = { - .config = &mmcc_falcon_regmap_config, - .clks = mmcc_falcon_clocks, - .num_clks = ARRAY_SIZE(mmcc_falcon_clocks), - .hwclks = mmcc_msmfalcon_hws, - .num_hwclks = ARRAY_SIZE(mmcc_msmfalcon_hws), - .resets = mmcc_falcon_resets, - .num_resets = ARRAY_SIZE(mmcc_falcon_resets), +static const struct qcom_cc_desc mmcc_660_desc = { + .config = &mmcc_660_regmap_config, + .clks = mmcc_660_clocks, + .num_clks = ARRAY_SIZE(mmcc_660_clocks), + .hwclks = mmcc_sdm660_hws, + .num_hwclks = ARRAY_SIZE(mmcc_sdm660_hws), + .resets = mmcc_660_resets, + .num_resets = ARRAY_SIZE(mmcc_660_resets), }; -static const struct of_device_id mmcc_falcon_match_table[] = { - { .compatible = "qcom,mmcc-msmfalcon" }, +static const struct of_device_id mmcc_660_match_table[] = { + { .compatible = "qcom,mmcc-sdm660" }, { } }; -MODULE_DEVICE_TABLE(of, mmcc_falcon_match_table); +MODULE_DEVICE_TABLE(of, mmcc_660_match_table); -static int mmcc_falcon_probe(struct platform_device *pdev) +static int mmcc_660_probe(struct platform_device *pdev) { int ret = 0; struct regmap *regmap; - regmap = qcom_cc_map(pdev, &mmcc_falcon_desc); + regmap = qcom_cc_map(pdev, &mmcc_660_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); @@ -3024,7 +3024,7 @@ static int mmcc_falcon_probe(struct platform_device *pdev) clk_alpha_pll_configure(&mmpll8_pll_out_main, regmap, &mmpll8_config); clk_alpha_pll_configure(&mmpll10_pll_out_main, regmap, &mmpll10_config); - ret = qcom_cc_really_probe(pdev, &mmcc_falcon_desc, regmap); + ret = qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register MMSS clocks\n"); return ret; @@ -3035,22 +3035,22 @@ static int mmcc_falcon_probe(struct platform_device *pdev) return ret; } -static struct platform_driver mmcc_falcon_driver = { - .probe = mmcc_falcon_probe, +static struct platform_driver mmcc_660_driver = { + .probe = mmcc_660_probe, .driver = { - .name = "mmcc-msmfalcon", - .of_match_table = mmcc_falcon_match_table, + .name = "mmcc-sdm660", + .of_match_table = mmcc_660_match_table, }, }; -static int __init mmcc_falcon_init(void) +static int __init mmcc_660_init(void) { - return platform_driver_register(&mmcc_falcon_driver); + return platform_driver_register(&mmcc_660_driver); } -core_initcall_sync(mmcc_falcon_init); +core_initcall_sync(mmcc_660_init); -static void __exit mmcc_falcon_exit(void) +static void __exit mmcc_660_exit(void) { - platform_driver_unregister(&mmcc_falcon_driver); + platform_driver_unregister(&mmcc_660_driver); } -module_exit(mmcc_falcon_exit); +module_exit(mmcc_660_exit); diff --git a/drivers/clk/qcom/vdd-level-falcon.h b/drivers/clk/qcom/vdd-level-660.h index 75567dbe2329..f98a96033ea9 100644 --- a/drivers/clk/qcom/vdd-level-falcon.h +++ b/drivers/clk/qcom/vdd-level-660.h @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ -#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H -#define __DRIVERS_CLK_QCOM_VDD_LEVEL_FALCON_H +#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H +#define __DRIVERS_CLK_QCOM_VDD_LEVEL_660_H #include <linux/regulator/rpm-smd-regulator.h> #include <linux/regulator/consumer.h> diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 118dbf1cef44..6ec828805428 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2333,6 +2333,9 @@ static int cpufreq_cpu_callback(struct notifier_block *nfb, { unsigned int cpu = (unsigned long)hcpu; + if (!cpufreq_driver) + return NOTIFY_OK; + switch (action & ~CPU_TASKS_FROZEN) { case CPU_ONLINE: cpufreq_online(cpu); @@ -2499,6 +2502,9 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data) pr_debug("trying to register driver %s\n", driver_data->name); + /* Register for hotplug notifers before blocking hotplug. */ + register_hotcpu_notifier(&cpufreq_cpu_notifier); + /* Protect against concurrent CPU online/offline. */ get_online_cpus(); @@ -2530,7 +2536,6 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data) goto err_if_unreg; } - register_hotcpu_notifier(&cpufreq_cpu_notifier); pr_info("driver %s up and running\n", driver_data->name); out: diff --git a/drivers/cpufreq/cpufreq_interactive.c b/drivers/cpufreq/cpufreq_interactive.c index 30e1a2138002..24ac49019b29 100644 --- a/drivers/cpufreq/cpufreq_interactive.c +++ b/drivers/cpufreq/cpufreq_interactive.c @@ -490,7 +490,7 @@ static void cpufreq_interactive_timer(unsigned long data) spin_lock_irqsave(&ppol->target_freq_lock, flags); spin_lock(&ppol->load_lock); - skip_hispeed_logic = tunables->enable_prediction ? true : + skip_hispeed_logic = tunables->ignore_hispeed_on_notif && ppol->notif_pending; skip_min_sample_time = tunables->fast_ramp_down && ppol->notif_pending; ppol->notif_pending = false; diff --git a/drivers/cpuidle/lpm-levels.c b/drivers/cpuidle/lpm-levels.c index 81801605d6e7..823b7d988284 100644 --- a/drivers/cpuidle/lpm-levels.c +++ b/drivers/cpuidle/lpm-levels.c @@ -1061,8 +1061,9 @@ static int cluster_select(struct lpm_cluster *cluster, bool from_idle, best_level = i; - if (predicted ? (pred_us <= pwr_params->max_residency) - : (sleep_us <= pwr_params->max_residency)) + if (from_idle && + (predicted ? (pred_us <= pwr_params->max_residency) + : (sleep_us <= pwr_params->max_residency))) break; } diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 11d88df37d31..32e7ad0e4a34 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -372,18 +372,18 @@ config CRYPTO_DEV_QCRYPTO config CRYPTO_DEV_QCOM_MSM_QCE tristate "Qualcomm Crypto Engine (QCE) module" - select CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_MSMFALCON || ARCH_MSMTRITON + select CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_SDM660 || ARCH_SDM630 default n help This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660 MSM8x55, MSM8960, MSM9615, MSM8916, MSM8994, MSM8996, FSM9900, - MSMTITANINUM, APQ8084, MSM8998, MSMFALCON and MSMTRITON. + MSMTITANINUM, APQ8084, MSM8998, SDM660 and SDM630. To compile this driver as a module, choose M here: the For MSM7x30 MSM8660 and MSM8x55 the module is called qce For MSM8960, APQ8064 and MSM9615 the module is called qce40 For MSM8974, MSM8916, MSM8994, MSM8996, MSM8992, MSMTITANIUM, - APQ8084, MSM8998, MSMFALCON and MSMTRITON the module is called qce50. + APQ8084, MSM8998, SDM660 and SDM630 the module is called qce50. config CRYPTO_DEV_QCEDEV tristate "QCEDEV Interface to CE module" @@ -391,7 +391,7 @@ config CRYPTO_DEV_QCEDEV help This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660, MSM8960, MSM9615, APQ8064, MSM8974, MSM8916, MSM8994, MSM8996, - APQ8084, MSM8998, MSMFALCON, MSMTRITON. This exposes the + APQ8084, MSM8998, SDM660, SDM630. This exposes the interface to the QCE hardware accelerator via IOCTLs. To compile this driver as a module, choose M here: the diff --git a/drivers/crypto/msm/ice.c b/drivers/crypto/msm/ice.c index 795d553f3318..027a0d0bd0b8 100644 --- a/drivers/crypto/msm/ice.c +++ b/drivers/crypto/msm/ice.c @@ -1658,6 +1658,9 @@ int qcom_ice_setup_ice_hw(const char *storage_type, int enable) struct ice_device *ice_dev = NULL; ice_dev = get_ice_device_from_storage_type(storage_type); + if (ice_dev == ERR_PTR(-EPROBE_DEFER)) + return -EPROBE_DEFER; + if (!ice_dev) return ret; diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 84d3ec98e6b9..7f29f3644fb6 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -3,7 +3,7 @@ config DRM_MSM tristate "MSM DRM" depends on DRM depends on ARCH_QCOM || (ARM && COMPILE_TEST) - depends on OF && COMMON_CLK + depends on OF select REGULATOR select DRM_KMS_HELPER select DRM_PANEL diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h index e6163384f9c1..2418ee003c22 100644 --- a/drivers/gpu/msm/adreno-gpulist.h +++ b/drivers/gpu/msm/adreno-gpulist.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2002,2007-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2002,2007-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -289,9 +289,11 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .major = 1, .minor = 2, .patchid = ANY_ID, - .features = ADRENO_64BIT, + .features = ADRENO_64BIT | ADRENO_CONTENT_PROTECTION | + ADRENO_CPZ_RETENTION, .pm4fw_name = "a530_pm4.fw", .pfpfw_name = "a530_pfp.fw", + .zap_name = "a512_zap", .gpudev = &adreno_a5xx_gpudev, .gmem_size = (SZ_256K + SZ_16K), .num_protected_regs = 0x20, diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c index bc681057250d..d997cdd2cc7e 100644 --- a/drivers/gpu/msm/kgsl_iommu.c +++ b/drivers/gpu/msm/kgsl_iommu.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2011-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -134,7 +134,7 @@ static void kgsl_iommu_unmap_globals(struct kgsl_pagetable *pagetable) } } -static void kgsl_iommu_map_globals(struct kgsl_pagetable *pagetable) +static int kgsl_iommu_map_globals(struct kgsl_pagetable *pagetable) { unsigned int i; @@ -143,9 +143,11 @@ static void kgsl_iommu_map_globals(struct kgsl_pagetable *pagetable) int ret = kgsl_mmu_map(pagetable, global_pt_entries[i].memdesc); - BUG_ON(ret); + if (ret) + return ret; } } + return 0; } static void kgsl_iommu_unmap_global_secure_pt_entry(struct kgsl_pagetable @@ -158,16 +160,16 @@ static void kgsl_iommu_unmap_global_secure_pt_entry(struct kgsl_pagetable } -static void kgsl_map_global_secure_pt_entry(struct kgsl_pagetable *pagetable) +static int kgsl_map_global_secure_pt_entry(struct kgsl_pagetable *pagetable) { - int ret; + int ret = 0; struct kgsl_memdesc *entry = kgsl_global_secure_pt_entry; if (entry != NULL) { entry->pagetable = pagetable; ret = kgsl_mmu_map(pagetable, entry); - BUG_ON(ret); } + return ret; } static void kgsl_iommu_remove_global(struct kgsl_mmu *mmu, @@ -1171,7 +1173,7 @@ static int _init_global_pt(struct kgsl_mmu *mmu, struct kgsl_pagetable *pt) goto done; } - kgsl_iommu_map_globals(pt); + ret = kgsl_iommu_map_globals(pt); done: if (ret) @@ -1227,7 +1229,7 @@ static int _init_secure_pt(struct kgsl_mmu *mmu, struct kgsl_pagetable *pt) ctx->regbase = iommu->regbase + KGSL_IOMMU_CB0_OFFSET + (cb_num << KGSL_IOMMU_CB_SHIFT); - kgsl_map_global_secure_pt_entry(pt); + ret = kgsl_map_global_secure_pt_entry(pt); done: if (ret) @@ -1288,7 +1290,7 @@ static int _init_per_process_pt(struct kgsl_mmu *mmu, struct kgsl_pagetable *pt) goto done; } - kgsl_iommu_map_globals(pt); + ret = kgsl_iommu_map_globals(pt); done: if (ret) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index a37b5ce9a6b2..287d839f98d0 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -2824,6 +2824,8 @@ err_late_init: unregister_hotcpu_notifier(&etm4_cpu_notifier); unregister_hotcpu_notifier(&etm4_cpu_dying_notifier); } + etmdrvdata[drvdata->cpu] = NULL; + dev_set_drvdata(dev, NULL); return ret; } diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c index fb2f27299417..11500fccc770 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -141,6 +141,7 @@ struct stm_drvdata { bool enable; DECLARE_BITMAP(entities, OST_ENTITY_MAX); bool data_barrier; + uint32_t ch_alloc_fail_count; }; static struct stm_drvdata *stmdrvdata; @@ -385,19 +386,26 @@ static const struct coresight_ops stm_cs_ops = { .source_ops = &stm_source_ops, }; -static uint32_t stm_channel_alloc(uint32_t off) +static uint32_t stm_channel_alloc(void) { struct stm_drvdata *drvdata = stmdrvdata; - uint32_t ch; - unsigned long flags; + uint32_t off, ch, num_ch_per_cpu; + int cpu; - spin_lock_irqsave(&drvdata->spinlock, flags); - do { - ch = find_next_zero_bit(drvdata->chs.bitmap, - NR_STM_CHANNEL, off); - } while ((ch < NR_STM_CHANNEL) && - test_and_set_bit(ch, drvdata->chs.bitmap)); - spin_unlock_irqrestore(&drvdata->spinlock, flags); + num_ch_per_cpu = NR_STM_CHANNEL/num_present_cpus(); + + cpu = get_cpu(); + + off = num_ch_per_cpu * cpu; + ch = find_next_zero_bit(drvdata->chs.bitmap, + NR_STM_CHANNEL, off); + if (ch > (off + num_ch_per_cpu)) { + put_cpu(); + return NR_STM_CHANNEL; + } + + set_bit(ch, drvdata->chs.bitmap); + put_cpu(); return ch; } @@ -405,11 +413,8 @@ static uint32_t stm_channel_alloc(uint32_t off) static void stm_channel_free(uint32_t ch) { struct stm_drvdata *drvdata = stmdrvdata; - unsigned long flags; - spin_lock_irqsave(&drvdata->spinlock, flags); clear_bit(ch, drvdata->chs.bitmap); - spin_unlock_irqrestore(&drvdata->spinlock, flags); } static int stm_send(void *addr, const void *data, uint32_t size) @@ -522,7 +527,14 @@ static inline int __stm_trace(uint32_t options, uint8_t entity_id, unsigned long ch_addr; /* allocate channel and get the channel address */ - ch = stm_channel_alloc(0); + ch = stm_channel_alloc(); + if (ch >= NR_STM_CHANNEL) { + drvdata->ch_alloc_fail_count++; + dev_err_ratelimited(drvdata->dev, + "Channel allocation failed %d", + drvdata->ch_alloc_fail_count); + return 0; + } ch_addr = (unsigned long)stm_channel_addr(drvdata, ch); /* send the ost header */ @@ -789,15 +801,18 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) if (boot_nr_channel) { res_size = min((resource_size_t)(boot_nr_channel * BYTES_PER_CHANNEL), resource_size(&res)); - bitmap_size = boot_nr_channel * sizeof(long); + bitmap_size = (boot_nr_channel + sizeof(long) - 1) / + sizeof(long); } else { res_size = min((resource_size_t)(NR_STM_CHANNEL * BYTES_PER_CHANNEL), resource_size(&res)); - bitmap_size = NR_STM_CHANNEL * sizeof(long); + bitmap_size = (NR_STM_CHANNEL + sizeof(long) - 1) / + sizeof(long); } drvdata->chs.base = devm_ioremap(dev, res.start, res_size); if (!drvdata->chs.base) return -ENOMEM; + drvdata->chs.bitmap = devm_kzalloc(dev, bitmap_size, GFP_KERNEL); if (!drvdata->chs.bitmap) return -ENOMEM; diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 9b8bcdffdfba..2557dcda7621 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -25,14 +25,6 @@ config INPUT if INPUT -config QPNP_POWER_ON - tristate "QPNP PMIC POWER-ON Driver" - depends on SPMI && ARCH_QCOM - help - This driver supports the power-on functionality on Qualcomm - PNP PMIC. It currently supports reporting the change in status of - the KPDPWR_N line (connected to the power-key). - config INPUT_LEDS tristate "Export input device LEDs in sysfs" depends on LEDS_CLASS diff --git a/drivers/input/Makefile b/drivers/input/Makefile index fd35ebf6acd9..2a6d05ab9170 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -7,7 +7,6 @@ obj-$(CONFIG_INPUT) += input-core.o input-core-y := input.o input-compat.o input-mt.o ff-core.o -obj-$(CONFIG_QPNP_POWER_ON) += qpnp-power-on.o obj-$(CONFIG_INPUT_FF_MEMLESS) += ff-memless.o obj-$(CONFIG_INPUT_POLLDEV) += input-polldev.o obj-$(CONFIG_INPUT_SPARSEKMAP) += sparse-keymap.o diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 9c1380b65b77..5cfa1848e37c 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -161,6 +161,15 @@ config INPUT_PMIC8XXX_PWRKEY To compile this driver as a module, choose M here: the module will be called pmic8xxx-pwrkey. +config INPUT_QPNP_POWER_ON + tristate "QPNP PMIC Power-on support" + depends on SPMI + help + This option enables device driver support for the power-on + functionality of Qualcomm Technologies, Inc. PNP PMICs. It supports + reporting the change in status of the KPDPWR_N line (connected to the + power-key) as well as reset features. + config INPUT_SPARCSPKR tristate "SPARC Speaker support" depends on PCI && SPARC64 diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index 4e806ac056ce..a5ab4b762d31 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_INPUT_PCSPKR) += pcspkr.o obj-$(CONFIG_INPUT_PM8941_PWRKEY) += pm8941-pwrkey.o obj-$(CONFIG_INPUT_PM8XXX_VIBRATOR) += pm8xxx-vibrator.o obj-$(CONFIG_INPUT_PMIC8XXX_PWRKEY) += pmic8xxx-pwrkey.o +obj-$(CONFIG_INPUT_QPNP_POWER_ON) += qpnp-power-on.o obj-$(CONFIG_INPUT_POWERMATE) += powermate.o obj-$(CONFIG_INPUT_PWM_BEEPER) += pwm-beeper.o obj-$(CONFIG_INPUT_RB532_BUTTON) += rb532_button.o diff --git a/drivers/input/qpnp-power-on.c b/drivers/input/misc/qpnp-power-on.c index 967b23cae05c..e1c16aa5da43 100644 --- a/drivers/input/qpnp-power-on.c +++ b/drivers/input/misc/qpnp-power-on.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -30,7 +30,7 @@ #include <linux/regulator/driver.h> #include <linux/regulator/machine.h> #include <linux/regulator/of_regulator.h> -#include <linux/qpnp/power-on.h> +#include <linux/input/qpnp-power-on.h> #include <linux/power_supply.h> #define PMIC_VER_8941 0x01 @@ -223,7 +223,7 @@ struct qpnp_pon { static int pon_ship_mode_en; module_param_named( - ship_mode_en, pon_ship_mode_en, int, S_IRUSR | S_IWUSR + ship_mode_en, pon_ship_mode_en, int, 0600 ); static struct qpnp_pon *sys_reset_dev; diff --git a/drivers/leds/leds-qpnp-flash-v2.c b/drivers/leds/leds-qpnp-flash-v2.c index 674ca6161af9..aa59677c4b6a 100644 --- a/drivers/leds/leds-qpnp-flash-v2.c +++ b/drivers/leds/leds-qpnp-flash-v2.c @@ -1733,7 +1733,7 @@ static int qpnp_flash_led_parse_common_dt(struct qpnp_flash_led *led, led->pdata->thermal_hysteresis = -EINVAL; rc = of_property_read_u32(node, "qcom,thermal-hysteresis", &val); if (!rc) { - if (led->pdata->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + if (led->pdata->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) val = THERMAL_HYST_TEMP_TO_VAL(val, 20); else val = THERMAL_HYST_TEMP_TO_VAL(val, 15); diff --git a/drivers/leds/leds-qpnp-wled.c b/drivers/leds/leds-qpnp-wled.c index 56750ac8e9e2..718badb16ea1 100644 --- a/drivers/leds/leds-qpnp-wled.c +++ b/drivers/leds/leds-qpnp-wled.c @@ -479,7 +479,7 @@ static int qpnp_wled_swire_avdd_config(struct qpnp_wled *wled) u8 val; if (wled->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE && - wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) return 0; if (!wled->disp_type_amoled || wled->avdd_mode_spmi) @@ -1103,11 +1103,11 @@ static bool is_avdd_trim_adjustment_required(struct qpnp_wled *wled) u8 reg = 0; /* - * AVDD trim adjustment is not required for pmi8998/pm2falcon and not + * AVDD trim adjustment is not required for pmi8998/pm660l and not * supported for pmi8994. */ if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE || + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PMI8994_SUBTYPE) return false; @@ -1133,7 +1133,7 @@ static int qpnp_wled_gm_config(struct qpnp_wled *wled) /* Configure the LOOP COMP GM register */ if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { if (wled->loop_auto_gm_en) reg |= QPNP_WLED_VLOOP_COMP_AUTO_GM_EN; @@ -1179,7 +1179,7 @@ static int qpnp_wled_ovp_config(struct qpnp_wled *wled) return 0; if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) ovp_table = qpnp_wled_ovp_thresholds_pmi8998; else ovp_table = qpnp_wled_ovp_thresholds_pmi8994; @@ -1264,10 +1264,10 @@ static int qpnp_wled_avdd_mode_config(struct qpnp_wled *wled) /* * At present, configuring the mode to SPMI/SWIRE for controlling - * AVDD voltage is available only in pmi8998/pm2falcon. + * AVDD voltage is available only in pmi8998/pm660l. */ if (wled->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE && - wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) return 0; /* AMOLED_VOUT should be configured for AMOLED */ @@ -1313,7 +1313,7 @@ static int qpnp_wled_ilim_config(struct qpnp_wled *wled) wled->ilim_ma = PMI8994_WLED_ILIM_MIN_MA; if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { ilim_table = qpnp_wled_ilim_settings_pmi8998; if (wled->ilim_ma > PMI8998_WLED_ILIM_MAX_MA) wled->ilim_ma = PMI8998_WLED_ILIM_MAX_MA; @@ -1352,7 +1352,7 @@ static int qpnp_wled_vref_config(struct qpnp_wled *wled) u8 reg = 0; if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) vref_setting = vref_setting_pmi8998; else vref_setting = vref_setting_pmi8994; @@ -1420,7 +1420,7 @@ static int qpnp_wled_config(struct qpnp_wled *wled) /* Configure auto PFM mode for LCD mode only */ if ((wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) && !wled->disp_type_amoled) { reg = 0; reg |= wled->lcd_auto_pfm_thresh; @@ -1563,7 +1563,7 @@ static int qpnp_wled_config(struct qpnp_wled *wled) reg = QPNP_WLED_SINK_TEST5_DIG; } else { reg = QPNP_WLED_SINK_TEST5_HYB; - if (wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + if (wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) reg |= QPNP_WLED_SINK_TEST5_HVG_PULL_STR_BIT; } @@ -1816,7 +1816,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) if (wled->disp_type_amoled) { if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) wled->loop_ea_gm = QPNP_WLED_LOOP_GM_DFLT_AMOLED_PMI8998; else @@ -1836,7 +1836,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { wled->loop_auto_gm_en = of_property_read_bool(pdev->dev.of_node, "qcom,loop-auto-gm-en"); @@ -1852,7 +1852,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { if (wled->pmic_rev_id->rev4 == PMI8998_V2P0_REV4) wled->lcd_auto_pfm_en = false; @@ -1905,7 +1905,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) wled->vref_uv = vref_setting_pmi8998.default_uv; else wled->vref_uv = vref_setting_pmi8994.default_uv; @@ -1929,7 +1929,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) wled->ovp_mv = 29600; else wled->ovp_mv = 29500; @@ -1943,7 +1943,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || - wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { + wled->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { if (wled->disp_type_amoled) wled->ilim_ma = PMI8998_AMOLED_DFLT_ILIM_MA; else diff --git a/drivers/media/dvb-core/dvb_ringbuffer.c b/drivers/media/dvb-core/dvb_ringbuffer.c index 0d44deed65bd..8ab60a4fec00 100644 --- a/drivers/media/dvb-core/dvb_ringbuffer.c +++ b/drivers/media/dvb-core/dvb_ringbuffer.c @@ -233,9 +233,11 @@ ssize_t dvb_ringbuffer_write_user(struct dvb_ringbuffer *rbuf, */ smp_store_release(&rbuf->pwrite, 0); } - status = copy_from_user(rbuf->data+rbuf->pwrite, buf, todo); - if (status) - return len - todo; + + if (copy_from_user(rbuf->data + rbuf->pwrite, buf, todo)) { + smp_store_release(&rbuf->pwrite, oldpwrite); + return -EFAULT; + } /* smp_store_release() for write pointer update, see above */ smp_store_release(&rbuf->pwrite, (rbuf->pwrite + todo) % rbuf->size); diff --git a/drivers/media/platform/msm/camera_v2/common/cam_soc_api.c b/drivers/media/platform/msm/camera_v2/common/cam_soc_api.c index 6c09f3820dfd..34fffa8dd7ce 100644 --- a/drivers/media/platform/msm/camera_v2/common/cam_soc_api.c +++ b/drivers/media/platform/msm/camera_v2/common/cam_soc_api.c @@ -686,6 +686,50 @@ error: } EXPORT_SYMBOL(msm_camera_regulator_enable); +/* set regulator mode */ +int msm_camera_regulator_set_mode(struct msm_cam_regulator *vdd_info, + int cnt, bool mode) +{ + int i; + int rc; + struct msm_cam_regulator *tmp = vdd_info; + + if (!tmp) { + pr_err("Invalid params"); + return -EINVAL; + } + CDBG("cnt : %d\n", cnt); + + for (i = 0; i < cnt; i++) { + if (tmp && !IS_ERR_OR_NULL(tmp->vdd)) { + CDBG("name : %s, enable : %d\n", tmp->name, mode); + if (mode) { + rc = regulator_set_mode(tmp->vdd, + REGULATOR_MODE_FAST); + if (rc < 0) { + pr_err("regulator enable failed %d\n", + i); + goto error; + } + } else { + rc = regulator_set_mode(tmp->vdd, + REGULATOR_MODE_NORMAL); + if (rc < 0) + pr_err("regulator disable failed %d\n", + i); + goto error; + } + } + tmp++; + } + + return 0; +error: + return rc; +} +EXPORT_SYMBOL(msm_camera_regulator_set_mode); + + /* Put regulators regulators */ void msm_camera_put_regulators(struct platform_device *pdev, struct msm_cam_regulator **vdd_info, int cnt) diff --git a/drivers/media/platform/msm/camera_v2/common/cam_soc_api.h b/drivers/media/platform/msm/camera_v2/common/cam_soc_api.h index 0e9d26bebe30..55074490bd72 100644 --- a/drivers/media/platform/msm/camera_v2/common/cam_soc_api.h +++ b/drivers/media/platform/msm/camera_v2/common/cam_soc_api.h @@ -248,6 +248,23 @@ int msm_camera_regulator_enable(struct msm_cam_regulator *vdd_info, int cnt, int enable); /** + * @brief : set the regultors mode + * + * This function sets the regulators for a specific + * mode. say:REGULATOR_MODE_FAST/REGULATOR_MODE_NORMAL + * + * @param vdd_info: Pointer to list of regulators + * @param cnt: Number of regulators to enable/disable + * @param mode: Flags specifies either enable/disable + * + * @return Status of operation. Negative in case of error. Zero otherwise. + */ + +int msm_camera_regulator_set_mode(struct msm_cam_regulator *vdd_info, + int cnt, bool mode); + + +/** * @brief : Release the regulators * * This function releases the regulator resources. diff --git a/drivers/media/platform/msm/camera_v2/common/msm_camera_io_util.c b/drivers/media/platform/msm/camera_v2/common/msm_camera_io_util.c index 6f438d59b30b..c243d587e308 100644 --- a/drivers/media/platform/msm/camera_v2/common/msm_camera_io_util.c +++ b/drivers/media/platform/msm/camera_v2/common/msm_camera_io_util.c @@ -394,6 +394,12 @@ int msm_camera_config_vreg(struct device *dev, struct camera_vreg_t *cam_vreg, pr_err("%s:%d vreg sequence invalid\n", __func__, __LINE__); return -EINVAL; } + + if (cam_vreg == NULL) { + pr_err("%s:%d cam_vreg sequence invalid\n", __func__, __LINE__); + return -EINVAL; + } + if (!num_vreg_seq) num_vreg_seq = num_vreg; diff --git a/drivers/media/platform/msm/camera_v2/fd/msm_fd_dev.c b/drivers/media/platform/msm/camera_v2/fd/msm_fd_dev.c index 31568da21fee..66eb3aebec83 100644 --- a/drivers/media/platform/msm/camera_v2/fd/msm_fd_dev.c +++ b/drivers/media/platform/msm/camera_v2/fd/msm_fd_dev.c @@ -364,7 +364,7 @@ static int msm_fd_vbif_error_handler(void *handle, uint32_t error) msm_fd_hw_get(fd, ctx->settings.speed); /* Get active buffer */ - active_buf = msm_fd_hw_get_active_buffer(fd); + active_buf = msm_fd_hw_get_active_buffer(fd, 1); if (active_buf == NULL) { dev_dbg(fd->dev, "no active buffer, return\n"); @@ -379,7 +379,7 @@ static int msm_fd_vbif_error_handler(void *handle, uint32_t error) msm_fd_hw_add_buffer(fd, active_buf); /* Schedule and restart */ - ret = msm_fd_hw_schedule_next_buffer(fd); + ret = msm_fd_hw_schedule_next_buffer(fd, 1); if (ret) { dev_err(fd->dev, "Cannot reschedule buffer, recovery failed\n"); fd->recovery_mode = 0; @@ -1221,11 +1221,12 @@ static void msm_fd_wq_handler(struct work_struct *work) int i; fd = container_of(work, struct msm_fd_device, work); - - active_buf = msm_fd_hw_get_active_buffer(fd); + MSM_FD_SPIN_LOCK(fd->slock, 1); + active_buf = msm_fd_hw_get_active_buffer(fd, 0); if (!active_buf) { /* This should never happen, something completely wrong */ dev_err(fd->dev, "Oops no active buffer empty queue\n"); + MSM_FD_SPIN_UNLOCK(fd->slock, 1); return; } ctx = vb2_get_drv_priv(active_buf->vb_v4l2_buf.vb2_buf.vb2_queue); @@ -1254,8 +1255,10 @@ static void msm_fd_wq_handler(struct work_struct *work) dev_dbg(fd->dev, "Got IRQ after Recovery\n"); } - /* We have the data from fd hw, we can start next processing */ - msm_fd_hw_schedule_next_buffer(fd); + if (fd->state == MSM_FD_DEVICE_RUNNING) { + /* We have the data from fd hw, we can start next processing */ + msm_fd_hw_schedule_next_buffer(fd, 0); + } /* Return buffer to vb queue */ active_buf->vb_v4l2_buf.sequence = ctx->fh.sequence; @@ -1270,8 +1273,12 @@ static void msm_fd_wq_handler(struct work_struct *work) fd_event->frame_id = ctx->sequence; v4l2_event_queue_fh(&ctx->fh, &event); - /* Release buffer from the device */ - msm_fd_hw_buffer_done(fd, active_buf); + if (fd->state == MSM_FD_DEVICE_RUNNING) { + /* Release buffer from the device */ + msm_fd_hw_buffer_done(fd, active_buf, 0); + } + + MSM_FD_SPIN_UNLOCK(fd->slock, 1); } /* diff --git a/drivers/media/platform/msm/camera_v2/fd/msm_fd_dev.h b/drivers/media/platform/msm/camera_v2/fd/msm_fd_dev.h index 7505f0585d42..6eae2b8d56fb 100644 --- a/drivers/media/platform/msm/camera_v2/fd/msm_fd_dev.h +++ b/drivers/media/platform/msm/camera_v2/fd/msm_fd_dev.h @@ -36,6 +36,18 @@ /* Max number of regulators defined in device tree */ #define MSM_FD_MAX_REGULATOR_NUM 3 +/* Conditional spin lock macro */ +#define MSM_FD_SPIN_LOCK(l, f) ({\ + if (f) \ + spin_lock(&l); \ +}) + +/* Conditional spin unlock macro */ +#define MSM_FD_SPIN_UNLOCK(l, f) ({ \ + if (f) \ + spin_unlock(&l); \ +}) + /* * struct msm_fd_size - Structure contain FD size related values. * @width: Image width. diff --git a/drivers/media/platform/msm/camera_v2/fd/msm_fd_hw.c b/drivers/media/platform/msm/camera_v2/fd/msm_fd_hw.c index 21d42a77accb..ea0db4d64c6d 100644 --- a/drivers/media/platform/msm/camera_v2/fd/msm_fd_hw.c +++ b/drivers/media/platform/msm/camera_v2/fd/msm_fd_hw.c @@ -1118,7 +1118,6 @@ static int msm_fd_hw_try_enable(struct msm_fd_device *fd, int enabled = 0; if (state == fd->state) { - fd->state = MSM_FD_DEVICE_RUNNING; atomic_set(&buffer->active, 1); @@ -1132,7 +1131,7 @@ static int msm_fd_hw_try_enable(struct msm_fd_device *fd, * msm_fd_hw_next_buffer - Get next buffer from fd device processing queue. * @fd: Fd device. */ -static struct msm_fd_buffer *msm_fd_hw_next_buffer(struct msm_fd_device *fd) +struct msm_fd_buffer *msm_fd_hw_get_next_buffer(struct msm_fd_device *fd) { struct msm_fd_buffer *buffer = NULL; @@ -1150,14 +1149,15 @@ static struct msm_fd_buffer *msm_fd_hw_next_buffer(struct msm_fd_device *fd) void msm_fd_hw_add_buffer(struct msm_fd_device *fd, struct msm_fd_buffer *buffer) { - spin_lock(&fd->slock); + MSM_FD_SPIN_LOCK(fd->slock, 1); atomic_set(&buffer->active, 0); init_completion(&buffer->completion); INIT_LIST_HEAD(&buffer->list); list_add_tail(&buffer->list, &fd->buf_queue); - spin_unlock(&fd->slock); + + MSM_FD_SPIN_UNLOCK(fd->slock, 1); } /* @@ -1173,8 +1173,7 @@ void msm_fd_hw_remove_buffers_from_queue(struct msm_fd_device *fd, struct msm_fd_buffer *active_buffer; unsigned long time; - spin_lock(&fd->slock); - + MSM_FD_SPIN_LOCK(fd->slock, 1); active_buffer = NULL; list_for_each_entry_safe(curr_buff, temp, &fd->buf_queue, list) { if (curr_buff->vb_v4l2_buf.vb2_buf.vb2_queue == vb2_q) { @@ -1189,21 +1188,31 @@ void msm_fd_hw_remove_buffers_from_queue(struct msm_fd_device *fd, } } } - spin_unlock(&fd->slock); + MSM_FD_SPIN_UNLOCK(fd->slock, 1); /* We need to wait active buffer to finish */ if (active_buffer) { time = wait_for_completion_timeout(&active_buffer->completion, msecs_to_jiffies(MSM_FD_PROCESSING_TIMEOUT_MS)); + + MSM_FD_SPIN_LOCK(fd->slock, 1); if (!time) { - /* Do a vb2 buffer done since it timed out */ - vb2_buffer_done(&active_buffer->vb_v4l2_buf.vb2_buf, - VB2_BUF_STATE_DONE); - /* Remove active buffer */ - msm_fd_hw_get_active_buffer(fd); - /* Schedule if other buffers are present in device */ - msm_fd_hw_schedule_next_buffer(fd); + if (atomic_read(&active_buffer->active)) { + atomic_set(&active_buffer->active, 0); + /* Do a vb2 buffer done since it timed out */ + vb2_buffer_done( + &active_buffer->vb_v4l2_buf.vb2_buf, + VB2_BUF_STATE_DONE); + /* Remove active buffer */ + msm_fd_hw_get_active_buffer(fd, 0); + /* Schedule if other buffers are present */ + msm_fd_hw_schedule_next_buffer(fd, 0); + } else { + dev_err(fd->dev, "activ buf no longer active\n"); + } } + fd->state = MSM_FD_DEVICE_IDLE; + MSM_FD_SPIN_UNLOCK(fd->slock, 1); } return; @@ -1215,22 +1224,19 @@ void msm_fd_hw_remove_buffers_from_queue(struct msm_fd_device *fd, * @buffer: Fd buffer. */ int msm_fd_hw_buffer_done(struct msm_fd_device *fd, - struct msm_fd_buffer *buffer) + struct msm_fd_buffer *buffer, u8 lock_flag) { int ret = 0; - - spin_lock(&fd->slock); + MSM_FD_SPIN_LOCK(fd->slock, lock_flag); if (atomic_read(&buffer->active)) { atomic_set(&buffer->active, 0); complete_all(&buffer->completion); } else { - dev_err(fd->dev, "Buffer is not active\n"); ret = -1; } - spin_unlock(&fd->slock); - + MSM_FD_SPIN_UNLOCK(fd->slock, lock_flag); return ret; } @@ -1238,17 +1244,18 @@ int msm_fd_hw_buffer_done(struct msm_fd_device *fd, * msm_fd_hw_get_active_buffer - Get active buffer from fd processing queue. * @fd: Fd device. */ -struct msm_fd_buffer *msm_fd_hw_get_active_buffer(struct msm_fd_device *fd) +struct msm_fd_buffer *msm_fd_hw_get_active_buffer(struct msm_fd_device *fd, + u8 lock_flag) { struct msm_fd_buffer *buffer = NULL; - spin_lock(&fd->slock); + MSM_FD_SPIN_LOCK(fd->slock, lock_flag); if (!list_empty(&fd->buf_queue)) { buffer = list_first_entry(&fd->buf_queue, struct msm_fd_buffer, list); list_del(&buffer->list); } - spin_unlock(&fd->slock); + MSM_FD_SPIN_UNLOCK(fd->slock, lock_flag); return buffer; } @@ -1263,12 +1270,13 @@ int msm_fd_hw_schedule_and_start(struct msm_fd_device *fd) { struct msm_fd_buffer *buf; - spin_lock(&fd->slock); - buf = msm_fd_hw_next_buffer(fd); + MSM_FD_SPIN_LOCK(fd->slock, 1); + + buf = msm_fd_hw_get_next_buffer(fd); if (buf) msm_fd_hw_try_enable(fd, buf, MSM_FD_DEVICE_IDLE); - spin_unlock(&fd->slock); + MSM_FD_SPIN_UNLOCK(fd->slock, 1); msm_fd_hw_update_settings(fd, buf); @@ -1281,26 +1289,26 @@ int msm_fd_hw_schedule_and_start(struct msm_fd_device *fd) * * NOTE: This can be executed only when device is in running state. */ -int msm_fd_hw_schedule_next_buffer(struct msm_fd_device *fd) +int msm_fd_hw_schedule_next_buffer(struct msm_fd_device *fd, u8 lock_flag) { struct msm_fd_buffer *buf; int ret; - spin_lock(&fd->slock); + MSM_FD_SPIN_LOCK(fd->slock, lock_flag); /* We can schedule next buffer only in running state */ if (fd->state != MSM_FD_DEVICE_RUNNING) { dev_err(fd->dev, "Can not schedule next buffer\n"); - spin_unlock(&fd->slock); + MSM_FD_SPIN_UNLOCK(fd->slock, lock_flag); return -EBUSY; } - buf = msm_fd_hw_next_buffer(fd); + buf = msm_fd_hw_get_next_buffer(fd); if (buf) { ret = msm_fd_hw_try_enable(fd, buf, MSM_FD_DEVICE_RUNNING); if (0 == ret) { - dev_err(fd->dev, "Ouch can not process next buffer\n"); - spin_unlock(&fd->slock); + dev_err(fd->dev, "Can not process next buffer\n"); + MSM_FD_SPIN_UNLOCK(fd->slock, lock_flag); return -EBUSY; } } else { @@ -1308,7 +1316,7 @@ int msm_fd_hw_schedule_next_buffer(struct msm_fd_device *fd) if (fd->recovery_mode) dev_err(fd->dev, "No Buffer in recovery mode.Device Idle\n"); } - spin_unlock(&fd->slock); + MSM_FD_SPIN_UNLOCK(fd->slock, lock_flag); msm_fd_hw_update_settings(fd, buf); diff --git a/drivers/media/platform/msm/camera_v2/fd/msm_fd_hw.h b/drivers/media/platform/msm/camera_v2/fd/msm_fd_hw.h index ea2e4cc1d117..62b381e5bfa6 100644 --- a/drivers/media/platform/msm/camera_v2/fd/msm_fd_hw.h +++ b/drivers/media/platform/msm/camera_v2/fd/msm_fd_hw.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -71,12 +71,15 @@ void msm_fd_hw_remove_buffers_from_queue(struct msm_fd_device *fd, struct vb2_queue *vb2_q); int msm_fd_hw_buffer_done(struct msm_fd_device *fd, - struct msm_fd_buffer *buffer); + struct msm_fd_buffer *buffer, u8 lock_flag); + +struct msm_fd_buffer *msm_fd_hw_get_active_buffer(struct msm_fd_device *fd, + u8 lock_flag); -struct msm_fd_buffer *msm_fd_hw_get_active_buffer(struct msm_fd_device *fd); +struct msm_fd_buffer *msm_fd_hw_get_next_buffer(struct msm_fd_device *fd); int msm_fd_hw_schedule_and_start(struct msm_fd_device *fd); -int msm_fd_hw_schedule_next_buffer(struct msm_fd_device *fd); +int msm_fd_hw_schedule_next_buffer(struct msm_fd_device *fd, u8 lock_flag); #endif /* __MSM_FD_HW_H__ */ diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp.c index 35daf30bac63..840d84388a17 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp.c @@ -500,6 +500,10 @@ static int vfe_probe(struct platform_device *pdev) memset(&vfe_common_data, 0, sizeof(vfe_common_data)); mutex_init(&vfe_common_data.vfe_common_mutex); spin_lock_init(&vfe_common_data.common_dev_data_lock); + spin_lock_init(&vfe_common_data.vfe_irq_dump. + common_dev_irq_dump_lock); + spin_lock_init(&vfe_common_data.vfe_irq_dump. + common_dev_tasklet_dump_lock); for (i = 0; i < (VFE_AXI_SRC_MAX * MAX_VFE); i++) spin_lock_init(&(vfe_common_data.streams[i].lock)); for (i = 0; i < (MSM_ISP_STATS_MAX * MAX_VFE); i++) diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp.h index 9c7eba21fde1..4b881f4fd7b6 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp.h +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp.h @@ -66,6 +66,8 @@ #define MAX_BUFFERS_IN_HW 2 #define MAX_VFE 2 +#define MAX_VFE_IRQ_DEBUG_DUMP_SIZE 10 +#define MAX_RECOVERY_THRESHOLD 5 struct vfe_device; struct msm_vfe_axi_stream; @@ -133,6 +135,8 @@ struct msm_isp_timestamp { }; struct msm_vfe_irq_ops { + void (*read_and_clear_irq_status)(struct vfe_device *vfe_dev, + uint32_t *irq_status0, uint32_t *irq_status1); void (*read_irq_status)(struct vfe_device *vfe_dev, uint32_t *irq_status0, uint32_t *irq_status1); void (*process_reg_update)(struct vfe_device *vfe_dev, @@ -525,6 +529,7 @@ struct msm_vfe_axi_shared_data { uint16_t stream_handle_cnt; uint32_t event_mask; uint8_t enable_frameid_recovery; + uint8_t recovery_count; }; struct msm_vfe_stats_hardware_info { @@ -691,6 +696,26 @@ struct master_slave_resource_info { enum msm_vfe_dual_cam_sync_mode dual_sync_mode; }; +struct msm_vfe_irq_debug_info { + uint32_t vfe_id; + struct msm_isp_timestamp ts; + uint32_t core_id; + uint32_t irq_status0[MAX_VFE]; + uint32_t irq_status1[MAX_VFE]; + uint32_t ping_pong_status[MAX_VFE]; +}; + +struct msm_vfe_irq_dump { + spinlock_t common_dev_irq_dump_lock; + spinlock_t common_dev_tasklet_dump_lock; + uint8_t current_irq_index; + uint8_t current_tasklet_index; + struct msm_vfe_irq_debug_info + irq_debug[MAX_VFE_IRQ_DEBUG_DUMP_SIZE]; + struct msm_vfe_irq_debug_info + tasklet_debug[MAX_VFE_IRQ_DEBUG_DUMP_SIZE]; +}; + struct msm_vfe_common_dev_data { spinlock_t common_dev_data_lock; struct dual_vfe_resource *dual_vfe_res; @@ -698,6 +723,8 @@ struct msm_vfe_common_dev_data { struct msm_vfe_axi_stream streams[VFE_AXI_SRC_MAX * MAX_VFE]; struct msm_vfe_stats_stream stats_streams[MSM_ISP_STATS_MAX * MAX_VFE]; struct mutex vfe_common_mutex; + /* Irq debug Info */ + struct msm_vfe_irq_dump vfe_irq_dump; }; struct msm_vfe_common_subdev { @@ -790,8 +817,9 @@ struct vfe_device { /* irq info */ uint32_t irq0_mask; uint32_t irq1_mask; - uint32_t bus_err_ign_mask; + uint32_t recovery_irq0_mask; + uint32_t recovery_irq1_mask; }; struct vfe_parent_device { diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c index 43f562b18209..bf18fc59585c 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp32.c @@ -576,7 +576,7 @@ static void msm_vfe32_process_error_status(struct vfe_device *vfe_dev) pr_err("%s: axi error\n", __func__); } -static void msm_vfe32_read_irq_status(struct vfe_device *vfe_dev, +static void msm_vfe32_read_and_clear_irq_status(struct vfe_device *vfe_dev, uint32_t *irq_status0, uint32_t *irq_status1) { *irq_status0 = msm_camera_io_r(vfe_dev->vfe_base + 0x2C); @@ -594,6 +594,13 @@ static void msm_vfe32_read_irq_status(struct vfe_device *vfe_dev, msm_camera_io_r(vfe_dev->vfe_base + 0x7B4); } +static void msm_vfe32_read_irq_status(struct vfe_device *vfe_dev, + uint32_t *irq_status0, uint32_t irq_status1) +{ + *irq_status0 = msm_camera_io_r(vfe_dev->vfe_base + 0x2C); + *irq_status1 = msm_camera_io_r(vfe_dev->vfe_base + 0x30); +} + static void msm_vfe32_process_reg_update(struct vfe_device *vfe_dev, uint32_t irq_status0, uint32_t irq_status1, struct msm_isp_timestamp *ts) @@ -1423,6 +1430,8 @@ struct msm_vfe_hardware_info vfe32_hw_info = { .vfe_clk_idx = VFE32_CLK_IDX, .vfe_ops = { .irq_ops = { + .read_and_clear_irq_status = + msm_vfe32_read_and_clear_irq_status, .read_irq_status = msm_vfe32_read_irq_status, .process_camif_irq = msm_vfe32_process_camif_irq, .process_reset_irq = msm_vfe32_process_reset_irq, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c index ab01d37790d6..8e549c338bdd 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp40.c @@ -566,7 +566,7 @@ static void msm_vfe40_process_error_status(struct vfe_device *vfe_dev) msm_isp_update_last_overflow_ab_ib(vfe_dev); } -static void msm_vfe40_read_irq_status(struct vfe_device *vfe_dev, +static void msm_vfe40_read_and_clear_irq_status(struct vfe_device *vfe_dev, uint32_t *irq_status0, uint32_t *irq_status1) { *irq_status0 = msm_camera_io_r(vfe_dev->vfe_base + 0x38); @@ -599,6 +599,13 @@ static void msm_vfe40_read_irq_status(struct vfe_device *vfe_dev, } +static void msm_vfe40_read_irq_status(struct vfe_device *vfe_dev, + uint32_t *irq_status0, uint32_t *irq_status1) +{ + *irq_status0 = msm_camera_io_r(vfe_dev->vfe_base + 0x38); + *irq_status1 = msm_camera_io_r(vfe_dev->vfe_base + 0x3C); +} + static void msm_vfe40_process_reg_update(struct vfe_device *vfe_dev, uint32_t irq_status0, uint32_t irq_status1, struct msm_isp_timestamp *ts) @@ -1770,7 +1777,8 @@ static int msm_vfe40_axi_halt(struct vfe_device *vfe_dev, static void msm_vfe40_axi_restart(struct vfe_device *vfe_dev, uint32_t blocking, uint32_t enable_camif) { - msm_vfe40_config_irq(vfe_dev, 0x800000E0, 0xFEFFFF7E, + msm_vfe40_config_irq(vfe_dev, vfe_dev->recovery_irq0_mask, + vfe_dev->recovery_irq1_mask, MSM_ISP_IRQ_ENABLE); msm_camera_io_w_mb(0x140000, vfe_dev->vfe_base + 0x318); @@ -2198,6 +2206,8 @@ struct msm_vfe_hardware_info vfe40_hw_info = { .min_ib = 12000000, .vfe_ops = { .irq_ops = { + .read_and_clear_irq_status = + msm_vfe40_read_and_clear_irq_status, .read_irq_status = msm_vfe40_read_irq_status, .process_camif_irq = msm_vfe40_process_input_irq, .process_reset_irq = msm_vfe40_process_reset_irq, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp44.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp44.c index 0a72a041de28..957cbc292be3 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp44.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp44.c @@ -401,7 +401,7 @@ static void msm_vfe44_process_error_status(struct vfe_device *vfe_dev) } } -static void msm_vfe44_read_irq_status(struct vfe_device *vfe_dev, +static void msm_vfe44_read_and_clear_irq_status(struct vfe_device *vfe_dev, uint32_t *irq_status0, uint32_t *irq_status1) { *irq_status0 = msm_camera_io_r(vfe_dev->vfe_base + 0x38); @@ -429,6 +429,13 @@ static void msm_vfe44_read_irq_status(struct vfe_device *vfe_dev, } +static void msm_vfe44_read_irq_status(struct vfe_device *vfe_dev, + uint32_t *irq_status0, uint32_t *irq_status1) +{ + *irq_status0 = msm_camera_io_r(vfe_dev->vfe_base + 0x38); + *irq_status1 = msm_camera_io_r(vfe_dev->vfe_base + 0x3C); +} + static void msm_vfe44_process_reg_update(struct vfe_device *vfe_dev, uint32_t irq_status0, uint32_t irq_status1, struct msm_isp_timestamp *ts) @@ -1341,8 +1348,8 @@ static int msm_vfe44_axi_halt(struct vfe_device *vfe_dev, static void msm_vfe44_axi_restart(struct vfe_device *vfe_dev, uint32_t blocking, uint32_t enable_camif) { - msm_vfe44_config_irq(vfe_dev, 0x800000E0, 0xFFFFFF7E, - MSM_ISP_IRQ_ENABLE); + msm_vfe44_config_irq(vfe_dev, vfe_dev->recovery_irq0_mask, + vfe_dev->recovery_irq1_mask, MSM_ISP_IRQ_ENABLE); msm_camera_io_w_mb(0x140000, vfe_dev->vfe_base + 0x318); /* Start AXI */ @@ -1806,6 +1813,8 @@ struct msm_vfe_hardware_info vfe44_hw_info = { .min_ib = 100000000, .vfe_ops = { .irq_ops = { + .read_and_clear_irq_status = + msm_vfe44_read_and_clear_irq_status, .read_irq_status = msm_vfe44_read_irq_status, .process_camif_irq = msm_vfe44_process_input_irq, .process_reset_irq = msm_vfe44_process_reset_irq, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp46.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp46.c index f2d53c956fdc..cc768db875db 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp46.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp46.c @@ -345,7 +345,7 @@ static void msm_vfe46_process_error_status(struct vfe_device *vfe_dev) pr_err("%s: status bf scale bus overflow\n", __func__); } -static void msm_vfe46_read_irq_status(struct vfe_device *vfe_dev, +static void msm_vfe46_read_and_clear_irq_status(struct vfe_device *vfe_dev, uint32_t *irq_status0, uint32_t *irq_status1) { *irq_status0 = msm_camera_io_r(vfe_dev->vfe_base + 0x6C); @@ -369,6 +369,13 @@ static void msm_vfe46_read_irq_status(struct vfe_device *vfe_dev, } +static void msm_vfe46_read_irq_status(struct vfe_device *vfe_dev, + uint32_t *irq_status0, uint32_t *irq_status1) +{ + *irq_status0 = msm_camera_io_r(vfe_dev->vfe_base + 0x6C); + *irq_status1 = msm_camera_io_r(vfe_dev->vfe_base + 0x70); +} + static void msm_vfe46_process_reg_update(struct vfe_device *vfe_dev, uint32_t irq_status0, uint32_t irq_status1, struct msm_isp_timestamp *ts) @@ -1406,7 +1413,8 @@ static int msm_vfe46_axi_halt(struct vfe_device *vfe_dev, static void msm_vfe46_axi_restart(struct vfe_device *vfe_dev, uint32_t blocking, uint32_t enable_camif) { - msm_vfe46_config_irq(vfe_dev, 0x810000E0, 0xFFFFFF7E, + msm_vfe46_config_irq(vfe_dev, vfe_dev->recovery_irq0_mask, + vfe_dev->recovery_irq1_mask, MSM_ISP_IRQ_ENABLE); msm_camera_io_w_mb(0x20000, vfe_dev->vfe_base + 0x3CC); @@ -1882,6 +1890,8 @@ struct msm_vfe_hardware_info vfe46_hw_info = { .min_ib = 100000000, .vfe_ops = { .irq_ops = { + .read_and_clear_irq_status = + msm_vfe46_read_and_clear_irq_status, .read_irq_status = msm_vfe46_read_irq_status, .process_camif_irq = msm_vfe46_process_input_irq, .process_reset_irq = msm_vfe46_process_reset_irq, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c index 13c6e000fefc..9747cfd6dca3 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c @@ -30,13 +30,10 @@ #define CDBG(fmt, args...) pr_debug(fmt, ##args) #define VFE47_8996V1_VERSION 0x70000000 -#define VFE48_SDM660_VERSION 0x80000003 #define VFE47_BURST_LEN 3 -#define VFE48_SDM660_BURST_LEN 4 #define VFE47_FETCH_BURST_LEN 3 #define VFE47_STATS_BURST_LEN 3 -#define VFE48_SDM660_STATS_BURST_LEN 4 #define VFE47_UB_SIZE_VFE0 2048 #define VFE47_UB_SIZE_VFE1 1536 #define VFE47_UB_STATS_SIZE 144 @@ -559,7 +556,7 @@ void msm_vfe47_process_error_status(struct vfe_device *vfe_dev) pr_err("%s: status dsp error\n", __func__); } -void msm_vfe47_read_irq_status(struct vfe_device *vfe_dev, +void msm_vfe47_read_and_clear_irq_status(struct vfe_device *vfe_dev, uint32_t *irq_status0, uint32_t *irq_status1) { *irq_status0 = msm_camera_io_r(vfe_dev->vfe_base + 0x6C); @@ -585,6 +582,13 @@ void msm_vfe47_read_irq_status(struct vfe_device *vfe_dev, } +void msm_vfe47_read_irq_status(struct vfe_device *vfe_dev, + uint32_t *irq_status0, uint32_t *irq_status1) +{ + *irq_status0 = msm_camera_io_r(vfe_dev->vfe_base + 0x6C); + *irq_status1 = msm_camera_io_r(vfe_dev->vfe_base + 0x70); +} + void msm_vfe47_process_reg_update(struct vfe_device *vfe_dev, uint32_t irq_status0, uint32_t irq_status1, struct msm_isp_timestamp *ts) @@ -1595,7 +1599,7 @@ void msm_vfe47_axi_cfg_wm_reg( { uint32_t val; int vfe_idx = msm_isp_get_vfe_idx_for_stream(vfe_dev, stream_info); - uint32_t wm_base, burst_len; + uint32_t wm_base; wm_base = VFE47_WM_BASE(stream_info->wm[vfe_idx][plane_idx]); val = msm_camera_io_r(vfe_dev->vfe_base + wm_base + 0x14); @@ -1613,11 +1617,7 @@ void msm_vfe47_axi_cfg_wm_reg( output_height - 1); msm_camera_io_w(val, vfe_dev->vfe_base + wm_base + 0x1C); /* WR_BUFFER_CFG */ - if (vfe_dev->vfe_hw_version == VFE48_SDM660_VERSION) - burst_len = VFE48_SDM660_BURST_LEN; - else - burst_len = VFE47_BURST_LEN; - val = burst_len | + val = VFE47_BURST_LEN | (stream_info->plane_cfg[vfe_idx][plane_idx]. output_height - 1) << 2 | @@ -1938,7 +1938,9 @@ void msm_vfe47_axi_restart(struct vfe_device *vfe_dev, uint32_t blocking, uint32_t enable_camif) { vfe_dev->hw_info->vfe_ops.irq_ops.config_irq(vfe_dev, - 0x810000E0, 0xFFFFFF7E, MSM_ISP_IRQ_ENABLE); + vfe_dev->recovery_irq0_mask, + vfe_dev->recovery_irq1_mask, + MSM_ISP_IRQ_ENABLE); /* Start AXI */ msm_camera_io_w(0x0, vfe_dev->vfe_base + 0x400); @@ -2212,7 +2214,7 @@ void msm_vfe47_stats_clear_wm_reg( void msm_vfe47_stats_cfg_ub(struct vfe_device *vfe_dev) { int i; - uint32_t ub_offset = 0, stats_burst_len; + uint32_t ub_offset = 0; uint32_t ub_size[VFE47_NUM_STATS_TYPE] = { 16, /* MSM_ISP_STATS_HDR_BE */ 16, /* MSM_ISP_STATS_BG */ @@ -2231,14 +2233,9 @@ void msm_vfe47_stats_cfg_ub(struct vfe_device *vfe_dev) else pr_err("%s: incorrect VFE device\n", __func__); - if (vfe_dev->vfe_hw_version == VFE48_SDM660_VERSION) - stats_burst_len = VFE48_SDM660_STATS_BURST_LEN; - else - stats_burst_len = VFE47_STATS_BURST_LEN; - for (i = 0; i < VFE47_NUM_STATS_TYPE; i++) { ub_offset -= ub_size[i]; - msm_camera_io_w(stats_burst_len << 30 | + msm_camera_io_w(VFE47_STATS_BURST_LEN << 30 | ub_offset << 16 | (ub_size[i] - 1), vfe_dev->vfe_base + VFE47_STATS_BASE(i) + 0x14); } @@ -2795,7 +2792,8 @@ struct msm_vfe_hardware_info vfe47_hw_info = { .min_ab = 100000000, .vfe_ops = { .irq_ops = { - .read_irq_status = msm_vfe47_read_irq_status, + .read_and_clear_irq_status = + msm_vfe47_read_and_clear_irq_status, .process_camif_irq = msm_vfe47_process_input_irq, .process_reset_irq = msm_vfe47_process_reset_irq, .process_halt_irq = msm_vfe47_process_halt_irq, @@ -2805,6 +2803,7 @@ struct msm_vfe_hardware_info vfe47_hw_info = { .process_stats_irq = msm_isp_process_stats_irq, .process_epoch_irq = msm_vfe47_process_epoch_irq, .config_irq = msm_vfe47_config_irq, + .read_irq_status = msm_vfe47_read_irq_status, }, .axi_ops = { .reload_wm = msm_vfe47_axi_reload_wm, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.h index 55cf6a17b18c..22a1a21bce9a 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.h +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.h @@ -30,6 +30,8 @@ enum msm_vfe47_stats_comp_idx { extern struct msm_vfe_hardware_info vfe47_hw_info; +void msm_vfe47_read_and_clear_irq_status(struct vfe_device *vfe_dev, + uint32_t *irq_status0, uint32_t *irq_status1); void msm_vfe47_read_irq_status(struct vfe_device *vfe_dev, uint32_t *irq_status0, uint32_t *irq_status1); void msm_vfe47_enable_camif_error(struct vfe_device *vfe_dev, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp48.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp48.c index f346ceb6c9e5..1f2db9683cd0 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp48.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp48.c @@ -26,6 +26,25 @@ #include "cam_soc_api.h" #define MSM_VFE48_BUS_CLIENT_INIT 0xABAB +#define VFE48_STATS_BURST_LEN 3 +#define VFE48_UB_SIZE_VFE 2048 /* 2048 * 256 bits = 64KB */ +#define VFE48_UB_STATS_SIZE 144 +#define MSM_ISP48_TOTAL_IMAGE_UB_VFE (VFE48_UB_SIZE_VFE - VFE48_UB_STATS_SIZE) + + +static uint32_t stats_base_addr[] = { + 0x1D4, /* HDR_BE */ + 0x254, /* BG(AWB_BG) */ + 0x214, /* BF */ + 0x1F4, /* HDR_BHIST */ + 0x294, /* RS */ + 0x2B4, /* CS */ + 0x2D4, /* IHIST */ + 0x274, /* BHIST (SKIN_BHIST) */ + 0x234, /* AEC_BG */ +}; + +#define VFE48_STATS_BASE(idx) (stats_base_addr[idx]) static struct msm_vfe_axi_hardware_info msm_vfe48_axi_hw_info = { .num_wm = 7, @@ -260,6 +279,40 @@ static void msm_vfe48_set_bus_err_ign_mask(struct vfe_device *vfe_dev, vfe_dev->bus_err_ign_mask &= ~(1 << wm); } +void msm_vfe48_stats_cfg_ub(struct vfe_device *vfe_dev) +{ + int i; + uint32_t ub_offset = 0, stats_burst_len; + uint32_t ub_size[VFE47_NUM_STATS_TYPE] = { + 16, /* MSM_ISP_STATS_HDR_BE */ + 16, /* MSM_ISP_STATS_BG */ + 16, /* MSM_ISP_STATS_BF */ + 16, /* MSM_ISP_STATS_HDR_BHIST */ + 16, /* MSM_ISP_STATS_RS */ + 16, /* MSM_ISP_STATS_CS */ + 16, /* MSM_ISP_STATS_IHIST */ + 16, /* MSM_ISP_STATS_BHIST */ + 16, /* MSM_ISP_STATS_AEC_BG */ + }; + + stats_burst_len = VFE48_STATS_BURST_LEN; + ub_offset = VFE48_UB_SIZE_VFE; + + for (i = 0; i < VFE47_NUM_STATS_TYPE; i++) { + ub_offset -= ub_size[i]; + msm_camera_io_w(stats_burst_len << 30 | + ub_offset << 16 | (ub_size[i] - 1), + vfe_dev->vfe_base + VFE48_STATS_BASE(i) + 0x14); + } +} + +uint32_t msm_vfe48_get_ub_size(struct vfe_device *vfe_dev) +{ + return MSM_ISP48_TOTAL_IMAGE_UB_VFE; +} + + + struct msm_vfe_hardware_info vfe48_hw_info = { .num_iommu_ctx = 1, .num_iommu_secure_ctx = 0, @@ -269,6 +322,8 @@ struct msm_vfe_hardware_info vfe48_hw_info = { .min_ab = 100000000, .vfe_ops = { .irq_ops = { + .read_and_clear_irq_status = + msm_vfe47_read_and_clear_irq_status, .read_irq_status = msm_vfe47_read_irq_status, .process_camif_irq = msm_vfe47_process_input_irq, .process_reset_irq = msm_vfe47_process_reset_irq, @@ -307,7 +362,7 @@ struct msm_vfe_hardware_info vfe48_hw_info = { .update_cgc_override = msm_vfe47_axi_update_cgc_override, .ub_reg_offset = msm_vfe47_ub_reg_offset, - .get_ub_size = msm_vfe47_get_ub_size, + .get_ub_size = msm_vfe48_get_ub_size, }, .core_ops = { .reg_update = msm_vfe47_reg_update, @@ -345,7 +400,7 @@ struct msm_vfe_hardware_info vfe48_hw_info = { .clear_wm_irq_mask = msm_vfe47_stats_clear_wm_irq_mask, .cfg_wm_reg = msm_vfe47_stats_cfg_wm_reg, .clear_wm_reg = msm_vfe47_stats_clear_wm_reg, - .cfg_ub = msm_vfe47_stats_cfg_ub, + .cfg_ub = msm_vfe48_stats_cfg_ub, .enable_module = msm_vfe47_stats_enable_module, .update_ping_pong_addr = msm_vfe47_stats_update_ping_pong_addr, diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h index ccca2010105f..3cf819fb1174 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h @@ -32,4 +32,8 @@ static inline int msm_vfe_is_vfe48(struct vfe_device *vfe_dev) MSM_VFE48_HW_VERSION_MASK) == MSM_VFE48_HW_VERSION); } +void msm_vfe48_stats_cfg_ub(struct vfe_device *vfe_dev); +uint32_t msm_vfe48_get_ub_size(struct vfe_device *vfe_dev); + + #endif /* __MSM_ISP48_H__ */ diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c index 941119fad78e..60801ff6be0a 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c @@ -558,6 +558,7 @@ static int msm_isp_composite_irq(struct vfe_device *vfe_dev, { /* interrupt recv on same vfe w/o recv on other vfe */ if (stream_info->composite_irq[irq] & (1 << vfe_dev->pdev->id)) { + msm_isp_dump_ping_pong_mismatch(vfe_dev); pr_err("%s: irq %d out of sync for dual vfe on vfe %d\n", __func__, irq, vfe_dev->pdev->id); return -EINVAL; @@ -1604,7 +1605,23 @@ void msm_isp_halt_send_error(struct vfe_device *vfe_dev, uint32_t event) struct msm_isp_event_data error_event; struct msm_vfe_axi_halt_cmd halt_cmd; struct vfe_device *temp_dev = NULL; + uint32_t irq_status0 = 0, irq_status1 = 0; + if (atomic_read(&vfe_dev->error_info.overflow_state) != + NO_OVERFLOW) + /* Recovery is already in Progress */ + return; + + if (event == ISP_EVENT_PING_PONG_MISMATCH && + vfe_dev->axi_data.recovery_count < MAX_RECOVERY_THRESHOLD) { + pr_err("%s: ping pong mismatch on vfe%d recovery count %d\n", + __func__, vfe_dev->pdev->id, + vfe_dev->axi_data.recovery_count); + msm_isp_process_overflow_irq(vfe_dev, + &irq_status0, &irq_status1, 1); + vfe_dev->axi_data.recovery_count++; + return; + } memset(&halt_cmd, 0, sizeof(struct msm_vfe_axi_halt_cmd)); memset(&error_event, 0, sizeof(struct msm_isp_event_data)); halt_cmd.stop_camif = 1; @@ -3777,6 +3794,7 @@ void msm_isp_process_axi_irq_stream(struct vfe_device *vfe_dev, (~(pingpong_status >> stream_info->wm[vfe_idx][i]) & 0x1)) { spin_unlock_irqrestore(&stream_info->lock, flags); + msm_isp_dump_ping_pong_mismatch(vfe_dev); pr_err("%s: Write master ping pong mismatch. Status: 0x%x %x\n", __func__, pingpong_status, stream_info->stream_src); @@ -3798,7 +3816,7 @@ void msm_isp_process_axi_irq_stream(struct vfe_device *vfe_dev, spin_unlock_irqrestore(&stream_info->lock, flags); if (rc < 0) msm_isp_halt_send_error(vfe_dev, - ISP_EVENT_BUF_FATAL_ERROR); + ISP_EVENT_PING_PONG_MISMATCH); return; } diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_stats_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_stats_util.c index 38ce78d941c9..72703c9590ed 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_stats_util.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_stats_util.c @@ -195,7 +195,7 @@ static int32_t msm_isp_stats_buf_divert(struct vfe_device *vfe_dev, spin_unlock_irqrestore(&stream_info->lock, flags); if (rc < 0) msm_isp_halt_send_error(vfe_dev, - ISP_EVENT_BUF_FATAL_ERROR); + ISP_EVENT_PING_PONG_MISMATCH); return rc; } diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c index 4abb6d1d91a8..e238f54a9100 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c @@ -21,6 +21,9 @@ #include "msm_camera_io_util.h" #include "cam_smmu_api.h" #include "msm_isp48.h" +#define CREATE_TRACE_POINTS +#include "trace/events/msm_cam.h" + #define MAX_ISP_V4l2_EVENTS 100 static DEFINE_MUTEX(bandwidth_mgr_mutex); @@ -1784,9 +1787,10 @@ static inline void msm_isp_update_error_info(struct vfe_device *vfe_dev, vfe_dev->error_info.error_count++; } -static int msm_isp_process_overflow_irq( +int msm_isp_process_overflow_irq( struct vfe_device *vfe_dev, - uint32_t *irq_status0, uint32_t *irq_status1) + uint32_t *irq_status0, uint32_t *irq_status1, + uint8_t force_overflow) { uint32_t overflow_mask; uint32_t bus_err = 0; @@ -1816,7 +1820,7 @@ static int msm_isp_process_overflow_irq( get_overflow_mask(&overflow_mask); overflow_mask &= *irq_status1; - if (overflow_mask) { + if (overflow_mask || force_overflow) { struct msm_isp_event_data error_event; int i; struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data; @@ -1840,7 +1844,8 @@ static int msm_isp_process_overflow_irq( pr_err("%s: wm %d assigned to stream handle %x\n", __func__, i, axi_data->free_wm[i]); } - + vfe_dev->recovery_irq0_mask = vfe_dev->irq0_mask; + vfe_dev->recovery_irq1_mask = vfe_dev->irq1_mask; vfe_dev->hw_info->vfe_ops.core_ops. set_halt_restart_mask(vfe_dev); /* mask off other vfe if dual vfe is used */ @@ -1855,6 +1860,8 @@ static int msm_isp_process_overflow_irq( atomic_set(&temp_vfe->error_info.overflow_state, OVERFLOW_DETECTED); + temp_vfe->recovery_irq0_mask = temp_vfe->irq0_mask; + temp_vfe->recovery_irq1_mask = temp_vfe->irq1_mask; temp_vfe->hw_info->vfe_ops.core_ops. set_halt_restart_mask(temp_vfe); } @@ -1889,6 +1896,77 @@ void msm_isp_reset_burst_count_and_frame_drop( msm_isp_reset_framedrop(vfe_dev, stream_info); } +void msm_isp_prepare_irq_debug_info(struct vfe_device *vfe_dev, + uint32_t irq_status0, uint32_t irq_status1) +{ + + unsigned long flags; + struct msm_vfe_irq_debug_info *irq_debug; + uint8_t current_index; + + spin_lock_irqsave(&vfe_dev->common_data->vfe_irq_dump. + common_dev_irq_dump_lock, flags); + /* Fill current VFE debug info */ + current_index = vfe_dev->common_data->vfe_irq_dump. + current_irq_index % MAX_VFE_IRQ_DEBUG_DUMP_SIZE; + irq_debug = &vfe_dev->common_data->vfe_irq_dump. + irq_debug[current_index]; + irq_debug->vfe_id = vfe_dev->pdev->id; + irq_debug->core_id = smp_processor_id(); + msm_isp_get_timestamp(&irq_debug->ts, vfe_dev); + irq_debug->irq_status0[vfe_dev->pdev->id] = irq_status0; + irq_debug->irq_status1[vfe_dev->pdev->id] = irq_status1; + irq_debug->ping_pong_status[vfe_dev->pdev->id] = + vfe_dev->hw_info->vfe_ops.axi_ops. + get_pingpong_status(vfe_dev); + if (vfe_dev->is_split && + (vfe_dev->common_data-> + dual_vfe_res->vfe_dev[!vfe_dev->pdev->id]) + && (vfe_dev->common_data->dual_vfe_res-> + vfe_dev[!vfe_dev->pdev->id]->vfe_open_cnt)) { + /* Fill other VFE debug Info */ + vfe_dev->hw_info->vfe_ops.irq_ops.read_irq_status( + vfe_dev->common_data->dual_vfe_res-> + vfe_dev[!vfe_dev->pdev->id], + &irq_debug->irq_status0[!vfe_dev->pdev->id], + &irq_debug->irq_status1[!vfe_dev->pdev->id]); + irq_debug->ping_pong_status[!vfe_dev->pdev->id] = + vfe_dev->hw_info->vfe_ops.axi_ops. + get_pingpong_status(vfe_dev->common_data-> + dual_vfe_res->vfe_dev[!vfe_dev->pdev->id]); + } + vfe_dev->common_data->vfe_irq_dump.current_irq_index++; + spin_unlock_irqrestore(&vfe_dev->common_data->vfe_irq_dump. + common_dev_irq_dump_lock, flags); +} + +void msm_isp_prepare_tasklet_debug_info(struct vfe_device *vfe_dev, + uint32_t irq_status0, uint32_t irq_status1, + struct msm_isp_timestamp ts) +{ + struct msm_vfe_irq_debug_info *irq_debug; + uint8_t current_index; + unsigned long flags; + + spin_lock_irqsave(&vfe_dev->common_data->vfe_irq_dump. + common_dev_tasklet_dump_lock, flags); + current_index = vfe_dev->common_data->vfe_irq_dump. + current_tasklet_index % MAX_VFE_IRQ_DEBUG_DUMP_SIZE; + irq_debug = &vfe_dev->common_data->vfe_irq_dump. + tasklet_debug[current_index]; + irq_debug->vfe_id = vfe_dev->pdev->id; + irq_debug->core_id = smp_processor_id(); + irq_debug->ts = ts; + irq_debug->irq_status0[vfe_dev->pdev->id] = irq_status0; + irq_debug->irq_status1[vfe_dev->pdev->id] = irq_status1; + irq_debug->ping_pong_status[vfe_dev->pdev->id] = + vfe_dev->hw_info->vfe_ops.axi_ops. + get_pingpong_status(vfe_dev); + vfe_dev->common_data->vfe_irq_dump.current_tasklet_index++; + spin_unlock_irqrestore(&vfe_dev->common_data->vfe_irq_dump. + common_dev_tasklet_dump_lock, flags); +} + static void msm_isp_enqueue_tasklet_cmd(struct vfe_device *vfe_dev, uint32_t irq_status0, uint32_t irq_status1) { @@ -1923,7 +2001,7 @@ irqreturn_t msm_isp_process_irq(int irq_num, void *data) uint32_t error_mask0, error_mask1; vfe_dev->hw_info->vfe_ops.irq_ops. - read_irq_status(vfe_dev, &irq_status0, &irq_status1); + read_and_clear_irq_status(vfe_dev, &irq_status0, &irq_status1); if ((irq_status0 == 0) && (irq_status1 == 0)) { ISP_DBG("%s:VFE%d irq_status0 & 1 are both 0\n", @@ -1932,7 +2010,7 @@ irqreturn_t msm_isp_process_irq(int irq_num, void *data) } if (msm_isp_process_overflow_irq(vfe_dev, - &irq_status0, &irq_status1)) { + &irq_status0, &irq_status1, 0)) { /* if overflow initiated no need to handle the interrupts */ pr_err("overflow processed\n"); return IRQ_HANDLED; @@ -1953,7 +2031,7 @@ irqreturn_t msm_isp_process_irq(int irq_num, void *data) ISP_DBG("%s: error_mask0/1 & error_count are set!\n", __func__); return IRQ_HANDLED; } - + msm_isp_prepare_irq_debug_info(vfe_dev, irq_status0, irq_status1); msm_isp_enqueue_tasklet_cmd(vfe_dev, irq_status0, irq_status1); return IRQ_HANDLED; @@ -1991,6 +2069,8 @@ void msm_isp_do_tasklet(unsigned long data) irq_status1 = queue_cmd->vfeInterruptStatus1; ts = queue_cmd->ts; spin_unlock_irqrestore(&vfe_dev->tasklet_lock, flags); + msm_isp_prepare_tasklet_debug_info(vfe_dev, + irq_status0, irq_status1, ts); ISP_DBG("%s: vfe_id %d status0: 0x%x status1: 0x%x\n", __func__, vfe_dev->pdev->id, irq_status0, irq_status1); irq_ops->process_reset_irq(vfe_dev, @@ -2242,3 +2322,53 @@ void msm_isp_flush_tasklet(struct vfe_device *vfe_dev) return; } +void msm_isp_irq_debug_dump(struct vfe_device *vfe_dev) +{ + + uint8_t i, dump_index; + unsigned long flags; + + spin_lock_irqsave(&vfe_dev->common_data->vfe_irq_dump. + common_dev_irq_dump_lock, flags); + dump_index = vfe_dev->common_data->vfe_irq_dump. + current_irq_index; + for (i = 0; i < MAX_VFE_IRQ_DEBUG_DUMP_SIZE; i++) { + trace_msm_cam_ping_pong_debug_dump( + vfe_dev->common_data->vfe_irq_dump. + irq_debug[dump_index % MAX_VFE_IRQ_DEBUG_DUMP_SIZE]); + dump_index++; + } + spin_unlock_irqrestore(&vfe_dev->common_data->vfe_irq_dump. + common_dev_irq_dump_lock, flags); +} + + +void msm_isp_tasklet_debug_dump(struct vfe_device *vfe_dev) +{ + + uint8_t i, dump_index; + unsigned long flags; + + spin_lock_irqsave(&vfe_dev->common_data->vfe_irq_dump. + common_dev_tasklet_dump_lock, flags); + dump_index = vfe_dev->common_data->vfe_irq_dump. + current_tasklet_index; + for (i = 0; i < MAX_VFE_IRQ_DEBUG_DUMP_SIZE; i++) { + trace_msm_cam_tasklet_debug_dump( + vfe_dev->common_data->vfe_irq_dump. + tasklet_debug[ + dump_index % MAX_VFE_IRQ_DEBUG_DUMP_SIZE]); + dump_index++; + } + spin_unlock_irqrestore(&vfe_dev->common_data->vfe_irq_dump. + common_dev_tasklet_dump_lock, flags); +} + +void msm_isp_dump_ping_pong_mismatch(struct vfe_device *vfe_dev) +{ + + trace_msm_cam_string(" ***** msm_isp_dump_irq_debug ****"); + msm_isp_irq_debug_dump(vfe_dev); + trace_msm_cam_string(" ***** msm_isp_dump_taskelet_debug ****"); + msm_isp_tasklet_debug_dump(vfe_dev); +} diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.h index f4280581a730..d075bd1721ac 100644 --- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.h +++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.h @@ -72,4 +72,9 @@ void msm_isp_print_fourcc_error(const char *origin, uint32_t fourcc_format); void msm_isp_flush_tasklet(struct vfe_device *vfe_dev); void msm_isp_get_timestamp(struct msm_isp_timestamp *time_stamp, struct vfe_device *vfe_dev); +void msm_isp_dump_ping_pong_mismatch(struct vfe_device *vfe_dev); +int msm_isp_process_overflow_irq( + struct vfe_device *vfe_dev, + uint32_t *irq_status0, uint32_t *irq_status1, + uint8_t force_overflow); #endif /* __MSM_ISP_UTIL_H__ */ diff --git a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c index b7724b4bf936..1cf2c54aa8b8 100644 --- a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c +++ b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.c @@ -1372,6 +1372,7 @@ static int cpp_open_node(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) mutex_unlock(&cpp_dev->mutex); return rc; } + cpp_dev->state = CPP_STATE_IDLE; CPP_DBG("Invoking msm_ion_client_create()\n"); @@ -2479,7 +2480,7 @@ static int msm_cpp_cfg_frame(struct cpp_device *cpp_dev, struct msm_buf_mngr_info buff_mgr_info, dup_buff_mgr_info; int32_t in_fd; int32_t num_output_bufs = 1; - int32_t stripe_base = 0; + uint32_t stripe_base = 0; uint32_t stripe_size; uint8_t tnr_enabled; enum msm_camera_buf_mngr_buf_type buf_type = @@ -2514,6 +2515,13 @@ static int msm_cpp_cfg_frame(struct cpp_device *cpp_dev, return -EINVAL; } + if (stripe_base == UINT_MAX || new_frame->num_strips > + (UINT_MAX - 1 - stripe_base) / stripe_size) { + pr_err("Invalid frame message,num_strips %d is large\n", + new_frame->num_strips); + return -EINVAL; + } + if ((stripe_base + new_frame->num_strips * stripe_size + 1) != new_frame->msg_len) { pr_err("Invalid frame message,len=%d,expected=%d\n", @@ -2913,15 +2921,14 @@ static int msm_cpp_validate_input(unsigned int cmd, void *arg, break; default: { if (ioctl_ptr == NULL) { - pr_err("Wrong ioctl_ptr %pK for cmd %u\n", - ioctl_ptr, cmd); + pr_err("Wrong ioctl_ptr for cmd %u\n", cmd); return -EINVAL; } *ioctl_ptr = arg; if ((*ioctl_ptr == NULL) || ((*ioctl_ptr)->ioctl_ptr == NULL)) { - pr_err("Wrong arg %pK for cmd %u\n", arg, cmd); + pr_err("Error invalid ioctl argument cmd %u", cmd); return -EINVAL; } break; @@ -4178,27 +4185,22 @@ static int msm_cpp_update_gdscr_status(struct cpp_device *cpp_dev, bool status) { int rc = 0; - int value = 0; - + uint32_t msm_cpp_reg_idx; if (!cpp_dev) { pr_err("%s: cpp device invalid\n", __func__); rc = -EINVAL; goto end; } - - if (cpp_dev->camss_cpp_base) { - value = msm_camera_io_r(cpp_dev->camss_cpp_base); - pr_debug("value from camss cpp %x, status %d\n", value, status); - if (status) { - value &= CPP_GDSCR_SW_COLLAPSE_ENABLE; - value |= CPP_GDSCR_HW_CONTROL_ENABLE; - } else { - value |= CPP_GDSCR_HW_CONTROL_DISABLE; - value &= CPP_GDSCR_SW_COLLAPSE_DISABLE; - } - pr_debug("value %x after camss cpp mask\n", value); - msm_camera_io_w(value, cpp_dev->camss_cpp_base); + msm_cpp_reg_idx = msm_cpp_get_regulator_index(cpp_dev, "vdd"); + if (msm_cpp_reg_idx < 0) { + pr_err(" Fail to regulator index\n"); + return -EINVAL; } + rc = msm_camera_regulator_set_mode(cpp_dev->cpp_vdd + + msm_cpp_reg_idx, 1, status); + if (rc < 0) + pr_err("update cpp gdscr status failed\n"); + end: return rc; } @@ -4307,14 +4309,6 @@ static int cpp_probe(struct platform_device *pdev) memset(&cpp_vbif, 0, sizeof(struct msm_cpp_vbif_data)); cpp_dev->vbif_data = &cpp_vbif; - cpp_dev->camss_cpp_base = - msm_camera_get_reg_base(pdev, "camss_cpp", true); - if (!cpp_dev->camss_cpp_base) { - rc = -ENOMEM; - pr_err("failed to get camss_cpp_base\n"); - goto camss_cpp_base_failed; - } - cpp_dev->base = msm_camera_get_reg_base(pdev, "cpp", true); if (!cpp_dev->base) { @@ -4486,7 +4480,7 @@ vbif_base_failed: cpp_base_failed: msm_camera_put_reg_base(pdev, cpp_dev->camss_cpp_base, "camss_cpp", true); -camss_cpp_base_failed: + kfree(cpp_dev); return rc; } diff --git a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.h b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.h index 470c0cf1131b..e69b9d633a1f 100644 --- a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.h +++ b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp.h @@ -289,6 +289,8 @@ struct cpp_device { int msm_cpp_set_micro_clk(struct cpp_device *cpp_dev); int msm_update_freq_tbl(struct cpp_device *cpp_dev); int msm_cpp_get_clock_index(struct cpp_device *cpp_dev, const char *clk_name); +int msm_cpp_get_regulator_index(struct cpp_device *cpp_dev, + const char *regulator_name); long msm_cpp_set_core_clk(struct cpp_device *cpp_dev, long rate, int idx); void msm_cpp_fetch_dt_params(struct cpp_device *cpp_dev); int msm_cpp_read_payload_params_from_dt(struct cpp_device *cpp_dev); diff --git a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp_soc.c b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp_soc.c index ddd32fc5c339..f016c348f144 100644 --- a/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp_soc.c +++ b/drivers/media/platform/msm/camera_v2/pproc/cpp/msm_cpp_soc.c @@ -71,6 +71,18 @@ int msm_cpp_get_clock_index(struct cpp_device *cpp_dev, const char *clk_name) return -EINVAL; } +int msm_cpp_get_regulator_index(struct cpp_device *cpp_dev, + const char *regulator_name) +{ + uint32_t i = 0; + + for (i = 0; i < cpp_dev->num_reg; i++) { + if (!strcmp(regulator_name, cpp_dev->cpp_vdd[i].name)) + return i; + } + return -EINVAL; +} + static int cpp_get_clk_freq_tbl_dt(struct cpp_device *cpp_dev) { uint32_t i, count, min_clk_rate; diff --git a/drivers/media/platform/msm/camera_v2/pproc/vpe/msm_vpe.c b/drivers/media/platform/msm/camera_v2/pproc/vpe/msm_vpe.c index f2f1dca81f18..d7fb2449582c 100644 --- a/drivers/media/platform/msm/camera_v2/pproc/vpe/msm_vpe.c +++ b/drivers/media/platform/msm/camera_v2/pproc/vpe/msm_vpe.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2015 The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2016 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1054,10 +1054,16 @@ static int vpe_reset(struct vpe_device *vpe_dev) return rc; } -static void vpe_update_scale_coef(struct vpe_device *vpe_dev, uint32_t *p) +static int vpe_update_scale_coef(struct vpe_device *vpe_dev, uint32_t *p) { uint32_t i, offset; offset = *p; + + if (offset > VPE_SCALE_COEFF_MAX_N-VPE_SCALE_COEFF_NUM) { + pr_err("%s: invalid offset %d passed in", __func__, offset); + return -EINVAL; + } + for (i = offset; i < (VPE_SCALE_COEFF_NUM + offset); i++) { VPE_DBG("Setting scale table %d\n", i); msm_camera_io_w(*(++p), @@ -1065,6 +1071,8 @@ static void vpe_update_scale_coef(struct vpe_device *vpe_dev, uint32_t *p) msm_camera_io_w(*(++p), vpe_dev->base + VPE_SCALE_COEFF_MSBn(i)); } + + return 0; } static void vpe_input_plane_config(struct vpe_device *vpe_dev, uint32_t *p) @@ -1102,13 +1110,16 @@ static void vpe_operation_config(struct vpe_device *vpe_dev, uint32_t *p) */ static void msm_vpe_transaction_setup(struct vpe_device *vpe_dev, void *data) { - int i; + int i, rc = 0; void *iter = data; vpe_mem_dump("vpe_transaction", data, VPE_TRANSACTION_SETUP_CONFIG_LEN); for (i = 0; i < VPE_NUM_SCALER_TABLES; ++i) { - vpe_update_scale_coef(vpe_dev, (uint32_t *)iter); + rc = vpe_update_scale_coef(vpe_dev, (uint32_t *)iter); + if (rc != 0) + return; + iter += VPE_SCALER_CONFIG_LEN; } vpe_input_plane_config(vpe_dev, (uint32_t *)iter); diff --git a/drivers/media/platform/msm/camera_v2/pproc/vpe/msm_vpe.h b/drivers/media/platform/msm/camera_v2/pproc/vpe/msm_vpe.h index f1869a2b9776..0c55ff70309e 100644 --- a/drivers/media/platform/msm/camera_v2/pproc/vpe/msm_vpe.h +++ b/drivers/media/platform/msm/camera_v2/pproc/vpe/msm_vpe.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2014, 2016 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -70,6 +70,7 @@ #define VPE_SCALE_COEFF_LSBn(n) (0x50400 + 8 * (n)) #define VPE_SCALE_COEFF_MSBn(n) (0x50404 + 8 * (n)) #define VPE_SCALE_COEFF_NUM 32 +#define VPE_SCALE_COEFF_MAX_N 127 /*********** end of register offset ********************/ diff --git a/drivers/media/platform/msm/camera_v2/sensor/flash/msm_flash.c b/drivers/media/platform/msm/camera_v2/sensor/flash/msm_flash.c index 800b2932854d..5376e1e4b6a4 100644 --- a/drivers/media/platform/msm/camera_v2/sensor/flash/msm_flash.c +++ b/drivers/media/platform/msm/camera_v2/sensor/flash/msm_flash.c @@ -502,6 +502,42 @@ static int32_t msm_flash_init( return 0; } +#ifdef CONFIG_COMPAT +static int32_t msm_flash_init_prepare( + struct msm_flash_ctrl_t *flash_ctrl, + struct msm_flash_cfg_data_t *flash_data) +{ + return msm_flash_init(flash_ctrl, flash_data); +} +#else +static int32_t msm_flash_init_prepare( + struct msm_flash_ctrl_t *flash_ctrl, + struct msm_flash_cfg_data_t *flash_data) +{ + struct msm_flash_cfg_data_t flash_data_k; + struct msm_flash_init_info_t flash_init_info; + int32_t i = 0; + + flash_data_k.cfg_type = flash_data->cfg_type; + for (i = 0; i < MAX_LED_TRIGGERS; i++) { + flash_data_k.flash_current[i] = + flash_data->flash_current[i]; + flash_data_k.flash_duration[i] = + flash_data->flash_duration[i]; + } + + flash_data_k.cfg.flash_init_info = &flash_init_info; + if (copy_from_user(&flash_init_info, + (void *)(flash_data->cfg.flash_init_info), + sizeof(struct msm_flash_init_info_t))) { + pr_err("%s copy_from_user failed %d\n", + __func__, __LINE__); + return -EFAULT; + } + return msm_flash_init(flash_ctrl, &flash_data_k); +} +#endif + static int32_t msm_flash_prepare( struct msm_flash_ctrl_t *flash_ctrl) { @@ -665,7 +701,7 @@ static int32_t msm_flash_config(struct msm_flash_ctrl_t *flash_ctrl, switch (flash_data->cfg_type) { case CFG_FLASH_INIT: - rc = msm_flash_init(flash_ctrl, flash_data); + rc = msm_flash_init_prepare(flash_ctrl, flash_data); break; case CFG_FLASH_RELEASE: if (flash_ctrl->flash_state != MSM_CAMERA_FLASH_RELEASE) { diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_base.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_base.c index 5e763f74170e..9048d54bed38 100644 --- a/drivers/media/platform/msm/sde/rotator/sde_rotator_base.c +++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_base.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012, 2015-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012, 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -76,7 +76,10 @@ u32 sde_apply_comp_ratio_factor(u32 quota, #define RES_1080p (1088*1920) #define RES_UHD (3840*2160) +#define RES_WQXGA (2560*1600) #define XIN_HALT_TIMEOUT_US 0x4000 +#define MDSS_MDP_HW_REV_320 0x30020000 /* sdm660 */ +#define MDSS_MDP_HW_REV_330 0x30030000 /* sdm630 */ static int sde_mdp_wait_for_xin_halt(u32 xin_id) { @@ -174,15 +177,32 @@ u32 sde_mdp_get_ot_limit(u32 width, u32 height, u32 pixfmt, u32 fps, u32 is_rd) SDEROT_DBG("w:%d h:%d fps:%d pixfmt:%8.8x yuv:%d res:%d rd:%d\n", width, height, fps, pixfmt, is_yuv, res, is_rd); - if (!is_yuv) - goto exit; + switch (mdata->mdss_version) { + case MDSS_MDP_HW_REV_320: + case MDSS_MDP_HW_REV_330: + if ((res <= RES_1080p) && (fps <= 30) && is_yuv) + ot_lim = 2; + else if ((res <= RES_1080p) && (fps <= 60) && is_yuv) + ot_lim = 4; + else if ((res <= RES_UHD) && (fps <= 30) && is_yuv) + ot_lim = 8; + else if ((res <= RES_WQXGA) && (fps <= 60) && is_yuv) + ot_lim = 4; + else if ((res <= RES_WQXGA) && (fps <= 60)) + ot_lim = 16; + break; + default: + if (is_yuv) { + if ((res <= RES_1080p) && (fps <= 30)) + ot_lim = 2; + else if ((res <= RES_1080p) && (fps <= 60)) + ot_lim = 4; + else if ((res <= RES_UHD) && (fps <= 30)) + ot_lim = 8; + } + break; + } - if ((res <= RES_1080p) && (fps <= 30)) - ot_lim = 2; - else if ((res <= RES_1080p) && (fps <= 60)) - ot_lim = 4; - else if ((res <= RES_UHD) && (fps <= 30)) - ot_lim = 8; exit: SDEROT_DBG("ot_lim=%d\n", ot_lim); diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c index 57b4560acdb2..2fc130137c25 100644 --- a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c +++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c @@ -530,7 +530,7 @@ static int sde_rotator_import_buffer(struct sde_layer_buffer *buffer, return ret; } -static int sde_rotator_secure_session_ctrl(struct sde_rot_entry *entry) +static int sde_rotator_secure_session_ctrl(bool enable) { struct sde_rot_data_type *mdata = sde_rot_get_mdata(); uint32_t sid_info; @@ -546,8 +546,7 @@ static int sde_rotator_secure_session_ctrl(struct sde_rot_entry *entry) desc.args[1] = SCM_BUFFER_PHYS(&sid_info); desc.args[2] = sizeof(uint32_t); - if (!mdata->sec_cam_en && - (entry->item.flags & SDE_ROTATION_SECURE_CAMERA)) { + if (!mdata->sec_cam_en && enable) { /* * Enable secure camera operation * Send SCM call to hypervisor to switch the @@ -573,11 +572,8 @@ static int sde_rotator_secure_session_ctrl(struct sde_rot_entry *entry) SDEROT_DBG("scm_call(1) ret=%d, resp=%x", ret, resp); - SDEROT_EVTLOG(1, entry->item.flags, - entry->src_buf.p[0].addr, - entry->dst_buf.p[0].addr); - } else if (mdata->sec_cam_en && !(entry->item.flags & - SDE_ROTATION_SECURE_CAMERA)) { + SDEROT_EVTLOG(1); + } else if (mdata->sec_cam_en && !enable) { /* * Disable secure camera operation * Send SCM call to hypervisor to switch the @@ -596,9 +592,7 @@ static int sde_rotator_secure_session_ctrl(struct sde_rot_entry *entry) /* force smmu to reattach */ sde_smmu_secure_ctrl(1); - SDEROT_EVTLOG(0, entry->item.flags, - entry->src_buf.p[0].addr, - entry->dst_buf.p[0].addr); + SDEROT_EVTLOG(0); } } else { return 0; @@ -618,6 +612,7 @@ static int sde_rotator_map_and_check_data(struct sde_rot_entry *entry) struct sde_mdp_format_params *fmt; struct sde_mdp_plane_sizes ps; bool rotation; + bool secure; input = &entry->item.input; output = &entry->item.output; @@ -628,7 +623,9 @@ static int sde_rotator_map_and_check_data(struct sde_rot_entry *entry) if (IS_ERR_VALUE(ret)) return ret; - ret = sde_rotator_secure_session_ctrl(entry); + secure = (entry->item.flags & SDE_ROTATION_SECURE_CAMERA) ? + true : false; + ret = sde_rotator_secure_session_ctrl(secure); if (ret) { SDEROT_ERR("failed secure session enabling/disabling %d\n", ret); @@ -2194,6 +2191,11 @@ static int sde_rotator_close(struct sde_rot_mgr *mgr, return -EINVAL; } + /* + * if secure camera session was enabled + * go back to non secure state + */ + sde_rotator_secure_session_ctrl(false); sde_rotator_release_rotator_perf_session(mgr, private); list_del_init(&private->list); diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c index 4008bae5ffee..347c0bef163f 100644 --- a/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c +++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_dev.c @@ -416,23 +416,10 @@ static int sde_rotator_start_streaming(struct vb2_queue *q, unsigned int count) { struct sde_rotator_ctx *ctx = vb2_get_drv_priv(q); struct sde_rotator_device *rot_dev = ctx->rot_dev; - struct sde_rotation_config config; - int ret; SDEDEV_DBG(rot_dev->dev, "start streaming s:%d t:%d\n", ctx->session_id, q->type); - sde_rot_mgr_lock(rot_dev->mgr); - sde_rotator_get_config_from_ctx(ctx, &config); - ret = sde_rotator_session_config(rot_dev->mgr, ctx->private, &config); - sde_rot_mgr_unlock(rot_dev->mgr); - if (ret < 0) { - SDEDEV_ERR(rot_dev->dev, - "fail config in stream on s:%d t:%d r:%d\n", - ctx->session_id, q->type, ret); - return -EINVAL; - } - if (!IS_ERR_OR_NULL(ctx->request) || atomic_read(&ctx->command_pending)) SDEDEV_ERR(rot_dev->dev, @@ -1501,11 +1488,39 @@ static int sde_rotator_streamon(struct file *file, void *fh, enum v4l2_buf_type buf_type) { struct sde_rotator_ctx *ctx = sde_rotator_ctx_from_fh(fh); + struct sde_rotator_device *rot_dev = ctx->rot_dev; + struct sde_rotation_config config; + struct vb2_queue *vq; int ret; SDEDEV_DBG(ctx->rot_dev->dev, "stream on s:%d t:%d\n", ctx->session_id, buf_type); + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, + buf_type == V4L2_BUF_TYPE_VIDEO_OUTPUT ? + V4L2_BUF_TYPE_VIDEO_CAPTURE : + V4L2_BUF_TYPE_VIDEO_OUTPUT); + + if (!vq) { + SDEDEV_ERR(ctx->rot_dev->dev, "fail to get vq on s:%d t:%d\n", + ctx->session_id, buf_type); + return -EINVAL; + } + + if (vb2_is_streaming(vq)) { + sde_rot_mgr_lock(rot_dev->mgr); + sde_rotator_get_config_from_ctx(ctx, &config); + ret = sde_rotator_session_config(rot_dev->mgr, ctx->private, + &config); + sde_rot_mgr_unlock(rot_dev->mgr); + if (ret < 0) { + SDEDEV_ERR(rot_dev->dev, + "fail config in stream on s:%d t:%d r:%d\n", + ctx->session_id, buf_type, ret); + return ret; + } + } + ret = v4l2_m2m_streamon(file, ctx->fh.m2m_ctx, buf_type); if (ret < 0) SDEDEV_ERR(ctx->rot_dev->dev, "fail stream on s:%d t:%d\n", diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c index 79013344b615..f2a9da737453 100644 --- a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c +++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c @@ -1078,21 +1078,33 @@ static u32 sde_hw_rotator_wait_done_regdma( spin_unlock_irqrestore(&rot->rotisr_lock, flags); } else { int cnt = 200; + bool pending; do { udelay(500); - status = SDE_ROTREG_READ(rot->mdss_base, ROTTOP_STATUS); + last_isr = SDE_ROTREG_READ(rot->mdss_base, + REGDMA_CSR_REGDMA_INT_STATUS); + pending = sde_hw_rotator_pending_swts(rot, ctx, &swts); cnt--; - } while ((cnt > 0) && (status & ROT_BUSY_BIT) - && ((status & ROT_ERROR_BIT) == 0)); + } while ((cnt > 0) && pending && + ((last_isr & REGDMA_INT_ERR_MASK) == 0)); - if (status & ROT_ERROR_BIT) - SDEROT_ERR("Rotator error\n"); - else if (status & ROT_BUSY_BIT) - SDEROT_ERR("Rotator busy\n"); + if (last_isr & REGDMA_INT_ERR_MASK) { + SDEROT_ERR("Rotator error, ts:0x%X/0x%X status:%x\n", + ctx->timestamp, swts, last_isr); + sde_hw_rotator_dump_status(rot); + status = ROT_ERROR_BIT; + } else if (pending) { + SDEROT_ERR("Rotator timeout, ts:0x%X/0x%X status:%x\n", + ctx->timestamp, swts, last_isr); + sde_hw_rotator_dump_status(rot); + status = ROT_ERROR_BIT; + } else { + status = 0; + } SDE_ROTREG_WRITE(rot->mdss_base, REGDMA_CSR_REGDMA_INT_CLEAR, - 0xFFFF); + last_isr); } sts = (status & ROT_ERROR_BIT) ? -ENODEV : 0; diff --git a/drivers/media/platform/msm/vidc/msm_smem.c b/drivers/media/platform/msm/vidc/msm_smem.c index 90047a608984..44c5c08f074c 100644 --- a/drivers/media/platform/msm/vidc/msm_smem.c +++ b/drivers/media/platform/msm/vidc/msm_smem.c @@ -513,10 +513,10 @@ static int ion_cache_operations(struct smem_client *client, rc = -EINVAL; goto cache_op_failed; } - rc = msm_ion_do_cache_op(client->clnt, + rc = msm_ion_do_cache_offset_op(client->clnt, (struct ion_handle *)mem->smem_priv, - 0, (unsigned long)mem->size, - msm_cache_ops); + 0, mem->offset, + (unsigned long)mem->size, msm_cache_ops); if (rc) { dprintk(VIDC_ERR, "cache operation failed %d\n", rc); diff --git a/drivers/media/platform/msm/vidc/msm_vidc.c b/drivers/media/platform/msm/vidc/msm_vidc.c index 8b1329db1742..babea6824c51 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc.c +++ b/drivers/media/platform/msm/vidc/msm_vidc.c @@ -333,7 +333,7 @@ static inline void populate_buf_info(struct buffer_info *binfo, binfo->timestamp.tv_sec = b->timestamp.tv_sec; binfo->timestamp.tv_usec = b->timestamp.tv_usec; dprintk(VIDC_DBG, "%s: fd[%d] = %d b->index = %d", - __func__, i, binfo->fd[0], b->index); + __func__, i, binfo->fd[i], b->index); } static inline void repopulate_v4l2_buffer(struct v4l2_buffer *b, @@ -658,8 +658,12 @@ int output_buffer_cache_invalidate(struct msm_vidc_inst *inst, for (i = 0; i < binfo->num_planes; i++) { if (binfo->handle[i]) { + struct msm_smem smem = *binfo->handle[i]; + + smem.offset = (unsigned int)(binfo->buff_off[i]); + smem.size = binfo->size[i]; rc = msm_comm_smem_cache_operations(inst, - binfo->handle[i], SMEM_CACHE_INVALIDATE); + &smem, SMEM_CACHE_INVALIDATE); if (rc) { dprintk(VIDC_ERR, "%s: Failed to clean caches: %d\n", diff --git a/drivers/media/platform/msm/vidc/venus_hfi.c b/drivers/media/platform/msm/vidc/venus_hfi.c index 9970c4152ef9..30d1bae48e7d 100644 --- a/drivers/media/platform/msm/vidc/venus_hfi.c +++ b/drivers/media/platform/msm/vidc/venus_hfi.c @@ -4418,6 +4418,7 @@ static void __unload_fw(struct venus_hfi_device *device) if (device->state != VENUS_STATE_DEINIT) flush_workqueue(device->venus_pm_workq); + __vote_buses(device, NULL, 0); subsystem_put(device->resources.fw.cookie); __interface_queues_release(device); __venus_power_off(device, false); diff --git a/drivers/mfd/wcd9xxx-irq.c b/drivers/mfd/wcd9xxx-irq.c index b6a476cd882d..2bc8bdff54f1 100644 --- a/drivers/mfd/wcd9xxx-irq.c +++ b/drivers/mfd/wcd9xxx-irq.c @@ -698,20 +698,27 @@ static int wcd9xxx_map_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq) static int wcd9xxx_irq_probe(struct platform_device *pdev) { - int irq; + int irq, dir_apps_irq = -EINVAL; struct wcd9xxx_irq_drv_data *data; struct device_node *node = pdev->dev.of_node; int ret = -EINVAL; irq = of_get_named_gpio(node, "qcom,gpio-connect", 0); - if (!gpio_is_valid(irq)) { + if (!gpio_is_valid(irq)) + dir_apps_irq = platform_get_irq_byname(pdev, "wcd_irq"); + + if (!gpio_is_valid(irq) && dir_apps_irq < 0) { dev_err(&pdev->dev, "TLMM connect gpio not found\n"); return -EPROBE_DEFER; } else { - irq = gpio_to_irq(irq); - if (irq < 0) { - dev_err(&pdev->dev, "Unable to configure irq\n"); - return irq; + if (dir_apps_irq > 0) { + irq = dir_apps_irq; + } else { + irq = gpio_to_irq(irq); + if (irq < 0) { + dev_err(&pdev->dev, "Unable to configure irq\n"); + return irq; + } } dev_dbg(&pdev->dev, "%s: virq = %d\n", __func__, irq); data = wcd9xxx_irq_add_domain(node, node->parent); diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c index 6b3d84a2c145..20949487f859 100644 --- a/drivers/misc/qseecom.c +++ b/drivers/misc/qseecom.c @@ -7660,11 +7660,11 @@ static void __qseecom_deinit_clk(enum qseecom_ce_hw_instance ce) } if (qclk->ce_core_clk != NULL) { clk_put(qclk->ce_core_clk); - qclk->ce_clk = NULL; + qclk->ce_core_clk = NULL; } if (qclk->ce_bus_clk != NULL) { clk_put(qclk->ce_bus_clk); - qclk->ce_clk = NULL; + qclk->ce_bus_clk = NULL; } if (qclk->ce_core_src_clk != NULL) { clk_put(qclk->ce_core_src_clk); diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c index 9ec0928658cd..5743588aa52b 100644 --- a/drivers/mmc/card/block.c +++ b/drivers/mmc/card/block.c @@ -136,6 +136,7 @@ struct mmc_blk_data { #define MMC_BLK_DISCARD BIT(2) #define MMC_BLK_SECDISCARD BIT(3) #define MMC_BLK_FLUSH BIT(4) +#define MMC_BLK_PARTSWITCH BIT(5) /* * Only set in main mmc_blk_data associated @@ -1416,8 +1417,13 @@ static inline int mmc_blk_part_switch(struct mmc_card *card, ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONFIG, part_config, card->ext_csd.part_time); - if (ret) + + if (ret) { + pr_err("%s: mmc_blk_part_switch failure, %d -> %d\n", + mmc_hostname(card->host), main_md->part_curr, + md->part_type); return ret; + } card->ext_csd.part_config = part_config; card->part_curr = md->part_type; @@ -3933,6 +3939,7 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req) struct mmc_host *host = card->host; unsigned long flags; unsigned int cmd_flags = req ? req->cmd_flags : 0; + int err; if (req && !mq->mqrq_prev->req) { /* claim host only for the first request */ @@ -3946,7 +3953,17 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req) } ret = mmc_blk_part_switch(card, md); + if (ret) { + err = mmc_blk_reset(md, card->host, MMC_BLK_PARTSWITCH); + if (!err) { + pr_err("%s: mmc_blk_reset(MMC_BLK_PARTSWITCH) succeeded.\n", + mmc_hostname(host)); + mmc_blk_reset_success(md, MMC_BLK_PARTSWITCH); + } else + pr_err("%s: mmc_blk_reset(MMC_BLK_PARTSWITCH) failed.\n", + mmc_hostname(host)); + if (req) { blk_end_request_all(req, -EIO); } diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index a444a3a80f52..152a3e3b4f47 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -1748,6 +1748,10 @@ EXPORT_SYMBOL(mmc_start_req); */ void mmc_wait_for_req(struct mmc_host *host, struct mmc_request *mrq) { +#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME + if (mmc_bus_needs_resume(host)) + mmc_resume_bus(host); +#endif __mmc_start_req(host, mrq); mmc_wait_for_req_done(host, mrq); } @@ -3105,9 +3109,6 @@ int mmc_resume_bus(struct mmc_host *host) } } - if (host->bus_ops->detect && !host->bus_dead) - host->bus_ops->detect(host); - mmc_bus_put(host); pr_debug("%s: Deferred resume completed\n", mmc_hostname(host)); return 0; diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 89288bd1eaa4..7aa01372412d 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -1192,10 +1192,6 @@ static int mmc_select_hs400(struct mmc_card *card) if (host->caps & MMC_CAP_WAIT_WHILE_BUSY) send_status = false; - /* Reduce frequency to HS frequency */ - max_dtr = card->ext_csd.hs_max_dtr; - mmc_set_clock(host, max_dtr); - /* Switch card to HS mode */ val = EXT_CSD_TIMING_HS; err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, @@ -1211,6 +1207,10 @@ static int mmc_select_hs400(struct mmc_card *card) /* Set host controller to HS timing */ mmc_set_timing(card->host, MMC_TIMING_MMC_HS); + /* Reduce frequency to HS frequency */ + max_dtr = card->ext_csd.hs_max_dtr; + mmc_set_clock(host, max_dtr); + if (!send_status) { err = mmc_switch_status(card); if (err) @@ -2514,12 +2514,6 @@ static int _mmc_suspend(struct mmc_host *host, bool is_suspend) goto out; } - if (mmc_card_doing_auto_bkops(host->card)) { - err = mmc_set_auto_bkops(host->card, false); - if (err) - goto out; - } - err = mmc_flush_cache(host->card); if (err) goto out; @@ -2599,9 +2593,6 @@ static int mmc_partial_init(struct mmc_host *host) pr_debug("%s: %s: reading and comparing ext_csd successful\n", mmc_hostname(host), __func__); - if (mmc_card_support_auto_bkops(host->card)) - (void)mmc_set_auto_bkops(host->card, true); - if (card->ext_csd.cmdq_support && (card->host->caps2 & MMC_CAP2_CMD_QUEUE)) { err = mmc_select_cmdq(card); diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index e7ebc3cb8eda..5fedab49cf34 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -1078,6 +1078,7 @@ static int mmc_sdio_resume(struct mmc_host *host) mmc_release_host(host); host->pm_flags &= ~MMC_PM_KEEP_POWER; + host->pm_flags &= ~MMC_PM_WAKE_SDIO_IRQ; return err; } diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index d51195e8a352..08822464d82f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2997,7 +2997,8 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) host->ops->adma_workaround(host, intmask); } if (host->data->error) { - if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT)) { + if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT + | SDHCI_INT_DATA_END_BIT)) { command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); if ((command != MMC_SEND_TUNING_BLOCK_HS200) && diff --git a/drivers/net/ethernet/msm/rndis_ipa.c b/drivers/net/ethernet/msm/rndis_ipa.c index 15cfb1d1dbeb..62e72ca01929 100644 --- a/drivers/net/ethernet/msm/rndis_ipa.c +++ b/drivers/net/ethernet/msm/rndis_ipa.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -135,29 +135,6 @@ enum rndis_ipa_operation { RNDIS_IPA_DEBUG("Driver state: %s\n",\ rndis_ipa_state_string(ctx->state)); -/** - * struct rndis_loopback_pipe - hold all information needed for - * pipe loopback logic - */ -struct rndis_loopback_pipe { - struct sps_pipe *ipa_sps; - struct ipa_sps_params ipa_sps_connect; - struct ipa_connect_params ipa_connect_params; - - struct sps_pipe *dma_sps; - struct sps_connect dma_connect; - - struct sps_alloc_dma_chan dst_alloc; - struct sps_dma_chan ipa_sps_channel; - enum sps_mode mode; - u32 ipa_peer_bam_hdl; - u32 peer_pipe_index; - u32 ipa_drv_ep_hdl; - u32 ipa_pipe_index; - enum ipa_client_type ipa_client; - ipa_notify_cb ipa_callback; - struct ipa_ep_cfg *ipa_ep_cfg; -}; /** * struct rndis_ipa_dev - main driver context parameters @@ -172,13 +149,9 @@ struct rndis_loopback_pipe { * @rx_dump_enable: dump all Rx packets * @icmp_filter: allow all ICMP packet to pass through the filters * @rm_enable: flag that enable/disable Resource manager request prior to Tx - * @loopback_enable: flag that enable/disable USB stub loopback * @deaggregation_enable: enable/disable IPA HW deaggregation logic * @during_xmit_error: flags that indicate that the driver is in a middle * of error handling in Tx path - * @usb_to_ipa_loopback_pipe: usb to ipa (Rx) pipe representation for loopback - * @ipa_to_usb_loopback_pipe: ipa to usb (Tx) pipe representation for loopback - * @bam_dma_hdl: handle representing bam-dma, used for loopback logic * @directory: holds all debug flags used by the driver to allow cleanup * for driver unload * @eth_ipv4_hdr_hdl: saved handle for ipv4 header-insertion table @@ -208,12 +181,8 @@ struct rndis_ipa_dev { bool rx_dump_enable; bool icmp_filter; bool rm_enable; - bool loopback_enable; bool deaggregation_enable; bool during_xmit_error; - struct rndis_loopback_pipe usb_to_ipa_loopback_pipe; - struct rndis_loopback_pipe ipa_to_usb_loopback_pipe; - u32 bam_dma_hdl; struct dentry *directory; uint32_t eth_ipv4_hdr_hdl; uint32_t eth_ipv6_hdr_hdl; @@ -277,31 +246,12 @@ static int resource_request(struct rndis_ipa_dev *rndis_ipa_ctx); static void resource_release(struct rndis_ipa_dev *rndis_ipa_ctx); static netdev_tx_t rndis_ipa_start_xmit(struct sk_buff *skb, struct net_device *net); -static int rndis_ipa_loopback_pipe_create( - struct rndis_ipa_dev *rndis_ipa_ctx, - struct rndis_loopback_pipe *loopback_pipe); -static void rndis_ipa_destroy_loopback_pipe( - struct rndis_loopback_pipe *loopback_pipe); -static int rndis_ipa_create_loopback(struct rndis_ipa_dev *rndis_ipa_ctx); -static void rndis_ipa_destroy_loopback(struct rndis_ipa_dev *rndis_ipa_ctx); -static int rndis_ipa_setup_loopback(bool enable, - struct rndis_ipa_dev *rndis_ipa_ctx); -static int rndis_ipa_debugfs_loopback_open(struct inode *inode, - struct file *file); static int rndis_ipa_debugfs_atomic_open(struct inode *inode, struct file *file); static int rndis_ipa_debugfs_aggr_open(struct inode *inode, struct file *file); static ssize_t rndis_ipa_debugfs_aggr_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos); -static ssize_t rndis_ipa_debugfs_loopback_write(struct file *file, - const char __user *buf, size_t count, loff_t *ppos); -static ssize_t rndis_ipa_debugfs_enable_write(struct file *file, - const char __user *buf, size_t count, loff_t *ppos); -static ssize_t rndis_ipa_debugfs_enable_read(struct file *file, - char __user *ubuf, size_t count, loff_t *ppos); -static ssize_t rndis_ipa_debugfs_loopback_read(struct file *file, - char __user *ubuf, size_t count, loff_t *ppos); static ssize_t rndis_ipa_debugfs_atomic_read(struct file *file, char __user *ubuf, size_t count, loff_t *ppos); static void rndis_ipa_dump_skb(struct sk_buff *skb); @@ -336,12 +286,6 @@ const struct file_operations rndis_ipa_debugfs_atomic_ops = { .read = rndis_ipa_debugfs_atomic_read, }; -const struct file_operations rndis_ipa_loopback_ops = { - .open = rndis_ipa_debugfs_loopback_open, - .read = rndis_ipa_debugfs_loopback_read, - .write = rndis_ipa_debugfs_loopback_write, -}; - const struct file_operations rndis_ipa_aggr_ops = { .open = rndis_ipa_debugfs_aggr_open, .write = rndis_ipa_debugfs_aggr_write, @@ -2195,14 +2139,6 @@ static int rndis_ipa_debugfs_init(struct rndis_ipa_dev *rndis_ipa_ctx) goto fail_file; } - file = debugfs_create_file("loopback_enable", flags_read_write, - rndis_ipa_ctx->directory, - rndis_ipa_ctx, &rndis_ipa_loopback_ops); - if (!file) { - RNDIS_IPA_ERROR("could not create outstanding file\n"); - goto fail_file; - } - file = debugfs_create_u8("state", flags_read_only, rndis_ipa_ctx->directory, (u8 *)&rndis_ipa_ctx->state); if (!file) { @@ -2358,59 +2294,6 @@ static ssize_t rndis_ipa_debugfs_aggr_write(struct file *file, return count; } -static int rndis_ipa_debugfs_loopback_open(struct inode *inode, - struct file *file) -{ - struct rndis_ipa_dev *rndis_ipa_ctx = inode->i_private; - file->private_data = rndis_ipa_ctx; - - return 0; -} - -static ssize_t rndis_ipa_debugfs_loopback_read(struct file *file, - char __user *ubuf, size_t count, loff_t *ppos) -{ - int cnt; - struct rndis_ipa_dev *rndis_ipa_ctx = file->private_data; - - file->private_data = &rndis_ipa_ctx->loopback_enable; - - cnt = rndis_ipa_debugfs_enable_read(file, - ubuf, count, ppos); - - return cnt; -} - -static ssize_t rndis_ipa_debugfs_loopback_write(struct file *file, - const char __user *buf, size_t count, loff_t *ppos) -{ - int retval; - int cnt; - struct rndis_ipa_dev *rndis_ipa_ctx = file->private_data; - bool old_state = rndis_ipa_ctx->loopback_enable; - - file->private_data = &rndis_ipa_ctx->loopback_enable; - - cnt = rndis_ipa_debugfs_enable_write(file, - buf, count, ppos); - - RNDIS_IPA_DEBUG("loopback_enable was set to:%d->%d\n", - old_state, rndis_ipa_ctx->loopback_enable); - - if (old_state == rndis_ipa_ctx->loopback_enable) { - RNDIS_IPA_ERROR("NOP - same state\n"); - return cnt; - } - - retval = rndis_ipa_setup_loopback( - rndis_ipa_ctx->loopback_enable, - rndis_ipa_ctx); - if (retval) - rndis_ipa_ctx->loopback_enable = old_state; - - return cnt; -} - static int rndis_ipa_debugfs_atomic_open(struct inode *inode, struct file *file) { struct rndis_ipa_dev *rndis_ipa_ctx = inode->i_private; @@ -2441,319 +2324,6 @@ static ssize_t rndis_ipa_debugfs_atomic_read(struct file *file, return simple_read_from_buffer(ubuf, count, ppos, atomic_str, nbytes); } -static ssize_t rndis_ipa_debugfs_enable_read(struct file *file, - char __user *ubuf, size_t count, loff_t *ppos) -{ - int nbytes; - int size = 0; - int ret; - loff_t pos; - u8 enable_str[sizeof(char)*3] = {0}; - bool *enable = file->private_data; - pos = *ppos; - nbytes = scnprintf(enable_str, sizeof(enable_str), "%d\n", *enable); - ret = simple_read_from_buffer(ubuf, count, ppos, enable_str, nbytes); - if (ret < 0) { - RNDIS_IPA_ERROR("simple_read_from_buffer problem\n"); - return ret; - } - size += ret; - count -= nbytes; - *ppos = pos + size; - return size; -} - -static ssize_t rndis_ipa_debugfs_enable_write(struct file *file, - const char __user *buf, size_t count, loff_t *ppos) -{ - unsigned long missing; - char input; - bool *enable = file->private_data; - if (count != sizeof(input) + 1) { - RNDIS_IPA_ERROR("wrong input length(%zd)\n", count); - return -EINVAL; - } - if (!buf) { - RNDIS_IPA_ERROR("Bad argument\n"); - return -EINVAL; - } - missing = copy_from_user(&input, buf, 1); - if (missing) - return -EFAULT; - RNDIS_IPA_DEBUG("input received %c\n", input); - *enable = input - '0'; - RNDIS_IPA_DEBUG("value was set to %d\n", *enable); - return count; -} - -/** - * Connects IPA->BAMDMA - * This shall simulate the path from IPA to USB - * Allowing the driver TX path - */ -static int rndis_ipa_loopback_pipe_create( - struct rndis_ipa_dev *rndis_ipa_ctx, - struct rndis_loopback_pipe *loopback_pipe) -{ - int retval; - - RNDIS_IPA_LOG_ENTRY(); - - /* SPS pipe has two side handshake - * This is the first handshake of IPA->BAMDMA, - * This is the IPA side - */ - loopback_pipe->ipa_connect_params.client = loopback_pipe->ipa_client; - loopback_pipe->ipa_connect_params.client_bam_hdl = - rndis_ipa_ctx->bam_dma_hdl; - loopback_pipe->ipa_connect_params.client_ep_idx = - loopback_pipe->peer_pipe_index; - loopback_pipe->ipa_connect_params.desc_fifo_sz = BAM_DMA_DESC_FIFO_SIZE; - loopback_pipe->ipa_connect_params.data_fifo_sz = BAM_DMA_DATA_FIFO_SIZE; - loopback_pipe->ipa_connect_params.notify = loopback_pipe->ipa_callback; - loopback_pipe->ipa_connect_params.priv = rndis_ipa_ctx; - loopback_pipe->ipa_connect_params.ipa_ep_cfg = - *(loopback_pipe->ipa_ep_cfg); - - /* loopback_pipe->ipa_sps_connect is out param */ - retval = ipa_connect(&loopback_pipe->ipa_connect_params, - &loopback_pipe->ipa_sps_connect, - &loopback_pipe->ipa_drv_ep_hdl); - if (retval) { - RNDIS_IPA_ERROR("ipa_connect() fail (%d)", retval); - return retval; - } - RNDIS_IPA_DEBUG("ipa_connect() succeeded, ipa_drv_ep_hdl=%d", - loopback_pipe->ipa_drv_ep_hdl); - - /* SPS pipe has two side handshake - * This is the second handshake of IPA->BAMDMA, - * This is the BAMDMA side - */ - loopback_pipe->dma_sps = sps_alloc_endpoint(); - if (!loopback_pipe->dma_sps) { - RNDIS_IPA_ERROR("sps_alloc_endpoint() failed "); - retval = -ENOMEM; - goto fail_sps_alloc; - } - - retval = sps_get_config(loopback_pipe->dma_sps, - &loopback_pipe->dma_connect); - if (retval) { - RNDIS_IPA_ERROR("sps_get_config() failed (%d)", retval); - goto fail_get_cfg; - } - - /* Start setting the non IPA ep for SPS driver*/ - loopback_pipe->dma_connect.mode = loopback_pipe->mode; - - /* SPS_MODE_DEST: DMA end point is the dest (consumer) IPA->DMA */ - if (loopback_pipe->mode == SPS_MODE_DEST) { - - loopback_pipe->dma_connect.source = - loopback_pipe->ipa_sps_connect.ipa_bam_hdl; - loopback_pipe->dma_connect.src_pipe_index = - loopback_pipe->ipa_sps_connect.ipa_ep_idx; - loopback_pipe->dma_connect.destination = - rndis_ipa_ctx->bam_dma_hdl; - loopback_pipe->dma_connect.dest_pipe_index = - loopback_pipe->peer_pipe_index; - - /* SPS_MODE_SRC: DMA end point is the source (producer) DMA->IPA */ - } else { - - loopback_pipe->dma_connect.source = - rndis_ipa_ctx->bam_dma_hdl; - loopback_pipe->dma_connect.src_pipe_index = - loopback_pipe->peer_pipe_index; - loopback_pipe->dma_connect.destination = - loopback_pipe->ipa_sps_connect.ipa_bam_hdl; - loopback_pipe->dma_connect.dest_pipe_index = - loopback_pipe->ipa_sps_connect.ipa_ep_idx; - - } - - loopback_pipe->dma_connect.desc = loopback_pipe->ipa_sps_connect.desc; - loopback_pipe->dma_connect.data = loopback_pipe->ipa_sps_connect.data; - loopback_pipe->dma_connect.event_thresh = 0x10; - /* BAM-to-BAM */ - loopback_pipe->dma_connect.options = SPS_O_AUTO_ENABLE; - - RNDIS_IPA_DEBUG("doing sps_connect() with - "); - RNDIS_IPA_DEBUG("src bam_hdl:0x%lx, src_pipe#:%d", - loopback_pipe->dma_connect.source, - loopback_pipe->dma_connect.src_pipe_index); - RNDIS_IPA_DEBUG("dst bam_hdl:0x%lx, dst_pipe#:%d", - loopback_pipe->dma_connect.destination, - loopback_pipe->dma_connect.dest_pipe_index); - - retval = sps_connect(loopback_pipe->dma_sps, - &loopback_pipe->dma_connect); - if (retval) { - RNDIS_IPA_ERROR("sps_connect() fail for BAMDMA side (%d)", - retval); - goto fail_sps_connect; - } - - RNDIS_IPA_LOG_EXIT(); - - return 0; - -fail_sps_connect: -fail_get_cfg: - sps_free_endpoint(loopback_pipe->dma_sps); -fail_sps_alloc: - ipa_disconnect(loopback_pipe->ipa_drv_ep_hdl); - return retval; -} - -static void rndis_ipa_destroy_loopback_pipe( - struct rndis_loopback_pipe *loopback_pipe) -{ - sps_disconnect(loopback_pipe->dma_sps); - sps_free_endpoint(loopback_pipe->dma_sps); -} - -/** - * rndis_ipa_create_loopback() - create a BAM-DMA loopback - * in order to replace the USB core - */ -static int rndis_ipa_create_loopback(struct rndis_ipa_dev *rndis_ipa_ctx) -{ - /* The BAM handle should be use as - * source/destination in the sps_connect() - */ - int retval; - - RNDIS_IPA_LOG_ENTRY(); - - - retval = sps_ctrl_bam_dma_clk(true); - if (retval) { - RNDIS_IPA_ERROR("fail on enabling BAM-DMA clocks"); - return -ENODEV; - } - - /* Get BAM handle instead of USB handle */ - rndis_ipa_ctx->bam_dma_hdl = sps_dma_get_bam_handle(); - if (!rndis_ipa_ctx->bam_dma_hdl) { - RNDIS_IPA_ERROR("sps_dma_get_bam_handle() failed"); - return -ENODEV; - } - RNDIS_IPA_DEBUG("sps_dma_get_bam_handle() succeeded (0x%x)", - rndis_ipa_ctx->bam_dma_hdl); - - /* IPA<-BAMDMA, NetDev Rx path (BAMDMA is the USB stub) */ - rndis_ipa_ctx->usb_to_ipa_loopback_pipe.ipa_client = - IPA_CLIENT_USB_PROD; - rndis_ipa_ctx->usb_to_ipa_loopback_pipe.peer_pipe_index = - FROM_USB_TO_IPA_BAMDMA; - /*DMA EP mode*/ - rndis_ipa_ctx->usb_to_ipa_loopback_pipe.mode = SPS_MODE_SRC; - rndis_ipa_ctx->usb_to_ipa_loopback_pipe.ipa_ep_cfg = - &usb_to_ipa_ep_cfg_deaggr_en; - rndis_ipa_ctx->usb_to_ipa_loopback_pipe.ipa_callback = - rndis_ipa_packet_receive_notify; - RNDIS_IPA_DEBUG("setting up IPA<-BAMDAM pipe (RNDIS_IPA RX path)"); - retval = rndis_ipa_loopback_pipe_create(rndis_ipa_ctx, - &rndis_ipa_ctx->usb_to_ipa_loopback_pipe); - if (retval) { - RNDIS_IPA_ERROR("fail to close IPA->BAMDAM pipe"); - goto fail_to_usb; - } - RNDIS_IPA_DEBUG("IPA->BAMDAM pipe successfully connected (TX path)"); - - /* IPA->BAMDMA, NetDev Tx path (BAMDMA is the USB stub)*/ - rndis_ipa_ctx->ipa_to_usb_loopback_pipe.ipa_client = - IPA_CLIENT_USB_CONS; - /*DMA EP mode*/ - rndis_ipa_ctx->ipa_to_usb_loopback_pipe.mode = SPS_MODE_DEST; - rndis_ipa_ctx->ipa_to_usb_loopback_pipe.ipa_ep_cfg = &ipa_to_usb_ep_cfg; - rndis_ipa_ctx->ipa_to_usb_loopback_pipe.peer_pipe_index = - FROM_IPA_TO_USB_BAMDMA; - rndis_ipa_ctx->ipa_to_usb_loopback_pipe.ipa_callback = - rndis_ipa_tx_complete_notify; - RNDIS_IPA_DEBUG("setting up IPA->BAMDAM pipe (RNDIS_IPA TX path)"); - retval = rndis_ipa_loopback_pipe_create(rndis_ipa_ctx, - &rndis_ipa_ctx->ipa_to_usb_loopback_pipe); - if (retval) { - RNDIS_IPA_ERROR("fail to close IPA<-BAMDAM pipe"); - goto fail_from_usb; - } - RNDIS_IPA_DEBUG("IPA<-BAMDAM pipe successfully connected(RX path)"); - - RNDIS_IPA_LOG_EXIT(); - - return 0; - -fail_from_usb: - rndis_ipa_destroy_loopback_pipe( - &rndis_ipa_ctx->usb_to_ipa_loopback_pipe); -fail_to_usb: - - return retval; -} - -static void rndis_ipa_destroy_loopback(struct rndis_ipa_dev *rndis_ipa_ctx) -{ - rndis_ipa_destroy_loopback_pipe( - &rndis_ipa_ctx->ipa_to_usb_loopback_pipe); - rndis_ipa_destroy_loopback_pipe( - &rndis_ipa_ctx->usb_to_ipa_loopback_pipe); - sps_dma_free_bam_handle(rndis_ipa_ctx->bam_dma_hdl); - if (sps_ctrl_bam_dma_clk(false)) - RNDIS_IPA_ERROR("fail to disable BAM-DMA clocks"); -} - -/** - * rndis_ipa_setup_loopback() - create/destroy a loopback on IPA HW - * (as USB pipes loopback) and notify RNDIS_IPA netdev for pipe connected - * @enable: flag that determines if the loopback should be created or destroyed - * @rndis_ipa_ctx: driver main context - * - * This function is the main loopback logic. - * It shall create/destory the loopback by using BAM-DMA and notify - * the netdev accordingly. - */ -static int rndis_ipa_setup_loopback(bool enable, - struct rndis_ipa_dev *rndis_ipa_ctx) -{ - int retval; - - if (!enable) { - rndis_ipa_destroy_loopback(rndis_ipa_ctx); - RNDIS_IPA_DEBUG("loopback destroy done"); - retval = rndis_ipa_pipe_disconnect_notify(rndis_ipa_ctx); - if (retval) { - RNDIS_IPA_ERROR("connect notify fail"); - return -ENODEV; - } - return 0; - } - - RNDIS_IPA_DEBUG("creating loopback (instead of USB core)"); - retval = rndis_ipa_create_loopback(rndis_ipa_ctx); - RNDIS_IPA_DEBUG("creating loopback- %s", (retval ? "FAIL" : "OK")); - if (retval) { - RNDIS_IPA_ERROR("Fail to connect loopback"); - return -ENODEV; - } - retval = rndis_ipa_pipe_connect_notify( - rndis_ipa_ctx->usb_to_ipa_loopback_pipe.ipa_drv_ep_hdl, - rndis_ipa_ctx->ipa_to_usb_loopback_pipe.ipa_drv_ep_hdl, - BAM_DMA_DATA_FIFO_SIZE, - 15, - BAM_DMA_DATA_FIFO_SIZE - rndis_ipa_ctx->net->mtu, - rndis_ipa_ctx); - if (retval) { - RNDIS_IPA_ERROR("connect notify fail"); - return -ENODEV; - } - - return 0; - -} - static int rndis_ipa_init_module(void) { pr_info("RNDIS_IPA module is loaded."); diff --git a/drivers/net/ppp/ppp_generic.c b/drivers/net/ppp/ppp_generic.c index e5bb870b5461..fa76ca128e1b 100644 --- a/drivers/net/ppp/ppp_generic.c +++ b/drivers/net/ppp/ppp_generic.c @@ -2390,6 +2390,8 @@ ppp_unregister_channel(struct ppp_channel *chan) spin_lock_bh(&pn->all_channels_lock); list_del(&pch->list); spin_unlock_bh(&pn->all_channels_lock); + put_net(pch->chan_net); + pch->chan_net = NULL; pch->file.dead = 1; wake_up_interruptible(&pch->file.rwait); diff --git a/drivers/net/wireless/ath/wil6210/cfg80211.c b/drivers/net/wireless/ath/wil6210/cfg80211.c index 17b419d408cd..8983b5f125c3 100644 --- a/drivers/net/wireless/ath/wil6210/cfg80211.c +++ b/drivers/net/wireless/ath/wil6210/cfg80211.c @@ -439,14 +439,6 @@ static int wil_cfg80211_scan(struct wiphy *wiphy, wil_dbg_misc(wil, "%s(), wdev=0x%p iftype=%d\n", __func__, wdev, wdev->iftype); - mutex_lock(&wil->p2p_wdev_mutex); - if (wil->scan_request) { - wil_err(wil, "Already scanning\n"); - mutex_unlock(&wil->p2p_wdev_mutex); - return -EAGAIN; - } - mutex_unlock(&wil->p2p_wdev_mutex); - /* check we are client side */ switch (wdev->iftype) { case NL80211_IFTYPE_STATION: @@ -463,12 +455,24 @@ static int wil_cfg80211_scan(struct wiphy *wiphy, return -EBUSY; } + mutex_lock(&wil->mutex); + + mutex_lock(&wil->p2p_wdev_mutex); + if (wil->scan_request || wil->p2p.discovery_started) { + wil_err(wil, "Already scanning\n"); + mutex_unlock(&wil->p2p_wdev_mutex); + rc = -EAGAIN; + goto out; + } + mutex_unlock(&wil->p2p_wdev_mutex); + /* social scan on P2P_DEVICE is handled as p2p search */ if (wdev->iftype == NL80211_IFTYPE_P2P_DEVICE && wil_p2p_is_social_scan(request)) { if (!wil->p2p.p2p_dev_started) { wil_err(wil, "P2P search requested on stopped P2P device\n"); - return -EIO; + rc = -EIO; + goto out; } wil->scan_request = request; wil->radio_wdev = wdev; @@ -477,7 +481,7 @@ static int wil_cfg80211_scan(struct wiphy *wiphy, wil->radio_wdev = wil_to_wdev(wil); wil->scan_request = NULL; } - return rc; + goto out; } (void)wil_p2p_stop_discovery(wil); @@ -500,7 +504,7 @@ static int wil_cfg80211_scan(struct wiphy *wiphy, if (rc) { wil_err(wil, "set SSID for scan request failed: %d\n", rc); - return rc; + goto out; } wil->scan_request = request; @@ -533,7 +537,7 @@ static int wil_cfg80211_scan(struct wiphy *wiphy, rc = wmi_set_ie(wil, WMI_FRAME_PROBE_REQ, request->ie_len, request->ie); if (rc) - goto out; + goto out_restore; if (wil->discovery_mode && cmd.cmd.scan_type == WMI_ACTIVE_SCAN) { cmd.cmd.discovery_mode = 1; @@ -544,16 +548,45 @@ static int wil_cfg80211_scan(struct wiphy *wiphy, rc = wmi_send(wil, WMI_START_SCAN_CMDID, &cmd, sizeof(cmd.cmd) + cmd.cmd.num_channels * sizeof(cmd.cmd.channel_list[0])); -out: +out_restore: if (rc) { del_timer_sync(&wil->scan_timer); wil->radio_wdev = wil_to_wdev(wil); wil->scan_request = NULL; } - +out: + mutex_unlock(&wil->mutex); return rc; } +static void wil_cfg80211_abort_scan(struct wiphy *wiphy, + struct wireless_dev *wdev) +{ + struct wil6210_priv *wil = wiphy_to_wil(wiphy); + + wil_dbg_misc(wil, "wdev=0x%p iftype=%d\n", wdev, wdev->iftype); + + mutex_lock(&wil->mutex); + mutex_lock(&wil->p2p_wdev_mutex); + + if (!wil->scan_request) + goto out; + + if (wdev != wil->scan_request->wdev) { + wil_dbg_misc(wil, "abort scan was called on the wrong iface\n"); + goto out; + } + + if (wil->radio_wdev == wil->p2p_wdev) + wil_p2p_stop_radio_operations(wil); + else + wil_abort_scan(wil, true); + +out: + mutex_unlock(&wil->p2p_wdev_mutex); + mutex_unlock(&wil->mutex); +} + static void wil_print_crypto(struct wil6210_priv *wil, struct cfg80211_crypto_settings *c) { @@ -759,6 +792,26 @@ static int wil_cfg80211_disconnect(struct wiphy *wiphy, return rc; } +static int wil_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed) +{ + struct wil6210_priv *wil = wiphy_to_wil(wiphy); + int rc; + + /* these parameters are explicitly not supported */ + if (changed & (WIPHY_PARAM_RETRY_LONG | + WIPHY_PARAM_FRAG_THRESHOLD | + WIPHY_PARAM_RTS_THRESHOLD)) + return -ENOTSUPP; + + if (changed & WIPHY_PARAM_RETRY_SHORT) { + rc = wmi_set_mgmt_retry(wil, wiphy->retry_short); + if (rc) + return rc; + } + + return 0; +} + int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, struct cfg80211_mgmt_tx_params *params, u64 *cookie) @@ -1025,16 +1078,8 @@ static int wil_remain_on_channel(struct wiphy *wiphy, wil_dbg_misc(wil, "%s() center_freq=%d, duration=%d iftype=%d\n", __func__, chan->center_freq, duration, wdev->iftype); - rc = wil_p2p_listen(wil, duration, chan, cookie); - if (rc) - return rc; - - wil->radio_wdev = wdev; - - cfg80211_ready_on_channel(wdev, *cookie, chan, duration, - GFP_KERNEL); - - return 0; + rc = wil_p2p_listen(wil, wdev, duration, chan, cookie); + return rc; } static int wil_cancel_remain_on_channel(struct wiphy *wiphy, @@ -1504,17 +1549,49 @@ static void wil_cfg80211_stop_p2p_device(struct wiphy *wiphy, wil_dbg_misc(wil, "%s: entered\n", __func__); mutex_lock(&wil->mutex); + mutex_lock(&wil->p2p_wdev_mutex); wil_p2p_stop_radio_operations(wil); p2p->p2p_dev_started = 0; + mutex_unlock(&wil->p2p_wdev_mutex); mutex_unlock(&wil->mutex); } +static int wil_cfg80211_set_power_mgmt(struct wiphy *wiphy, + struct net_device *dev, + bool enabled, int timeout) +{ + struct wil6210_priv *wil = wiphy_to_wil(wiphy); + enum wmi_ps_profile_type ps_profile; + int rc; + + if (!test_bit(WMI_FW_CAPABILITY_PS_CONFIG, wil->fw_capabilities)) { + wil_err(wil, "set_power_mgmt not supported\n"); + return -EOPNOTSUPP; + } + + wil_dbg_misc(wil, "enabled=%d, timeout=%d\n", + enabled, timeout); + + if (enabled) + ps_profile = WMI_PS_PROFILE_TYPE_DEFAULT; + else + ps_profile = WMI_PS_PROFILE_TYPE_PS_DISABLED; + + rc = wmi_ps_dev_profile_cfg(wil, ps_profile); + if (rc) + wil_err(wil, "wmi_ps_dev_profile_cfg failed (%d)\n", rc); + + return rc; +} + static struct cfg80211_ops wil_cfg80211_ops = { .add_virtual_intf = wil_cfg80211_add_iface, .del_virtual_intf = wil_cfg80211_del_iface, .scan = wil_cfg80211_scan, + .abort_scan = wil_cfg80211_abort_scan, .connect = wil_cfg80211_connect, .disconnect = wil_cfg80211_disconnect, + .set_wiphy_params = wil_cfg80211_set_wiphy_params, .change_virtual_intf = wil_cfg80211_change_iface, .get_station = wil_cfg80211_get_station, .dump_station = wil_cfg80211_dump_station, @@ -1535,6 +1612,7 @@ static struct cfg80211_ops wil_cfg80211_ops = { /* P2P device */ .start_p2p_device = wil_cfg80211_start_p2p_device, .stop_p2p_device = wil_cfg80211_stop_p2p_device, + .set_power_mgmt = wil_cfg80211_set_power_mgmt, }; static void wil_wiphy_init(struct wiphy *wiphy) @@ -1551,7 +1629,8 @@ static void wil_wiphy_init(struct wiphy *wiphy) BIT(NL80211_IFTYPE_MONITOR); wiphy->flags |= WIPHY_FLAG_HAVE_AP_SME | WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL | - WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD; + WIPHY_FLAG_AP_PROBE_RESP_OFFLOAD | + WIPHY_FLAG_PS_ON_BY_DEFAULT; dev_dbg(wiphy_dev(wiphy), "%s : flags = 0x%08x\n", __func__, wiphy->flags); wiphy->probe_resp_offload = diff --git a/drivers/net/wireless/ath/wil6210/main.c b/drivers/net/wireless/ath/wil6210/main.c index 5285ebc8b9af..fa061daa56d7 100644 --- a/drivers/net/wireless/ath/wil6210/main.c +++ b/drivers/net/wireless/ath/wil6210/main.c @@ -24,6 +24,7 @@ #include "boot_loader.h" #define WAIT_FOR_HALP_VOTE_MS 100 +#define WAIT_FOR_SCAN_ABORT_MS 1000 bool debug_fw; /* = false; */ module_param(debug_fw, bool, S_IRUGO); @@ -213,7 +214,7 @@ __acquires(&sta->tid_rx_lock) __releases(&sta->tid_rx_lock) memset(&sta->stats, 0, sizeof(sta->stats)); } -static bool wil_ap_is_connected(struct wil6210_priv *wil) +static bool wil_is_connected(struct wil6210_priv *wil) { int i; @@ -267,7 +268,7 @@ static void _wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid, case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_P2P_CLIENT: wil_bcast_fini(wil); - netif_tx_stop_all_queues(ndev); + wil_update_net_queues_bh(wil, NULL, true); netif_carrier_off(ndev); if (test_bit(wil_status_fwconnected, wil->status)) { @@ -283,8 +284,12 @@ static void _wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid, break; case NL80211_IFTYPE_AP: case NL80211_IFTYPE_P2P_GO: - if (!wil_ap_is_connected(wil)) + if (!wil_is_connected(wil)) { + wil_update_net_queues_bh(wil, NULL, true); clear_bit(wil_status_fwconnected, wil->status); + } else { + wil_update_net_queues_bh(wil, NULL, false); + } break; default: break; @@ -384,18 +389,19 @@ static void wil_fw_error_worker(struct work_struct *work) wil->last_fw_recovery = jiffies; + wil_info(wil, "fw error recovery requested (try %d)...\n", + wil->recovery_count); + if (!no_fw_recovery) + wil->recovery_state = fw_recovery_running; + if (wil_wait_for_recovery(wil) != 0) + return; + mutex_lock(&wil->mutex); switch (wdev->iftype) { case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_P2P_CLIENT: case NL80211_IFTYPE_MONITOR: - wil_info(wil, "fw error recovery requested (try %d)...\n", - wil->recovery_count); - if (!no_fw_recovery) - wil->recovery_state = fw_recovery_running; - if (0 != wil_wait_for_recovery(wil)) - break; - + /* silent recovery, upper layers will see disconnect */ __wil_down(wil); __wil_up(wil); break; @@ -512,10 +518,13 @@ int wil_priv_init(struct wil6210_priv *wil) INIT_WORK(&wil->wmi_event_worker, wmi_event_worker); INIT_WORK(&wil->fw_error_worker, wil_fw_error_worker); INIT_WORK(&wil->probe_client_worker, wil_probe_client_worker); + INIT_WORK(&wil->p2p.delayed_listen_work, wil_p2p_delayed_listen_work); INIT_LIST_HEAD(&wil->pending_wmi_ev); INIT_LIST_HEAD(&wil->probe_client_pending); spin_lock_init(&wil->wmi_ev_lock); + spin_lock_init(&wil->net_queue_lock); + wil->net_queue_stopped = 1; init_waitqueue_head(&wil->wq); wil_ftm_init(wil); @@ -574,6 +583,7 @@ void wil_priv_deinit(struct wil6210_priv *wil) cancel_work_sync(&wil->disconnect_worker); cancel_work_sync(&wil->fw_error_worker); cancel_work_sync(&wil->p2p.discovery_expired_work); + cancel_work_sync(&wil->p2p.delayed_listen_work); mutex_lock(&wil->mutex); wil6210_disconnect(wil, NULL, WLAN_REASON_DEAUTH_LEAVING, false); mutex_unlock(&wil->mutex); @@ -691,6 +701,19 @@ static int wil_target_reset(struct wil6210_priv *wil) return 0; } +static void wil_collect_fw_info(struct wil6210_priv *wil) +{ + struct wiphy *wiphy = wil_to_wiphy(wil); + u8 retry_short; + int rc; + + rc = wmi_get_mgmt_retry(wil, &retry_short); + if (!rc) { + wiphy->retry_short = retry_short; + wil_dbg_misc(wil, "FW retry_short: %d\n", retry_short); + } +} + void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r) { le32_to_cpus(&r->base); @@ -807,6 +830,31 @@ static int wil_wait_for_fw_ready(struct wil6210_priv *wil) return 0; } +void wil_abort_scan(struct wil6210_priv *wil, bool sync) +{ + int rc; + + lockdep_assert_held(&wil->p2p_wdev_mutex); + + if (!wil->scan_request) + return; + + wil_dbg_misc(wil, "Abort scan_request 0x%p\n", wil->scan_request); + del_timer_sync(&wil->scan_timer); + mutex_unlock(&wil->p2p_wdev_mutex); + rc = wmi_abort_scan(wil); + if (!rc && sync) + wait_event_interruptible_timeout(wil->wq, !wil->scan_request, + msecs_to_jiffies( + WAIT_FOR_SCAN_ABORT_MS)); + + mutex_lock(&wil->p2p_wdev_mutex); + if (wil->scan_request) { + cfg80211_scan_done(wil->scan_request, true); + wil->scan_request = NULL; + } +} + /* * We reset all the structures, and we reset the UMAC. * After calling this routine, you're expected to reload @@ -859,13 +907,7 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw) mutex_unlock(&wil->wmi_mutex); mutex_lock(&wil->p2p_wdev_mutex); - if (wil->scan_request) { - wil_dbg_misc(wil, "Abort scan_request 0x%p\n", - wil->scan_request); - del_timer_sync(&wil->scan_timer); - cfg80211_scan_done(wil->scan_request, true); - wil->scan_request = NULL; - } + wil_abort_scan(wil, false); mutex_unlock(&wil->p2p_wdev_mutex); wil_mask_irq(wil); @@ -876,7 +918,10 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw) flush_workqueue(wil->wmi_wq); wil_bl_crash_info(wil, false); + wil_disable_irq(wil); rc = wil_target_reset(wil); + wil6210_clear_irq(wil); + wil_enable_irq(wil); wil_rx_fini(wil); if (rc) { wil_bl_crash_info(wil, true); @@ -942,6 +987,8 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw) return rc; } + wil_collect_fw_info(wil); + if (wil->platform_ops.notify) { rc = wil->platform_ops.notify(wil->platform_handle, WIL_PLATFORM_EVT_FW_RDY); @@ -1058,17 +1105,11 @@ int __wil_down(struct wil6210_priv *wil) } wil_enable_irq(wil); - wil_p2p_stop_radio_operations(wil); wil_ftm_stop_operations(wil); mutex_lock(&wil->p2p_wdev_mutex); - if (wil->scan_request) { - wil_dbg_misc(wil, "Abort scan_request 0x%p\n", - wil->scan_request); - del_timer_sync(&wil->scan_timer); - cfg80211_scan_done(wil->scan_request, true); - wil->scan_request = NULL; - } + wil_p2p_stop_radio_operations(wil); + wil_abort_scan(wil, false); mutex_unlock(&wil->p2p_wdev_mutex); wil_reset(wil, false); diff --git a/drivers/net/wireless/ath/wil6210/netdev.c b/drivers/net/wireless/ath/wil6210/netdev.c index f4fca9d4eedf..05ecf3a00f57 100644 --- a/drivers/net/wireless/ath/wil6210/netdev.c +++ b/drivers/net/wireless/ath/wil6210/netdev.c @@ -235,7 +235,7 @@ int wil_if_add(struct wil6210_priv *wil) netif_napi_add(ndev, &wil->napi_tx, wil6210_netdev_poll_tx, WIL6210_NAPI_BUDGET); - netif_tx_stop_all_queues(ndev); + wil_update_net_queues_bh(wil, NULL, true); rc = register_netdev(ndev); if (rc < 0) { diff --git a/drivers/net/wireless/ath/wil6210/p2p.c b/drivers/net/wireless/ath/wil6210/p2p.c index 42148da111f1..24184cfc5da4 100644 --- a/drivers/net/wireless/ath/wil6210/p2p.c +++ b/drivers/net/wireless/ath/wil6210/p2p.c @@ -22,6 +22,43 @@ #define P2P_SEARCH_DURATION_MS 500 #define P2P_DEFAULT_BI 100 +static int wil_p2p_start_listen(struct wil6210_priv *wil) +{ + struct wil_p2p_info *p2p = &wil->p2p; + u8 channel = p2p->listen_chan.hw_value; + int rc; + + lockdep_assert_held(&wil->mutex); + + rc = wmi_p2p_cfg(wil, channel, P2P_DEFAULT_BI); + if (rc) { + wil_err(wil, "wmi_p2p_cfg failed\n"); + goto out; + } + + rc = wmi_set_ssid(wil, strlen(P2P_WILDCARD_SSID), P2P_WILDCARD_SSID); + if (rc) { + wil_err(wil, "wmi_set_ssid failed\n"); + goto out_stop; + } + + rc = wmi_start_listen(wil); + if (rc) { + wil_err(wil, "wmi_start_listen failed\n"); + goto out_stop; + } + + INIT_WORK(&p2p->discovery_expired_work, wil_p2p_listen_expired); + mod_timer(&p2p->discovery_timer, + jiffies + msecs_to_jiffies(p2p->listen_duration)); +out_stop: + if (rc) + wmi_stop_discovery(wil); + +out: + return rc; +} + bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request) { return (request->n_channels == 1) && @@ -46,7 +83,7 @@ int wil_p2p_search(struct wil6210_priv *wil, wil_dbg_misc(wil, "%s: channel %d\n", __func__, P2P_DMG_SOCIAL_CHANNEL); - mutex_lock(&wil->mutex); + lockdep_assert_held(&wil->mutex); if (p2p->discovery_started) { wil_err(wil, "%s: search failed. discovery already ongoing\n", @@ -103,22 +140,19 @@ out_stop: wmi_stop_discovery(wil); out: - mutex_unlock(&wil->mutex); return rc; } -int wil_p2p_listen(struct wil6210_priv *wil, unsigned int duration, - struct ieee80211_channel *chan, u64 *cookie) +int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev, + unsigned int duration, struct ieee80211_channel *chan, + u64 *cookie) { struct wil_p2p_info *p2p = &wil->p2p; - u8 channel = P2P_DMG_SOCIAL_CHANNEL; int rc; if (!chan) return -EINVAL; - channel = chan->hw_value; - wil_dbg_misc(wil, "%s: duration %d\n", __func__, duration); mutex_lock(&wil->mutex); @@ -129,35 +163,30 @@ int wil_p2p_listen(struct wil6210_priv *wil, unsigned int duration, goto out; } - rc = wmi_p2p_cfg(wil, channel, P2P_DEFAULT_BI); - if (rc) { - wil_err(wil, "%s: wmi_p2p_cfg failed\n", __func__); - goto out; - } - - rc = wmi_set_ssid(wil, strlen(P2P_WILDCARD_SSID), P2P_WILDCARD_SSID); - if (rc) { - wil_err(wil, "%s: wmi_set_ssid failed\n", __func__); - goto out_stop; - } + memcpy(&p2p->listen_chan, chan, sizeof(*chan)); + *cookie = ++p2p->cookie; + p2p->listen_duration = duration; - rc = wmi_start_listen(wil); - if (rc) { - wil_err(wil, "%s: wmi_start_listen failed\n", __func__); - goto out_stop; + mutex_lock(&wil->p2p_wdev_mutex); + if (wil->scan_request) { + wil_dbg_misc(wil, "Delaying p2p listen until scan done\n"); + p2p->pending_listen_wdev = wdev; + p2p->discovery_started = 1; + rc = 0; + mutex_unlock(&wil->p2p_wdev_mutex); + goto out; } + mutex_unlock(&wil->p2p_wdev_mutex); - memcpy(&p2p->listen_chan, chan, sizeof(*chan)); - *cookie = ++p2p->cookie; + rc = wil_p2p_start_listen(wil); + if (rc) + goto out; p2p->discovery_started = 1; - INIT_WORK(&p2p->discovery_expired_work, wil_p2p_listen_expired); - mod_timer(&p2p->discovery_timer, - jiffies + msecs_to_jiffies(duration)); + wil->radio_wdev = wdev; -out_stop: - if (rc) - wmi_stop_discovery(wil); + cfg80211_ready_on_channel(wdev, *cookie, chan, duration, + GFP_KERNEL); out: mutex_unlock(&wil->mutex); @@ -170,9 +199,14 @@ u8 wil_p2p_stop_discovery(struct wil6210_priv *wil) u8 started = p2p->discovery_started; if (p2p->discovery_started) { - del_timer_sync(&p2p->discovery_timer); + if (p2p->pending_listen_wdev) { + /* discovery not really started, only pending */ + p2p->pending_listen_wdev = NULL; + } else { + del_timer_sync(&p2p->discovery_timer); + wmi_stop_discovery(wil); + } p2p->discovery_started = 0; - wmi_stop_discovery(wil); } return started; @@ -253,11 +287,57 @@ void wil_p2p_search_expired(struct work_struct *work) if (started) { mutex_lock(&wil->p2p_wdev_mutex); - cfg80211_scan_done(wil->scan_request, 0); - wil->scan_request = NULL; - wil->radio_wdev = wil->wdev; + if (wil->scan_request) { + cfg80211_scan_done(wil->scan_request, 0); + wil->scan_request = NULL; + wil->radio_wdev = wil->wdev; + } + mutex_unlock(&wil->p2p_wdev_mutex); + } +} + +void wil_p2p_delayed_listen_work(struct work_struct *work) +{ + struct wil_p2p_info *p2p = container_of(work, + struct wil_p2p_info, delayed_listen_work); + struct wil6210_priv *wil = container_of(p2p, + struct wil6210_priv, p2p); + int rc; + + mutex_lock(&wil->mutex); + + wil_dbg_misc(wil, "Checking delayed p2p listen\n"); + if (!p2p->discovery_started || !p2p->pending_listen_wdev) + goto out; + + mutex_lock(&wil->p2p_wdev_mutex); + if (wil->scan_request) { + /* another scan started, wait again... */ mutex_unlock(&wil->p2p_wdev_mutex); + goto out; } + mutex_unlock(&wil->p2p_wdev_mutex); + + rc = wil_p2p_start_listen(wil); + + mutex_lock(&wil->p2p_wdev_mutex); + if (rc) { + cfg80211_remain_on_channel_expired(p2p->pending_listen_wdev, + p2p->cookie, + &p2p->listen_chan, + GFP_KERNEL); + wil->radio_wdev = wil->wdev; + } else { + cfg80211_ready_on_channel(p2p->pending_listen_wdev, p2p->cookie, + &p2p->listen_chan, + p2p->listen_duration, GFP_KERNEL); + wil->radio_wdev = p2p->pending_listen_wdev; + } + p2p->pending_listen_wdev = NULL; + mutex_unlock(&wil->p2p_wdev_mutex); + +out: + mutex_unlock(&wil->mutex); } void wil_p2p_stop_radio_operations(struct wil6210_priv *wil) @@ -265,8 +345,7 @@ void wil_p2p_stop_radio_operations(struct wil6210_priv *wil) struct wil_p2p_info *p2p = &wil->p2p; lockdep_assert_held(&wil->mutex); - - mutex_lock(&wil->p2p_wdev_mutex); + lockdep_assert_held(&wil->p2p_wdev_mutex); if (wil->radio_wdev != wil->p2p_wdev) goto out; @@ -274,10 +353,8 @@ void wil_p2p_stop_radio_operations(struct wil6210_priv *wil) if (!p2p->discovery_started) { /* Regular scan on the p2p device */ if (wil->scan_request && - wil->scan_request->wdev == wil->p2p_wdev) { - cfg80211_scan_done(wil->scan_request, 1); - wil->scan_request = NULL; - } + wil->scan_request->wdev == wil->p2p_wdev) + wil_abort_scan(wil, true); goto out; } @@ -300,5 +377,4 @@ void wil_p2p_stop_radio_operations(struct wil6210_priv *wil) out: wil->radio_wdev = wil->wdev; - mutex_unlock(&wil->p2p_wdev_mutex); } diff --git a/drivers/net/wireless/ath/wil6210/txrx.c b/drivers/net/wireless/ath/wil6210/txrx.c index 4c38520d4dd2..4ac9ba04afed 100644 --- a/drivers/net/wireless/ath/wil6210/txrx.c +++ b/drivers/net/wireless/ath/wil6210/txrx.c @@ -88,6 +88,18 @@ static inline int wil_vring_wmark_high(struct vring *vring) return vring->size/4; } +/* returns true if num avail descriptors is lower than wmark_low */ +static inline int wil_vring_avail_low(struct vring *vring) +{ + return wil_vring_avail_tx(vring) < wil_vring_wmark_low(vring); +} + +/* returns true if num avail descriptors is higher than wmark_high */ +static inline int wil_vring_avail_high(struct vring *vring) +{ + return wil_vring_avail_tx(vring) > wil_vring_wmark_high(vring); +} + /* wil_val_in_range - check if value in [min,max) */ static inline bool wil_val_in_range(int val, int min, int max) { @@ -1780,6 +1792,89 @@ static int wil_tx_vring(struct wil6210_priv *wil, struct vring *vring, return rc; } +/** + * Check status of tx vrings and stop/wake net queues if needed + * + * This function does one of two checks: + * In case check_stop is true, will check if net queues need to be stopped. If + * the conditions for stopping are met, netif_tx_stop_all_queues() is called. + * In case check_stop is false, will check if net queues need to be waked. If + * the conditions for waking are met, netif_tx_wake_all_queues() is called. + * vring is the vring which is currently being modified by either adding + * descriptors (tx) into it or removing descriptors (tx complete) from it. Can + * be null when irrelevant (e.g. connect/disconnect events). + * + * The implementation is to stop net queues if modified vring has low + * descriptor availability. Wake if all vrings are not in low descriptor + * availability and modified vring has high descriptor availability. + */ +static inline void __wil_update_net_queues(struct wil6210_priv *wil, + struct vring *vring, + bool check_stop) +{ + int i; + + if (vring) + wil_dbg_txrx(wil, "vring %d, check_stop=%d, stopped=%d", + (int)(vring - wil->vring_tx), check_stop, + wil->net_queue_stopped); + else + wil_dbg_txrx(wil, "check_stop=%d, stopped=%d", + check_stop, wil->net_queue_stopped); + + if (check_stop == wil->net_queue_stopped) + /* net queues already in desired state */ + return; + + if (check_stop) { + if (!vring || unlikely(wil_vring_avail_low(vring))) { + /* not enough room in the vring */ + netif_tx_stop_all_queues(wil_to_ndev(wil)); + wil->net_queue_stopped = true; + wil_dbg_txrx(wil, "netif_tx_stop called\n"); + } + return; + } + + /* check wake */ + for (i = 0; i < WIL6210_MAX_TX_RINGS; i++) { + struct vring *cur_vring = &wil->vring_tx[i]; + struct vring_tx_data *txdata = &wil->vring_tx_data[i]; + + if (!cur_vring->va || !txdata->enabled || cur_vring == vring) + continue; + + if (wil_vring_avail_low(cur_vring)) { + wil_dbg_txrx(wil, "vring %d full, can't wake\n", + (int)(cur_vring - wil->vring_tx)); + return; + } + } + + if (!vring || wil_vring_avail_high(vring)) { + /* enough room in the vring */ + wil_dbg_txrx(wil, "calling netif_tx_wake\n"); + netif_tx_wake_all_queues(wil_to_ndev(wil)); + wil->net_queue_stopped = false; + } +} + +void wil_update_net_queues(struct wil6210_priv *wil, struct vring *vring, + bool check_stop) +{ + spin_lock(&wil->net_queue_lock); + __wil_update_net_queues(wil, vring, check_stop); + spin_unlock(&wil->net_queue_lock); +} + +void wil_update_net_queues_bh(struct wil6210_priv *wil, struct vring *vring, + bool check_stop) +{ + spin_lock_bh(&wil->net_queue_lock); + __wil_update_net_queues(wil, vring, check_stop); + spin_unlock_bh(&wil->net_queue_lock); +} + netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev) { struct wil6210_priv *wil = ndev_to_wil(ndev); @@ -1822,14 +1917,10 @@ netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev) /* set up vring entry */ rc = wil_tx_vring(wil, vring, skb); - /* do we still have enough room in the vring? */ - if (unlikely(wil_vring_avail_tx(vring) < wil_vring_wmark_low(vring))) { - netif_tx_stop_all_queues(wil_to_ndev(wil)); - wil_dbg_txrx(wil, "netif_tx_stop : ring full\n"); - } - switch (rc) { case 0: + /* shall we stop net queues? */ + wil_update_net_queues_bh(wil, vring, true); /* statistics will be updated on the tx_complete */ dev_kfree_skb_any(skb); return NETDEV_TX_OK; @@ -1978,10 +2069,9 @@ int wil_tx_complete(struct wil6210_priv *wil, int ringid) txdata->last_idle = get_cycles(); } - if (wil_vring_avail_tx(vring) > wil_vring_wmark_high(vring)) { - wil_dbg_txrx(wil, "netif_tx_wake : ring not full\n"); - netif_tx_wake_all_queues(wil_to_ndev(wil)); - } + /* shall we wake net queues? */ + if (done) + wil_update_net_queues(wil, vring, false); return done; } diff --git a/drivers/net/wireless/ath/wil6210/wil6210.h b/drivers/net/wireless/ath/wil6210/wil6210.h index a19dba5b9e5f..bab0ed20c8c4 100644 --- a/drivers/net/wireless/ath/wil6210/wil6210.h +++ b/drivers/net/wireless/ath/wil6210/wil6210.h @@ -280,10 +280,11 @@ struct fw_map { u32 to; /* linker address - to, exclusive */ u32 host; /* PCI/Host address - BAR0 + 0x880000 */ const char *name; /* for debugfs */ + bool fw; /* true if FW mapping, false if UCODE mapping */ }; /* array size should be in sync with actual definition in the wmi.c */ -extern const struct fw_map fw_mapping[8]; +extern const struct fw_map fw_mapping[10]; /** * mk_cidxtid - construct @cidxtid field @@ -465,8 +466,11 @@ struct wil_p2p_info { u8 discovery_started; u8 p2p_dev_started; u64 cookie; + struct wireless_dev *pending_listen_wdev; + unsigned int listen_duration; struct timer_list discovery_timer; /* listen/search duration */ struct work_struct discovery_expired_work; /* listen/search expire */ + struct work_struct delayed_listen_work; /* listen after scan done */ }; enum wil_sta_status { @@ -628,6 +632,8 @@ struct wil6210_priv { * - consumed in thread by wmi_event_worker */ spinlock_t wmi_ev_lock; + spinlock_t net_queue_lock; /* guarding stop/wake netif queue */ + int net_queue_stopped; /* netif_tx_stop_all_queues invoked */ struct napi_struct napi_rx; struct napi_struct napi_tx; /* keep alive */ @@ -823,6 +829,10 @@ int wmi_delba_tx(struct wil6210_priv *wil, u8 ringid, u16 reason); int wmi_delba_rx(struct wil6210_priv *wil, u8 cidxtid, u16 reason); int wmi_addba_rx_resp(struct wil6210_priv *wil, u8 cid, u8 tid, u8 token, u16 status, bool amsdu, u16 agg_wsize, u16 timeout); +int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil, + enum wmi_ps_profile_type ps_profile); +int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short); +int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short); int wil_addba_rx_request(struct wil6210_priv *wil, u8 cidxtid, u8 dialog_token, __le16 ba_param_set, __le16 ba_timeout, __le16 ba_seq_ctrl); @@ -843,13 +853,15 @@ bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request); void wil_p2p_discovery_timer_fn(ulong x); int wil_p2p_search(struct wil6210_priv *wil, struct cfg80211_scan_request *request); -int wil_p2p_listen(struct wil6210_priv *wil, unsigned int duration, - struct ieee80211_channel *chan, u64 *cookie); +int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev, + unsigned int duration, struct ieee80211_channel *chan, + u64 *cookie); u8 wil_p2p_stop_discovery(struct wil6210_priv *wil); int wil_p2p_cancel_listen(struct wil6210_priv *wil, u64 cookie); void wil_p2p_listen_expired(struct work_struct *work); void wil_p2p_search_expired(struct work_struct *work); void wil_p2p_stop_radio_operations(struct wil6210_priv *wil); +void wil_p2p_delayed_listen_work(struct work_struct *work); /* WMI for P2P */ int wmi_p2p_cfg(struct wil6210_priv *wil, int channel, int bi); @@ -877,6 +889,9 @@ int wmi_pcp_stop(struct wil6210_priv *wil); int wmi_led_cfg(struct wil6210_priv *wil, bool enable); int wmi_aoa_meas(struct wil6210_priv *wil, const void *mac_addr, u8 chan, u8 type); +int wmi_abort_scan(struct wil6210_priv *wil); +void wil_abort_scan(struct wil6210_priv *wil, bool sync); + void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid, u16 reason_code, bool from_event); void wil_probe_client_flush(struct wil6210_priv *wil); @@ -894,6 +909,10 @@ int wil_vring_init_bcast(struct wil6210_priv *wil, int id, int size); int wil_bcast_init(struct wil6210_priv *wil); void wil_bcast_fini(struct wil6210_priv *wil); +void wil_update_net_queues(struct wil6210_priv *wil, struct vring *vring, + bool should_stop); +void wil_update_net_queues_bh(struct wil6210_priv *wil, struct vring *vring, + bool check_stop); netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); int wil_tx_complete(struct wil6210_priv *wil, int ringid); void wil6210_unmask_irq_tx(struct wil6210_priv *wil); diff --git a/drivers/net/wireless/ath/wil6210/wil_crash_dump.c b/drivers/net/wireless/ath/wil6210/wil_crash_dump.c index b57d280946e0..d051eea47a54 100644 --- a/drivers/net/wireless/ath/wil6210/wil_crash_dump.c +++ b/drivers/net/wireless/ath/wil6210/wil_crash_dump.c @@ -36,6 +36,9 @@ static int wil_fw_get_crash_dump_bounds(struct wil6210_priv *wil, for (i = 1; i < ARRAY_SIZE(fw_mapping); i++) { map = &fw_mapping[i]; + if (!map->fw) + continue; + if (map->host < host_min) host_min = map->host; @@ -73,6 +76,9 @@ int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size) for (i = 0; i < ARRAY_SIZE(fw_mapping); i++) { map = &fw_mapping[i]; + if (!map->fw) + continue; + data = (void * __force)wil->csr + HOSTADDR(map->host); len = map->to - map->from; offset = map->host - host_min; diff --git a/drivers/net/wireless/ath/wil6210/wmi.c b/drivers/net/wireless/ath/wil6210/wmi.c index f5575747d11e..24f42e3a6d92 100644 --- a/drivers/net/wireless/ath/wil6210/wmi.c +++ b/drivers/net/wireless/ath/wil6210/wmi.c @@ -85,19 +85,29 @@ MODULE_PARM_DESC(led_id, * array size should be in sync with the declaration in the wil6210.h */ const struct fw_map fw_mapping[] = { - {0x000000, 0x040000, 0x8c0000, "fw_code"}, /* FW code RAM 256k */ - {0x800000, 0x808000, 0x900000, "fw_data"}, /* FW data RAM 32k */ - {0x840000, 0x860000, 0x908000, "fw_peri"}, /* periph. data RAM 128k */ - {0x880000, 0x88a000, 0x880000, "rgf"}, /* various RGF 40k */ - {0x88a000, 0x88b000, 0x88a000, "AGC_tbl"}, /* AGC table 4k */ - {0x88b000, 0x88c000, 0x88b000, "rgf_ext"}, /* Pcie_ext_rgf 4k */ - {0x88c000, 0x88c200, 0x88c000, "mac_rgf_ext"}, /* mac_ext_rgf 512b */ - {0x8c0000, 0x949000, 0x8c0000, "upper"}, /* upper area 548k */ - /* - * 920000..930000 ucode code RAM - * 930000..932000 ucode data RAM - * 932000..949000 back-door debug data + /* FW code RAM 256k */ + {0x000000, 0x040000, 0x8c0000, "fw_code", true}, + /* FW data RAM 32k */ + {0x800000, 0x808000, 0x900000, "fw_data", true}, + /* periph data 128k */ + {0x840000, 0x860000, 0x908000, "fw_peri", true}, + /* various RGF 40k */ + {0x880000, 0x88a000, 0x880000, "rgf", true}, + /* AGC table 4k */ + {0x88a000, 0x88b000, 0x88a000, "AGC_tbl", true}, + /* Pcie_ext_rgf 4k */ + {0x88b000, 0x88c000, 0x88b000, "rgf_ext", true}, + /* mac_ext_rgf 512b */ + {0x88c000, 0x88c200, 0x88c000, "mac_rgf_ext", true}, + /* upper area 548k */ + {0x8c0000, 0x949000, 0x8c0000, "upper", true}, + /* UCODE areas - accessible by debugfs blobs but not by + * wmi_addr_remap. UCODE areas MUST be added AFTER FW areas! */ + /* ucode code RAM 128k */ + {0x000000, 0x020000, 0x920000, "uc_code", false}, + /* ucode data RAM 16k */ + {0x800000, 0x804000, 0x940000, "uc_data", false}, }; struct blink_on_off_time led_blink_time[] = { @@ -109,7 +119,7 @@ struct blink_on_off_time led_blink_time[] = { u8 led_polarity = LED_POLARITY_LOW_ACTIVE; /** - * return AHB address for given firmware/ucode internal (linker) address + * return AHB address for given firmware internal (linker) address * @x - internal address * If address have no valid AHB mapping, return 0 */ @@ -118,7 +128,8 @@ static u32 wmi_addr_remap(u32 x) uint i; for (i = 0; i < ARRAY_SIZE(fw_mapping); i++) { - if ((x >= fw_mapping[i].from) && (x < fw_mapping[i].to)) + if (fw_mapping[i].fw && + ((x >= fw_mapping[i].from) && (x < fw_mapping[i].to))) return x + fw_mapping[i].host - fw_mapping[i].from; } @@ -428,9 +439,11 @@ static void wmi_evt_scan_complete(struct wil6210_priv *wil, int id, mutex_lock(&wil->p2p_wdev_mutex); if (wil->scan_request) { struct wmi_scan_complete_event *data = d; - bool aborted = (data->status != WMI_SCAN_SUCCESS); + int status = le32_to_cpu(data->status); + bool aborted = (status != WMI_SCAN_SUCCESS) && + (status != WMI_SCAN_ABORT_REJECTED); - wil_dbg_wmi(wil, "SCAN_COMPLETE(0x%08x)\n", data->status); + wil_dbg_wmi(wil, "SCAN_COMPLETE(0x%08x)\n", status); wil_dbg_misc(wil, "Complete scan_request 0x%p aborted %d\n", wil->scan_request, aborted); @@ -438,6 +451,11 @@ static void wmi_evt_scan_complete(struct wil6210_priv *wil, int id, cfg80211_scan_done(wil->scan_request, aborted); wil->radio_wdev = wil->wdev; wil->scan_request = NULL; + wake_up_interruptible(&wil->wq); + if (wil->p2p.pending_listen_wdev) { + wil_dbg_misc(wil, "Scheduling delayed listen\n"); + schedule_work(&wil->p2p.delayed_listen_work); + } } else { wil_err(wil, "SCAN_COMPLETE while not scanning\n"); } @@ -547,7 +565,6 @@ static void wmi_evt_connect(struct wil6210_priv *wil, int id, void *d, int len) if ((wdev->iftype == NL80211_IFTYPE_STATION) || (wdev->iftype == NL80211_IFTYPE_P2P_CLIENT)) { if (rc) { - netif_tx_stop_all_queues(ndev); netif_carrier_off(ndev); wil_err(wil, "%s: cfg80211_connect_result with failure\n", @@ -587,7 +604,7 @@ static void wmi_evt_connect(struct wil6210_priv *wil, int id, void *d, int len) wil->sta[evt->cid].status = wil_sta_connected; set_bit(wil_status_fwconnected, wil->status); - netif_tx_wake_all_queues(ndev); + wil_update_net_queues_bh(wil, NULL, false); out: if (rc) @@ -1595,6 +1612,112 @@ int wmi_addba_rx_resp(struct wil6210_priv *wil, u8 cid, u8 tid, u8 token, return rc; } +int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil, + enum wmi_ps_profile_type ps_profile) +{ + int rc; + struct wmi_ps_dev_profile_cfg_cmd cmd = { + .ps_profile = ps_profile, + }; + struct { + struct wmi_cmd_hdr wmi; + struct wmi_ps_dev_profile_cfg_event evt; + } __packed reply; + u32 status; + + wil_dbg_wmi(wil, "Setting ps dev profile %d\n", ps_profile); + + reply.evt.status = cpu_to_le32(WMI_PS_CFG_CMD_STATUS_ERROR); + + rc = wmi_call(wil, WMI_PS_DEV_PROFILE_CFG_CMDID, &cmd, sizeof(cmd), + WMI_PS_DEV_PROFILE_CFG_EVENTID, &reply, sizeof(reply), + 100); + if (rc) + return rc; + + status = le32_to_cpu(reply.evt.status); + + if (status != WMI_PS_CFG_CMD_STATUS_SUCCESS) { + wil_err(wil, "ps dev profile cfg failed with status %d\n", + status); + rc = -EINVAL; + } + + return rc; +} + +int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short) +{ + int rc; + struct wmi_set_mgmt_retry_limit_cmd cmd = { + .mgmt_retry_limit = retry_short, + }; + struct { + struct wmi_cmd_hdr wmi; + struct wmi_set_mgmt_retry_limit_event evt; + } __packed reply; + + wil_dbg_wmi(wil, "Setting mgmt retry short %d\n", retry_short); + + if (!test_bit(WMI_FW_CAPABILITY_MGMT_RETRY_LIMIT, wil->fw_capabilities)) + return -ENOTSUPP; + + reply.evt.status = WMI_FW_STATUS_FAILURE; + + rc = wmi_call(wil, WMI_SET_MGMT_RETRY_LIMIT_CMDID, &cmd, sizeof(cmd), + WMI_SET_MGMT_RETRY_LIMIT_EVENTID, &reply, sizeof(reply), + 100); + if (rc) + return rc; + + if (reply.evt.status != WMI_FW_STATUS_SUCCESS) { + wil_err(wil, "set mgmt retry limit failed with status %d\n", + reply.evt.status); + rc = -EINVAL; + } + + return rc; +} + +int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short) +{ + int rc; + struct { + struct wmi_cmd_hdr wmi; + struct wmi_get_mgmt_retry_limit_event evt; + } __packed reply; + + wil_dbg_wmi(wil, "getting mgmt retry short\n"); + + if (!test_bit(WMI_FW_CAPABILITY_MGMT_RETRY_LIMIT, wil->fw_capabilities)) + return -ENOTSUPP; + + reply.evt.mgmt_retry_limit = 0; + rc = wmi_call(wil, WMI_GET_MGMT_RETRY_LIMIT_CMDID, NULL, 0, + WMI_GET_MGMT_RETRY_LIMIT_EVENTID, &reply, sizeof(reply), + 100); + if (rc) + return rc; + + if (retry_short) + *retry_short = reply.evt.mgmt_retry_limit; + + return 0; +} + +int wmi_abort_scan(struct wil6210_priv *wil) +{ + int rc; + + wil_dbg_wmi(wil, "sending WMI_ABORT_SCAN_CMDID\n"); + + rc = wmi_send(wil, WMI_ABORT_SCAN_CMDID, NULL, 0); + if (rc) + wil_err(wil, "Failed to abort scan (%d)\n", rc); + + return rc; +} + void wmi_event_flush(struct wil6210_priv *wil) { struct pending_wmi_event *evt, *t; diff --git a/drivers/net/wireless/ath/wil6210/wmi.h b/drivers/net/wireless/ath/wil6210/wmi.h index f430e8a80603..d93a4d490d24 100644 --- a/drivers/net/wireless/ath/wil6210/wmi.h +++ b/drivers/net/wireless/ath/wil6210/wmi.h @@ -35,6 +35,7 @@ #define WMI_MAC_LEN (6) #define WMI_PROX_RANGE_NUM (3) #define WMI_MAX_LOSS_DMG_BEACONS (20) +#define MAX_NUM_OF_SECTORS (128) /* Mailbox interface * used for commands and events @@ -51,8 +52,10 @@ enum wmi_mid { * the host */ enum wmi_fw_capability { - WMI_FW_CAPABILITY_FTM = 0, - WMI_FW_CAPABILITY_PS_CONFIG = 1, + WMI_FW_CAPABILITY_FTM = 0, + WMI_FW_CAPABILITY_PS_CONFIG = 1, + WMI_FW_CAPABILITY_RF_SECTORS = 2, + WMI_FW_CAPABILITY_MGMT_RETRY_LIMIT = 3, WMI_FW_CAPABILITY_MAX, }; @@ -66,137 +69,149 @@ struct wmi_cmd_hdr { /* List of Commands */ enum wmi_command_id { - WMI_CONNECT_CMDID = 0x01, - WMI_DISCONNECT_CMDID = 0x03, - WMI_DISCONNECT_STA_CMDID = 0x04, - WMI_START_SCAN_CMDID = 0x07, - WMI_SET_BSS_FILTER_CMDID = 0x09, - WMI_SET_PROBED_SSID_CMDID = 0x0A, - WMI_SET_LISTEN_INT_CMDID = 0x0B, - WMI_BCON_CTRL_CMDID = 0x0F, - WMI_ADD_CIPHER_KEY_CMDID = 0x16, - WMI_DELETE_CIPHER_KEY_CMDID = 0x17, - WMI_PCP_CONF_CMDID = 0x18, - WMI_SET_APPIE_CMDID = 0x3F, - WMI_SET_WSC_STATUS_CMDID = 0x41, - WMI_PXMT_RANGE_CFG_CMDID = 0x42, - WMI_PXMT_SNR2_RANGE_CFG_CMDID = 0x43, - WMI_MEM_READ_CMDID = 0x800, - WMI_MEM_WR_CMDID = 0x801, - WMI_ECHO_CMDID = 0x803, - WMI_DEEP_ECHO_CMDID = 0x804, - WMI_CONFIG_MAC_CMDID = 0x805, - WMI_CONFIG_PHY_DEBUG_CMDID = 0x806, - WMI_ADD_DEBUG_TX_PCKT_CMDID = 0x808, - WMI_PHY_GET_STATISTICS_CMDID = 0x809, - WMI_FS_TUNE_CMDID = 0x80A, - WMI_CORR_MEASURE_CMDID = 0x80B, - WMI_READ_RSSI_CMDID = 0x80C, - WMI_TEMP_SENSE_CMDID = 0x80E, - WMI_DC_CALIB_CMDID = 0x80F, - WMI_SEND_TONE_CMDID = 0x810, - WMI_IQ_TX_CALIB_CMDID = 0x811, - WMI_IQ_RX_CALIB_CMDID = 0x812, - WMI_SET_UCODE_IDLE_CMDID = 0x813, - WMI_SET_WORK_MODE_CMDID = 0x815, - WMI_LO_LEAKAGE_CALIB_CMDID = 0x816, - WMI_MARLON_R_READ_CMDID = 0x818, - WMI_MARLON_R_WRITE_CMDID = 0x819, - WMI_MARLON_R_TXRX_SEL_CMDID = 0x81A, - MAC_IO_STATIC_PARAMS_CMDID = 0x81B, - MAC_IO_DYNAMIC_PARAMS_CMDID = 0x81C, - WMI_SILENT_RSSI_CALIB_CMDID = 0x81D, - WMI_RF_RX_TEST_CMDID = 0x81E, - WMI_CFG_RX_CHAIN_CMDID = 0x820, - WMI_VRING_CFG_CMDID = 0x821, - WMI_BCAST_VRING_CFG_CMDID = 0x822, - WMI_VRING_BA_EN_CMDID = 0x823, - WMI_VRING_BA_DIS_CMDID = 0x824, - WMI_RCP_ADDBA_RESP_CMDID = 0x825, - WMI_RCP_DELBA_CMDID = 0x826, - WMI_SET_SSID_CMDID = 0x827, - WMI_GET_SSID_CMDID = 0x828, - WMI_SET_PCP_CHANNEL_CMDID = 0x829, - WMI_GET_PCP_CHANNEL_CMDID = 0x82A, - WMI_SW_TX_REQ_CMDID = 0x82B, - WMI_READ_MAC_RXQ_CMDID = 0x830, - WMI_READ_MAC_TXQ_CMDID = 0x831, - WMI_WRITE_MAC_RXQ_CMDID = 0x832, - WMI_WRITE_MAC_TXQ_CMDID = 0x833, - WMI_WRITE_MAC_XQ_FIELD_CMDID = 0x834, - WMI_MLME_PUSH_CMDID = 0x835, - WMI_BEAMFORMING_MGMT_CMDID = 0x836, - WMI_BF_TXSS_MGMT_CMDID = 0x837, - WMI_BF_SM_MGMT_CMDID = 0x838, - WMI_BF_RXSS_MGMT_CMDID = 0x839, - WMI_BF_TRIG_CMDID = 0x83A, - WMI_LINK_MAINTAIN_CFG_WRITE_CMDID = 0x842, - WMI_LINK_MAINTAIN_CFG_READ_CMDID = 0x843, - WMI_SET_SECTORS_CMDID = 0x849, - WMI_MAINTAIN_PAUSE_CMDID = 0x850, - WMI_MAINTAIN_RESUME_CMDID = 0x851, - WMI_RS_MGMT_CMDID = 0x852, - WMI_RF_MGMT_CMDID = 0x853, - WMI_THERMAL_THROTTLING_CTRL_CMDID = 0x854, - WMI_THERMAL_THROTTLING_GET_STATUS_CMDID = 0x855, - WMI_OTP_READ_CMDID = 0x856, - WMI_OTP_WRITE_CMDID = 0x857, - WMI_LED_CFG_CMDID = 0x858, + WMI_CONNECT_CMDID = 0x01, + WMI_DISCONNECT_CMDID = 0x03, + WMI_DISCONNECT_STA_CMDID = 0x04, + WMI_START_SCAN_CMDID = 0x07, + WMI_SET_BSS_FILTER_CMDID = 0x09, + WMI_SET_PROBED_SSID_CMDID = 0x0A, + WMI_SET_LISTEN_INT_CMDID = 0x0B, + WMI_BCON_CTRL_CMDID = 0x0F, + WMI_ADD_CIPHER_KEY_CMDID = 0x16, + WMI_DELETE_CIPHER_KEY_CMDID = 0x17, + WMI_PCP_CONF_CMDID = 0x18, + WMI_SET_APPIE_CMDID = 0x3F, + WMI_SET_WSC_STATUS_CMDID = 0x41, + WMI_PXMT_RANGE_CFG_CMDID = 0x42, + WMI_PXMT_SNR2_RANGE_CFG_CMDID = 0x43, + WMI_MEM_READ_CMDID = 0x800, + WMI_MEM_WR_CMDID = 0x801, + WMI_ECHO_CMDID = 0x803, + WMI_DEEP_ECHO_CMDID = 0x804, + WMI_CONFIG_MAC_CMDID = 0x805, + WMI_CONFIG_PHY_DEBUG_CMDID = 0x806, + WMI_ADD_DEBUG_TX_PCKT_CMDID = 0x808, + WMI_PHY_GET_STATISTICS_CMDID = 0x809, + WMI_FS_TUNE_CMDID = 0x80A, + WMI_CORR_MEASURE_CMDID = 0x80B, + WMI_READ_RSSI_CMDID = 0x80C, + WMI_TEMP_SENSE_CMDID = 0x80E, + WMI_DC_CALIB_CMDID = 0x80F, + WMI_SEND_TONE_CMDID = 0x810, + WMI_IQ_TX_CALIB_CMDID = 0x811, + WMI_IQ_RX_CALIB_CMDID = 0x812, + WMI_SET_UCODE_IDLE_CMDID = 0x813, + WMI_SET_WORK_MODE_CMDID = 0x815, + WMI_LO_LEAKAGE_CALIB_CMDID = 0x816, + WMI_MARLON_R_READ_CMDID = 0x818, + WMI_MARLON_R_WRITE_CMDID = 0x819, + WMI_MARLON_R_TXRX_SEL_CMDID = 0x81A, + MAC_IO_STATIC_PARAMS_CMDID = 0x81B, + MAC_IO_DYNAMIC_PARAMS_CMDID = 0x81C, + WMI_SILENT_RSSI_CALIB_CMDID = 0x81D, + WMI_RF_RX_TEST_CMDID = 0x81E, + WMI_CFG_RX_CHAIN_CMDID = 0x820, + WMI_VRING_CFG_CMDID = 0x821, + WMI_BCAST_VRING_CFG_CMDID = 0x822, + WMI_VRING_BA_EN_CMDID = 0x823, + WMI_VRING_BA_DIS_CMDID = 0x824, + WMI_RCP_ADDBA_RESP_CMDID = 0x825, + WMI_RCP_DELBA_CMDID = 0x826, + WMI_SET_SSID_CMDID = 0x827, + WMI_GET_SSID_CMDID = 0x828, + WMI_SET_PCP_CHANNEL_CMDID = 0x829, + WMI_GET_PCP_CHANNEL_CMDID = 0x82A, + WMI_SW_TX_REQ_CMDID = 0x82B, + WMI_READ_MAC_RXQ_CMDID = 0x830, + WMI_READ_MAC_TXQ_CMDID = 0x831, + WMI_WRITE_MAC_RXQ_CMDID = 0x832, + WMI_WRITE_MAC_TXQ_CMDID = 0x833, + WMI_WRITE_MAC_XQ_FIELD_CMDID = 0x834, + WMI_MLME_PUSH_CMDID = 0x835, + WMI_BEAMFORMING_MGMT_CMDID = 0x836, + WMI_BF_TXSS_MGMT_CMDID = 0x837, + WMI_BF_SM_MGMT_CMDID = 0x838, + WMI_BF_RXSS_MGMT_CMDID = 0x839, + WMI_BF_TRIG_CMDID = 0x83A, + WMI_LINK_MAINTAIN_CFG_WRITE_CMDID = 0x842, + WMI_LINK_MAINTAIN_CFG_READ_CMDID = 0x843, + WMI_SET_SECTORS_CMDID = 0x849, + WMI_MAINTAIN_PAUSE_CMDID = 0x850, + WMI_MAINTAIN_RESUME_CMDID = 0x851, + WMI_RS_MGMT_CMDID = 0x852, + WMI_RF_MGMT_CMDID = 0x853, + WMI_THERMAL_THROTTLING_CTRL_CMDID = 0x854, + WMI_THERMAL_THROTTLING_GET_STATUS_CMDID = 0x855, + WMI_OTP_READ_CMDID = 0x856, + WMI_OTP_WRITE_CMDID = 0x857, + WMI_LED_CFG_CMDID = 0x858, /* Performance monitoring commands */ - WMI_BF_CTRL_CMDID = 0x862, - WMI_NOTIFY_REQ_CMDID = 0x863, - WMI_GET_STATUS_CMDID = 0x864, - WMI_GET_RF_STATUS_CMDID = 0x866, - WMI_GET_BASEBAND_TYPE_CMDID = 0x867, - WMI_UNIT_TEST_CMDID = 0x900, - WMI_HICCUP_CMDID = 0x901, - WMI_FLASH_READ_CMDID = 0x902, - WMI_FLASH_WRITE_CMDID = 0x903, + WMI_BF_CTRL_CMDID = 0x862, + WMI_NOTIFY_REQ_CMDID = 0x863, + WMI_GET_STATUS_CMDID = 0x864, + WMI_GET_RF_STATUS_CMDID = 0x866, + WMI_GET_BASEBAND_TYPE_CMDID = 0x867, + WMI_UNIT_TEST_CMDID = 0x900, + WMI_HICCUP_CMDID = 0x901, + WMI_FLASH_READ_CMDID = 0x902, + WMI_FLASH_WRITE_CMDID = 0x903, /* Power management */ - WMI_TRAFFIC_DEFERRAL_CMDID = 0x904, - WMI_TRAFFIC_RESUME_CMDID = 0x905, + WMI_TRAFFIC_DEFERRAL_CMDID = 0x904, + WMI_TRAFFIC_RESUME_CMDID = 0x905, /* P2P */ - WMI_P2P_CFG_CMDID = 0x910, - WMI_PORT_ALLOCATE_CMDID = 0x911, - WMI_PORT_DELETE_CMDID = 0x912, - WMI_POWER_MGMT_CFG_CMDID = 0x913, - WMI_START_LISTEN_CMDID = 0x914, - WMI_START_SEARCH_CMDID = 0x915, - WMI_DISCOVERY_START_CMDID = 0x916, - WMI_DISCOVERY_STOP_CMDID = 0x917, - WMI_PCP_START_CMDID = 0x918, - WMI_PCP_STOP_CMDID = 0x919, - WMI_GET_PCP_FACTOR_CMDID = 0x91B, + WMI_P2P_CFG_CMDID = 0x910, + WMI_PORT_ALLOCATE_CMDID = 0x911, + WMI_PORT_DELETE_CMDID = 0x912, + WMI_POWER_MGMT_CFG_CMDID = 0x913, + WMI_START_LISTEN_CMDID = 0x914, + WMI_START_SEARCH_CMDID = 0x915, + WMI_DISCOVERY_START_CMDID = 0x916, + WMI_DISCOVERY_STOP_CMDID = 0x917, + WMI_PCP_START_CMDID = 0x918, + WMI_PCP_STOP_CMDID = 0x919, + WMI_GET_PCP_FACTOR_CMDID = 0x91B, /* Power Save Configuration Commands */ - WMI_PS_DEV_PROFILE_CFG_CMDID = 0x91C, + WMI_PS_DEV_PROFILE_CFG_CMDID = 0x91C, /* Not supported yet */ - WMI_PS_DEV_CFG_CMDID = 0x91D, + WMI_PS_DEV_CFG_CMDID = 0x91D, /* Not supported yet */ - WMI_PS_DEV_CFG_READ_CMDID = 0x91E, + WMI_PS_DEV_CFG_READ_CMDID = 0x91E, /* Per MAC Power Save Configuration commands * Not supported yet */ - WMI_PS_MID_CFG_CMDID = 0x91F, + WMI_PS_MID_CFG_CMDID = 0x91F, /* Not supported yet */ - WMI_PS_MID_CFG_READ_CMDID = 0x920, - WMI_RS_CFG_CMDID = 0x921, - WMI_GET_DETAILED_RS_RES_CMDID = 0x922, - WMI_AOA_MEAS_CMDID = 0x923, - WMI_TOF_SESSION_START_CMDID = 0x991, - WMI_TOF_GET_CAPABILITIES_CMDID = 0x992, - WMI_TOF_SET_LCR_CMDID = 0x993, - WMI_TOF_SET_LCI_CMDID = 0x994, - WMI_TOF_CHANNEL_INFO_CMDID = 0x995, - WMI_SET_MAC_ADDRESS_CMDID = 0xF003, - WMI_ABORT_SCAN_CMDID = 0xF007, - WMI_SET_PROMISCUOUS_MODE_CMDID = 0xF041, - WMI_GET_PMK_CMDID = 0xF048, - WMI_SET_PASSPHRASE_CMDID = 0xF049, - WMI_SEND_ASSOC_RES_CMDID = 0xF04A, - WMI_SET_ASSOC_REQ_RELAY_CMDID = 0xF04B, - WMI_MAC_ADDR_REQ_CMDID = 0xF04D, - WMI_FW_VER_CMDID = 0xF04E, - WMI_PMC_CMDID = 0xF04F, + WMI_PS_MID_CFG_READ_CMDID = 0x920, + WMI_RS_CFG_CMDID = 0x921, + WMI_GET_DETAILED_RS_RES_CMDID = 0x922, + WMI_AOA_MEAS_CMDID = 0x923, + WMI_SET_MGMT_RETRY_LIMIT_CMDID = 0x930, + WMI_GET_MGMT_RETRY_LIMIT_CMDID = 0x931, + WMI_TOF_SESSION_START_CMDID = 0x991, + WMI_TOF_GET_CAPABILITIES_CMDID = 0x992, + WMI_TOF_SET_LCR_CMDID = 0x993, + WMI_TOF_SET_LCI_CMDID = 0x994, + WMI_TOF_CHANNEL_INFO_CMDID = 0x995, + WMI_TOF_SET_TX_RX_OFFSET_CMDID = 0x997, + WMI_TOF_GET_TX_RX_OFFSET_CMDID = 0x998, + WMI_GET_RF_SECTOR_PARAMS_CMDID = 0x9A0, + WMI_SET_RF_SECTOR_PARAMS_CMDID = 0x9A1, + WMI_GET_SELECTED_RF_SECTOR_INDEX_CMDID = 0x9A2, + WMI_SET_SELECTED_RF_SECTOR_INDEX_CMDID = 0x9A3, + WMI_SET_RF_SECTOR_ON_CMDID = 0x9A4, + WMI_PRIO_TX_SECTORS_ORDER_CMDID = 0x9A5, + WMI_PRIO_TX_SECTORS_NUMBER_CMDID = 0x9A6, + WMI_PRIO_TX_SECTORS_SET_DEFAULT_CFG_CMDID = 0x9A7, + WMI_SET_MAC_ADDRESS_CMDID = 0xF003, + WMI_ABORT_SCAN_CMDID = 0xF007, + WMI_SET_PROMISCUOUS_MODE_CMDID = 0xF041, + WMI_GET_PMK_CMDID = 0xF048, + WMI_SET_PASSPHRASE_CMDID = 0xF049, + WMI_SEND_ASSOC_RES_CMDID = 0xF04A, + WMI_SET_ASSOC_REQ_RELAY_CMDID = 0xF04B, + WMI_MAC_ADDR_REQ_CMDID = 0xF04D, + WMI_FW_VER_CMDID = 0xF04E, + WMI_PMC_CMDID = 0xF04F, }; /* WMI_CONNECT_CMDID */ @@ -879,6 +894,14 @@ struct wmi_aoa_meas_cmd { __le32 meas_rf_mask; } __packed; +/* WMI_SET_MGMT_RETRY_LIMIT_CMDID */ +struct wmi_set_mgmt_retry_limit_cmd { + /* MAC retransmit limit for mgmt frames */ + u8 mgmt_retry_limit; + /* alignment to 32b */ + u8 reserved[3]; +} __packed; + enum wmi_tof_burst_duration { WMI_TOF_BURST_DURATION_250_USEC = 2, WMI_TOF_BURST_DURATION_500_USEC = 3, @@ -942,6 +965,15 @@ struct wmi_tof_channel_info_cmd { __le32 channel_info_report_request; } __packed; +/* WMI_TOF_SET_TX_RX_OFFSET_CMDID */ +struct wmi_tof_set_tx_rx_offset_cmd { + /* TX delay offset */ + __le32 tx_offset; + /* RX delay offset */ + __le32 rx_offset; + __le32 reserved[2]; +} __packed; + /* WMI Events * List of Events (target to host) */ @@ -1035,12 +1067,24 @@ enum wmi_event_id { WMI_RS_CFG_DONE_EVENTID = 0x1921, WMI_GET_DETAILED_RS_RES_EVENTID = 0x1922, WMI_AOA_MEAS_EVENTID = 0x1923, + WMI_SET_MGMT_RETRY_LIMIT_EVENTID = 0x1930, + WMI_GET_MGMT_RETRY_LIMIT_EVENTID = 0x1931, WMI_TOF_SESSION_END_EVENTID = 0x1991, WMI_TOF_GET_CAPABILITIES_EVENTID = 0x1992, WMI_TOF_SET_LCR_EVENTID = 0x1993, WMI_TOF_SET_LCI_EVENTID = 0x1994, WMI_TOF_FTM_PER_DEST_RES_EVENTID = 0x1995, WMI_TOF_CHANNEL_INFO_EVENTID = 0x1996, + WMI_TOF_SET_TX_RX_OFFSET_EVENTID = 0x1997, + WMI_TOF_GET_TX_RX_OFFSET_EVENTID = 0x1998, + WMI_GET_RF_SECTOR_PARAMS_DONE_EVENTID = 0x19A0, + WMI_SET_RF_SECTOR_PARAMS_DONE_EVENTID = 0x19A1, + WMI_GET_SELECTED_RF_SECTOR_INDEX_DONE_EVENTID = 0x19A2, + WMI_SET_SELECTED_RF_SECTOR_INDEX_DONE_EVENTID = 0x19A3, + WMI_SET_RF_SECTOR_ON_DONE_EVENTID = 0x19A4, + WMI_PRIO_TX_SECTORS_ORDER_EVENTID = 0x19A5, + WMI_PRIO_TX_SECTORS_NUMBER_EVENTID = 0x19A6, + WMI_PRIO_TX_SECTORS_SET_DEFAULT_CFG_EVENTID = 0x19A7, WMI_SET_CHANNEL_EVENTID = 0x9000, WMI_ASSOC_REQ_EVENTID = 0x9001, WMI_EAPOL_RX_EVENTID = 0x9002, @@ -1166,6 +1210,7 @@ enum baseband_type { BASEBAND_SPARROW_M_B0 = 0x05, BASEBAND_SPARROW_M_C0 = 0x06, BASEBAND_SPARROW_M_D0 = 0x07, + BASEBAND_TALYN_M_A0 = 0x08, }; /* WMI_GET_BASEBAND_TYPE_EVENTID */ @@ -2070,6 +2115,22 @@ struct wmi_aoa_meas_event { u8 meas_data[WMI_AOA_MAX_DATA_SIZE]; } __packed; +/* WMI_SET_MGMT_RETRY_LIMIT_EVENTID */ +struct wmi_set_mgmt_retry_limit_event { + /* enum wmi_fw_status */ + u8 status; + /* alignment to 32b */ + u8 reserved[3]; +} __packed; + +/* WMI_GET_MGMT_RETRY_LIMIT_EVENTID */ +struct wmi_get_mgmt_retry_limit_event { + /* MAC retransmit limit for mgmt frames */ + u8 mgmt_retry_limit; + /* alignment to 32b */ + u8 reserved[3]; +} __packed; + /* WMI_TOF_GET_CAPABILITIES_EVENTID */ struct wmi_tof_get_capabilities_event { u8 ftm_capability; @@ -2184,4 +2245,283 @@ struct wmi_tof_channel_info_event { u8 report[0]; } __packed; +/* WMI_TOF_SET_TX_RX_OFFSET_EVENTID */ +struct wmi_tof_set_tx_rx_offset_event { + /* enum wmi_fw_status */ + u8 status; + u8 reserved[3]; +} __packed; + +/* WMI_TOF_GET_TX_RX_OFFSET_EVENTID */ +struct wmi_tof_get_tx_rx_offset_event { + /* enum wmi_fw_status */ + u8 status; + u8 reserved1[3]; + /* TX delay offset */ + __le32 tx_offset; + /* RX delay offset */ + __le32 rx_offset; + __le32 reserved2[2]; +} __packed; + +/* Result status codes for WMI commands */ +enum wmi_rf_sector_status { + WMI_RF_SECTOR_STATUS_SUCCESS = 0x00, + WMI_RF_SECTOR_STATUS_BAD_PARAMETERS_ERROR = 0x01, + WMI_RF_SECTOR_STATUS_BUSY_ERROR = 0x02, + WMI_RF_SECTOR_STATUS_NOT_SUPPORTED_ERROR = 0x03, +}; + +/* Types of the RF sector (TX,RX) */ +enum wmi_rf_sector_type { + WMI_RF_SECTOR_TYPE_RX = 0x00, + WMI_RF_SECTOR_TYPE_TX = 0x01, +}; + +/* Content of RF Sector (six 32-bits registers) */ +struct wmi_rf_sector_info { + /* Phase values for RF Chains[15-0] (2bits per RF chain) */ + __le32 psh_hi; + /* Phase values for RF Chains[31-16] (2bits per RF chain) */ + __le32 psh_lo; + /* ETYPE Bit0 for all RF chains[31-0] - bit0 of Edge amplifier gain + * index + */ + __le32 etype0; + /* ETYPE Bit1 for all RF chains[31-0] - bit1 of Edge amplifier gain + * index + */ + __le32 etype1; + /* ETYPE Bit2 for all RF chains[31-0] - bit2 of Edge amplifier gain + * index + */ + __le32 etype2; + /* D-Type values (3bits each) for 8 Distribution amplifiers + X16 + * switch bits + */ + __le32 dtype_swch_off; +} __packed; + +#define WMI_INVALID_RF_SECTOR_INDEX (0xFFFF) +#define WMI_MAX_RF_MODULES_NUM (8) + +/* WMI_GET_RF_SECTOR_PARAMS_CMD */ +struct wmi_get_rf_sector_params_cmd { + /* Sector number to be retrieved */ + __le16 sector_idx; + /* enum wmi_rf_sector_type - type of requested RF sector */ + u8 sector_type; + /* bitmask vector specifying destination RF modules */ + u8 rf_modules_vec; +} __packed; + +/* \WMI_GET_RF_SECTOR_PARAMS_DONE_EVENT */ +struct wmi_get_rf_sector_params_done_event { + /* result status of WMI_GET_RF_SECTOR_PARAMS_CMD (enum + * wmi_rf_sector_status) + */ + u8 status; + /* align next field to U64 boundary */ + u8 reserved[7]; + /* TSF timestamp when RF sectors where retrieved */ + __le64 tsf; + /* Content of RF sector retrieved from each RF module */ + struct wmi_rf_sector_info sectors_info[WMI_MAX_RF_MODULES_NUM]; +} __packed; + +/* WMI_SET_RF_SECTOR_PARAMS_CMD */ +struct wmi_set_rf_sector_params_cmd { + /* Sector number to be retrieved */ + __le16 sector_idx; + /* enum wmi_rf_sector_type - type of requested RF sector */ + u8 sector_type; + /* bitmask vector specifying destination RF modules */ + u8 rf_modules_vec; + /* Content of RF sector to be written to each RF module */ + struct wmi_rf_sector_info sectors_info[WMI_MAX_RF_MODULES_NUM]; +} __packed; + +/* \WMI_SET_RF_SECTOR_PARAMS_DONE_EVENT */ +struct wmi_set_rf_sector_params_done_event { + /* result status of WMI_SET_RF_SECTOR_PARAMS_CMD (enum + * wmi_rf_sector_status) + */ + u8 status; +} __packed; + +/* WMI_GET_SELECTED_RF_SECTOR_INDEX_CMD - Get RF sector index selected by + * TXSS/BRP for communication with specified CID + */ +struct wmi_get_selected_rf_sector_index_cmd { + /* Connection/Station ID in [0:7] range */ + u8 cid; + /* type of requested RF sector (enum wmi_rf_sector_type) */ + u8 sector_type; + /* align to U32 boundary */ + u8 reserved[2]; +} __packed; + +/* \WMI_GET_SELECTED_RF_SECTOR_INDEX_DONE_EVENT - Returns retrieved RF sector + * index selected by TXSS/BRP for communication with specified CID + */ +struct wmi_get_selected_rf_sector_index_done_event { + /* Retrieved sector index selected in TXSS (for TX sector request) or + * BRP (for RX sector request) + */ + __le16 sector_idx; + /* result status of WMI_GET_SELECTED_RF_SECTOR_INDEX_CMD (enum + * wmi_rf_sector_status) + */ + u8 status; + /* align next field to U64 boundary */ + u8 reserved[5]; + /* TSF timestamp when result was retrieved */ + __le64 tsf; +} __packed; + +/* WMI_SET_SELECTED_RF_SECTOR_INDEX_CMD - Force RF sector index for + * communication with specified CID. Assumes that TXSS/BRP is disabled by + * other command + */ +struct wmi_set_selected_rf_sector_index_cmd { + /* Connection/Station ID in [0:7] range */ + u8 cid; + /* type of requested RF sector (enum wmi_rf_sector_type) */ + u8 sector_type; + /* Forced sector index */ + __le16 sector_idx; +} __packed; + +/* \WMI_SET_SELECTED_RF_SECTOR_INDEX_DONE_EVENT - Success/Fail status for + * WMI_SET_SELECTED_RF_SECTOR_INDEX_CMD + */ +struct wmi_set_selected_rf_sector_index_done_event { + /* result status of WMI_SET_SELECTED_RF_SECTOR_INDEX_CMD (enum + * wmi_rf_sector_status) + */ + u8 status; + /* align to U32 boundary */ + u8 reserved[3]; +} __packed; + +/* WMI_SET_RF_SECTOR_ON_CMD - Activates specified sector for specified rf + * modules + */ +struct wmi_set_rf_sector_on_cmd { + /* Sector index to be activated */ + __le16 sector_idx; + /* type of requested RF sector (enum wmi_rf_sector_type) */ + u8 sector_type; + /* bitmask vector specifying destination RF modules */ + u8 rf_modules_vec; +} __packed; + +/* \WMI_SET_RF_SECTOR_ON_DONE_EVENT - Success/Fail status for + * WMI_SET_RF_SECTOR_ON_CMD + */ +struct wmi_set_rf_sector_on_done_event { + /* result status of WMI_SET_RF_SECTOR_ON_CMD (enum + * wmi_rf_sector_status) + */ + u8 status; + /* align to U32 boundary */ + u8 reserved[3]; +} __packed; + +enum wmi_sector_sweep_type { + WMI_SECTOR_SWEEP_TYPE_TXSS = 0x00, + WMI_SECTOR_SWEEP_TYPE_BCON = 0x01, + WMI_SECTOR_SWEEP_TYPE_TXSS_AND_BCON = 0x02, + WMI_SECTOR_SWEEP_TYPE_NUM = 0x03, +}; + +/* WMI_PRIO_TX_SECTORS_ORDER_CMDID + * + * Set the order of TX sectors in TXSS and/or Beacon(AP). + * + * Returned event: + * - WMI_PRIO_TX_SECTORS_ORDER_EVENTID + */ +struct wmi_prio_tx_sectors_order_cmd { + /* tx sectors order to be applied, 0xFF for end of array */ + u8 tx_sectors_priority_array[MAX_NUM_OF_SECTORS]; + /* enum wmi_sector_sweep_type, TXSS and/or Beacon */ + u8 sector_sweep_type; + /* needed only for TXSS configuration */ + u8 cid; + /* alignment to 32b */ + u8 reserved[2]; +} __packed; + +/* completion status codes */ +enum wmi_prio_tx_sectors_cmd_status { + WMI_PRIO_TX_SECT_CMD_STATUS_SUCCESS = 0x00, + WMI_PRIO_TX_SECT_CMD_STATUS_BAD_PARAM = 0x01, + /* other error */ + WMI_PRIO_TX_SECT_CMD_STATUS_ERROR = 0x02, +}; + +/* WMI_PRIO_TX_SECTORS_ORDER_EVENTID */ +struct wmi_prio_tx_sectors_order_event { + /* enum wmi_prio_tx_sectors_cmd_status */ + u8 status; + /* alignment to 32b */ + u8 reserved[3]; +} __packed; + +struct wmi_prio_tx_sectors_num_cmd { + /* [0-128], 0 = No changes */ + u8 beacon_number_of_sectors; + /* [0-128], 0 = No changes */ + u8 txss_number_of_sectors; + /* [0-8] needed only for TXSS configuration */ + u8 cid; +} __packed; + +/* WMI_PRIO_TX_SECTORS_NUMBER_CMDID + * + * Set the number of active sectors in TXSS and/or Beacon. + * + * Returned event: + * - WMI_PRIO_TX_SECTORS_NUMBER_EVENTID + */ +struct wmi_prio_tx_sectors_number_cmd { + struct wmi_prio_tx_sectors_num_cmd active_sectors_num; + /* alignment to 32b */ + u8 reserved; +} __packed; + +/* WMI_PRIO_TX_SECTORS_NUMBER_EVENTID */ +struct wmi_prio_tx_sectors_number_event { + /* enum wmi_prio_tx_sectors_cmd_status */ + u8 status; + /* alignment to 32b */ + u8 reserved[3]; +} __packed; + +/* WMI_PRIO_TX_SECTORS_SET_DEFAULT_CFG_CMDID + * + * Set default sectors order and number (hard coded in board file) + * in TXSS and/or Beacon. + * + * Returned event: + * - WMI_PRIO_TX_SECTORS_SET_DEFAULT_CFG_EVENTID + */ +struct wmi_prio_tx_sectors_set_default_cfg_cmd { + /* enum wmi_sector_sweep_type, TXSS and/or Beacon */ + u8 sector_sweep_type; + /* needed only for TXSS configuration */ + u8 cid; + /* alignment to 32b */ + u8 reserved[2]; +} __packed; + +/* WMI_PRIO_TX_SECTORS_SET_DEFAULT_CFG_EVENTID */ +struct wmi_prio_tx_sectors_set_default_cfg_event { + /* enum wmi_prio_tx_sectors_cmd_status */ + u8 status; + /* alignment to 32b */ + u8 reserved[3]; +} __packed; + #endif /* __WILOCITY_WMI_H__ */ diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 9a6f1aed82e8..7c8b5e3e57a1 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -589,6 +589,7 @@ struct msm_pcie_dev_t { bool cfg_access; spinlock_t cfg_lock; unsigned long irqsave_flags; + struct mutex enumerate_lock; struct mutex setup_lock; struct irq_domain *irq_domain; @@ -4964,12 +4965,15 @@ int msm_pcie_enumerate(u32 rc_idx) int ret = 0, bus_ret = 0, scan_ret = 0; struct msm_pcie_dev_t *dev = &msm_pcie_dev[rc_idx]; + mutex_lock(&dev->enumerate_lock); + PCIE_DBG(dev, "Enumerate RC%d\n", rc_idx); if (!dev->drv_ready) { PCIE_DBG(dev, "RC%d has not been successfully probed yet\n", rc_idx); - return -EPROBE_DEFER; + ret = -EPROBE_DEFER; + goto out; } if (!dev->enumerated) { @@ -4996,8 +5000,7 @@ int msm_pcie_enumerate(u32 rc_idx) PCIE_ERR(dev, "PCIe: failed to get host bridge resources for RC%d: %d\n", dev->rc_idx, ret); - - return ret; + goto out; } bus = pci_create_root_bus(&dev->pdev->dev, 0, @@ -5008,8 +5011,8 @@ int msm_pcie_enumerate(u32 rc_idx) PCIE_ERR(dev, "PCIe: failed to create root bus for RC%d\n", dev->rc_idx); - - return -ENOMEM; + ret = -ENOMEM; + goto out; } scan_ret = pci_scan_child_bus(bus); @@ -5057,7 +5060,8 @@ int msm_pcie_enumerate(u32 rc_idx) PCIE_ERR(dev, "PCIe: Did not find PCI device for RC%d.\n", dev->rc_idx); - return -ENODEV; + ret = -ENODEV; + goto out; } bus_ret = bus_for_each_dev(&pci_bus_type, NULL, dev, @@ -5067,7 +5071,8 @@ int msm_pcie_enumerate(u32 rc_idx) PCIE_ERR(dev, "PCIe: Failed to set up device table for RC%d\n", dev->rc_idx); - return -ENODEV; + ret = -ENODEV; + goto out; } } else { PCIE_ERR(dev, "PCIe: failed to enable RC%d.\n", @@ -5078,6 +5083,9 @@ int msm_pcie_enumerate(u32 rc_idx) dev->rc_idx); } +out: + mutex_unlock(&dev->enumerate_lock); + return ret; } EXPORT_SYMBOL(msm_pcie_enumerate); @@ -6436,6 +6444,7 @@ int __init pcie_init(void) rc_name, i); spin_lock_init(&msm_pcie_dev[i].cfg_lock); msm_pcie_dev[i].cfg_access = true; + mutex_init(&msm_pcie_dev[i].enumerate_lock); mutex_init(&msm_pcie_dev[i].setup_lock); mutex_init(&msm_pcie_dev[i].recovery_lock); spin_lock_init(&msm_pcie_dev[i].linkdown_lock); diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 223339ff119d..e1ef353aa1e1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -46,7 +46,7 @@ obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-v3.o obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qrbtc-v2.o -obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-v3-falcon.o +obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-v3-660.o obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o obj-$(CONFIG_PHY_BRCMSTB_SATA) += phy-brcmstb-sata.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c b/drivers/phy/phy-qcom-ufs-qmp-v3-660.c index e88c00e01e0b..a0cb7d0896d1 100644 --- a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.c +++ b/drivers/phy/phy-qcom-ufs-qmp-v3-660.c @@ -12,12 +12,12 @@ * */ -#include "phy-qcom-ufs-qmp-v3-falcon.h" +#include "phy-qcom-ufs-qmp-v3-660.h" -#define UFS_PHY_NAME "ufs_phy_qmp_v3_falcon" +#define UFS_PHY_NAME "ufs_phy_qmp_v3_660" static -int ufs_qcom_phy_qmp_v3_falcon_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, +int ufs_qcom_phy_qmp_v3_660_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy, bool is_rate_B) { int err; @@ -55,9 +55,9 @@ out: return err; } -static int ufs_qcom_phy_qmp_v3_falcon_init(struct phy *generic_phy) +static int ufs_qcom_phy_qmp_v3_660_init(struct phy *generic_phy) { - struct ufs_qcom_phy_qmp_v3_falcon *phy = phy_get_drvdata(generic_phy); + struct ufs_qcom_phy_qmp_v3_660 *phy = phy_get_drvdata(generic_phy); struct ufs_qcom_phy *phy_common = &phy->common_cfg; int err; @@ -80,7 +80,7 @@ out: } static -void ufs_qcom_phy_qmp_v3_falcon_power_control(struct ufs_qcom_phy *phy, +void ufs_qcom_phy_qmp_v3_660_power_control(struct ufs_qcom_phy *phy, bool power_ctrl) { if (!power_ctrl) { @@ -104,7 +104,7 @@ void ufs_qcom_phy_qmp_v3_falcon_power_control(struct ufs_qcom_phy *phy, } static inline -void ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable(struct ufs_qcom_phy *phy, +void ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val) { /* @@ -114,7 +114,7 @@ void ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable(struct ufs_qcom_phy *phy, } static -void ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, +void ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, bool ctrl) { u32 temp; @@ -131,7 +131,7 @@ void ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg(struct ufs_qcom_phy *phy, mb(); } -static inline void ufs_qcom_phy_qmp_v3_falcon_start_serdes( +static inline void ufs_qcom_phy_qmp_v3_660_start_serdes( struct ufs_qcom_phy *phy) { u32 tmp; @@ -144,7 +144,7 @@ static inline void ufs_qcom_phy_qmp_v3_falcon_start_serdes( mb(); } -static int ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready( +static int ufs_qcom_phy_qmp_v3_660_is_pcs_ready( struct ufs_qcom_phy *phy_common) { int err = 0; @@ -158,7 +158,7 @@ static int ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready( return err; } -static void ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump( +static void ufs_qcom_phy_qmp_v3_660_dbg_register_dump( struct ufs_qcom_phy *phy) { ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE, @@ -171,30 +171,30 @@ static void ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump( "PHY TX0 Registers "); } -struct phy_ops ufs_qcom_phy_qmp_v3_falcon_phy_ops = { - .init = ufs_qcom_phy_qmp_v3_falcon_init, +struct phy_ops ufs_qcom_phy_qmp_v3_660_phy_ops = { + .init = ufs_qcom_phy_qmp_v3_660_init, .exit = ufs_qcom_phy_exit, .power_on = ufs_qcom_phy_power_on, .power_off = ufs_qcom_phy_power_off, .owner = THIS_MODULE, }; -struct ufs_qcom_phy_specific_ops phy_v3_falcon_ops = { - .calibrate_phy = ufs_qcom_phy_qmp_v3_falcon_phy_calibrate, - .start_serdes = ufs_qcom_phy_qmp_v3_falcon_start_serdes, +struct ufs_qcom_phy_specific_ops phy_v3_660_ops = { + .calibrate_phy = ufs_qcom_phy_qmp_v3_660_phy_calibrate, + .start_serdes = ufs_qcom_phy_qmp_v3_660_start_serdes, .is_physical_coding_sublayer_ready = - ufs_qcom_phy_qmp_v3_falcon_is_pcs_ready, - .set_tx_lane_enable = ufs_qcom_phy_qmp_v3_falcon_set_tx_lane_enable, - .ctrl_rx_linecfg = ufs_qcom_phy_qmp_v3_falcon_ctrl_rx_linecfg, - .power_control = ufs_qcom_phy_qmp_v3_falcon_power_control, - .dbg_register_dump = ufs_qcom_phy_qmp_v3_falcon_dbg_register_dump, + ufs_qcom_phy_qmp_v3_660_is_pcs_ready, + .set_tx_lane_enable = ufs_qcom_phy_qmp_v3_660_set_tx_lane_enable, + .ctrl_rx_linecfg = ufs_qcom_phy_qmp_v3_660_ctrl_rx_linecfg, + .power_control = ufs_qcom_phy_qmp_v3_660_power_control, + .dbg_register_dump = ufs_qcom_phy_qmp_v3_660_dbg_register_dump, }; -static int ufs_qcom_phy_qmp_v3_falcon_probe(struct platform_device *pdev) +static int ufs_qcom_phy_qmp_v3_660_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct phy *generic_phy; - struct ufs_qcom_phy_qmp_v3_falcon *phy; + struct ufs_qcom_phy_qmp_v3_660 *phy; int err = 0; phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); @@ -204,8 +204,8 @@ static int ufs_qcom_phy_qmp_v3_falcon_probe(struct platform_device *pdev) } generic_phy = ufs_qcom_phy_generic_probe(pdev, &phy->common_cfg, - &ufs_qcom_phy_qmp_v3_falcon_phy_ops, - &phy_v3_falcon_ops); + &ufs_qcom_phy_qmp_v3_660_phy_ops, + &phy_v3_660_ops); if (!generic_phy) { dev_err(dev, "%s: ufs_qcom_phy_generic_probe() failed\n", @@ -223,7 +223,7 @@ out: return err; } -static int ufs_qcom_phy_qmp_v3_falcon_remove(struct platform_device *pdev) +static int ufs_qcom_phy_qmp_v3_660_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct phy *generic_phy = to_phy(dev); @@ -238,23 +238,23 @@ static int ufs_qcom_phy_qmp_v3_falcon_remove(struct platform_device *pdev) return err; } -static const struct of_device_id ufs_qcom_phy_qmp_v3_falcon_of_match[] = { - {.compatible = "qcom,ufs-phy-qmp-v3-falcon"}, +static const struct of_device_id ufs_qcom_phy_qmp_v3_660_of_match[] = { + {.compatible = "qcom,ufs-phy-qmp-v3-660"}, {}, }; -MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_falcon_of_match); +MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_v3_660_of_match); -static struct platform_driver ufs_qcom_phy_qmp_v3_falcon_driver = { - .probe = ufs_qcom_phy_qmp_v3_falcon_probe, - .remove = ufs_qcom_phy_qmp_v3_falcon_remove, +static struct platform_driver ufs_qcom_phy_qmp_v3_660_driver = { + .probe = ufs_qcom_phy_qmp_v3_660_probe, + .remove = ufs_qcom_phy_qmp_v3_660_remove, .driver = { - .of_match_table = ufs_qcom_phy_qmp_v3_falcon_of_match, - .name = "ufs_qcom_phy_qmp_v3_falcon", + .of_match_table = ufs_qcom_phy_qmp_v3_660_of_match, + .name = "ufs_qcom_phy_qmp_v3_660", .owner = THIS_MODULE, }, }; -module_platform_driver(ufs_qcom_phy_qmp_v3_falcon_driver); +module_platform_driver(ufs_qcom_phy_qmp_v3_660_driver); -MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3 falcon"); +MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP v3 660"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h b/drivers/phy/phy-qcom-ufs-qmp-v3-660.h index e64601cc6b22..8d0183d87e20 100644 --- a/drivers/phy/phy-qcom-ufs-qmp-v3-falcon.h +++ b/drivers/phy/phy-qcom-ufs-qmp-v3-660.h @@ -12,8 +12,8 @@ * */ -#ifndef UFS_QCOM_PHY_QMP_V3_FALCON_H_ -#define UFS_QCOM_PHY_QMP_V3_FALCON_H_ +#ifndef UFS_QCOM_PHY_QMP_V3_660_H_ +#define UFS_QCOM_PHY_QMP_V3_660_H_ #include "phy-qcom-ufs-i.h" @@ -185,14 +185,14 @@ #define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1) /* - * This structure represents the v3 falcon specific phy. + * This structure represents the v3 660 specific phy. * common_cfg MUST remain the first field in this structure * in case extra fields are added. This way, when calling * get_ufs_qcom_phy() of generic phy, we can extract the * common phy structure (struct ufs_qcom_phy) out of it * regardless of the relevant specific phy. */ -struct ufs_qcom_phy_qmp_v3_falcon { +struct ufs_qcom_phy_qmp_v3_660 { struct ufs_qcom_phy common_cfg; }; diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 68546eec7f61..3f9f58f57393 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -112,13 +112,13 @@ config PINCTRL_MSM8996 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm MSM8996 platform. -config PINCTRL_MSMFALCON - tristate "Qualcomm MSMFALCON pin controller driver" +config PINCTRL_SDM660 + tristate "Qualcomm SDM660 pin controller driver" depends on GPIOLIB && OF select PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm MSMFALCON platform. + Qualcomm TLMM block found in the Qualcomm SDM660 platform. config PINCTRL_WCD tristate "Qualcomm Technologies, Inc WCD pin controller driver" diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index fa228c7243e2..502b91f455d7 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -14,6 +14,6 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o -obj-$(CONFIG_PINCTRL_MSMFALCON) += pinctrl-msmfalcon.o +obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_WCD) += pinctrl-wcd.o obj-$(CONFIG_PINCTRL_LPI) += pinctrl-lpi.o diff --git a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c index 91bbce2ce1d1..4dbb4cae2fae 100644 --- a/drivers/pinctrl/qcom/pinctrl-msmfalcon.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c @@ -92,7 +92,7 @@ .intr_detection_bit = -1, \ .intr_detection_width = -1, \ } -static const struct pinctrl_pin_desc msmfalcon_pins[] = { +static const struct pinctrl_pin_desc sdm660_pins[] = { PINCTRL_PIN(0, "GPIO_0"), PINCTRL_PIN(1, "GPIO_1"), PINCTRL_PIN(2, "GPIO_2"), @@ -341,7 +341,7 @@ static const unsigned int sdc2_cmd_pins[] = { 118 }; static const unsigned int sdc2_data_pins[] = { 119 }; static const unsigned int sdc1_rclk_pins[] = { 120 }; -enum msmfalcon_functions { +enum sdm660_functions { msm_mux_blsp_spi1, msm_mux_gpio, msm_mux_blsp_uim1, @@ -1259,7 +1259,7 @@ static const char * const LCD_PWR_groups[] = { "gpio113", }; -static const struct msm_function msmfalcon_functions[] = { +static const struct msm_function sdm660_functions[] = { FUNCTION(blsp_spi1), FUNCTION(gpio), FUNCTION(blsp_uim1), @@ -1486,7 +1486,7 @@ static const struct msm_function msmfalcon_functions[] = { FUNCTION(LCD_PWR), }; -static const struct msm_pingroup msmfalcon_groups[] = { +static const struct msm_pingroup sdm660_groups[] = { PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch0, NA, NA, qdss_gpio4, atest_gpsadc1, NA), PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch1, NA, NA, @@ -1675,48 +1675,48 @@ static const struct msm_pingroup msmfalcon_groups[] = { SDC_QDSD_PINGROUP(sdc1_rclk, 0x99a000, 15, 0), }; -static const struct msm_pinctrl_soc_data msmfalcon_pinctrl = { - .pins = msmfalcon_pins, - .npins = ARRAY_SIZE(msmfalcon_pins), - .functions = msmfalcon_functions, - .nfunctions = ARRAY_SIZE(msmfalcon_functions), - .groups = msmfalcon_groups, - .ngroups = ARRAY_SIZE(msmfalcon_groups), +static const struct msm_pinctrl_soc_data sdm660_pinctrl = { + .pins = sdm660_pins, + .npins = ARRAY_SIZE(sdm660_pins), + .functions = sdm660_functions, + .nfunctions = ARRAY_SIZE(sdm660_functions), + .groups = sdm660_groups, + .ngroups = ARRAY_SIZE(sdm660_groups), .ngpios = 114, }; -static int msmfalcon_pinctrl_probe(struct platform_device *pdev) +static int sdm660_pinctrl_probe(struct platform_device *pdev) { - return msm_pinctrl_probe(pdev, &msmfalcon_pinctrl); + return msm_pinctrl_probe(pdev, &sdm660_pinctrl); } -static const struct of_device_id msmfalcon_pinctrl_of_match[] = { - { .compatible = "qcom,msmfalcon-pinctrl", }, +static const struct of_device_id sdm660_pinctrl_of_match[] = { + { .compatible = "qcom,sdm660-pinctrl", }, { }, }; -static struct platform_driver msmfalcon_pinctrl_driver = { +static struct platform_driver sdm660_pinctrl_driver = { .driver = { - .name = "msmfalcon-pinctrl", + .name = "sdm660-pinctrl", .owner = THIS_MODULE, - .of_match_table = msmfalcon_pinctrl_of_match, + .of_match_table = sdm660_pinctrl_of_match, }, - .probe = msmfalcon_pinctrl_probe, + .probe = sdm660_pinctrl_probe, .remove = msm_pinctrl_remove, }; -static int __init msmfalcon_pinctrl_init(void) +static int __init sdm660_pinctrl_init(void) { - return platform_driver_register(&msmfalcon_pinctrl_driver); + return platform_driver_register(&sdm660_pinctrl_driver); } -arch_initcall(msmfalcon_pinctrl_init); +arch_initcall(sdm660_pinctrl_init); -static void __exit msmfalcon_pinctrl_exit(void) +static void __exit sdm660_pinctrl_exit(void) { - platform_driver_unregister(&msmfalcon_pinctrl_driver); + platform_driver_unregister(&sdm660_pinctrl_driver); } -module_exit(msmfalcon_pinctrl_exit); +module_exit(sdm660_pinctrl_exit); -MODULE_DESCRIPTION("QTI msmfalcon pinctrl driver"); +MODULE_DESCRIPTION("QTI sdm660 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msmfalcon_pinctrl_of_match); +MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match); diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa.c b/drivers/platform/msm/ipa/ipa_v2/ipa.c index 73add50cf224..d82651f7b492 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa.c @@ -450,7 +450,7 @@ static int ipa_open(struct inode *inode, struct file *filp) { struct ipa_context *ctx = NULL; - IPADBG("ENTER\n"); + IPADBG_LOW("ENTER\n"); ctx = container_of(inode->i_cdev, struct ipa_context, cdev); filp->private_data = ctx; @@ -2936,11 +2936,11 @@ static int ipa_get_clks(struct device *dev) void _ipa_enable_clks_v2_0(void) { - IPADBG("enabling gcc_ipa_clk\n"); + IPADBG_LOW("enabling gcc_ipa_clk\n"); if (ipa_clk) { clk_prepare(ipa_clk); clk_enable(ipa_clk); - IPADBG("curr_ipa_clk_rate=%d", ipa_ctx->curr_ipa_clk_rate); + IPADBG_LOW("curr_ipa_clk_rate=%d", ipa_ctx->curr_ipa_clk_rate); clk_set_rate(ipa_clk, ipa_ctx->curr_ipa_clk_rate); ipa_uc_notify_clk_state(true); } else { @@ -3072,7 +3072,7 @@ void _ipa_disable_clks_v1_1(void) void _ipa_disable_clks_v2_0(void) { - IPADBG("disabling gcc_ipa_clk\n"); + IPADBG_LOW("disabling gcc_ipa_clk\n"); ipa_suspend_apps_pipes(true); ipa_sps_irq_control_all(false); ipa_uc_notify_clk_state(false); @@ -3093,7 +3093,7 @@ void _ipa_disable_clks_v2_0(void) */ void ipa_disable_clks(void) { - IPADBG("disabling IPA clocks and bus voting\n"); + IPADBG_LOW("disabling IPA clocks and bus voting\n"); ipa_ctx->ctrl->ipa_disable_clks(); @@ -3237,7 +3237,7 @@ void ipa2_inc_client_enable_clks(struct ipa_active_client_logging_info *id) ipa_ctx->ipa_active_clients.cnt++; if (ipa_ctx->ipa_active_clients.cnt == 1) ipa_enable_clks(); - IPADBG("active clients = %d\n", ipa_ctx->ipa_active_clients.cnt); + IPADBG_LOW("active clients = %d\n", ipa_ctx->ipa_active_clients.cnt); ipa_active_clients_unlock(); } @@ -3269,7 +3269,7 @@ int ipa2_inc_client_enable_clks_no_block(struct ipa_active_client_logging_info ipa2_active_clients_log_inc(id, true); ipa_ctx->ipa_active_clients.cnt++; - IPADBG("active clients = %d\n", ipa_ctx->ipa_active_clients.cnt); + IPADBG_LOW("active clients = %d\n", ipa_ctx->ipa_active_clients.cnt); bail: ipa_active_clients_trylock_unlock(&flags); @@ -3297,7 +3297,7 @@ void ipa2_dec_client_disable_clks(struct ipa_active_client_logging_info *id) ipa_active_clients_lock(); ipa2_active_clients_log_dec(id, false); ipa_ctx->ipa_active_clients.cnt--; - IPADBG("active clients = %d\n", ipa_ctx->ipa_active_clients.cnt); + IPADBG_LOW("active clients = %d\n", ipa_ctx->ipa_active_clients.cnt); if (ipa_ctx->ipa_active_clients.cnt == 0) { if (ipa_ctx->tag_process_before_gating) { IPA_ACTIVE_CLIENTS_PREP_SPECIAL(log_info, @@ -3337,7 +3337,7 @@ void ipa_inc_acquire_wakelock(enum ipa_wakelock_ref_client ref_client) ipa_ctx->wakelock_ref_cnt.cnt |= (1 << ref_client); if (ipa_ctx->wakelock_ref_cnt.cnt) __pm_stay_awake(&ipa_ctx->w_lock); - IPADBG("active wakelock ref cnt = %d client enum %d\n", + IPADBG_LOW("active wakelock ref cnt = %d client enum %d\n", ipa_ctx->wakelock_ref_cnt.cnt, ref_client); spin_unlock_irqrestore(&ipa_ctx->wakelock_ref_cnt.spinlock, flags); } @@ -3358,7 +3358,7 @@ void ipa_dec_release_wakelock(enum ipa_wakelock_ref_client ref_client) return; spin_lock_irqsave(&ipa_ctx->wakelock_ref_cnt.spinlock, flags); ipa_ctx->wakelock_ref_cnt.cnt &= ~(1 << ref_client); - IPADBG("active wakelock ref cnt = %d client enum %d\n", + IPADBG_LOW("active wakelock ref cnt = %d client enum %d\n", ipa_ctx->wakelock_ref_cnt.cnt, ref_client); if (ipa_ctx->wakelock_ref_cnt.cnt == 0) __pm_relax(&ipa_ctx->w_lock); @@ -3402,7 +3402,7 @@ int ipa2_set_required_perf_profile(enum ipa_voltage_level floor_voltage, enum ipa_voltage_level needed_voltage; u32 clk_rate; - IPADBG("floor_voltage=%d, bandwidth_mbps=%u", + IPADBG_LOW("floor_voltage=%d, bandwidth_mbps=%u", floor_voltage, bandwidth_mbps); if (floor_voltage < IPA_VOLTAGE_UNSPECIFIED || @@ -3412,7 +3412,7 @@ int ipa2_set_required_perf_profile(enum ipa_voltage_level floor_voltage, } if (ipa_ctx->enable_clock_scaling) { - IPADBG("Clock scaling is enabled\n"); + IPADBG_LOW("Clock scaling is enabled\n"); if (bandwidth_mbps >= ipa_ctx->ctrl->clock_scaling_bw_threshold_turbo) needed_voltage = IPA_VOLTAGE_TURBO; @@ -3422,7 +3422,7 @@ int ipa2_set_required_perf_profile(enum ipa_voltage_level floor_voltage, else needed_voltage = IPA_VOLTAGE_SVS; } else { - IPADBG("Clock scaling is disabled\n"); + IPADBG_LOW("Clock scaling is disabled\n"); needed_voltage = IPA_VOLTAGE_NOMINAL; } @@ -3444,13 +3444,13 @@ int ipa2_set_required_perf_profile(enum ipa_voltage_level floor_voltage, } if (clk_rate == ipa_ctx->curr_ipa_clk_rate) { - IPADBG("Same voltage\n"); + IPADBG_LOW("Same voltage\n"); return 0; } ipa_active_clients_lock(); ipa_ctx->curr_ipa_clk_rate = clk_rate; - IPADBG("setting clock rate to %u\n", ipa_ctx->curr_ipa_clk_rate); + IPADBG_LOW("setting clock rate to %u\n", ipa_ctx->curr_ipa_clk_rate); if (ipa_ctx->ipa_active_clients.cnt > 0) { clk_set_rate(ipa_clk, ipa_ctx->curr_ipa_clk_rate); if (ipa_ctx->ipa_hw_mode != IPA_HW_MODE_VIRTUAL) @@ -3458,10 +3458,10 @@ int ipa2_set_required_perf_profile(enum ipa_voltage_level floor_voltage, ipa_ctx->ipa_bus_hdl, ipa_get_bus_vote())) WARN_ON(1); } else { - IPADBG("clocks are gated, not setting rate\n"); + IPADBG_LOW("clocks are gated, not setting rate\n"); } ipa_active_clients_unlock(); - IPADBG("Done\n"); + IPADBG_LOW("Done\n"); return 0; } @@ -3755,6 +3755,13 @@ static int ipa_init(const struct ipa_plat_drv_res *resource_p, goto fail_mem_ctx; } + ipa_ctx->logbuf = ipc_log_context_create(IPA_IPC_LOG_PAGES, "ipa", 0); + if (ipa_ctx->logbuf == NULL) { + IPAERR("failed to get logbuf\n"); + result = -ENOMEM; + goto fail_logbuf; + } + ipa_ctx->pdev = ipa_dev; ipa_ctx->uc_pdev = ipa_dev; ipa_ctx->smmu_present = smmu_info.present; @@ -4289,6 +4296,8 @@ fail_bus_reg: fail_bind: kfree(ipa_ctx->ctrl); fail_mem_ctrl: + ipc_log_context_destroy(ipa_ctx->logbuf); +fail_logbuf: kfree(ipa_ctx); ipa_ctx = NULL; fail_mem_ctx: diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_debugfs.c b/drivers/platform/msm/ipa/ipa_v2/ipa_debugfs.c index 50c387ec785d..7ce51fccb822 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_debugfs.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_debugfs.c @@ -1804,6 +1804,44 @@ static ssize_t ipa_write_polling_iteration(struct file *file, return count; } +static ssize_t ipa_enable_ipc_low(struct file *file, + const char __user *ubuf, size_t count, loff_t *ppos) +{ + unsigned long missing; + s8 option = 0; + + if (sizeof(dbg_buff) < count + 1) + return -EFAULT; + + missing = copy_from_user(dbg_buff, ubuf, count); + if (missing) + return -EFAULT; + + dbg_buff[count] = '\0'; + if (kstrtos8(dbg_buff, 0, &option)) + return -EFAULT; + + if (option) { + if (!ipa_ctx->logbuf_low) { + ipa_ctx->logbuf_low = + ipc_log_context_create(IPA_IPC_LOG_PAGES, + "ipa_low", 0); + } + + if (ipa_ctx->logbuf_low == NULL) { + IPAERR("failed to get logbuf_low\n"); + return -EFAULT; + } + + } else { + if (ipa_ctx->logbuf_low) + ipc_log_context_destroy(ipa_ctx->logbuf_low); + ipa_ctx->logbuf_low = NULL; + } + + return count; +} + const struct file_operations ipa_gen_reg_ops = { .read = ipa_read_gen_reg, }; @@ -1882,6 +1920,10 @@ const struct file_operations ipa2_active_clients = { .write = ipa2_clear_active_clients_log, }; +const struct file_operations ipa_ipc_low_ops = { + .write = ipa_enable_ipc_low, +}; + const struct file_operations ipa_rx_poll_time_ops = { .read = ipa_read_rx_polling_timeout, .write = ipa_write_rx_polling_timeout, @@ -2097,6 +2139,13 @@ void ipa_debugfs_init(void) goto fail; } + file = debugfs_create_file("enable_low_prio_print", write_only_mode, + dent, 0, &ipa_ipc_low_ops); + if (!file) { + IPAERR("could not create enable_low_prio_print file\n"); + goto fail; + } + return; fail: diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_dma.c b/drivers/platform/msm/ipa/ipa_v2/ipa_dma.c index e08f281b1864..21be67aa2494 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_dma.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_dma.c @@ -32,16 +32,39 @@ #define IPADMA_DRV_NAME "ipa_dma" #define IPADMA_DBG(fmt, args...) \ - pr_debug(IPADMA_DRV_NAME " %s:%d " fmt, \ - __func__, __LINE__, ## args) + do { \ + pr_debug(IPADMA_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf(), \ + IPADMA_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \ + IPADMA_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPADMA_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPADMA_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \ + IPADMA_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + #define IPADMA_ERR(fmt, args...) \ - pr_err(IPADMA_DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args) + do { \ + pr_err(IPADMA_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf(), \ + IPADMA_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \ + IPADMA_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) #define IPADMA_FUNC_ENTRY() \ - IPADMA_DBG("ENTRY\n") + IPADMA_DBG_LOW("ENTRY\n") #define IPADMA_FUNC_EXIT() \ - IPADMA_DBG("EXIT\n") + IPADMA_DBG_LOW("EXIT\n") + #ifdef CONFIG_DEBUG_FS #define IPADMA_MAX_MSG_LEN 1024 @@ -270,7 +293,7 @@ int ipa2_dma_enable(void) } mutex_lock(&ipa_dma_ctx->enable_lock); if (ipa_dma_ctx->is_enabled) { - IPADMA_DBG("Already enabled.\n"); + IPADMA_ERR("Already enabled.\n"); mutex_unlock(&ipa_dma_ctx->enable_lock); return -EPERM; } @@ -296,7 +319,7 @@ static bool ipa_dma_work_pending(void) IPADMA_DBG("pending uc\n"); return true; } - IPADMA_DBG("no pending work\n"); + IPADMA_DBG_LOW("no pending work\n"); return false; } @@ -324,7 +347,7 @@ int ipa2_dma_disable(void) mutex_lock(&ipa_dma_ctx->enable_lock); spin_lock_irqsave(&ipa_dma_ctx->pending_lock, flags); if (!ipa_dma_ctx->is_enabled) { - IPADMA_DBG("Already disabled.\n"); + IPADMA_ERR("Already disabled.\n"); spin_unlock_irqrestore(&ipa_dma_ctx->pending_lock, flags); mutex_unlock(&ipa_dma_ctx->enable_lock); return -EPERM; @@ -371,6 +394,8 @@ int ipa2_dma_sync_memcpy(u64 dest, u64 src, int len) IPADMA_FUNC_ENTRY(); + IPADMA_DBG_LOW("dest = 0x%llx, src = 0x%llx, len = %d\n", + dest, src, len); if (ipa_dma_ctx == NULL) { IPADMA_ERR("IPADMA isn't initialized, can't memcpy\n"); return -EPERM; @@ -398,7 +423,7 @@ int ipa2_dma_sync_memcpy(u64 dest, u64 src, int len) if (atomic_read(&ipa_dma_ctx->sync_memcpy_pending_cnt) >= IPA_DMA_MAX_PENDING_SYNC) { atomic_dec(&ipa_dma_ctx->sync_memcpy_pending_cnt); - IPADMA_DBG("Reached pending requests limit\n"); + IPADMA_ERR("Reached pending requests limit\n"); return -EFAULT; } @@ -531,6 +556,8 @@ int ipa2_dma_async_memcpy(u64 dest, u64 src, int len, unsigned long flags; IPADMA_FUNC_ENTRY(); + IPADMA_DBG_LOW("dest = 0x%llx, src = 0x%llx, len = %d\n", + dest, src, len); if (ipa_dma_ctx == NULL) { IPADMA_ERR("IPADMA isn't initialized, can't memcpy\n"); return -EPERM; @@ -562,7 +589,7 @@ int ipa2_dma_async_memcpy(u64 dest, u64 src, int len, if (atomic_read(&ipa_dma_ctx->async_memcpy_pending_cnt) >= IPA_DMA_MAX_PENDING_ASYNC) { atomic_dec(&ipa_dma_ctx->async_memcpy_pending_cnt); - IPADMA_DBG("Reached pending requests limit\n"); + IPADMA_ERR("Reached pending requests limit\n"); return -EFAULT; } @@ -692,7 +719,7 @@ void ipa2_dma_destroy(void) IPADMA_FUNC_ENTRY(); if (!ipa_dma_ctx) { - IPADMA_DBG("IPADMA isn't initialized\n"); + IPADMA_ERR("IPADMA isn't initialized\n"); return; } @@ -836,7 +863,7 @@ static ssize_t ipa_dma_debugfs_reset_statistics(struct file *file, switch (in_num) { case 0: if (ipa_dma_work_pending()) - IPADMA_DBG("Note, there are pending memcpy\n"); + IPADMA_ERR("Note, there are pending memcpy\n"); atomic_set(&ipa_dma_ctx->total_async_memcpy, 0); atomic_set(&ipa_dma_ctx->total_sync_memcpy, 0); diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c index a7f1f9a040f9..7b48991cba65 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_dp.c @@ -346,7 +346,7 @@ int ipa_send_one(struct ipa_sys_context *sys, struct ipa_desc *desc, if (desc->type == IPA_IMM_CMD_DESC) { sps_flags |= SPS_IOVEC_FLAG_IMME; len = desc->opcode; - IPADBG("sending cmd=%d pyld_len=%d sps_flags=%x\n", + IPADBG_LOW("sending cmd=%d pyld_len=%d sps_flags=%x\n", desc->opcode, desc->len, sps_flags); IPA_DUMP_BUFF(desc->pyld, dma_address, desc->len); } else { @@ -624,7 +624,7 @@ static void ipa_sps_irq_cmd_ack(void *user1, int user2) WARN_ON(1); return; } - IPADBG("got ack for cmd=%d\n", desc->opcode); + IPADBG_LOW("got ack for cmd=%d\n", desc->opcode); complete(&desc->xfer_done); } @@ -641,11 +641,12 @@ static void ipa_sps_irq_cmd_ack(void *user1, int user2) int ipa_send_cmd(u16 num_desc, struct ipa_desc *descr) { struct ipa_desc *desc; - int result = 0; + int i, result = 0; struct ipa_sys_context *sys; int ep_idx; - IPADBG("sending command\n"); + for (i = 0; i < num_desc; i++) + IPADBG_LOW("sending imm cmd %d\n", descr[i].opcode); ep_idx = ipa2_get_ep_mapping(IPA_CLIENT_APPS_CMD_PROD); if (-1 == ep_idx) { @@ -706,7 +707,7 @@ static void ipa_sps_irq_tx_notify(struct sps_event_notify *notify) struct ipa_sys_context *sys = (struct ipa_sys_context *)notify->user; int ret; - IPADBG("event %d notified\n", notify->event_id); + IPADBG_LOW("event %d notified\n", notify->event_id); switch (notify->event_id) { case SPS_EVENT_EOT: @@ -749,7 +750,7 @@ static void ipa_sps_irq_tx_no_aggr_notify(struct sps_event_notify *notify) { struct ipa_tx_pkt_wrapper *tx_pkt; - IPADBG("event %d notified\n", notify->event_id); + IPADBG_LOW("event %d notified\n", notify->event_id); switch (notify->event_id) { case SPS_EVENT_EOT: @@ -1596,7 +1597,7 @@ static void ipa_tx_comp_usr_notify_release(void *user1, int user2) struct sk_buff *skb = (struct sk_buff *)user1; int ep_idx = user2; - IPADBG("skb=%p ep=%d\n", skb, ep_idx); + IPADBG_LOW("skb=%p ep=%d\n", skb, ep_idx); IPA_STATS_INC_CNT(ipa_ctx->stats.tx_pkts_compl); @@ -1916,7 +1917,7 @@ static void ipa_replenish_wlan_rx_cache(struct ipa_sys_context *sys) int ret; u32 rx_len_cached = 0; - IPADBG("\n"); + IPADBG_LOW("\n"); spin_lock_bh(&ipa_ctx->wc_memb.wlan_spinlock); rx_len_cached = sys->len; @@ -2339,7 +2340,7 @@ static int ipa_lan_rx_pyld_hdlr(struct sk_buff *skb, } if (sys->len_partial) { - IPADBG("len_partial %d\n", sys->len_partial); + IPADBG_LOW("len_partial %d\n", sys->len_partial); buf = skb_push(skb, sys->len_partial); memcpy(buf, sys->prev_skb->data, sys->len_partial); sys->len_partial = 0; @@ -2351,7 +2352,7 @@ static int ipa_lan_rx_pyld_hdlr(struct sk_buff *skb, /* this pipe has TX comp (status only) + mux-ed LAN RX data * (status+data) */ if (sys->len_rem) { - IPADBG("rem %d skb %d pad %d\n", sys->len_rem, skb->len, + IPADBG_LOW("rem %d skb %d pad %d\n", sys->len_rem, skb->len, sys->len_pad); if (sys->len_rem <= skb->len) { if (sys->prev_skb) { @@ -2402,7 +2403,7 @@ static int ipa_lan_rx_pyld_hdlr(struct sk_buff *skb, begin: while (skb->len) { sys->drop_packet = false; - IPADBG("LEN_REM %d\n", skb->len); + IPADBG_LOW("LEN_REM %d\n", skb->len); if (skb->len < IPA_PKT_STATUS_SIZE) { WARN_ON(sys->prev_skb != NULL); @@ -2413,7 +2414,7 @@ begin: } status = (struct ipa_hw_pkt_status *)skb->data; - IPADBG("STATUS opcode=%d src=%d dst=%d len=%d\n", + IPADBG_LOW("STATUS opcode=%d src=%d dst=%d len=%d\n", status->status_opcode, status->endp_src_idx, status->endp_dest_idx, status->pkt_len); if (sys->status_stat) { @@ -2451,7 +2452,7 @@ begin: if (status->status_mask & IPA_HW_PKT_STATUS_MASK_TAG_VALID) { struct ipa_tag_completion *comp; - IPADBG("TAG packet arrived\n"); + IPADBG_LOW("TAG packet arrived\n"); if (status->tag_f_2 == IPA_COOKIE) { skb_pull(skb, IPA_PKT_STATUS_SIZE); if (skb->len < sizeof(comp)) { @@ -2491,7 +2492,7 @@ begin: if (skb->len == IPA_PKT_STATUS_SIZE && !status->exception) { WARN_ON(sys->prev_skb != NULL); - IPADBG("Ins header in next buffer\n"); + IPADBG_LOW("Ins header in next buffer\n"); sys->prev_skb = skb_copy(skb, GFP_KERNEL); sys->len_partial = skb->len; return rc; @@ -2502,12 +2503,13 @@ begin: len = status->pkt_len + pad_len_byte + IPA_SIZE_DL_CSUM_META_TRAILER; - IPADBG("pad %d pkt_len %d len %d\n", pad_len_byte, + IPADBG_LOW("pad %d pkt_len %d len %d\n", pad_len_byte, status->pkt_len, len); if (status->exception == IPA_HW_PKT_STATUS_EXCEPTION_DEAGGR) { - IPADBG("Dropping packet on DeAggr Exception\n"); + IPADBG_LOW("Dropping packet"); + IPADBG_LOW(" on DeAggr Exception\n"); sys->drop_packet = true; } @@ -2516,7 +2518,7 @@ begin: skb2 = ipa_skb_copy_for_client(skb, skb2_len); if (likely(skb2)) { if (skb->len < len + IPA_PKT_STATUS_SIZE) { - IPADBG("SPL skb len %d len %d\n", + IPADBG_LOW("SPL skb len %d len %d\n", skb->len, len); sys->prev_skb = skb2; sys->len_rem = len - skb->len + @@ -2526,7 +2528,7 @@ begin: } else { skb_trim(skb2, status->pkt_len + IPA_PKT_STATUS_SIZE); - IPADBG("rx avail for %d\n", + IPADBG_LOW("rx avail for %d\n", status->endp_dest_idx); if (sys->drop_packet) { dev_kfree_skb_any(skb2); @@ -2570,11 +2572,12 @@ begin: } /* TX comp */ ipa_wq_write_done_status(src_pipe); - IPADBG("tx comp imp for %d\n", src_pipe); + IPADBG_LOW("tx comp imp for %d\n", src_pipe); } else { /* TX comp */ ipa_wq_write_done_status(status->endp_src_idx); - IPADBG("tx comp exp for %d\n", status->endp_src_idx); + IPADBG_LOW + ("tx comp exp for %d\n", status->endp_src_idx); skb_pull(skb, IPA_PKT_STATUS_SIZE); IPA_STATS_INC_CNT(ipa_ctx->stats.stat_compl); IPA_STATS_DEC_CNT( @@ -2610,13 +2613,13 @@ static void wan_rx_handle_splt_pyld(struct sk_buff *skb, { struct sk_buff *skb2; - IPADBG("rem %d skb %d\n", sys->len_rem, skb->len); + IPADBG_LOW("rem %d skb %d\n", sys->len_rem, skb->len); if (sys->len_rem <= skb->len) { if (sys->prev_skb) { skb2 = join_prev_skb(sys->prev_skb, skb, sys->len_rem); if (likely(skb2)) { - IPADBG( + IPADBG_LOW( "removing Status element from skb and sending to WAN client"); skb_pull(skb2, IPA_PKT_STATUS_SIZE); skb2->truesize = skb2->len + @@ -2679,14 +2682,14 @@ static int ipa_wan_rx_pyld_hdlr(struct sk_buff *skb, while (skb->len) { - IPADBG("LEN_REM %d\n", skb->len); + IPADBG_LOW("LEN_REM %d\n", skb->len); if (skb->len < IPA_PKT_STATUS_SIZE) { IPAERR("status straddles buffer\n"); WARN_ON(1); goto bail; } status = (struct ipa_hw_pkt_status *)skb->data; - IPADBG("STATUS opcode=%d src=%d dst=%d len=%d\n", + IPADBG_LOW("STATUS opcode=%d src=%d dst=%d len=%d\n", status->status_opcode, status->endp_src_idx, status->endp_dest_idx, status->pkt_len); @@ -2717,7 +2720,7 @@ static int ipa_wan_rx_pyld_hdlr(struct sk_buff *skb, goto bail; } if (status->pkt_len == 0) { - IPADBG("Skip aggr close status\n"); + IPADBG_LOW("Skip aggr close status\n"); skb_pull(skb, IPA_PKT_STATUS_SIZE); IPA_STATS_DEC_CNT(ipa_ctx->stats.rx_pkts); IPA_STATS_INC_CNT(ipa_ctx->stats.wan_aggr_close); @@ -2744,11 +2747,11 @@ static int ipa_wan_rx_pyld_hdlr(struct sk_buff *skb, /*QMAP is BE: convert the pkt_len field from BE to LE*/ pkt_len_with_pad = ntohs((qmap_hdr>>16) & 0xffff); - IPADBG("pkt_len with pad %d\n", pkt_len_with_pad); + IPADBG_LOW("pkt_len with pad %d\n", pkt_len_with_pad); /*get the CHECKSUM_PROCESS bit*/ checksum_trailer_exists = status->status_mask & IPA_HW_PKT_STATUS_MASK_CKSUM_PROCESS; - IPADBG("checksum_trailer_exists %d\n", + IPADBG_LOW("checksum_trailer_exists %d\n", checksum_trailer_exists); frame_len = IPA_PKT_STATUS_SIZE + @@ -2756,7 +2759,7 @@ static int ipa_wan_rx_pyld_hdlr(struct sk_buff *skb, pkt_len_with_pad; if (checksum_trailer_exists) frame_len += IPA_DL_CHECKSUM_LENGTH; - IPADBG("frame_len %d\n", frame_len); + IPADBG_LOW("frame_len %d\n", frame_len); skb2 = skb_clone(skb, GFP_KERNEL); if (likely(skb2)) { @@ -2765,16 +2768,16 @@ static int ipa_wan_rx_pyld_hdlr(struct sk_buff *skb, * payload split across 2 buff */ if (skb->len < frame_len) { - IPADBG("SPL skb len %d len %d\n", + IPADBG_LOW("SPL skb len %d len %d\n", skb->len, frame_len); sys->prev_skb = skb2; sys->len_rem = frame_len - skb->len; skb_pull(skb, skb->len); } else { skb_trim(skb2, frame_len); - IPADBG("rx avail for %d\n", + IPADBG_LOW("rx avail for %d\n", status->endp_dest_idx); - IPADBG( + IPADBG_LOW( "removing Status element from skb and sending to WAN client"); skb_pull(skb2, IPA_PKT_STATUS_SIZE); skb2->truesize = skb2->len + @@ -2914,7 +2917,7 @@ void ipa_lan_rx_cb(void *priv, enum ipa_dp_evt_type evt, unsigned long data) ------------------------------------------ */ *(u16 *)rx_skb->cb = ((metadata >> 16) & 0xFFFF); - IPADBG("meta_data: 0x%x cb: 0x%x\n", + IPADBG_LOW("meta_data: 0x%x cb: 0x%x\n", metadata, *(u32 *)rx_skb->cb); ep->client_notify(ep->priv, IPA_RECEIVE, (unsigned long)(rx_skb)); @@ -3017,7 +3020,7 @@ static void ipa_wlan_wq_rx_common(struct ipa_sys_context *sys, u32 size) static void ipa_dma_memcpy_notify(struct ipa_sys_context *sys, struct sps_iovec *iovec) { - IPADBG("ENTER.\n"); + IPADBG_LOW("ENTER.\n"); if (unlikely(list_empty(&sys->head_desc_list))) { IPAERR("descriptor list is empty!\n"); WARN_ON(1); @@ -3064,7 +3067,8 @@ void ipa_sps_irq_rx_no_aggr_notify(struct sps_event_notify *notify) if (IPA_CLIENT_IS_APPS_CONS(rx_pkt->sys->ep->client)) atomic_set(&ipa_ctx->sps_pm.eot_activity, 1); rx_pkt->len = notify->data.transfer.iovec.size; - IPADBG("event %d notified sys=%p len=%u\n", notify->event_id, + IPADBG_LOW + ("event %d notified sys=%p len=%u\n", notify->event_id, notify->user, rx_pkt->len); queue_work(rx_pkt->sys->wq, &rx_pkt->work); break; @@ -3370,15 +3374,15 @@ static void ipa_tx_client_rx_notify_release(void *user1, int user2) struct ipa_tx_data_desc *dd = (struct ipa_tx_data_desc *)user1; int ep_idx = user2; - IPADBG("Received data desc anchor:%p\n", dd); + IPADBG_LOW("Received data desc anchor:%p\n", dd); atomic_inc(&ipa_ctx->ep[ep_idx].avail_fifo_desc); ipa_ctx->ep[ep_idx].wstats.rx_pkts_status_rcvd++; /* wlan host driver waits till tx complete before unload */ - IPADBG("ep=%d fifo_desc_free_count=%d\n", + IPADBG_LOW("ep=%d fifo_desc_free_count=%d\n", ep_idx, atomic_read(&ipa_ctx->ep[ep_idx].avail_fifo_desc)); - IPADBG("calling client notify callback with priv:%p\n", + IPADBG_LOW("calling client notify callback with priv:%p\n", ipa_ctx->ep[ep_idx].priv); if (ipa_ctx->ep[ep_idx].client_notify) { @@ -3442,7 +3446,7 @@ int ipa2_tx_dp_mul(enum ipa_client_type src, return -EINVAL; } - IPADBG("Received data desc anchor:%p\n", data_desc); + IPADBG_LOW("Received data desc anchor:%p\n", data_desc); spin_lock_bh(&ipa_ctx->wc_memb.ipa_tx_mul_spinlock); @@ -3451,7 +3455,7 @@ int ipa2_tx_dp_mul(enum ipa_client_type src, IPAERR("dest EP does not exist.\n"); goto fail_send; } - IPADBG("ep idx:%d\n", ep_idx); + IPADBG_LOW("ep idx:%d\n", ep_idx); sys = ipa_ctx->ep[ep_idx].sys; if (unlikely(ipa_ctx->ep[ep_idx].valid == 0)) { @@ -3465,7 +3469,7 @@ int ipa2_tx_dp_mul(enum ipa_client_type src, list_for_each_entry(entry, &data_desc->link, link) { num_desc++; } - IPADBG("Number of Data Descriptors:%d", num_desc); + IPADBG_LOW("Number of Data Descriptors:%d", num_desc); if (atomic_read(&sys->ep->avail_fifo_desc) < num_desc) { IPAERR("Insufficient data descriptors available\n"); @@ -3475,7 +3479,7 @@ int ipa2_tx_dp_mul(enum ipa_client_type src, /* Assign callback only for last data descriptor */ cnt = 0; list_for_each_entry(entry, &data_desc->link, link) { - IPADBG("Parsing data desc :%d\n", cnt); + IPADBG_LOW("Parsing data desc :%d\n", cnt); cnt++; ((u8 *)entry->pyld_buffer)[IPA_WLAN_HDR_QMAP_ID_OFFSET] = (u8)sys->ep->cfg.meta.qmap_id; @@ -3484,18 +3488,18 @@ int ipa2_tx_dp_mul(enum ipa_client_type src, desc.type = IPA_DATA_DESC_SKB; desc.user1 = data_desc; desc.user2 = ep_idx; - IPADBG("priv:%p pyld_buf:0x%p pyld_len:%d\n", + IPADBG_LOW("priv:%p pyld_buf:0x%p pyld_len:%d\n", entry->priv, desc.pyld, desc.len); /* In case of last descriptor populate callback */ if (cnt == num_desc) { - IPADBG("data desc:%p\n", data_desc); + IPADBG_LOW("data desc:%p\n", data_desc); desc.callback = ipa_tx_client_rx_notify_release; } else { desc.callback = ipa_tx_client_rx_pkt_status; } - IPADBG("calling ipa_send_one()\n"); + IPADBG_LOW("calling ipa_send_one()\n"); if (ipa_send_one(sys, &desc, true)) { IPAERR("fail to send skb\n"); sys->ep->wstats.rx_pkt_leak += (cnt-1); @@ -3507,7 +3511,7 @@ int ipa2_tx_dp_mul(enum ipa_client_type src, atomic_dec(&sys->ep->avail_fifo_desc); sys->ep->wstats.rx_pkts_rcvd++; - IPADBG("ep=%d fifo desc=%d\n", + IPADBG_LOW("ep=%d fifo desc=%d\n", ep_idx, atomic_read(&sys->ep->avail_fifo_desc)); } diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c b/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c index d6e563b935b6..7ca2314d5839 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_flt.c @@ -209,7 +209,7 @@ static int ipa_generate_flt_hw_rule(enum ipa_ip_type ip, } } - IPADBG("en_rule 0x%x, action=%d, rt_idx=%d, uc=%d, retain_hdr=%d\n", + IPADBG_LOW("en_rule 0x%x, action=%d, rt_idx=%d, uc=%d, retain_hdr=%d\n", en_rule, hdr->u.hdr.action, hdr->u.hdr.rt_tbl_idx, @@ -601,7 +601,7 @@ static void __ipa_reap_sys_flt_tbls(enum ipa_ip_type ip) tbl = &ipa_ctx->glob_flt_tbl[ip]; if (tbl->prev_mem.phys_base) { - IPADBG("reaping glob flt tbl (prev) ip=%d\n", ip); + IPADBG_LOW("reaping glob flt tbl (prev) ip=%d\n", ip); dma_free_coherent(ipa_ctx->pdev, tbl->prev_mem.size, tbl->prev_mem.base, tbl->prev_mem.phys_base); memset(&tbl->prev_mem, 0, sizeof(tbl->prev_mem)); @@ -609,7 +609,7 @@ static void __ipa_reap_sys_flt_tbls(enum ipa_ip_type ip) if (list_empty(&tbl->head_flt_rule_list)) { if (tbl->curr_mem.phys_base) { - IPADBG("reaping glob flt tbl (curr) ip=%d\n", ip); + IPADBG_LOW("reaping glob flt tbl (curr) ip=%d\n", ip); dma_free_coherent(ipa_ctx->pdev, tbl->curr_mem.size, tbl->curr_mem.base, tbl->curr_mem.phys_base); @@ -620,7 +620,8 @@ static void __ipa_reap_sys_flt_tbls(enum ipa_ip_type ip) for (i = 0; i < ipa_ctx->ipa_num_pipes; i++) { tbl = &ipa_ctx->flt_tbl[i][ip]; if (tbl->prev_mem.phys_base) { - IPADBG("reaping flt tbl (prev) pipe=%d ip=%d\n", i, ip); + IPADBG_LOW("reaping flt tbl"); + IPADBG_LOW("(prev) pipe=%d ip=%d\n", i, ip); dma_free_coherent(ipa_ctx->pdev, tbl->prev_mem.size, tbl->prev_mem.base, tbl->prev_mem.phys_base); @@ -629,7 +630,8 @@ static void __ipa_reap_sys_flt_tbls(enum ipa_ip_type ip) if (list_empty(&tbl->head_flt_rule_list)) { if (tbl->curr_mem.phys_base) { - IPADBG("reaping flt tbl (curr) pipe=%d ip=%d\n", + IPADBG_LOW("reaping flt tbl"); + IPADBG_LOW("(curr) pipe=%d ip=%d\n", i, ip); dma_free_coherent(ipa_ctx->pdev, tbl->curr_mem.size, @@ -897,7 +899,7 @@ int __ipa_commit_flt_v2(enum ipa_ip_type ip) for (i = 0; i < 6; i++) { if (ipa_ctx->skip_ep_cfg_shadow[i]) { - IPADBG("skip %d\n", i); + IPADBG_LOW("skip %d\n", i); continue; } @@ -906,7 +908,7 @@ int __ipa_commit_flt_v2(enum ipa_ip_type ip) ipa2_get_ep_mapping(IPA_CLIENT_APPS_CMD_PROD) == i || (ipa2_get_ep_mapping(IPA_CLIENT_APPS_LAN_WAN_PROD) == i && ipa_ctx->modem_cfg_emb_pipe_flt)) { - IPADBG("skip %d\n", i); + IPADBG_LOW("skip %d\n", i); continue; } @@ -932,12 +934,12 @@ int __ipa_commit_flt_v2(enum ipa_ip_type ip) for (i = 11; i < ipa_ctx->ipa_num_pipes; i++) { if (ipa_ctx->skip_ep_cfg_shadow[i]) { - IPADBG("skip %d\n", i); + IPADBG_LOW("skip %d\n", i); continue; } if (ipa2_get_ep_mapping(IPA_CLIENT_APPS_LAN_WAN_PROD) == i && ipa_ctx->modem_cfg_emb_pipe_flt) { - IPADBG("skip %d\n", i); + IPADBG_LOW("skip %d\n", i); continue; } if (ip == IPA_IP_v4) { @@ -1066,7 +1068,7 @@ static int __ipa_add_flt_rule(struct ipa_flt_tbl *tbl, enum ipa_ip_type ip, } *rule_hdl = id; entry->id = id; - IPADBG("add flt rule rule_cnt=%d\n", tbl->rule_cnt); + IPADBG_LOW("add flt rule rule_cnt=%d\n", tbl->rule_cnt); return 0; @@ -1095,7 +1097,7 @@ static int __ipa_del_flt_rule(u32 rule_hdl) entry->tbl->rule_cnt--; if (entry->rt_tbl) entry->rt_tbl->ref_cnt--; - IPADBG("del flt rule rule_cnt=%d\n", entry->tbl->rule_cnt); + IPADBG_LOW("del flt rule rule_cnt=%d\n", entry->tbl->rule_cnt); entry->cookie = 0; kmem_cache_free(ipa_ctx->flt_rule_cache, entry); @@ -1176,7 +1178,7 @@ static int __ipa_add_global_flt_rule(enum ipa_ip_type ip, } tbl = &ipa_ctx->glob_flt_tbl[ip]; - IPADBG("add global flt rule ip=%d\n", ip); + IPADBG_LOW("add global flt rule ip=%d\n", ip); return __ipa_add_flt_rule(tbl, ip, rule, add_rear, rule_hdl); } @@ -1203,7 +1205,7 @@ static int __ipa_add_ep_flt_rule(enum ipa_ip_type ip, enum ipa_client_type ep, IPADBG("ep not connected ep_idx=%d\n", ipa_ep_idx); tbl = &ipa_ctx->flt_tbl[ipa_ep_idx][ip]; - IPADBG("add ep flt rule ip=%d ep=%d\n", ip, ep); + IPADBG_LOW("add ep flt rule ip=%d ep=%d\n", ip, ep); return __ipa_add_flt_rule(tbl, ip, rule, add_rear, rule_hdl); } diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c b/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c index 62e026262663..40d42e1775a9 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_hdr.c @@ -43,7 +43,7 @@ static int ipa_generate_hdr_hw_tbl(struct ipa_mem_buffer *mem) IPAERR("hdr tbl empty\n"); return -EPERM; } - IPADBG("tbl_sz=%d\n", ipa_ctx->hdr_tbl.end); + IPADBG_LOW("tbl_sz=%d\n", ipa_ctx->hdr_tbl.end); mem->base = dma_alloc_coherent(ipa_ctx->pdev, mem->size, &mem->phys_base, GFP_KERNEL); @@ -57,7 +57,7 @@ static int ipa_generate_hdr_hw_tbl(struct ipa_mem_buffer *mem) link) { if (entry->is_hdr_proc_ctx) continue; - IPADBG("hdr of len %d ofst=%d\n", entry->hdr_len, + IPADBG_LOW("hdr of len %d ofst=%d\n", entry->hdr_len, entry->offset_entry->offset); memcpy(mem->base + entry->offset_entry->offset, entry->hdr, entry->hdr_len); @@ -74,7 +74,7 @@ static void ipa_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem, list_for_each_entry(entry, &ipa_ctx->hdr_proc_ctx_tbl.head_proc_ctx_entry_list, link) { - IPADBG("processing type %d ofst=%d\n", + IPADBG_LOW("processing type %d ofst=%d\n", entry->type, entry->offset_entry->offset); if (entry->type == IPA_HDR_PROC_NONE) { struct ipa_hdr_proc_ctx_add_hdr_seq *ctx; @@ -88,7 +88,7 @@ static void ipa_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem, entry->hdr->phys_base : hdr_base_addr + entry->hdr->offset_entry->offset; - IPADBG("header address 0x%x\n", + IPADBG_LOW("header address 0x%x\n", ctx->hdr_add.hdr_addr); ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END; ctx->end.length = 0; @@ -105,7 +105,7 @@ static void ipa_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem, entry->hdr->phys_base : hdr_base_addr + entry->hdr->offset_entry->offset; - IPADBG("header address 0x%x\n", + IPADBG_LOW("header address 0x%x\n", ctx->hdr_add.hdr_addr); ctx->cmd.type = IPA_PROC_CTX_TLV_TYPE_PROC_CMD; ctx->cmd.length = 0; @@ -117,7 +117,7 @@ static void ipa_hdr_proc_ctx_to_hw_format(struct ipa_mem_buffer *mem, ctx->cmd.value = IPA_HDR_UCP_802_3_TO_ETHII; else if (entry->type == IPA_HDR_PROC_802_3_TO_802_3) ctx->cmd.value = IPA_HDR_UCP_802_3_TO_802_3; - IPADBG("command id %d\n", ctx->cmd.value); + IPADBG_LOW("command id %d\n", ctx->cmd.value); ctx->end.type = IPA_PROC_CTX_TLV_TYPE_END; ctx->end.length = 0; ctx->end.value = 0; @@ -144,7 +144,7 @@ static int ipa_generate_hdr_proc_ctx_hw_tbl(u32 hdr_sys_addr, /* make sure table is aligned */ mem->size += IPA_HDR_PROC_CTX_TABLE_ALIGNMENT_BYTE; - IPADBG("tbl_sz=%d\n", ipa_ctx->hdr_proc_ctx_tbl.end); + IPADBG_LOW("tbl_sz=%d\n", ipa_ctx->hdr_proc_ctx_tbl.end); mem->base = dma_alloc_coherent(ipa_ctx->pdev, mem->size, &mem->phys_base, GFP_KERNEL); @@ -487,7 +487,7 @@ static int __ipa_add_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx, int needed_len; int mem_size; - IPADBG("processing type %d hdr_hdl %d\n", + IPADBG_LOW("processing type %d hdr_hdl %d\n", proc_ctx->type, proc_ctx->hdr_hdl); if (!HDR_PROC_TYPE_IS_VALID(proc_ctx->type)) { @@ -566,7 +566,7 @@ static int __ipa_add_hdr_proc_ctx(struct ipa_hdr_proc_ctx_add *proc_ctx, entry->offset_entry = offset; list_add(&entry->link, &htbl->head_proc_ctx_entry_list); htbl->proc_ctx_cnt++; - IPADBG("add proc ctx of sz=%d cnt=%d ofst=%d\n", needed_len, + IPADBG_LOW("add proc ctx of sz=%d cnt=%d ofst=%d\n", needed_len, htbl->proc_ctx_cnt, offset->offset); id = ipa_id_alloc(entry); @@ -692,12 +692,12 @@ static int __ipa_add_hdr(struct ipa_hdr_add *hdr) list_add(&entry->link, &htbl->head_hdr_entry_list); htbl->hdr_cnt++; if (entry->is_hdr_proc_ctx) - IPADBG("add hdr of sz=%d hdr_cnt=%d phys_base=%pa\n", + IPADBG_LOW("add hdr of sz=%d hdr_cnt=%d phys_base=%pa\n", hdr->hdr_len, htbl->hdr_cnt, &entry->phys_base); else - IPADBG("add hdr of sz=%d hdr_cnt=%d ofst=%d\n", + IPADBG_LOW("add hdr of sz=%d hdr_cnt=%d ofst=%d\n", hdr->hdr_len, htbl->hdr_cnt, entry->offset_entry->offset); diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_i.h b/drivers/platform/msm/ipa/ipa_v2/ipa_i.h index fd61435db5e2..6515d29e497a 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_i.h +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_i.h @@ -54,10 +54,37 @@ #define IPA_MAX_STATUS_STAT_NUM 30 +#define IPA_IPC_LOG_PAGES 50 + #define IPADBG(fmt, args...) \ - pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args) + do { \ + pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\ + if (ipa_ctx) { \ + IPA_IPC_LOGGING(ipa_ctx->logbuf, \ + DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa_ctx->logbuf_low, \ + DRV_NAME " %s:%d " fmt, ## args); \ + } \ + } while (0) + +#define IPADBG_LOW(fmt, args...) \ + do { \ + pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\ + if (ipa_ctx) \ + IPA_IPC_LOGGING(ipa_ctx->logbuf_low, \ + DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + #define IPAERR(fmt, args...) \ - pr_err(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args) + do { \ + pr_err(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\ + if (ipa_ctx) { \ + IPA_IPC_LOGGING(ipa_ctx->logbuf, \ + DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa_ctx->logbuf_low, \ + DRV_NAME " %s:%d " fmt, ## args); \ + } \ + } while (0) #define WLAN_AMPDU_TX_EP 15 #define WLAN_PROD_TX_EP 19 @@ -1003,6 +1030,8 @@ struct ipacm_client_info { * @use_ipa_teth_bridge: use tethering bridge driver * @ipa_bam_remote_mode: ipa bam is in remote mode * @modem_cfg_emb_pipe_flt: modem configure embedded pipe filtering rules + * @logbuf: ipc log buffer for high priority messages + * @logbuf_low: ipc log buffer for low priority messages * @ipa_wdi2: using wdi-2.0 * @ipa_bus_hdl: msm driver handle for the data path bus * @ctrl: holds the core specific operations based on @@ -1095,6 +1124,8 @@ struct ipa_context { /* featurize if memory footprint becomes a concern */ struct ipa_stats stats; void *smem_pipe_mem; + void *logbuf; + void *logbuf_low; u32 ipa_bus_hdl; struct ipa_controller *ctrl; struct idr ipa_idr; diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_interrupts.c b/drivers/platform/msm/ipa/ipa_v2/ipa_interrupts.c index 17f577ab6c4c..c17dee939f1c 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_interrupts.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_interrupts.c @@ -103,11 +103,12 @@ static int handle_interrupt(int irq_num, bool isr_context) switch (interrupt_info.interrupt) { case IPA_TX_SUSPEND_IRQ: + IPADBG_LOW("processing TX_SUSPEND interrupt work-around\n"); suspend_data = ipa_read_reg(ipa_ctx->mmio, IPA_IRQ_SUSPEND_INFO_EE_n_ADDR(ipa_ee)); if (!is_valid_ep(suspend_data)) return 0; - + IPADBG_LOW("get interrupt %d\n", suspend_data); suspend_interrupt_data = kzalloc(sizeof(*suspend_interrupt_data), GFP_ATOMIC); if (!suspend_interrupt_data) { @@ -167,9 +168,11 @@ static void ipa_process_interrupts(bool isr_context) u32 i = 0; u32 en; bool uc_irq; - en = ipa_read_reg(ipa_ctx->mmio, IPA_IRQ_EN_EE_n_ADDR(ipa_ee)); reg = ipa_read_reg(ipa_ctx->mmio, IPA_IRQ_STTS_EE_n_ADDR(ipa_ee)); + IPADBG_LOW( + "ISR enter\n isr_ctx = %d EN reg = 0x%x STTS reg = 0x%x\n", + isr_context, en, reg); while (en & reg) { bmsk = 1; for (i = 0; i < IPA_IRQ_NUM_MAX; i++) { @@ -206,21 +209,22 @@ static void ipa_process_interrupts(bool isr_context) reg = ipa_read_reg(ipa_ctx->mmio, IPA_IRQ_STTS_EE_n_ADDR(ipa_ee)); } + IPADBG_LOW("Exit\n"); } static void ipa_interrupt_defer(struct work_struct *work) { - IPADBG("processing interrupts in wq\n"); + IPADBG_LOW("processing interrupts in wq\n"); IPA_ACTIVE_CLIENTS_INC_SIMPLE(); ipa_process_interrupts(false); IPA_ACTIVE_CLIENTS_DEC_SIMPLE(); - IPADBG("Done\n"); + IPADBG_LOW("Done\n"); } static irqreturn_t ipa_isr(int irq, void *ctxt) { unsigned long flags; - + IPADBG_LOW("Enter\n"); /* defer interrupt handling in case IPA is not clocked on */ if (ipa_active_clients_trylock(&flags) == 0) { IPADBG("defer interrupt processing\n"); @@ -235,7 +239,7 @@ static irqreturn_t ipa_isr(int irq, void *ctxt) } ipa_process_interrupts(true); - + IPADBG_LOW("Exit\n"); bail: ipa_active_clients_trylock_unlock(&flags); return IRQ_HANDLED; @@ -260,7 +264,7 @@ int ipa2_add_interrupt_handler(enum ipa_irq_type interrupt, u32 bmsk; int irq_num; - IPADBG("in ipa2_add_interrupt_handler\n"); + IPADBG_LOW("in ipa2_add_interrupt_handler\n"); if (interrupt < IPA_BAD_SNOC_ACCESS_IRQ || interrupt >= IPA_IRQ_MAX) { IPAERR("invalid interrupt number %d\n", interrupt); @@ -284,7 +288,7 @@ int ipa2_add_interrupt_handler(enum ipa_irq_type interrupt, bmsk = 1 << irq_num; val |= bmsk; ipa_write_reg(ipa_ctx->mmio, IPA_IRQ_EN_EE_n_ADDR(ipa_ee), val); - IPADBG("wrote IPA_IRQ_EN_EE_n_ADDR register. reg = %d\n", val); + IPADBG_LOW("wrote IPA_IRQ_EN_EE_n_ADDR register. reg = %d\n", val); return 0; } diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c b/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c index f5afb4b0141c..dfc3e06f452b 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_intf.c @@ -532,9 +532,8 @@ ssize_t ipa_read(struct file *filp, char __user *buf, size_t count, list_del(&msg->link); } - IPADBG("msg=%p\n", msg); - if (msg) { + IPADBG("msg=%pK\n", msg); locked = 0; mutex_unlock(&ipa_ctx->msg_lock); if (copy_to_user(buf, &msg->meta, @@ -558,6 +557,7 @@ ssize_t ipa_read(struct file *filp, char __user *buf, size_t count, IPA_STATS_INC_CNT( ipa_ctx->stats.msg_r[msg->meta.msg_type]); kfree(msg); + msg = NULL; } ret = -EAGAIN; diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_mhi.c b/drivers/platform/msm/ipa/ipa_v2/ipa_mhi.c index e8f25c9c23d3..0ab4a6882a63 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_mhi.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_mhi.c @@ -20,16 +20,40 @@ #include "ipa_i.h" #include "ipa_qmi_service.h" -#define IPA_MHI_DRV_NAME +#define IPA_MHI_DRV_NAME "ipa_mhi" #define IPA_MHI_DBG(fmt, args...) \ - pr_debug(IPA_MHI_DRV_NAME " %s:%d " fmt, \ - __func__, __LINE__, ## args) + do { \ + pr_debug(IPA_MHI_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPA_MHI_DBG_LOW(fmt, args...) \ + do { \ + pr_debug(IPA_MHI_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + #define IPA_MHI_ERR(fmt, args...) \ - pr_err(IPA_MHI_DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args) + do { \ + pr_err(IPA_MHI_DRV_NAME " %s:%d " fmt, \ + __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \ + IPA_MHI_DRV_NAME " %s:%d " fmt, ## args); \ + } while (0) + #define IPA_MHI_FUNC_ENTRY() \ - IPA_MHI_DBG("ENTRY\n") + IPA_MHI_DBG_LOW("ENTRY\n") #define IPA_MHI_FUNC_EXIT() \ - IPA_MHI_DBG("EXIT\n") + IPA_MHI_DBG_LOW("EXIT\n") + bool ipa2_mhi_sps_channel_empty(enum ipa_client_type client) { diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c b/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c index 3f20941155a5..0f5d7b7719b5 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.c @@ -310,7 +310,7 @@ static void ipa_a5_svc_recv_msg(struct work_struct *work) int rc; do { - IPAWANDBG("Notified about a Receive Event"); + IPAWANDBG_LOW("Notified about a Receive Event"); rc = qmi_recv_msg(ipa_svc_handle); } while (rc == 0); if (rc != -ENOMSG) @@ -384,7 +384,7 @@ static int ipa_check_qmi_response(int rc, req_id, result, error); return result; } - IPAWANDBG("Received %s successfully\n", resp_type); + IPAWANDBG_LOW("Received %s successfully\n", resp_type); return 0; } @@ -711,7 +711,7 @@ static void ipa_q6_clnt_recv_msg(struct work_struct *work) int rc; do { - IPAWANDBG("Notified about a Receive Event"); + IPAWANDBG_LOW("Notified about a Receive Event"); rc = qmi_recv_msg(ipa_q6_clnt); } while (rc == 0); if (rc != -ENOMSG) @@ -723,7 +723,7 @@ static void ipa_q6_clnt_notify(struct qmi_handle *handle, { switch (event) { case QMI_RECV_MSG: - IPAWANDBG("client qmi recv message called"); + IPAWANDBG_LOW("client qmi recv message called"); if (!atomic_read(&workqueues_stopped)) queue_delayed_work(ipa_clnt_resp_workqueue, &work_recv_msg_client, 0); @@ -1094,7 +1094,7 @@ int ipa_qmi_get_data_stats(struct ipa_get_data_stats_req_msg_v01 *req, resp_desc.msg_id = QMI_IPA_GET_DATA_STATS_RESP_V01; resp_desc.ei_array = ipa_get_data_stats_resp_msg_data_v01_ei; - IPAWANDBG("Sending QMI_IPA_GET_DATA_STATS_REQ_V01\n"); + IPAWANDBG_LOW("Sending QMI_IPA_GET_DATA_STATS_REQ_V01\n"); if (unlikely(!ipa_q6_clnt)) return -ETIMEDOUT; rc = qmi_send_req_wait(ipa_q6_clnt, &req_desc, req, @@ -1103,7 +1103,7 @@ int ipa_qmi_get_data_stats(struct ipa_get_data_stats_req_msg_v01 *req, sizeof(struct ipa_get_data_stats_resp_msg_v01), QMI_SEND_STATS_REQ_TIMEOUT_MS); - IPAWANDBG("QMI_IPA_GET_DATA_STATS_RESP_V01 received\n"); + IPAWANDBG_LOW("QMI_IPA_GET_DATA_STATS_RESP_V01 received\n"); return ipa_check_qmi_response(rc, QMI_IPA_GET_DATA_STATS_REQ_V01, resp->resp.result, @@ -1124,7 +1124,7 @@ int ipa_qmi_get_network_stats(struct ipa_get_apn_data_stats_req_msg_v01 *req, resp_desc.msg_id = QMI_IPA_GET_APN_DATA_STATS_RESP_V01; resp_desc.ei_array = ipa_get_apn_data_stats_resp_msg_data_v01_ei; - IPAWANDBG("Sending QMI_IPA_GET_APN_DATA_STATS_REQ_V01\n"); + IPAWANDBG_LOW("Sending QMI_IPA_GET_APN_DATA_STATS_REQ_V01\n"); if (unlikely(!ipa_q6_clnt)) return -ETIMEDOUT; rc = qmi_send_req_wait(ipa_q6_clnt, &req_desc, req, @@ -1133,7 +1133,7 @@ int ipa_qmi_get_network_stats(struct ipa_get_apn_data_stats_req_msg_v01 *req, sizeof(struct ipa_get_apn_data_stats_resp_msg_v01), QMI_SEND_STATS_REQ_TIMEOUT_MS); - IPAWANDBG("QMI_IPA_GET_APN_DATA_STATS_RESP_V01 received\n"); + IPAWANDBG_LOW("QMI_IPA_GET_APN_DATA_STATS_RESP_V01 received\n"); return ipa_check_qmi_response(rc, QMI_IPA_GET_APN_DATA_STATS_REQ_V01, resp->resp.result, @@ -1157,7 +1157,7 @@ int ipa_qmi_set_data_quota(struct ipa_set_data_usage_quota_req_msg_v01 *req) resp_desc.msg_id = QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01; resp_desc.ei_array = ipa_set_data_usage_quota_resp_msg_data_v01_ei; - IPAWANDBG("Sending QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01\n"); + IPAWANDBG_LOW("Sending QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01\n"); if (unlikely(!ipa_q6_clnt)) return -ETIMEDOUT; rc = qmi_send_req_wait(ipa_q6_clnt, &req_desc, req, @@ -1165,7 +1165,7 @@ int ipa_qmi_set_data_quota(struct ipa_set_data_usage_quota_req_msg_v01 *req) &resp_desc, &resp, sizeof(resp), QMI_SEND_STATS_REQ_TIMEOUT_MS); - IPAWANDBG("QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01 received\n"); + IPAWANDBG_LOW("QMI_IPA_SET_DATA_USAGE_QUOTA_RESP_V01 received\n"); return ipa_check_qmi_response(rc, QMI_IPA_SET_DATA_USAGE_QUOTA_REQ_V01, resp.resp.result, @@ -1192,14 +1192,14 @@ int ipa_qmi_stop_data_qouta(void) resp_desc.msg_id = QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01; resp_desc.ei_array = ipa_stop_data_usage_quota_resp_msg_data_v01_ei; - IPAWANDBG("Sending QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01\n"); + IPAWANDBG_LOW("Sending QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01\n"); if (unlikely(!ipa_q6_clnt)) return -ETIMEDOUT; rc = qmi_send_req_wait(ipa_q6_clnt, &req_desc, &req, sizeof(req), &resp_desc, &resp, sizeof(resp), QMI_SEND_STATS_REQ_TIMEOUT_MS); - IPAWANDBG("QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01 received\n"); + IPAWANDBG_LOW("QMI_IPA_STOP_DATA_USAGE_QUOTA_RESP_V01 received\n"); return ipa_check_qmi_response(rc, QMI_IPA_STOP_DATA_USAGE_QUOTA_REQ_V01, resp.resp.result, diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.h b/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.h index 7793fc05a339..c7c6234aae0e 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.h +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_qmi_service.h @@ -31,9 +31,39 @@ #define SUBSYS_MODEM "modem" #define IPAWANDBG(fmt, args...) \ - pr_debug(DEV_NAME " %s:%d " fmt, __func__, __LINE__, ## args) + do { \ + pr_debug(DEV_NAME " %s:%d " fmt, __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPAWANDBG_LOW(fmt, args...) \ + do { \ + pr_debug(DEV_NAME " %s:%d " fmt, __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + } while (0) + #define IPAWANERR(fmt, args...) \ - pr_err(DEV_NAME " %s:%d " fmt, __func__, __LINE__, ## args) + do { \ + pr_err(DEV_NAME " %s:%d " fmt, __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + } while (0) + +#define IPAWANINFO(fmt, args...) \ + do { \ + pr_info(DEV_NAME " %s:%d " fmt, __func__, __LINE__, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + IPA_IPC_LOGGING(ipa_get_ipc_logbuf_low(), \ + DEV_NAME " %s:%d " fmt, ## args); \ + } while (0) + extern struct ipa_qmi_context *ipa_qmi_ctx; extern struct mutex ipa_qmi_lock; diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c b/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c index 5e7a5383334c..069c5cbcf4f3 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_rt.c @@ -87,7 +87,7 @@ int __ipa_generate_rt_hw_rule_v2(enum ipa_ip_type ip, return -EPERM; } - IPADBG("en_rule 0x%x\n", en_rule); + IPADBG_LOW("en_rule 0x%x\n", en_rule); rule_hdr->u.hdr.en_rule = en_rule; ipa_write_32(rule_hdr->u.word, (u8 *)rule_hdr); @@ -490,7 +490,9 @@ static void __ipa_reap_sys_rt_tbls(enum ipa_ip_type ip) set = &ipa_ctx->rt_tbl_set[ip]; list_for_each_entry(tbl, &set->head_rt_tbl_list, link) { if (tbl->prev_mem.phys_base) { - IPADBG("reaping rt tbl name=%s ip=%d\n", tbl->name, ip); + IPADBG_LOW("reaping rt"); + IPADBG_LOW("tbl name=%s ip=%d\n", + tbl->name, ip); dma_free_coherent(ipa_ctx->pdev, tbl->prev_mem.size, tbl->prev_mem.base, tbl->prev_mem.phys_base); @@ -503,8 +505,9 @@ static void __ipa_reap_sys_rt_tbls(enum ipa_ip_type ip) list_del(&tbl->link); WARN_ON(tbl->prev_mem.phys_base != 0); if (tbl->curr_mem.phys_base) { - IPADBG("reaping sys rt tbl name=%s ip=%d\n", tbl->name, - ip); + IPADBG_LOW("reaping sys"); + IPADBG_LOW("rt tbl name=%s ip=%d\n", + tbl->name, ip); dma_free_coherent(ipa_ctx->pdev, tbl->curr_mem.size, tbl->curr_mem.base, tbl->curr_mem.phys_base); @@ -931,7 +934,7 @@ static int __ipa_del_rt_tbl(struct ipa_rt_tbl *entry) list_del(&entry->link); clear_bit(entry->idx, &ipa_ctx->rt_idx_bitmap[ip]); entry->set->tbl_cnt--; - IPADBG("del rt tbl_idx=%d tbl_cnt=%d\n", entry->idx, + IPADBG_LOW("del rt tbl_idx=%d tbl_cnt=%d\n", entry->idx, entry->set->tbl_cnt); kmem_cache_free(ipa_ctx->rt_tbl_cache, entry); } else { @@ -939,7 +942,7 @@ static int __ipa_del_rt_tbl(struct ipa_rt_tbl *entry) &ipa_ctx->reap_rt_tbl_set[ip].head_rt_tbl_list); clear_bit(entry->idx, &ipa_ctx->rt_idx_bitmap[ip]); entry->set->tbl_cnt--; - IPADBG("del sys rt tbl_idx=%d tbl_cnt=%d\n", entry->idx, + IPADBG_LOW("del sys rt tbl_idx=%d tbl_cnt=%d\n", entry->idx, entry->set->tbl_cnt); } @@ -1019,7 +1022,8 @@ static int __ipa_add_rt_rule(enum ipa_ip_type ip, const char *name, WARN_ON(1); goto ipa_insert_failed; } - IPADBG("add rt rule tbl_idx=%d rule_cnt=%d\n", tbl->idx, tbl->rule_cnt); + IPADBG_LOW("add rt rule tbl_idx=%d", tbl->idx); + IPADBG_LOW("rule_cnt=%d\n", tbl->rule_cnt); *rule_hdl = id; entry->id = id; @@ -1103,7 +1107,7 @@ int __ipa_del_rt_rule(u32 rule_hdl) __ipa_release_hdr_proc_ctx(entry->proc_ctx->id); list_del(&entry->link); entry->tbl->rule_cnt--; - IPADBG("del rt rule tbl_idx=%d rule_cnt=%d\n", entry->tbl->idx, + IPADBG_LOW("del rt rule tbl_idx=%d rule_cnt=%d\n", entry->tbl->idx, entry->tbl->rule_cnt); if (entry->tbl->rule_cnt == 0 && entry->tbl->ref_cnt == 0) { if (__ipa_del_rt_tbl(entry->tbl)) diff --git a/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c index 8968d5d4509f..87d84b43c829 100644 --- a/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c +++ b/drivers/platform/msm/ipa/ipa_v2/ipa_utils.c @@ -1675,6 +1675,7 @@ int ipa_generate_hw_rule(enum ipa_ip_type ip, * OFFSET_MEQ32_0 with mask of 0 and val of 0 and offset 0 */ if (attrib->attrib_mask == 0) { + IPADBG_LOW("building default rule\n"); if (ipa_ofst_meq32[ofst_meq32] == -1) { IPAERR("ran out of meq32 eq\n"); return -EPERM; @@ -4913,13 +4914,17 @@ static int ipa2_stop_gsi_channel(u32 clnt_hdl) static void *ipa2_get_ipc_logbuf(void) { - /* no support for IPC logging in IPAv2 */ + if (ipa_ctx) + return ipa_ctx->logbuf; + return NULL; } static void *ipa2_get_ipc_logbuf_low(void) { - /* no support for IPC logging in IPAv2 */ + if (ipa_ctx) + return ipa_ctx->logbuf_low; + return NULL; } diff --git a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c index c2e43a62ab69..b7583b990a84 100644 --- a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c +++ b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa.c @@ -1052,7 +1052,7 @@ static int ipa_wwan_xmit(struct sk_buff *skb, struct net_device *dev) struct ipa_tx_meta meta; if (skb->protocol != htons(ETH_P_MAP)) { - IPAWANDBG + IPAWANDBG_LOW ("SW filtering out none QMAP packet received from %s", current->comm); dev_kfree_skb_any(skb); @@ -1077,7 +1077,8 @@ static int ipa_wwan_xmit(struct sk_buff *skb, struct net_device *dev) if (atomic_read(&wwan_ptr->outstanding_pkts) >= wwan_ptr->outstanding_high) { if (!qmap_check) { - IPAWANDBG("pending(%d)/(%d)- stop(%d), qmap_chk(%d)\n", + IPAWANDBG_LOW + ("pending(%d)/(%d)- stop(%d), qmap_chk(%d)\n", atomic_read(&wwan_ptr->outstanding_pkts), wwan_ptr->outstanding_high, netif_queue_stopped(dev), @@ -1171,7 +1172,8 @@ static void apps_ipa_tx_complete_notify(void *priv, netif_queue_stopped(wwan_ptr->net) && atomic_read(&wwan_ptr->outstanding_pkts) < (wwan_ptr->outstanding_low)) { - IPAWANDBG("Outstanding low (%d) - wake up queue\n", + IPAWANDBG_LOW + ("Outstanding low (%d) - wake up queue\n", wwan_ptr->outstanding_low); netif_wake_queue(wwan_ptr->net); } @@ -1201,7 +1203,7 @@ static void apps_ipa_packet_receive_notify(void *priv, int result; unsigned int packet_len = skb->len; - IPAWANDBG("Rx packet was received"); + IPAWANDBG_LOW("Rx packet was received"); skb->dev = ipa_netdevs[0]; skb->protocol = htons(ETH_P_MAP); @@ -1763,10 +1765,10 @@ static void q6_rm_notify_cb(void *user_data, { switch (event) { case IPA_RM_RESOURCE_GRANTED: - IPAWANDBG("%s: Q6_PROD GRANTED CB\n", __func__); + IPAWANDBG_LOW("%s: Q6_PROD GRANTED CB\n", __func__); break; case IPA_RM_RESOURCE_RELEASED: - IPAWANDBG("%s: Q6_PROD RELEASED CB\n", __func__); + IPAWANDBG_LOW("%s: Q6_PROD RELEASED CB\n", __func__); break; default: return; @@ -1873,7 +1875,7 @@ static void wake_tx_queue(struct work_struct *work) */ static void ipa_rm_resource_granted(void *dev) { - IPAWANDBG("Resource Granted - starting queue\n"); + IPAWANDBG_LOW("Resource Granted - starting queue\n"); schedule_work(&ipa_tx_wakequeue_work); } @@ -2246,7 +2248,7 @@ static int rmnet_ipa_ap_suspend(struct device *dev) struct net_device *netdev = ipa_netdevs[0]; struct wwan_private *wwan_ptr = netdev_priv(netdev); - IPAWANDBG("Enter...\n"); + IPAWANDBG_LOW("Enter...\n"); /* Do not allow A7 to suspend in case there are oustanding packets */ if (atomic_read(&wwan_ptr->outstanding_pkts) != 0) { IPAWANDBG("Outstanding packets, postponing AP suspend.\n"); @@ -2257,7 +2259,7 @@ static int rmnet_ipa_ap_suspend(struct device *dev) netif_tx_lock_bh(netdev); ipa_rm_release_resource(IPA_RM_RESOURCE_WWAN_0_PROD); netif_tx_unlock_bh(netdev); - IPAWANDBG("Exit\n"); + IPAWANDBG_LOW("Exit\n"); return 0; } @@ -2276,9 +2278,9 @@ static int rmnet_ipa_ap_resume(struct device *dev) { struct net_device *netdev = ipa_netdevs[0]; - IPAWANDBG("Enter...\n"); + IPAWANDBG_LOW("Enter...\n"); netif_wake_queue(netdev); - IPAWANDBG("Exit\n"); + IPAWANDBG_LOW("Exit\n"); return 0; } @@ -2355,6 +2357,7 @@ static int ssr_notifier_cb(struct notifier_block *this, return NOTIFY_DONE; } } + IPAWANDBG_LOW("Exit\n"); return NOTIFY_DONE; } @@ -2573,7 +2576,7 @@ int rmnet_ipa_set_data_quota(struct wan_ioctl_set_data_quota *data) * * Return codes: * 0: Success - * -EFAULT: Invalid interface name provided + * -EFAULT: Invalid src/dst pipes provided * other: See ipa_qmi_set_data_quota */ int rmnet_ipa_set_tether_client_pipe( @@ -2581,6 +2584,23 @@ int rmnet_ipa_set_tether_client_pipe( { int number, i; + /* error checking if ul_src_pipe_len valid or not*/ + if (data->ul_src_pipe_len > QMI_IPA_MAX_PIPES_V01 || + data->ul_src_pipe_len < 0) { + IPAWANERR("UL src pipes %d exceeding max %d\n", + data->ul_src_pipe_len, + QMI_IPA_MAX_PIPES_V01); + return -EFAULT; + } + /* error checking if dl_dst_pipe_len valid or not*/ + if (data->dl_dst_pipe_len > QMI_IPA_MAX_PIPES_V01 || + data->dl_dst_pipe_len < 0) { + IPAWANERR("DL dst pipes %d exceeding max %d\n", + data->dl_dst_pipe_len, + QMI_IPA_MAX_PIPES_V01); + return -EFAULT; + } + IPAWANDBG("client %d, UL %d, DL %d, reset %d\n", data->ipa_client, data->ul_src_pipe_len, @@ -2641,7 +2661,7 @@ int rmnet_ipa_query_tethering_stats(struct wan_ioctl_query_tether_stats *data, IPAWANERR("reset the pipe stats\n"); } else { /* print tethered-client enum */ - IPAWANDBG("Tethered-client enum(%d)\n", data->ipa_client); + IPAWANDBG_LOW("Tethered-client enum(%d)\n", data->ipa_client); } rc = ipa_qmi_get_data_stats(req, resp); @@ -2659,10 +2679,11 @@ int rmnet_ipa_query_tethering_stats(struct wan_ioctl_query_tether_stats *data, if (resp->dl_dst_pipe_stats_list_valid) { for (pipe_len = 0; pipe_len < resp->dl_dst_pipe_stats_list_len; pipe_len++) { - IPAWANDBG("Check entry(%d) dl_dst_pipe(%d)\n", + IPAWANDBG_LOW("Check entry(%d) dl_dst_pipe(%d)\n", pipe_len, resp->dl_dst_pipe_stats_list [pipe_len].pipe_index); - IPAWANDBG("dl_p_v4(%lu)v6(%lu) dl_b_v4(%lu)v6(%lu)\n", + IPAWANDBG_LOW + ("dl_p_v4(%lu)v6(%lu) dl_b_v4(%lu)v6(%lu)\n", (unsigned long int) resp-> dl_dst_pipe_stats_list[pipe_len]. num_ipv4_packets, @@ -2698,7 +2719,7 @@ int rmnet_ipa_query_tethering_stats(struct wan_ioctl_query_tether_stats *data, } } } - IPAWANDBG("v4_rx_p(%lu) v6_rx_p(%lu) v4_rx_b(%lu) v6_rx_b(%lu)\n", + IPAWANDBG_LOW("v4_rx_p(%lu) v6_rx_p(%lu) v4_rx_b(%lu) v6_rx_b(%lu)\n", (unsigned long int) data->ipv4_rx_packets, (unsigned long int) data->ipv6_rx_packets, (unsigned long int) data->ipv4_rx_bytes, @@ -2707,11 +2728,12 @@ int rmnet_ipa_query_tethering_stats(struct wan_ioctl_query_tether_stats *data, if (resp->ul_src_pipe_stats_list_valid) { for (pipe_len = 0; pipe_len < resp->ul_src_pipe_stats_list_len; pipe_len++) { - IPAWANDBG("Check entry(%d) ul_dst_pipe(%d)\n", + IPAWANDBG_LOW("Check entry(%d) ul_dst_pipe(%d)\n", pipe_len, resp->ul_src_pipe_stats_list[pipe_len]. pipe_index); - IPAWANDBG("ul_p_v4(%lu)v6(%lu)ul_b_v4(%lu)v6(%lu)\n", + IPAWANDBG_LOW + ("ul_p_v4(%lu)v6(%lu)ul_b_v4(%lu)v6(%lu)\n", (unsigned long int) resp-> ul_src_pipe_stats_list[pipe_len]. num_ipv4_packets, @@ -2747,7 +2769,7 @@ int rmnet_ipa_query_tethering_stats(struct wan_ioctl_query_tether_stats *data, } } } - IPAWANDBG("tx_p_v4(%lu)v6(%lu)tx_b_v4(%lu) v6(%lu)\n", + IPAWANDBG_LOW("tx_p_v4(%lu)v6(%lu)tx_b_v4(%lu) v6(%lu)\n", (unsigned long int) data->ipv4_tx_packets, (unsigned long int) data->ipv6_tx_packets, (unsigned long int) data->ipv4_tx_bytes, diff --git a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa_fd_ioctl.c b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa_fd_ioctl.c index 811dba4ab756..6a92c5fb7d52 100644 --- a/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa_fd_ioctl.c +++ b/drivers/platform/msm/ipa/ipa_v2/rmnet_ipa_fd_ioctl.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -145,8 +145,7 @@ static long wan_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) break; case WAN_IOC_POLL_TETHERING_STATS: - IPAWANDBG("device %s got WAN_IOCTL_POLL_TETHERING_STATS :>>>\n", - DRIVER_NAME); + IPAWANDBG_LOW("got WAN_IOCTL_POLL_TETHERING_STATS :>>>\n"); pyld_sz = sizeof(struct wan_ioctl_poll_tethering_stats); param = kzalloc(pyld_sz, GFP_KERNEL); if (!param) { @@ -170,8 +169,7 @@ static long wan_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) break; case WAN_IOC_SET_DATA_QUOTA: - IPAWANDBG("device %s got WAN_IOCTL_SET_DATA_QUOTA :>>>\n", - DRIVER_NAME); + IPAWANDBG_LOW("got WAN_IOCTL_SET_DATA_QUOTA :>>>\n"); pyld_sz = sizeof(struct wan_ioctl_set_data_quota); param = kzalloc(pyld_sz, GFP_KERNEL); if (!param) { @@ -195,8 +193,7 @@ static long wan_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) break; case WAN_IOC_SET_TETHER_CLIENT_PIPE: - IPAWANDBG("device %s got WAN_IOC_SET_TETHER_CLIENT_PIPE :>>>\n", - DRIVER_NAME); + IPAWANDBG_LOW("got WAN_IOC_SET_TETHER_CLIENT_PIPE :>>>\n"); pyld_sz = sizeof(struct wan_ioctl_set_tether_client_pipe); param = kzalloc(pyld_sz, GFP_KERNEL); if (!param) { @@ -216,8 +213,7 @@ static long wan_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) break; case WAN_IOC_QUERY_TETHER_STATS: - IPAWANDBG("device %s got WAN_IOC_QUERY_TETHER_STATS :>>>\n", - DRIVER_NAME); + IPAWANDBG_LOW("got WAN_IOC_QUERY_TETHER_STATS :>>>\n"); pyld_sz = sizeof(struct wan_ioctl_query_tether_stats); param = kzalloc(pyld_sz, GFP_KERNEL); if (!param) { @@ -243,8 +239,7 @@ static long wan_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) break; case WAN_IOC_RESET_TETHER_STATS: - IPAWANDBG("device %s got WAN_IOC_RESET_TETHER_STATS :>>>\n", - DRIVER_NAME); + IPAWANDBG_LOW("got WAN_IOC_RESET_TETHER_STATS :>>>\n"); pyld_sz = sizeof(struct wan_ioctl_reset_tether_stats); param = kzalloc(pyld_sz, GFP_KERNEL); if (!param) { diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c index 2101147e7d24..3d276b0f535d 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c @@ -2301,13 +2301,17 @@ void ipa3_q6_post_shutdown_cleanup(void) int client_idx; IPADBG_LOW("ENTER\n"); - IPA_ACTIVE_CLIENTS_INC_SIMPLE(); if (!ipa3_ctx->uc_ctx.uc_loaded) { IPAERR("uC is not loaded. Skipping\n"); return; } + IPA_ACTIVE_CLIENTS_INC_SIMPLE(); + + /* Handle the issue where SUSPEND was removed for some reason */ + ipa3_q6_avoid_holb(); + for (client_idx = 0; client_idx < IPA_CLIENT_MAX; client_idx++) if (IPA_CLIENT_IS_Q6_PROD(client_idx)) { if (ipa3_uc_is_gsi_channel_empty(client_idx)) { @@ -3612,6 +3616,7 @@ static int ipa3_apps_cons_request_resource(void) static void ipa3_sps_release_resource(struct work_struct *work) { + mutex_lock(&ipa3_ctx->transport_pm.transport_pm_mutex); /* check whether still need to decrease client usage */ if (atomic_read(&ipa3_ctx->transport_pm.dec_clients)) { if (atomic_read(&ipa3_ctx->transport_pm.eot_activity)) { @@ -3623,6 +3628,7 @@ static void ipa3_sps_release_resource(struct work_struct *work) } } atomic_set(&ipa3_ctx->transport_pm.eot_activity, 0); + mutex_unlock(&ipa3_ctx->transport_pm.transport_pm_mutex); } int ipa3_create_apps_resource(void) @@ -4402,6 +4408,8 @@ static int ipa3_pre_init(const struct ipa3_plat_drv_res *resource_p, goto fail_create_transport_wq; } + /* Initialize the SPS PM lock. */ + mutex_init(&ipa3_ctx->transport_pm.transport_pm_mutex); spin_lock_init(&ipa3_ctx->transport_pm.lock); ipa3_ctx->transport_pm.res_granted = false; ipa3_ctx->transport_pm.res_rel_in_prog = false; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c index 26bd180624f1..00bfbf84c75a 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_client.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_client.c @@ -1474,7 +1474,7 @@ static int ipa3_is_xdci_channel_empty(struct ipa3_ep_context *ep, return 0; } -static int ipa3_enable_force_clear(u32 request_id, bool throttle_source, +int ipa3_enable_force_clear(u32 request_id, bool throttle_source, u32 source_pipe_bitmask) { struct ipa_enable_force_clear_datapath_req_msg_v01 req; @@ -1497,7 +1497,7 @@ static int ipa3_enable_force_clear(u32 request_id, bool throttle_source, return 0; } -static int ipa3_disable_force_clear(u32 request_id) +int ipa3_disable_force_clear(u32 request_id) { struct ipa_disable_force_clear_datapath_req_msg_v01 req; int result; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h index b4f447f56d1c..fe7c88a25374 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_i.h @@ -974,6 +974,7 @@ struct ipa3_uc_wdi_ctx { * @lock: lock for ensuring atomic operations * @res_granted: true if SPS requested IPA resource and IPA granted it * @res_rel_in_prog: true if releasing IPA resource is in progress + * @transport_pm_mutex: Mutex to protect the transport_pm functionality. */ struct ipa3_transport_pm { spinlock_t lock; @@ -981,6 +982,7 @@ struct ipa3_transport_pm { bool res_rel_in_prog; atomic_t dec_clients; atomic_t eot_activity; + struct mutex transport_pm_mutex; }; /** @@ -1917,6 +1919,9 @@ int ipa3_alloc_rule_id(struct idr *rule_ids); int ipa3_id_alloc(void *ptr); void *ipa3_id_find(u32 id); void ipa3_id_remove(u32 id); +int ipa3_enable_force_clear(u32 request_id, bool throttle_source, + u32 source_pipe_bitmask); +int ipa3_disable_force_clear(u32 request_id); int ipa3_set_required_perf_profile(enum ipa_voltage_level floor_voltage, u32 bandwidth_mbps); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c index 8cb6935cd720..41bb8651f69c 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c @@ -1370,6 +1370,7 @@ int ipa3_disable_wdi_pipe(u32 clnt_hdl) u32 prod_hdl; int i; u32 rx_door_bell_value; + u32 source_pipe_bitmask = 0; if (clnt_hdl >= ipa3_ctx->ipa_num_pipes || ipa3_ctx->ep[clnt_hdl].valid == 0) { @@ -1405,6 +1406,17 @@ int ipa3_disable_wdi_pipe(u32 clnt_hdl) * holb on IPA Producer pipe */ if (IPA_CLIENT_IS_PROD(ep->client)) { + /* enable force clear */ + IPADBG("Stopping PROD channel - hdl=%d clnt=%d\n", + clnt_hdl, ep->client); + source_pipe_bitmask = 1 << + ipa3_get_ep_mapping(ep->client); + result = ipa3_enable_force_clear(clnt_hdl, false, + source_pipe_bitmask); + if (result) + goto uc_timeout; + + /* remove delay on wlan-prod pipe*/ memset(&ep_cfg_ctrl, 0 , sizeof(struct ipa_ep_cfg_ctrl)); ipa3_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); @@ -1437,7 +1449,7 @@ int ipa3_disable_wdi_pipe(u32 clnt_hdl) rx_door_bell_value, *ipa3_ctx->uc_ctx.rdy_ring_rp_va, *ipa3_ctx->uc_ctx.rdy_comp_ring_wp_va); - if (rx_door_bell_value != + if (*ipa3_ctx->uc_ctx.rdy_ring_rp_va != *ipa3_ctx->uc_ctx.rdy_comp_ring_wp_va) { usleep_range(IPA_UC_WAIT_MIN_SLEEP, IPA_UC_WAII_MAX_SLEEP); @@ -1470,11 +1482,14 @@ int ipa3_disable_wdi_pipe(u32 clnt_hdl) memset(&ep_cfg_ctrl, 0, sizeof(struct ipa_ep_cfg_ctrl)); ep_cfg_ctrl.ipa_ep_delay = true; ipa3_cfg_ep_ctrl(clnt_hdl, &ep_cfg_ctrl); + /* disable force clear */ + ipa3_disable_force_clear(clnt_hdl); } IPA_ACTIVE_CLIENTS_DEC_EP(ipa3_get_client_mapping(clnt_hdl)); ep->uc_offload_state &= ~IPA_WDI_ENABLED; IPADBG("client (ep: %d) disabled\n", clnt_hdl); + uc_timeout: return result; } diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c index ff197705d845..f042d19f196a 100644 --- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c @@ -2736,6 +2736,23 @@ int rmnet_ipa3_set_tether_client_pipe( { int number, i; + /* error checking if ul_src_pipe_len valid or not*/ + if (data->ul_src_pipe_len > QMI_IPA_MAX_PIPES_V01 || + data->ul_src_pipe_len < 0) { + IPAWANERR("UL src pipes %d exceeding max %d\n", + data->ul_src_pipe_len, + QMI_IPA_MAX_PIPES_V01); + return -EFAULT; + } + /* error checking if dl_dst_pipe_len valid or not*/ + if (data->dl_dst_pipe_len > QMI_IPA_MAX_PIPES_V01 || + data->dl_dst_pipe_len < 0) { + IPAWANERR("DL dst pipes %d exceeding max %d\n", + data->dl_dst_pipe_len, + QMI_IPA_MAX_PIPES_V01); + return -EFAULT; + } + IPAWANDBG("client %d, UL %d, DL %d, reset %d\n", data->ipa_client, data->ul_src_pipe_len, diff --git a/drivers/platform/msm/qpnp-revid.c b/drivers/platform/msm/qpnp-revid.c index cfc8093fa3dd..6b5db58f856a 100644 --- a/drivers/platform/msm/qpnp-revid.c +++ b/drivers/platform/msm/qpnp-revid.c @@ -56,8 +56,8 @@ static const char *const pmic_names[] = { [PMI8998_SUBTYPE] = "PMI8998", [PM8005_SUBTYPE] = "PM8005", [PM8937_SUBTYPE] = "PM8937", - [PM2FALCON_SUBTYPE] = "PM2FALCON", - [PMFALCON_SUBTYPE] = "PMFALCON", + [PM660L_SUBTYPE] = "PM660L", + [PM660_SUBTYPE] = "PM660", [PMI8937_SUBTYPE] = "PMI8937", }; diff --git a/drivers/power/qcom-charger/fg-core.h b/drivers/power/qcom-charger/fg-core.h index 6f8266a3161c..07bde30524ac 100644 --- a/drivers/power/qcom-charger/fg-core.h +++ b/drivers/power/qcom-charger/fg-core.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -62,6 +62,7 @@ CHARS_PER_ITEM) + 1) \ #define FG_SRAM_ADDRESS_MAX 255 +#define FG_SRAM_LEN 504 #define PROFILE_LEN 224 #define PROFILE_COMP_LEN 148 #define BUCKET_COUNT 8 @@ -160,6 +161,8 @@ enum fg_sram_param_id { FG_SRAM_RECHARGE_VBATT_THR, FG_SRAM_KI_COEFF_MED_DISCHG, FG_SRAM_KI_COEFF_HI_DISCHG, + FG_SRAM_ESR_TIGHT_FILTER, + FG_SRAM_ESR_BROAD_FILTER, FG_SRAM_MAX, }; @@ -224,6 +227,11 @@ struct fg_dt_props { int cl_min_cap_limit; int jeita_hyst_temp; int batt_temp_delta; + int esr_flt_switch_temp; + int esr_tight_flt_upct; + int esr_broad_flt_upct; + int esr_tight_lt_flt_upct; + int esr_broad_lt_flt_upct; int jeita_thresholds[NUM_JEITA_LEVELS]; int ki_coeff_soc[KI_COEFF_SOC_LEVELS]; int ki_coeff_med_dischg[KI_COEFF_SOC_LEVELS]; @@ -336,12 +344,14 @@ struct fg_chip { bool ki_coeff_dischg_en; bool esr_fcc_ctrl_en; bool soc_reporting_ready; + bool esr_flt_cold_temp_en; struct completion soc_update; struct completion soc_ready; struct delayed_work profile_load_work; struct work_struct status_change_work; struct work_struct cycle_count_work; struct delayed_work batt_avg_work; + struct delayed_work sram_dump_work; struct fg_circ_buf ibatt_circ_buf; struct fg_circ_buf vbatt_circ_buf; }; @@ -392,6 +402,7 @@ extern int fg_clear_ima_errors_if_any(struct fg_chip *chip, bool check_hw_sts); extern int fg_clear_dma_errors_if_any(struct fg_chip *chip); extern int fg_debugfs_create(struct fg_chip *chip); extern void fill_string(char *str, size_t str_len, u8 *buf, int buf_len); +extern void dump_sram(u8 *buf, int addr, int len); extern int64_t twos_compliment_extend(int64_t val, int s_bit_pos); extern s64 fg_float_decode(u16 val); extern bool is_input_present(struct fg_chip *chip); diff --git a/drivers/power/qcom-charger/fg-util.c b/drivers/power/qcom-charger/fg-util.c index 405d875ea7df..41d2af0fbdc6 100644 --- a/drivers/power/qcom-charger/fg-util.c +++ b/drivers/power/qcom-charger/fg-util.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -10,8 +10,6 @@ * GNU General Public License for more details. */ -#define pr_fmt(fmt) "FG: %s: " fmt, __func__ - #include "fg-core.h" void fg_circ_buf_add(struct fg_circ_buf *buf, int val) @@ -174,6 +172,24 @@ void fill_string(char *str, size_t str_len, u8 *buf, int buf_len) } } +void dump_sram(u8 *buf, int addr, int len) +{ + int i; + char str[16]; + + /* + * Length passed should be in multiple of 4 as each FG SRAM word + * holds 4 bytes. To keep this simple, even if a length which is + * not a multiple of 4 bytes or less than 4 bytes is passed, SRAM + * registers dumped will be always in multiple of 4 bytes. + */ + for (i = 0; i < len; i += 4) { + str[0] = '\0'; + fill_string(str, sizeof(str), buf + i, 4); + pr_info("%03d %s\n", addr + (i / 4), str); + } +} + static inline bool fg_sram_address_valid(u16 address, int len) { if (address > FG_SRAM_ADDRESS_MAX) diff --git a/drivers/power/qcom-charger/pmic-voter.c b/drivers/power/qcom-charger/pmic-voter.c index 8072b63f53fe..e1a92fb23912 100644 --- a/drivers/power/qcom-charger/pmic-voter.c +++ b/drivers/power/qcom-charger/pmic-voter.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2016 The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -21,6 +21,7 @@ #include "pmic-voter.h" #define NUM_MAX_CLIENTS 8 +#define DEBUG_FORCE_CLIENT "DEBUG_FORCE_CLIENT" static DEFINE_SPINLOCK(votable_list_slock); static LIST_HEAD(votable_list); @@ -48,7 +49,12 @@ struct votable { const char *effective_client); char *client_strs[NUM_MAX_CLIENTS]; bool voted_on; - struct dentry *ent; + struct dentry *root; + struct dentry *status_ent; + u32 force_val; + struct dentry *force_val_ent; + bool force_active; + struct dentry *force_active_ent; }; /** @@ -236,6 +242,9 @@ int get_client_vote(struct votable *votable, const char *client_str) */ int get_effective_result_locked(struct votable *votable) { + if (votable->force_active) + return votable->force_val; + return votable->effective_result; } @@ -249,8 +258,29 @@ int get_effective_result(struct votable *votable) return value; } +/** + * get_effective_client() - + * get_effective_client_locked() - + * The unlocked and locked variants of getting the effective client + * amongst all the enabled voters. + * + * @votable: the votable object + * + * Returns: + * The effective client. + * For MIN and MAX votable, returns NULL when the votable + * object has been created but no clients have casted their votes or + * the last enabled client disables its vote. + * For SET_ANY votable it returns NULL too when no clients have casted + * their votes. But for SET_ANY since there is no concept of abstaining + * from election, the only client that casts a vote or the client that + * caused the result to change is returned. + */ const char *get_effective_client_locked(struct votable *votable) { + if (votable->force_active) + return DEBUG_FORCE_CLIENT; + return get_client_str(votable, votable->effective_client_id); } @@ -313,7 +343,7 @@ int vote(struct votable *votable, const char *client_str, bool enabled, int val) if ((votable->votes[client_id].enabled == enabled) && (votable->votes[client_id].value == val)) { - pr_debug("%s: %s,%d same vote %s of %d\n", + pr_debug("%s: %s,%d same vote %s of val=%d\n", votable->name, client_str, client_id, enabled ? "on" : "off", @@ -325,13 +355,13 @@ int vote(struct votable *votable, const char *client_str, bool enabled, int val) votable->votes[client_id].value = val; if (similar_vote && votable->voted_on) { - pr_debug("%s: %s,%d Similar vote %s of %d\n", + pr_debug("%s: %s,%d Ignoring similar vote %s of val=%d\n", votable->name, client_str, client_id, enabled ? "on" : "off", val); goto out; } - pr_debug("%s: %s,%d voting %s of %d\n", + pr_debug("%s: %s,%d voting %s of val=%d\n", votable->name, client_str, client_id, enabled ? "on" : "off", val); switch (votable->type) { @@ -361,7 +391,7 @@ int vote(struct votable *votable, const char *client_str, bool enabled, int val) votable->name, effective_result, get_client_str(votable, effective_id), effective_id); - if (votable->callback) + if (votable->callback && !votable->force_active) rc = votable->callback(votable, votable->data, effective_result, get_client_str(votable, effective_id)); @@ -412,6 +442,42 @@ out: return NULL; } +static int force_active_get(void *data, u64 *val) +{ + struct votable *votable = data; + + *val = votable->force_active; + + return 0; +} + +static int force_active_set(void *data, u64 val) +{ + struct votable *votable = data; + int rc = 0; + + lock_votable(votable); + votable->force_active = !!val; + + if (!votable->callback) + goto out; + + if (votable->force_active) { + rc = votable->callback(votable, votable->data, + votable->force_val, + DEBUG_FORCE_CLIENT); + } else { + rc = votable->callback(votable, votable->data, + votable->effective_result, + get_client_str(votable, votable->effective_client_id)); + } +out: + unlock_votable(votable); + return rc; +} +DEFINE_SIMPLE_ATTRIBUTE(votable_force_ops, force_active_get, force_active_set, + "%lld\n"); + static int show_votable_clients(struct seq_file *m, void *data) { struct votable *votable = m->private; @@ -421,8 +487,8 @@ static int show_votable_clients(struct seq_file *m, void *data) lock_votable(votable); - seq_printf(m, "%s:\n", votable->name); - seq_puts(m, "Clients:\n"); + seq_printf(m, "Votable %s:\n", votable->name); + seq_puts(m, "clients:\n"); for (i = 0; i < votable->num_clients; i++) { if (votable->client_strs[i]) { seq_printf(m, "%-15s:\t\ten=%d\t\tv=%d\n", @@ -444,7 +510,7 @@ static int show_votable_clients(struct seq_file *m, void *data) break; } - seq_printf(m, "Type: %s\n", type_str); + seq_printf(m, "type: %s\n", type_str); seq_puts(m, "Effective:\n"); effective_client_str = get_effective_client_locked(votable); seq_printf(m, "%-15s:\t\tv=%d\n", @@ -455,16 +521,16 @@ static int show_votable_clients(struct seq_file *m, void *data) return 0; } -static int votable_debugfs_open(struct inode *inode, struct file *file) +static int votable_status_open(struct inode *inode, struct file *file) { struct votable *votable = inode->i_private; return single_open(file, show_votable_clients, votable); } -static const struct file_operations votable_debugfs_ops = { +static const struct file_operations votable_status_ops = { .owner = THIS_MODULE, - .open = votable_debugfs_open, + .open = votable_status_open, .read = seq_read, .llseek = seq_lseek, .release = single_release, @@ -527,11 +593,45 @@ struct votable *create_votable(const char *name, list_add(&votable->list, &votable_list); spin_unlock_irqrestore(&votable_list_slock, flags); - votable->ent = debugfs_create_file(name, S_IFREG | S_IRUGO, - debug_root, votable, - &votable_debugfs_ops); - if (!votable->ent) { - pr_err("Couldn't create %s debug file\n", name); + votable->root = debugfs_create_dir(name, debug_root); + if (!votable->root) { + pr_err("Couldn't create debug dir %s\n", name); + kfree(votable->name); + kfree(votable); + return ERR_PTR(-ENOMEM); + } + + votable->status_ent = debugfs_create_file("status", S_IFREG | S_IRUGO, + votable->root, votable, + &votable_status_ops); + if (!votable->status_ent) { + pr_err("Couldn't create status dbg file for %s\n", name); + debugfs_remove_recursive(votable->root); + kfree(votable->name); + kfree(votable); + return ERR_PTR(-EEXIST); + } + + votable->force_val_ent = debugfs_create_u32("force_val", + S_IFREG | S_IWUSR | S_IRUGO, + votable->root, + &(votable->force_val)); + + if (!votable->force_val_ent) { + pr_err("Couldn't create force_val dbg file for %s\n", name); + debugfs_remove_recursive(votable->root); + kfree(votable->name); + kfree(votable); + return ERR_PTR(-EEXIST); + } + + votable->force_active_ent = debugfs_create_file("force_active", + S_IFREG | S_IRUGO, + votable->root, votable, + &votable_force_ops); + if (!votable->force_active_ent) { + pr_err("Couldn't create force_active dbg file for %s\n", name); + debugfs_remove_recursive(votable->root); kfree(votable->name); kfree(votable); return ERR_PTR(-EEXIST); @@ -552,7 +652,8 @@ void destroy_votable(struct votable *votable) list_del(&votable->list); spin_unlock_irqrestore(&votable_list_slock, flags); - debugfs_remove(votable->ent); + debugfs_remove_recursive(votable->root); + for (i = 0; i < votable->num_clients && votable->client_strs[i]; i++) kfree(votable->client_strs[i]); diff --git a/drivers/power/qcom-charger/qpnp-fg-gen3.c b/drivers/power/qcom-charger/qpnp-fg-gen3.c index 7c1ece431beb..8523efa1a4ab 100644 --- a/drivers/power/qcom-charger/qpnp-fg-gen3.c +++ b/drivers/power/qcom-charger/qpnp-fg-gen3.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -12,6 +12,7 @@ #define pr_fmt(fmt) "FG: %s: " fmt, __func__ +#include <linux/ktime.h> #include <linux/of.h> #include <linux/of_irq.h> #include <linux/of_platform.h> @@ -36,6 +37,11 @@ #define SYS_TERM_CURR_OFFSET 0 #define VBATT_FULL_WORD 7 #define VBATT_FULL_OFFSET 0 +#define ESR_FILTER_WORD 8 +#define ESR_UPD_TIGHT_OFFSET 0 +#define ESR_UPD_BROAD_OFFSET 1 +#define ESR_UPD_TIGHT_LOW_TEMP_OFFSET 2 +#define ESR_UPD_BROAD_LOW_TEMP_OFFSET 3 #define KI_COEFF_MED_DISCHG_WORD 9 #define KI_COEFF_MED_DISCHG_OFFSET 3 #define KI_COEFF_HI_DISCHG_WORD 10 @@ -202,6 +208,10 @@ static struct fg_sram_param pmi8998_v1_sram_params[] = { PARAM(KI_COEFF_HI_DISCHG, KI_COEFF_HI_DISCHG_WORD, KI_COEFF_HI_DISCHG_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), + PARAM(ESR_TIGHT_FILTER, ESR_FILTER_WORD, ESR_UPD_TIGHT_OFFSET, + 1, 512, 1000000, 0, fg_encode_default, NULL), + PARAM(ESR_BROAD_FILTER, ESR_FILTER_WORD, ESR_UPD_BROAD_OFFSET, + 1, 512, 1000000, 0, fg_encode_default, NULL), }; static struct fg_sram_param pmi8998_v2_sram_params[] = { @@ -262,6 +272,10 @@ static struct fg_sram_param pmi8998_v2_sram_params[] = { PARAM(KI_COEFF_HI_DISCHG, KI_COEFF_HI_DISCHG_v2_WORD, KI_COEFF_HI_DISCHG_v2_OFFSET, 1, 1000, 244141, 0, fg_encode_default, NULL), + PARAM(ESR_TIGHT_FILTER, ESR_FILTER_WORD, ESR_UPD_TIGHT_OFFSET, + 1, 512, 1000000, 0, fg_encode_default, NULL), + PARAM(ESR_BROAD_FILTER, ESR_FILTER_WORD, ESR_UPD_BROAD_OFFSET, + 1, 512, 1000000, 0, fg_encode_default, NULL), }; static struct fg_alg_flag pmi8998_v1_alg_flags[] = { @@ -330,17 +344,18 @@ module_param_named( debug_mask, fg_gen3_debug_mask, int, S_IRUSR | S_IWUSR ); -static int fg_sram_update_period_ms = 30000; +static bool fg_profile_dump; module_param_named( - sram_update_period_ms, fg_sram_update_period_ms, int, S_IRUSR | S_IWUSR + profile_dump, fg_profile_dump, bool, S_IRUSR | S_IWUSR ); -static bool fg_sram_dump; +static int fg_sram_dump_period_ms = 20000; module_param_named( - sram_dump, fg_sram_dump, bool, S_IRUSR | S_IWUSR + sram_dump_period_ms, fg_sram_dump_period_ms, int, S_IRUSR | S_IWUSR ); static int fg_restart; +static bool fg_sram_dump; /* All getters HERE */ @@ -797,7 +812,7 @@ static const char *fg_get_battery_type(struct fg_chip *chip) if (chip->bp.batt_type_str) { if (chip->profile_loaded) return chip->bp.batt_type_str; - else + else if (chip->profile_available) return LOADING_BATT_TYPE; } @@ -1548,6 +1563,65 @@ static int fg_adjust_recharge_soc(struct fg_chip *chip) return 0; } +static int fg_esr_filter_config(struct fg_chip *chip, int batt_temp) +{ + u8 esr_tight_lt_flt, esr_broad_lt_flt; + bool cold_temp = false; + int rc; + + /* + * If the battery temperature is lower than -20 C, then skip modifying + * ESR filter. + */ + if (batt_temp < -210) + return 0; + + /* + * If battery temperature is lesser than 10 C (default), then apply the + * normal ESR tight and broad filter values to ESR low temperature tight + * and broad filters. If battery temperature is higher than 10 C, then + * apply back the low temperature ESR filter coefficients to ESR low + * temperature tight and broad filters. + */ + if (batt_temp > chip->dt.esr_flt_switch_temp + && chip->esr_flt_cold_temp_en) { + fg_encode(chip->sp, FG_SRAM_ESR_TIGHT_FILTER, + chip->dt.esr_tight_lt_flt_upct, &esr_tight_lt_flt); + fg_encode(chip->sp, FG_SRAM_ESR_BROAD_FILTER, + chip->dt.esr_broad_lt_flt_upct, &esr_broad_lt_flt); + } else if (batt_temp <= chip->dt.esr_flt_switch_temp + && !chip->esr_flt_cold_temp_en) { + fg_encode(chip->sp, FG_SRAM_ESR_TIGHT_FILTER, + chip->dt.esr_tight_flt_upct, &esr_tight_lt_flt); + fg_encode(chip->sp, FG_SRAM_ESR_BROAD_FILTER, + chip->dt.esr_broad_flt_upct, &esr_broad_lt_flt); + cold_temp = true; + } else { + return 0; + } + + rc = fg_sram_write(chip, ESR_FILTER_WORD, + ESR_UPD_TIGHT_LOW_TEMP_OFFSET, &esr_tight_lt_flt, 1, + FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing ESR LT tight filter, rc=%d\n", rc); + return rc; + } + + rc = fg_sram_write(chip, ESR_FILTER_WORD, + ESR_UPD_BROAD_LOW_TEMP_OFFSET, &esr_broad_lt_flt, 1, + FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing ESR LT broad filter, rc=%d\n", rc); + return rc; + } + + chip->esr_flt_cold_temp_en = cold_temp; + fg_dbg(chip, FG_STATUS, "applied %s ESR filter values\n", + cold_temp ? "cold" : "normal"); + return 0; +} + static int fg_esr_fcc_config(struct fg_chip *chip) { union power_supply_propval prop = {0, }; @@ -1615,6 +1689,18 @@ static int fg_esr_fcc_config(struct fg_chip *chip) return 0; } +static int fg_batt_missing_config(struct fg_chip *chip, bool enable) +{ + int rc; + + rc = fg_masked_write(chip, BATT_INFO_BATT_MISS_CFG(chip), + BM_FROM_BATT_ID_BIT, enable ? BM_FROM_BATT_ID_BIT : 0); + if (rc < 0) + pr_err("Error in writing to %04x, rc=%d\n", + BATT_INFO_BATT_MISS_CFG(chip), rc); + return rc; +} + static void fg_batt_avg_update(struct fg_chip *chip) { if (chip->charge_status == chip->prev_charge_status) @@ -1838,18 +1924,6 @@ static int fg_get_cycle_count(struct fg_chip *chip) return count; } -static void dump_sram(u8 *buf, int len) -{ - int i; - char str[16]; - - for (i = 0; i < len; i += 4) { - str[0] = '\0'; - fill_string(str, sizeof(str), buf + i, 4); - pr_info("%03d %s\n", PROFILE_LOAD_WORD + (i / 4), str); - } -} - #define PROFILE_LOAD_BIT BIT(0) #define BOOTLOADER_LOAD_BIT BIT(1) #define BOOTLOADER_RESTART_BIT BIT(2) @@ -1885,11 +1959,13 @@ static bool is_profile_load_required(struct fg_chip *chip) if (!chip->dt.force_load_profile) { pr_warn("Profiles doesn't match, skipping loading it since force_load_profile is disabled\n"); - if (fg_sram_dump) { + if (fg_profile_dump) { pr_info("FG: loaded profile:\n"); - dump_sram(buf, PROFILE_COMP_LEN); + dump_sram(buf, PROFILE_LOAD_WORD, + PROFILE_COMP_LEN); pr_info("FG: available profile:\n"); - dump_sram(chip->batt_profile, PROFILE_LEN); + dump_sram(chip->batt_profile, PROFILE_LOAD_WORD, + PROFILE_LEN); } return false; } @@ -1897,14 +1973,26 @@ static bool is_profile_load_required(struct fg_chip *chip) fg_dbg(chip, FG_STATUS, "Profiles are different, loading the correct one\n"); } else { fg_dbg(chip, FG_STATUS, "Profile integrity bit is not set\n"); - if (fg_sram_dump) { + if (fg_profile_dump) { pr_info("FG: profile to be loaded:\n"); - dump_sram(chip->batt_profile, PROFILE_LEN); + dump_sram(chip->batt_profile, PROFILE_LOAD_WORD, + PROFILE_LEN); } } return true; } +static void clear_battery_profile(struct fg_chip *chip) +{ + u8 val = 0; + int rc; + + rc = fg_sram_write(chip, PROFILE_INTEGRITY_WORD, + PROFILE_INTEGRITY_OFFSET, &val, 1, FG_IMA_DEFAULT); + if (rc < 0) + pr_err("failed to write profile integrity rc=%d\n", rc); +} + #define SOC_READY_WAIT_MS 2000 static int __fg_restart(struct fg_chip *chip) { @@ -2056,6 +2144,71 @@ out: vote(chip->awake_votable, PROFILE_LOAD, false, 0); } +static void sram_dump_work(struct work_struct *work) +{ + struct fg_chip *chip = container_of(work, struct fg_chip, + sram_dump_work.work); + u8 buf[FG_SRAM_LEN]; + int rc; + s64 timestamp_ms; + + rc = fg_sram_read(chip, 0, 0, buf, FG_SRAM_LEN, FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in reading FG SRAM, rc:%d\n", rc); + goto resched; + } + + timestamp_ms = ktime_to_ms(ktime_get_boottime()); + fg_dbg(chip, FG_STATUS, "SRAM Dump Started at %lld.%lld\n", + timestamp_ms / 1000, timestamp_ms % 1000); + dump_sram(buf, 0, FG_SRAM_LEN); + timestamp_ms = ktime_to_ms(ktime_get_boottime()); + fg_dbg(chip, FG_STATUS, "SRAM Dump done at %lld.%lld\n", + timestamp_ms / 1000, timestamp_ms % 1000); +resched: + schedule_delayed_work(&chip->sram_dump_work, + msecs_to_jiffies(fg_sram_dump_period_ms)); +} + +static int fg_sram_dump_sysfs(const char *val, const struct kernel_param *kp) +{ + int rc; + struct power_supply *bms_psy; + struct fg_chip *chip; + bool old_val = fg_sram_dump; + + rc = param_set_bool(val, kp); + if (rc) { + pr_err("Unable to set fg_sram_dump: %d\n", rc); + return rc; + } + + if (fg_sram_dump == old_val) + return 0; + + bms_psy = power_supply_get_by_name("bms"); + if (!bms_psy) { + pr_err("bms psy not found\n"); + return -ENODEV; + } + + chip = power_supply_get_drvdata(bms_psy); + if (fg_sram_dump) + schedule_delayed_work(&chip->sram_dump_work, + msecs_to_jiffies(fg_sram_dump_period_ms)); + else + cancel_delayed_work_sync(&chip->sram_dump_work); + + return 0; +} + +static struct kernel_param_ops fg_sram_dump_ops = { + .set = fg_sram_dump_sysfs, + .get = param_get_bool, +}; + +module_param_cb(sram_dump_en, &fg_sram_dump_ops, &fg_sram_dump, 0644); + static int fg_restart_sysfs(const char *val, const struct kernel_param *kp) { int rc; @@ -2148,7 +2301,14 @@ static int fg_get_time_to_full(struct fg_chip *chip, int *val) return -ENODATA; } - if (chip->charge_status == POWER_SUPPLY_STATUS_FULL) { + rc = fg_get_prop_capacity(chip, &msoc); + if (rc < 0) { + pr_err("failed to get msoc rc=%d\n", rc); + return rc; + } + fg_dbg(chip, FG_TTF, "msoc=%d\n", msoc); + + if (msoc >= 100) { *val = 0; return 0; } @@ -2211,13 +2371,6 @@ static int fg_get_time_to_full(struct fg_chip *chip, int *val) act_cap_uah *= MILLI_UNIT; fg_dbg(chip, FG_TTF, "actual_capacity_uah=%d\n", act_cap_uah); - rc = fg_get_prop_capacity(chip, &msoc); - if (rc < 0) { - pr_err("failed to get msoc rc=%d\n", rc); - return rc; - } - fg_dbg(chip, FG_TTF, "msoc=%d\n", msoc); - rc = fg_get_sram_prop(chip, FG_SRAM_FULL_SOC, &full_soc); if (rc < 0) { pr_err("failed to get full soc rc=%d\n", rc); @@ -2257,7 +2410,7 @@ skip_cc_estimate: fg_dbg(chip, FG_TTF, "t_predicted_cc=%lld\n", t_predicted_cc); /* CV estimate starts here */ - if (chip->charge_type == POWER_SUPPLY_CHARGE_TYPE_TAPER) + if (chip->charge_type >= POWER_SUPPLY_CHARGE_TYPE_TAPER) ln_val = ibatt_avg / abs(chip->dt.sys_term_curr_ma); else ln_val = i_cc2cv / abs(chip->dt.sys_term_curr_ma); @@ -2355,7 +2508,7 @@ static int fg_psy_get_property(struct power_supply *psy, pval->intval = chip->cl.nom_cap_uah; break; case POWER_SUPPLY_PROP_RESISTANCE_ID: - rc = fg_get_batt_id(chip, &pval->intval); + pval->intval = chip->batt_id_ohms; break; case POWER_SUPPLY_PROP_BATTERY_TYPE: pval->strval = fg_get_battery_type(chip); @@ -2709,6 +2862,26 @@ static int fg_hw_init(struct fg_chip *chip) } } + fg_encode(chip->sp, FG_SRAM_ESR_TIGHT_FILTER, + chip->dt.esr_tight_flt_upct, buf); + rc = fg_sram_write(chip, chip->sp[FG_SRAM_ESR_TIGHT_FILTER].addr_word, + chip->sp[FG_SRAM_ESR_TIGHT_FILTER].addr_byte, buf, + chip->sp[FG_SRAM_ESR_TIGHT_FILTER].len, FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing ESR tight filter, rc=%d\n", rc); + return rc; + } + + fg_encode(chip->sp, FG_SRAM_ESR_BROAD_FILTER, + chip->dt.esr_broad_flt_upct, buf); + rc = fg_sram_write(chip, chip->sp[FG_SRAM_ESR_BROAD_FILTER].addr_word, + chip->sp[FG_SRAM_ESR_BROAD_FILTER].addr_byte, buf, + chip->sp[FG_SRAM_ESR_BROAD_FILTER].len, FG_IMA_DEFAULT); + if (rc < 0) { + pr_err("Error in writing ESR broad filter, rc=%d\n", rc); + return rc; + } + return 0; } @@ -2764,7 +2937,6 @@ static irqreturn_t fg_batt_missing_irq_handler(int irq, void *data) u8 status; int rc; - fg_dbg(chip, FG_IRQ, "irq %d triggered\n", irq); rc = fg_read(chip, BATT_INFO_INT_RT_STS(chip), &status, 1); if (rc < 0) { pr_err("failed to read addr=0x%04x, rc=%d\n", @@ -2772,23 +2944,39 @@ static irqreturn_t fg_batt_missing_irq_handler(int irq, void *data) return IRQ_HANDLED; } + fg_dbg(chip, FG_IRQ, "irq %d triggered sts:%d\n", irq, status); chip->battery_missing = (status & BT_MISS_BIT); if (chip->battery_missing) { chip->profile_available = false; chip->profile_loaded = false; - clear_cycle_counter(chip); chip->soc_reporting_ready = false; - } else { - rc = fg_get_batt_profile(chip); - if (rc < 0) { - chip->soc_reporting_ready = true; - pr_err("Error in getting battery profile, rc:%d\n", rc); - return IRQ_HANDLED; - } - schedule_delayed_work(&chip->profile_load_work, 0); + return IRQ_HANDLED; + } + + rc = fg_batt_missing_config(chip, false); + if (rc < 0) { + pr_err("Error in disabling BMD, rc=%d\n", rc); + return IRQ_HANDLED; } + rc = fg_get_batt_profile(chip); + if (rc < 0) { + chip->soc_reporting_ready = true; + pr_err("Error in getting battery profile, rc:%d\n", rc); + goto enable_bmd; + } + + clear_battery_profile(chip); + schedule_delayed_work(&chip->profile_load_work, 0); + +enable_bmd: + /* Wait for 200ms before enabling BMD again */ + msleep(200); + rc = fg_batt_missing_config(chip, true); + if (rc < 0) + pr_err("Error in enabling BMD, rc=%d\n", rc); + return IRQ_HANDLED; } @@ -2805,6 +2993,10 @@ static irqreturn_t fg_delta_batt_temp_irq_handler(int irq, void *data) return IRQ_HANDLED; } + rc = fg_esr_filter_config(chip, batt_temp); + if (rc < 0) + pr_err("Error in configuring ESR filter rc:%d\n", rc); + if (!is_charger_available(chip)) { chip->last_batt_temp = batt_temp; return IRQ_HANDLED; @@ -3111,6 +3303,11 @@ static int fg_parse_ki_coefficients(struct fg_chip *chip) #define DEFAULT_CL_MAX_LIM_DECIPERC 0 #define BTEMP_DELTA_LOW 2 #define BTEMP_DELTA_HIGH 10 +#define DEFAULT_ESR_FLT_TEMP_DECIDEGC 100 +#define DEFAULT_ESR_TIGHT_FLT_UPCT 3907 +#define DEFAULT_ESR_BROAD_FLT_UPCT 99610 +#define DEFAULT_ESR_TIGHT_LT_FLT_UPCT 48829 +#define DEFAULT_ESR_BROAD_LT_FLT_UPCT 148438 static int fg_parse_dt(struct fg_chip *chip) { struct device_node *child, *revid_node, *node = chip->dev->of_node; @@ -3157,7 +3354,7 @@ static int fg_parse_dt(struct fg_chip *chip) return -EINVAL; } break; - case PMFALCON_SUBTYPE: + case PM660_SUBTYPE: chip->sp = pmi8998_v2_sram_params; chip->alg_flags = pmi8998_v2_alg_flags; break; @@ -3387,6 +3584,40 @@ static int fg_parse_dt(struct fg_chip *chip) else chip->dt.rconn_mohms = temp; + rc = of_property_read_u32(node, "qcom,fg-esr-filter-switch-temp", + &temp); + if (rc < 0) + chip->dt.esr_flt_switch_temp = DEFAULT_ESR_FLT_TEMP_DECIDEGC; + else + chip->dt.esr_flt_switch_temp = temp; + + rc = of_property_read_u32(node, "qcom,fg-esr-tight-filter-micro-pct", + &temp); + if (rc < 0) + chip->dt.esr_tight_flt_upct = DEFAULT_ESR_TIGHT_FLT_UPCT; + else + chip->dt.esr_tight_flt_upct = temp; + + rc = of_property_read_u32(node, "qcom,fg-esr-broad-filter-micro-pct", + &temp); + if (rc < 0) + chip->dt.esr_broad_flt_upct = DEFAULT_ESR_BROAD_FLT_UPCT; + else + chip->dt.esr_broad_flt_upct = temp; + + rc = of_property_read_u32(node, "qcom,fg-esr-tight-lt-filter-micro-pct", + &temp); + if (rc < 0) + chip->dt.esr_tight_lt_flt_upct = DEFAULT_ESR_TIGHT_LT_FLT_UPCT; + else + chip->dt.esr_tight_lt_flt_upct = temp; + + rc = of_property_read_u32(node, "qcom,fg-esr-broad-lt-filter-micro-pct", + &temp); + if (rc < 0) + chip->dt.esr_broad_lt_flt_upct = DEFAULT_ESR_BROAD_LT_FLT_UPCT; + else + chip->dt.esr_broad_lt_flt_upct = temp; return 0; } @@ -3449,6 +3680,7 @@ static int fg_gen3_probe(struct platform_device *pdev) INIT_WORK(&chip->status_change_work, status_change_work); INIT_WORK(&chip->cycle_count_work, cycle_count_work); INIT_DELAYED_WORK(&chip->batt_avg_work, batt_avg_work); + INIT_DELAYED_WORK(&chip->sram_dump_work, sram_dump_work); rc = fg_memif_init(chip); if (rc < 0) { @@ -3511,9 +3743,13 @@ static int fg_gen3_probe(struct platform_device *pdev) if (!rc) rc = fg_get_battery_temp(chip, &batt_temp); - if (!rc) + if (!rc) { pr_info("battery SOC:%d voltage: %duV temp: %d id: %dKOhms\n", msoc, volt_uv, batt_temp, chip->batt_id_ohms / 1000); + rc = fg_esr_filter_config(chip, batt_temp); + if (rc < 0) + pr_err("Error in configuring ESR filter rc:%d\n", rc); + } device_init_wakeup(chip->dev, true); if (chip->profile_available) @@ -3542,6 +3778,8 @@ static int fg_gen3_suspend(struct device *dev) } cancel_delayed_work_sync(&chip->batt_avg_work); + if (fg_sram_dump) + cancel_delayed_work_sync(&chip->sram_dump_work); return 0; } @@ -3563,6 +3801,9 @@ static int fg_gen3_resume(struct device *dev) fg_circ_buf_clr(&chip->ibatt_circ_buf); fg_circ_buf_clr(&chip->vbatt_circ_buf); schedule_delayed_work(&chip->batt_avg_work, 0); + if (fg_sram_dump) + schedule_delayed_work(&chip->sram_dump_work, + msecs_to_jiffies(fg_sram_dump_period_ms)); return 0; } diff --git a/drivers/power/qcom-charger/qpnp-smb2.c b/drivers/power/qcom-charger/qpnp-smb2.c index 90e3689086a6..a07325102631 100644 --- a/drivers/power/qcom-charger/qpnp-smb2.c +++ b/drivers/power/qcom-charger/qpnp-smb2.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016 The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1144,13 +1144,6 @@ static int smb2_configure_typec(struct smb_charger *chg) return rc; } - rc = smblib_validate_initial_typec_legacy_status(chg); - if (rc < 0) { - dev_err(chg->dev, "Couldn't validate typec legacy status rc=%d\n", - rc); - return rc; - } - return rc; } @@ -1453,7 +1446,7 @@ static int smb2_setup_wa_flags(struct smb2 *chip) if (pmic_rev_id->rev4 == PMI8998_V2P0_REV4) /* PMI rev 2.0 */ chg->wa_flags |= TYPEC_CC2_REMOVAL_WA_BIT; break; - case PMFALCON_SUBTYPE: + case PM660_SUBTYPE: chip->chg.wa_flags |= BOOST_BACK_WA; break; default: @@ -1891,6 +1884,12 @@ static int smb2_probe(struct platform_device *pdev) goto cleanup; } + rc = smb2_init_hw(chip); + if (rc < 0) { + pr_err("Couldn't initialize hardware rc=%d\n", rc); + goto cleanup; + } + rc = smb2_init_dc_psy(chip); if (rc < 0) { pr_err("Couldn't initialize dc psy rc=%d\n", rc); @@ -1923,12 +1922,6 @@ static int smb2_probe(struct platform_device *pdev) goto cleanup; } - rc = smb2_init_hw(chip); - if (rc < 0) { - pr_err("Couldn't initialize hardware rc=%d\n", rc); - goto cleanup; - } - rc = smb2_determine_initial_status(chip); if (rc < 0) { pr_err("Couldn't determine initial status rc=%d\n", diff --git a/drivers/power/qcom-charger/smb-lib.c b/drivers/power/qcom-charger/smb-lib.c index 86140386f0e3..6d010a11d034 100644 --- a/drivers/power/qcom-charger/smb-lib.c +++ b/drivers/power/qcom-charger/smb-lib.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016 The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -16,7 +16,7 @@ #include <linux/iio/consumer.h> #include <linux/power_supply.h> #include <linux/regulator/driver.h> -#include <linux/qpnp/power-on.h> +#include <linux/input/qpnp-power-on.h> #include <linux/irq.h> #include "smb-lib.h" #include "smb-reg.h" @@ -627,6 +627,21 @@ static void smblib_uusb_removal(struct smb_charger *chg) smblib_err(chg, "Couldn't un-vote for USB ICL rc=%d\n", rc); } +static bool smblib_sysok_reason_usbin(struct smb_charger *chg) +{ + int rc; + u8 stat; + + rc = smblib_read(chg, SYSOK_REASON_STATUS_REG, &stat); + if (rc < 0) { + smblib_err(chg, "Couldn't get SYSOK_REASON_STATUS rc=%d\n", rc); + /* assuming 'not usbin' in case of read failure */ + return false; + } + + return stat & SYSOK_REASON_USBIN_BIT; +} + /********************* * VOTABLE CALLBACKS * *********************/ @@ -2852,6 +2867,8 @@ static void smblib_handle_typec_removal(struct smb_charger *chg) typec_source_removal(chg); typec_sink_removal(chg); + chg->usb_ever_removed = true; + smblib_update_usb_type(chg); } @@ -2860,6 +2877,7 @@ static void smblib_handle_typec_insertion(struct smb_charger *chg, { int rp; bool vbus_cc_short = false; + bool valid_legacy_cable; vote(chg->pd_disallowed_votable_indirect, CC_DETACHED_VOTER, false, 0); @@ -2871,10 +2889,12 @@ static void smblib_handle_typec_insertion(struct smb_charger *chg, typec_sink_removal(chg); } + valid_legacy_cable = legacy_cable && + (chg->usb_ever_removed || !smblib_sysok_reason_usbin(chg)); vote(chg->pd_disallowed_votable_indirect, LEGACY_CABLE_VOTER, - legacy_cable, 0); + valid_legacy_cable, 0); - if (legacy_cable) { + if (valid_legacy_cable) { rp = smblib_get_prop_ufp_mode(chg); if (rp == POWER_SUPPLY_TYPEC_SOURCE_HIGH || rp == POWER_SUPPLY_TYPEC_NON_COMPLIANT) { @@ -3476,40 +3496,3 @@ int smblib_deinit(struct smb_charger *chg) return 0; } - -int smblib_validate_initial_typec_legacy_status(struct smb_charger *chg) -{ - int rc; - u8 stat; - - - if (qpnp_pon_is_warm_reset()) - return 0; - - rc = smblib_read(chg, TYPE_C_STATUS_5_REG, &stat); - if (rc < 0) { - smblib_err(chg, "Couldn't read TYPE_C_STATUS_5 rc=%d\n", rc); - return rc; - } - - if ((stat & TYPEC_LEGACY_CABLE_STATUS_BIT) == 0) - return 0; - - rc = smblib_masked_write(chg, TYPE_C_INTRPT_ENB_SOFTWARE_CTRL_REG, - TYPEC_DISABLE_CMD_BIT, TYPEC_DISABLE_CMD_BIT); - if (rc < 0) { - smblib_err(chg, "Couldn't disable typec rc=%d\n", rc); - return rc; - } - - usleep_range(150000, 151000); - - rc = smblib_masked_write(chg, TYPE_C_INTRPT_ENB_SOFTWARE_CTRL_REG, - TYPEC_DISABLE_CMD_BIT, 0); - if (rc < 0) { - smblib_err(chg, "Couldn't enable typec rc=%d\n", rc); - return rc; - } - - return 0; -} diff --git a/drivers/power/qcom-charger/smb-lib.h b/drivers/power/qcom-charger/smb-lib.h index f6335aae2637..b65c0211405a 100644 --- a/drivers/power/qcom-charger/smb-lib.h +++ b/drivers/power/qcom-charger/smb-lib.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016 The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -233,6 +233,7 @@ struct smb_charger { /* extcon for VBUS / ID notification to USB for uUSB */ struct extcon_dev *extcon; + bool usb_ever_removed; }; int smblib_read(struct smb_charger *chg, u16 addr, u8 *val); @@ -377,8 +378,6 @@ int smblib_get_prop_slave_current_now(struct smb_charger *chg, int smblib_set_prop_ship_mode(struct smb_charger *chg, const union power_supply_propval *val); -int smblib_validate_initial_typec_legacy_status(struct smb_charger *chg); - int smblib_init(struct smb_charger *chg); int smblib_deinit(struct smb_charger *chg); #endif /* __SMB2_CHARGER_H */ diff --git a/drivers/power/qcom-charger/smb-reg.h b/drivers/power/qcom-charger/smb-reg.h index a30efbe3651e..a9606ab1944b 100644 --- a/drivers/power/qcom-charger/smb-reg.h +++ b/drivers/power/qcom-charger/smb-reg.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016 The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -860,6 +860,10 @@ enum { #define WDOG_STATUS_1_BIT BIT(1) #define BARK_BITE_STATUS_BIT BIT(0) +#define SYSOK_REASON_STATUS_REG (MISC_BASE + 0x0D) +#define SYSOK_REASON_DCIN_BIT BIT(1) +#define SYSOK_REASON_USBIN_BIT BIT(0) + /* MISC Interrupt Bits */ #define SWITCHER_POWER_OK_RT_STS_BIT BIT(7) #define TEMPERATURE_CHANGE_RT_STS_BIT BIT(6) diff --git a/drivers/power/reset/msm-poweroff.c b/drivers/power/reset/msm-poweroff.c index 267df592ba8a..cd02ed5bd46a 100644 --- a/drivers/power/reset/msm-poweroff.c +++ b/drivers/power/reset/msm-poweroff.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -23,7 +23,7 @@ #include <linux/reboot.h> #include <linux/pm.h> #include <linux/delay.h> -#include <linux/qpnp/power-on.h> +#include <linux/input/qpnp-power-on.h> #include <linux/of_address.h> #include <asm/cacheflush.h> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index bd2c1a8e7540..8d54ece776e2 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -835,6 +835,15 @@ config REGULATOR_QPNP_LCDB negative voltage bias for the LCD display panel. It also allows configurability for the various bias-voltage parameters. +config REGULATOR_QPNP_OLEDB + depends on SPMI + tristate "Qualcomm Technologies, Inc QPNP OLEDB regulator support" + help + This driver supports the OLEDB(AVDD bias) signal for AMOLED panel in Qualcomm + Technologies, Inc QPNP PMIC. It exposes the OLED voltage configuration + via the regulator framework. The configurable range of this bias is + 5V to 8.1V. + config REGULATOR_SPM bool "SPM regulator driver" depends on SPMI diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index abd116d3d8af..20cf304a4714 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -117,6 +117,7 @@ obj-$(CONFIG_REGULATOR_CPRH_KBSS) += cprh-kbss-regulator.o obj-$(CONFIG_REGULATOR_CPR4_MMSS_LDO) += cpr4-mmss-ldo-regulator.o obj-$(CONFIG_REGULATOR_QPNP_LABIBB) += qpnp-labibb-regulator.o obj-$(CONFIG_REGULATOR_QPNP_LCDB) += qpnp-lcdb-regulator.o +obj-$(CONFIG_REGULATOR_QPNP_OLEDB) += qpnp-oledb-regulator.o obj-$(CONFIG_REGULATOR_STUB) += stub-regulator.o obj-$(CONFIG_REGULATOR_KRYO) += kryo-regulator.o obj-$(CONFIG_REGULATOR_CPR2_GFX) += cpr2-gfx-regulator.o diff --git a/drivers/regulator/cpr4-mmss-ldo-regulator.c b/drivers/regulator/cpr4-mmss-ldo-regulator.c index 9fa5c309b02a..2843f71745fc 100644 --- a/drivers/regulator/cpr4-mmss-ldo-regulator.c +++ b/drivers/regulator/cpr4-mmss-ldo-regulator.c @@ -36,10 +36,10 @@ #include "cpr3-regulator.h" -#define MSMFALCON_MMSS_FUSE_CORNERS 6 +#define SDM660_MMSS_FUSE_CORNERS 6 /** - * struct cpr4_msmfalcon_mmss_fuses - MMSS specific fuse data for MSMFALCON + * struct cpr4_sdm660_mmss_fuses - MMSS specific fuse data for SDM660 * @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value * for each fuse corner (raw, not converted to a voltage) * @offset_voltage: The closed-loop voltage margin adjustment fuse parameter @@ -55,19 +55,19 @@ * * This struct holds the values for all of the fuses read from memory. */ -struct cpr4_msmfalcon_mmss_fuses { - u64 init_voltage[MSMFALCON_MMSS_FUSE_CORNERS]; - u64 offset_voltage[MSMFALCON_MMSS_FUSE_CORNERS]; +struct cpr4_sdm660_mmss_fuses { + u64 init_voltage[SDM660_MMSS_FUSE_CORNERS]; + u64 offset_voltage[SDM660_MMSS_FUSE_CORNERS]; u64 cpr_fusing_rev; - u64 ldo_enable[MSMFALCON_MMSS_FUSE_CORNERS]; + u64 ldo_enable[SDM660_MMSS_FUSE_CORNERS]; u64 ldo_cpr_cl_enable; }; /* Fuse combos 0 - 7 map to CPR fusing revision 0 - 7 */ -#define CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT 8 +#define CPR4_SDM660_MMSS_FUSE_COMBO_COUNT 8 /* - * MSMFALCON MMSS fuse parameter locations: + * SDM660 MMSS fuse parameter locations: * * Structs are organized with the following dimensions: * Outer: 0 to 3 for fuse corners from lowest to highest corner @@ -79,7 +79,7 @@ struct cpr4_msmfalcon_mmss_fuses { * a given parameter may correspond to different fuse rows. */ static const struct cpr3_fuse_param -msmfalcon_mmss_init_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { +sdm660_mmss_init_voltage_param[SDM660_MMSS_FUSE_CORNERS][2] = { {{65, 39, 43}, {} }, {{65, 39, 43}, {} }, {{65, 34, 38}, {} }, @@ -88,13 +88,13 @@ msmfalcon_mmss_init_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { {{65, 24, 28}, {} }, }; -static const struct cpr3_fuse_param msmfalcon_cpr_fusing_rev_param[] = { +static const struct cpr3_fuse_param sdm660_cpr_fusing_rev_param[] = { {71, 34, 36}, {}, }; static const struct cpr3_fuse_param -msmfalcon_mmss_offset_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { +sdm660_mmss_offset_voltage_param[SDM660_MMSS_FUSE_CORNERS][2] = { {{} }, {{} }, {{} }, @@ -104,7 +104,7 @@ msmfalcon_mmss_offset_voltage_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { }; static const struct cpr3_fuse_param -msmfalcon_mmss_ldo_enable_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { +sdm660_mmss_ldo_enable_param[SDM660_MMSS_FUSE_CORNERS][2] = { {{73, 62, 62}, {} }, {{73, 61, 61}, {} }, {{73, 60, 60}, {} }, @@ -113,53 +113,53 @@ msmfalcon_mmss_ldo_enable_param[MSMFALCON_MMSS_FUSE_CORNERS][2] = { {{73, 57, 57}, {} }, }; -static const struct cpr3_fuse_param msmfalcon_ldo_cpr_cl_enable_param[] = { +static const struct cpr3_fuse_param sdm660_ldo_cpr_cl_enable_param[] = { {71, 38, 38}, {}, }; -/* Additional MSMFALCON specific data: */ +/* Additional SDM660 specific data: */ /* Open loop voltage fuse reference voltages in microvolts */ -static const int msmfalcon_mmss_fuse_ref_volt[MSMFALCON_MMSS_FUSE_CORNERS] = { - 584000, - 644000, - 724000, - 788000, - 868000, - 924000, +static const int sdm660_mmss_fuse_ref_volt[SDM660_MMSS_FUSE_CORNERS] = { + 585000, + 645000, + 725000, + 790000, + 870000, + 925000, }; -#define MSMFALCON_MMSS_FUSE_STEP_VOLT 10000 -#define MSMFALCON_MMSS_OFFSET_FUSE_STEP_VOLT 10000 -#define MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE 5 +#define SDM660_MMSS_FUSE_STEP_VOLT 10000 +#define SDM660_MMSS_OFFSET_FUSE_STEP_VOLT 10000 +#define SDM660_MMSS_VOLTAGE_FUSE_SIZE 5 -#define MSMFALCON_MMSS_CPR_SENSOR_COUNT 11 +#define SDM660_MMSS_CPR_SENSOR_COUNT 11 -#define MSMFALCON_MMSS_CPR_CLOCK_RATE 19200000 +#define SDM660_MMSS_CPR_CLOCK_RATE 19200000 /** - * cpr4_msmfalcon_mmss_read_fuse_data() - load MMSS specific fuse parameter + * cpr4_sdm660_mmss_read_fuse_data() - load MMSS specific fuse parameter * values * @vreg: Pointer to the CPR3 regulator * - * This function allocates a cpr4_msmfalcon_mmss_fuses struct, fills it with + * This function allocates a cpr4_sdm660_mmss_fuses struct, fills it with * values read out of hardware fuses, and finally copies common fuse values * into the regulator struct. * * Return: 0 on success, errno on failure */ -static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) +static int cpr4_sdm660_mmss_read_fuse_data(struct cpr3_regulator *vreg) { void __iomem *base = vreg->thread->ctrl->fuse_base; - struct cpr4_msmfalcon_mmss_fuses *fuse; + struct cpr4_sdm660_mmss_fuses *fuse; int i, rc; fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL); if (!fuse) return -ENOMEM; - rc = cpr3_read_fuse_param(base, msmfalcon_cpr_fusing_rev_param, + rc = cpr3_read_fuse_param(base, sdm660_cpr_fusing_rev_param, &fuse->cpr_fusing_rev); if (rc) { cpr3_err(vreg, "Unable to read CPR fusing revision fuse, rc=%d\n", @@ -168,7 +168,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev); - rc = cpr3_read_fuse_param(base, msmfalcon_ldo_cpr_cl_enable_param, + rc = cpr3_read_fuse_param(base, sdm660_ldo_cpr_cl_enable_param, &fuse->ldo_cpr_cl_enable); if (rc) { cpr3_err(vreg, "Unable to read ldo cpr closed-loop enable fuse, rc=%d\n", @@ -176,9 +176,9 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) return rc; } - for (i = 0; i < MSMFALCON_MMSS_FUSE_CORNERS; i++) { + for (i = 0; i < SDM660_MMSS_FUSE_CORNERS; i++) { rc = cpr3_read_fuse_param(base, - msmfalcon_mmss_init_voltage_param[i], + sdm660_mmss_init_voltage_param[i], &fuse->init_voltage[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n", @@ -187,7 +187,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msmfalcon_mmss_offset_voltage_param[i], + sdm660_mmss_offset_voltage_param[i], &fuse->offset_voltage[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d offset voltage fuse, rc=%d\n", @@ -196,7 +196,7 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msmfalcon_mmss_ldo_enable_param[i], + sdm660_mmss_ldo_enable_param[i], &fuse->ldo_enable[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d ldo enable fuse, rc=%d\n", @@ -206,31 +206,31 @@ static int cpr4_msmfalcon_mmss_read_fuse_data(struct cpr3_regulator *vreg) } vreg->fuse_combo = fuse->cpr_fusing_rev; - if (vreg->fuse_combo >= CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT) { + if (vreg->fuse_combo >= CPR4_SDM660_MMSS_FUSE_COMBO_COUNT) { cpr3_err(vreg, "invalid CPR fuse combo = %d found, not in range 0 - %d\n", vreg->fuse_combo, - CPR4_MSMFALCON_MMSS_FUSE_COMBO_COUNT - 1); + CPR4_SDM660_MMSS_FUSE_COMBO_COUNT - 1); return -EINVAL; } vreg->cpr_rev_fuse = fuse->cpr_fusing_rev; - vreg->fuse_corner_count = MSMFALCON_MMSS_FUSE_CORNERS; + vreg->fuse_corner_count = SDM660_MMSS_FUSE_CORNERS; vreg->platform_fuses = fuse; return 0; } /** - * cpr3_msmfalcon_mmss_calculate_open_loop_voltages() - calculate the open-loop + * cpr3_sdm660_mmss_calculate_open_loop_voltages() - calculate the open-loop * voltage for each corner of a CPR3 regulator * @vreg: Pointer to the CPR3 regulator * * Return: 0 on success, errno on failure */ -static int cpr4_msmfalcon_mmss_calculate_open_loop_voltages( +static int cpr4_sdm660_mmss_calculate_open_loop_voltages( struct cpr3_regulator *vreg) { - struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses; + struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses; int i, rc = 0; const int *ref_volt; int *fuse_volt; @@ -240,11 +240,11 @@ static int cpr4_msmfalcon_mmss_calculate_open_loop_voltages( if (!fuse_volt) return -ENOMEM; - ref_volt = msmfalcon_mmss_fuse_ref_volt; + ref_volt = sdm660_mmss_fuse_ref_volt; for (i = 0; i < vreg->fuse_corner_count; i++) { fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(ref_volt[i], - MSMFALCON_MMSS_FUSE_STEP_VOLT, fuse->init_voltage[i], - MSMFALCON_MMSS_VOLTAGE_FUSE_SIZE); + SDM660_MMSS_FUSE_STEP_VOLT, fuse->init_voltage[i], + SDM660_MMSS_VOLTAGE_FUSE_SIZE); cpr3_info(vreg, "fuse_corner[%d] open-loop=%7d uV\n", i, fuse_volt[i]); } @@ -298,7 +298,7 @@ done: */ static int cpr4_mmss_parse_ldo_mode_data(struct cpr3_regulator *vreg) { - struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses; + struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses; int i, rc = 0; u32 *ldo_allowed; char *prop_str = "qcom,cpr-corner-allow-ldo-mode"; @@ -341,7 +341,7 @@ done: */ static int cpr4_mmss_parse_corner_operating_mode(struct cpr3_regulator *vreg) { - struct cpr4_msmfalcon_mmss_fuses *fuse = vreg->platform_fuses; + struct cpr4_sdm660_mmss_fuses *fuse = vreg->platform_fuses; int i, rc = 0; u32 *use_closed_loop; char *prop_str = "qcom,cpr-corner-allow-closed-loop"; @@ -476,7 +476,7 @@ static int cpr4_mmss_init_thread(struct cpr3_thread *thread) vreg->ldo_regulator_bypass = BHS_MODE; vreg->ldo_type = CPR3_LDO300; - rc = cpr4_msmfalcon_mmss_read_fuse_data(vreg); + rc = cpr4_sdm660_mmss_read_fuse_data(vreg); if (rc) { cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc); return rc; @@ -489,7 +489,7 @@ static int cpr4_mmss_init_thread(struct cpr3_thread *thread) return rc; } - rc = cpr4_msmfalcon_mmss_calculate_open_loop_voltages(vreg); + rc = cpr4_sdm660_mmss_calculate_open_loop_voltages(vreg); if (rc) { cpr3_err(vreg, "unable to calculate open-loop voltages, rc=%d\n", rc); @@ -548,7 +548,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl) return rc; } - ctrl->sensor_count = MSMFALCON_MMSS_CPR_SENSOR_COUNT; + ctrl->sensor_count = SDM660_MMSS_CPR_SENSOR_COUNT; /* * MMSS only has one thread (0) so the zeroed array does not need @@ -559,7 +559,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl) if (!ctrl->sensor_owner) return -ENOMEM; - ctrl->cpr_clock_rate = MSMFALCON_MMSS_CPR_CLOCK_RATE; + ctrl->cpr_clock_rate = SDM660_MMSS_CPR_CLOCK_RATE; ctrl->ctrl_type = CPR_CTRL_TYPE_CPR4; ctrl->support_ldo300_vreg = true; @@ -572,7 +572,7 @@ static int cpr4_mmss_init_controller(struct cpr3_controller *ctrl) &ctrl->step_quot_fixed); ctrl->use_dynamic_step_quot = !ctrl->step_quot_fixed; - /* iface_clk is optional for msmfalcon */ + /* iface_clk is optional for sdm660 */ ctrl->iface_clk = NULL; ctrl->bus_clk = devm_clk_get(ctrl->dev, "bus_clk"); if (IS_ERR(ctrl->bus_clk)) { @@ -688,7 +688,7 @@ static int cpr4_mmss_regulator_resume(struct platform_device *pdev) /* Data corresponds to the SoC revision */ static const struct of_device_id cpr4_mmss_regulator_match_table[] = { { - .compatible = "qcom,cpr4-msmfalcon-mmss-ldo-regulator", + .compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator", .data = (void *)NULL, }, }; diff --git a/drivers/regulator/cprh-kbss-regulator.c b/drivers/regulator/cprh-kbss-regulator.c index 9cbd1ee18ec3..0472ce13197b 100644 --- a/drivers/regulator/cprh-kbss-regulator.c +++ b/drivers/regulator/cprh-kbss-regulator.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -36,9 +36,10 @@ #include "cpr3-regulator.h" #define MSM8998_KBSS_FUSE_CORNERS 4 +#define SDM660_KBSS_FUSE_CORNERS 5 /** - * struct cprh_msm8998_kbss_fuses - KBSS specific fuse data for MSM8998 + * struct cprh_kbss_fuses - KBSS specific fuse data * @ro_sel: Ring oscillator select fuse parameter value for each * fuse corner * @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value @@ -59,11 +60,11 @@ * * This struct holds the values for all of the fuses read from memory. */ -struct cprh_msm8998_kbss_fuses { - u64 ro_sel[MSM8998_KBSS_FUSE_CORNERS]; - u64 init_voltage[MSM8998_KBSS_FUSE_CORNERS]; - u64 target_quot[MSM8998_KBSS_FUSE_CORNERS]; - u64 quot_offset[MSM8998_KBSS_FUSE_CORNERS]; +struct cprh_kbss_fuses { + u64 *ro_sel; + u64 *init_voltage; + u64 *target_quot; + u64 *quot_offset; u64 speed_bin; u64 cpr_fusing_rev; u64 force_highest_corner; @@ -76,7 +77,8 @@ struct cprh_msm8998_kbss_fuses { * Fuse combos 16 - 23 map to CPR fusing revision 0 - 7 with speed bin fuse = 2. * Fuse combos 24 - 31 map to CPR fusing revision 0 - 7 with speed bin fuse = 3. */ -#define CPRH_MSM8998_KBSS_FUSE_COMBO_COUNT 32 +#define CPRH_MSM8998_KBSS_FUSE_COMBO_COUNT 32 +#define CPRH_SDM660_KBSS_FUSE_COMBO_COUNT 16 /* * Constants which define the name of each fuse corner. @@ -95,13 +97,45 @@ static const char * const cprh_msm8998_kbss_fuse_corner_name[] = { [CPRH_MSM8998_KBSS_FUSE_CORNER_TURBO_L1] = "TURBO_L1", }; +enum cprh_sdm660_power_kbss_fuse_corner { + CPRH_SDM660_POWER_KBSS_FUSE_CORNER_LOWSVS = 0, + CPRH_SDM660_POWER_KBSS_FUSE_CORNER_SVS = 1, + CPRH_SDM660_POWER_KBSS_FUSE_CORNER_SVSPLUS = 2, + CPRH_SDM660_POWER_KBSS_FUSE_CORNER_NOM = 3, + CPRH_SDM660_POWER_KBSS_FUSE_CORNER_TURBO_L1 = 4, +}; + +static const char * const cprh_sdm660_power_kbss_fuse_corner_name[] = { + [CPRH_SDM660_POWER_KBSS_FUSE_CORNER_LOWSVS] = "LowSVS", + [CPRH_SDM660_POWER_KBSS_FUSE_CORNER_SVS] = "SVS", + [CPRH_SDM660_POWER_KBSS_FUSE_CORNER_SVSPLUS] = "SVSPLUS", + [CPRH_SDM660_POWER_KBSS_FUSE_CORNER_NOM] = "NOM", + [CPRH_SDM660_POWER_KBSS_FUSE_CORNER_TURBO_L1] = "TURBO_L1", +}; + +enum cprh_sdm660_perf_kbss_fuse_corner { + CPRH_SDM660_PERF_KBSS_FUSE_CORNER_SVS = 0, + CPRH_SDM660_PERF_KBSS_FUSE_CORNER_SVSPLUS = 1, + CPRH_SDM660_PERF_KBSS_FUSE_CORNER_NOM = 2, + CPRH_SDM660_PERF_KBSS_FUSE_CORNER_TURBO = 3, + CPRH_SDM660_PERF_KBSS_FUSE_CORNER_TURBO_L2 = 4, +}; + +static const char * const cprh_sdm660_perf_kbss_fuse_corner_name[] = { + [CPRH_SDM660_PERF_KBSS_FUSE_CORNER_SVS] = "SVS", + [CPRH_SDM660_PERF_KBSS_FUSE_CORNER_SVSPLUS] = "SVSPLUS", + [CPRH_SDM660_PERF_KBSS_FUSE_CORNER_NOM] = "NOM", + [CPRH_SDM660_PERF_KBSS_FUSE_CORNER_TURBO] = "TURBO", + [CPRH_SDM660_PERF_KBSS_FUSE_CORNER_TURBO_L2] = "TURBO_L2", +}; + /* KBSS cluster IDs */ -#define MSM8998_KBSS_POWER_CLUSTER_ID 0 -#define MSM8998_KBSS_PERFORMANCE_CLUSTER_ID 1 +#define CPRH_KBSS_POWER_CLUSTER_ID 0 +#define CPRH_KBSS_PERFORMANCE_CLUSTER_ID 1 /* KBSS controller IDs */ -#define MSM8998_KBSS_MIN_CONTROLLER_ID 0 -#define MSM8998_KBSS_MAX_CONTROLLER_ID 1 +#define CPRH_KBSS_MIN_CONTROLLER_ID 0 +#define CPRH_KBSS_MAX_CONTROLLER_ID 1 /* * MSM8998 KBSS fuse parameter locations: @@ -119,13 +153,13 @@ static const char * const cprh_msm8998_kbss_fuse_corner_name[] = { */ static const struct cpr3_fuse_param msm8998_kbss_ro_sel_param[2][MSM8998_KBSS_FUSE_CORNERS][2] = { - [MSM8998_KBSS_POWER_CLUSTER_ID] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { {{67, 12, 15}, {} }, {{67, 8, 11}, {} }, {{67, 4, 7}, {} }, {{67, 0, 3}, {} }, }, - [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { {{69, 26, 29}, {} }, {{69, 22, 25}, {} }, {{69, 18, 21}, {} }, @@ -134,14 +168,32 @@ msm8998_kbss_ro_sel_param[2][MSM8998_KBSS_FUSE_CORNERS][2] = { }; static const struct cpr3_fuse_param +sdm660_kbss_ro_sel_param[2][SDM660_KBSS_FUSE_CORNERS][3] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { + {{67, 12, 15}, {} }, + {{67, 8, 11}, {} }, + {{65, 56, 59}, {} }, + {{67, 4, 7}, {} }, + {{67, 0, 3}, {} }, + }, + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { + {{68, 61, 63}, {69, 0, 0} }, + {{69, 1, 4}, {} }, + {{68, 57, 60}, {} }, + {{68, 53, 56}, {} }, + {{66, 14, 17}, {} }, + }, +}; + +static const struct cpr3_fuse_param msm8998_kbss_init_voltage_param[2][MSM8998_KBSS_FUSE_CORNERS][2] = { - [MSM8998_KBSS_POWER_CLUSTER_ID] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { {{67, 34, 39}, {} }, {{67, 28, 33}, {} }, {{67, 22, 27}, {} }, {{67, 16, 21}, {} }, }, - [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { {{69, 48, 53}, {} }, {{69, 42, 47}, {} }, {{69, 36, 41}, {} }, @@ -150,14 +202,32 @@ msm8998_kbss_init_voltage_param[2][MSM8998_KBSS_FUSE_CORNERS][2] = { }; static const struct cpr3_fuse_param +sdm660_kbss_init_voltage_param[2][SDM660_KBSS_FUSE_CORNERS][2] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { + {{67, 34, 39}, {} }, + {{67, 28, 33}, {} }, + {{71, 3, 8}, {} }, + {{67, 22, 27}, {} }, + {{67, 16, 21}, {} }, + }, + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { + {{69, 17, 22}, {} }, + {{69, 23, 28}, {} }, + {{69, 11, 16}, {} }, + {{69, 5, 10}, {} }, + {{70, 42, 47}, {} }, + }, +}; + +static const struct cpr3_fuse_param msm8998_kbss_target_quot_param[2][MSM8998_KBSS_FUSE_CORNERS][3] = { - [MSM8998_KBSS_POWER_CLUSTER_ID] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { {{68, 18, 29}, {} }, {{68, 6, 17}, {} }, {{67, 58, 63}, {68, 0, 5} }, {{67, 46, 57}, {} }, }, - [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { {{70, 32, 43}, {} }, {{70, 20, 31}, {} }, {{70, 8, 19}, {} }, @@ -166,14 +236,32 @@ msm8998_kbss_target_quot_param[2][MSM8998_KBSS_FUSE_CORNERS][3] = { }; static const struct cpr3_fuse_param +sdm660_kbss_target_quot_param[2][SDM660_KBSS_FUSE_CORNERS][3] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { + {{68, 12, 23}, {} }, + {{68, 0, 11}, {} }, + {{71, 9, 20}, {} }, + {{67, 52, 63}, {} }, + {{67, 40, 51}, {} }, + }, + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { + {{69, 53, 63}, {70, 0, 0}, {} }, + {{70, 1, 12}, {} }, + {{69, 41, 52}, {} }, + {{69, 29, 40}, {} }, + {{70, 48, 59}, {} }, + }, +}; + +static const struct cpr3_fuse_param msm8998_kbss_quot_offset_param[2][MSM8998_KBSS_FUSE_CORNERS][3] = { - [MSM8998_KBSS_POWER_CLUSTER_ID] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { {{} }, {{68, 63, 63}, {69, 0, 5}, {} }, {{68, 56, 62}, {} }, {{68, 49, 55}, {} }, }, - [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { {{} }, {{71, 13, 15}, {71, 21, 24}, {} }, {{71, 6, 12}, {} }, @@ -181,12 +269,35 @@ msm8998_kbss_quot_offset_param[2][MSM8998_KBSS_FUSE_CORNERS][3] = { }, }; +static const struct cpr3_fuse_param +sdm660_kbss_quot_offset_param[2][SDM660_KBSS_FUSE_CORNERS][3] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { + {{} }, + {{68, 38, 44}, {} }, + {{71, 21, 27}, {} }, + {{68, 31, 37}, {} }, + {{68, 24, 30}, {} }, + }, + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { + {{} }, + {{70, 27, 33}, {} }, + {{70, 20, 26}, {} }, + {{70, 13, 19}, {} }, + {{70, 60, 63}, {71, 0, 2}, {} }, + }, +}; + static const struct cpr3_fuse_param msm8998_cpr_fusing_rev_param[] = { {39, 51, 53}, {}, }; -static const struct cpr3_fuse_param msm8998_kbss_speed_bin_param[] = { +static const struct cpr3_fuse_param sdm660_cpr_fusing_rev_param[] = { + {71, 28, 30}, + {}, +}; + +static const struct cpr3_fuse_param kbss_speed_bin_param[] = { {38, 29, 31}, {}, }; @@ -199,16 +310,28 @@ msm8998_cpr_force_highest_corner_param[] = { static const struct cpr3_fuse_param msm8998_kbss_aging_init_quot_diff_param[2][2] = { - [MSM8998_KBSS_POWER_CLUSTER_ID] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { {69, 6, 13}, {}, }, - [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { {71, 25, 32}, {}, }, }; +static const struct cpr3_fuse_param +sdm660_kbss_aging_init_quot_diff_param[2][2] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { + {68, 45, 52}, + {}, + }, + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { + {70, 34, 41}, + {}, + }, +}; + /* * Open loop voltage fuse reference voltages in microvolts for MSM8998 v1 */ @@ -225,13 +348,13 @@ msm8998_v1_kbss_fuse_ref_volt[MSM8998_KBSS_FUSE_CORNERS] = { */ static const int msm8998_v2_kbss_fuse_ref_volt[2][MSM8998_KBSS_FUSE_CORNERS] = { - [MSM8998_KBSS_POWER_CLUSTER_ID] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { 688000, 756000, 828000, 1056000, }, - [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { 756000, 756000, 828000, @@ -239,24 +362,49 @@ msm8998_v2_kbss_fuse_ref_volt[2][MSM8998_KBSS_FUSE_CORNERS] = { }, }; -#define MSM8998_KBSS_FUSE_STEP_VOLT 10000 -#define MSM8998_KBSS_VOLTAGE_FUSE_SIZE 6 -#define MSM8998_KBSS_QUOT_OFFSET_SCALE 5 -#define MSM8998_KBSS_AGING_INIT_QUOT_DIFF_SIZE 8 -#define MSM8998_KBSS_AGING_INIT_QUOT_DIFF_SCALE 1 +/* + * Open loop voltage fuse reference voltages in microvolts for SDM660 + */ +static const int +sdm660_kbss_fuse_ref_volt[2][SDM660_KBSS_FUSE_CORNERS] = { + [CPRH_KBSS_POWER_CLUSTER_ID] = { + 644000, + 724000, + 788000, + 868000, + 1068000, + }, + [CPRH_KBSS_PERFORMANCE_CLUSTER_ID] = { + 724000, + 788000, + 868000, + 988000, + 1068000, + }, +}; -#define MSM8998_KBSS_POWER_CPR_SENSOR_COUNT 6 -#define MSM8998_KBSS_PERFORMANCE_CPR_SENSOR_COUNT 9 +#define CPRH_KBSS_FUSE_STEP_VOLT 10000 +#define CPRH_KBSS_VOLTAGE_FUSE_SIZE 6 +#define CPRH_KBSS_QUOT_OFFSET_SCALE 5 +#define CPRH_KBSS_AGING_INIT_QUOT_DIFF_SIZE 8 +#define CPRH_KBSS_AGING_INIT_QUOT_DIFF_SCALE 1 -#define MSM8998_KBSS_CPR_CLOCK_RATE 19200000 +#define CPRH_KBSS_CPR_CLOCK_RATE 19200000 -#define MSM8998_KBSS_MAX_CORNER_BAND_COUNT 4 -#define MSM8998_KBSS_MAX_CORNER_COUNT 40 +#define CPRH_KBSS_MAX_CORNER_BAND_COUNT 4 +#define CPRH_KBSS_MAX_CORNER_COUNT 40 -#define MSM8998_KBSS_CPR_SDELTA_CORE_COUNT 4 +#define CPRH_KBSS_CPR_SDELTA_CORE_COUNT 4 -#define MSM8998_KBSS_MAX_TEMP_POINTS 3 -#define MSM8998_KBSS_POWER_TEMP_SENSOR_ID_START 1 +#define CPRH_KBSS_MAX_TEMP_POINTS 3 + +/* + * msm8998 configuration + */ +#define MSM8998_KBSS_POWER_CPR_SENSOR_COUNT 6 +#define MSM8998_KBSS_PERFORMANCE_CPR_SENSOR_COUNT 9 + +#define MSM8998_KBSS_POWER_TEMP_SENSOR_ID_START 1 #define MSM8998_KBSS_POWER_TEMP_SENSOR_ID_END 5 #define MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START 6 #define MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_END 10 @@ -267,34 +415,49 @@ msm8998_v2_kbss_fuse_ref_volt[2][MSM8998_KBSS_FUSE_CORNERS] = { #define MSM8998_KBSS_PERFORMANCE_AGING_SENSOR_ID 0 #define MSM8998_KBSS_PERFORMANCE_AGING_BYPASS_MASK0 0 +/* + * sdm660 configuration + */ +#define SDM660_KBSS_POWER_CPR_SENSOR_COUNT 6 +#define SDM660_KBSS_PERFORMANCE_CPR_SENSOR_COUNT 9 + +#define SDM660_KBSS_POWER_TEMP_SENSOR_ID_START 10 +#define SDM660_KBSS_POWER_TEMP_SENSOR_ID_END 11 +#define SDM660_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START 4 +#define SDM660_KBSS_PERFORMANCE_TEMP_SENSOR_ID_END 9 + +#define SDM660_KBSS_POWER_AGING_SENSOR_ID 0 +#define SDM660_KBSS_POWER_AGING_BYPASS_MASK0 0 + +#define SDM660_KBSS_PERFORMANCE_AGING_SENSOR_ID 0 +#define SDM660_KBSS_PERFORMANCE_AGING_BYPASS_MASK0 0 + +/* + * SOC IDs + */ +enum soc_id { + MSM8998_V1_SOC_ID = 1, + MSM8998_V2_SOC_ID = 2, + SDM660_SOC_ID = 3, +}; + /** - * cprh_msm8998_kbss_read_fuse_data() - load KBSS specific fuse parameter values + * cprh_msm8998_kbss_read_fuse_data() - load msm8998 KBSS specific fuse + * parameter values * @vreg: Pointer to the CPR3 regulator + * @fuse: KBSS specific fuse data * - * This function allocates a cprh_msm8998_kbss_fuses struct, fills it with - * values read out of hardware fuses, and finally copies common fuse values - * into the CPR3 regulator struct. + * This function fills cprh_kbss_fuses struct with values read out of hardware + * fuses. * * Return: 0 on success, errno on failure */ -static int cprh_msm8998_kbss_read_fuse_data(struct cpr3_regulator *vreg) +static int cprh_msm8998_kbss_read_fuse_data(struct cpr3_regulator *vreg, + struct cprh_kbss_fuses *fuse) { void __iomem *base = vreg->thread->ctrl->fuse_base; - struct cprh_msm8998_kbss_fuses *fuse; int i, id, rc; - fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL); - if (!fuse) - return -ENOMEM; - - rc = cpr3_read_fuse_param(base, msm8998_kbss_speed_bin_param, - &fuse->speed_bin); - if (rc) { - cpr3_err(vreg, "Unable to read speed bin fuse, rc=%d\n", rc); - return rc; - } - cpr3_info(vreg, "speed bin = %llu\n", fuse->speed_bin); - rc = cpr3_read_fuse_param(base, msm8998_cpr_fusing_rev_param, &fuse->cpr_fusing_rev); if (rc) { @@ -305,7 +468,6 @@ static int cprh_msm8998_kbss_read_fuse_data(struct cpr3_regulator *vreg) cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev); id = vreg->thread->ctrl->ctrl_id; - for (i = 0; i < MSM8998_KBSS_FUSE_CORNERS; i++) { rc = cpr3_read_fuse_param(base, msm8998_kbss_init_voltage_param[id][i], @@ -355,8 +517,8 @@ static int cprh_msm8998_kbss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msm8998_cpr_force_highest_corner_param, - &fuse->force_highest_corner); + msm8998_cpr_force_highest_corner_param, + &fuse->force_highest_corner); if (rc) { cpr3_err(vreg, "Unable to read CPR force highest corner fuse, rc=%d\n", rc); @@ -373,9 +535,174 @@ static int cprh_msm8998_kbss_read_fuse_data(struct cpr3_regulator *vreg) return -EINVAL; } + return rc; +}; + +/** + * cprh_sdm660_kbss_read_fuse_data() - load SDM660 KBSS specific fuse parameter + * values + * @vreg: Pointer to the CPR3 regulator + * @fuse: KBSS specific fuse data + * + * This function fills cprh_kbss_fuses struct with values read out of hardware + * fuses. + * + * Return: 0 on success, errno on failure + */ +static int cprh_sdm660_kbss_read_fuse_data(struct cpr3_regulator *vreg, + struct cprh_kbss_fuses *fuse) +{ + void __iomem *base = vreg->thread->ctrl->fuse_base; + int i, id, rc; + + rc = cpr3_read_fuse_param(base, sdm660_cpr_fusing_rev_param, + &fuse->cpr_fusing_rev); + if (rc) { + cpr3_err(vreg, "Unable to read CPR fusing revision fuse, rc=%d\n", + rc); + return rc; + } + cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev); + + id = vreg->thread->ctrl->ctrl_id; + for (i = 0; i < SDM660_KBSS_FUSE_CORNERS; i++) { + rc = cpr3_read_fuse_param(base, + sdm660_kbss_init_voltage_param[id][i], + &fuse->init_voltage[i]); + if (rc) { + cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n", + i, rc); + return rc; + } + + rc = cpr3_read_fuse_param(base, + sdm660_kbss_target_quot_param[id][i], + &fuse->target_quot[i]); + if (rc) { + cpr3_err(vreg, "Unable to read fuse-corner %d target quotient fuse, rc=%d\n", + i, rc); + return rc; + } + + rc = cpr3_read_fuse_param(base, + sdm660_kbss_ro_sel_param[id][i], + &fuse->ro_sel[i]); + if (rc) { + cpr3_err(vreg, "Unable to read fuse-corner %d RO select fuse, rc=%d\n", + i, rc); + return rc; + } + + rc = cpr3_read_fuse_param(base, + sdm660_kbss_quot_offset_param[id][i], + &fuse->quot_offset[i]); + if (rc) { + cpr3_err(vreg, "Unable to read fuse-corner %d quotient offset fuse, rc=%d\n", + i, rc); + return rc; + } + } + + rc = cpr3_read_fuse_param(base, + sdm660_kbss_aging_init_quot_diff_param[id], + &fuse->aging_init_quot_diff); + if (rc) { + cpr3_err(vreg, "Unable to read aging initial quotient difference fuse, rc=%d\n", + rc); + return rc; + } + + vreg->fuse_combo = fuse->cpr_fusing_rev + 8 * fuse->speed_bin; + if (vreg->fuse_combo >= CPRH_SDM660_KBSS_FUSE_COMBO_COUNT) { + cpr3_err(vreg, "invalid CPR fuse combo = %d found\n", + vreg->fuse_combo); + return -EINVAL; + } + + return rc; +}; + +/** + * cprh_kbss_read_fuse_data() - load KBSS specific fuse parameter values + * @vreg: Pointer to the CPR3 regulator + * + * This function allocates a cprh_kbss_fuses struct, fills it with values + * read out of hardware fuses, and finally copies common fuse values + * into the CPR3 regulator struct. + * + * Return: 0 on success, errno on failure + */ +static int cprh_kbss_read_fuse_data(struct cpr3_regulator *vreg) +{ + void __iomem *base = vreg->thread->ctrl->fuse_base; + struct cprh_kbss_fuses *fuse; + int rc, fuse_corners; + enum soc_id soc_revision; + + fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL); + if (!fuse) + return -ENOMEM; + + soc_revision = vreg->thread->ctrl->soc_revision; + switch (soc_revision) { + case SDM660_SOC_ID: + fuse_corners = SDM660_KBSS_FUSE_CORNERS; + break; + case MSM8998_V1_SOC_ID: + case MSM8998_V2_SOC_ID: + fuse_corners = MSM8998_KBSS_FUSE_CORNERS; + break; + default: + cpr3_err(vreg, "unsupported soc id = %d\n", soc_revision); + return -EINVAL; + } + + fuse->ro_sel = devm_kcalloc(vreg->thread->ctrl->dev, fuse_corners, + sizeof(*fuse->ro_sel), GFP_KERNEL); + fuse->init_voltage = devm_kcalloc(vreg->thread->ctrl->dev, fuse_corners, + sizeof(*fuse->init_voltage), GFP_KERNEL); + fuse->target_quot = devm_kcalloc(vreg->thread->ctrl->dev, fuse_corners, + sizeof(*fuse->target_quot), GFP_KERNEL); + fuse->quot_offset = devm_kcalloc(vreg->thread->ctrl->dev, fuse_corners, + sizeof(*fuse->quot_offset), GFP_KERNEL); + + if (!fuse->ro_sel || !fuse->init_voltage || !fuse->target_quot + || !fuse->quot_offset) + return -ENOMEM; + + rc = cpr3_read_fuse_param(base, kbss_speed_bin_param, &fuse->speed_bin); + if (rc) { + cpr3_err(vreg, "Unable to read speed bin fuse, rc=%d\n", rc); + return rc; + } + cpr3_info(vreg, "speed bin = %llu\n", fuse->speed_bin); + + switch (soc_revision) { + case SDM660_SOC_ID: + rc = cprh_sdm660_kbss_read_fuse_data(vreg, fuse); + if (rc) { + cpr3_err(vreg, "sdm660 kbss fuse data read failed, rc=%d\n", + rc); + return rc; + } + break; + case MSM8998_V1_SOC_ID: + case MSM8998_V2_SOC_ID: + rc = cprh_msm8998_kbss_read_fuse_data(vreg, fuse); + if (rc) { + cpr3_err(vreg, "msm8998 kbss fuse data read failed, rc=%d\n", + rc); + return rc; + } + break; + default: + cpr3_err(vreg, "unsupported soc id = %d\n", soc_revision); + return -EINVAL; + } + vreg->speed_bin_fuse = fuse->speed_bin; vreg->cpr_rev_fuse = fuse->cpr_fusing_rev; - vreg->fuse_corner_count = MSM8998_KBSS_FUSE_CORNERS; + vreg->fuse_corner_count = fuse_corners; vreg->platform_fuses = fuse; return 0; @@ -399,13 +726,13 @@ static int cprh_kbss_parse_corner_data(struct cpr3_regulator *vreg) } /* - * A total of MSM8998_KBSS_MAX_CORNER_COUNT - 1 corners + * A total of CPRH_KBSS_MAX_CORNER_COUNT - 1 corners * may be specified in device tree as an additional corner * must be allocated to correspond to the APM crossover voltage. */ - if (vreg->corner_count > MSM8998_KBSS_MAX_CORNER_COUNT - 1) { + if (vreg->corner_count > CPRH_KBSS_MAX_CORNER_COUNT - 1) { cpr3_err(vreg, "corner count %d exceeds supported maximum %d\n", - vreg->corner_count, MSM8998_KBSS_MAX_CORNER_COUNT - 1); + vreg->corner_count, CPRH_KBSS_MAX_CORNER_COUNT - 1); return -EINVAL; } @@ -413,7 +740,7 @@ static int cprh_kbss_parse_corner_data(struct cpr3_regulator *vreg) } /** - * cprh_msm8998_kbss_calculate_open_loop_voltages() - calculate the open-loop + * cprh_kbss_calculate_open_loop_voltages() - calculate the open-loop * voltage for each corner of a CPR3 regulator * @vreg: Pointer to the CPR3 regulator * @@ -429,17 +756,18 @@ static int cprh_kbss_parse_corner_data(struct cpr3_regulator *vreg) * * Return: 0 on success, errno on failure */ -static int cprh_msm8998_kbss_calculate_open_loop_voltages( - struct cpr3_regulator *vreg) +static int cprh_kbss_calculate_open_loop_voltages(struct cpr3_regulator *vreg) { struct device_node *node = vreg->of_node; - struct cprh_msm8998_kbss_fuses *fuse = vreg->platform_fuses; - int i, j, soc_revision, id, rc = 0; + struct cprh_kbss_fuses *fuse = vreg->platform_fuses; + int i, j, id, rc = 0; bool allow_interpolation; u64 freq_low, volt_low, freq_high, volt_high; const int *ref_volt; int *fuse_volt; int *fmax_corner; + const char * const *corner_name; + enum soc_id soc_revision; fuse_volt = kcalloc(vreg->fuse_corner_count, sizeof(*fuse_volt), GFP_KERNEL); @@ -452,20 +780,36 @@ static int cprh_msm8998_kbss_calculate_open_loop_voltages( id = vreg->thread->ctrl->ctrl_id; soc_revision = vreg->thread->ctrl->soc_revision; - if (soc_revision == 1) + + switch (soc_revision) { + case SDM660_SOC_ID: + ref_volt = sdm660_kbss_fuse_ref_volt[id]; + if (id == CPRH_KBSS_POWER_CLUSTER_ID) + corner_name = cprh_sdm660_power_kbss_fuse_corner_name; + else + corner_name = cprh_sdm660_perf_kbss_fuse_corner_name; + break; + case MSM8998_V1_SOC_ID: ref_volt = msm8998_v1_kbss_fuse_ref_volt; - else + corner_name = cprh_msm8998_kbss_fuse_corner_name; + break; + case MSM8998_V2_SOC_ID: ref_volt = msm8998_v2_kbss_fuse_ref_volt[id]; + corner_name = cprh_msm8998_kbss_fuse_corner_name; + break; + default: + cpr3_err(vreg, "unsupported soc id = %d\n", soc_revision); + rc = -EINVAL; + goto done; + } for (i = 0; i < vreg->fuse_corner_count; i++) { - fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse( - ref_volt[i], - MSM8998_KBSS_FUSE_STEP_VOLT, fuse->init_voltage[i], - MSM8998_KBSS_VOLTAGE_FUSE_SIZE); + fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(ref_volt[i], + CPRH_KBSS_FUSE_STEP_VOLT, fuse->init_voltage[i], + CPRH_KBSS_VOLTAGE_FUSE_SIZE); /* Log fused open-loop voltage values for debugging purposes. */ - cpr3_info(vreg, "fused %8s: open-loop=%7d uV\n", - cprh_msm8998_kbss_fuse_corner_name[i], + cpr3_info(vreg, "fused %8s: open-loop=%7d uV\n", corner_name[i], fuse_volt[i]); } @@ -563,7 +907,7 @@ done: */ static int cprh_msm8998_partial_binning_override(struct cpr3_regulator *vreg) { - struct cprh_msm8998_kbss_fuses *fuse = vreg->platform_fuses; + struct cprh_kbss_fuses *fuse = vreg->platform_fuses; struct cpr3_corner *corner; struct cpr4_sdelta *sdelta; int i; @@ -659,11 +1003,11 @@ static int cprh_kbss_parse_core_count_temp_adj_properties( kfree(combo_corner_bands); if (vreg->corner_band_count <= 0 || - vreg->corner_band_count > MSM8998_KBSS_MAX_CORNER_BAND_COUNT || + vreg->corner_band_count > CPRH_KBSS_MAX_CORNER_BAND_COUNT || vreg->corner_band_count > vreg->corner_count) { cpr3_err(vreg, "invalid corner band count %d > %d (max) for %d corners\n", vreg->corner_band_count, - MSM8998_KBSS_MAX_CORNER_BAND_COUNT, + CPRH_KBSS_MAX_CORNER_BAND_COUNT, vreg->corner_count); return -EINVAL; } @@ -761,9 +1105,9 @@ static int cprh_kbss_parse_core_count_temp_adj_properties( temp_point_count = len / sizeof(u32); if (temp_point_count <= 0 || temp_point_count > - MSM8998_KBSS_MAX_TEMP_POINTS) { + CPRH_KBSS_MAX_TEMP_POINTS) { cpr3_err(ctrl, "invalid number of temperature points %d > %d (max)\n", - temp_point_count, MSM8998_KBSS_MAX_TEMP_POINTS); + temp_point_count, CPRH_KBSS_MAX_TEMP_POINTS); rc = -EINVAL; goto free_temp; } @@ -811,18 +1155,35 @@ static int cprh_kbss_parse_core_count_temp_adj_properties( goto free_temp; } - ctrl->temp_sensor_id_start = ctrl->ctrl_id == - MSM8998_KBSS_POWER_CLUSTER_ID - ? MSM8998_KBSS_POWER_TEMP_SENSOR_ID_START : - MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START; - ctrl->temp_sensor_id_end = ctrl->ctrl_id == - MSM8998_KBSS_POWER_CLUSTER_ID - ? MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START : - MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_END; + switch (ctrl->soc_revision) { + case SDM660_SOC_ID: + ctrl->temp_sensor_id_start = ctrl->ctrl_id == + CPRH_KBSS_POWER_CLUSTER_ID + ? SDM660_KBSS_POWER_TEMP_SENSOR_ID_START : + SDM660_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START; + ctrl->temp_sensor_id_end = ctrl->ctrl_id == + CPRH_KBSS_POWER_CLUSTER_ID + ? SDM660_KBSS_POWER_TEMP_SENSOR_ID_END : + SDM660_KBSS_PERFORMANCE_TEMP_SENSOR_ID_END; + break; + case MSM8998_V1_SOC_ID: + case MSM8998_V2_SOC_ID: + ctrl->temp_sensor_id_start = ctrl->ctrl_id == + CPRH_KBSS_POWER_CLUSTER_ID + ? MSM8998_KBSS_POWER_TEMP_SENSOR_ID_START : + MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START; + ctrl->temp_sensor_id_end = ctrl->ctrl_id == + CPRH_KBSS_POWER_CLUSTER_ID + ? MSM8998_KBSS_POWER_TEMP_SENSOR_ID_END : + MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_END; + break; + default: + cpr3_err(ctrl, "unsupported soc id = %d\n", ctrl->soc_revision); + rc = -EINVAL; + goto free_temp; + } ctrl->allow_temp_adj = true; - return 0; - free_temp: kfree(temp); @@ -906,8 +1267,8 @@ static int cprh_kbss_mem_acc_crossover_as_corner(struct cpr3_regulator *vreg) } /** - * cprh_msm8998_kbss_set_no_interpolation_quotients() - use the fused target - * quotient values for lower frequencies. + * cprh_kbss_set_no_interpolation_quotients() - use the fused target quotient + * values for lower frequencies. * @vreg: Pointer to the CPR3 regulator * @volt_adjust: Pointer to array of per-corner closed-loop adjustment * voltages @@ -918,11 +1279,10 @@ static int cprh_kbss_mem_acc_crossover_as_corner(struct cpr3_regulator *vreg) * * Return: 0 on success, errno on failure */ -static int cprh_msm8998_kbss_set_no_interpolation_quotients( - struct cpr3_regulator *vreg, int *volt_adjust, - int *volt_adjust_fuse, int *ro_scale) +static int cprh_kbss_set_no_interpolation_quotients(struct cpr3_regulator *vreg, + int *volt_adjust, int *volt_adjust_fuse, int *ro_scale) { - struct cprh_msm8998_kbss_fuses *fuse = vreg->platform_fuses; + struct cprh_kbss_fuses *fuse = vreg->platform_fuses; u32 quot, ro; int quot_adjust; int i, fuse_corner; @@ -949,7 +1309,7 @@ static int cprh_msm8998_kbss_set_no_interpolation_quotients( } /** - * cprh_msm8998_kbss_calculate_target_quotients() - calculate the CPR target + * cprh_kbss_calculate_target_quotients() - calculate the CPR target * quotient for each corner of a CPR3 regulator * @vreg: Pointer to the CPR3 regulator * @@ -965,10 +1325,9 @@ static int cprh_msm8998_kbss_set_no_interpolation_quotients( * * Return: 0 on success, errno on failure */ -static int cprh_msm8998_kbss_calculate_target_quotients( - struct cpr3_regulator *vreg) +static int cprh_kbss_calculate_target_quotients(struct cpr3_regulator *vreg) { - struct cprh_msm8998_kbss_fuses *fuse = vreg->platform_fuses; + struct cprh_kbss_fuses *fuse = vreg->platform_fuses; int rc; bool allow_interpolation; u64 freq_low, freq_high, prev_quot; @@ -978,18 +1337,49 @@ static int cprh_msm8998_kbss_calculate_target_quotients( int i, j, fuse_corner, quot_adjust; int *fmax_corner; int *volt_adjust, *volt_adjust_fuse, *ro_scale; + int lowest_fuse_corner, highest_fuse_corner; + const char * const *corner_name; + + switch (vreg->thread->ctrl->soc_revision) { + case SDM660_SOC_ID: + if (vreg->thread->ctrl->ctrl_id == CPRH_KBSS_POWER_CLUSTER_ID) { + corner_name = cprh_sdm660_power_kbss_fuse_corner_name; + lowest_fuse_corner = + CPRH_SDM660_POWER_KBSS_FUSE_CORNER_LOWSVS; + highest_fuse_corner = + CPRH_SDM660_POWER_KBSS_FUSE_CORNER_TURBO_L1; + } else { + corner_name = cprh_sdm660_perf_kbss_fuse_corner_name; + lowest_fuse_corner = + CPRH_SDM660_PERF_KBSS_FUSE_CORNER_SVS; + highest_fuse_corner = + CPRH_SDM660_PERF_KBSS_FUSE_CORNER_TURBO_L2; + } + break; + case MSM8998_V1_SOC_ID: + case MSM8998_V2_SOC_ID: + corner_name = cprh_msm8998_kbss_fuse_corner_name; + lowest_fuse_corner = + CPRH_MSM8998_KBSS_FUSE_CORNER_LOWSVS; + highest_fuse_corner = + CPRH_MSM8998_KBSS_FUSE_CORNER_TURBO_L1; + break; + default: + cpr3_err(vreg, "unsupported soc id = %d\n", + vreg->thread->ctrl->soc_revision); + return -EINVAL; + } /* Log fused quotient values for debugging purposes. */ - cpr3_info(vreg, "fused LowSVS: quot[%2llu]=%4llu\n", - fuse->ro_sel[CPRH_MSM8998_KBSS_FUSE_CORNER_LOWSVS], - fuse->target_quot[CPRH_MSM8998_KBSS_FUSE_CORNER_LOWSVS]); - for (i = CPRH_MSM8998_KBSS_FUSE_CORNER_SVS; - i <= CPRH_MSM8998_KBSS_FUSE_CORNER_TURBO_L1; i++) + cpr3_info(vreg, "fused %8s: quot[%2llu]=%4llu\n", + corner_name[lowest_fuse_corner], + fuse->ro_sel[lowest_fuse_corner], + fuse->target_quot[lowest_fuse_corner]); + for (i = lowest_fuse_corner + 1; i <= highest_fuse_corner; i++) cpr3_info(vreg, "fused %8s: quot[%2llu]=%4llu, quot_offset[%2llu]=%4llu\n", - cprh_msm8998_kbss_fuse_corner_name[i], - fuse->ro_sel[i], fuse->target_quot[i], + corner_name[i], fuse->ro_sel[i], fuse->target_quot[i], fuse->ro_sel[i], fuse->quot_offset[i] * - MSM8998_KBSS_QUOT_OFFSET_SCALE); + CPRH_KBSS_QUOT_OFFSET_SCALE); allow_interpolation = of_property_read_bool(vreg->of_node, "qcom,allow-quotient-interpolation"); @@ -1022,8 +1412,8 @@ static int cprh_msm8998_kbss_calculate_target_quotients( if (!allow_interpolation) { /* Use fused target quotients for lower frequencies. */ - return cprh_msm8998_kbss_set_no_interpolation_quotients( - vreg, volt_adjust, volt_adjust_fuse, ro_scale); + return cprh_kbss_set_no_interpolation_quotients(vreg, + volt_adjust, volt_adjust_fuse, ro_scale); } /* Determine highest corner mapped to each fuse corner */ @@ -1044,7 +1434,7 @@ static int cprh_msm8998_kbss_calculate_target_quotients( * Interpolation is not possible for corners mapped to the lowest fuse * corner so use the fuse corner value directly. */ - i = CPRH_MSM8998_KBSS_FUSE_CORNER_LOWSVS; + i = lowest_fuse_corner; quot_adjust = cpr3_quot_adjustment(ro_scale[i], volt_adjust_fuse[i]); quot = fuse->target_quot[i] + quot_adjust; quot_high[i] = quot_low[i] = quot; @@ -1053,19 +1443,17 @@ static int cprh_msm8998_kbss_calculate_target_quotients( cpr3_debug(vreg, "adjusted fuse corner %d RO%u target quot: %llu --> %u (%d uV)\n", i, ro, fuse->target_quot[i], quot, volt_adjust_fuse[i]); - for (i = 0; i <= fmax_corner[CPRH_MSM8998_KBSS_FUSE_CORNER_LOWSVS]; - i++) + for (i = 0; i <= fmax_corner[lowest_fuse_corner]; i++) vreg->corner[i].target_quot[ro] = quot; - for (i = CPRH_MSM8998_KBSS_FUSE_CORNER_SVS; - i < vreg->fuse_corner_count; i++) { + for (i = lowest_fuse_corner + 1; i < vreg->fuse_corner_count; i++) { quot_high[i] = fuse->target_quot[i]; if (fuse->ro_sel[i] == fuse->ro_sel[i - 1]) quot_low[i] = quot_high[i - 1]; else quot_low[i] = quot_high[i] - fuse->quot_offset[i] - * MSM8998_KBSS_QUOT_OFFSET_SCALE; + * CPRH_KBSS_QUOT_OFFSET_SCALE; if (quot_high[i] < quot_low[i]) { cpr3_debug(vreg, "quot_high[%d]=%llu < quot_low[%d]=%llu; overriding: quot_high[%d]=%llu\n", i, quot_high[i], i, quot_low[i], @@ -1203,10 +1591,10 @@ static int cprh_kbss_init_thread(struct cpr3_thread *thread) */ static int cprh_kbss_init_regulator(struct cpr3_regulator *vreg) { - struct cprh_msm8998_kbss_fuses *fuse; + struct cprh_kbss_fuses *fuse; int rc; - rc = cprh_msm8998_kbss_read_fuse_data(vreg); + rc = cprh_kbss_read_fuse_data(vreg); if (rc) { cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc); return rc; @@ -1221,7 +1609,7 @@ static int cprh_kbss_init_regulator(struct cpr3_regulator *vreg) return rc; } - rc = cprh_msm8998_kbss_calculate_open_loop_voltages(vreg); + rc = cprh_kbss_calculate_open_loop_voltages(vreg); if (rc) { cpr3_err(vreg, "unable to calculate open-loop voltages, rc=%d\n", rc); @@ -1246,7 +1634,7 @@ static int cprh_kbss_init_regulator(struct cpr3_regulator *vreg) return rc; } - rc = cprh_msm8998_kbss_calculate_target_quotients(vreg); + rc = cprh_kbss_calculate_target_quotients(vreg); if (rc) { cpr3_err(vreg, "unable to calculate target quotients, rc=%d\n", rc); @@ -1269,7 +1657,7 @@ static int cprh_kbss_init_regulator(struct cpr3_regulator *vreg) if (vreg->allow_core_count_adj && (vreg->max_core_count <= 0 || vreg->max_core_count > - MSM8998_KBSS_CPR_SDELTA_CORE_COUNT)) { + CPRH_KBSS_CPR_SDELTA_CORE_COUNT)) { cpr3_err(vreg, "qcom,max-core-count has invalid value = %d\n", vreg->max_core_count); return -EINVAL; @@ -1310,10 +1698,10 @@ static int cprh_kbss_init_regulator(struct cpr3_regulator *vreg) */ static int cprh_kbss_init_aging(struct cpr3_controller *ctrl) { - struct cprh_msm8998_kbss_fuses *fuse = NULL; + struct cprh_kbss_fuses *fuse = NULL; struct cpr3_regulator *vreg; u32 aging_ro_scale; - int i, j, rc; + int i, j, rc = 0; for (i = 0; i < ctrl->thread_count; i++) { for (j = 0; j < ctrl->thread[i].vreg_count; j++) { @@ -1344,28 +1732,51 @@ static int cprh_kbss_init_aging(struct cpr3_controller *ctrl) ctrl->aging_complete_vdd_mode = REGULATOR_MODE_IDLE; ctrl->aging_sensor_count = 1; - ctrl->aging_sensor = kzalloc(sizeof(*ctrl->aging_sensor), GFP_KERNEL); + ctrl->aging_sensor = devm_kzalloc(ctrl->dev, + sizeof(*ctrl->aging_sensor), + GFP_KERNEL); if (!ctrl->aging_sensor) return -ENOMEM; - if (ctrl->ctrl_id == MSM8998_KBSS_POWER_CLUSTER_ID) { - ctrl->aging_sensor->sensor_id - = MSM8998_KBSS_POWER_AGING_SENSOR_ID; - ctrl->aging_sensor->bypass_mask[0] - = MSM8998_KBSS_POWER_AGING_BYPASS_MASK0; - } else { - ctrl->aging_sensor->sensor_id - = MSM8998_KBSS_PERFORMANCE_AGING_SENSOR_ID; - ctrl->aging_sensor->bypass_mask[0] - = MSM8998_KBSS_PERFORMANCE_AGING_BYPASS_MASK0; + switch (ctrl->soc_revision) { + case SDM660_SOC_ID: + if (ctrl->ctrl_id == CPRH_KBSS_POWER_CLUSTER_ID) { + ctrl->aging_sensor->sensor_id + = SDM660_KBSS_POWER_AGING_SENSOR_ID; + ctrl->aging_sensor->bypass_mask[0] + = SDM660_KBSS_POWER_AGING_BYPASS_MASK0; + } else { + ctrl->aging_sensor->sensor_id + = SDM660_KBSS_PERFORMANCE_AGING_SENSOR_ID; + ctrl->aging_sensor->bypass_mask[0] + = SDM660_KBSS_PERFORMANCE_AGING_BYPASS_MASK0; + } + break; + case MSM8998_V1_SOC_ID: + case MSM8998_V2_SOC_ID: + if (ctrl->ctrl_id == CPRH_KBSS_POWER_CLUSTER_ID) { + ctrl->aging_sensor->sensor_id + = MSM8998_KBSS_POWER_AGING_SENSOR_ID; + ctrl->aging_sensor->bypass_mask[0] + = MSM8998_KBSS_POWER_AGING_BYPASS_MASK0; + } else { + ctrl->aging_sensor->sensor_id + = MSM8998_KBSS_PERFORMANCE_AGING_SENSOR_ID; + ctrl->aging_sensor->bypass_mask[0] + = MSM8998_KBSS_PERFORMANCE_AGING_BYPASS_MASK0; + } + break; + default: + cpr3_err(ctrl, "unsupported soc id = %d\n", ctrl->soc_revision); + return -EINVAL; } ctrl->aging_sensor->ro_scale = aging_ro_scale; ctrl->aging_sensor->init_quot_diff = cpr3_convert_open_loop_voltage_fuse(0, - MSM8998_KBSS_AGING_INIT_QUOT_DIFF_SCALE, + CPRH_KBSS_AGING_INIT_QUOT_DIFF_SCALE, fuse->aging_init_quot_diff, - MSM8998_KBSS_AGING_INIT_QUOT_DIFF_SIZE); + CPRH_KBSS_AGING_INIT_QUOT_DIFF_SIZE); cpr3_debug(ctrl, "sensor %u aging init quotient diff = %d, aging RO scale = %u QUOT/V\n", ctrl->aging_sensor->sensor_id, @@ -1403,8 +1814,8 @@ static int cprh_kbss_init_controller(struct cpr3_controller *ctrl) return rc; } - if (ctrl->ctrl_id < MSM8998_KBSS_MIN_CONTROLLER_ID || - ctrl->ctrl_id > MSM8998_KBSS_MAX_CONTROLLER_ID) { + if (ctrl->ctrl_id < CPRH_KBSS_MIN_CONTROLLER_ID || + ctrl->ctrl_id > CPRH_KBSS_MAX_CONTROLLER_ID) { cpr3_err(ctrl, "invalid qcom,cpr-controller-id specified\n"); return -EINVAL; } @@ -1503,9 +1914,28 @@ static int cprh_kbss_init_controller(struct cpr3_controller *ctrl) "qcom,cpr-corner-switch-delay-time", &ctrl->corner_switch_delay_time); - ctrl->sensor_count = ctrl->ctrl_id == MSM8998_KBSS_POWER_CLUSTER_ID ? - MSM8998_KBSS_POWER_CPR_SENSOR_COUNT : - MSM8998_KBSS_PERFORMANCE_CPR_SENSOR_COUNT; + switch (ctrl->soc_revision) { + case SDM660_SOC_ID: + if (ctrl->ctrl_id == CPRH_KBSS_POWER_CLUSTER_ID) + ctrl->sensor_count = + SDM660_KBSS_POWER_CPR_SENSOR_COUNT; + else + ctrl->sensor_count = + SDM660_KBSS_PERFORMANCE_CPR_SENSOR_COUNT; + break; + case MSM8998_V1_SOC_ID: + case MSM8998_V2_SOC_ID: + if (ctrl->ctrl_id == CPRH_KBSS_POWER_CLUSTER_ID) + ctrl->sensor_count = + MSM8998_KBSS_POWER_CPR_SENSOR_COUNT; + else + ctrl->sensor_count = + MSM8998_KBSS_PERFORMANCE_CPR_SENSOR_COUNT; + break; + default: + cpr3_err(ctrl, "unsupported soc id = %d\n", ctrl->soc_revision); + return -EINVAL; + } /* * KBSS only has one thread (0) per controller so the zeroed @@ -1516,7 +1946,7 @@ static int cprh_kbss_init_controller(struct cpr3_controller *ctrl) if (!ctrl->sensor_owner) return -ENOMEM; - ctrl->cpr_clock_rate = MSM8998_KBSS_CPR_CLOCK_RATE; + ctrl->cpr_clock_rate = CPRH_KBSS_CPR_CLOCK_RATE; ctrl->supports_hw_closed_loop = true; ctrl->use_hw_closed_loop = of_property_read_bool(ctrl->dev->of_node, "qcom,cpr-hw-closed-loop"); @@ -1580,15 +2010,19 @@ static int cprh_kbss_regulator_resume(struct platform_device *pdev) static struct of_device_id cprh_regulator_match_table[] = { { .compatible = "qcom,cprh-msm8998-v1-kbss-regulator", - .data = (void *)(uintptr_t)1 + .data = (void *)(uintptr_t)MSM8998_V1_SOC_ID, }, { .compatible = "qcom,cprh-msm8998-v2-kbss-regulator", - .data = (void *)(uintptr_t)2 + .data = (void *)(uintptr_t)MSM8998_V2_SOC_ID, }, { .compatible = "qcom,cprh-msm8998-kbss-regulator", - .data = (void *)(uintptr_t)2 + .data = (void *)(uintptr_t)MSM8998_V2_SOC_ID, + }, + { + .compatible = "qcom,cprh-sdm660-kbss-regulator", + .data = (void *)(uintptr_t)SDM660_SOC_ID, }, {} }; diff --git a/drivers/regulator/msm_gfx_ldo.c b/drivers/regulator/msm_gfx_ldo.c index d2f743b8089a..265ca9ed5258 100644 --- a/drivers/regulator/msm_gfx_ldo.c +++ b/drivers/regulator/msm_gfx_ldo.c @@ -152,7 +152,7 @@ static struct ldo_config msm8953_ldo_config[] = { {LDO_MAX_OFFSET, LDO_MAX_OFFSET}, }; -static struct ldo_config msmfalcon_ldo_config[] = { +static struct ldo_config sdm660_ldo_config[] = { {LDO_ATEST_REG, 0x00000080}, {LDO_CFG0_REG, 0x0100A600}, {LDO_CFG1_REG, 0x000000A0}, @@ -185,7 +185,7 @@ static const int msm8953_fuse_ref_volt[MSM8953_LDO_FUSE_CORNERS] = { enum { MSM8953_SOC_ID, - MSMFALCON_SOC_ID, + SDM660_SOC_ID, }; static int convert_open_loop_voltage_fuse(int ref_volt, int step_volt, @@ -1516,8 +1516,8 @@ static const struct of_device_id msm_gfx_ldo_match_table[] = { .data = (void *)(uintptr_t)MSM8953_SOC_ID, }, { - .compatible = "qcom,msmfalcon-gfx-ldo", - .data = (void *)(uintptr_t)MSMFALCON_SOC_ID, + .compatible = "qcom,sdm660-gfx-ldo", + .data = (void *)(uintptr_t)SDM660_SOC_ID, }, {} }; @@ -1572,8 +1572,8 @@ static int msm_gfx_ldo_probe(struct platform_device *pdev) return rc; } break; - case MSMFALCON_SOC_ID: - ldo_vreg->ldo_init_config = msmfalcon_ldo_config; + case SDM660_SOC_ID: + ldo_vreg->ldo_init_config = sdm660_ldo_config; ldo_vreg->ops_type = VOLTAGE; init_data->constraints.valid_ops_mask |= REGULATOR_CHANGE_BYPASS; diff --git a/drivers/regulator/qpnp-labibb-regulator.c b/drivers/regulator/qpnp-labibb-regulator.c index 15ade85f446b..8dbe3080873c 100644 --- a/drivers/regulator/qpnp-labibb-regulator.c +++ b/drivers/regulator/qpnp-labibb-regulator.c @@ -46,6 +46,7 @@ /* LAB register offset definitions */ #define REG_LAB_STATUS1 0x08 +#define REG_LAB_SWIRE_PGM_CTL 0x40 #define REG_LAB_VOLTAGE 0x41 #define REG_LAB_RING_SUPPRESSION_CTL 0x42 #define REG_LAB_LCD_AMOLED_SEL 0x44 @@ -63,16 +64,25 @@ #define REG_LAB_SPARE_CTL 0x60 #define REG_LAB_PFM_CTL 0x62 +/* LAB registers for PM660A */ +#define REG_LAB_VOUT_DEFAULT 0x44 +#define REG_LAB_SW_HIGH_PSRR_CTL 0x70 +#define REG_LAB_LDO_PD_CTL 0x78 +#define REG_LAB_VPH_ENVELOP_CTL 0x7E + /* LAB register bits definitions */ /* REG_LAB_STATUS1 */ #define LAB_STATUS1_VREG_OK_MASK BIT(7) #define LAB_STATUS1_VREG_OK BIT(7) +/* REG_LAB_SWIRE_PGM_CTL */ +#define LAB_EN_SWIRE_PGM_VOUT BIT(7) +#define LAB_EN_SWIRE_PGM_PD BIT(6) + /* REG_LAB_VOLTAGE */ #define LAB_VOLTAGE_OVERRIDE_EN BIT(7) -#define LAB_VOLTAGE_SET_BITS 4 -#define LAB_VOLTAGE_SET_MASK ((1 << LAB_VOLTAGE_SET_BITS) - 1) +#define LAB_VOLTAGE_SET_MASK GENMASK(3, 0) /* REG_LAB_RING_SUPPRESSION_CTL */ #define LAB_RING_SUPPRESSION_CTL_EN BIT(7) @@ -98,34 +108,27 @@ #define LAB_OVERRIDE_CURRENT_MAX_BIT BIT(3) /* REG_LAB_CURRENT_SENSE */ -#define LAB_CURRENT_SENSE_GAIN_BITS 2 -#define LAB_CURRENT_SENSE_GAIN_MASK ((1 << LAB_CURRENT_SENSE_GAIN_BITS) \ - - 1) +#define LAB_CURRENT_SENSE_GAIN_MASK GENMASK(1, 0) /* REG_LAB_PS_CTL */ -#define LAB_PS_CTL_BITS 2 -#define LAB_PS_CTL_MASK ((1 << LAB_PS_CTL_BITS) - 1) +#define LAB_PS_THRESH_MASK GENMASK(1, 0) #define LAB_PS_CTL_EN BIT(7) /* REG_LAB_RDSON_MNGMNT */ #define LAB_RDSON_MNGMNT_NFET_SLEW_EN BIT(5) #define LAB_RDSON_MNGMNT_PFET_SLEW_EN BIT(4) -#define LAB_RDSON_MNGMNT_NFET_BITS 2 -#define LAB_RDSON_MNGMNT_NFET_MASK ((1 << LAB_RDSON_MNGMNT_NFET_BITS) - 1) +#define LAB_RDSON_MNGMNT_NFET_MASK GENMASK(3, 2) #define LAB_RDSON_MNGMNT_NFET_SHIFT 2 -#define LAB_RDSON_MNGMNT_PFET_BITS 2 -#define LAB_RDSON_MNGMNT_PFET_MASK ((1 << LAB_RDSON_MNGMNT_PFET_BITS) - 1) +#define LAB_RDSON_MNGMNT_PFET_MASK GENMASK(1, 0) #define LAB_RDSON_NFET_SW_SIZE_QUARTER 0x0 #define LAB_RDSON_PFET_SW_SIZE_QUARTER 0x0 /* REG_LAB_PRECHARGE_CTL */ -#define LAB_PRECHARGE_CTL_EN BIT(2) -#define LAB_PRECHARGE_CTL_EN_BITS 2 -#define LAB_PRECHARGE_CTL_EN_MASK ((1 << LAB_PRECHARGE_CTL_EN_BITS) - 1) +#define LAB_FAST_PRECHARGE_CTL_EN BIT(2) +#define LAB_MAX_PRECHARGE_TIME_MASK GENMASK(1, 0) /* REG_LAB_SOFT_START_CTL */ -#define LAB_SOFT_START_CTL_BITS 2 -#define LAB_SOFT_START_CTL_MASK ((1 << LAB_SOFT_START_CTL_BITS) - 1) +#define LAB_SOFT_START_CTL_MASK GENMASK(1, 0) /* REG_LAB_SPARE_CTL */ #define LAB_SPARE_TOUCH_WAKE_BIT BIT(3) @@ -134,10 +137,19 @@ /* REG_LAB_PFM_CTL */ #define LAB_PFM_EN_BIT BIT(7) +/* REG_LAB_SW_HIGH_PSRR_CTL */ +#define LAB_EN_SW_HIGH_PSRR_MODE BIT(7) +#define LAB_SW_HIGH_PSRR_REQ BIT(0) + +/* REG_LAB_VPH_ENVELOP_CTL */ +#define LAB_VREF_HIGH_PSRR_SEL_MASK GENMASK(7, 6) +#define LAB_SEL_HW_HIGH_PSRR_SRC_MASK GENMASK(1, 0) +#define LAB_SEL_HW_HIGH_PSRR_SRC_SHIFT 6 + /* IBB register offset definitions */ #define REG_IBB_REVISION4 0x03 #define REG_IBB_STATUS1 0x08 -#define REG_IBB_VOLTAGE 0x41 +#define REG_IBB_VOLTAGE 0x41 #define REG_IBB_RING_SUPPRESSION_CTL 0x42 #define REG_IBB_LCD_AMOLED_SEL 0x44 #define REG_IBB_MODULE_RDY 0x45 @@ -153,9 +165,19 @@ #define REG_IBB_PWRUP_PWRDN_CTL_2 0x59 #define REG_IBB_SOFT_START_CTL 0x5F #define REG_IBB_SWIRE_CTL 0x5A +#define REG_IBB_OUTPUT_SLEW_CTL 0x5D #define REG_IBB_SPARE_CTL 0x60 #define REG_IBB_NLIMIT_DAC 0x61 +/* IBB registers for PM660A */ +#define REG_IBB_DEFAULT_VOLTAGE 0x40 +#define REG_IBB_FLOAT_CTL 0x43 +#define REG_IBB_VREG_OK_CTL 0x55 +#define REG_IBB_VOUT_MIN_MAGNITUDE 0x5C +#define REG_IBB_PFM_CTL 0x62 +#define REG_IBB_SMART_PS_CTL 0x65 +#define REG_IBB_ADAPT_DEAD_TIME 0x67 + /* IBB register bits definition */ /* REG_IBB_STATUS1 */ @@ -164,12 +186,22 @@ /* REG_IBB_VOLTAGE */ #define IBB_VOLTAGE_OVERRIDE_EN BIT(7) -#define IBB_VOLTAGE_SET_BITS 6 -#define IBB_VOLTAGE_SET_MASK ((1 << IBB_VOLTAGE_SET_BITS) - 1) +#define IBB_VOLTAGE_SET_MASK GENMASK(5, 0) + +/* REG_IBB_CLK_DIV */ +#define IBB_CLK_DIV_OVERRIDE_EN BIT(7) +#define IBB_CLK_DIV_MASK GENMASK(3, 0) /* REG_IBB_RING_SUPPRESSION_CTL */ #define IBB_RING_SUPPRESSION_CTL_EN BIT(7) +/* REG_IBB_FLOAT_CTL */ +#define IBB_FLOAT_EN BIT(0) +#define IBB_SMART_FLOAT_EN BIT(7) + +/* REG_IBB_MIN_MAGNITUDE */ +#define IBB_MIN_VOLTAGE_0P8_V BIT(3) + /* REG_IBB_MODULE_RDY */ #define IBB_MODULE_RDY_EN BIT(7) @@ -182,35 +214,47 @@ #define IBB_PD_CTL_HALF_STRENGTH BIT(0) #define IBB_PD_CTL_STRENGTH_MASK BIT(0) #define IBB_PD_CTL_EN BIT(7) +#define IBB_SWIRE_PD_UPD BIT(1) #define IBB_PD_CTL_EN_MASK BIT(7) /* REG_IBB_CURRENT_LIMIT */ -#define IBB_CURRENT_LIMIT_BITS 5 -#define IBB_CURRENT_LIMIT_MASK ((1 << IBB_CURRENT_LIMIT_BITS) - 1) +#define IBB_CURRENT_LIMIT_MASK GENMASK(4, 0) #define IBB_CURRENT_LIMIT_DEBOUNCE_SHIFT 5 +#define IBB_CURRENT_LIMIT_DEBOUNCE_MASK GENMASK(6, 5) #define IBB_CURRENT_LIMIT_EN BIT(7) #define IBB_ILIMIT_COUNT_CYC8 0 #define IBB_CURRENT_MAX_500MA 0xA /* REG_IBB_PS_CTL */ #define IBB_PS_CTL_EN 0x85 -#define IBB_PS_CTL_DISABLE 0x5 + +/* REG_IBB_SMART_PS_CTL */ +#define IBB_SMART_PS_CTL_EN BIT(7) +#define IBB_NUM_SWIRE_PULSE_WAIT 0x5 + +/* REG_IBB_OUTPUT_SLEW_CTL */ +#define IBB_SLEW_CTL_EN BIT(7) +#define IBB_SLEW_RATE_SPEED_FAST_EN BIT(6) +#define IBB_SLEW_RATE_TRANS_TIME_FAST_SHIFT 3 +#define IBB_SLEW_RATE_TRANS_TIME_FAST_MASK GENMASK(5, 3) +#define IBB_SLEW_RATE_TRANS_TIME_SLOW_MASK GENMASK(2, 0) + +/* REG_IBB_VREG_OK_CTL */ +#define IBB_VREG_OK_EN_OVERLOAD_BLANK BIT(7) +#define IBB_VREG_OK_OVERLOAD_DEB_SHIFT 5 +#define IBB_VREG_OK_OVERLOAD_DEB_MASK GENMASK(6, 5) /* REG_IBB_RDSON_MNGMNT */ #define IBB_NFET_SLEW_EN BIT(7) #define IBB_PFET_SLEW_EN BIT(6) #define IBB_OVERRIDE_NFET_SW_SIZE BIT(5) #define IBB_OVERRIDE_PFET_SW_SIZE BIT(2) -#define IBB_NFET_SW_SIZE_BITS 2 -#define IBB_PFET_SW_SIZE_BITS 2 -#define IBB_NFET_SW_SIZE_MASK ((1 << NFET_SW_SIZE_BITS) - 1) -#define IBB_PFET_SW_SIZE_MASK ((1 << PFET_SW_SIZE_BITS) - 1) -#define IBB_NFET_SW_SIZE_SHIFT 3 +#define IBB_NFET_SW_SIZE_MASK GENMASK(3, 2) +#define IBB_PFET_SW_SIZE_MASK GENMASK(1, 0) /* REG_IBB_NONOVERLAP_TIME_1 */ -#define IBB_OVERRIDE_NONOVERLAP BIT(6) -#define IBB_NONOVERLAP_NFET_BITS 3 -#define IBB_NONOVERLAP_NFET_MASK ((1 << IBB_NONOVERLAP_NFET_BITS) - 1) +#define IBB_OVERRIDE_NONOVERLAP BIT(6) +#define IBB_NONOVERLAP_NFET_MASK GENMASK(2, 0) #define IBB_NFET_GATE_DELAY_2 0x3 /* REG_IBB_NONOVERLAP_TIME_2 */ @@ -226,37 +270,41 @@ #define IBB_FAST_STARTUP BIT(3) /* REG_IBB_SWIRE_CTL */ -#define IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_BITS 6 -#define IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK \ - ((1 << IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_BITS) - 1) +#define IBB_SWIRE_VOUT_UPD_EN BIT(6) +#define IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK GENMASK(5, 0) +#define MAX_OUTPUT_EDGE_VOLTAGE_MV 6300 #define MAX_OUTPUT_PULSE_VOLTAGE_MV 7700 #define MIN_OUTPUT_PULSE_VOLTAGE_MV 1400 #define OUTPUT_VOLTAGE_STEP_MV 100 /* REG_IBB_NLIMIT_DAC */ -#define IBB_NLIMIT_DAC_EN 0x0 -#define IBB_NLIMIT_DAC_DISABLE 0x5 +#define IBB_DEFAULT_NLIMIT_DAC 0x5 + +/* REG_IBB_PFM_CTL */ +#define IBB_PFM_ENABLE BIT(7) +#define IBB_PFM_PEAK_CURRENT_BIT_SHIFT 1 +#define IBB_PFM_PEAK_CURRENT_MASK GENMASK(3, 1) +#define IBB_PFM_HYSTERESIS_BIT_SHIFT 4 +#define IBB_PFM_HYSTERESIS_MASK GENMASK(5, 4) /* REG_IBB_PWRUP_PWRDN_CTL_1 */ #define IBB_PWRUP_PWRDN_CTL_1_DLY1_BITS 2 -#define IBB_PWRUP_PWRDN_CTL_1_DLY1_MASK \ - ((1 << IBB_PWRUP_PWRDN_CTL_1_DLY1_BITS) - 1) +#define IBB_PWRUP_PWRDN_CTL_1_DLY1_MASK GENMASK(5, 4) #define IBB_PWRUP_PWRDN_CTL_1_DLY1_SHIFT 4 -#define IBB_PWRUP_PWRDN_CTL_1_DLY2_BITS 2 -#define IBB_PWRUP_PWRDN_CTL_1_DLY2_MASK \ - ((1 << IBB_PWRUP_PWRDN_CTL_1_DLY2_BITS) - 1) +#define IBB_PWRUP_PWRDN_CTL_1_EN_DLY2 BIT(3) +#define IBB_PWRUP_PWRDN_CTL_1_DLY2_MASK GENMASK(1, 0) #define IBB_PWRUP_PWRDN_CTL_1_LAB_VREG_OK BIT(7) #define IBB_PWRUP_PWRDN_CTL_1_EN_DLY1 BIT(6) #define PWRUP_PWRDN_CTL_1_DISCHARGE_EN BIT(2) /* REG_IBB_PWRUP_PWRDN_CTL_2 */ -#define IBB_DIS_DLY_BITS 2 -#define IBB_DIS_DLY_MASK ((1 << IBB_DIS_DLY_BITS) - 1) +#define IBB_DIS_DLY_MASK GENMASK(1, 0) #define IBB_WAIT_MBG_OK BIT(2) /* Constants */ #define SWIRE_DEFAULT_2ND_CMD_DLY_MS 20 #define SWIRE_DEFAULT_IBB_PS_ENABLE_DLY_MS 200 +#define IBB_HW_DEFAULT_SLEW_RATE 12000 /** * enum qpnp_labibb_mode - working mode of LAB/IBB regulators @@ -285,28 +333,28 @@ enum ibb_mode { IBB_HW_SW_CONTROL, }; -static const int ibb_discharge_resistor_plan[] = { +static const int ibb_discharge_resistor_table[] = { 300, 64, 32, 16, }; -static const int ibb_pwrup_dly_plan[] = { +static const int ibb_pwrup_dly_table[] = { 1000, 2000, 4000, 8000, }; -static const int ibb_pwrdn_dly_plan[] = { +static const int ibb_pwrdn_dly_table[] = { 1000, 2000, 4000, 8000, }; -static const int lab_clk_div_plan[] = { +static const int lab_clk_div_table[] = { 3200, 2740, 2400, @@ -325,7 +373,7 @@ static const int lab_clk_div_plan[] = { 910, }; -static const int ibb_clk_div_plan[] = { +static const int ibb_clk_div_table[] = { 3200, 2740, 2400, @@ -344,7 +392,7 @@ static const int ibb_clk_div_plan[] = { 910, }; -static const int lab_current_limit_plan[] = { +static const int lab_current_limit_table[] = { 200, 400, 600, @@ -355,14 +403,14 @@ static const int lab_current_limit_plan[] = { 1600, }; -static const char * const lab_current_sense_plan[] = { +static const char * const lab_current_sense_table[] = { "0.5x", "1x", "1.5x", "2x" }; -static const int ibb_current_limit_plan[] = { +static const int ibb_current_limit_table[] = { 0, 50, 100, @@ -397,48 +445,105 @@ static const int ibb_current_limit_plan[] = { 1550, }; -static const int ibb_debounce_plan[] = { +static const int ibb_output_slew_ctl_table[] = { + 100, + 200, + 500, + 1000, + 2000, + 10000, + 12000, + 15000 +}; + +static const int ibb_debounce_table[] = { 8, 16, 32, 64, }; -static const int lab_ps_threshold_plan[] = { +static const int ibb_overload_debounce_table[] = { + 1, + 2, + 4, + 8 +}; + +static const int ibb_vreg_ok_deb_table[] = { + 4, + 8, + 16, + 32 +}; + +static const int lab_ps_thresh_table_v1[] = { 20, 30, 40, 50, }; -static const int lab_soft_start_plan[] = { +static const int lab_ps_thresh_table_v2[] = { + 50, + 60, + 70, + 80, +}; + +static const int lab_soft_start_table[] = { 200, 400, 600, 800, }; -static const int lab_rdson_nfet_plan[] = { +static const int lab_rdson_nfet_table[] = { 25, 50, 75, 100, }; -static const int lab_rdson_pfet_plan[] = { +static const int lab_rdson_pfet_table[] = { 25, 50, 75, 100, }; -static const int lab_max_precharge_plan[] = { +static const int lab_max_precharge_table[] = { 200, 300, 400, 500, }; +static const int ibb_pfm_peak_curr_table[] = { + 150, + 200, + 250, + 300, + 350, + 400, + 450, + 500 +}; + +static const int ibb_pfm_hysteresis_table[] = { + 0, + 25, + 50, + 0 +}; + +static const int lab_vref_high_psrr_table[] = { + 350, + 400, + 450, + 500 +}; + struct lab_regulator { struct regulator_desc rdesc; struct regulator_dev *rdev; @@ -471,6 +576,7 @@ struct ibb_regulator { u32 pwrdn_dly; int vreg_enabled; + int num_swire_trans; }; struct qpnp_labibb { @@ -484,12 +590,16 @@ struct qpnp_labibb { u8 ibb_dig_major; struct lab_regulator lab_vreg; struct ibb_regulator ibb_vreg; + const struct ibb_ver_ops *ibb_ver_ops; + const struct lab_ver_ops *lab_ver_ops; + struct mutex bus_mutex; enum qpnp_labibb_mode mode; bool standalone; bool ttw_en; bool in_ttw_mode; bool ibb_settings_saved; bool swire_control; + bool pbs_control; bool ttw_force_lab_on; bool skip_2nd_swire_cmd; bool pfm_enable; @@ -497,6 +607,28 @@ struct qpnp_labibb { u32 swire_ibb_ps_enable_delay; }; +struct ibb_ver_ops { + int (*set_default_voltage)(struct qpnp_labibb *labibb, + bool use_default); + int (*set_voltage)(struct qpnp_labibb *labibb, int min_uV, int max_uV); + int (*sel_mode)(struct qpnp_labibb *labibb, bool is_ibb); + int (*get_mode)(struct qpnp_labibb *labibb); + int (*set_clk_div)(struct qpnp_labibb *labibb, u8 val); + int (*smart_ps_config)(struct qpnp_labibb *labibb, bool enable, + int num_swire_trans, int neg_curr_limit); + int (*soft_start_ctl)(struct qpnp_labibb *labibb, + struct device_node *of_node); + int (*voltage_at_one_pulse)(struct qpnp_labibb *labibb, u32 volt); +}; + +struct lab_ver_ops { + const char *ver_str; + int (*set_default_voltage)(struct qpnp_labibb *labibb, + bool default_pres); + int (*ps_ctl)(struct qpnp_labibb *labibb, + u32 thresh, bool enable); +}; + enum ibb_settings_index { IBB_PD_CTL = 0, IBB_CURRENT_LIMIT, @@ -545,114 +677,722 @@ static struct settings lab_settings[LAB_SETTINGS_MAX] = { SETTING(LAB_RDSON_MNGMNT, false), }; -static int qpnp_labibb_read(struct qpnp_labibb *labibb, u8 *val, u16 address, - int count) +static int +qpnp_labibb_read(struct qpnp_labibb *labibb, u16 address, + u8 *val, int count) { int rc = 0; struct platform_device *pdev = labibb->pdev; - if (address == 0) { - pr_err("address cannot be zero address=0x%02x sid=0x%02x rc=%d\n", - address, to_spmi_device(pdev->dev.parent)->usid, rc); - return -EINVAL; - } - + mutex_lock(&(labibb->bus_mutex)); rc = regmap_bulk_read(labibb->regmap, address, val, count); - if (rc) { + if (rc < 0) pr_err("SPMI read failed address=0x%02x sid=0x%02x rc=%d\n", address, to_spmi_device(pdev->dev.parent)->usid, rc); - return rc; - } - return 0; + mutex_unlock(&(labibb->bus_mutex)); + return rc; } -static int qpnp_labibb_write(struct qpnp_labibb *labibb, u16 address, u8 *val, - int count) +static int +qpnp_labibb_write(struct qpnp_labibb *labibb, u16 address, + u8 *val, int count) { int rc = 0; struct platform_device *pdev = labibb->pdev; + mutex_lock(&(labibb->bus_mutex)); if (address == 0) { pr_err("address cannot be zero address=0x%02x sid=0x%02x rc=%d\n", address, to_spmi_device(pdev->dev.parent)->usid, rc); - return -EINVAL; + rc = -EINVAL; + goto error; } rc = regmap_bulk_write(labibb->regmap, address, val, count); - if (rc) { + if (rc < 0) pr_err("write failed address=0x%02x sid=0x%02x rc=%d\n", address, to_spmi_device(pdev->dev.parent)->usid, rc); - return rc; - } - return 0; +error: + mutex_unlock(&(labibb->bus_mutex)); + return rc; } -static int qpnp_labibb_masked_write(struct qpnp_labibb *labibb, u16 address, - u8 mask, u8 val) +static int +qpnp_labibb_masked_write(struct qpnp_labibb *labibb, u16 address, + u8 mask, u8 val) { - int rc; + int rc = 0; + struct platform_device *pdev = labibb->pdev; + + mutex_lock(&(labibb->bus_mutex)); + if (address == 0) { + pr_err("address cannot be zero address=0x%02x sid=0x%02x\n", + address, to_spmi_device(pdev->dev.parent)->usid); + rc = -EINVAL; + goto error; + } rc = regmap_update_bits(labibb->regmap, address, mask, val); - if (rc) { + if (rc < 0) pr_err("spmi write failed: addr=%03X, rc=%d\n", address, rc); - return rc; - } - return 0; +error: + mutex_unlock(&(labibb->bus_mutex)); + return rc; } static int qpnp_labibb_sec_write(struct qpnp_labibb *labibb, u16 base, - u8 offset, u8 *val, int count) + u8 offset, u8 val) { - int rc; + int rc = 0; u8 sec_val = REG_LAB_IBB_SEC_UNLOCK_CODE; + struct platform_device *pdev = labibb->pdev; - rc = qpnp_labibb_write(labibb, base + REG_LAB_IBB_SEC_ACCESS, &sec_val, - 1); - if (rc) { - pr_err("qpnp_lab_write register %x failed rc = %d\n", + mutex_lock(&(labibb->bus_mutex)); + if (base == 0) { + pr_err("base cannot be zero base=0x%02x sid=0x%02x\n", + base, to_spmi_device(pdev->dev.parent)->usid); + rc = -EINVAL; + goto error; + } + + rc = regmap_write(labibb->regmap, base + REG_LAB_IBB_SEC_ACCESS, + sec_val); + if (rc < 0) { + pr_err("register %x failed rc = %d\n", base + REG_LAB_IBB_SEC_ACCESS, rc); - return rc; + goto error; } - rc = qpnp_labibb_write(labibb, base + offset, val, count); - if (rc) - pr_err("qpnp_labibb_write failed: addr=%03X, rc=%d\n", + rc = regmap_write(labibb->regmap, base + offset, val); + if (rc < 0) + pr_err("failed: addr=%03X, rc=%d\n", base + offset, rc); +error: + mutex_unlock(&(labibb->bus_mutex)); return rc; } static int qpnp_labibb_sec_masked_write(struct qpnp_labibb *labibb, u16 base, u8 offset, u8 mask, u8 val) { - int rc; + int rc = 0; u8 sec_val = REG_LAB_IBB_SEC_UNLOCK_CODE; + struct platform_device *pdev = labibb->pdev; - rc = qpnp_labibb_write(labibb, base + REG_LAB_IBB_SEC_ACCESS, &sec_val, - 1); - if (rc) { - pr_err("qpnp_lab_write register %x failed rc = %d\n", + mutex_lock(&(labibb->bus_mutex)); + if (base == 0) { + pr_err("base cannot be zero base=0x%02x sid=0x%02x\n", + base, to_spmi_device(pdev->dev.parent)->usid); + rc = -EINVAL; + goto error; + } + + rc = regmap_write(labibb->regmap, base + REG_LAB_IBB_SEC_ACCESS, + sec_val); + if (rc < 0) { + pr_err("register %x failed rc = %d\n", base + REG_LAB_IBB_SEC_ACCESS, rc); + goto error; + } + + rc = regmap_update_bits(labibb->regmap, base + offset, mask, val); + if (rc < 0) + pr_err("spmi write failed: addr=%03X, rc=%d\n", base, rc); + +error: + mutex_unlock(&(labibb->bus_mutex)); + return rc; +} + +static int qpnp_ibb_smart_ps_config_v1(struct qpnp_labibb *labibb, bool enable, + int num_swire_trans, int neg_curr_limit) +{ + return 0; +} + +static int qpnp_ibb_smart_ps_config_v2(struct qpnp_labibb *labibb, bool enable, + int num_swire_trans, int neg_curr_limit) +{ + u8 val; + int rc = 0; + + if (enable) { + val = IBB_NUM_SWIRE_PULSE_WAIT; + rc = qpnp_labibb_write(labibb, + labibb->ibb_base + REG_IBB_PS_CTL, &val, 1); + if (rc < 0) { + pr_err("write register %x failed rc = %d\n", + REG_IBB_PS_CTL, rc); + return rc; + } + } + + val = enable ? IBB_SMART_PS_CTL_EN : IBB_NUM_SWIRE_PULSE_WAIT; + if (num_swire_trans) + val |= num_swire_trans; + else + val |= IBB_NUM_SWIRE_PULSE_WAIT; + + rc = qpnp_labibb_write(labibb, + labibb->ibb_base + REG_IBB_SMART_PS_CTL, &val, 1); + if (rc < 0) { + pr_err("write register %x failed rc = %d\n", + REG_IBB_SMART_PS_CTL, rc); return rc; } - rc = qpnp_labibb_masked_write(labibb, base + offset, mask, val); - if (rc) - pr_err("qpnp_lab_write register %x failed rc = %d\n", - base + offset, rc); + val = enable ? (neg_curr_limit ? neg_curr_limit : + IBB_DEFAULT_NLIMIT_DAC) : IBB_DEFAULT_NLIMIT_DAC; + + rc = qpnp_labibb_write(labibb, + labibb->ibb_base + REG_IBB_NLIMIT_DAC, &val, 1); + if (rc < 0) + pr_err("write register %x failed rc = %d\n", + REG_IBB_NLIMIT_DAC, rc); return rc; } +static int qpnp_labibb_sel_mode_v1(struct qpnp_labibb *labibb, bool is_ibb) +{ + int rc = 0; + u8 val; + u16 base; + + val = (labibb->mode == QPNP_LABIBB_LCD_MODE) ? REG_LAB_IBB_LCD_MODE : + REG_LAB_IBB_AMOLED_MODE; + + base = is_ibb ? labibb->ibb_base : labibb->lab_base; + + rc = qpnp_labibb_sec_write(labibb, base, REG_LAB_LCD_AMOLED_SEL, + val); + if (rc < 0) + pr_err("register %x failed rc = %d\n", + REG_LAB_LCD_AMOLED_SEL, rc); + + return rc; +} + +static int qpnp_labibb_sel_mode_v2(struct qpnp_labibb *labibb, bool is_ibb) +{ + return 0; +} + +static int qpnp_ibb_get_mode_v1(struct qpnp_labibb *labibb) +{ + int rc = 0; + u8 val; + + rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_LCD_AMOLED_SEL, + &val, 1); + if (rc < 0) + return rc; + + if (val == REG_LAB_IBB_AMOLED_MODE) + labibb->mode = QPNP_LABIBB_AMOLED_MODE; + else + labibb->mode = QPNP_LABIBB_LCD_MODE; + + return 0; +} + +static int qpnp_ibb_get_mode_v2(struct qpnp_labibb *labibb) +{ + labibb->mode = QPNP_LABIBB_AMOLED_MODE; + + return 0; +} + +static int qpnp_ibb_set_clk_div_v1(struct qpnp_labibb *labibb, u8 val) +{ + int rc = 0; + + rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_CLK_DIV, + &val, 1); + + return rc; +} + +static int qpnp_ibb_set_clk_div_v2(struct qpnp_labibb *labibb, u8 val) +{ + int rc = 0; + + val |= IBB_CLK_DIV_OVERRIDE_EN; + rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + + REG_IBB_CLK_DIV, IBB_CLK_DIV_MASK | + IBB_CLK_DIV_OVERRIDE_EN, val); + + return rc; +} + +static int qpnp_ibb_soft_start_ctl_v1(struct qpnp_labibb *labibb, + struct device_node *of_node) +{ + int rc = 0; + u8 val; + u32 tmp; + + rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-soft-start", + &(labibb->ibb_vreg.soft_start)); + if (rc < 0) { + pr_err("qcom,qpnp-ibb-soft-start is missing, rc = %d\n", + rc); + return rc; + } + + rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-discharge-resistor", + &tmp); + + if (rc < 0) { + pr_err("qcom,qpnp-ibb-discharge-resistor is missing, rc = %d\n", + rc); + return rc; + } + + if (labibb->mode == QPNP_LABIBB_AMOLED_MODE) { + /* + * AMOLED mode needs ibb discharge resistor to be + * configured for 300KOhm + */ + if (tmp < ibb_discharge_resistor_table[0]) + tmp = ibb_discharge_resistor_table[0]; + } + + for (val = 0; val < ARRAY_SIZE(ibb_discharge_resistor_table); val++) + if (ibb_discharge_resistor_table[val] == tmp) + break; + + if (val == ARRAY_SIZE(ibb_discharge_resistor_table)) { + pr_err("Invalid value in qcom,qpnp-ibb-discharge-resistor\n"); + return -EINVAL; + } + + rc = qpnp_labibb_write(labibb, labibb->ibb_base + + REG_IBB_SOFT_START_CTL, &val, 1); + if (rc < 0) + pr_err("write to register %x failed rc = %d\n", + REG_IBB_SOFT_START_CTL, rc); + + return rc; +} + +static int qpnp_ibb_soft_start_ctl_v2(struct qpnp_labibb *labibb, + struct device_node *of_node) +{ + return 0; +} + +static int qpnp_ibb_vreg_ok_ctl(struct qpnp_labibb *labibb, + struct device_node *of_node) +{ + u8 val = 0; + int rc = 0, i = 0; + u32 tmp; + + if (labibb->pmic_rev_id->pmic_subtype != PM660L_SUBTYPE) + return rc; + + val |= IBB_VREG_OK_EN_OVERLOAD_BLANK; + + rc = of_property_read_u32(of_node, + "qcom,qpnp-ibb-overload-debounce", &tmp); + if (rc < 0) { + pr_err("failed to read qcom,qpnp-ibb-overload-debounce rc=%d\n", + rc); + return rc; + } + + for (i = 0; i < ARRAY_SIZE(ibb_overload_debounce_table); i++) + if (ibb_overload_debounce_table[i] == tmp) + break; + + if (i == ARRAY_SIZE(ibb_overload_debounce_table)) { + pr_err("Invalid value in qcom,qpnp-ibb-overload-debounce\n"); + return -EINVAL; + } + val |= i << IBB_VREG_OK_OVERLOAD_DEB_SHIFT; + + rc = of_property_read_u32(of_node, + "qcom,qpnp-ibb-vreg-ok-debounce", &tmp); + if (rc < 0) { + pr_err("failed to read qcom,qpnp-ibb-vreg-ok-debounce rc=%d\n", + rc); + return rc; + } + + for (i = 0; i < ARRAY_SIZE(ibb_vreg_ok_deb_table); i++) + if (ibb_vreg_ok_deb_table[i] == tmp) + break; + + if (i == ARRAY_SIZE(ibb_vreg_ok_deb_table)) { + pr_err("Invalid value in qcom,qpnp-ibb-vreg-ok-debounce\n"); + return -EINVAL; + } + val |= i; + + rc = qpnp_labibb_write(labibb, labibb->ibb_base + + REG_IBB_VREG_OK_CTL, + &val, 1); + if (rc < 0) + pr_err("write to register %x failed rc = %d\n", + REG_IBB_VREG_OK_CTL, rc); + + return rc; +} + +static int qpnp_ibb_set_default_voltage_v1(struct qpnp_labibb *labibb, + bool use_default) +{ + u8 val; + int rc = 0; + + if (!use_default) { + if (labibb->ibb_vreg.curr_volt < labibb->ibb_vreg.min_volt) { + pr_err("qcom,qpnp-ibb-init-voltage %d is less than the the minimum voltage %d", + labibb->ibb_vreg.curr_volt, labibb->ibb_vreg.min_volt); + return -EINVAL; + } + + val = DIV_ROUND_UP(labibb->ibb_vreg.curr_volt - + labibb->ibb_vreg.min_volt, + labibb->ibb_vreg.step_size); + if (val > IBB_VOLTAGE_SET_MASK) { + pr_err("qcom,qpnp-lab-init-voltage %d is larger than the max supported voltage %ld", + labibb->ibb_vreg.curr_volt, + labibb->ibb_vreg.min_volt + + labibb->ibb_vreg.step_size * + IBB_VOLTAGE_SET_MASK); + return -EINVAL; + } + + labibb->ibb_vreg.curr_volt = val * labibb->ibb_vreg.step_size + + labibb->ibb_vreg.min_volt; + val |= IBB_VOLTAGE_OVERRIDE_EN; + } else { + val = 0; + } + + rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + + REG_IBB_VOLTAGE, IBB_VOLTAGE_SET_MASK | + IBB_VOLTAGE_OVERRIDE_EN, val); + if (rc < 0) + pr_err("write to register %x failed rc = %d\n", REG_IBB_VOLTAGE, + rc); + + return rc; +} + +static int qpnp_ibb_set_default_voltage_v2(struct qpnp_labibb *labibb, + bool use_default) +{ + int rc = 0; + u8 val; + + val = DIV_ROUND_UP(labibb->ibb_vreg.curr_volt, + labibb->ibb_vreg.step_size); + if (val > IBB_VOLTAGE_SET_MASK) { + pr_err("Invalid qcom,qpnp-ibb-init-voltage property %d", + labibb->ibb_vreg.curr_volt); + return -EINVAL; + } + + labibb->ibb_vreg.curr_volt = val * labibb->ibb_vreg.step_size; + + rc = qpnp_labibb_write(labibb, labibb->ibb_base + + REG_IBB_DEFAULT_VOLTAGE, &val, 1); + if (rc < 0) + pr_err("write to register %x failed rc = %d\n", + REG_IBB_DEFAULT_VOLTAGE, rc); + + return rc; +} + +static int qpnp_ibb_set_voltage_v1(struct qpnp_labibb *labibb, + int min_uV, int max_uV) +{ + int rc, new_uV; + u8 val; + + if (min_uV < labibb->ibb_vreg.min_volt) { + pr_err("min_uV %d is less than min_volt %d", min_uV, + labibb->ibb_vreg.min_volt); + return -EINVAL; + } + + val = DIV_ROUND_UP(min_uV - labibb->ibb_vreg.min_volt, + labibb->ibb_vreg.step_size); + new_uV = val * labibb->ibb_vreg.step_size + labibb->ibb_vreg.min_volt; + + if (new_uV > max_uV) { + pr_err("unable to set voltage %d (min:%d max:%d)\n", new_uV, + min_uV, max_uV); + return -EINVAL; + } + + rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + + REG_IBB_VOLTAGE, + IBB_VOLTAGE_SET_MASK | + IBB_VOLTAGE_OVERRIDE_EN, + val | IBB_VOLTAGE_OVERRIDE_EN); + + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", REG_IBB_VOLTAGE, + rc); + return rc; + } + + if (new_uV > labibb->ibb_vreg.curr_volt) { + val = DIV_ROUND_UP(new_uV - labibb->ibb_vreg.curr_volt, + labibb->ibb_vreg.step_size); + udelay(val * labibb->ibb_vreg.slew_rate); + } + labibb->ibb_vreg.curr_volt = new_uV; + + return 0; +} + +static int qpnp_ibb_set_voltage_v2(struct qpnp_labibb *labibb, + int min_uV, int max_uV) +{ + int rc, new_uV; + u8 val; + + val = DIV_ROUND_UP(min_uV, labibb->ibb_vreg.step_size); + new_uV = val * labibb->ibb_vreg.step_size; + + if (new_uV > max_uV) { + pr_err("unable to set voltage %d (min:%d max:%d)\n", new_uV, + min_uV, max_uV); + return -EINVAL; + } + + rc = qpnp_labibb_write(labibb, labibb->ibb_base + + REG_IBB_VOLTAGE, &val, 1); + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", REG_IBB_VOLTAGE, + rc); + return rc; + } + + if (new_uV > labibb->ibb_vreg.curr_volt) { + val = DIV_ROUND_UP(new_uV - labibb->ibb_vreg.curr_volt, + labibb->ibb_vreg.step_size); + udelay(val * labibb->ibb_vreg.slew_rate); + } + labibb->ibb_vreg.curr_volt = new_uV; + + return 0; +} + +static int qpnp_ibb_output_voltage_at_one_pulse_v1(struct qpnp_labibb *labibb, + u32 volt) +{ + int rc = 0; + u8 val; + + /* + * Set the output voltage 100mV lower as the IBB HW module + * counts one pulse less in SWIRE mode. + */ + val = DIV_ROUND_UP((volt - MIN_OUTPUT_PULSE_VOLTAGE_MV), + OUTPUT_VOLTAGE_STEP_MV) - 1; + rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + + REG_IBB_SWIRE_CTL, + IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK, + val); + if (rc < 0) + pr_err("write register %x failed rc = %d\n", + REG_IBB_SWIRE_CTL, rc); + + return rc; +} + +static int qpnp_ibb_output_voltage_at_one_pulse_v2(struct qpnp_labibb *labibb, + u32 volt) +{ + int rc = 0; + u8 val; + + val = DIV_ROUND_UP(volt, OUTPUT_VOLTAGE_STEP_MV); + + rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + + REG_IBB_SWIRE_CTL, + IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK, + val); + if (rc < 0) + pr_err("qpnp_labiibb_write register %x failed rc = %d\n", + REG_IBB_SWIRE_CTL, rc); + + return rc; +} + +static const struct ibb_ver_ops ibb_ops_v1 = { + .set_default_voltage = qpnp_ibb_set_default_voltage_v1, + .set_voltage = qpnp_ibb_set_voltage_v1, + .sel_mode = qpnp_labibb_sel_mode_v1, + .get_mode = qpnp_ibb_get_mode_v1, + .set_clk_div = qpnp_ibb_set_clk_div_v1, + .smart_ps_config = qpnp_ibb_smart_ps_config_v1, + .soft_start_ctl = qpnp_ibb_soft_start_ctl_v1, + .voltage_at_one_pulse = qpnp_ibb_output_voltage_at_one_pulse_v1, +}; + +static const struct ibb_ver_ops ibb_ops_v2 = { + .set_default_voltage = qpnp_ibb_set_default_voltage_v2, + .set_voltage = qpnp_ibb_set_voltage_v2, + .sel_mode = qpnp_labibb_sel_mode_v2, + .get_mode = qpnp_ibb_get_mode_v2, + .set_clk_div = qpnp_ibb_set_clk_div_v2, + .smart_ps_config = qpnp_ibb_smart_ps_config_v2, + .soft_start_ctl = qpnp_ibb_soft_start_ctl_v2, + .voltage_at_one_pulse = qpnp_ibb_output_voltage_at_one_pulse_v2, +}; + +static int qpnp_lab_set_default_voltage_v1(struct qpnp_labibb *labibb, + bool default_pres) +{ + u8 val; + int rc = 0; + + if (!default_pres) { + if (labibb->lab_vreg.curr_volt < labibb->lab_vreg.min_volt) { + pr_err("qcom,qpnp-lab-init-voltage %d is less than the the minimum voltage %d", + labibb->lab_vreg.curr_volt, + labibb->lab_vreg.min_volt); + return -EINVAL; + } + + val = DIV_ROUND_UP(labibb->lab_vreg.curr_volt - + labibb->lab_vreg.min_volt, + labibb->lab_vreg.step_size); + if (val > LAB_VOLTAGE_SET_MASK) { + pr_err("qcom,qpnp-lab-init-voltage %d is larger than the max supported voltage %ld", + labibb->lab_vreg.curr_volt, + labibb->lab_vreg.min_volt + + labibb->lab_vreg.step_size * + LAB_VOLTAGE_SET_MASK); + return -EINVAL; + } + + labibb->lab_vreg.curr_volt = val * labibb->lab_vreg.step_size + + labibb->lab_vreg.min_volt; + val |= LAB_VOLTAGE_OVERRIDE_EN; + + } else { + val = 0; + } + + rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + + REG_LAB_VOLTAGE, LAB_VOLTAGE_SET_MASK | + LAB_VOLTAGE_OVERRIDE_EN, val); + + if (rc < 0) + pr_err("write to register %x failed rc = %d\n", REG_LAB_VOLTAGE, + rc); + + return rc; +} + +static int qpnp_lab_set_default_voltage_v2(struct qpnp_labibb *labibb, + bool default_pres) +{ + int rc = 0; + u8 val; + + val = DIV_ROUND_UP((labibb->lab_vreg.curr_volt + - labibb->lab_vreg.min_volt), labibb->lab_vreg.step_size); + + rc = qpnp_labibb_write(labibb, labibb->lab_base + + REG_LAB_VOUT_DEFAULT, &val, 1); + if (rc < 0) + pr_err("write to register %x failed rc = %d\n", + REG_LAB_VOUT_DEFAULT, rc); + + return rc; +} + +static int qpnp_lab_ps_ctl_v1(struct qpnp_labibb *labibb, + u32 thresh, bool enable) +{ + int rc = 0; + u8 val; + + if (enable) { + for (val = 0; val < ARRAY_SIZE(lab_ps_thresh_table_v1); val++) + if (lab_ps_thresh_table_v1[val] == thresh) + break; + + if (val == ARRAY_SIZE(lab_ps_thresh_table_v1)) { + pr_err("Invalid value in qcom,qpnp-lab-ps-threshold\n"); + return -EINVAL; + } + + val |= LAB_PS_CTL_EN; + } else { + val = 0; + } + + rc = qpnp_labibb_write(labibb, labibb->lab_base + + REG_LAB_PS_CTL, &val, 1); + + if (rc < 0) + pr_err("write register %x failed rc = %d\n", + REG_LAB_PS_CTL, rc); + + return rc; +} + +static int qpnp_lab_ps_ctl_v2(struct qpnp_labibb *labibb, + u32 thresh, bool enable) +{ + int rc = 0; + u8 val; + + if (enable) { + for (val = 0; val < ARRAY_SIZE(lab_ps_thresh_table_v2); val++) + if (lab_ps_thresh_table_v2[val] == thresh) + break; + + if (val == ARRAY_SIZE(lab_ps_thresh_table_v2)) { + pr_err("Invalid value in qcom,qpnp-lab-ps-threshold\n"); + return -EINVAL; + } + + val |= LAB_PS_CTL_EN; + } else { + val = 0; + } + + rc = qpnp_labibb_write(labibb, labibb->lab_base + + REG_LAB_PS_CTL, &val, 1); + + if (rc < 0) + pr_err("write register %x failed rc = %d\n", + REG_LAB_PS_CTL, rc); + + return rc; +} + +static const struct lab_ver_ops lab_ops_v1 = { + .set_default_voltage = qpnp_lab_set_default_voltage_v1, + .ps_ctl = qpnp_lab_ps_ctl_v1, +}; + +static const struct lab_ver_ops lab_ops_v2 = { + .set_default_voltage = qpnp_lab_set_default_voltage_v2, + .ps_ctl = qpnp_lab_ps_ctl_v2, +}; + static int qpnp_labibb_get_matching_idx(const char *val) { int i; - for (i = 0; i < ARRAY_SIZE(lab_current_sense_plan); i++) - if (!strcmp(lab_current_sense_plan[i], val)) + for (i = 0; i < ARRAY_SIZE(lab_current_sense_table); i++) + if (!strcmp(lab_current_sense_table[i], val)) return i; return -EINVAL; @@ -677,7 +1417,7 @@ static int qpnp_ibb_set_mode(struct qpnp_labibb *labibb, enum ibb_mode mode) rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + REG_IBB_ENABLE_CTL, IBB_ENABLE_CTL_MASK, val); - if (rc) + if (rc < 0) pr_err("Unable to configure IBB_ENABLE_CTL rc=%d\n", rc); return rc; @@ -688,21 +1428,21 @@ static int qpnp_ibb_ps_config(struct qpnp_labibb *labibb, bool enable) u8 val; int rc; - val = enable ? IBB_PS_CTL_EN : IBB_PS_CTL_DISABLE; + val = enable ? IBB_PS_CTL_EN : IBB_NUM_SWIRE_PULSE_WAIT; rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_PS_CTL, - &val, 1); - if (rc) { - pr_err("qpnp_ibb_ps_config write register %x failed rc = %d\n", - REG_IBB_PS_CTL, rc); + &val, 1); + if (rc < 0) { + pr_err("write register %x failed rc = %d\n", + REG_IBB_PS_CTL, rc); return rc; } - val = enable ? IBB_NLIMIT_DAC_EN : IBB_NLIMIT_DAC_DISABLE; + val = enable ? 0 : IBB_DEFAULT_NLIMIT_DAC; rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_NLIMIT_DAC, - &val, 1); - if (rc) - pr_err("qpnp_ibb_ps_config write register %x failed rc = %d\n", - REG_IBB_NLIMIT_DAC, rc); + &val, 1); + if (rc < 0) + pr_err("write register %x failed rc = %d\n", + REG_IBB_NLIMIT_DAC, rc); return rc; } @@ -710,7 +1450,7 @@ static int qpnp_lab_dt_init(struct qpnp_labibb *labibb, struct device_node *of_node) { int rc = 0; - u8 i, val; + u8 i, val, mask; u32 tmp; /* @@ -718,234 +1458,242 @@ static int qpnp_lab_dt_init(struct qpnp_labibb *labibb, * GPIO selector. */ if (labibb->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE) { - if (labibb->mode == QPNP_LABIBB_LCD_MODE) - val = REG_LAB_IBB_LCD_MODE; - else - val = REG_LAB_IBB_AMOLED_MODE; - - rc = qpnp_labibb_sec_write(labibb, labibb->lab_base, - REG_LAB_LCD_AMOLED_SEL, &val, 1); - - if (rc) { - pr_err("qpnp_lab_sec_write register %x failed rc = %d\n", - REG_LAB_LCD_AMOLED_SEL, rc); + rc = labibb->ibb_ver_ops->sel_mode(labibb, 0); + if (rc < 0) return rc; - } } val = 0; - if (of_property_read_bool(of_node, "qcom,qpnp-lab-full-pull-down")) val |= LAB_PD_CTL_STRONG_PULL; if (!of_property_read_bool(of_node, "qcom,qpnp-lab-pull-down-enable")) val |= LAB_PD_CTL_DISABLE_PD; - rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_PD_CTL, - &val, 1); + mask = LAB_PD_CTL_EN_MASK | LAB_PD_CTL_STRENGTH_MASK; + rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + REG_LAB_PD_CTL, + mask, val); - if (rc) { - pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", REG_LAB_PD_CTL, rc); return rc; } rc = of_property_read_u32(of_node, - "qcom,qpnp-lab-switching-clock-frequency", &tmp); - if (rc) { - pr_err("get qcom,qpnp-lab-switching-clock-frequency failed rc = %d\n", - rc); - return rc; - } - - for (val = 0; val < ARRAY_SIZE(lab_clk_div_plan); val++) - if (lab_clk_div_plan[val] == tmp) - break; + "qcom,qpnp-lab-switching-clock-frequency", &tmp); + if (!rc) { + for (val = 0; val < ARRAY_SIZE(lab_clk_div_table); val++) + if (lab_clk_div_table[val] == tmp) + break; - if (val == ARRAY_SIZE(lab_clk_div_plan)) { - pr_err("Invalid property in qpnp-lab-switching-clock-frequency\n"); - return -EINVAL; - } + if (val == ARRAY_SIZE(lab_clk_div_table)) { + pr_err("Invalid value in qpnp-lab-switching-clock-frequency\n"); + return -EINVAL; + } - rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_CLK_DIV, - &val, 1); - if (rc) { - pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", - REG_LAB_CLK_DIV, rc); - return rc; + rc = qpnp_labibb_write(labibb, labibb->lab_base + + REG_LAB_CLK_DIV, &val, 1); + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", + REG_LAB_CLK_DIV, rc); + return rc; + } } - rc = of_property_read_u32(of_node, - "qcom,qpnp-lab-limit-maximum-current", &tmp); + if (of_property_read_bool(of_node, + "qcom,qpnp-lab-limit-max-current-enable")) { + val = LAB_CURRENT_LIMIT_EN_BIT; - if (rc) { - pr_err("get qcom,qpnp-lab-limit-maximum-current failed rc = %d\n", - rc); - return rc; - } + rc = of_property_read_u32(of_node, + "qcom,qpnp-lab-limit-maximum-current", &tmp); - for (val = 0; val < ARRAY_SIZE(lab_current_limit_plan); val++) - if (lab_current_limit_plan[val] == tmp) - break; + if (rc < 0) { + pr_err("get qcom,qpnp-lab-limit-maximum-current failed rc = %d\n", + rc); + return rc; + } - if (val == ARRAY_SIZE(lab_current_limit_plan)) { - pr_err("Invalid property in qcom,qpnp-lab-limit-maximum-current\n"); - return -EINVAL; - } + for (i = 0; i < ARRAY_SIZE(lab_current_limit_table); i++) + if (lab_current_limit_table[i] == tmp) + break; - if (of_property_read_bool(of_node, - "qcom,qpnp-lab-limit-max-current-enable")) - val |= LAB_CURRENT_LIMIT_EN_BIT; + if (i == ARRAY_SIZE(lab_current_limit_table)) { + pr_err("Invalid value in qcom,qpnp-lab-limit-maximum-current\n"); + return -EINVAL; + } - rc = qpnp_labibb_write(labibb, labibb->lab_base + - REG_LAB_CURRENT_LIMIT, &val, 1); - if (rc) { - pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", - REG_LAB_CURRENT_LIMIT, rc); - return rc; + val |= i; + rc = qpnp_labibb_write(labibb, labibb->lab_base + + REG_LAB_CURRENT_LIMIT, &val, 1); + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", + REG_LAB_CURRENT_LIMIT, rc); + return rc; + } } if (of_property_read_bool(of_node, "qcom,qpnp-lab-ring-suppression-enable")) { val = LAB_RING_SUPPRESSION_CTL_EN; rc = qpnp_labibb_write(labibb, labibb->lab_base + - REG_LAB_RING_SUPPRESSION_CTL, - &val, - 1); - if (rc) { - pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", + REG_LAB_RING_SUPPRESSION_CTL, &val, 1); + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", REG_LAB_RING_SUPPRESSION_CTL, rc); return rc; } } - rc = of_property_read_u32(of_node, "qcom,qpnp-lab-ps-threshold", &tmp); + if (of_property_read_bool(of_node, "qcom,qpnp-lab-ps-enable")) { - if (rc) { - pr_err("get qcom,qpnp-lab-ps-threshold failed rc = %d\n", - rc); - return rc; + rc = of_property_read_u32(of_node, + "qcom,qpnp-lab-ps-threshold", &tmp); + + if (rc < 0) { + pr_err("get qcom,qpnp-lab-ps-threshold failed rc = %d\n", + rc); + return rc; + } + rc = labibb->lab_ver_ops->ps_ctl(labibb, tmp, true); + if (rc < 0) + return rc; + } else { + rc = labibb->lab_ver_ops->ps_ctl(labibb, tmp, false); + if (rc < 0) + return rc; } - for (val = 0; val < ARRAY_SIZE(lab_ps_threshold_plan); val++) - if (lab_ps_threshold_plan[val] == tmp) - break; + val = 0; + mask = 0; + rc = of_property_read_u32(of_node, "qcom,qpnp-lab-pfet-size", &tmp); + if (!rc) { + for (val = 0; val < ARRAY_SIZE(lab_rdson_pfet_table); val++) + if (tmp == lab_rdson_pfet_table[val]) + break; - if (val == ARRAY_SIZE(lab_ps_threshold_plan)) { - pr_err("Invalid property in qcom,qpnp-lab-ps-threshold\n"); - return -EINVAL; + if (val == ARRAY_SIZE(lab_rdson_pfet_table)) { + pr_err("Invalid value in qcom,qpnp-lab-pfet-size\n"); + return -EINVAL; + } + val |= LAB_RDSON_MNGMNT_PFET_SLEW_EN; + mask |= LAB_RDSON_MNGMNT_PFET_MASK | + LAB_RDSON_MNGMNT_PFET_SLEW_EN; } - if (of_property_read_bool(of_node, "qcom,qpnp-lab-ps-enable")) - val |= LAB_PS_CTL_EN; + rc = of_property_read_u32(of_node, "qcom,qpnp-lab-nfet-size", + &tmp); + if (!rc) { + for (i = 0; i < ARRAY_SIZE(lab_rdson_nfet_table); i++) + if (tmp == lab_rdson_nfet_table[i]) + break; - rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_PS_CTL, - &val, 1); + if (i == ARRAY_SIZE(lab_rdson_nfet_table)) { + pr_err("Invalid value in qcom,qpnp-lab-nfet-size\n"); + return -EINVAL; + } - if (rc) { - pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", - REG_LAB_PS_CTL, rc); - return rc; + val |= i << LAB_RDSON_MNGMNT_NFET_SHIFT; + val |= LAB_RDSON_MNGMNT_NFET_SLEW_EN; + mask |= LAB_RDSON_MNGMNT_NFET_MASK | + LAB_RDSON_MNGMNT_NFET_SLEW_EN; } - rc = of_property_read_u32(of_node, "qcom,qpnp-lab-pfet-size", &tmp); - - if (rc) { - pr_err("get qcom,qpnp-lab-pfet-size, rc = %d\n", rc); + rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + + REG_LAB_RDSON_MNGMNT, mask, val); + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", + REG_LAB_RDSON_MNGMNT, rc); return rc; } - for (val = 0; val < ARRAY_SIZE(lab_rdson_pfet_plan); val++) - if (tmp == lab_rdson_pfet_plan[val]) - break; - - if (val == ARRAY_SIZE(lab_rdson_pfet_plan)) { - pr_err("Invalid property in qcom,qpnp-lab-pfet-size\n"); - return -EINVAL; + rc = of_property_read_u32(of_node, "qcom,qpnp-lab-init-voltage", + &(labibb->lab_vreg.curr_volt)); + if (rc < 0) { + pr_err("get qcom,qpnp-lab-init-voltage failed, rc = %d\n", + rc); + return rc; } - rc = of_property_read_u32(of_node, "qcom,qpnp-lab-nfet-size", &tmp); + if (of_property_read_bool(of_node, + "qcom,qpnp-lab-use-default-voltage")) + rc = labibb->lab_ver_ops->set_default_voltage(labibb, true); + else + rc = labibb->lab_ver_ops->set_default_voltage(labibb, false); - if (rc) { - pr_err("get qcom,qpnp-lab-nfet-size, rc = %d\n", rc); + if (rc < 0) return rc; - } - for (i = 0; i < ARRAY_SIZE(lab_rdson_nfet_plan); i++) - if (tmp == lab_rdson_nfet_plan[i]) - break; + if (of_property_read_bool(of_node, + "qcom,qpnp-lab-enable-sw-high-psrr")) { + val = LAB_EN_SW_HIGH_PSRR_MODE; - if (i == ARRAY_SIZE(lab_rdson_nfet_plan)) { - pr_err("Iniid property in qcom,qpnp-lab-nfet-size\n"); - return -EINVAL; + rc = qpnp_labibb_write(labibb, labibb->lab_base + + REG_LAB_SW_HIGH_PSRR_CTL, &val, 1); + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", + REG_LAB_SW_HIGH_PSRR_CTL, rc); + return rc; + } } - val |= i << LAB_RDSON_MNGMNT_NFET_SHIFT; - val |= (LAB_RDSON_MNGMNT_NFET_SLEW_EN | LAB_RDSON_MNGMNT_PFET_SLEW_EN); - - rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_RDSON_MNGMNT, - &val, 1); - if (rc) { - pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", - REG_LAB_RDSON_MNGMNT, rc); - return rc; + rc = of_property_read_u32(of_node, + "qcom,qpnp-lab-ldo-pulldown-enable", (u32 *)&val); + if (!rc) { + rc = qpnp_labibb_write(labibb, labibb->lab_base + + REG_LAB_LDO_PD_CTL, &val, 1); + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", + REG_LAB_LDO_PD_CTL, rc); + return rc; + } } - rc = of_property_read_u32(of_node, "qcom,qpnp-lab-init-voltage", - &(labibb->lab_vreg.curr_volt)); - if (rc) { - pr_err("get qcom,qpnp-lab-init-voltage failed, rc = %d\n", rc); - return rc; - } + rc = of_property_read_u32(of_node, + "qcom,qpnp-lab-high-psrr-src-select", &tmp); + if (!rc) { + val = tmp; - if (!of_property_read_bool(of_node, - "qcom,qpnp-lab-use-default-voltage")) { - if (labibb->lab_vreg.curr_volt < labibb->lab_vreg.min_volt) { - pr_err("Invalid qcom,qpnp-lab-init-voltage property, qcom,qpnp-lab-init-voltage %d is less than the the minimum voltage %d", - labibb->lab_vreg.curr_volt, - labibb->lab_vreg.min_volt); - return -EINVAL; + rc = of_property_read_u32(of_node, + "qcom,qpnp-lab-vref-high-psrr-select", &tmp); + if (rc < 0) { + pr_err("get qcom,qpnp-lab-vref-high-psrr-select failed rc = %d\n", + rc); + return rc; } - val = DIV_ROUND_UP(labibb->lab_vreg.curr_volt - - labibb->lab_vreg.min_volt, - labibb->lab_vreg.step_size); + for (i = 0; i < ARRAY_SIZE(lab_vref_high_psrr_table); i++) + if (lab_vref_high_psrr_table[i] == tmp) + break; - if (val > LAB_VOLTAGE_SET_MASK) { - pr_err("Invalid qcom,qpnp-lab-init-voltage property, qcom,qpnp-lab-init-voltage %d is larger than the max supported voltage %d", - labibb->lab_vreg.curr_volt, - labibb->lab_vreg.min_volt + - labibb->lab_vreg.step_size * - LAB_VOLTAGE_SET_MASK); + if (i == ARRAY_SIZE(lab_vref_high_psrr_table)) { + pr_err("Invalid value in qpnp-lab-vref-high-psrr-selct\n"); return -EINVAL; } + val |= (i << LAB_SEL_HW_HIGH_PSRR_SRC_SHIFT); - labibb->lab_vreg.curr_volt = val * labibb->lab_vreg.step_size + - labibb->lab_vreg.min_volt; - val |= LAB_VOLTAGE_OVERRIDE_EN; - } else { - val = 0; - } - - rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + - REG_LAB_VOLTAGE, - LAB_VOLTAGE_SET_MASK | - LAB_VOLTAGE_OVERRIDE_EN, + rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + + REG_LAB_VPH_ENVELOP_CTL, + LAB_VREF_HIGH_PSRR_SEL_MASK | + LAB_SEL_HW_HIGH_PSRR_SRC_MASK, val); - if (rc) { - pr_err("write to register %x failed rc = %d\n", REG_LAB_VOLTAGE, - rc); - return rc; + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", + REG_LAB_VPH_ENVELOP_CTL, rc); + return rc; + } } if (labibb->swire_control) { rc = qpnp_ibb_set_mode(labibb, IBB_HW_CONTROL); - if (rc) + if (rc < 0) { pr_err("Unable to set SWIRE_RDY rc=%d\n", rc); + return rc; + } } - return rc; + return 0; } #define LAB_CURRENT_MAX_1600MA 0x7 @@ -1038,14 +1786,14 @@ static int qpnp_labibb_restore_settings(struct qpnp_labibb *labibb) if (ibb_settings[i].sec_access) rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, ibb_settings[i].address, - &ibb_settings[i].value, 1); + ibb_settings[i].value); else rc = qpnp_labibb_write(labibb, labibb->ibb_base + ibb_settings[i].address, &ibb_settings[i].value, 1); - if (rc) { - pr_err("qpnp_labibb_write register %x failed rc = %d\n", + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", ibb_settings[i].address, rc); return rc; } @@ -1055,14 +1803,14 @@ static int qpnp_labibb_restore_settings(struct qpnp_labibb *labibb) if (lab_settings[i].sec_access) rc = qpnp_labibb_sec_write(labibb, labibb->lab_base, lab_settings[i].address, - &lab_settings[i].value, 1); + lab_settings[i].value); else rc = qpnp_labibb_write(labibb, labibb->lab_base + lab_settings[i].address, &lab_settings[i].value, 1); - if (rc) { - pr_err("qpnp_labibb_write register %x failed rc = %d\n", + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", lab_settings[i].address, rc); return rc; } @@ -1076,22 +1824,20 @@ static int qpnp_labibb_save_settings(struct qpnp_labibb *labibb) int rc, i; for (i = 0; i < ARRAY_SIZE(ibb_settings); i++) { - rc = qpnp_labibb_read(labibb, &ibb_settings[i].value, - labibb->ibb_base + - ibb_settings[i].address, 1); - if (rc) { - pr_err("qpnp_labibb_read register %x failed rc = %d\n", + rc = qpnp_labibb_read(labibb, labibb->ibb_base + + ibb_settings[i].address, &ibb_settings[i].value, 1); + if (rc < 0) { + pr_err("read register %x failed rc = %d\n", ibb_settings[i].address, rc); return rc; } } for (i = 0; i < ARRAY_SIZE(lab_settings); i++) { - rc = qpnp_labibb_read(labibb, &lab_settings[i].value, - labibb->lab_base + - lab_settings[i].address, 1); - if (rc) { - pr_err("qpnp_labibb_read register %x failed rc = %d\n", + rc = qpnp_labibb_read(labibb, labibb->lab_base + + lab_settings[i].address, &lab_settings[i].value, 1); + if (rc < 0) { + pr_err("read register %x failed rc = %d\n", lab_settings[i].address, rc); return rc; } @@ -1108,17 +1854,17 @@ static int qpnp_labibb_ttw_enter_ibb_common(struct qpnp_labibb *labibb) val = 0; rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_PD_CTL, &val, 1); - if (rc) { - pr_err("qpnp_labibb_read register %x failed rc = %d\n", + if (rc < 0) { + pr_err("read register %x failed rc = %d\n", REG_IBB_PD_CTL, rc); return rc; } val = 0; rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, - REG_IBB_PWRUP_PWRDN_CTL_1, &val, 1); - if (rc) { - pr_err("qpnp_labibb_write register %x failed rc = %d\n", + REG_IBB_PWRUP_PWRDN_CTL_1, val); + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", REG_IBB_PWRUP_PWRDN_CTL_1, rc); return rc; } @@ -1127,8 +1873,8 @@ static int qpnp_labibb_ttw_enter_ibb_common(struct qpnp_labibb *labibb) rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base, REG_IBB_PWRUP_PWRDN_CTL_2, IBB_DIS_DLY_MASK | IBB_WAIT_MBG_OK, val); - if (rc) { - pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n", + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", REG_IBB_PWRUP_PWRDN_CTL_2, rc); return rc; } @@ -1137,8 +1883,8 @@ static int qpnp_labibb_ttw_enter_ibb_common(struct qpnp_labibb *labibb) IBB_OVERRIDE_PFET_SW_SIZE; rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + REG_IBB_RDSON_MNGMNT, 0xFF, val); - if (rc) { - pr_err("qpnp_labibb_write register %x failed rc = %d\n", + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", REG_IBB_RDSON_MNGMNT, rc); return rc; } @@ -1146,9 +1892,9 @@ static int qpnp_labibb_ttw_enter_ibb_common(struct qpnp_labibb *labibb) val = IBB_CURRENT_LIMIT_EN | IBB_CURRENT_MAX_500MA | (IBB_ILIMIT_COUNT_CYC8 << IBB_CURRENT_LIMIT_DEBOUNCE_SHIFT); rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, - REG_IBB_CURRENT_LIMIT, &val, 1); - if (rc) - pr_err("qpnp_labibb_write register %x failed rc = %d\n", + REG_IBB_CURRENT_LIMIT, val); + if (rc < 0) + pr_err("write to register %x failed rc = %d\n", REG_IBB_CURRENT_LIMIT, rc); return rc; @@ -1162,8 +1908,8 @@ static int qpnp_labibb_ttw_enter_ibb_pmi8996(struct qpnp_labibb *labibb) val = IBB_BYPASS_PWRDN_DLY2_BIT | IBB_FAST_STARTUP; rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_SPARE_CTL, &val, 1); - if (rc) - pr_err("qpnp_labibb_write register %x failed rc = %d\n", + if (rc < 0) + pr_err("write to register %x failed rc = %d\n", REG_IBB_SPARE_CTL, rc); return rc; @@ -1175,7 +1921,7 @@ static int qpnp_labibb_ttw_enter_ibb_pmi8950(struct qpnp_labibb *labibb) u8 val; rc = qpnp_ibb_ps_config(labibb, true); - if (rc) { + if (rc < 0) { pr_err("Failed to enable ibb_ps_config rc=%d\n", rc); return rc; } @@ -1183,8 +1929,8 @@ static int qpnp_labibb_ttw_enter_ibb_pmi8950(struct qpnp_labibb *labibb) val = IBB_SOFT_START_CHARGING_RESISTOR_16K; rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_SOFT_START_CTL, &val, 1); - if (rc) { - pr_err("qpnp_labibb_write register %x failed rc = %d\n", + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", REG_IBB_SOFT_START_CTL, rc); return rc; } @@ -1192,8 +1938,8 @@ static int qpnp_labibb_ttw_enter_ibb_pmi8950(struct qpnp_labibb *labibb) val = IBB_MODULE_RDY_EN; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_IBB_MODULE_RDY, &val, 1); - if (rc) - pr_err("qpnp_labibb_write register %x failed rc = %d\n", + if (rc < 0) + pr_err("write to register %x failed rc = %d\n", REG_IBB_MODULE_RDY, rc); return rc; @@ -1218,8 +1964,8 @@ static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) val = LAB_MODULE_RDY_EN; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_MODULE_RDY, &val, 1); - if (rc) { - pr_err("qpnp_labibb_write register %x failed rc = %d\n", + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", REG_LAB_MODULE_RDY, rc); return rc; } @@ -1228,8 +1974,8 @@ static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) val = LAB_ENABLE_CTL_EN; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_ENABLE_CTL, &val, 1); - if (rc) { - pr_err("qpnp_labibb_write register %x failed rc = %d\n", + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", REG_LAB_ENABLE_CTL, rc); return rc; } @@ -1240,15 +1986,15 @@ static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) LAB_RDSON_PFET_SW_SIZE_QUARTER; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_RDSON_MNGMNT, &val, 1); - if (rc) { - pr_err("qpnp_labibb_write register %x failed rc = %d\n", + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", REG_LAB_RDSON_MNGMNT, rc); return rc; } rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + REG_LAB_PS_CTL, LAB_PS_CTL_EN, LAB_PS_CTL_EN); - if (rc) { + if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_PS_CTL, rc); return rc; @@ -1257,7 +2003,7 @@ static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) val = LAB_PD_CTL_DISABLE_PD; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_PD_CTL, &val, 1); - if (rc) { + if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_PD_CTL, rc); return rc; @@ -1268,7 +2014,7 @@ static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) val |= LAB_SPARE_TOUCH_WAKE_BIT; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_SPARE_CTL, &val, 1); - if (rc) { + if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_SPARE_CTL, rc); return rc; @@ -1277,7 +2023,7 @@ static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) val = 0; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_SOFT_START_CTL, &val, 1); - if (rc) { + if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_SOFT_START_CTL, rc); return rc; @@ -1298,13 +2044,13 @@ static int qpnp_labibb_regulator_ttw_mode_enter(struct qpnp_labibb *labibb) rc = qpnp_labibb_ttw_enter_ibb_pmi8950(labibb); break; } - if (rc) { + if (rc < 0) { pr_err("Failed to configure TTW-enter for IBB rc=%d\n", rc); return rc; } rc = qpnp_ibb_set_mode(labibb, IBB_HW_CONTROL); - if (rc) { + if (rc < 0) { pr_err("Unable to set SWIRE_RDY rc = %d\n", rc); return rc; } @@ -1320,7 +2066,7 @@ static int qpnp_labibb_ttw_exit_ibb_common(struct qpnp_labibb *labibb) val = IBB_FASTER_PFET_OFF; rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_SPARE_CTL, &val, 1); - if (rc) + if (rc < 0) pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_IBB_SPARE_CTL, rc); @@ -1339,7 +2085,7 @@ static int qpnp_labibb_regulator_ttw_mode_exit(struct qpnp_labibb *labibb) /* Restore the IBB settings back to switch back to normal mode */ rc = qpnp_labibb_restore_settings(labibb); - if (rc) { + if (rc < 0) { pr_err("Error in restoring IBB setttings, rc=%d\n", rc); return rc; } @@ -1348,7 +2094,7 @@ static int qpnp_labibb_regulator_ttw_mode_exit(struct qpnp_labibb *labibb) val = 0; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_ENABLE_CTL, &val, 1); - if (rc) { + if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_ENABLE_CTL, rc); return rc; @@ -1357,7 +2103,7 @@ static int qpnp_labibb_regulator_ttw_mode_exit(struct qpnp_labibb *labibb) val = LAB_PD_CTL_STRONG_PULL; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_PD_CTL, &val, 1); - if (rc) { + if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_PD_CTL, rc); return rc; @@ -1366,7 +2112,7 @@ static int qpnp_labibb_regulator_ttw_mode_exit(struct qpnp_labibb *labibb) val = 0; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_SPARE_CTL, &val, 1); - if (rc) { + if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_SPARE_CTL, rc); return rc; @@ -1380,7 +2126,7 @@ static int qpnp_labibb_regulator_ttw_mode_exit(struct qpnp_labibb *labibb) rc = qpnp_labibb_ttw_exit_ibb_common(labibb); break; } - if (rc) { + if (rc < 0) { pr_err("Failed to configure TTW-exit for IBB rc=%d\n", rc); return rc; } @@ -1418,9 +2164,9 @@ static int qpnp_labibb_regulator_enable(struct qpnp_labibb *labibb) usleep_range(dly, dly + 100); /* after this delay, lab should be enabled */ - rc = qpnp_labibb_read(labibb, &val, - labibb->lab_base + REG_LAB_STATUS1, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->lab_base + REG_LAB_STATUS1, + &val, 1); + if (rc < 0) { pr_err("read register %x failed rc = %d\n", REG_LAB_STATUS1, rc); goto err_out; @@ -1439,9 +2185,9 @@ static int qpnp_labibb_regulator_enable(struct qpnp_labibb *labibb) dly = labibb->ibb_vreg.soft_start + labibb->ibb_vreg.pwrup_dly; retries = 10; while (retries--) { - rc = qpnp_labibb_read(labibb, &val, - labibb->ibb_base + REG_IBB_STATUS1, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->ibb_base + + REG_IBB_STATUS1, &val, 1); + if (rc < 0) { pr_err("read register %x failed rc = %d\n", REG_IBB_STATUS1, rc); goto err_out; @@ -1465,7 +2211,7 @@ static int qpnp_labibb_regulator_enable(struct qpnp_labibb *labibb) return 0; err_out: rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_DIS); - if (rc) { + if (rc < 0) { pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc); return rc; } @@ -1490,7 +2236,7 @@ static int qpnp_labibb_regulator_disable(struct qpnp_labibb *labibb) */ if (labibb->ttw_en && !labibb->in_ttw_mode) { rc = qpnp_labibb_regulator_ttw_mode_enter(labibb); - if (rc) { + if (rc < 0) { pr_err("Error in entering TTW mode rc = %d\n", rc); return rc; } @@ -1500,7 +2246,7 @@ static int qpnp_labibb_regulator_disable(struct qpnp_labibb *labibb) } rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_DIS); - if (rc) { + if (rc < 0) { pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc); return rc; } @@ -1510,9 +2256,9 @@ static int qpnp_labibb_regulator_disable(struct qpnp_labibb *labibb) retries = 2; while (retries--) { usleep_range(dly, dly + 100); - rc = qpnp_labibb_read(labibb, &val, - labibb->ibb_base + REG_IBB_STATUS1, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->ibb_base + + REG_IBB_STATUS1, &val, 1); + if (rc < 0) { pr_err("read register %x failed rc = %d\n", REG_IBB_STATUS1, rc); return rc; @@ -1553,7 +2299,7 @@ static int qpnp_lab_regulator_enable(struct regulator_dev *rdev) if (labibb->skip_2nd_swire_cmd) { rc = qpnp_ibb_ps_config(labibb, false); - if (rc) { + if (rc < 0) { pr_err("Failed to disable IBB PS rc=%d\n", rc); return rc; } @@ -1567,7 +2313,7 @@ static int qpnp_lab_regulator_enable(struct regulator_dev *rdev) val = LAB_ENABLE_CTL_EN; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_ENABLE_CTL, &val, 1); - if (rc) { + if (rc < 0) { pr_err("qpnp_lab_regulator_enable write register %x failed rc = %d\n", REG_LAB_ENABLE_CTL, rc); return rc; @@ -1575,9 +2321,9 @@ static int qpnp_lab_regulator_enable(struct regulator_dev *rdev) udelay(labibb->lab_vreg.soft_start); - rc = qpnp_labibb_read(labibb, &val, - labibb->lab_base + REG_LAB_STATUS1, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->lab_base + + REG_LAB_STATUS1, &val, 1); + if (rc < 0) { pr_err("qpnp_lab_regulator_enable read register %x failed rc = %d\n", REG_LAB_STATUS1, rc); return rc; @@ -1608,7 +2354,7 @@ static int qpnp_lab_regulator_disable(struct regulator_dev *rdev) val = 0; rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_ENABLE_CTL, &val, 1); - if (rc) { + if (rc < 0) { pr_err("qpnp_lab_regulator_enable write register %x failed rc = %d\n", REG_LAB_ENABLE_CTL, rc); return rc; @@ -1661,7 +2407,7 @@ static int qpnp_lab_regulator_set_voltage(struct regulator_dev *rdev, LAB_VOLTAGE_OVERRIDE_EN, val | LAB_VOLTAGE_OVERRIDE_EN); - if (rc) { + if (rc < 0) { pr_err("write to register %x failed rc = %d\n", REG_LAB_VOLTAGE, rc); return rc; @@ -1684,9 +2430,9 @@ static int qpnp_skip_swire_command(struct qpnp_labibb *labibb) do { /* poll for ibb vreg_ok */ - rc = qpnp_labibb_read(labibb, ®, - labibb->ibb_base + REG_IBB_STATUS1, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->ibb_base + + REG_IBB_STATUS1, ®, 1); + if (rc < 0) { pr_err("Failed to read ibb_status1 reg rc=%d\n", rc); return rc; } @@ -1705,7 +2451,7 @@ static int qpnp_skip_swire_command(struct qpnp_labibb *labibb) /* move to SW control */ rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_EN); - if (rc) { + if (rc < 0) { pr_err("Failed switch to IBB_SW_CONTROL rc=%d\n", rc); return rc; } @@ -1720,7 +2466,7 @@ static int qpnp_skip_swire_command(struct qpnp_labibb *labibb) usleep_range(dly, dly + 10); rc = qpnp_ibb_set_mode(labibb, IBB_HW_SW_CONTROL); - if (rc) { + if (rc < 0) { pr_err("Failed switch to IBB_HW_SW_CONTROL rc=%d\n", rc); return rc; } @@ -1730,13 +2476,13 @@ static int qpnp_skip_swire_command(struct qpnp_labibb *labibb) /* Move back to SWIRE control */ rc = qpnp_ibb_set_mode(labibb, IBB_HW_CONTROL); - if (rc) + if (rc < 0) pr_err("Failed switch to IBB_HW_CONTROL rc=%d\n", rc); /* delay before enabling the PS mode */ msleep(labibb->swire_ibb_ps_enable_delay); rc = qpnp_ibb_ps_config(labibb, true); - if (rc) + if (rc < 0) pr_err("Unable to enable IBB PS rc=%d\n", rc); return rc; @@ -1804,7 +2550,7 @@ static int register_qpnp_lab_regulator(struct qpnp_labibb *labibb, struct regulator_init_data *init_data; struct regulator_desc *rdesc = &labibb->lab_vreg.rdesc; struct regulator_config cfg = {}; - u8 val; + u8 val, mask; const char *current_sense_str; bool config_current_sense = false; u32 tmp; @@ -1845,54 +2591,53 @@ static int register_qpnp_lab_regulator(struct qpnp_labibb *labibb, rc = of_property_read_u32(of_node, "qcom,qpnp-lab-soft-start", &(labibb->lab_vreg.soft_start)); - if (rc < 0) { - pr_err("qcom,qpnp-lab-soft-start is missing, rc = %d\n", - rc); - return rc; - } - - for (val = 0; val < ARRAY_SIZE(lab_soft_start_plan); val++) - if (lab_soft_start_plan[val] == labibb->lab_vreg.soft_start) - break; + if (!rc) { + for (val = 0; val < ARRAY_SIZE(lab_soft_start_table); val++) + if (lab_soft_start_table[val] == + labibb->lab_vreg.soft_start) + break; - if (val == ARRAY_SIZE(lab_soft_start_plan)) - val = ARRAY_SIZE(lab_soft_start_plan) - 1; + if (val == ARRAY_SIZE(lab_soft_start_table)) + val = ARRAY_SIZE(lab_soft_start_table) - 1; - rc = qpnp_labibb_write(labibb, labibb->lab_base + + rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_SOFT_START_CTL, &val, 1); - if (rc) { - pr_err("qpnp_labibb_write register %x failed rc = %d\n", - REG_LAB_SOFT_START_CTL, rc); - return rc; - } + if (rc < 0) { + pr_err("qpnp_labibb_write register %x failed rc = %d\n", + REG_LAB_SOFT_START_CTL, rc); + return rc; + } - labibb->lab_vreg.soft_start = lab_soft_start_plan + labibb->lab_vreg.soft_start = lab_soft_start_table [val & LAB_SOFT_START_CTL_MASK]; - - rc = of_property_read_u32(of_node, "qcom,qpnp-lab-max-precharge-time", - &tmp); - if (rc) { - pr_err("get qcom,qpnp-lab-max-precharge-time failed, rc = %d\n", - rc); - return rc; } - for (val = 0; val < ARRAY_SIZE(lab_max_precharge_plan); val++) - if (lab_max_precharge_plan[val] == tmp) - break; + val = 0; + mask = 0; + rc = of_property_read_u32(of_node, + "qcom,qpnp-lab-max-precharge-time", &tmp); + if (!rc) { + for (val = 0; val < ARRAY_SIZE(lab_max_precharge_table); val++) + if (lab_max_precharge_table[val] == tmp) + break; - if (val == ARRAY_SIZE(lab_max_precharge_plan)) { - pr_err("Invalid property in qcom,qpnp-lab-max-precharge-time\n"); - return -EINVAL; + if (val == ARRAY_SIZE(lab_max_precharge_table)) { + pr_err("Invalid value in qcom,qpnp-lab-max-precharge-time\n"); + return -EINVAL; + } + + mask = LAB_MAX_PRECHARGE_TIME_MASK; } if (of_property_read_bool(of_node, - "qcom,qpnp-lab-max-precharge-enable")) - val |= LAB_PRECHARGE_CTL_EN; + "qcom,qpnp-lab-max-precharge-enable")) { + val |= LAB_FAST_PRECHARGE_CTL_EN; + mask |= LAB_FAST_PRECHARGE_CTL_EN; + } - rc = qpnp_labibb_write(labibb, labibb->lab_base + - REG_LAB_PRECHARGE_CTL, &val, 1); - if (rc) { + rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + + REG_LAB_PRECHARGE_CTL, mask, val); + if (rc < 0) { pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", REG_LAB_PRECHARGE_CTL, rc); return rc; @@ -1930,7 +2675,7 @@ static int register_qpnp_lab_regulator(struct qpnp_labibb *labibb, REG_LAB_CURRENT_SENSE, LAB_CURRENT_SENSE_GAIN_MASK, val); - if (rc) { + if (rc < 0) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_LAB_CURRENT_SENSE, rc); return rc; @@ -1939,17 +2684,17 @@ static int register_qpnp_lab_regulator(struct qpnp_labibb *labibb, val = (labibb->standalone) ? 0 : LAB_IBB_EN_RDY_EN; rc = qpnp_labibb_sec_write(labibb, labibb->lab_base, - REG_LAB_IBB_EN_RDY, &val, 1); + REG_LAB_IBB_EN_RDY, val); - if (rc) { + if (rc < 0) { pr_err("qpnp_lab_sec_write register %x failed rc = %d\n", REG_LAB_IBB_EN_RDY, rc); return rc; } - rc = qpnp_labibb_read(labibb, &val, - labibb->ibb_base + REG_IBB_ENABLE_CTL, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_ENABLE_CTL, + &val, 1); + if (rc < 0) { pr_err("qpnp_labibb_read register %x failed rc = %d\n", REG_IBB_ENABLE_CTL, rc); return rc; @@ -1958,53 +2703,41 @@ static int register_qpnp_lab_regulator(struct qpnp_labibb *labibb, if (!(val & (IBB_ENABLE_CTL_SWIRE_RDY | IBB_ENABLE_CTL_MODULE_EN))) { /* SWIRE_RDY and IBB_MODULE_EN not enabled */ rc = qpnp_lab_dt_init(labibb, of_node); - if (rc) { + if (rc < 0) { pr_err("qpnp-lab: wrong DT parameter specified: rc = %d\n", rc); return rc; } } else { - rc = qpnp_labibb_read(labibb, &val, - labibb->lab_base + REG_LAB_LCD_AMOLED_SEL, 1); - if (rc) { - pr_err("qpnp_labibb_read register %x failed rc = %d\n", - REG_LAB_LCD_AMOLED_SEL, rc); - return rc; - } - - if (val == REG_LAB_IBB_AMOLED_MODE) - labibb->mode = QPNP_LABIBB_AMOLED_MODE; - else - labibb->mode = QPNP_LABIBB_LCD_MODE; + rc = labibb->ibb_ver_ops->get_mode(labibb); - rc = qpnp_labibb_read(labibb, &val, labibb->lab_base + - REG_LAB_VOLTAGE, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->lab_base + + REG_LAB_VOLTAGE, &val, 1); + if (rc < 0) { pr_err("qpnp_lab_read read register %x failed rc = %d\n", REG_LAB_VOLTAGE, rc); return rc; } - if (val & LAB_VOLTAGE_OVERRIDE_EN) { - labibb->lab_vreg.curr_volt = + labibb->lab_vreg.curr_volt = (val & LAB_VOLTAGE_SET_MASK) * labibb->lab_vreg.step_size + labibb->lab_vreg.min_volt; - } else if (labibb->mode == QPNP_LABIBB_LCD_MODE) { + if (labibb->mode == QPNP_LABIBB_LCD_MODE) { rc = of_property_read_u32(of_node, "qcom,qpnp-lab-init-lcd-voltage", &(labibb->lab_vreg.curr_volt)); - if (rc) { + if (rc < 0) { pr_err("get qcom,qpnp-lab-init-lcd-voltage failed, rc = %d\n", rc); return rc; } - } else { + } else if (!(val & LAB_VOLTAGE_OVERRIDE_EN)) { rc = of_property_read_u32(of_node, "qcom,qpnp-lab-init-amoled-voltage", &(labibb->lab_vreg.curr_volt)); - if (rc) { + if (rc < 0) { pr_err("get qcom,qpnp-lab-init-amoled-voltage failed, rc = %d\n", rc); return rc; @@ -2027,9 +2760,9 @@ static int register_qpnp_lab_regulator(struct qpnp_labibb *labibb, } } - rc = qpnp_labibb_read(labibb, &val, - labibb->lab_base + REG_LAB_MODULE_RDY, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->lab_base + REG_LAB_MODULE_RDY, + &val, 1); + if (rc < 0) { pr_err("qpnp_lab_read read register %x failed rc = %d\n", REG_LAB_MODULE_RDY, rc); return rc; @@ -2041,7 +2774,7 @@ static int register_qpnp_lab_regulator(struct qpnp_labibb *labibb, rc = qpnp_labibb_write(labibb, labibb->lab_base + REG_LAB_MODULE_RDY, &val, 1); - if (rc) { + if (rc < 0) { pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", REG_LAB_MODULE_RDY, rc); return rc; @@ -2084,12 +2817,161 @@ static int register_qpnp_lab_regulator(struct qpnp_labibb *labibb, return 0; } +static int qpnp_ibb_pfm_mode_enable(struct qpnp_labibb *labibb, + struct device_node *of_node) +{ + int rc = 0; + u32 i, tmp = 0; + u8 val = IBB_PFM_ENABLE; + + rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-pfm-peak-curr", + &tmp); + if (rc < 0) { + pr_err("qcom,qpnp-ibb-pfm-peak-curr is missing, rc = %d\n", + rc); + return rc; + } + for (i = 0; i < ARRAY_SIZE(ibb_pfm_peak_curr_table); i++) + if (ibb_pfm_peak_curr_table[i] == tmp) + break; + + if (i == ARRAY_SIZE(ibb_pfm_peak_curr_table)) { + pr_err("Invalid value in qcom,qpnp-ibb-pfm-peak-curr\n"); + return -EINVAL; + } + + val |= (i << IBB_PFM_PEAK_CURRENT_BIT_SHIFT); + + rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-pfm-hysteresis", + &tmp); + if (rc < 0) { + pr_err("qcom,qpnp-ibb-pfm-hysteresis is missing, rc = %d\n", + rc); + return rc; + } + + for (i = 0; i < ARRAY_SIZE(ibb_pfm_hysteresis_table); i++) + if (ibb_pfm_hysteresis_table[i] == tmp) + break; + + if (i == ARRAY_SIZE(ibb_pfm_hysteresis_table)) { + pr_err("Invalid value in qcom,qpnp-ibb-pfm-hysteresis\n"); + return -EINVAL; + } + + val |= (i << IBB_PFM_HYSTERESIS_BIT_SHIFT); + + rc = qpnp_labibb_write(labibb, labibb->ibb_base + + REG_IBB_PFM_CTL, &val, 1); + if (rc < 0) + pr_err("qpnp_ibb_pfm_ctl write register %x failed rc = %d\n", + REG_IBB_PFM_CTL, rc); + + return rc; +} + +static int qpnp_labibb_pbs_mode_enable(struct qpnp_labibb *labibb, + struct device_node *of_node) +{ + int rc = 0; + + rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + + REG_IBB_SWIRE_CTL, + IBB_SWIRE_VOUT_UPD_EN, 0); + if (rc < 0) { + pr_err("qpnp_ibb_swire_ctl write register %x failed rc = %d\n", + REG_IBB_SWIRE_CTL, rc); + return rc; + } + + rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + + REG_IBB_PD_CTL, IBB_SWIRE_PD_UPD, 0); + if (rc < 0) { + pr_err("qpnp_ibb_pd_ctl write register %x failed rc = %d\n", + REG_IBB_PD_CTL, rc); + return rc; + } + + rc = qpnp_labibb_masked_write(labibb, labibb->lab_base + + REG_LAB_SWIRE_PGM_CTL, LAB_EN_SWIRE_PGM_VOUT | + LAB_EN_SWIRE_PGM_PD, 0); + if (rc < 0) + pr_err("qpnp_lab_swire_pgm_ctl write register %x failed rc = %d\n", + REG_LAB_SWIRE_PGM_CTL, rc); + + return rc; +} + +static int qpnp_ibb_slew_rate_config(struct qpnp_labibb *labibb, + struct device_node *of_node) +{ + int rc = 0; + u32 i, tmp = 0; + u8 val = 0, mask = 0; + + rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-fast-slew-rate", + &tmp); + if (!rc) { + for (i = 0; i < ARRAY_SIZE(ibb_output_slew_ctl_table); i++) + if (ibb_output_slew_ctl_table[i] == tmp) + break; + + if (i == ARRAY_SIZE(ibb_output_slew_ctl_table)) { + pr_err("Invalid value in qcom,qpnp-ibb-fast-slew-rate\n"); + return -EINVAL; + } + + labibb->ibb_vreg.slew_rate = tmp; + val |= (i << IBB_SLEW_RATE_TRANS_TIME_FAST_SHIFT) | + IBB_SLEW_RATE_SPEED_FAST_EN | IBB_SLEW_CTL_EN; + + mask = IBB_SLEW_RATE_SPEED_FAST_EN | + IBB_SLEW_RATE_TRANS_TIME_FAST_MASK | IBB_SLEW_CTL_EN; + } + + rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-slow-slew-rate", + &tmp); + if (!rc) { + for (i = 0; i < ARRAY_SIZE(ibb_output_slew_ctl_table); i++) + if (ibb_output_slew_ctl_table[i] == tmp) + break; + + if (i == ARRAY_SIZE(ibb_output_slew_ctl_table)) { + pr_err("Invalid value in qcom,qpnp-ibb-slow-slew-rate\n"); + return -EINVAL; + } + + labibb->ibb_vreg.slew_rate = tmp; + val |= (i | IBB_SLEW_CTL_EN); + + mask |= IBB_SLEW_RATE_SPEED_FAST_EN | + IBB_SLEW_RATE_TRANS_TIME_SLOW_MASK | IBB_SLEW_CTL_EN; + } + + rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + + REG_IBB_OUTPUT_SLEW_CTL, + mask, val); + if (rc < 0) + pr_err("qpnp_labibb_write register %x failed rc = %d\n", + REG_IBB_OUTPUT_SLEW_CTL, rc); + + return rc; +} + +static bool qpnp_ibb_poff_ctl_required(struct qpnp_labibb *labibb) +{ + if (labibb->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) + return false; + + return true; +} + static int qpnp_ibb_dt_init(struct qpnp_labibb *labibb, struct device_node *of_node) { int rc = 0; - u32 i, tmp; - u8 val; + u32 i, tmp = 0; + u8 val, mask; /* * Do not configure LCD_AMOLED_SEL for pmi8998 as it will be done by @@ -2097,180 +2979,166 @@ static int qpnp_ibb_dt_init(struct qpnp_labibb *labibb, * by the bootloader. */ if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) { - rc = qpnp_labibb_read(labibb, &val, - labibb->ibb_base + REG_IBB_LCD_AMOLED_SEL, 1); + rc = qpnp_labibb_read(labibb, labibb->ibb_base + + REG_IBB_LCD_AMOLED_SEL, &val, 1); if (rc) { pr_err("qpnp_labibb_read register %x failed rc = %d\n", - REG_IBB_LCD_AMOLED_SEL, rc); + REG_IBB_LCD_AMOLED_SEL, rc); return rc; } - if (val == REG_LAB_IBB_AMOLED_MODE) labibb->mode = QPNP_LABIBB_AMOLED_MODE; else labibb->mode = QPNP_LABIBB_LCD_MODE; } else { - if (labibb->mode == QPNP_LABIBB_LCD_MODE) - val = REG_LAB_IBB_LCD_MODE; - else - val = REG_LAB_IBB_AMOLED_MODE; - - rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, - REG_LAB_LCD_AMOLED_SEL, &val, 1); - if (rc) { + rc = labibb->ibb_ver_ops->sel_mode(labibb, 1); + if (rc < 0) { pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n", REG_IBB_LCD_AMOLED_SEL, rc); return rc; } } - rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-lab-pwrdn-delay", - &tmp); - if (rc < 0) { - pr_err("qcom,qpnp-ibb-lab-pwrdn-delay is missing, rc = %d\n", - rc); - return rc; - } - val = 0; + mask = 0; + rc = of_property_read_u32(of_node, + "qcom,qpnp-ibb-lab-pwrdn-delay", &tmp); + if (!rc) { + for (val = 0; val < ARRAY_SIZE(ibb_pwrdn_dly_table); val++) + if (ibb_pwrdn_dly_table[val] == tmp) + break; - for (val = 0; val < ARRAY_SIZE(ibb_pwrdn_dly_plan); val++) - if (ibb_pwrdn_dly_plan[val] == tmp) - break; + if (val == ARRAY_SIZE(ibb_pwrdn_dly_table)) { + pr_err("Invalid value in qcom,qpnp-ibb-lab-pwrdn-delay\n"); + return -EINVAL; + } - if (val == ARRAY_SIZE(ibb_pwrdn_dly_plan)) { - pr_err("Invalid property in qcom,qpnp-ibb-lab-pwrdn-delay\n"); - return -EINVAL; + labibb->ibb_vreg.pwrdn_dly = tmp; + val |= IBB_PWRUP_PWRDN_CTL_1_EN_DLY2; + mask |= IBB_PWRUP_PWRDN_CTL_1_EN_DLY2; } - labibb->ibb_vreg.pwrdn_dly = tmp; + rc = of_property_read_u32(of_node, + "qcom,qpnp-ibb-lab-pwrup-delay", &tmp); + if (!rc) { + for (i = 0; i < ARRAY_SIZE(ibb_pwrup_dly_table); i++) + if (ibb_pwrup_dly_table[i] == tmp) + break; - rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-lab-pwrup-delay", - &tmp); - if (rc < 0) { - pr_err("qcom,qpnp-ibb-lab-pwrup-delay is missing, rc = %d\n", - rc); - return rc; - } + if (i == ARRAY_SIZE(ibb_pwrup_dly_table)) { + pr_err("Invalid value in qcom,qpnp-ibb-lab-pwrup-delay\n"); + return -EINVAL; + } - for (i = 0; i < ARRAY_SIZE(ibb_pwrup_dly_plan); i++) - if (ibb_pwrup_dly_plan[i] == tmp) - break; + labibb->ibb_vreg.pwrup_dly = tmp; - if (i == ARRAY_SIZE(ibb_pwrup_dly_plan)) { - pr_err("Invalid property in qcom,qpnp-ibb-lab-pwrup-delay\n"); - return -EINVAL; + val |= (i << IBB_PWRUP_PWRDN_CTL_1_DLY1_SHIFT); + val |= (IBB_PWRUP_PWRDN_CTL_1_EN_DLY1 | + IBB_PWRUP_PWRDN_CTL_1_LAB_VREG_OK); + mask |= (IBB_PWRUP_PWRDN_CTL_1_EN_DLY1 | + IBB_PWRUP_PWRDN_CTL_1_DLY1_MASK | + IBB_PWRUP_PWRDN_CTL_1_LAB_VREG_OK); } - labibb->ibb_vreg.pwrup_dly = tmp; - - val |= (i << IBB_PWRUP_PWRDN_CTL_1_DLY1_SHIFT); - - if (of_property_read_bool(of_node, "qcom,qpnp-ibb-en-discharge")) + if (of_property_read_bool(of_node, + "qcom,qpnp-ibb-en-discharge")) { val |= PWRUP_PWRDN_CTL_1_DISCHARGE_EN; + mask |= PWRUP_PWRDN_CTL_1_DISCHARGE_EN; + } - val |= (IBB_PWRUP_PWRDN_CTL_1_EN_DLY1 | - IBB_PWRUP_PWRDN_CTL_1_LAB_VREG_OK); - - rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, - REG_IBB_PWRUP_PWRDN_CTL_1, - &val, - 1); - if (rc) { + rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base, + REG_IBB_PWRUP_PWRDN_CTL_1, mask, val); + if (rc < 0) { pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n", REG_IBB_PWRUP_PWRDN_CTL_1, rc); return rc; } - val = 0; + if (of_property_read_bool(of_node, "qcom,qpnp-ibb-slew-rate-config")) { + rc = qpnp_ibb_slew_rate_config(labibb, of_node); + if (rc < 0) + return rc; + } + + val = 0; if (!of_property_read_bool(of_node, "qcom,qpnp-ibb-full-pull-down")) - val |= IBB_PD_CTL_HALF_STRENGTH; + val = IBB_PD_CTL_HALF_STRENGTH; if (of_property_read_bool(of_node, "qcom,qpnp-ibb-pull-down-enable")) val |= IBB_PD_CTL_EN; - rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_PD_CTL, - &val, 1); + mask = IBB_PD_CTL_STRENGTH_MASK | IBB_PD_CTL_EN; + rc = qpnp_labibb_masked_write(labibb, + labibb->ibb_base + REG_IBB_PD_CTL, mask, val); - if (rc) { + if (rc < 0) { pr_err("qpnp_lab_dt_init write register %x failed rc = %d\n", REG_IBB_PD_CTL, rc); return rc; } rc = of_property_read_u32(of_node, - "qcom,qpnp-ibb-switching-clock-frequency", &tmp); - if (rc) { - pr_err("get qcom,qpnp-ibb-switching-clock-frequency failed rc = %d\n", - rc); - return rc; - } - - for (val = 0; val < ARRAY_SIZE(ibb_clk_div_plan); val++) - if (ibb_clk_div_plan[val] == tmp) - break; - - if (val == ARRAY_SIZE(ibb_clk_div_plan)) { - pr_err("Invalid property in qpnp-ibb-switching-clock-frequency\n"); - return -EINVAL; - } + "qcom,qpnp-ibb-switching-clock-frequency", &tmp); + if (!rc) { + for (val = 0; val < ARRAY_SIZE(ibb_clk_div_table); val++) + if (ibb_clk_div_table[val] == tmp) + break; - rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_CLK_DIV, - &val, 1); - if (rc) { - pr_err("qpnp_ibb_dt_init write register %x failed rc = %d\n", - REG_IBB_CLK_DIV, rc); - return rc; + if (val == ARRAY_SIZE(ibb_clk_div_table)) { + pr_err("Invalid value in qpnp-ibb-switching-clock-frequency\n"); + return -EINVAL; + } + rc = labibb->ibb_ver_ops->set_clk_div(labibb, val); + if (rc < 0) { + pr_err("qpnp_ibb_dt_init write register %x failed rc = %d\n", + REG_IBB_CLK_DIV, rc); + return rc; + } } + val = 0; + mask = 0; rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-limit-maximum-current", &tmp); + if (!rc) { + for (val = 0; val < ARRAY_SIZE(ibb_current_limit_table); val++) + if (ibb_current_limit_table[val] == tmp) + break; - if (rc) { - pr_err("get qcom,qpnp-ibb-limit-maximum-current failed rc = %d\n", - rc); - return rc; - } - - for (val = 0; val < ARRAY_SIZE(ibb_current_limit_plan); val++) - if (ibb_current_limit_plan[val] == tmp) - break; + if (val == ARRAY_SIZE(ibb_current_limit_table)) { + pr_err("Invalid value in qcom,qpnp-ibb-limit-maximum-current\n"); + return -EINVAL; + } - if (val == ARRAY_SIZE(ibb_current_limit_plan)) { - pr_err("Invalid property in qcom,qpnp-ibb-limit-maximum-current\n"); - return -EINVAL; + mask = IBB_CURRENT_LIMIT_MASK; } - rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-debounce-cycle", - &tmp); - - if (rc) { - pr_err("get qcom,qpnp-ibb-debounce-cycle failed rc = %d\n", - rc); - return rc; - } + rc = of_property_read_u32(of_node, + "qcom,qpnp-ibb-debounce-cycle", &tmp); + if (!rc) { + for (i = 0; i < ARRAY_SIZE(ibb_debounce_table); i++) + if (ibb_debounce_table[i] == tmp) + break; - for (i = 0; i < ARRAY_SIZE(ibb_debounce_plan); i++) - if (ibb_debounce_plan[i] == tmp) - break; + if (i == ARRAY_SIZE(ibb_debounce_table)) { + pr_err("Invalid value in qcom,qpnp-ibb-debounce-cycle\n"); + return -EINVAL; + } - if (i == ARRAY_SIZE(ibb_debounce_plan)) { - pr_err("Invalid property in qcom,qpnp-ibb-debounce-cycle\n"); - return -EINVAL; + val |= (i << IBB_CURRENT_LIMIT_DEBOUNCE_SHIFT); + mask |= IBB_CURRENT_LIMIT_DEBOUNCE_MASK; } - val |= (i << IBB_CURRENT_LIMIT_DEBOUNCE_SHIFT); - if (of_property_read_bool(of_node, - "qcom,qpnp-ibb-limit-max-current-enable")) + "qcom,qpnp-ibb-limit-max-current-enable")) { val |= IBB_CURRENT_LIMIT_EN; + mask |= IBB_CURRENT_LIMIT_EN; + } - rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, - REG_IBB_CURRENT_LIMIT, - &val, - 1); - if (rc) { + rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base, + REG_IBB_CURRENT_LIMIT, mask, val); + if (rc < 0) { pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n", REG_IBB_CURRENT_LIMIT, rc); return rc; @@ -2283,7 +3151,7 @@ static int qpnp_ibb_dt_init(struct qpnp_labibb *labibb, REG_IBB_RING_SUPPRESSION_CTL, &val, 1); - if (rc) { + if (rc < 0) { pr_err("qpnp_ibb_dt_init write register %x failed rc = %d\n", REG_IBB_RING_SUPPRESSION_CTL, rc); return rc; @@ -2292,67 +3160,60 @@ static int qpnp_ibb_dt_init(struct qpnp_labibb *labibb, if (of_property_read_bool(of_node, "qcom,qpnp-ibb-ps-enable")) { rc = qpnp_ibb_ps_config(labibb, true); - if (rc) { + if (rc < 0) { pr_err("qpnp_ibb_dt_init PS enable failed rc=%d\n", rc); return rc; } } else { rc = qpnp_ibb_ps_config(labibb, false); - if (rc) { + if (rc < 0) { pr_err("qpnp_ibb_dt_init PS disable failed rc=%d\n", rc); return rc; } } + if (of_property_read_bool(of_node, + "qcom,qpnp-ibb-smart-ps-enable")){ + of_property_read_u32(of_node, "qcom,qpnp-ibb-num-swire-trans", + &labibb->ibb_vreg.num_swire_trans); + + of_property_read_u32(of_node, + "qcom,qpnp-ibb-neg-curr-limit", &tmp); + + rc = labibb->ibb_ver_ops->smart_ps_config(labibb, true, + labibb->ibb_vreg.num_swire_trans, tmp); + if (rc < 0) { + pr_err("qpnp_ibb_dt_init smart PS enable failed rc=%d\n", + rc); + return rc; + } + + } + rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-init-voltage", &(labibb->ibb_vreg.curr_volt)); - if (rc) { + if (rc < 0) { pr_err("get qcom,qpnp-ibb-init-voltage failed, rc = %d\n", rc); return rc; } - if (!of_property_read_bool(of_node, - "qcom,qpnp-ibb-use-default-voltage")) { - if (labibb->ibb_vreg.curr_volt < labibb->ibb_vreg.min_volt) { - pr_err("Invalid qcom,qpnp-ibb-init-voltage property, qcom,qpnp-ibb-init-voltage %d is less than the the minimum voltage %d", - labibb->ibb_vreg.curr_volt, - labibb->ibb_vreg.min_volt); - return -EINVAL; - } - - val = DIV_ROUND_UP(labibb->ibb_vreg.curr_volt - - labibb->ibb_vreg.min_volt, - labibb->ibb_vreg.step_size); + if (of_property_read_bool(of_node, + "qcom,qpnp-ibb-use-default-voltage")) + rc = labibb->ibb_ver_ops->set_default_voltage(labibb, true); + else + rc = labibb->ibb_ver_ops->set_default_voltage(labibb, false); - if (val > IBB_VOLTAGE_SET_MASK) { - pr_err("Invalid qcom,qpnp-ibb-init-voltage property, qcom,qpnp-lab-init-voltage %d is larger than the max supported voltage %d", - labibb->ibb_vreg.curr_volt, - labibb->ibb_vreg.min_volt + - labibb->ibb_vreg.step_size * - IBB_VOLTAGE_SET_MASK); - return -EINVAL; - } + if (rc < 0) + return rc; - labibb->ibb_vreg.curr_volt = val * labibb->ibb_vreg.step_size + - labibb->ibb_vreg.min_volt; - val |= IBB_VOLTAGE_OVERRIDE_EN; - } else { - val = 0; + if (of_property_read_bool(of_node, "qcom,qpnp-ibb-overload-blank")) { + rc = qpnp_ibb_vreg_ok_ctl(labibb, of_node); + if (rc < 0) + return rc; } - rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + - REG_IBB_VOLTAGE, - IBB_VOLTAGE_SET_MASK | - IBB_VOLTAGE_OVERRIDE_EN, - val); - - if (rc) - pr_err("qpnp_ibb_masked_write write register %x failed rc = %d\n", - REG_IBB_VOLTAGE, rc); - - - return rc; + return 0; } static int qpnp_ibb_regulator_enable(struct regulator_dev *rdev) @@ -2367,7 +3228,7 @@ static int qpnp_ibb_regulator_enable(struct regulator_dev *rdev) return qpnp_labibb_regulator_enable(labibb); rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_EN); - if (rc) { + if (rc < 0) { pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc); return rc; } @@ -2377,9 +3238,9 @@ static int qpnp_ibb_regulator_enable(struct regulator_dev *rdev) /* Wait for a small period before reading IBB_STATUS1 */ usleep_range(delay, delay + 100); - rc = qpnp_labibb_read(labibb, &val, - labibb->ibb_base + REG_IBB_STATUS1, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->ibb_base + + REG_IBB_STATUS1, &val, 1); + if (rc < 0) { pr_err("qpnp_ibb_regulator_enable read register %x failed rc = %d\n", REG_IBB_STATUS1, rc); return rc; @@ -2410,7 +3271,7 @@ static int qpnp_ibb_regulator_disable(struct regulator_dev *rdev) return qpnp_labibb_regulator_disable(labibb); rc = qpnp_ibb_set_mode(labibb, IBB_SW_CONTROL_DIS); - if (rc) { + if (rc < 0) { pr_err("Unable to set IBB_MODULE_EN rc = %d\n", rc); return rc; } @@ -2433,51 +3294,18 @@ static int qpnp_ibb_regulator_is_enabled(struct regulator_dev *rdev) static int qpnp_ibb_regulator_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV, unsigned *selector) { - int rc, new_uV; - u8 val; + int rc = 0; + struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); if (labibb->swire_control) return 0; - if (min_uV < labibb->ibb_vreg.min_volt) { - pr_err("min_uV %d is less than min_volt %d", min_uV, - labibb->ibb_vreg.min_volt); - return -EINVAL; - } - - val = DIV_ROUND_UP(min_uV - labibb->ibb_vreg.min_volt, - labibb->ibb_vreg.step_size); - new_uV = val * labibb->ibb_vreg.step_size + labibb->ibb_vreg.min_volt; - - if (new_uV > max_uV) { - pr_err("unable to set voltage %d (min:%d max:%d)\n", new_uV, - min_uV, max_uV); - return -EINVAL; - } - - rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + - REG_IBB_VOLTAGE, - IBB_VOLTAGE_SET_MASK | - IBB_VOLTAGE_OVERRIDE_EN, - val | IBB_VOLTAGE_OVERRIDE_EN); - - if (rc) { - pr_err("write to register %x failed rc = %d\n", REG_IBB_VOLTAGE, - rc); - return rc; - } - - if (new_uV > labibb->ibb_vreg.curr_volt) { - val = DIV_ROUND_UP(new_uV - labibb->ibb_vreg.curr_volt, - labibb->ibb_vreg.step_size); - udelay(val * labibb->ibb_vreg.slew_rate); - } - labibb->ibb_vreg.curr_volt = new_uV; - - return 0; + rc = labibb->ibb_ver_ops->set_voltage(labibb, min_uV, max_uV); + return rc; } + static int qpnp_ibb_regulator_get_voltage(struct regulator_dev *rdev) { struct qpnp_labibb *labibb = rdev_get_drvdata(rdev); @@ -2534,50 +3362,11 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-slew-rate", &(labibb->ibb_vreg.slew_rate)); - if (rc < 0) { - pr_err("qcom,qpnp-ibb-slew-rate is missing, rc = %d\n", - rc); - return rc; - } + if (rc < 0) + labibb->ibb_vreg.slew_rate = IBB_HW_DEFAULT_SLEW_RATE; - rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-soft-start", - &(labibb->ibb_vreg.soft_start)); + rc = labibb->ibb_ver_ops->soft_start_ctl(labibb, of_node); if (rc < 0) { - pr_err("qcom,qpnp-ibb-soft-start is missing, rc = %d\n", - rc); - return rc; - } - - rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-discharge-resistor", - &tmp); - - if (rc < 0) { - pr_err("qcom,qpnp-ibb-discharge-resistor is missing, rc = %d\n", - rc); - return rc; - } - - if (labibb->mode == QPNP_LABIBB_AMOLED_MODE) { - /* - * AMOLED mode needs ibb discharge resistor to be - * configured for 300KOhm - */ - if (tmp < ibb_discharge_resistor_plan[0]) - tmp = ibb_discharge_resistor_plan[0]; - } - - for (val = 0; val < ARRAY_SIZE(ibb_discharge_resistor_plan); val++) - if (ibb_discharge_resistor_plan[val] == tmp) - break; - - if (val == ARRAY_SIZE(ibb_discharge_resistor_plan)) { - pr_err("Invalid property in qcom,qpnp-ibb-discharge-resistor\n"); - return -EINVAL; - } - - rc = qpnp_labibb_write(labibb, labibb->ibb_base + - REG_IBB_SOFT_START_CTL, &val, 1); - if (rc) { pr_err("qpnp_labibb_write register %x failed rc = %d\n", REG_IBB_SOFT_START_CTL, rc); return rc; @@ -2585,42 +3374,29 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, if (of_find_property(of_node, "qcom,output-voltage-one-pulse", NULL)) { if (!labibb->swire_control) { - pr_err("Invalid property 'qcom,output-voltage-one-pulse', valid only in SWIRE config\n"); + pr_err("output-voltage-one-pulse valid for SWIRE only\n"); return -EINVAL; } rc = of_property_read_u32(of_node, "qcom,output-voltage-one-pulse", &tmp); - if (rc) { + if (rc < 0) { pr_err("failed to read qcom,output-voltage-one-pulse rc=%d\n", rc); return rc; } if (tmp > MAX_OUTPUT_PULSE_VOLTAGE_MV || - tmp < MIN_OUTPUT_PULSE_VOLTAGE_MV) { + tmp < MIN_OUTPUT_PULSE_VOLTAGE_MV) { pr_err("Invalid one-pulse voltage range %d\n", tmp); return -EINVAL; } - - /* - * Set the output voltage 100mV lower as the IBB HW module - * counts one pulse less in SWIRE mode. - */ - val = DIV_ROUND_UP((tmp - MIN_OUTPUT_PULSE_VOLTAGE_MV), - OUTPUT_VOLTAGE_STEP_MV) - 1; - rc = qpnp_labibb_masked_write(labibb, labibb->ibb_base + - REG_IBB_SWIRE_CTL, - IBB_OUTPUT_VOLTAGE_AT_ONE_PULSE_MASK, - val); - if (rc) { - pr_err("qpnp_labiibb_write register %x failed rc = %d\n", - REG_IBB_SWIRE_CTL, rc); + rc = labibb->ibb_ver_ops->voltage_at_one_pulse(labibb, tmp); + if (rc < 0) return rc; - } } - rc = qpnp_labibb_read(labibb, &ibb_enable_ctl, - labibb->ibb_base + REG_IBB_ENABLE_CTL, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_ENABLE_CTL, + &ibb_enable_ctl, 1); + if (rc < 0) { pr_err("qpnp_ibb_read register %x failed rc = %d\n", REG_IBB_ENABLE_CTL, rc); return rc; @@ -2635,47 +3411,40 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, if (ibb_enable_ctl & (IBB_ENABLE_CTL_SWIRE_RDY | IBB_ENABLE_CTL_MODULE_EN)) { - /* SWIRE_RDY or IBB_MODULE_EN enabled */ - rc = qpnp_labibb_read(labibb, &val, - labibb->ibb_base + REG_IBB_LCD_AMOLED_SEL, 1); - if (rc) { + + rc = labibb->ibb_ver_ops->get_mode(labibb); + if (rc < 0) { pr_err("qpnp_labibb_read register %x failed rc = %d\n", REG_IBB_LCD_AMOLED_SEL, rc); return rc; } - - if (val == REG_LAB_IBB_AMOLED_MODE) - labibb->mode = QPNP_LABIBB_AMOLED_MODE; - else - labibb->mode = QPNP_LABIBB_LCD_MODE; - - rc = qpnp_labibb_read(labibb, &val, - labibb->ibb_base + REG_IBB_VOLTAGE, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->ibb_base + + REG_IBB_VOLTAGE, &val, 1); + if (rc < 0) { pr_err("qpnp_labibb_read read register %x failed rc = %d\n", REG_IBB_VOLTAGE, rc); return rc; } - if (val & IBB_VOLTAGE_OVERRIDE_EN) { - labibb->ibb_vreg.curr_volt = - (val & IBB_VOLTAGE_SET_MASK) * - labibb->ibb_vreg.step_size + - labibb->ibb_vreg.min_volt; - } else if (labibb->mode == QPNP_LABIBB_LCD_MODE) { + labibb->ibb_vreg.curr_volt = + (val & IBB_VOLTAGE_SET_MASK) * + labibb->ibb_vreg.step_size + + labibb->ibb_vreg.min_volt; + + if (labibb->mode == QPNP_LABIBB_LCD_MODE) { rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-init-lcd-voltage", &(labibb->ibb_vreg.curr_volt)); - if (rc) { + if (rc < 0) { pr_err("get qcom,qpnp-ibb-init-lcd-voltage failed, rc = %d\n", rc); return rc; } - } else { + } else if (!(val & IBB_VOLTAGE_OVERRIDE_EN)) { rc = of_property_read_u32(of_node, "qcom,qpnp-ibb-init-amoled-voltage", &(labibb->ibb_vreg.curr_volt)); - if (rc) { + if (rc < 0) { pr_err("get qcom,qpnp-ibb-init-amoled-voltage failed, rc = %d\n", rc); return rc; @@ -2683,40 +3452,41 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, } - rc = qpnp_labibb_read(labibb, &val, labibb->ibb_base + - REG_IBB_PWRUP_PWRDN_CTL_1, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->ibb_base + + REG_IBB_PWRUP_PWRDN_CTL_1, &val, 1); + if (rc < 0) { pr_err("qpnp_labibb_config_init read register %x failed rc = %d\n", REG_IBB_PWRUP_PWRDN_CTL_1, rc); return rc; } - labibb->ibb_vreg.pwrup_dly = ibb_pwrup_dly_plan[ - (val >> - IBB_PWRUP_PWRDN_CTL_1_DLY1_SHIFT) & - IBB_PWRUP_PWRDN_CTL_1_DLY1_MASK]; - labibb->ibb_vreg.pwrdn_dly = ibb_pwrdn_dly_plan[val & + labibb->ibb_vreg.pwrup_dly = ibb_pwrup_dly_table[ + (val & + IBB_PWRUP_PWRDN_CTL_1_DLY1_MASK)]; + labibb->ibb_vreg.pwrdn_dly = ibb_pwrdn_dly_table[val & IBB_PWRUP_PWRDN_CTL_1_DLY2_MASK]; labibb->ibb_vreg.vreg_enabled = 1; } else { /* SWIRE_RDY and IBB_MODULE_EN not enabled */ rc = qpnp_ibb_dt_init(labibb, of_node); - if (rc) { + if (rc < 0) { pr_err("qpnp-ibb: wrong DT parameter specified: rc = %d\n", rc); return rc; } } - if (labibb->mode == QPNP_LABIBB_AMOLED_MODE) { + if (labibb->mode == QPNP_LABIBB_AMOLED_MODE && + qpnp_ibb_poff_ctl_required(labibb)) { + val = IBB_OVERRIDE_NONOVERLAP | IBB_NFET_GATE_DELAY_2; rc = qpnp_labibb_sec_masked_write(labibb, labibb->ibb_base, REG_IBB_NONOVERLAP_TIME_1, IBB_OVERRIDE_NONOVERLAP | IBB_NONOVERLAP_NFET_MASK, val); - if (rc) { + if (rc < 0) { pr_err("qpnp_labibb_sec_masked_write register %x failed rc = %d\n", REG_IBB_NONOVERLAP_TIME_1, rc); return rc; @@ -2724,9 +3494,9 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, val = IBB_N2P_MUX_SEL; rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, - REG_IBB_NONOVERLAP_TIME_2, &val, 1); + REG_IBB_NONOVERLAP_TIME_2, val); - if (rc) { + if (rc < 0) { pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n", REG_IBB_NONOVERLAP_TIME_2, rc); return rc; @@ -2734,11 +3504,11 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, val = IBB_FASTER_PFET_OFF; rc = qpnp_labibb_masked_write(labibb, - labibb->ibb_base + REG_IBB_SPARE_CTL, - IBB_POFF_CTL_MASK, val); - if (rc) { - pr_err("qpnp_labibb_masked_write %x failed rc = %d\n", - REG_IBB_SPARE_CTL, rc); + labibb->ibb_base + REG_IBB_SPARE_CTL, + IBB_POFF_CTL_MASK, val); + if (rc < 0) { + pr_err("write to register %x failed rc = %d\n", + REG_IBB_SPARE_CTL, rc); return rc; } } @@ -2746,8 +3516,8 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, if (labibb->standalone) { val = 0; rc = qpnp_labibb_sec_write(labibb, labibb->ibb_base, - REG_IBB_PWRUP_PWRDN_CTL_1, &val, 1); - if (rc) { + REG_IBB_PWRUP_PWRDN_CTL_1, val); + if (rc < 0) { pr_err("qpnp_labibb_sec_write register %x failed rc = %d\n", REG_IBB_PWRUP_PWRDN_CTL_1, rc); return rc; @@ -2756,9 +3526,9 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, labibb->ibb_vreg.pwrdn_dly = 0; } - rc = qpnp_labibb_read(labibb, &val, - labibb->ibb_base + REG_IBB_MODULE_RDY, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->ibb_base + REG_IBB_MODULE_RDY, + &val, 1); + if (rc < 0) { pr_err("qpnp_ibb_read read register %x failed rc = %d\n", REG_IBB_MODULE_RDY, rc); return rc; @@ -2770,13 +3540,26 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, rc = qpnp_labibb_write(labibb, labibb->ibb_base + REG_IBB_MODULE_RDY, &val, 1); - if (rc) { + if (rc < 0) { pr_err("qpnp_ibb_dt_init write register %x failed rc = %d\n", REG_IBB_MODULE_RDY, rc); return rc; } } + if (of_property_read_bool(of_node, + "qcom,qpnp-ibb-enable-pfm-mode")) { + rc = qpnp_ibb_pfm_mode_enable(labibb, of_node); + if (rc < 0) + return rc; + } + + if (labibb->pbs_control) { + rc = qpnp_labibb_pbs_mode_enable(labibb, of_node); + if (rc < 0) + return rc; + } + if (init_data->constraints.name) { rdesc->owner = THIS_MODULE; rdesc->type = REGULATOR_VOLTAGE; @@ -2835,9 +3618,9 @@ static int qpnp_labibb_check_ttw_supported(struct qpnp_labibb *labibb) switch (labibb->pmic_rev_id->pmic_subtype) { case PMI8996_SUBTYPE: - rc = qpnp_labibb_read(labibb, &val, - labibb->ibb_base + REG_IBB_REVISION4, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, labibb->ibb_base + + REG_IBB_REVISION4, &val, 1); + if (rc < 0) { pr_err("qpnp_labibb_read register %x failed rc = %d\n", REG_IBB_REVISION4, rc); return rc; @@ -2891,6 +3674,7 @@ static int qpnp_labibb_regulator_probe(struct platform_device *pdev) mutex_init(&(labibb->lab_vreg.lab_mutex)); mutex_init(&(labibb->ibb_vreg.ibb_mutex)); + mutex_init(&(labibb->bus_mutex)); revid_dev_node = of_parse_phandle(labibb->dev->of_node, "qcom,pmic-revid", 0); @@ -2905,21 +3689,33 @@ static int qpnp_labibb_regulator_probe(struct platform_device *pdev) return -EPROBE_DEFER; } - rc = of_property_read_string(labibb->dev->of_node, - "qcom,qpnp-labibb-mode", &mode_name); - if (!rc) { - if (strcmp("lcd", mode_name) == 0) { - labibb->mode = QPNP_LABIBB_LCD_MODE; - } else if (strcmp("amoled", mode_name) == 0) { - labibb->mode = QPNP_LABIBB_AMOLED_MODE; + if (labibb->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { + labibb->ibb_ver_ops = &ibb_ops_v2; + labibb->lab_ver_ops = &lab_ops_v2; + } else { + labibb->ibb_ver_ops = &ibb_ops_v1; + labibb->lab_ver_ops = &lab_ops_v1; + } + + if (labibb->pmic_rev_id->pmic_subtype == PM660L_SUBTYPE) { + labibb->mode = QPNP_LABIBB_AMOLED_MODE; + } else { + rc = of_property_read_string(labibb->dev->of_node, + "qcom,qpnp-labibb-mode", &mode_name); + if (!rc) { + if (strcmp("lcd", mode_name) == 0) { + labibb->mode = QPNP_LABIBB_LCD_MODE; + } else if (strcmp("amoled", mode_name) == 0) { + labibb->mode = QPNP_LABIBB_AMOLED_MODE; + } else { + pr_err("Invalid device property in qcom,qpnp-labibb-mode: %s\n", + mode_name); + return -EINVAL; + } } else { - pr_err("Invalid device property in qcom,qpnp-labibb-mode: %s\n", - mode_name); - return -EINVAL; + pr_err("qpnp_labibb: qcom,qpnp-labibb-mode is missing.\n"); + return rc; } - } else { - pr_err("qpnp_labibb: qcom,qpnp-labibb-mode is missing.\n"); - return rc; } labibb->standalone = of_property_read_bool(labibb->dev->of_node, @@ -2937,6 +3733,9 @@ static int qpnp_labibb_regulator_probe(struct platform_device *pdev) labibb->swire_control = of_property_read_bool(labibb->dev->of_node, "qcom,swire-control"); + + labibb->pbs_control = of_property_read_bool(labibb->dev->of_node, + "qcom,pbs-control"); if (labibb->swire_control && labibb->mode != QPNP_LABIBB_AMOLED_MODE) { pr_err("Invalid mode for SWIRE control\n"); return -EINVAL; @@ -2950,14 +3749,14 @@ static int qpnp_labibb_regulator_probe(struct platform_device *pdev) rc = of_property_read_u32(labibb->dev->of_node, "qcom,swire-2nd-cmd-delay", &labibb->swire_2nd_cmd_delay); - if (rc) + if (rc < 0) labibb->swire_2nd_cmd_delay = SWIRE_DEFAULT_2ND_CMD_DLY_MS; rc = of_property_read_u32(labibb->dev->of_node, "qcom,swire-ibb-ps-enable-delay", &labibb->swire_ibb_ps_enable_delay); - if (rc) + if (rc < 0) labibb->swire_ibb_ps_enable_delay = SWIRE_DEFAULT_IBB_PS_ENABLE_DLY_MS; } @@ -2976,16 +3775,16 @@ static int qpnp_labibb_regulator_probe(struct platform_device *pdev) return rc; } - rc = qpnp_labibb_read(labibb, &revision, base + REG_REVISION_2, - 1); - if (rc) { + rc = qpnp_labibb_read(labibb, base + REG_REVISION_2, + &revision, 1); + if (rc < 0) { pr_err("Reading REVISION_2 failed rc=%d\n", rc); goto fail_registration; } - rc = qpnp_labibb_read(labibb, &type, - base + REG_PERPH_TYPE, 1); - if (rc) { + rc = qpnp_labibb_read(labibb, base + REG_PERPH_TYPE, + &type, 1); + if (rc < 0) { pr_err("Peripheral type read failed rc=%d\n", rc); goto fail_registration; } @@ -3001,7 +3800,7 @@ static int qpnp_labibb_regulator_probe(struct platform_device *pdev) goto fail_registration; } rc = register_qpnp_lab_regulator(labibb, child); - if (rc) + if (rc < 0) goto fail_registration; break; @@ -3009,7 +3808,7 @@ static int qpnp_labibb_regulator_probe(struct platform_device *pdev) labibb->ibb_base = base; labibb->ibb_dig_major = revision; rc = register_qpnp_ibb_regulator(labibb, child); - if (rc) + if (rc < 0) goto fail_registration; break; @@ -3023,13 +3822,16 @@ static int qpnp_labibb_regulator_probe(struct platform_device *pdev) if (labibb->ttw_en) { rc = qpnp_labibb_check_ttw_supported(labibb); - if (rc) { + if (rc < 0) { pr_err("pmic revision check failed for TTW rc=%d\n", rc); goto fail_registration; } } dev_set_drvdata(&pdev->dev, labibb); + pr_info("LAB/IBB registered successfully, lab_vreg enable=%d ibb_vreg enable=%d\n", + labibb->lab_vreg.vreg_enabled, + labibb->ibb_vreg.vreg_enabled); return 0; diff --git a/drivers/regulator/qpnp-oledb-regulator.c b/drivers/regulator/qpnp-oledb-regulator.c new file mode 100644 index 000000000000..dd52b74b11b6 --- /dev/null +++ b/drivers/regulator/qpnp-oledb-regulator.c @@ -0,0 +1,1193 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) "OLEDB: %s: " fmt, __func__ + +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/regmap.h> +#include <linux/spmi.h> +#include <linux/platform_device.h> +#include <linux/regulator/driver.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/of_regulator.h> + +#define QPNP_OLEDB_REGULATOR_DRIVER_NAME "qcom,qpnp-oledb-regulator" +#define OLEDB_VOUT_STEP_MV 100 +#define OLEDB_VOUT_MIN_MV 5000 +#define OLEDB_VOUT_MAX_MV 8100 +#define OLEDB_VOUT_HW_DEFAULT 6400 + +#define OLEDB_MODULE_RDY 0x45 +#define OLEDB_MODULE_RDY_BIT BIT(7) + +#define OLEDB_MODULE_ENABLE 0x46 +#define OLEDB_MODULE_ENABLE_BIT BIT(7) + +#define OLEDB_EXT_PIN_CTL 0x47 +#define OLEDB_EXT_PIN_CTL_BIT BIT(7) + +#define OLEDB_SWIRE_CONTROL 0x48 +#define OLEDB_EN_SWIRE_VOUT_UPD_BIT BIT(6) +#define OLEDB_EN_SWIRE_PD_UPD_BIT BIT(7) + +#define OLEDB_VOUT_PGM 0x49 +#define OLEDB_VOUT_PGM_MASK GENMASK(4, 0) + +#define OLEDB_VOUT_DEFAULT 0x4A +#define OLEDB_VOUT_DEFAULT_MASK GENMASK(4, 0) + +#define OLEDB_PD_CTL 0x4B + +#define OLEDB_ILIM_NFET 0x4E +#define OLEDB_ILIMIT_NFET_MASK GENMASK(2, 0) + +#define OLEDB_BIAS_GEN_WARMUP_DELAY 0x52 +#define OLEDB_BIAS_GEN_WARMUP_DELAY_MASK GENMASK(1, 0) + +#define OLEDB_SHORT_PROTECT 0x59 +#define OLEDB_ENABLE_SC_DETECTION_BIT BIT(7) +#define OLEDB_DBNC_SHORT_DETECTION_MASK GENMASK(1, 0) + +#define OLEDB_FAST_PRECHARGE 0x5A +#define OLEDB_FAST_PRECHG_PPULSE_EN_BIT BIT(7) +#define OLEDB_DBNC_PRECHARGE_MASK GENMASK(5, 4) +#define OLEDB_DBNC_PRECHARGE_SHIFT 4 +#define OLEDB_PRECHARGE_PULSE_PERIOD_MASK GENMASK(3, 2) +#define OLEDB_PRECHARGE_PULSE_PERIOD_SHIFT 2 +#define OLEDB_PRECHARGE_PULSE_TON_MASK GENMASK(1, 0) + +#define OLEDB_EN_PSM 0x5B +#define OLEDB_PSM_ENABLE_BIT BIT(7) + +#define OLEDB_PSM_CTL 0x5C +#define OLEDB_PSM_HYSTERYSIS_CTL_BIT BIT(3) +#define OLEDB_PSM_HYSTERYSIS_CTL_BIT_SHIFT 3 +#define OLEDB_VREF_PSM_MASK GENMASK(2, 0) + +#define OLEDB_PFM_CTL 0x5D +#define OLEDB_PFM_ENABLE_BIT BIT(7) +#define OLEDB_PFM_HYSTERYSIS_CTRL_BIT_MASK BIT(4) +#define OLEDB_PFM_HYSTERYSIS_CTL_BIT_SHIFT 4 +#define OLEDB_PFM_CURR_LIMIT_MASK GENMASK(3, 2) +#define OLEDB_PFM_CURR_LIMIT_SHIFT 2 +#define OLEDB_PFM_OFF_TIME_NS_MASK GENMASK(1, 0) + +#define OLEDB_NLIMIT 0x64 +#define OLEDB_ENABLE_NLIMIT_BIT BIT(7) +#define OLEDB_ENABLE_NLIMIT_BIT_SHIFT 7 +#define OLEDB_NLIMIT_PGM_MASK GENMASK(1, 0) + +#define OLEDB_PSM_HYS_CTRL_MIN 13 +#define OLEDB_PSM_HYS_CTRL_MAX 26 + +#define OLEDB_PFM_HYS_CTRL_MIN 13 +#define OLEDB_PFM_HYS_CTRL_MAX 26 + +#define OLEDB_PFM_OFF_TIME_MIN 110 +#define OLEDB_PFM_OFF_TIME_MAX 480 + +#define OLEDB_PRECHG_TIME_MIN 1 +#define OLEDB_PRECHG_TIME_MAX 8 + +#define OLEDB_PRECHG_PULSE_PERIOD_MIN 3 +#define OLEDB_PRECHG_PULSE_PERIOD_MAX 12 + +#define OLEDB_MIN_SC_DBNC_TIME_FSW 2 +#define OLEDB_MAX_SC_DBNC_TIME_FSW 16 + +#define OLEDB_PRECHG_PULSE_ON_TIME_MIN 1200 +#define OLEDB_PRECHG_PULSE_ON_TIME_MAX 3000 + +#define PSM_HYSTERYSIS_MV_TO_VAL(val_mv) ((val_mv/13) - 1) +#define PFM_HYSTERYSIS_MV_TO_VAL(val_mv) ((val_mv/13) - 1) +#define PFM_OFF_TIME_NS_TO_VAL(val_ns) ((val_ns/110) - 1) +#define PRECHG_DEBOUNCE_TIME_MS_TO_VAL(val_ms) ((val_ms/2) - \ + (val_ms/8)) +#define PRECHG_PULSE_PERIOD_US_TO_VAL(val_us) ((val_us/3) - 1) +#define PRECHG_PULSE_ON_TIME_NS_TO_VAL(val_ns) (val_ns/600 - 2) +#define SHORT_CIRCUIT_DEBOUNCE_TIME_TO_VAL(val) ((val/4) - (val/16)) + +struct qpnp_oledb_psm_ctl { + int psm_enable; + int psm_hys_ctl; + int psm_vref; +}; + +struct qpnp_oledb_pfm_ctl { + int pfm_enable; + int pfm_hys_ctl; + int pfm_curr_limit; + int pfm_off_time; +}; + +struct qpnp_oledb_fast_precharge_ctl { + int fast_prechg_ppulse_en; + int prechg_debounce_time; + int prechg_pulse_period; + int prechg_pulse_on_time; +}; + +struct qpnp_oledb { + struct platform_device *pdev; + struct device *dev; + struct regmap *regmap; + struct regulator_desc rdesc; + struct regulator_dev *rdev; + struct qpnp_oledb_psm_ctl psm_ctl; + struct qpnp_oledb_pfm_ctl pfm_ctl; + struct qpnp_oledb_fast_precharge_ctl fast_prechg_ctl; + + u32 base; + int current_voltage; + int default_voltage; + int vout_mv; + int warmup_delay; + int peak_curr_limit; + int pd_ctl; + int negative_curr_limit; + int nlimit_enable; + int sc_en; + int sc_dbnc_time; + bool mod_enable; + bool swire_control; + bool ext_pin_control; + bool ext_pinctl_state; + bool dynamic_ext_pinctl_config; + bool pbs_control; +}; + +static const u16 oledb_warmup_dly_ns[] = {6700, 13300, 26700, 53400}; +static const u16 oledb_peak_curr_limit_ma[] = {115, 265, 415, 570, + 720, 870, 1020, 1170}; +static const u16 oledb_psm_vref_mv[] = {440, 510, 580, 650, 715, + 780, 850, 920}; +static const u16 oledb_pfm_curr_limit_ma[] = {130, 200, 270, 340}; +static const u16 oledb_nlimit_ma[] = {170, 300, 420, 550}; + +static int qpnp_oledb_read(struct qpnp_oledb *oledb, u32 address, + u8 *val, int count) +{ + int rc = 0; + struct platform_device *pdev = oledb->pdev; + + rc = regmap_bulk_read(oledb->regmap, address, val, count); + if (rc) + pr_err("Failed to read address=0x%02x sid=0x%02x rc=%d\n", + address, to_spmi_device(pdev->dev.parent)->usid, rc); + + return rc; +} + +static int qpnp_oledb_masked_write(struct qpnp_oledb *oledb, + u32 address, u8 mask, u8 val) +{ + int rc; + + rc = regmap_update_bits(oledb->regmap, address, mask, val); + if (rc < 0) + pr_err("Failed to write address 0x%04X, rc = %d\n", + address, rc); + else + pr_debug("Wrote 0x%02X to addr 0x%04X\n", + val, address); + + return rc; +} + +static int qpnp_oledb_write(struct qpnp_oledb *oledb, u16 address, u8 *val, + int count) +{ + int rc = 0; + struct platform_device *pdev = oledb->pdev; + + rc = regmap_bulk_write(oledb->regmap, address, val, count); + if (rc) + pr_err("Failed to write address=0x%02x sid=0x%02x rc=%d\n", + address, to_spmi_device(pdev->dev.parent)->usid, rc); + else + pr_debug("Wrote 0x%02X to addr 0x%04X\n", + *val, address); + + return 0; +} + +static int qpnp_oledb_regulator_enable(struct regulator_dev *rdev) +{ + int rc = 0; + u8 val = 0; + + struct qpnp_oledb *oledb = rdev_get_drvdata(rdev); + + if (oledb->ext_pin_control) { + rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_EXT_PIN_CTL, + &val, 1); + if (rc < 0) { + pr_err("Failed to read EXT_PIN_CTL rc=%d\n", rc); + return rc; + } + + /* + * Enable ext-pin-ctl after display-supply is turned on. + * This is to avoid glitches on the external pin. + */ + if (!(val & OLEDB_EXT_PIN_CTL_BIT) && + oledb->dynamic_ext_pinctl_config) { + val = OLEDB_EXT_PIN_CTL_BIT; + rc = qpnp_oledb_write(oledb, oledb->base + + OLEDB_EXT_PIN_CTL, &val, 1); + if (rc < 0) { + pr_err("Failed to write EXT_PIN_CTL rc=%d\n", + rc); + return rc; + } + } + pr_debug("ext-pin-ctrl mode enabled\n"); + } else { + val = OLEDB_MODULE_ENABLE_BIT; + rc = qpnp_oledb_write(oledb, oledb->base + OLEDB_MODULE_ENABLE, + &val, 1); + if (rc < 0) { + pr_err("Failed to write MODULE_ENABLE rc=%d\n", rc); + return rc; + } + + ndelay(oledb->warmup_delay); + pr_debug("register-control mode, module enabled\n"); + } + + oledb->mod_enable = true; + if (oledb->pbs_control) { + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_SWIRE_CONTROL, OLEDB_EN_SWIRE_PD_UPD_BIT | + OLEDB_EN_SWIRE_VOUT_UPD_BIT, 0); + if (rc < 0) + pr_err("Failed to write SWIRE_CTL for pbs mode rc=%d\n", + rc); + } + + return rc; +} + +static int qpnp_oledb_regulator_disable(struct regulator_dev *rdev) +{ + int rc = 0; + + struct qpnp_oledb *oledb = rdev_get_drvdata(rdev); + + /* + * Disable ext-pin-ctl after display-supply is turned off. This is to + * avoid glitches on the external pin. + */ + if (oledb->ext_pin_control && oledb->dynamic_ext_pinctl_config) { + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_EXT_PIN_CTL, OLEDB_EXT_PIN_CTL_BIT, 0); + if (rc < 0) { + pr_err("Failed to write EXT_PIN_CTL rc=%d\n", rc); + return rc; + } + pr_debug("ext-pin-ctrl mode disabled\n"); + } else { + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_MODULE_ENABLE, + OLEDB_MODULE_ENABLE_BIT, 0); + if (rc < 0) { + pr_err("Failed to write MODULE_ENABLE rc=%d\n", rc); + return rc; + } + pr_debug("Register-control mode, module disabled\n"); + } + + oledb->mod_enable = false; + + return rc; +} + +static int qpnp_oledb_regulator_is_enabled(struct regulator_dev *rdev) +{ + struct qpnp_oledb *oledb = rdev_get_drvdata(rdev); + + return oledb->mod_enable; +} + +static int qpnp_oledb_regulator_set_voltage(struct regulator_dev *rdev, + int min_uV, int max_uV, unsigned *selector) +{ + u8 val; + int rc = 0; + + struct qpnp_oledb *oledb = rdev_get_drvdata(rdev); + + if (oledb->swire_control) + return 0; + + val = DIV_ROUND_UP(min_uV - OLEDB_VOUT_MIN_MV, OLEDB_VOUT_STEP_MV); + + rc = qpnp_oledb_write(oledb, oledb->base + OLEDB_VOUT_PGM, + &val, 1); + if (rc < 0) { + pr_err("Failed to write VOUT_PGM rc=%d\n", rc); + return rc; + } + + oledb->current_voltage = min_uV; + pr_debug("register-control mode, current voltage %d\n", + oledb->current_voltage); + + return 0; +} + +static int qpnp_oledb_regulator_get_voltage(struct regulator_dev *rdev) +{ + struct qpnp_oledb *oledb = rdev_get_drvdata(rdev); + + if (oledb->swire_control) + return 0; + + return oledb->current_voltage; +} + +static struct regulator_ops qpnp_oledb_ops = { + .enable = qpnp_oledb_regulator_enable, + .disable = qpnp_oledb_regulator_disable, + .is_enabled = qpnp_oledb_regulator_is_enabled, + .set_voltage = qpnp_oledb_regulator_set_voltage, + .get_voltage = qpnp_oledb_regulator_get_voltage, +}; + +static int qpnp_oledb_register_regulator(struct qpnp_oledb *oledb) +{ + int rc = 0; + struct platform_device *pdev = oledb->pdev; + struct regulator_init_data *init_data; + struct regulator_desc *rdesc = &oledb->rdesc; + struct regulator_config cfg = {}; + + init_data = of_get_regulator_init_data(&pdev->dev, + pdev->dev.of_node, rdesc); + if (!init_data) { + pr_err("Unable to get OLEDB regulator init data\n"); + return -ENOMEM; + } + + if (init_data->constraints.name) { + rdesc->owner = THIS_MODULE; + rdesc->type = REGULATOR_VOLTAGE; + rdesc->ops = &qpnp_oledb_ops; + rdesc->name = init_data->constraints.name; + + cfg.dev = &pdev->dev; + cfg.init_data = init_data; + cfg.driver_data = oledb; + cfg.of_node = pdev->dev.of_node; + + if (of_get_property(pdev->dev.of_node, "parent-supply", + NULL)) + init_data->supply_regulator = "parent"; + + init_data->constraints.valid_ops_mask + |= REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS; + + oledb->rdev = devm_regulator_register(oledb->dev, rdesc, &cfg); + if (IS_ERR(oledb->rdev)) { + rc = PTR_ERR(oledb->rdev); + oledb->rdev = NULL; + pr_err("Unable to register OLEDB regulator, rc = %d\n", + rc); + return rc; + } + } else { + pr_err("OLEDB regulator name missing\n"); + return -EINVAL; + } + + return 0; +} + +static int qpnp_oledb_get_curr_voltage(struct qpnp_oledb *oledb, + u16 *current_voltage) +{ + int rc = 0; + u8 val; + + if (!(oledb->mod_enable || oledb->ext_pinctl_state)) { + rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_VOUT_DEFAULT, + &val, 1); + if (rc < 0) { + pr_err("Failed to read VOUT_DEFAULT rc=%d\n", rc); + return rc; + } + } else { + rc = qpnp_oledb_read(oledb, oledb->base + + OLEDB_VOUT_PGM, &val, 1); + if (rc < 0) { + pr_err("Failed to read VOUT_PGM rc=%d\n", rc); + return rc; + } + } + + *current_voltage = (val * OLEDB_VOUT_STEP_MV) + OLEDB_VOUT_MIN_MV; + + return rc; +} + +static int qpnp_oledb_init_nlimit(struct qpnp_oledb *oledb) +{ + int rc = 0, i = 0; + u32 val, mask = 0; + + if (oledb->nlimit_enable != -EINVAL) { + val = oledb->nlimit_enable << + OLEDB_ENABLE_NLIMIT_BIT_SHIFT; + mask = OLEDB_ENABLE_NLIMIT_BIT; + if (oledb->negative_curr_limit != -EINVAL) { + for (i = 0; i < ARRAY_SIZE(oledb_nlimit_ma); i++) { + if (oledb->negative_curr_limit == + oledb_nlimit_ma[i]) + break; + } + val |= i; + mask |= OLEDB_NLIMIT_PGM_MASK; + } + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_NLIMIT, mask, val); + if (rc < 0) + pr_err("Failed to write NLIMT rc=%d\n", rc); + } + + return rc; +} + +static int qpnp_oledb_init_psm(struct qpnp_oledb *oledb) +{ + int rc = 0, i = 0; + u32 val = 0, mask = 0, temp = 0; + struct qpnp_oledb_psm_ctl *psm_ctl = &oledb->psm_ctl; + + if (psm_ctl->psm_enable == -EINVAL) + return rc; + + if (psm_ctl->psm_enable) { + val = OLEDB_PSM_ENABLE_BIT; + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_EN_PSM, OLEDB_PSM_ENABLE_BIT, val); + if (rc < 0) { + pr_err("Failed to write PSM_EN rc=%d\n", rc); + return rc; + } + + val = 0; + if (psm_ctl->psm_vref != -EINVAL) { + for (i = 0; i < ARRAY_SIZE(oledb_psm_vref_mv); i++) { + if (psm_ctl->psm_vref == + oledb_psm_vref_mv[i]) + break; + } + val = i; + mask = OLEDB_VREF_PSM_MASK; + } + + if (psm_ctl->psm_hys_ctl != -EINVAL) { + temp = PSM_HYSTERYSIS_MV_TO_VAL(psm_ctl->psm_hys_ctl); + val |= (temp << OLEDB_PSM_HYSTERYSIS_CTL_BIT_SHIFT); + mask |= OLEDB_PSM_HYSTERYSIS_CTL_BIT; + } + if (val) { + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_PSM_CTL, mask, val); + if (rc < 0) + pr_err("Failed to write PSM_CTL rc=%d\n", rc); + } + } else { + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_EN_PSM, OLEDB_PSM_ENABLE_BIT, 0); + if (rc < 0) + pr_err("Failed to write PSM_CTL rc=%d\n", rc); + } + + return rc; +} + +static int qpnp_oledb_init_pfm(struct qpnp_oledb *oledb) +{ + int rc = 0, i = 0; + u32 val = 0, temp = 0, mask = 0; + struct qpnp_oledb_pfm_ctl *pfm_ctl = &oledb->pfm_ctl; + + if (pfm_ctl->pfm_enable == -EINVAL) + return rc; + + if (pfm_ctl->pfm_enable) { + mask = val = OLEDB_PFM_ENABLE_BIT; + if (pfm_ctl->pfm_hys_ctl != -EINVAL) { + temp = PFM_HYSTERYSIS_MV_TO_VAL(pfm_ctl->pfm_hys_ctl); + val |= temp << + OLEDB_PFM_HYSTERYSIS_CTL_BIT_SHIFT; + mask |= OLEDB_PFM_HYSTERYSIS_CTRL_BIT_MASK; + } + + if (pfm_ctl->pfm_curr_limit != -EINVAL) { + for (i = 0; i < ARRAY_SIZE(oledb_pfm_curr_limit_ma); + i++) { + if (pfm_ctl->pfm_curr_limit == + oledb_pfm_curr_limit_ma[i]) + break; + } + val |= (i << OLEDB_PFM_CURR_LIMIT_SHIFT); + mask |= OLEDB_PFM_CURR_LIMIT_MASK; + } + + if (pfm_ctl->pfm_off_time != -EINVAL) { + val |= PFM_OFF_TIME_NS_TO_VAL(pfm_ctl->pfm_off_time); + mask |= OLEDB_PFM_OFF_TIME_NS_MASK; + } + + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_PFM_CTL, mask, val); + if (rc < 0) + pr_err("Failed to write PFM_CTL rc=%d\n", rc); + } else { + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_PFM_CTL, OLEDB_PFM_ENABLE_BIT, 0); + if (rc < 0) + pr_err("Failed to write PFM_CTL rc=%d\n", rc); + } + + return rc; +} + +static int qpnp_oledb_init_fast_precharge(struct qpnp_oledb *oledb) +{ + int rc = 0; + u32 val = 0, temp = 0, mask = 0; + struct qpnp_oledb_fast_precharge_ctl *prechg_ctl = + &oledb->fast_prechg_ctl; + + if (prechg_ctl->fast_prechg_ppulse_en == -EINVAL) + return rc; + + if (prechg_ctl->fast_prechg_ppulse_en) { + mask = val = OLEDB_FAST_PRECHG_PPULSE_EN_BIT; + if (prechg_ctl->prechg_debounce_time != -EINVAL) { + temp = PRECHG_DEBOUNCE_TIME_MS_TO_VAL( + prechg_ctl->prechg_debounce_time); + val |= temp << OLEDB_DBNC_PRECHARGE_SHIFT; + mask |= OLEDB_DBNC_PRECHARGE_MASK; + } + + if (prechg_ctl->prechg_pulse_period != -EINVAL) { + temp = PRECHG_PULSE_PERIOD_US_TO_VAL( + prechg_ctl->prechg_pulse_period); + val |= temp << OLEDB_PRECHARGE_PULSE_PERIOD_SHIFT; + mask |= OLEDB_PRECHARGE_PULSE_PERIOD_MASK; + } + + if (prechg_ctl->prechg_pulse_on_time != -EINVAL) { + val |= PRECHG_PULSE_ON_TIME_NS_TO_VAL( + prechg_ctl->prechg_pulse_on_time); + mask |= OLEDB_PRECHARGE_PULSE_TON_MASK; + } + + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_FAST_PRECHARGE, mask, val); + if (rc < 0) + pr_err("Failed to write FAST_PRECHARGE rc=%d\n", rc); + } else { + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_FAST_PRECHARGE, + OLEDB_FAST_PRECHG_PPULSE_EN_BIT, 0); + if (rc < 0) + pr_err("Failed to write FAST_PRECHARGE rc=%d\n", rc); + } + + return rc; +} + +static int qpnp_oledb_hw_init(struct qpnp_oledb *oledb) +{ + int rc, i = 0; + u8 val = 0, mask = 0; + u16 current_voltage; + + if (oledb->default_voltage != -EINVAL) { + val = (oledb->default_voltage - OLEDB_VOUT_MIN_MV) / + OLEDB_VOUT_STEP_MV; + rc = qpnp_oledb_write(oledb, oledb->base + + OLEDB_VOUT_DEFAULT, &val, 1); + if (rc < 0) { + pr_err("Failed to write VOUT_DEFAULT rc=%d\n", rc); + return rc; + } + } + + rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_MODULE_ENABLE, + (u8 *)&oledb->mod_enable, 1); + if (rc < 0) { + pr_err("Failed to read MODULE_ENABLE rc=%d\n", rc); + return rc; + } + + rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_EXT_PIN_CTL, + (u8 *)&oledb->ext_pinctl_state, 1); + if (rc < 0) { + pr_err("Failed to read EXT_PIN_CTL rc=%d\n", rc); + return rc; + } + + rc = qpnp_oledb_get_curr_voltage(oledb, ¤t_voltage); + if (rc < 0) + return rc; + + if (!((val & OLEDB_EXT_PIN_CTL_BIT) || oledb->mod_enable)) { + if (oledb->warmup_delay != -EINVAL) { + for (i = 0; i < ARRAY_SIZE(oledb_warmup_dly_ns); i++) { + if (oledb->warmup_delay == + oledb_warmup_dly_ns[i]) + break; + } + val = i; + rc = qpnp_oledb_masked_write(oledb, + oledb->base + OLEDB_BIAS_GEN_WARMUP_DELAY, + OLEDB_BIAS_GEN_WARMUP_DELAY_MASK, val); + if (rc < 0) { + pr_err("Failed to write WARMUP_DELAY rc=%d\n", + rc); + return rc; + } + } else { + rc = qpnp_oledb_read(oledb, oledb->base + + OLEDB_BIAS_GEN_WARMUP_DELAY, + &val, 1); + if (rc < 0) { + pr_err("Failed to read WARMUP_DELAY rc=%d\n", + rc); + return rc; + } + oledb->warmup_delay = oledb_warmup_dly_ns[val]; + } + + if (oledb->peak_curr_limit != -EINVAL) { + for (i = 0; i < ARRAY_SIZE(oledb_peak_curr_limit_ma); + i++) { + if (oledb->peak_curr_limit == + oledb_peak_curr_limit_ma[i]) + break; + } + val = i; + rc = qpnp_oledb_write(oledb, + oledb->base + OLEDB_ILIM_NFET, + &val, 1); + if (rc < 0) { + pr_err("Failed to write ILIM_NEFT rc=%d\n", rc); + return rc; + } + } + + if (oledb->pd_ctl != -EINVAL) { + val = oledb->pd_ctl; + rc = qpnp_oledb_write(oledb, oledb->base + + OLEDB_PD_CTL, &val, 1); + if (rc < 0) { + pr_err("Failed to write PD_CTL rc=%d\n", rc); + return rc; + } + } + + if (oledb->sc_en != -EINVAL) { + val = oledb->sc_en ? OLEDB_ENABLE_SC_DETECTION_BIT : 0; + mask = OLEDB_ENABLE_SC_DETECTION_BIT; + if (oledb->sc_dbnc_time != -EINVAL) { + val |= SHORT_CIRCUIT_DEBOUNCE_TIME_TO_VAL( + oledb->sc_dbnc_time); + mask |= OLEDB_DBNC_PRECHARGE_MASK; + } + + rc = qpnp_oledb_write(oledb, oledb->base + + OLEDB_SHORT_PROTECT, &val, 1); + if (rc < 0) { + pr_err("Failed to write SHORT_PROTECT rc=%d\n", + rc); + return rc; + } + } + + rc = qpnp_oledb_init_nlimit(oledb); + if (rc < 0) + return rc; + + rc = qpnp_oledb_init_psm(oledb); + if (rc < 0) + return rc; + + rc = qpnp_oledb_init_pfm(oledb); + if (rc < 0) + return rc; + + rc = qpnp_oledb_init_fast_precharge(oledb); + if (rc < 0) + return rc; + + if (oledb->swire_control) { + val = OLEDB_EN_SWIRE_PD_UPD_BIT | + OLEDB_EN_SWIRE_VOUT_UPD_BIT; + rc = qpnp_oledb_masked_write(oledb, oledb->base + + OLEDB_SWIRE_CONTROL, OLEDB_EN_SWIRE_PD_UPD_BIT | + OLEDB_EN_SWIRE_VOUT_UPD_BIT, val); + if (rc < 0) + return rc; + } + + rc = qpnp_oledb_read(oledb, oledb->base + OLEDB_MODULE_RDY, + &val, 1); + if (rc < 0) { + pr_err("Failed to read MODULE_RDY rc=%d\n", rc); + return rc; + } + + if (!(val & OLEDB_MODULE_RDY_BIT)) { + val = OLEDB_MODULE_RDY_BIT; + rc = qpnp_oledb_write(oledb, oledb->base + + OLEDB_MODULE_RDY, &val, 1); + if (rc < 0) { + pr_err("Failed to write MODULE_RDY rc=%d\n", + rc); + return rc; + } + } + + if (!oledb->dynamic_ext_pinctl_config) { + if (oledb->ext_pin_control) { + val = OLEDB_EXT_PIN_CTL_BIT; + rc = qpnp_oledb_write(oledb, oledb->base + + OLEDB_EXT_PIN_CTL, &val, 1); + if (rc < 0) { + pr_err("Failed to write EXT_PIN_CTL rc=%d\n", + rc); + return rc; + } + } else { + val = OLEDB_MODULE_ENABLE_BIT; + rc = qpnp_oledb_write(oledb, oledb->base + + OLEDB_MODULE_ENABLE, &val, 1); + if (rc < 0) { + pr_err("Failed to write MODULE_ENABLE rc=%d\n", + rc); + return rc; + } + + ndelay(oledb->warmup_delay); + } + + oledb->mod_enable = true; + if (oledb->pbs_control) { + rc = qpnp_oledb_masked_write(oledb, + oledb->base + OLEDB_SWIRE_CONTROL, + OLEDB_EN_SWIRE_PD_UPD_BIT | + OLEDB_EN_SWIRE_VOUT_UPD_BIT, 0); + if (rc < 0) { + pr_err("Failed to write SWIRE_CTL rc=%d\n", + rc); + return rc; + } + } + } + + oledb->current_voltage = current_voltage; + } else { + /* module is enabled */ + if (oledb->current_voltage == -EINVAL) { + oledb->current_voltage = current_voltage; + } else if (!oledb->swire_control) { + if (oledb->current_voltage < OLEDB_VOUT_MIN_MV) { + pr_err("current_voltage %d is less than min_volt %d\n", + oledb->current_voltage, OLEDB_VOUT_MIN_MV); + return -EINVAL; + } + val = DIV_ROUND_UP(oledb->current_voltage - + OLEDB_VOUT_MIN_MV, OLEDB_VOUT_STEP_MV); + rc = qpnp_oledb_write(oledb, oledb->base + + OLEDB_VOUT_PGM, &val, 1); + if (rc < 0) { + pr_err("Failed to write VOUT_PGM rc=%d\n", + rc); + return rc; + } + } + + oledb->mod_enable = true; + } + + return rc; +} + +static int qpnp_oledb_parse_nlimit(struct qpnp_oledb *oledb) +{ + int rc = 0; + struct device_node *of_node = oledb->dev->of_node; + + oledb->nlimit_enable = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,negative-curr-limit-enable", + &oledb->nlimit_enable); + if (!rc) { + oledb->negative_curr_limit = -EINVAL; + rc = of_property_read_u32(of_node, + "qcom,negative-curr-limit-ma", + &oledb->negative_curr_limit); + if (!rc) { + u16 min_curr_limit = oledb_nlimit_ma[0]; + u16 max_curr_limit = oledb_nlimit_ma[ARRAY_SIZE( + oledb_nlimit_ma) - 1]; + if (oledb->negative_curr_limit < min_curr_limit || + oledb->negative_curr_limit > max_curr_limit) { + pr_err("Invalid value in qcom,negative-curr-limit-ma\n"); + return -EINVAL; + } + } + } + + return 0; +} + +static int qpnp_oledb_parse_psm(struct qpnp_oledb *oledb) +{ + int rc = 0; + struct qpnp_oledb_psm_ctl *psm_ctl = &oledb->psm_ctl; + struct device_node *of_node = oledb->dev->of_node; + + psm_ctl->psm_enable = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,psm-enable", + &psm_ctl->psm_enable); + if (!rc) { + psm_ctl->psm_hys_ctl = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,psm-hys-mv", + &psm_ctl->psm_hys_ctl); + if (!rc) { + if (psm_ctl->psm_hys_ctl < OLEDB_PSM_HYS_CTRL_MIN || + psm_ctl->psm_hys_ctl > OLEDB_PSM_HYS_CTRL_MAX) { + pr_err("Invalid value in qcom,psm-hys-mv\n"); + return -EINVAL; + } + } + + psm_ctl->psm_vref = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,psm-vref-mv", + &psm_ctl->psm_vref); + if (!rc) { + u16 min_vref = oledb_psm_vref_mv[0]; + u16 max_vref = oledb_psm_vref_mv[ARRAY_SIZE( + oledb_psm_vref_mv) - 1]; + if (psm_ctl->psm_vref < min_vref || + psm_ctl->psm_vref > max_vref) { + pr_err("Invalid value in qcom,psm-vref-mv\n"); + return -EINVAL; + } + } + } + + return 0; +} + +static int qpnp_oledb_parse_pfm(struct qpnp_oledb *oledb) +{ + int rc = 0; + struct qpnp_oledb_pfm_ctl *pfm_ctl = &oledb->pfm_ctl; + struct device_node *of_node = oledb->dev->of_node; + + pfm_ctl->pfm_enable = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,pfm-enable", + &pfm_ctl->pfm_enable); + if (!rc) { + pfm_ctl->pfm_hys_ctl = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,pfm-hys-mv", + &pfm_ctl->pfm_hys_ctl); + if (!rc) { + if (pfm_ctl->pfm_hys_ctl < OLEDB_PFM_HYS_CTRL_MIN || + pfm_ctl->pfm_hys_ctl > OLEDB_PFM_HYS_CTRL_MAX) { + pr_err("Invalid value in qcom,pfm-hys-mv\n"); + return -EINVAL; + } + } + + pfm_ctl->pfm_curr_limit = -EINVAL; + rc = of_property_read_u32(of_node, + "qcom,pfm-curr-limit-ma", &pfm_ctl->pfm_curr_limit); + if (!rc) { + u16 min_limit = oledb_pfm_curr_limit_ma[0]; + u16 max_limit = oledb_pfm_curr_limit_ma[ARRAY_SIZE( + oledb_pfm_curr_limit_ma) - 1]; + if (pfm_ctl->pfm_curr_limit < min_limit || + pfm_ctl->pfm_curr_limit > max_limit) { + pr_err("Invalid value in qcom,pfm-curr-limit-ma\n"); + return -EINVAL; + } + } + + pfm_ctl->pfm_off_time = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,pfm-off-time-ns", + &pfm_ctl->pfm_off_time); + if (!rc) { + if (pfm_ctl->pfm_off_time < OLEDB_PFM_OFF_TIME_MIN || + pfm_ctl->pfm_off_time > OLEDB_PFM_OFF_TIME_MAX) { + pr_err("Invalid value in qcom,pfm-off-time-ns\n"); + return -EINVAL; + } + } + } + + return 0; +} + +static int qpnp_oledb_parse_fast_precharge(struct qpnp_oledb *oledb) +{ + int rc = 0; + struct device_node *of_node = oledb->dev->of_node; + struct qpnp_oledb_fast_precharge_ctl *fast_prechg = + &oledb->fast_prechg_ctl; + + fast_prechg->fast_prechg_ppulse_en = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,fast-precharge-ppulse-enable", + &fast_prechg->fast_prechg_ppulse_en); + if (!rc) { + fast_prechg->prechg_debounce_time = -EINVAL; + rc = of_property_read_u32(of_node, + "qcom,precharge-debounce-time-ms", + &fast_prechg->prechg_debounce_time); + if (!rc) { + int dbnc_time = fast_prechg->prechg_debounce_time; + + if (dbnc_time < OLEDB_PRECHG_TIME_MIN || dbnc_time > + OLEDB_PRECHG_TIME_MAX) { + pr_err("Invalid value in qcom,precharge-debounce-time-ms\n"); + return -EINVAL; + } + } + + fast_prechg->prechg_pulse_period = -EINVAL; + rc = of_property_read_u32(of_node, + "qcom,precharge-pulse-period-us", + &fast_prechg->prechg_pulse_period); + if (!rc) { + int pulse_period = fast_prechg->prechg_pulse_period; + + if (pulse_period < OLEDB_PRECHG_PULSE_PERIOD_MIN || + pulse_period > OLEDB_PRECHG_PULSE_PERIOD_MAX) { + pr_err("Invalid value in qcom,precharge-pulse-period-us\n"); + return -EINVAL; + } + } + + fast_prechg->prechg_pulse_on_time = -EINVAL; + rc = of_property_read_u32(of_node, + "qcom,precharge-pulse-on-time-ns", + &fast_prechg->prechg_pulse_on_time); + if (!rc) { + int pulse_on_time = fast_prechg->prechg_pulse_on_time; + + if (pulse_on_time < OLEDB_PRECHG_PULSE_ON_TIME_MIN || + pulse_on_time > OLEDB_PRECHG_PULSE_ON_TIME_MAX) { + pr_err("Invalid value in qcom,precharge-pulse-on-time-ns\n"); + return -EINVAL; + } + } + } + + return 0; +} + +static int qpnp_oledb_parse_dt(struct qpnp_oledb *oledb) +{ + int rc = 0; + struct device_node *of_node = oledb->dev->of_node; + + oledb->swire_control = + of_property_read_bool(of_node, "qcom,swire-control"); + + oledb->ext_pin_control = + of_property_read_bool(of_node, "qcom,ext-pin-control"); + + if (oledb->ext_pin_control) + oledb->dynamic_ext_pinctl_config = + of_property_read_bool(of_node, + "qcom,dynamic-ext-pinctl-config"); + oledb->pbs_control = + of_property_read_bool(of_node, "qcom,pbs-control"); + + oledb->current_voltage = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,oledb-init-voltage-mv", + &oledb->current_voltage); + if (!rc && (oledb->current_voltage < OLEDB_VOUT_MIN_MV || + oledb->current_voltage > OLEDB_VOUT_MAX_MV)) { + pr_err("Invalid value in qcom,oledb-init-voltage-mv\n"); + return -EINVAL; + } + + oledb->default_voltage = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,oledb-default-voltage-mv", + &oledb->default_voltage); + if (!rc && (oledb->default_voltage < OLEDB_VOUT_MIN_MV || + oledb->default_voltage > OLEDB_VOUT_MAX_MV)) { + pr_err("Invalid value in qcom,oledb-default-voltage-mv\n"); + return -EINVAL; + } + + oledb->warmup_delay = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,bias-gen-warmup-delay-ns", + &oledb->warmup_delay); + if (!rc) { + u16 min_delay = oledb_warmup_dly_ns[0]; + u16 max_delay = oledb_warmup_dly_ns[ARRAY_SIZE( + oledb_warmup_dly_ns) - 1]; + if (oledb->warmup_delay < min_delay || + oledb->warmup_delay > max_delay) { + pr_err("Invalid value in qcom,bias-gen-warmup-delay-ns\n"); + return -EINVAL; + } + } + + oledb->peak_curr_limit = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,peak-curr-limit-ma", + &oledb->peak_curr_limit); + if (!rc) { + u16 min_limit = oledb_peak_curr_limit_ma[0]; + u16 max_limit = oledb_peak_curr_limit_ma[ARRAY_SIZE( + oledb_peak_curr_limit_ma) - 1]; + if (oledb->peak_curr_limit < min_limit || + oledb->peak_curr_limit > max_limit) { + pr_err("Invalid value in qcom,peak-curr-limit-ma\n"); + return -EINVAL; + } + } + + oledb->pd_ctl = -EINVAL; + of_property_read_u32(of_node, "qcom,pull-down-enable", &oledb->pd_ctl); + + oledb->sc_en = -EINVAL; + rc = of_property_read_u32(of_node, "qcom,enable-short-circuit", + &oledb->sc_en); + if (!rc) { + oledb->sc_dbnc_time = -EINVAL; + rc = of_property_read_u32(of_node, + "qcom,short-circuit-dbnc-time", &oledb->sc_dbnc_time); + if (!rc) { + if (oledb->sc_dbnc_time < OLEDB_MIN_SC_DBNC_TIME_FSW || + oledb->sc_dbnc_time > OLEDB_MAX_SC_DBNC_TIME_FSW) { + pr_err("Invalid value in qcom,short-circuit-dbnc-time\n"); + return -EINVAL; + } + } + } + + rc = qpnp_oledb_parse_nlimit(oledb); + if (rc < 0) + return rc; + + rc = qpnp_oledb_parse_psm(oledb); + if (rc < 0) + return rc; + + rc = qpnp_oledb_parse_pfm(oledb); + if (rc < 0) + return rc; + + rc = qpnp_oledb_parse_fast_precharge(oledb); + + return rc; +} + +static int qpnp_oledb_regulator_probe(struct platform_device *pdev) +{ + int rc = 0; + u32 val; + struct qpnp_oledb *oledb; + struct device_node *of_node = pdev->dev.of_node; + + oledb = devm_kzalloc(&pdev->dev, + sizeof(struct qpnp_oledb), GFP_KERNEL); + if (!oledb) + return -ENOMEM; + + oledb->pdev = pdev; + oledb->dev = &pdev->dev; + oledb->regmap = dev_get_regmap(pdev->dev.parent, NULL); + dev_set_drvdata(&pdev->dev, oledb); + if (!oledb->regmap) { + pr_err("Couldn't get parent's regmap\n"); + return -EINVAL; + } + + rc = of_property_read_u32(of_node, "reg", &val); + if (rc < 0) { + pr_err("Couldn't find reg in node, rc = %d\n", rc); + return rc; + } + + oledb->base = val; + rc = qpnp_oledb_parse_dt(oledb); + if (rc < 0) { + pr_err("Failed to parse common OLEDB device tree\n"); + return rc; + } + + rc = qpnp_oledb_hw_init(oledb); + if (rc < 0) { + pr_err("Failed to initialize OLEDB, rc=%d\n", rc); + return rc; + } + + rc = qpnp_oledb_register_regulator(oledb); + if (!rc) + pr_info("OLEDB registered successfully, ext_pin_en=%d mod_en=%d cuurent_voltage=%d mV\n", + oledb->ext_pin_control, oledb->mod_enable, + oledb->current_voltage); + + return rc; +} + +static int qpnp_oledb_regulator_remove(struct platform_device *pdev) +{ + return 0; +} + +const struct of_device_id qpnp_oledb_regulator_match_table[] = { + { .compatible = QPNP_OLEDB_REGULATOR_DRIVER_NAME,}, + { }, +}; + +static struct platform_driver qpnp_oledb_regulator_driver = { + .driver = { + .name = QPNP_OLEDB_REGULATOR_DRIVER_NAME, + .of_match_table = qpnp_oledb_regulator_match_table, + }, + .probe = qpnp_oledb_regulator_probe, + .remove = qpnp_oledb_regulator_remove, +}; + +static int __init qpnp_oledb_regulator_init(void) +{ + return platform_driver_register(&qpnp_oledb_regulator_driver); +} +arch_initcall(qpnp_oledb_regulator_init); + +static void __exit qpnp_oledb_regulator_exit(void) +{ + platform_driver_unregister(&qpnp_oledb_regulator_driver); +} +module_exit(qpnp_oledb_regulator_exit); + +MODULE_DESCRIPTION("QPNP OLEDB driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("qpnp-oledb-regulator"); diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index 6e88e4b11273..2138e81bb9e9 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -1344,7 +1344,8 @@ start: hba->clk_gating.state = REQ_CLKS_ON; trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); - schedule_work(&hba->clk_gating.ungate_work); + queue_work(hba->clk_gating.ungating_workq, + &hba->clk_gating.ungate_work); /* * fall through to check if we should wait for this * work to be done or not. @@ -1617,6 +1618,7 @@ static enum hrtimer_restart ufshcd_clkgate_hrtimer_handler( static void ufshcd_init_clk_gating(struct ufs_hba *hba) { struct ufs_clk_gating *gating = &hba->clk_gating; + char wq_name[sizeof("ufs_clk_ungating_00")]; hba->clk_gating.state = CLKS_ON; @@ -1645,6 +1647,10 @@ static void ufshcd_init_clk_gating(struct ufs_hba *hba) hrtimer_init(&gating->gate_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); gating->gate_hrtimer.function = ufshcd_clkgate_hrtimer_handler; + snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_ungating_%d", + hba->host->host_no); + hba->clk_gating.ungating_workq = create_singlethread_workqueue(wq_name); + gating->is_enabled = true; gating->delay_ms_pwr_save = UFSHCD_CLK_GATING_DELAY_MS_PWR_SAVE; @@ -1707,6 +1713,7 @@ static void ufshcd_exit_clk_gating(struct ufs_hba *hba) device_remove_file(hba->dev, &hba->clk_gating.enable_attr); ufshcd_cancel_gate_work(hba); cancel_work_sync(&hba->clk_gating.ungate_work); + destroy_workqueue(hba->clk_gating.ungating_workq); } static void ufshcd_set_auto_hibern8_timer(struct ufs_hba *hba, u32 delay) diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h index b20afd85beab..c34a998aac17 100644 --- a/drivers/scsi/ufs/ufshcd.h +++ b/drivers/scsi/ufs/ufshcd.h @@ -431,6 +431,7 @@ struct ufs_clk_gating { struct device_attribute enable_attr; bool is_enabled; int active_reqs; + struct workqueue_struct *ungating_workq; }; /* Hibern8 state */ diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 21733633cb6c..281e83d90970 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -483,6 +483,15 @@ config PANIC_ON_GLADIATOR_ERROR_V2 If unsure, say N. +config MSM_GLADIATOR_ERROR_V2_MAIN_LOGGER_ONLY + depends on MSM_GLADIATOR_ERP_V2 + bool "QCOM Gladiator error v2 main logger support only" + help + Gladiator has two error loggers to report error captured. + By default, two error loggers will both be enabled. + This option enables only the main error logger. + If unsure, say no + config MSM_GLADIATOR_HANG_DETECT tristate "MSM Gladiator Hang Detection Support" help diff --git a/drivers/soc/qcom/gladiator_erp_v2.c b/drivers/soc/qcom/gladiator_erp_v2.c index 91b5d39be242..256b1a4fcdd5 100644 --- a/drivers/soc/qcom/gladiator_erp_v2.c +++ b/drivers/soc/qcom/gladiator_erp_v2.c @@ -23,6 +23,11 @@ #include <linux/clk.h> #define MODULE_NAME "gladiator-v2_error_reporting" +#ifdef CONFIG_MSM_GLADIATOR_ERROR_V2_MAIN_LOGGER_ONLY +#define OBSERVER_ERROR_ENABLE 0 +#else +#define OBSERVER_ERROR_ENABLE 1 +#endif /* Register Offsets */ #define GLADIATOR_ID_COREID 0x0 @@ -733,7 +738,8 @@ static int parse_dt_node(struct platform_device *pdev, static inline void gladiator_irq_init(void __iomem *gladiator_virt_base) { writel_relaxed(1, gladiator_virt_base + GLADIATOR_FAULTEN); - writel_relaxed(1, gladiator_virt_base + OBSERVER_0_FAULTEN); + writel_relaxed(OBSERVER_ERROR_ENABLE, + gladiator_virt_base + OBSERVER_0_FAULTEN); } #define CCI_LEVEL 2 diff --git a/drivers/soc/qcom/icnss.c b/drivers/soc/qcom/icnss.c index c3792d5a72ac..561a0d38e502 100644 --- a/drivers/soc/qcom/icnss.c +++ b/drivers/soc/qcom/icnss.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -720,6 +720,15 @@ int icnss_power_on(struct device *dev) } EXPORT_SYMBOL(icnss_power_on); +bool icnss_is_fw_ready(void) +{ + if (!penv) + return false; + else + return test_bit(ICNSS_FW_READY, &penv->state); +} +EXPORT_SYMBOL(icnss_is_fw_ready); + int icnss_power_off(struct device *dev) { struct icnss_priv *priv = dev_get_drvdata(dev); diff --git a/drivers/soc/qcom/memshare/msm_memshare.c b/drivers/soc/qcom/memshare/msm_memshare.c index dcca82fc25c6..5726c3277456 100644 --- a/drivers/soc/qcom/memshare/msm_memshare.c +++ b/drivers/soc/qcom/memshare/msm_memshare.c @@ -337,6 +337,21 @@ static int modem_notifier_cb(struct notifier_block *this, unsigned long code, bootup_request++; break; + case SUBSYS_BEFORE_POWERUP: + if (_cmd) + notifdata = (struct notif_data *) _cmd; + else + break; + + if (notifdata->enable_ramdump) { + pr_info("memshare: %s, Ramdump collection is enabled\n", + __func__); + ret = mem_share_do_ramdump(); + if (ret) + pr_err("Ramdump collection failed\n"); + } + break; + case SUBSYS_AFTER_POWERUP: pr_debug("memshare: Modem has booted up\n"); for (i = 0; i < MAX_CLIENTS; i++) { @@ -387,22 +402,6 @@ static int modem_notifier_cb(struct notifier_block *this, unsigned long code, bootup_request++; break; - case SUBSYS_RAMDUMP_NOTIFICATION: - if (_cmd) - notifdata = (struct notif_data *) _cmd; - else - break; - - if (!(notifdata->enable_ramdump)) { - pr_info("In %s, Ramdump collection is disabled\n", - __func__); - } else { - ret = mem_share_do_ramdump(); - if (ret) - pr_err("Ramdump collection failed\n"); - } - break; - default: pr_debug("Memshare: code: %lu\n", code); break; @@ -511,6 +510,8 @@ static int handle_alloc_generic_req(void *req_h, void *req, void *conn_h) pr_err("memshare: %s client not found, requested client: %d, proc_id: %d\n", __func__, alloc_req->client_id, alloc_req->proc_id); + kfree(alloc_resp); + alloc_resp = NULL; return -EINVAL; } @@ -555,6 +556,9 @@ static int handle_alloc_generic_req(void *req_h, void *req, void *conn_h) if (rc < 0) pr_err("In %s, Error sending the alloc request: %d\n", __func__, rc); + + kfree(alloc_resp); + alloc_resp = NULL; return rc; } @@ -672,6 +676,8 @@ static int handle_query_size_req(void *req_h, void *req, void *conn_h) pr_err("memshare: %s client not found, requested client: %d, proc_id: %d\n", __func__, query_req->client_id, query_req->proc_id); + kfree(query_resp); + query_resp = NULL; return -EINVAL; } @@ -697,6 +703,8 @@ static int handle_query_size_req(void *req_h, void *req, void *conn_h) pr_err("In %s, Error sending the query request: %d\n", __func__, rc); + kfree(query_resp); + query_resp = NULL; return rc; } diff --git a/drivers/soc/qcom/msm_glink_pkt.c b/drivers/soc/qcom/msm_glink_pkt.c index 9ebc6a3c23c9..78f6a2aa8f66 100644 --- a/drivers/soc/qcom/msm_glink_pkt.c +++ b/drivers/soc/qcom/msm_glink_pkt.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -502,13 +502,21 @@ static void glink_pkt_queue_rx_intent_worker(struct work_struct *work) struct queue_rx_intent_work, work); struct glink_pkt_dev *devp = work_item->devp; - if (!devp || !devp->handle) { + if (!devp) { + GLINK_PKT_ERR("%s: Invalid device\n", __func__); + kfree(work_item); + return; + } + mutex_lock(&devp->ch_lock); + if (!devp->handle) { GLINK_PKT_ERR("%s: Invalid device Handle\n", __func__); + mutex_unlock(&devp->ch_lock); kfree(work_item); return; } ret = glink_queue_rx_intent(devp->handle, devp, work_item->intent_size); + mutex_unlock(&devp->ch_lock); GLINK_PKT_INFO("%s: Triggered with size[%zu] ret[%d]\n", __func__, work_item->intent_size, ret); if (ret) @@ -1051,6 +1059,27 @@ error: } /** + * pop_rx_pkt() - return first pkt from rx pkt_list + * devp: pointer to G-Link packet device. + * + * This function return first item from rx pkt_list and NULL if list is empty. + */ +struct glink_rx_pkt *pop_rx_pkt(struct glink_pkt_dev *devp) +{ + unsigned long flags; + struct glink_rx_pkt *pkt = NULL; + + spin_lock_irqsave(&devp->pkt_list_lock, flags); + if (!list_empty(&devp->pkt_list)) { + pkt = list_first_entry(&devp->pkt_list, + struct glink_rx_pkt, list); + list_del(&pkt->list); + } + spin_unlock_irqrestore(&devp->pkt_list_lock, flags); + return pkt; +} + +/** * glink_pkt_release() - release operation on glink_pkt device * inode: Pointer to the inode structure. * file: Pointer to the file structure. @@ -1064,6 +1093,7 @@ int glink_pkt_release(struct inode *inode, struct file *file) int ret = 0; struct glink_pkt_dev *devp = file->private_data; unsigned long flags; + struct glink_rx_pkt *pkt; GLINK_PKT_INFO("%s() on dev id:%d by [%s] ref_cnt[%d]\n", __func__, devp->i, current->comm, devp->ref_cnt); @@ -1072,9 +1102,14 @@ int glink_pkt_release(struct inode *inode, struct file *file) devp->ref_cnt--; if (devp->handle && devp->ref_cnt == 0) { + while ((pkt = pop_rx_pkt(devp))) { + glink_rx_done(devp->handle, pkt->data, false); + kfree(pkt); + } wake_up(&devp->ch_read_wait_queue); wake_up_interruptible(&devp->ch_opened_wait_queue); ret = glink_close(devp->handle); + devp->handle = NULL; if (ret) { GLINK_PKT_ERR("%s: close failed ret[%d]\n", __func__, ret); diff --git a/drivers/soc/qcom/msm_smem.c b/drivers/soc/qcom/msm_smem.c index 8f5ad7af8d0d..9c4d89ac704d 100644 --- a/drivers/soc/qcom/msm_smem.c +++ b/drivers/soc/qcom/msm_smem.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -375,7 +375,7 @@ static void *__smem_get_entry_secure(unsigned id, uint32_t a_hdr_size; int rc; - SMEM_DBG("%s(%u, %u, %u, %u, %d, %d)\n", __func__, id, *size, to_proc, + SMEM_DBG("%s(%u, %u, %u, %d, %d)\n", __func__, id, to_proc, flags, skip_init_check, use_rspinlock); if (!skip_init_check && !smem_initialized_check()) @@ -817,7 +817,7 @@ EXPORT_SYMBOL(smem_alloc); void *smem_get_entry(unsigned id, unsigned *size, unsigned to_proc, unsigned flags) { - SMEM_DBG("%s(%u, %u, %u, %u)\n", __func__, id, *size, to_proc, flags); + SMEM_DBG("%s(%u, %u, %u)\n", __func__, id, to_proc, flags); /* * Handle the circular dependecy between SMEM and software implemented diff --git a/drivers/soc/qcom/pil-q6v5-mss.c b/drivers/soc/qcom/pil-q6v5-mss.c index 8ed98e2cbd5e..5f01d30de8d9 100644 --- a/drivers/soc/qcom/pil-q6v5-mss.c +++ b/drivers/soc/qcom/pil-q6v5-mss.c @@ -38,7 +38,7 @@ #define MAX_VDD_MSS_UV 1150000 #define PROXY_TIMEOUT_MS 10000 -#define MAX_SSR_REASON_LEN 81U +#define MAX_SSR_REASON_LEN 130U #define STOP_ACK_TIMEOUT_MS 1000 #define subsys_to_drv(d) container_of(d, struct modem_data, subsys_desc) diff --git a/drivers/soc/qcom/smcinvoke.c b/drivers/soc/qcom/smcinvoke.c index e920dfee8530..d0fef9d31755 100644 --- a/drivers/soc/qcom/smcinvoke.c +++ b/drivers/soc/qcom/smcinvoke.c @@ -192,9 +192,9 @@ static int prepare_send_scm_msg(const uint8_t *in_buf, size_t in_buf_len, desc.arginfo = SMCINVOKE_TZ_PARAM_ID; desc.args[0] = (uint64_t)virt_to_phys(in_buf); - desc.args[1] = in_buf_len; + desc.args[1] = inbuf_flush_size; desc.args[2] = (uint64_t)virt_to_phys(out_buf); - desc.args[3] = out_buf_len; + desc.args[3] = outbuf_flush_size; dmac_flush_range(in_buf, in_buf + inbuf_flush_size); dmac_flush_range(out_buf, out_buf + outbuf_flush_size); diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index bd58fcfe3061..dd3e545eb7da 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -535,12 +535,15 @@ static struct msm_soc_info cpu_of_id[] = { /* Hamster ID */ [306] = {MSM_CPU_HAMSTER, "MSMHAMSTER"}, - /* falcon ID */ - [317] = {MSM_CPU_FALCON, "MSMFALCON"}, - [324] = {MSM_CPU_FALCON, "APQFALCON"}, + /* 660 ID */ + [317] = {MSM_CPU_660, "SDM660"}, + [324] = {MSM_CPU_660, "SDA660"}, + [325] = {MSM_CPU_660, "SDM658"}, + [326] = {MSM_CPU_660, "SDA658"}, - /* triton ID */ - [318] = {MSM_CPU_TRITON, "MSMTRITON"}, + /* 630 ID */ + [318] = {MSM_CPU_630, "SDM630"}, + [327] = {MSM_CPU_630, "SDA630"}, /* Uninitialized IDs are not known to run Linux. MSM_CPU_UNKNOWN is set to 0 to ensure these IDs are @@ -1208,17 +1211,29 @@ static void * __init setup_dummy_socinfo(void) dummy_socinfo.id = 306; strlcpy(dummy_socinfo.build_id, "msmhamster - ", sizeof(dummy_socinfo.build_id)); - } else if (early_machine_is_msmfalcon()) { + } else if (early_machine_is_sdm660()) { dummy_socinfo.id = 317; - strlcpy(dummy_socinfo.build_id, "msmfalcon - ", + strlcpy(dummy_socinfo.build_id, "sdm660 - ", sizeof(dummy_socinfo.build_id)); - } else if (early_machine_is_apqfalcon()) { + } else if (early_machine_is_sda660()) { dummy_socinfo.id = 324; - strlcpy(dummy_socinfo.build_id, "apqfalcon - ", + strlcpy(dummy_socinfo.build_id, "sda660 - ", sizeof(dummy_socinfo.build_id)); - } else if (early_machine_is_msmtriton()) { + } else if (early_machine_is_sdm658()) { + dummy_socinfo.id = 325; + strlcpy(dummy_socinfo.build_id, "sdm658 - ", + sizeof(dummy_socinfo.build_id)); + } else if (early_machine_is_sda658()) { + dummy_socinfo.id = 326; + strlcpy(dummy_socinfo.build_id, "sda658 - ", + sizeof(dummy_socinfo.build_id)); + } else if (early_machine_is_sdm630()) { dummy_socinfo.id = 318; - strlcpy(dummy_socinfo.build_id, "msmtriton - ", + strlcpy(dummy_socinfo.build_id, "sdm630 - ", + sizeof(dummy_socinfo.build_id)); + } else if (early_machine_is_sda630()) { + dummy_socinfo.id = 327; + strlcpy(dummy_socinfo.build_id, "sda630 - ", sizeof(dummy_socinfo.build_id)); } else if (early_machine_is_apq8998()) { dummy_socinfo.id = 319; diff --git a/drivers/soc/qcom/spcom.c b/drivers/soc/qcom/spcom.c index e8ea99827403..9b71083e4f27 100644 --- a/drivers/soc/qcom/spcom.c +++ b/drivers/soc/qcom/spcom.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -274,6 +274,8 @@ static int spcom_open(struct spcom_channel *ch, unsigned int timeout_msec); static int spcom_close(struct spcom_channel *ch); static void spcom_notify_rx_abort(void *handle, const void *priv, const void *pkt_priv); +static struct spcom_channel *spcom_find_channel_by_name(const char *name); +static int spcom_unlock_ion_buf(struct spcom_channel *ch, int fd); /** * spcom_is_ready() - driver is initialized and ready. @@ -347,6 +349,9 @@ static int spcom_create_predefined_channels_chardev(void) static void spcom_link_state_notif_cb(struct glink_link_state_cb_info *cb_info, void *priv) { + struct spcom_channel *ch = NULL; + const char *ch_name = "sp_kernel"; + spcom_dev->link_state = cb_info->link_state; pr_debug("spcom_link_state_notif_cb called. transport = %s edge = %s\n", @@ -359,6 +364,17 @@ static void spcom_link_state_notif_cb(struct glink_link_state_cb_info *cb_info, break; case GLINK_LINK_STATE_DOWN: pr_err("GLINK_LINK_STATE_DOWN.\n"); + + /* + * Free all the SKP ION buffers that were locked + * for SPSS app swapping, when remote subsystem reset. + */ + pr_debug("Free all SKP ION buffers on SSR.\n"); + ch = spcom_find_channel_by_name(ch_name); + if (!ch) + pr_err("failed to find channel [%s].\n", ch_name); + else + spcom_unlock_ion_buf(ch, SPCOM_ION_FD_UNLOCK_ALL); break; default: pr_err("unknown link_state [%d].\n", cb_info->link_state); @@ -1643,24 +1659,18 @@ static int spcom_handle_lock_ion_buf_command(struct spcom_channel *ch, } /** - * spcom_handle_unlock_ion_buf_command() - Unlock an ION buffer. + * spcom_unlock_ion_buf() - Unlock an ION buffer. * * Unlock an ION buffer, let it be free, when it is no longer being used by * the remote subsystem. */ -static int spcom_handle_unlock_ion_buf_command(struct spcom_channel *ch, - void *cmd_buf, int size) +static int spcom_unlock_ion_buf(struct spcom_channel *ch, int fd) { - struct spcom_user_command *cmd = cmd_buf; - int fd = cmd->arg; struct ion_client *ion_client = spcom_dev->ion_client; int i; + bool found = false; - if (size != sizeof(*cmd)) { - pr_err("cmd size [%d] , expected [%d].\n", - (int) size, (int) sizeof(*cmd)); - return -EINVAL; - } + pr_debug("Unlock ion buf ch [%s] fd [%d].\n", ch->name, fd); /* Check ION client */ if (ion_client == NULL) { @@ -1669,6 +1679,8 @@ static int spcom_handle_unlock_ion_buf_command(struct spcom_channel *ch, } if (fd == (int) SPCOM_ION_FD_UNLOCK_ALL) { + pr_debug("unlocked ALL ion buf ch [%s].\n", ch->name); + found = true; /* unlock all ION buf */ for (i = 0 ; i < ARRAY_SIZE(ch->ion_handle_table) ; i++) { if (ch->ion_handle_table[i] != NULL) { @@ -1686,15 +1698,45 @@ static int spcom_handle_unlock_ion_buf_command(struct spcom_channel *ch, ch->ion_handle_table[i] = NULL; ch->ion_fd_table[i] = -1; pr_debug("unlocked ion buf#[%d].\n", i); + found = true; break; } } } + if (!found) { + pr_err("ch [%s] fd [%d] was not found.\n", ch->name, fd); + return -ENODEV; + } + return 0; } /** + * spcom_handle_unlock_ion_buf_command() - Unlock an ION buffer. + * + * Unlock an ION buffer, let it be free, when it is no longer being used by + * the remote subsystem. + */ +static int spcom_handle_unlock_ion_buf_command(struct spcom_channel *ch, + void *cmd_buf, int size) +{ + int ret; + struct spcom_user_command *cmd = cmd_buf; + int fd = cmd->arg; + + if (size != sizeof(*cmd)) { + pr_err("cmd size [%d] , expected [%d].\n", + (int) size, (int) sizeof(*cmd)); + return -EINVAL; + } + + ret = spcom_unlock_ion_buf(ch, fd); + + return ret; +} + +/** * spcom_handle_fake_ssr_command() - Handle fake ssr command from user space. */ static int spcom_handle_fake_ssr_command(struct spcom_channel *ch, int arg) diff --git a/drivers/soc/qcom/spss_utils.c b/drivers/soc/qcom/spss_utils.c index e54819b4837b..c93a9a5c8a1c 100644 --- a/drivers/soc/qcom/spss_utils.c +++ b/drivers/soc/qcom/spss_utils.c @@ -48,6 +48,7 @@ static const char *test_firmware_name; static const char *prod_firmware_name; static const char *firmware_name; static struct device *spss_dev; +static u32 spss_debug_reg_addr; /* SP_SCSR_MBn_SP2CL_GPm(n,m) */ /*==========================================================================*/ /* Device Sysfs */ @@ -117,6 +118,51 @@ static ssize_t test_fuse_state_store(struct device *dev, static DEVICE_ATTR(test_fuse_state, 0444, test_fuse_state_show, test_fuse_state_store); +static ssize_t spss_debug_reg_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int ret; + void __iomem *spss_debug_reg = NULL; + int val1, val2; + + if (!dev || !attr || !buf) { + pr_err("invalid param.\n"); + return -EINVAL; + } + + pr_debug("spss_debug_reg_addr [0x%x].\n", spss_debug_reg_addr); + + spss_debug_reg = ioremap_nocache(spss_debug_reg_addr, 0x16); + + if (!spss_debug_reg) { + pr_err("can't map debug reg addr.\n"); + return -EFAULT; + } + + val1 = readl_relaxed(spss_debug_reg); + val2 = readl_relaxed(((char *) spss_debug_reg) + 0x04); + + ret = snprintf(buf, PAGE_SIZE, "val1 [0x%x] val2 [0x%x]", val1, val2); + + iounmap(spss_debug_reg); + + return ret; +} + +static ssize_t spss_debug_reg_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + pr_err("set debug reg is not allowed.\n"); + + return -EINVAL; +} + +static DEVICE_ATTR(spss_debug_reg, 0444, + spss_debug_reg_show, spss_debug_reg_store); + static int spss_create_sysfs(struct device *dev) { int ret; @@ -133,6 +179,12 @@ static int spss_create_sysfs(struct device *dev) return ret; } + ret = device_create_file(dev, &dev_attr_spss_debug_reg); + if (ret < 0) { + pr_err("failed to create sysfs file for spss_debug_reg.\n"); + return ret; + } + return 0; } @@ -201,6 +253,13 @@ static int spss_parse_dt(struct device_node *node) iounmap(spss_fuse_reg); + ret = of_property_read_u32(node, "qcom,spss-debug-reg-addr", + &spss_debug_reg_addr); + if (ret < 0) { + pr_err("can't get debug regs addr.\n"); + return ret; + } + return 0; } diff --git a/drivers/soc/qcom/subsys-pil-tz.c b/drivers/soc/qcom/subsys-pil-tz.c index b8d096a9c057..769a683e3d8d 100644 --- a/drivers/soc/qcom/subsys-pil-tz.c +++ b/drivers/soc/qcom/subsys-pil-tz.c @@ -25,6 +25,7 @@ #include <linux/msm-bus-board.h> #include <linux/msm-bus.h> #include <linux/dma-mapping.h> +#include <linux/highmem.h> #include <soc/qcom/subsystem_restart.h> #include <soc/qcom/ramdump.h> @@ -613,6 +614,10 @@ static int pil_init_image_trusted(struct pil_desc *pil, return -ENOMEM; } + /* Make sure there are no mappings in PKMAP and fixmap */ + kmap_flush_unused(); + kmap_atomic_flush_unused(); + memcpy(mdata_buf, metadata, size); request.proc = d->pas_id; diff --git a/drivers/staging/android/ion/ion.c b/drivers/staging/android/ion/ion.c index e0af922a0329..e0af922a0329 100755..100644 --- a/drivers/staging/android/ion/ion.c +++ b/drivers/staging/android/ion/ion.c diff --git a/drivers/thermal/msm-tsens.c b/drivers/thermal/msm-tsens.c index 243b3229f53e..b7733e90fc8b 100644 --- a/drivers/thermal/msm-tsens.c +++ b/drivers/thermal/msm-tsens.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -140,215 +140,7 @@ #define TSENS_CTRL_ADDR(n) (n) #define TSENS_EN BIT(0) -#define TSENS_SW_RST BIT(1) -#define TSENS_ADC_CLK_SEL BIT(2) -#define TSENS_SENSOR0_SHIFT 3 -#define TSENS_62_5_MS_MEAS_PERIOD 1 -#define TSENS_312_5_MS_MEAS_PERIOD 2 -#define TSENS_MEAS_PERIOD_SHIFT 18 - -#define TSENS_GLOBAL_CONFIG(n) ((n) + 0x34) -#define TSENS_S0_MAIN_CONFIG(n) ((n) + 0x38) -#define TSENS_SN_REMOTE_CONFIG(n) ((n) + 0x3c) - -#define TSENS_EEPROM(n) ((n) + 0xd0) -#define TSENS_EEPROM_REDUNDANCY_SEL(n) ((n) + 0x444) -#define TSENS_EEPROM_BACKUP_REGION(n) ((n) + 0x440) - -#define TSENS_MAIN_CALIB_ADDR_RANGE 6 -#define TSENS_BACKUP_CALIB_ADDR_RANGE 4 - -#define TSENS_EEPROM_8X26_1(n) ((n) + 0x1c0) -#define TSENS_EEPROM_8X26_2(n) ((n) + 0x444) -#define TSENS_8X26_MAIN_CALIB_ADDR_RANGE 4 - -#define TSENS_EEPROM_8X10_1(n) ((n) + 0x1a4) -#define TSENS_EEPROM_8X10_1_OFFSET 8 -#define TSENS_EEPROM_8X10_2(n) ((n) + 0x1a8) -#define TSENS_EEPROM_8X10_SPARE_1(n) ((n) + 0xd8) -#define TSENS_EEPROM_8X10_SPARE_2(n) ((n) + 0xdc) - -#define TSENS_9900_EEPROM(n) ((n) + 0xd0) -#define TSENS_9900_EEPROM_REDUNDANCY_SEL(n) ((n) + 0x1c4) -#define TSENS_9900_EEPROM_BACKUP_REGION(n) ((n) + 0x450) -#define TSENS_9900_CALIB_ADDR_RANGE 4 - -#define TSENS_8939_EEPROM(n) ((n) + 0xa0) - -#define TSENS_8994_EEPROM(n) ((n) + 0xd0) -#define TSENS_8994_EEPROM_REDUN_SEL(n) ((n) + 0x464) -#define TSENS_REDUN_REGION1_EEPROM(n) ((n) + 0x1c0) -#define TSENS_REDUN_REGION2_EEPROM(n) ((n) + 0x1c4) -#define TSENS_REDUN_REGION3_EEPROM(n) ((n) + 0x1cc) -#define TSENS_REDUN_REGION4_EEPROM(n) ((n) + 0x440) -#define TSENS_REDUN_REGION5_EEPROM(n) ((n) + 0x444) - -/* TSENS calibration Mask data */ -#define TSENS_BASE1_MASK 0xff -#define TSENS0_POINT1_MASK 0x3f00 -#define TSENS1_POINT1_MASK 0xfc000 -#define TSENS2_POINT1_MASK 0x3f00000 -#define TSENS3_POINT1_MASK 0xfc000000 -#define TSENS4_POINT1_MASK 0x3f -#define TSENS5_POINT1_MASK 0xfc0 -#define TSENS6_POINT1_MASK 0x3f000 -#define TSENS7_POINT1_MASK 0xfc0000 -#define TSENS8_POINT1_MASK 0x3f000000 -#define TSENS8_POINT1_MASK_BACKUP 0x3f -#define TSENS9_POINT1_MASK 0x3f -#define TSENS9_POINT1_MASK_BACKUP 0xfc0 -#define TSENS10_POINT1_MASK 0xfc0 -#define TSENS10_POINT1_MASK_BACKUP 0x3f000 -#define TSENS_CAL_SEL_0_1 0xc0000000 -#define TSENS_CAL_SEL_2 0x40000000 -#define TSENS_CAL_SEL_SHIFT 30 -#define TSENS_CAL_SEL_SHIFT_2 28 -#define TSENS_ONE_POINT_CALIB 0x1 -#define TSENS_ONE_POINT_CALIB_OPTION_2 0x2 -#define TSENS_TWO_POINT_CALIB 0x3 - -#define TSENS0_POINT1_SHIFT 8 -#define TSENS1_POINT1_SHIFT 14 -#define TSENS2_POINT1_SHIFT 20 -#define TSENS3_POINT1_SHIFT 26 -#define TSENS5_POINT1_SHIFT 6 -#define TSENS6_POINT1_SHIFT 12 -#define TSENS7_POINT1_SHIFT 18 -#define TSENS8_POINT1_SHIFT 24 -#define TSENS9_POINT1_BACKUP_SHIFT 6 -#define TSENS10_POINT1_SHIFT 6 -#define TSENS10_POINT1_BACKUP_SHIFT 12 - -#define TSENS_POINT2_BASE_SHIFT 12 -#define TSENS_POINT2_BASE_BACKUP_SHIFT 18 -#define TSENS0_POINT2_SHIFT 20 -#define TSENS0_POINT2_BACKUP_SHIFT 26 -#define TSENS1_POINT2_SHIFT 26 -#define TSENS2_POINT2_BACKUP_SHIFT 6 -#define TSENS3_POINT2_SHIFT 6 -#define TSENS3_POINT2_BACKUP_SHIFT 12 -#define TSENS4_POINT2_SHIFT 12 -#define TSENS4_POINT2_BACKUP_SHIFT 18 -#define TSENS5_POINT2_SHIFT 18 -#define TSENS5_POINT2_BACKUP_SHIFT 24 -#define TSENS6_POINT2_SHIFT 24 -#define TSENS7_POINT2_BACKUP_SHIFT 6 -#define TSENS8_POINT2_SHIFT 6 -#define TSENS8_POINT2_BACKUP_SHIFT 12 -#define TSENS9_POINT2_SHIFT 12 -#define TSENS9_POINT2_BACKUP_SHIFT 18 -#define TSENS10_POINT2_SHIFT 18 -#define TSENS10_POINT2_BACKUP_SHIFT 24 - -#define TSENS_BASE2_MASK 0xff000 -#define TSENS_BASE2_BACKUP_MASK 0xfc0000 -#define TSENS0_POINT2_MASK 0x3f00000 -#define TSENS0_POINT2_BACKUP_MASK 0xfc000000 -#define TSENS1_POINT2_MASK 0xfc000000 -#define TSENS1_POINT2_BACKUP_MASK 0x3f -#define TSENS2_POINT2_MASK 0x3f -#define TSENS2_POINT2_BACKUP_MASK 0xfc0 -#define TSENS3_POINT2_MASK 0xfc0 -#define TSENS3_POINT2_BACKUP_MASK 0x3f000 -#define TSENS4_POINT2_MASK 0x3f000 -#define TSENS4_POINT2_BACKUP_MASK 0xfc0000 -#define TSENS5_POINT2_MASK 0xfc0000 -#define TSENS5_POINT2_BACKUP_MASK 0x3f000000 -#define TSENS6_POINT2_MASK 0x3f000000 -#define TSENS6_POINT2_BACKUP_MASK 0x3f -#define TSENS7_POINT2_MASK 0x3f -#define TSENS7_POINT2_BACKUP_MASK 0xfc0 -#define TSENS8_POINT2_MASK 0xfc0 -#define TSENS8_POINT2_BACKUP_MASK 0x3f000 -#define TSENS9_POINT2_MASK 0x3f000 -#define TSENS9_POINT2_BACKUP_MASK 0xfc0000 -#define TSENS10_POINT2_MASK 0xfc0000 -#define TSENS10_POINT2_BACKUP_MASK 0x3f000000 - -#define TSENS_8X26_BASE0_MASK 0x1fe000 -#define TSENS0_8X26_POINT1_MASK 0x7e00000 -#define TSENS1_8X26_POINT1_MASK 0x3f -#define TSENS2_8X26_POINT1_MASK 0xfc0 -#define TSENS3_8X26_POINT1_MASK 0x3f000 -#define TSENS4_8X26_POINT1_MASK 0xfc0000 -#define TSENS5_8X26_POINT1_MASK 0x3f000000 -#define TSENS6_8X26_POINT1_MASK 0x3f00000 -#define TSENS_8X26_TSENS_CAL_SEL 0xe0000000 -#define TSENS_8X26_BASE1_MASK 0xff -#define TSENS0_8X26_POINT2_MASK 0x3f00 -#define TSENS1_8X26_POINT2_MASK 0xfc000 -#define TSENS2_8X26_POINT2_MASK 0x3f00000 -#define TSENS3_8X26_POINT2_MASK 0xfc000000 -#define TSENS4_8X26_POINT2_MASK 0x3f00000 -#define TSENS5_8X26_POINT2_MASK 0xfc000000 -#define TSENS6_8X26_POINT2_MASK 0x7e0000 - -#define TSENS_8X26_CAL_SEL_SHIFT 29 -#define TSENS_8X26_BASE0_SHIFT 13 -#define TSENS0_8X26_POINT1_SHIFT 21 -#define TSENS2_8X26_POINT1_SHIFT 6 -#define TSENS3_8X26_POINT1_SHIFT 12 -#define TSENS4_8X26_POINT1_SHIFT 18 -#define TSENS5_8X26_POINT1_SHIFT 24 -#define TSENS6_8X26_POINT1_SHIFT 20 - -#define TSENS0_8X26_POINT2_SHIFT 8 -#define TSENS1_8X26_POINT2_SHIFT 14 -#define TSENS2_8X26_POINT2_SHIFT 20 -#define TSENS3_8X26_POINT2_SHIFT 26 -#define TSENS4_8X26_POINT2_SHIFT 20 -#define TSENS5_8X26_POINT2_SHIFT 26 -#define TSENS6_8X26_POINT2_SHIFT 17 - -#define TSENS_8X10_CAL_SEL_SHIFT 28 -#define TSENS_8X10_BASE1_SHIFT 8 -#define TSENS0_8X10_POINT1_SHIFT 16 -#define TSENS0_8X10_POINT2_SHIFT 22 -#define TSENS1_8X10_POINT2_SHIFT 6 -#define TSENS_8X10_BASE0_MASK 0xff -#define TSENS_8X10_BASE1_MASK 0xff00 -#define TSENS0_8X10_POINT1_MASK 0x3f0000 -#define TSENS0_8X10_POINT2_MASK 0xfc00000 -#define TSENS_8X10_TSENS_CAL_SEL 0x70000000 -#define TSENS1_8X10_POINT1_MASK 0x3f -#define TSENS1_8X10_POINT2_MASK 0xfc0 -#define TSENS_8X10_REDUN_SEL_MASK 0x6000000 -#define TSENS_8X10_REDUN_SEL_SHIFT 25 - -#define TSENS0_9900_POINT1_SHIFT 19 -#define TSENS2_9900_POINT1_SHIFT 12 -#define TSENS3_9900_POINT1_SHIFT 24 -#define TSENS4_9900_POINT1_SHIFT 6 -#define TSENS5_9900_POINT1_SHIFT 18 -#define TSENS_9900_BASE1_MASK 0xff -#define TSENS0_9900_POINT1_MASK 0x1f80000 -#define TSENS1_9900_POINT1_MASK 0x3f -#define TSENS2_9900_POINT1_MASK 0x3f000 -#define TSENS3_9900_POINT1_MASK 0x3f000000 -#define TSENS4_9900_POINT1_MASK 0xfc0 -#define TSENS5_9900_POINT1_MASK 0xfc0000 -#define TSENS6_9900_POINT1_MASK 0x3f - -#define TSENS_9900_BASE2_SHIFT 8 -#define TSENS0_9900_POINT2_SHIFT 25 -#define TSENS1_9900_POINT2_SHIFT 6 -#define TSENS2_9900_POINT2_SHIFT 18 -#define TSENS4_9900_POINT2_SHIFT 12 -#define TSENS5_9900_POINT2_SHIFT 24 -#define TSENS6_9900_POINT2_SHIFT 6 -#define TSENS_9900_BASE2_MASK 0xff00 -#define TSENS0_9900_POINT2_MASK 0x7e000000 -#define TSENS1_9900_POINT2_MASK 0xfc0 -#define TSENS2_9900_POINT2_MASK 0xfc0000 -#define TSENS3_9900_POINT2_MASK 0x3f -#define TSENS4_9900_POINT2_MASK 0x3f000 -#define TSENS5_9900_POINT2_MASK 0x3f000000 -#define TSENS6_9900_POINT2_MASK 0xfc0 - -#define TSENS_9900_CAL_SEL_SHIFT 16 -#define TSENS_9900_TSENS_CAL_SEL 0x00070000 - -#define TSENS_BIT_APPEND 0x3 + #define TSENS_CAL_DEGC_POINT1 30 #define TSENS_CAL_DEGC_POINT2 120 #define TSENS_SLOPE_FACTOR 1000 @@ -359,354 +151,11 @@ #define TSENS_THRESHOLD_MAX_CODE 0x3ff #define TSENS_THRESHOLD_MIN_CODE 0x0 -#define TSENS_GLOBAL_INIT_DATA 0x302f16c -#define TSENS_S0_MAIN_CFG_INIT_DATA 0x1c3 -#define TSENS_SN_REMOTE_CFG_DATA 0x11c3 - -#define TSENS_QFPROM_BACKUP_SEL 0x3 -#define TSENS_QFPROM_BACKUP_REDUN_SEL 0xe0000000 -#define TSENS_QFPROM_BACKUP_REDUN_SHIFT 29 - -#define TSENS_QFPROM_BACKUP_9900_REDUN_SEL 0x07000000 -#define TSENS_QFPROM_BACKUP_9900_REDUN_SHIFT 24 - -#define TSENS_TORINO_BASE0 0x3ff -#define TSENS_TORINO_BASE1 0xffc00 -#define TSENS_TORINO_POINT0 0xf00000 -#define TSENS_TORINO_POINT1 0xf0000000 -#define TSENS_TORINO_POINT2 0xf0 -#define TSENS_TORINO_POINT3 0xf000 -#define TSENS_TORINO_POINT4 0xf00000 -#define TSENS_TORINO_CALIB_PT 0x70000000 - -#define TSENS_TORINO_BASE1_SHIFT 10 -#define TSENS_TORINO_POINT0_SHIFT 20 -#define TSENS_TORINO_POINT1_SHIFT 28 -#define TSENS_TORINO_POINT2_SHIFT 4 -#define TSENS_TORINO_POINT3_SHIFT 12 -#define TSENS_TORINO_POINT4_SHIFT 20 -#define TSENS_TORINO_CALIB_SHIFT 28 - #define TSENS_TYPE0 0 #define TSENS_TYPE2 2 #define TSENS_TYPE3 3 #define TSENS_TYPE4 4 -#define TSENS_8916_BASE0_MASK 0x0000007f -#define TSENS_8916_BASE1_MASK 0xfe000000 - -#define TSENS0_8916_POINT1_MASK 0x00000f80 -#define TSENS1_8916_POINT1_MASK 0x003e0000 -#define TSENS2_8916_POINT1_MASK 0xf8000000 -#define TSENS3_8916_POINT1_MASK 0x000003e0 -#define TSENS4_8916_POINT1_MASK 0x000f8000 - -#define TSENS0_8916_POINT2_MASK 0x0001f000 -#define TSENS1_8916_POINT2_MASK 0x07c00000 -#define TSENS2_8916_POINT2_MASK 0x0000001f -#define TSENS3_8916_POINT2_MASK 0x00007c00 -#define TSENS4_8916_POINT2_MASK 0x01f00000 - -#define TSENS_8916_TSENS_CAL_SEL 0xe0000000 - -#define TSENS_8916_CAL_SEL_SHIFT 29 -#define TSENS_8916_BASE1_SHIFT 25 - -#define TSENS0_8916_POINT1_SHIFT 7 -#define TSENS1_8916_POINT1_SHIFT 17 -#define TSENS2_8916_POINT1_SHIFT 27 -#define TSENS3_8916_POINT1_SHIFT 5 -#define TSENS4_8916_POINT1_SHIFT 15 - -#define TSENS0_8916_POINT2_SHIFT 12 -#define TSENS1_8916_POINT2_SHIFT 22 -#define TSENS3_8916_POINT2_SHIFT 10 -#define TSENS4_8916_POINT2_SHIFT 20 -#define TSENS_VALID_CNT_2 2 - -#define TSENS_8939_BASE0_MASK 0x000000ff -#define TSENS_8939_BASE1_MASK 0xff000000 - -#define TSENS0_8939_POINT1_MASK 0x000001f8 -#define TSENS1_8939_POINT1_MASK 0x001f8000 -#define TSENS2_8939_POINT1_MASK_0_4 0xf8000000 -#define TSENS2_8939_POINT1_MASK_5 0x00000001 -#define TSENS3_8939_POINT1_MASK 0x00001f80 -#define TSENS4_8939_POINT1_MASK 0x01f80000 -#define TSENS5_8939_POINT1_MASK 0x00003f00 -#define TSENS6_8939_POINT1_MASK 0x03f00000 -#define TSENS7_8939_POINT1_MASK 0x0000003f -#define TSENS8_8939_POINT1_MASK 0x0003f000 - -#define TSENS0_8939_POINT2_MASK 0x00007e00 -#define TSENS1_8939_POINT2_MASK 0x07e00000 -#define TSENS2_8939_POINT2_MASK 0x0000007e -#define TSENS3_8939_POINT2_MASK 0x0007e000 -#define TSENS4_8939_POINT2_MASK 0x7e000000 -#define TSENS5_8939_POINT2_MASK 0x000fc000 -#define TSENS6_8939_POINT2_MASK 0xfc000000 -#define TSENS7_8939_POINT2_MASK 0x00000fc0 -#define TSENS8_8939_POINT2_MASK 0x00fc0000 - -#define TSENS_8939_TSENS_CAL_SEL 0x7 -#define TSENS_8939_CAL_SEL_SHIFT 0 -#define TSENS_8939_BASE1_SHIFT 24 - -#define TSENS0_8939_POINT1_SHIFT 3 -#define TSENS1_8939_POINT1_SHIFT 15 -#define TSENS2_8939_POINT1_SHIFT_0_4 27 -#define TSENS2_8939_POINT1_SHIFT_5 5 -#define TSENS3_8939_POINT1_SHIFT 7 -#define TSENS4_8939_POINT1_SHIFT 19 -#define TSENS5_8939_POINT1_SHIFT 8 -#define TSENS6_8939_POINT1_SHIFT 20 -#define TSENS8_8939_POINT1_SHIFT 12 - -#define TSENS0_8939_POINT2_SHIFT 9 -#define TSENS1_8939_POINT2_SHIFT 21 -#define TSENS2_8939_POINT2_SHIFT 1 -#define TSENS3_8939_POINT2_SHIFT 13 -#define TSENS4_8939_POINT2_SHIFT 25 -#define TSENS5_8939_POINT2_SHIFT 14 -#define TSENS6_8939_POINT2_SHIFT 26 -#define TSENS7_8939_POINT2_SHIFT 6 -#define TSENS8_8939_POINT2_SHIFT 18 - -#define TSENS_BASE0_8994_MASK 0x3ff -#define TSENS_BASE1_8994_MASK 0xffc00 -#define TSENS_BASE1_8994_SHIFT 10 -#define TSENS0_OFFSET_8994_MASK 0xf00000 -#define TSENS0_OFFSET_8994_SHIFT 20 -#define TSENS1_OFFSET_8994_MASK 0xf000000 -#define TSENS1_OFFSET_8994_SHIFT 24 -#define TSENS2_OFFSET_8994_MASK 0xf0000000 -#define TSENS2_OFFSET_8994_SHIFT 28 -#define TSENS3_OFFSET_8994_MASK 0xf -#define TSENS4_OFFSET_8994_MASK 0xf0 -#define TSENS4_OFFSET_8994_SHIFT 4 -#define TSENS5_OFFSET_8994_MASK 0xf00 -#define TSENS5_OFFSET_8994_SHIFT 8 -#define TSENS6_OFFSET_8994_MASK 0xf000 -#define TSENS6_OFFSET_8994_SHIFT 12 -#define TSENS7_OFFSET_8994_MASK 0xf0000 -#define TSENS7_OFFSET_8994_SHIFT 16 -#define TSENS8_OFFSET_8994_MASK 0xf00000 -#define TSENS8_OFFSET_8994_SHIFT 20 -#define TSENS9_OFFSET_8994_MASK 0xf000000 -#define TSENS9_OFFSET_8994_SHIFT 24 -#define TSENS10_OFFSET_8994_MASK 0xf0000000 -#define TSENS10_OFFSET_8994_SHIFT 28 -#define TSENS11_OFFSET_8994_MASK 0xf -#define TSENS12_OFFSET_8994_MASK 0xf0 -#define TSENS12_OFFSET_8994_SHIFT 4 -#define TSENS13_OFFSET_8994_MASK 0xf00 -#define TSENS13_OFFSET_8994_SHIFT 8 -#define TSENS14_OFFSET_8994_MASK 0xf000 -#define TSENS14_OFFSET_8994_SHIFT 12 -#define TSENS15_OFFSET_8994_MASK 0xf0000 -#define TSENS15_OFFSET_8994_SHIFT 16 -#define TSENS_8994_CAL_SEL_MASK 0x700000 -#define TSENS_8994_CAL_SEL_SHIFT 20 - -#define TSENS_BASE0_8994_REDUN_MASK 0x7fe00000 -#define TSENS_BASE0_8994_REDUN_MASK_SHIFT 21 -#define TSENS_BASE1_BIT0_8994_REDUN_MASK 0x80000000 -#define TSENS_BASE1_BIT0_SHIFT_COMPUTE 31 -#define TSENS_BASE1_BIT1_9_8994_REDUN_MASK 0x1ff -#define TSENS0_OFFSET_8994_REDUN_MASK 0x1e00 -#define TSENS0_OFFSET_8994_REDUN_SHIFT 9 -#define TSENS1_OFFSET_8994_REDUN_MASK 0x1e000 -#define TSENS1_OFFSET_8994_REDUN_SHIFT 13 -#define TSENS2_OFFSET_8994_REDUN_MASK 0x1e0000 -#define TSENS2_OFFSET_8994_REDUN_SHIFT 17 -#define TSENS3_OFFSET_8994_REDUN_MASK 0x1e00000 -#define TSENS3_OFFSET_8994_REDUN_SHIFT 21 -#define TSENS4_OFFSET_8994_REDUN_MASK 0x1e000000 -#define TSENS4_OFFSET_8994_REDUN_SHIFT 25 -#define TSENS5_OFFSET_8994_REDUN_MASK_BIT0_2 0xe0000000 -#define TSENS5_OFFSET_8994_REDUN_SHIFT_BIT0_2 29 -#define TSENS5_OFFSET_8994_REDUN_MASK_BIT3 0x800000 -#define TSENS5_OFFSET_8994_REDUN_SHIFT_BIT3 23 -#define TSENS6_OFFSET_8994_REDUN_MASK 0xf000000 -#define TSENS6_OFFSET_8994_REDUN_SHIFT 24 -#define TSENS7_OFFSET_8994_REDUN_MASK 0xf0000000 -#define TSENS7_OFFSET_8994_REDUN_SHIFT 28 -#define TSENS8_OFFSET_8994_REDUN_MASK 0xf -#define TSENS9_OFFSET_8994_REDUN_MASK 0xf0 -#define TSENS9_OFFSET_8994_REDUN_SHIFT 4 -#define TSENS10_OFFSET_8994_REDUN_MASK 0xf00 -#define TSENS10_OFFSET_8994_REDUN_SHIFT 8 -#define TSENS11_OFFSET_8994_REDUN_MASK 0xf000 -#define TSENS11_OFFSET_8994_REDUN_SHIFT 12 -#define TSENS12_OFFSET_8994_REDUN_MASK 0xf0000 -#define TSENS12_OFFSET_8994_REDUN_SHIFT 16 -#define TSENS13_OFFSET_8994_REDUN_MASK 0xf00000 -#define TSENS13_OFFSET_8994_REDUN_SHIFT 20 -#define TSENS14_OFFSET_8994_REDUN_MASK 0xf000000 -#define TSENS14_OFFSET_8994_REDUN_SHIFT 24 -#define TSENS15_OFFSET_8994_REDUN_MASK 0xf0000000 -#define TSENS15_OFFSET_8994_REDUN_SHIFT 28 -#define TSENS_8994_REDUN_SEL_MASK 0x7 -#define TSENS_8994_CAL_SEL_REDUN_MASK 0xe0000000 -#define TSENS_8994_CAL_SEL_REDUN_SHIFT 29 - -#define TSENS_MSM8909_BASE0_MASK 0x000000ff -#define TSENS_MSM8909_BASE1_MASK 0x0000ff00 - -#define TSENS0_MSM8909_POINT1_MASK 0x0000003f -#define TSENS1_MSM8909_POINT1_MASK 0x0003f000 -#define TSENS2_MSM8909_POINT1_MASK 0x3f000000 -#define TSENS3_MSM8909_POINT1_MASK 0x000003f0 -#define TSENS4_MSM8909_POINT1_MASK 0x003f0000 - -#define TSENS0_MSM8909_POINT2_MASK 0x00000fc0 -#define TSENS1_MSM8909_POINT2_MASK 0x00fc0000 -#define TSENS2_MSM8909_POINT2_MASK_0_1 0xc0000000 -#define TSENS2_MSM8909_POINT2_MASK_2_5 0x0000000f -#define TSENS3_MSM8909_POINT2_MASK 0x0000fc00 -#define TSENS4_MSM8909_POINT2_MASK 0x0fc00000 - -#define TSENS_MSM8909_TSENS_CAL_SEL 0x00070000 -#define TSENS_MSM8909_CAL_SEL_SHIFT 16 -#define TSENS_MSM8909_BASE1_SHIFT 8 - -#define TSENS1_MSM8909_POINT1_SHIFT 12 -#define TSENS2_MSM8909_POINT1_SHIFT 24 -#define TSENS3_MSM8909_POINT1_SHIFT 4 -#define TSENS4_MSM8909_POINT1_SHIFT 16 - -#define TSENS0_MSM8909_POINT2_SHIFT 6 -#define TSENS1_MSM8909_POINT2_SHIFT 18 -#define TSENS2_MSM8909_POINT2_SHIFT_0_1 30 -#define TSENS2_MSM8909_POINT2_SHIFT_2_5 2 -#define TSENS3_MSM8909_POINT2_SHIFT 10 -#define TSENS4_MSM8909_POINT2_SHIFT 22 - -#define TSENS_ZIRC_CAL_SEL 0x700 -#define TSENS_ZIRC_CAL_SEL_SHIFT 8 -#define TSENS_BASE0_ZIRC_MASK 0x3ff -#define TSENS_BASE1_ZIRC_MASK 0xffc00 -#define TSENS_BASE1_ZIRC_SHIFT 10 -#define TSENS0_OFFSET_ZIRC_MASK 0xf00000 -#define TSENS0_OFFSET_ZIRC_SHIFT 20 -#define TSENS1_OFFSET_ZIRC_MASK 0xf000000 -#define TSENS1_OFFSET_ZIRC_SHIFT 24 -#define TSENS2_OFFSET_ZIRC_MASK 0xf0000000 -#define TSENS2_OFFSET_ZIRC_SHIFT 28 -#define TSENS3_OFFSET_ZIRC_MASK 0xf -#define TSENS4_OFFSET_ZIRC_MASK 0xf0 -#define TSENS4_OFFSET_ZIRC_SHIFT 4 - -#define TSENS_CONTR_14_BASE0_MASK 0x000000ff -#define TSENS_CONTR_14_BASE1_MASK 0xff000000 - -#define TSENS0_CONTR_14_POINT1_MASK 0x000001f8 -#define TSENS1_CONTR_14_POINT1_MASK 0x001f8000 -#define TSENS2_CONTR_14_POINT1_MASK_0_4 0xf8000000 -#define TSENS2_CONTR_14_POINT1_MASK_5 0x00000001 -#define TSENS3_CONTR_14_POINT1_MASK 0x00001f80 -#define TSENS4_CONTR_14_POINT1_MASK 0x01f80000 -#define TSENS5_CONTR_14_POINT1_MASK 0x00003f00 -#define TSENS6_CONTR_14_POINT1_MASK 0x03f00000 -#define TSENS7_CONTR_14_POINT1_MASK 0x0000003f -#define TSENS8_CONTR_14_POINT1_MASK 0x0003f000 -#define TSENS9_CONTR_14_POINT1_MASK 0x0000003f -#define TSENS10_CONTR_14_POINT1_MASK 0x0003f000 - -#define TSENS0_CONTR_14_POINT2_MASK 0x00007e00 -#define TSENS1_CONTR_14_POINT2_MASK 0x07e00000 -#define TSENS2_CONTR_14_POINT2_MASK 0x0000007e -#define TSENS3_CONTR_14_POINT2_MASK 0x0007e000 -#define TSENS4_CONTR_14_POINT2_MASK 0x7e000000 -#define TSENS5_CONTR_14_POINT2_MASK 0x000fc000 -#define TSENS6_CONTR_14_POINT2_MASK 0xfc000000 -#define TSENS7_CONTR_14_POINT2_MASK 0x00000fc0 -#define TSENS8_CONTR_14_POINT2_MASK 0x00fc0000 -#define TSENS9_CONTR_14_POINT2_MASK 0x00000fc0 -#define TSENS10_CONTR_14_POINT2_MASK 0x00fc0000 - -#define TSENS_CONTR_14_TSENS_CAL_SEL 0x00000007 -#define TSENS_CONTR_14_BASE1_SHIFT 24 - -#define TSENS0_CONTR_14_POINT1_SHIFT 3 -#define TSENS1_CONTR_14_POINT1_SHIFT 15 -#define TSENS2_CONTR_14_POINT1_SHIFT_0_4 27 -#define TSENS2_CONTR_14_POINT1_SHIFT_5 5 -#define TSENS3_CONTR_14_POINT1_SHIFT 7 -#define TSENS4_CONTR_14_POINT1_SHIFT 19 -#define TSENS5_CONTR_14_POINT1_SHIFT 8 -#define TSENS6_CONTR_14_POINT1_SHIFT 20 -#define TSENS8_CONTR_14_POINT1_SHIFT 12 -#define TSENS10_CONTR_14_POINT1_SHIFT 12 - -#define TSENS0_CONTR_14_POINT2_SHIFT 9 -#define TSENS1_CONTR_14_POINT2_SHIFT 21 -#define TSENS2_CONTR_14_POINT2_SHIFT 1 -#define TSENS3_CONTR_14_POINT2_SHIFT 13 -#define TSENS4_CONTR_14_POINT2_SHIFT 25 -#define TSENS5_CONTR_14_POINT2_SHIFT 14 -#define TSENS6_CONTR_14_POINT2_SHIFT 26 -#define TSENS7_CONTR_14_POINT2_SHIFT 6 -#define TSENS8_CONTR_14_POINT2_SHIFT 18 -#define TSENS9_CONTR_14_POINT2_SHIFT 6 -#define TSENS10_CONTR_14_POINT2_SHIFT 18 - -#define TSENS_TWO_POINT_CALIB_N_WA 0x6 -#define TSENS_TWO_POINT_CALIB_N_OFFSET_WA 0x7 - -#define TSENS_MSM8952_D30_WA_S0 2 -#define TSENS_MSM8952_D30_WA_S1 4 -#define TSENS_MSM8952_D30_WA_S2 4 -#define TSENS_MSM8952_D30_WA_S3 1 -#define TSENS_MSM8952_D30_WA_S4 2 -#define TSENS_MSM8952_D30_WA_S5 1 -#define TSENS_MSM8952_D30_WA_S7 3 -#define TSENS_MSM8952_D30_WA_S8 2 -#define TSENS_MSM8952_D30_WA_S10 3 - -#define TSENS_MSM8952_D120_WA_S0 1 -#define TSENS_MSM8952_D120_WA_S1 4 -#define TSENS_MSM8952_D120_WA_S2 5 -#define TSENS_MSM8952_D120_WA_S3 1 -#define TSENS_MSM8952_D120_WA_S4 3 -#define TSENS_MSM8952_D120_WA_S5 1 -#define TSENS_MSM8952_D120_WA_S6 1 -#define TSENS_MSM8952_D120_WA_S7 4 -#define TSENS_MSM8952_D120_WA_S8 4 -#define TSENS_MSM8952_D120_WA_S10 2 - -#define TSENS_NO_CALIB_POINT1_DATA 500 -#define TSENS_NO_CALIB_POINT2_DATA 780 - -#define TSENS_MDM9607_TSENS_CAL_SEL 0x00700000 -#define TSENS_MDM9607_CAL_SEL_SHIFT 20 -#define TSENS_MDM9607_BASE1_SHIFT 12 - -#define TSENS_MDM9607_BASE0_MASK 0x000000ff -#define TSENS_MDM9607_BASE1_MASK 0x000ff000 - -#define TSENS0_MDM9607_POINT1_MASK 0x00003f00 -#define TSENS1_MDM9607_POINT1_MASK 0x03f00000 -#define TSENS2_MDM9607_POINT1_MASK 0x0000003f -#define TSENS3_MDM9607_POINT1_MASK 0x0003f000 -#define TSENS4_MDM9607_POINT1_MASK 0x0000003f - -#define TSENS0_MDM9607_POINT2_MASK 0x000fc000 -#define TSENS1_MDM9607_POINT2_MASK 0xfc000000 -#define TSENS2_MDM9607_POINT2_MASK 0x00000fc0 -#define TSENS3_MDM9607_POINT2_MASK 0x00fc0000 -#define TSENS4_MDM9607_POINT2_MASK 0x0000fc00 - -#define TSENS0_MDM9607_POINT1_SHIFT 8 -#define TSENS1_MDM9607_POINT1_SHIFT 20 -#define TSENS3_MDM9607_POINT1_SHIFT 12 - -#define TSENS0_MDM9607_POINT2_SHIFT 14 -#define TSENS1_MDM9607_POINT2_SHIFT 26 -#define TSENS2_MDM9607_POINT2_SHIFT 6 -#define TSENS3_MDM9607_POINT2_SHIFT 18 -#define TSENS4_MDM9607_POINT2_SHIFT 6 - /* debug defines */ #define TSENS_DBG_BUS_ID_0 0 #define TSENS_DBG_BUS_ID_1 1 @@ -721,10 +170,8 @@ #define TSENS_DEBUG_OFFSET_WORD3 0xc #define TSENS_DEBUG_OFFSET_ROW 0x10 #define TSENS_DEBUG_DECIDEGC -950 -#define TSENS_DEBUG_MIN_CYCLE 63000 -#define TSENS_DEBUG_MAX_CYCLE 64000 -#define TSENS_DEBUG_POLL_MIN 200000 -#define TSENS_DEBUG_POLL_MAX 210000 +#define TSENS_DEBUG_CYCLE_MS 64 +#define TSENS_DEBUG_POLL_MS 200 #define TSENS_DEBUG_BUS_ID2_MIN_CYCLE 50 #define TSENS_DEBUG_BUS_ID2_MAX_CYCLE 51 #define TSENS_DEBUG_ID_MASK_1_4 0xffffffe1 @@ -733,26 +180,6 @@ static uint32_t tsens_sec_to_msec_value = 1000; static uint32_t tsens_completion_timeout_hz = HZ/2; static uint32_t tsens_poll_check = 1; -enum tsens_calib_fuse_map_type { - TSENS_CALIB_FUSE_MAP_8974 = 0, - TSENS_CALIB_FUSE_MAP_8X26, - TSENS_CALIB_FUSE_MAP_8X10, - TSENS_CALIB_FUSE_MAP_9900, - TSENS_CALIB_FUSE_MAP_9630, - TSENS_CALIB_FUSE_MAP_8916, - TSENS_CALIB_FUSE_MAP_8939, - TSENS_CALIB_FUSE_MAP_8994, - TSENS_CALIB_FUSE_MAP_MSM8909, - TSENS_CALIB_FUSE_MAP_MSMZIRC, - TSENS_CALIB_FUSE_MAP_NONE, - TSENS_CALIB_FUSE_MAP_8992, - TSENS_CALIB_FUSE_MAP_MSM8952, - TSENS_CALIB_FUSE_MAP_MDM9607, - TSENS_CALIB_FUSE_MAP_MSM8937, - TSENS_CALIB_FUSE_MAP_MSMGOLD, - TSENS_CALIB_FUSE_MAP_NUM, -}; - /* Trips: warm and cool */ enum tsens_trip_type { TSENS_TRIP_WARM = 0, @@ -848,7 +275,6 @@ struct tsens_tm_device { int calib_len; struct resource *res_tsens_mem; struct resource *res_calib_mem; - uint32_t calib_mode; uint32_t tsens_type; bool tsens_valid_status_check; struct tsens_dbg_counter tsens_thread_iq_dbg; @@ -880,68 +306,17 @@ static struct dentry *dent; static struct dentry *dfile_stats; static struct of_device_id tsens_match[] = { - { .compatible = "qcom,msm-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_8974, - }, - { .compatible = "qcom,msm8x26-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_8X26, - }, - { .compatible = "qcom,msm8x10-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_8X10, - }, - { .compatible = "qcom,fsm9900-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_9900, - }, - { .compatible = "qcom,mdm9630-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_9630, - }, - { .compatible = "qcom,msm8916-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_8916, - }, - { .compatible = "qcom,msm8939-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_8939, - }, - { .compatible = "qcom,msm8994-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_8994, - }, - { .compatible = "qcom,msm8909-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_MSM8909, - }, - { .compatible = "qcom,msmzirc-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_MSMZIRC, - }, { .compatible = "qcom,msm8996-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_NONE, - }, - { .compatible = "qcom,msm8992-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_8992, - }, - { .compatible = "qcom,msm8952-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_MSM8952, - }, - { .compatible = "qcom,mdm9607-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_MDM9607, }, { .compatible = "qcom,msmtitanium-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_NONE, - }, - { .compatible = "qcom,msm8937-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_MSM8937, - }, - { .compatible = "qcom,msmgold-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_MSMGOLD, }, { .compatible = "qcom,msm8998-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_NONE, }, { .compatible = "qcom,msmhamster-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_NONE, }, - { .compatible = "qcom,msmfalcon-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_NONE, + { .compatible = "qcom,sdm660-tsens", }, - { .compatible = "qcom,msmtriton-tsens", - .data = (void *)TSENS_CALIB_FUSE_MAP_NONE, + { .compatible = "qcom,sdm630-tsens", }, {} }; @@ -2035,8 +1410,7 @@ static void tsens_poll(struct work_struct *work) spin_unlock_irqrestore(&tmdev->tsens_crit_lock, flags); if (tmdev->tsens_critical_poll) { - usleep_range(TSENS_DEBUG_POLL_MIN, - TSENS_DEBUG_POLL_MAX); + msleep(TSENS_DEBUG_POLL_MS); sensor_status_addr = TSENS_TM_SN_STATUS(tmdev->tsens_addr); spin_lock_irqsave(&tmdev->tsens_crit_lock, flags); @@ -2190,8 +1564,7 @@ debug_start: offset += TSENS_DEBUG_OFFSET_ROW; } loop++; - usleep_range(TSENS_DEBUG_MIN_CYCLE, - TSENS_DEBUG_MAX_CYCLE); + msleep(TSENS_DEBUG_CYCLE_MS); } BUG(); } @@ -2737,2639 +2110,6 @@ static int tsens_hw_init(struct tsens_tm_device *tmdev) return 0; } -static int tsens_calib_msm8937_msmgold_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base0_data = 0, tsens_base1_data = 0, ext_sen = 1; - int tsens0_point1 = 0, tsens0_point2 = 0; - int tsens1_point1 = 0, tsens1_point2 = 0; - int tsens2_point1 = 0, tsens2_point2 = 0; - int tsens3_point1 = 0, tsens3_point2 = 0; - int tsens4_point1 = 0, tsens4_point2 = 0; - int tsens5_point1 = 0, tsens5_point2 = 0; - int tsens6_point1 = 0, tsens6_point2 = 0; - int tsens7_point1 = 0, tsens7_point2 = 0; - int tsens8_point1 = 0, tsens8_point2 = 0; - int tsens9_point1 = 0, tsens9_point2 = 0; - int tsens10_point1 = 0, tsens10_point2 = 0; - - int tsens_calibration_mode = 0, temp = 0; - uint32_t calib_data[5] = {0, 0, 0, 0, 0}; - uint32_t calib_tsens_point1_data[11], calib_tsens_point2_data[11]; - - if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_MSMGOLD) - ext_sen = 0; - - if (!tmdev->calibration_less_mode) { - - calib_data[0] = readl_relaxed(tmdev->tsens_calib_addr + 0x1D8); - calib_data[1] = readl_relaxed(tmdev->tsens_calib_addr + 0x1DC); - calib_data[2] = readl_relaxed(tmdev->tsens_calib_addr + 0x210); - calib_data[3] = readl_relaxed(tmdev->tsens_calib_addr + 0x214); - calib_data[4] = readl_relaxed(tmdev->tsens_calib_addr + 0x230); - - tsens_calibration_mode = - (calib_data[2] & - TSENS_CONTR_14_TSENS_CAL_SEL); - - pr_debug("calib mode is %d\n", tsens_calibration_mode); - } - - if ((tsens_calibration_mode == TSENS_TWO_POINT_CALIB) || - (tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2)) { - tsens_base0_data = (calib_data[0] & - TSENS_CONTR_14_BASE0_MASK); - tsens0_point1 = (calib_data[2] & - TSENS0_CONTR_14_POINT1_MASK) - >> TSENS0_CONTR_14_POINT1_SHIFT; - tsens1_point1 = (calib_data[2] & - TSENS1_CONTR_14_POINT1_MASK) - >> TSENS1_CONTR_14_POINT1_SHIFT; - tsens2_point1 = (calib_data[2] & - TSENS2_CONTR_14_POINT1_MASK_0_4) - >> TSENS2_CONTR_14_POINT1_SHIFT_0_4; - temp = (calib_data[3] & TSENS2_CONTR_14_POINT1_MASK_5) - << TSENS2_CONTR_14_POINT1_SHIFT_5; - tsens2_point1 |= temp; - tsens3_point1 = (calib_data[3] & - TSENS3_CONTR_14_POINT1_MASK) - >> TSENS3_CONTR_14_POINT1_SHIFT; - tsens4_point1 = (calib_data[3] & - TSENS4_CONTR_14_POINT1_MASK) - >> TSENS4_CONTR_14_POINT1_SHIFT; - tsens5_point1 = (calib_data[0] & - TSENS5_CONTR_14_POINT1_MASK) - >> TSENS5_CONTR_14_POINT1_SHIFT; - tsens6_point1 = (calib_data[0] & - TSENS6_CONTR_14_POINT1_MASK) - >> TSENS6_CONTR_14_POINT1_SHIFT; - tsens7_point1 = (calib_data[1] & - TSENS7_CONTR_14_POINT1_MASK); - tsens8_point1 = (calib_data[1] & - TSENS8_CONTR_14_POINT1_MASK) - >> TSENS8_CONTR_14_POINT1_SHIFT; - tsens9_point1 = (calib_data[4] & - TSENS9_CONTR_14_POINT1_MASK); - if (ext_sen) - tsens10_point1 = (calib_data[4] & - TSENS10_CONTR_14_POINT1_MASK) - >> TSENS10_CONTR_14_POINT1_SHIFT; - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base1_data = (calib_data[1] & - TSENS_CONTR_14_BASE1_MASK) - >> TSENS_CONTR_14_BASE1_SHIFT; - tsens0_point2 = (calib_data[2] & - TSENS0_CONTR_14_POINT2_MASK) - >> TSENS0_CONTR_14_POINT2_SHIFT; - tsens1_point2 = (calib_data[2] & - TSENS1_CONTR_14_POINT2_MASK) - >> TSENS1_CONTR_14_POINT2_SHIFT; - tsens2_point2 = (calib_data[3] & - TSENS2_CONTR_14_POINT2_MASK) - >> TSENS2_CONTR_14_POINT2_SHIFT; - tsens3_point2 = (calib_data[3] & - TSENS3_CONTR_14_POINT2_MASK) - >> TSENS3_CONTR_14_POINT2_SHIFT; - tsens4_point2 = (calib_data[3] & - TSENS4_CONTR_14_POINT2_MASK) - >> TSENS4_CONTR_14_POINT2_SHIFT; - tsens5_point2 = (calib_data[0] & - TSENS5_CONTR_14_POINT2_MASK) - >> TSENS5_CONTR_14_POINT2_SHIFT; - tsens6_point2 = (calib_data[0] & - TSENS6_CONTR_14_POINT2_MASK) - >> TSENS6_CONTR_14_POINT2_SHIFT; - tsens7_point2 = (calib_data[1] & - TSENS7_CONTR_14_POINT2_MASK) - >> TSENS7_CONTR_14_POINT2_SHIFT; - tsens8_point2 = (calib_data[1] & - TSENS8_CONTR_14_POINT2_MASK) - >> TSENS8_CONTR_14_POINT2_SHIFT; - tsens9_point2 = (calib_data[4] & - TSENS9_CONTR_14_POINT2_MASK) - >> TSENS9_CONTR_14_POINT2_SHIFT; - if (ext_sen) - tsens10_point2 = (calib_data[4] & - TSENS10_CONTR_14_POINT2_MASK) - >> TSENS10_CONTR_14_POINT2_SHIFT; - } - - if (tsens_calibration_mode == 0) { - pr_debug("TSENS in calibrationless mode\n"); - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - calib_tsens_point2_data[i] = TSENS_NO_CALIB_POINT2_DATA; - calib_tsens_point1_data[i] = TSENS_NO_CALIB_POINT1_DATA; - } - } - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - calib_tsens_point1_data[0] = - (((tsens_base0_data) + tsens0_point1) << 2) + - tmdev->sensor[0].wa_temp1_calib_offset_factor; - calib_tsens_point1_data[1] = - (((tsens_base0_data) + tsens1_point1) << 2) + - tmdev->sensor[1].wa_temp1_calib_offset_factor; - calib_tsens_point1_data[2] = - (((tsens_base0_data) + tsens2_point1) << 2) + - tmdev->sensor[2].wa_temp1_calib_offset_factor; - calib_tsens_point1_data[3] = - (((tsens_base0_data) + tsens3_point1) << 2) + - tmdev->sensor[3].wa_temp1_calib_offset_factor; - calib_tsens_point1_data[4] = - (((tsens_base0_data) + tsens4_point1) << 2) + - tmdev->sensor[4].wa_temp1_calib_offset_factor; - calib_tsens_point1_data[5] = - (((tsens_base0_data) + tsens5_point1) << 2) + - tmdev->sensor[5].wa_temp1_calib_offset_factor; - calib_tsens_point1_data[6] = - (((tsens_base0_data) + tsens6_point1) << 2) + - tmdev->sensor[6].wa_temp1_calib_offset_factor; - calib_tsens_point1_data[7] = - (((tsens_base0_data) + tsens7_point1) << 2) + - tmdev->sensor[7].wa_temp1_calib_offset_factor; - calib_tsens_point1_data[8] = - (((tsens_base0_data) + tsens8_point1) << 2) + - tmdev->sensor[8].wa_temp1_calib_offset_factor; - calib_tsens_point1_data[9] = - (((tsens_base0_data) + tsens9_point1) << 2) + - tmdev->sensor[9].wa_temp1_calib_offset_factor; - if (ext_sen) - calib_tsens_point1_data[10] = - (((tsens_base0_data) + tsens10_point1) << 2) + - tmdev->sensor[10].wa_temp1_calib_offset_factor; - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - pr_debug("two point calibration calculation\n"); - calib_tsens_point2_data[0] = - ((tsens_base1_data + tsens0_point2) << 2) + - tmdev->sensor[0].wa_temp2_calib_offset_factor; - calib_tsens_point2_data[1] = - ((tsens_base1_data + tsens1_point2) << 2) + - tmdev->sensor[1].wa_temp2_calib_offset_factor; - calib_tsens_point2_data[2] = - ((tsens_base1_data + tsens2_point2) << 2) + - tmdev->sensor[2].wa_temp2_calib_offset_factor; - calib_tsens_point2_data[3] = - ((tsens_base1_data + tsens3_point2) << 2) + - tmdev->sensor[3].wa_temp2_calib_offset_factor; - calib_tsens_point2_data[4] = - ((tsens_base1_data + tsens4_point2) << 2) + - tmdev->sensor[4].wa_temp2_calib_offset_factor; - calib_tsens_point2_data[5] = - ((tsens_base1_data + tsens5_point2) << 2) + - tmdev->sensor[5].wa_temp2_calib_offset_factor; - calib_tsens_point2_data[6] = - ((tsens_base1_data + tsens6_point2) << 2) + - tmdev->sensor[6].wa_temp2_calib_offset_factor; - calib_tsens_point2_data[7] = - ((tsens_base1_data + tsens7_point2) << 2) + - tmdev->sensor[7].wa_temp2_calib_offset_factor; - calib_tsens_point2_data[8] = - ((tsens_base1_data + tsens8_point2) << 2) + - tmdev->sensor[8].wa_temp2_calib_offset_factor; - calib_tsens_point2_data[9] = - ((tsens_base1_data + tsens9_point2) << 2) + - tmdev->sensor[9].wa_temp2_calib_offset_factor; - if (ext_sen) - calib_tsens_point2_data[10] = - ((tsens_base1_data + tsens10_point2) << 2) + - tmdev->sensor[10].wa_temp2_calib_offset_factor; - } - - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0; - - tmdev->sensor[i].calib_data_point2 = calib_tsens_point2_data[i]; - tmdev->sensor[i].calib_data_point1 = calib_tsens_point1_data[i]; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* - * slope (m) = adc_code2 - adc_code1 (y2 - y1) - * temp_120_degc - temp_30_degc (x2 - x1) - */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - tmdev->sensor[i].offset = (tmdev->sensor[i].calib_data_point1 * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d and slope:%d\n", tmdev->sensor[i].offset, - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - return 0; -} - -static int tsens_calib_mdm9607_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base0_data = 0, tsens_base1_data = 0; - int tsens0_point1 = 0, tsens0_point2 = 0; - int tsens1_point1 = 0, tsens1_point2 = 0; - int tsens2_point1 = 0, tsens2_point2 = 0; - int tsens3_point1 = 0, tsens3_point2 = 0; - int tsens4_point1 = 0, tsens4_point2 = 0; - int tsens_calibration_mode = 0; - uint32_t calib_data[3] = {0, 0, 0}; - uint32_t calib_tsens_point1_data[5], calib_tsens_point2_data[5]; - - if (!tmdev->calibration_less_mode) { - calib_data[0] = readl_relaxed(tmdev->tsens_calib_addr + 0x228); - calib_data[1] = readl_relaxed(tmdev->tsens_calib_addr + 0x22c); - calib_data[2] = readl_relaxed(tmdev->tsens_calib_addr + 0x230); - - tsens_calibration_mode = - (calib_data[2] & TSENS_MDM9607_TSENS_CAL_SEL) >> - TSENS_MDM9607_CAL_SEL_SHIFT; - - pr_debug("calib mode is %d\n", tsens_calibration_mode); - } - - if ((tsens_calibration_mode == TSENS_TWO_POINT_CALIB) || - (tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2)) { - tsens_base0_data = - (calib_data[0] & TSENS_MDM9607_BASE0_MASK); - tsens0_point1 = (calib_data[0] & TSENS0_MDM9607_POINT1_MASK) - >> TSENS0_MDM9607_POINT1_SHIFT; - tsens1_point1 = (calib_data[0] & TSENS1_MDM9607_POINT1_MASK) - >> TSENS1_MDM9607_POINT1_SHIFT; - tsens2_point1 = (calib_data[1] & TSENS2_MDM9607_POINT1_MASK); - tsens3_point1 = (calib_data[1] & TSENS3_MDM9607_POINT1_MASK) - >> TSENS3_MDM9607_POINT1_SHIFT; - tsens4_point1 = (calib_data[2] & TSENS4_MDM9607_POINT1_MASK); - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base1_data = (calib_data[2] & TSENS_MDM9607_BASE1_MASK) - >> TSENS_MDM9607_BASE1_SHIFT; - tsens0_point2 = (calib_data[0] & TSENS0_MDM9607_POINT2_MASK) - >> TSENS0_MDM9607_POINT2_SHIFT; - tsens1_point2 = (calib_data[0] & TSENS1_MDM9607_POINT2_MASK) - >> TSENS1_MDM9607_POINT2_SHIFT; - tsens2_point2 = (calib_data[1] & TSENS2_MDM9607_POINT2_MASK) - >> TSENS2_MDM9607_POINT2_SHIFT; - tsens3_point2 = (calib_data[1] & TSENS3_MDM9607_POINT2_MASK) - >> TSENS3_MDM9607_POINT2_SHIFT; - tsens4_point2 = (calib_data[2] & TSENS4_MDM9607_POINT2_MASK) - >> TSENS4_MDM9607_POINT2_SHIFT; - } - - if (tsens_calibration_mode == 0) { - pr_debug("TSENS in calibrationless mode\n"); - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - calib_tsens_point2_data[i] = TSENS_NO_CALIB_POINT2_DATA; - calib_tsens_point1_data[i] = TSENS_NO_CALIB_POINT1_DATA; - } - } - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - calib_tsens_point1_data[0] = - (((tsens_base0_data) + tsens0_point1) << 2); - calib_tsens_point1_data[1] = - (((tsens_base0_data) + tsens1_point1) << 2); - calib_tsens_point1_data[2] = - (((tsens_base0_data) + tsens2_point1) << 2); - calib_tsens_point1_data[3] = - (((tsens_base0_data) + tsens3_point1) << 2); - calib_tsens_point1_data[4] = - (((tsens_base0_data) + tsens4_point1) << 2); - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - pr_debug("two point calibration calculation\n"); - calib_tsens_point2_data[0] = - ((tsens_base1_data + tsens0_point2) << 2); - calib_tsens_point2_data[1] = - ((tsens_base1_data + tsens1_point2) << 2); - calib_tsens_point2_data[2] = - ((tsens_base1_data + tsens2_point2) << 2); - calib_tsens_point2_data[3] = - ((tsens_base1_data + tsens3_point2) << 2); - calib_tsens_point2_data[4] = - ((tsens_base1_data + tsens4_point2) << 2); - } - - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0; - - tmdev->sensor[i].calib_data_point2 = calib_tsens_point2_data[i]; - tmdev->sensor[i].calib_data_point1 = calib_tsens_point1_data[i]; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* - * slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - * temp_120_degc - temp_30_degc (x2 - x1) - */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - tmdev->sensor[i].offset = (tmdev->sensor[i].calib_data_point1 * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d and slope:%d\n", tmdev->sensor[i].offset, - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - - return 0; -} - -static int tsens_calib_msm8952_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base0_data = 0, tsens_base1_data = 0; - int tsens0_point1 = 0, tsens0_point2 = 0; - int tsens1_point1 = 0, tsens1_point2 = 0; - int tsens2_point1 = 0, tsens2_point2 = 0; - int tsens3_point1 = 0, tsens3_point2 = 0; - int tsens4_point1 = 0, tsens4_point2 = 0; - int tsens5_point1 = 0, tsens5_point2 = 0; - int tsens6_point1 = 0, tsens6_point2 = 0; - int tsens7_point1 = 0, tsens7_point2 = 0; - int tsens8_point1 = 0, tsens8_point2 = 0; - int tsens9_point1 = 0, tsens9_point2 = 0; - int tsens10_point1 = 0, tsens10_point2 = 0; - - int tsens_calibration_mode = 0, temp = 0; - uint32_t calib_data[5] = {0, 0, 0, 0, 0}; - uint32_t calib_tsens_point1_data[11], calib_tsens_point2_data[11]; - - if (!tmdev->calibration_less_mode) { - calib_data[0] = readl_relaxed( - TSENS_8939_EEPROM - (tmdev->tsens_calib_addr) + 0x30); - calib_data[1] = readl_relaxed( - (TSENS_8939_EEPROM - (tmdev->tsens_calib_addr) + 0x34)); - calib_data[2] = readl_relaxed( - (TSENS_8939_EEPROM - (tmdev->tsens_calib_addr))); - calib_data[3] = readl_relaxed( - (TSENS_8939_EEPROM - (tmdev->tsens_calib_addr) + 0x4)); - calib_data[4] = readl_relaxed( - (TSENS_8939_EEPROM - (tmdev->tsens_calib_addr) + 0x50)); - - tsens_calibration_mode = - (calib_data[0] & - TSENS_CONTR_14_TSENS_CAL_SEL); - - pr_debug("calib mode is %d\n", tsens_calibration_mode); - } - - if ((tsens_calibration_mode == TSENS_TWO_POINT_CALIB) || - (tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2)) { - tsens_base0_data = (calib_data[2] & - TSENS_CONTR_14_BASE0_MASK); - tsens0_point1 = (calib_data[0] & - TSENS0_CONTR_14_POINT1_MASK) - >> TSENS0_CONTR_14_POINT1_SHIFT; - tsens1_point1 = (calib_data[0] & - TSENS1_CONTR_14_POINT1_MASK) - >> TSENS1_CONTR_14_POINT1_SHIFT; - tsens2_point1 = (calib_data[0] & - TSENS2_CONTR_14_POINT1_MASK_0_4) - >> TSENS2_CONTR_14_POINT1_SHIFT_0_4; - temp = (calib_data[1] & TSENS2_CONTR_14_POINT1_MASK_5) - << TSENS2_CONTR_14_POINT1_SHIFT_5; - tsens2_point1 |= temp; - tsens3_point1 = (calib_data[1] & - TSENS3_CONTR_14_POINT1_MASK) - >> TSENS3_CONTR_14_POINT1_SHIFT; - tsens4_point1 = (calib_data[1] & - TSENS4_CONTR_14_POINT1_MASK) - >> TSENS4_CONTR_14_POINT1_SHIFT; - tsens5_point1 = (calib_data[2] & - TSENS5_CONTR_14_POINT1_MASK) - >> TSENS5_CONTR_14_POINT1_SHIFT; - tsens6_point1 = (calib_data[2] & - TSENS6_CONTR_14_POINT1_MASK) - >> TSENS6_CONTR_14_POINT1_SHIFT; - tsens7_point1 = (calib_data[3] & - TSENS7_CONTR_14_POINT1_MASK); - tsens8_point1 = (calib_data[3] & - TSENS8_CONTR_14_POINT1_MASK) - >> TSENS8_CONTR_14_POINT1_SHIFT; - tsens9_point1 = (calib_data[4] & - TSENS9_CONTR_14_POINT1_MASK); - tsens10_point1 = (calib_data[4] & - TSENS10_CONTR_14_POINT1_MASK) - >> TSENS10_CONTR_14_POINT1_SHIFT; - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base1_data = (calib_data[3] & - TSENS_CONTR_14_BASE1_MASK) - >> TSENS_CONTR_14_BASE1_SHIFT; - tsens0_point2 = (calib_data[0] & - TSENS0_CONTR_14_POINT2_MASK) - >> TSENS0_CONTR_14_POINT2_SHIFT; - tsens1_point2 = (calib_data[0] & - TSENS1_CONTR_14_POINT2_MASK) - >> TSENS1_CONTR_14_POINT2_SHIFT; - tsens2_point2 = (calib_data[1] & - TSENS2_CONTR_14_POINT2_MASK) - >> TSENS2_CONTR_14_POINT2_SHIFT; - tsens3_point2 = (calib_data[1] & - TSENS3_CONTR_14_POINT2_MASK) - >> TSENS3_CONTR_14_POINT2_SHIFT; - tsens4_point2 = (calib_data[1] & - TSENS4_CONTR_14_POINT2_MASK) - >> TSENS4_CONTR_14_POINT2_SHIFT; - tsens5_point2 = (calib_data[2] & - TSENS5_CONTR_14_POINT2_MASK) - >> TSENS5_CONTR_14_POINT2_SHIFT; - tsens6_point2 = (calib_data[2] & - TSENS6_CONTR_14_POINT2_MASK) - >> TSENS6_CONTR_14_POINT2_SHIFT; - tsens7_point2 = (calib_data[3] & - TSENS7_CONTR_14_POINT2_MASK) - >> TSENS7_CONTR_14_POINT2_SHIFT; - tsens8_point2 = (calib_data[3] & - TSENS8_CONTR_14_POINT2_MASK) - >> TSENS8_CONTR_14_POINT2_SHIFT; - tsens9_point2 = (calib_data[4] & - TSENS9_CONTR_14_POINT2_MASK) - >> TSENS9_CONTR_14_POINT2_SHIFT; - tsens10_point2 = (calib_data[4] & - TSENS10_CONTR_14_POINT2_MASK) - >> TSENS10_CONTR_14_POINT2_SHIFT; - } - - if (tsens_calibration_mode == 0) { - pr_debug("TSENS in calibrationless mode\n"); - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - calib_tsens_point2_data[i] = TSENS_NO_CALIB_POINT2_DATA; - calib_tsens_point1_data[i] = TSENS_NO_CALIB_POINT1_DATA; - } - } - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - calib_tsens_point1_data[0] = - (((tsens_base0_data) + tsens0_point1) << 2); - calib_tsens_point1_data[0] = calib_tsens_point1_data[0] + - TSENS_MSM8952_D30_WA_S0; - calib_tsens_point1_data[1] = - (((tsens_base0_data) + tsens1_point1) << 2); - calib_tsens_point1_data[1] = calib_tsens_point1_data[1] - - TSENS_MSM8952_D30_WA_S1; - calib_tsens_point1_data[2] = - (((tsens_base0_data) + tsens2_point1) << 2); - calib_tsens_point1_data[2] = calib_tsens_point1_data[2] + - TSENS_MSM8952_D30_WA_S2; - calib_tsens_point1_data[3] = - (((tsens_base0_data) + tsens3_point1) << 2); - calib_tsens_point1_data[3] = calib_tsens_point1_data[3] + - TSENS_MSM8952_D30_WA_S3; - calib_tsens_point1_data[4] = - (((tsens_base0_data) + tsens4_point1) << 2); - calib_tsens_point1_data[4] = calib_tsens_point1_data[4] + - TSENS_MSM8952_D30_WA_S4; - calib_tsens_point1_data[5] = - (((tsens_base0_data) + tsens5_point1) << 2); - calib_tsens_point1_data[5] = calib_tsens_point1_data[5] - - TSENS_MSM8952_D30_WA_S5; - calib_tsens_point1_data[6] = - (((tsens_base0_data) + tsens6_point1) << 2); - calib_tsens_point1_data[7] = - (((tsens_base0_data) + tsens7_point1) << 2); - calib_tsens_point1_data[7] = calib_tsens_point1_data[7] + - TSENS_MSM8952_D30_WA_S7; - calib_tsens_point1_data[8] = - (((tsens_base0_data) + tsens8_point1) << 2); - calib_tsens_point1_data[8] = calib_tsens_point1_data[8] + - TSENS_MSM8952_D30_WA_S8; - calib_tsens_point1_data[9] = - (((tsens_base0_data) + tsens9_point1) << 2); - calib_tsens_point1_data[10] = - (((tsens_base0_data) + tsens10_point1) << 2); - calib_tsens_point1_data[10] = calib_tsens_point1_data[10] - - TSENS_MSM8952_D30_WA_S10; - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - pr_debug("two point calibration calculation\n"); - calib_tsens_point2_data[0] = - ((tsens_base1_data + tsens0_point2) << 2); - calib_tsens_point1_data[0] = calib_tsens_point1_data[0] - - TSENS_MSM8952_D120_WA_S0; - calib_tsens_point2_data[1] = - ((tsens_base1_data + tsens1_point2) << 2); - calib_tsens_point1_data[1] = calib_tsens_point1_data[1] - - TSENS_MSM8952_D120_WA_S1; - calib_tsens_point2_data[2] = - ((tsens_base1_data + tsens2_point2) << 2); - calib_tsens_point1_data[2] = calib_tsens_point1_data[2] + - TSENS_MSM8952_D120_WA_S2; - calib_tsens_point2_data[3] = - ((tsens_base1_data + tsens3_point2) << 2); - calib_tsens_point1_data[3] = calib_tsens_point1_data[3] + - TSENS_MSM8952_D120_WA_S3; - calib_tsens_point2_data[4] = - ((tsens_base1_data + tsens4_point2) << 2); - calib_tsens_point1_data[4] = calib_tsens_point1_data[4] + - TSENS_MSM8952_D120_WA_S4; - calib_tsens_point2_data[5] = - ((tsens_base1_data + tsens5_point2) << 2); - calib_tsens_point1_data[5] = calib_tsens_point1_data[5] - - TSENS_MSM8952_D120_WA_S5; - calib_tsens_point2_data[6] = - ((tsens_base1_data + tsens6_point2) << 2); - calib_tsens_point1_data[6] = calib_tsens_point1_data[6] - - TSENS_MSM8952_D120_WA_S6; - calib_tsens_point2_data[7] = - ((tsens_base1_data + tsens7_point2) << 2); - calib_tsens_point1_data[7] = calib_tsens_point1_data[7] + - TSENS_MSM8952_D120_WA_S7; - calib_tsens_point2_data[8] = - ((tsens_base1_data + tsens8_point2) << 2); - calib_tsens_point1_data[8] = calib_tsens_point1_data[8] + - TSENS_MSM8952_D120_WA_S8; - calib_tsens_point2_data[9] = - ((tsens_base1_data + tsens9_point2) << 2); - calib_tsens_point2_data[10] = - ((tsens_base1_data + tsens10_point2) << 2); - calib_tsens_point1_data[10] = calib_tsens_point1_data[10] - - TSENS_MSM8952_D120_WA_S10; - } - - if ((tsens_calibration_mode == TSENS_TWO_POINT_CALIB_N_WA) || - (tsens_calibration_mode == - TSENS_TWO_POINT_CALIB_N_OFFSET_WA)) { - calib_tsens_point1_data[0] = - (((tsens_base0_data) + tsens0_point1) << 2); - calib_tsens_point1_data[1] = - (((tsens_base0_data) + tsens1_point1) << 2); - calib_tsens_point1_data[2] = - (((tsens_base0_data) + tsens2_point1) << 2); - calib_tsens_point1_data[3] = - (((tsens_base0_data) + tsens3_point1) << 2); - calib_tsens_point1_data[4] = - (((tsens_base0_data) + tsens4_point1) << 2); - calib_tsens_point1_data[5] = - (((tsens_base0_data) + tsens5_point1) << 2); - calib_tsens_point1_data[6] = - (((tsens_base0_data) + tsens6_point1) << 2); - calib_tsens_point1_data[7] = - (((tsens_base0_data) + tsens7_point1) << 2); - calib_tsens_point1_data[8] = - (((tsens_base0_data) + tsens8_point1) << 2); - calib_tsens_point1_data[9] = - (((tsens_base0_data) + tsens9_point1) << 2); - calib_tsens_point1_data[10] = - (((tsens_base0_data) + tsens10_point1) << 2); - } - - if ((tsens_calibration_mode == TSENS_TWO_POINT_CALIB_N_WA) || - (tsens_calibration_mode == - TSENS_TWO_POINT_CALIB_N_OFFSET_WA)) { - pr_debug("two point calibration calculation\n"); - calib_tsens_point2_data[0] = - ((tsens_base1_data + tsens0_point2) << 2); - calib_tsens_point2_data[1] = - ((tsens_base1_data + tsens1_point2) << 2); - calib_tsens_point2_data[2] = - ((tsens_base1_data + tsens2_point2) << 2); - calib_tsens_point2_data[3] = - ((tsens_base1_data + tsens3_point2) << 2); - calib_tsens_point2_data[4] = - ((tsens_base1_data + tsens4_point2) << 2); - calib_tsens_point2_data[5] = - ((tsens_base1_data + tsens5_point2) << 2); - calib_tsens_point2_data[6] = - ((tsens_base1_data + tsens6_point2) << 2); - calib_tsens_point2_data[7] = - ((tsens_base1_data + tsens7_point2) << 2); - calib_tsens_point2_data[8] = - ((tsens_base1_data + tsens8_point2) << 2); - calib_tsens_point2_data[9] = - ((tsens_base1_data + tsens9_point2) << 2); - calib_tsens_point2_data[10] = - ((tsens_base1_data + tsens10_point2) << 2); - } - - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0; - - tmdev->sensor[i].calib_data_point2 = calib_tsens_point2_data[i]; - tmdev->sensor[i].calib_data_point1 = calib_tsens_point1_data[i]; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* - * slope (m) = adc_code2 - adc_code1 (y2 - y1) - * temp_120_degc - temp_30_degc (x2 - x1) - */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - tmdev->sensor[i].offset = (tmdev->sensor[i].calib_data_point1 * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d and slope:%d\n", tmdev->sensor[i].offset, - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - return 0; -} - -static int tsens_calib_msm8909_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base0_data = 0, tsens_base1_data = 0; - int tsens0_point1 = 0, tsens0_point2 = 0; - int tsens1_point1 = 0, tsens1_point2 = 0; - int tsens2_point1 = 0, tsens2_point2 = 0; - int tsens3_point1 = 0, tsens3_point2 = 0; - int tsens4_point1 = 0, tsens4_point2 = 0; - int tsens_calibration_mode = 0, temp = 0; - uint32_t calib_data[3] = {0, 0, 0}; - uint32_t calib_tsens_point1_data[5], calib_tsens_point2_data[5]; - - if (!tmdev->calibration_less_mode) { - - calib_data[0] = readl_relaxed( - TSENS_8939_EEPROM(tmdev->tsens_calib_addr)); - calib_data[1] = readl_relaxed( - (TSENS_8939_EEPROM(tmdev->tsens_calib_addr) + 0x4)); - calib_data[2] = readl_relaxed( - (TSENS_8939_EEPROM(tmdev->tsens_calib_addr) + 0x3c)); - - tsens_calibration_mode = - (calib_data[2] & TSENS_MSM8909_TSENS_CAL_SEL) >> - TSENS_MSM8909_CAL_SEL_SHIFT; - - pr_debug("calib mode is %d\n", tsens_calibration_mode); - } - - if ((tsens_calibration_mode == TSENS_TWO_POINT_CALIB) || - (tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2)) { - tsens_base0_data = (calib_data[2] & TSENS_MSM8909_BASE0_MASK); - tsens0_point1 = (calib_data[0] & TSENS0_MSM8909_POINT1_MASK); - tsens1_point1 = (calib_data[0] & TSENS1_MSM8909_POINT1_MASK) - >> TSENS1_MSM8909_POINT1_SHIFT; - tsens2_point1 = (calib_data[0] & TSENS2_MSM8909_POINT1_MASK) - >> TSENS2_MSM8909_POINT1_SHIFT; - tsens3_point1 = (calib_data[1] & TSENS3_MSM8909_POINT1_MASK) - >> TSENS3_MSM8909_POINT1_SHIFT; - tsens4_point1 = (calib_data[1] & TSENS4_MSM8909_POINT1_MASK) - >> TSENS4_MSM8909_POINT1_SHIFT; - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base1_data = (calib_data[2] & TSENS_MSM8909_BASE1_MASK) - >> TSENS_MSM8909_BASE1_SHIFT; - tsens0_point2 = (calib_data[0] & TSENS0_MSM8909_POINT2_MASK) - >> TSENS0_MSM8909_POINT2_SHIFT; - tsens1_point2 = (calib_data[0] & TSENS1_MSM8909_POINT2_MASK) - >> TSENS1_MSM8909_POINT2_SHIFT; - tsens2_point2 = - (calib_data[0] & TSENS2_MSM8909_POINT2_MASK_0_1) - >> TSENS2_MSM8909_POINT2_SHIFT_0_1; - temp = (calib_data[1] & TSENS2_MSM8909_POINT2_MASK_2_5) << - TSENS2_MSM8909_POINT2_SHIFT_2_5; - tsens2_point2 |= temp; - tsens3_point2 = (calib_data[1] & TSENS3_MSM8909_POINT2_MASK) - >> TSENS3_MSM8909_POINT2_SHIFT; - tsens4_point2 = (calib_data[1] & TSENS4_MSM8909_POINT2_MASK) - >> TSENS4_MSM8909_POINT2_SHIFT; - } - - if (tsens_calibration_mode == 0) { - pr_debug("TSENS is calibrationless mode\n"); - for (i = 0; i < tmdev->tsens_num_sensor; i++) - calib_tsens_point2_data[i] = 780; - calib_tsens_point1_data[0] = 500; - calib_tsens_point1_data[1] = 500; - calib_tsens_point1_data[2] = 500; - calib_tsens_point1_data[3] = 500; - calib_tsens_point1_data[4] = 500; - } - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - calib_tsens_point1_data[0] = - (((tsens_base0_data) + tsens0_point1) << 2); - calib_tsens_point1_data[1] = - (((tsens_base0_data) + tsens1_point1) << 2); - calib_tsens_point1_data[2] = - (((tsens_base0_data) + tsens2_point1) << 2); - calib_tsens_point1_data[3] = - (((tsens_base0_data) + tsens3_point1) << 2); - calib_tsens_point1_data[4] = - (((tsens_base0_data) + tsens4_point1) << 2); - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - pr_debug("two point calibration calculation\n"); - calib_tsens_point2_data[0] = - ((tsens_base1_data + tsens0_point2) << 2); - calib_tsens_point2_data[1] = - ((tsens_base1_data + tsens1_point2) << 2); - calib_tsens_point2_data[2] = - ((tsens_base1_data + tsens2_point2) << 2); - calib_tsens_point2_data[3] = - ((tsens_base1_data + tsens3_point2) << 2); - calib_tsens_point2_data[4] = - ((tsens_base1_data + tsens4_point2) << 2); - } - - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0; - - tmdev->sensor[i].calib_data_point2 = calib_tsens_point2_data[i]; - tmdev->sensor[i].calib_data_point1 = calib_tsens_point1_data[i]; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - * temp_120_degc - temp_30_degc (x2 - x1) */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - tmdev->sensor[i].offset = (tmdev->sensor[i].calib_data_point1 * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d and slope:%d\n", tmdev->sensor[i].offset, - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - - return 0; -} - -static int tsens_calib_8939_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base0_data = 0, tsens_base1_data = 0; - int tsens0_point1 = 0, tsens0_point2 = 0; - int tsens1_point1 = 0, tsens1_point2 = 0; - int tsens2_point1 = 0, tsens2_point2 = 0; - int tsens3_point1 = 0, tsens3_point2 = 0; - int tsens4_point1 = 0, tsens4_point2 = 0; - int tsens5_point1 = 0, tsens5_point2 = 0; - int tsens6_point1 = 0, tsens6_point2 = 0; - int tsens7_point1 = 0, tsens7_point2 = 0; - int tsens8_point1 = 0, tsens8_point2 = 0; - int tsens_calibration_mode = 0, temp = 0; - uint32_t calib_data[4] = {0, 0, 0, 0}; - uint32_t calib_tsens_point1_data[9], calib_tsens_point2_data[9]; - - if (!tmdev->calibration_less_mode) { - - calib_data[0] = readl_relaxed( - TSENS_8939_EEPROM(tmdev->tsens_calib_addr) + 0x30); - calib_data[1] = readl_relaxed( - (TSENS_8939_EEPROM(tmdev->tsens_calib_addr) + 0x34)); - calib_data[2] = readl_relaxed( - (TSENS_8939_EEPROM(tmdev->tsens_calib_addr))); - calib_data[3] = readl_relaxed( - (TSENS_8939_EEPROM(tmdev->tsens_calib_addr) + 0x4)); - - tsens_calibration_mode = - (calib_data[0] & TSENS_8939_TSENS_CAL_SEL); - - pr_debug("calib mode is %d\n", tsens_calibration_mode); - } - - if ((tsens_calibration_mode == TSENS_TWO_POINT_CALIB) || - (tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2)) { - tsens_base0_data = (calib_data[2] & TSENS_8939_BASE0_MASK); - tsens0_point1 = (calib_data[0] & TSENS0_8939_POINT1_MASK) >> - TSENS0_8939_POINT1_SHIFT; - tsens1_point1 = (calib_data[0] & TSENS1_8939_POINT1_MASK) >> - TSENS1_8939_POINT1_SHIFT; - tsens2_point1 = (calib_data[0] & TSENS2_8939_POINT1_MASK_0_4) - >> TSENS2_8939_POINT1_SHIFT_0_4; - temp = (calib_data[1] & TSENS2_8939_POINT1_MASK_5) << - TSENS2_8939_POINT1_SHIFT_5; - tsens2_point1 |= temp; - tsens3_point1 = (calib_data[1] & TSENS3_8939_POINT1_MASK) >> - TSENS3_8939_POINT1_SHIFT; - tsens4_point1 = (calib_data[1] & TSENS4_8939_POINT1_MASK) >> - TSENS4_8939_POINT1_SHIFT; - tsens5_point1 = (calib_data[2] & TSENS5_8939_POINT1_MASK) >> - TSENS5_8939_POINT1_SHIFT; - tsens6_point1 = (calib_data[2] & TSENS6_8939_POINT1_MASK) >> - TSENS6_8939_POINT1_SHIFT; - tsens7_point1 = (calib_data[3] & TSENS7_8939_POINT1_MASK); - tsens8_point1 = (calib_data[3] & TSENS8_8939_POINT1_MASK) >> - TSENS8_8939_POINT1_SHIFT; - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base1_data = (calib_data[3] & TSENS_8939_BASE1_MASK) >> - TSENS_8939_BASE1_SHIFT; - tsens0_point2 = (calib_data[0] & TSENS0_8939_POINT2_MASK) >> - TSENS0_8939_POINT2_SHIFT; - tsens1_point2 = (calib_data[0] & TSENS1_8939_POINT2_MASK) >> - TSENS1_8939_POINT2_SHIFT; - tsens2_point2 = (calib_data[1] & TSENS2_8939_POINT2_MASK) >> - TSENS2_8939_POINT2_SHIFT; - tsens3_point2 = (calib_data[1] & TSENS3_8939_POINT2_MASK) >> - TSENS3_8939_POINT2_SHIFT; - tsens4_point2 = (calib_data[1] & TSENS4_8939_POINT2_MASK) >> - TSENS4_8939_POINT2_SHIFT; - tsens5_point2 = (calib_data[2] & TSENS5_8939_POINT2_MASK) >> - TSENS5_8939_POINT2_SHIFT; - tsens6_point2 = (calib_data[2] & TSENS6_8939_POINT2_MASK) >> - TSENS6_8939_POINT2_SHIFT; - tsens7_point2 = (calib_data[3] & TSENS7_8939_POINT2_MASK) >> - TSENS7_8939_POINT2_SHIFT; - tsens8_point2 = (calib_data[3] & TSENS8_8939_POINT2_MASK) >> - TSENS8_8939_POINT2_SHIFT; - } - - if (tsens_calibration_mode == 0) { - pr_debug("TSENS is calibrationless mode\n"); - for (i = 0; i < tmdev->tsens_num_sensor; i++) - calib_tsens_point2_data[i] = 780; - calib_tsens_point1_data[0] = 500; - calib_tsens_point1_data[1] = 500; - calib_tsens_point1_data[2] = 500; - calib_tsens_point1_data[3] = 500; - calib_tsens_point1_data[4] = 500; - calib_tsens_point1_data[5] = 500; - calib_tsens_point1_data[6] = 500; - calib_tsens_point1_data[7] = 500; - calib_tsens_point1_data[8] = 500; - } - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - calib_tsens_point1_data[0] = - (((tsens_base0_data) + tsens0_point1) << 2); - calib_tsens_point1_data[1] = - (((tsens_base0_data) + tsens1_point1) << 2); - calib_tsens_point1_data[2] = - (((tsens_base0_data) + tsens2_point1) << 2); - calib_tsens_point1_data[3] = - (((tsens_base0_data) + tsens3_point1) << 2); - calib_tsens_point1_data[4] = - (((tsens_base0_data) + tsens4_point1) << 2); - calib_tsens_point1_data[5] = - (((tsens_base0_data) + tsens5_point1) << 2); - calib_tsens_point1_data[6] = - (((tsens_base0_data) + tsens6_point1) << 2); - calib_tsens_point1_data[7] = - (((tsens_base0_data) + tsens7_point1) << 2); - calib_tsens_point1_data[8] = - (((tsens_base0_data) + tsens8_point1) << 2); - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - pr_debug("two point calibration calculation\n"); - calib_tsens_point2_data[0] = - ((tsens_base1_data + tsens0_point2) << 2); - calib_tsens_point2_data[1] = - ((tsens_base1_data + tsens1_point2) << 2); - calib_tsens_point2_data[2] = - ((tsens_base1_data + tsens2_point2) << 2); - calib_tsens_point2_data[3] = - ((tsens_base1_data + tsens3_point2) << 2); - calib_tsens_point2_data[4] = - ((tsens_base1_data + tsens4_point2) << 2); - calib_tsens_point2_data[5] = - ((tsens_base1_data + tsens5_point2) << 2); - calib_tsens_point2_data[6] = - ((tsens_base1_data + tsens6_point2) << 2); - calib_tsens_point2_data[7] = - ((tsens_base1_data + tsens7_point2) << 2); - calib_tsens_point2_data[8] = - ((tsens_base1_data + tsens8_point2) << 2); - } - - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0; - - tmdev->sensor[i].calib_data_point2 = calib_tsens_point2_data[i]; - tmdev->sensor[i].calib_data_point1 = calib_tsens_point1_data[i]; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - * temp_120_degc - temp_30_degc (x2 - x1) */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - tmdev->sensor[i].offset = (tmdev->sensor[i].calib_data_point1 * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d and slope:%d\n", tmdev->sensor[i].offset, - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - - return 0; -} - -static int tsens_calib_8916_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base0_data = 0, tsens_base1_data = 0; - int tsens0_point1 = 0, tsens0_point2 = 0; - int tsens1_point1 = 0, tsens1_point2 = 0; - int tsens2_point1 = 0, tsens2_point2 = 0; - int tsens3_point1 = 0, tsens3_point2 = 0; - int tsens4_point1 = 0, tsens4_point2 = 0; - int tsens_calibration_mode = 0; - uint32_t calib_data[3] = {0, 0, 0}; - uint32_t calib_tsens_point1_data[5], calib_tsens_point2_data[5]; - - if (!tmdev->calibration_less_mode) { - - calib_data[0] = readl_relaxed( - TSENS_EEPROM(tmdev->tsens_calib_addr)); - calib_data[1] = readl_relaxed( - (TSENS_EEPROM(tmdev->tsens_calib_addr) + 0x4)); - calib_data[2] = readl_relaxed( - (TSENS_EEPROM(tmdev->tsens_calib_addr) + 0x1c)); - - tsens_calibration_mode = - (calib_data[2] & TSENS_8916_TSENS_CAL_SEL) >> - TSENS_8916_CAL_SEL_SHIFT; - - pr_debug("calib mode is %d\n", tsens_calibration_mode); - } - - if ((tsens_calibration_mode == TSENS_TWO_POINT_CALIB) || - (tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2)) { - tsens_base0_data = (calib_data[0] & TSENS_8916_BASE0_MASK); - tsens0_point1 = (calib_data[0] & TSENS0_8916_POINT1_MASK) >> - TSENS0_8916_POINT1_SHIFT; - tsens1_point1 = (calib_data[0] & TSENS1_8916_POINT1_MASK) >> - TSENS1_8916_POINT1_SHIFT; - tsens2_point1 = (calib_data[0] & TSENS2_8916_POINT1_MASK) >> - TSENS2_8916_POINT1_SHIFT; - tsens3_point1 = (calib_data[1] & TSENS3_8916_POINT1_MASK) >> - TSENS3_8916_POINT1_SHIFT; - tsens4_point1 = (calib_data[1] & TSENS4_8916_POINT1_MASK) >> - TSENS4_8916_POINT1_SHIFT; - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base1_data = (calib_data[1] & TSENS_8916_BASE1_MASK) >> - TSENS_8916_BASE1_SHIFT; - tsens0_point2 = (calib_data[0] & TSENS0_8916_POINT2_MASK) >> - TSENS0_8916_POINT2_SHIFT; - tsens1_point2 = (calib_data[0] & TSENS1_8916_POINT2_MASK) >> - TSENS1_8916_POINT2_SHIFT; - tsens2_point2 = (calib_data[1] & TSENS2_8916_POINT2_MASK); - tsens3_point2 = (calib_data[1] & TSENS3_8916_POINT2_MASK) >> - TSENS3_8916_POINT2_SHIFT; - tsens4_point2 = (calib_data[1] & TSENS4_8916_POINT2_MASK) >> - TSENS4_8916_POINT2_SHIFT; - } - - if (tsens_calibration_mode == 0) { - pr_debug("TSENS is calibrationless mode\n"); - for (i = 0; i < tmdev->tsens_num_sensor; i++) - calib_tsens_point2_data[i] = 780; - calib_tsens_point1_data[0] = 500; - calib_tsens_point1_data[1] = 500; - calib_tsens_point1_data[2] = 500; - calib_tsens_point1_data[3] = 500; - calib_tsens_point1_data[4] = 500; - } - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - calib_tsens_point1_data[0] = - (((tsens_base0_data) + tsens0_point1) << 3); - calib_tsens_point1_data[1] = - (((tsens_base0_data) + tsens1_point1) << 3); - calib_tsens_point1_data[2] = - (((tsens_base0_data) + tsens2_point1) << 3); - calib_tsens_point1_data[3] = - (((tsens_base0_data) + tsens3_point1) << 3); - calib_tsens_point1_data[4] = - (((tsens_base0_data) + tsens4_point1) << 3); - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - pr_debug("two point calibration calculation\n"); - calib_tsens_point2_data[0] = - ((tsens_base1_data + tsens0_point2) << 3); - calib_tsens_point2_data[1] = - ((tsens_base1_data + tsens1_point2) << 3); - calib_tsens_point2_data[2] = - ((tsens_base1_data + tsens2_point2) << 3); - calib_tsens_point2_data[3] = - ((tsens_base1_data + tsens3_point2) << 3); - calib_tsens_point2_data[4] = - ((tsens_base1_data + tsens4_point2) << 3); - } - - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0; - - tmdev->sensor[i].calib_data_point2 = calib_tsens_point2_data[i]; - tmdev->sensor[i].calib_data_point1 = calib_tsens_point1_data[i]; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - * temp_120_degc - temp_30_degc (x2 - x1) */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - tmdev->sensor[i].offset = (tmdev->sensor[i].calib_data_point1 * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d and slope:%d\n", tmdev->sensor[i].offset, - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - - return 0; -} - -static int tsens_calib_9630_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base0_data = 0, tsens0_point = 0, tsens1_point = 0; - int tsens2_point = 0, tsens3_point = 0, tsens4_point = 0; - int tsens_base1_data = 0, tsens_calibration_mode = 0, calib_mode = 0; - uint32_t calib_data[2], calib_tsens_point_data[5]; - - if (tmdev->calibration_less_mode) - goto calibration_less_mode; - - calib_data[0] = readl_relaxed( - TSENS_EEPROM(tmdev->tsens_calib_addr)); - calib_data[1] = readl_relaxed( - (TSENS_EEPROM(tmdev->tsens_calib_addr) + 0x4)); - - calib_mode = (calib_data[1] & TSENS_TORINO_CALIB_PT) >> - TSENS_TORINO_CALIB_SHIFT; - pr_debug("calib mode is %d\n", calib_mode); - if (calib_mode == TSENS_TWO_POINT_CALIB) { - tsens_base0_data = (calib_data[0] & TSENS_TORINO_BASE0); - tsens_base1_data = (calib_data[0] & TSENS_TORINO_BASE1) >> - TSENS_TORINO_BASE1_SHIFT; - tsens0_point = (calib_data[0] & TSENS_TORINO_POINT0) >> - TSENS_TORINO_POINT0_SHIFT; - tsens1_point = (calib_data[0] & TSENS_TORINO_POINT1) >> - TSENS_TORINO_POINT1_SHIFT; - tsens2_point = (calib_data[0] & TSENS_TORINO_POINT2) >> - TSENS_TORINO_POINT2_SHIFT; - tsens3_point = (calib_data[0] & TSENS_TORINO_POINT3) >> - TSENS_TORINO_POINT3_SHIFT; - tsens4_point = (calib_data[0] & TSENS_TORINO_POINT4) >> - TSENS_TORINO_POINT4_SHIFT; - calib_tsens_point_data[0] = tsens0_point; - calib_tsens_point_data[1] = tsens1_point; - calib_tsens_point_data[2] = tsens2_point; - calib_tsens_point_data[3] = tsens3_point; - calib_tsens_point_data[4] = tsens4_point; - } - - if (calib_mode == 0) { -calibration_less_mode: - pr_debug("TSENS is calibrationless mode\n"); - calib_tsens_point_data[0] = 532; - calib_tsens_point_data[1] = 532; - calib_tsens_point_data[2] = 532; - calib_tsens_point_data[3] = 532; - calib_tsens_point_data[4] = 532; - goto compute_intercept_slope; - } - -compute_intercept_slope: - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0, adc_code_of_tempx = 0; - - tmdev->sensor[i].calib_data_point2 = tsens_base1_data; - tmdev->sensor[i].calib_data_point1 = tsens_base0_data; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - temp_120_degc - temp_30_degc (x2 - x1) */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - adc_code_of_tempx = - tsens_base0_data + calib_tsens_point_data[i]; - pr_debug("offset_adc_code_of_tempx:0x%x\n", - adc_code_of_tempx); - tmdev->sensor[i].offset = (adc_code_of_tempx * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d and slope:%d\n", tmdev->sensor[i].offset, - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - - return 0; -} - -static int tsens_calib_8994_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base0_data = 0, tsens0_point = 0, tsens1_point = 0; - int tsens2_point = 0, tsens3_point = 0, tsens4_point = 0; - int tsens5_point = 0, tsens6_point = 0, tsens7_point = 0; - int tsens8_point = 0, tsens9_point = 0, tsens10_point = 0; - int tsens11_point = 0, tsens12_point = 0, tsens13_point = 0; - int tsens14_point = 0, tsens15_point = 0; - int tsens_base1_data = 0, calib_mode = 0; - uint32_t calib_data[6], calib_tsens_point_data[16], calib_redun_sel; - - if (tmdev->calibration_less_mode) - goto calibration_less_mode; - - calib_redun_sel = readl_relaxed( - TSENS_8994_EEPROM_REDUN_SEL(tmdev->tsens_calib_addr)); - calib_redun_sel = calib_redun_sel & TSENS_8994_CAL_SEL_REDUN_MASK; - calib_redun_sel >>= TSENS_8994_CAL_SEL_REDUN_SHIFT; - - if (calib_redun_sel == TSENS_QFPROM_BACKUP_SEL) { - calib_data[0] = readl_relaxed( - TSENS_REDUN_REGION1_EEPROM(tmdev->tsens_calib_addr)); - calib_data[1] = readl_relaxed( - TSENS_REDUN_REGION2_EEPROM(tmdev->tsens_calib_addr)); - calib_data[2] = readl_relaxed( - TSENS_REDUN_REGION3_EEPROM(tmdev->tsens_calib_addr)); - calib_data[3] = readl_relaxed( - TSENS_REDUN_REGION4_EEPROM(tmdev->tsens_calib_addr)); - calib_data[4] = readl_relaxed( - TSENS_REDUN_REGION5_EEPROM(tmdev->tsens_calib_addr)); - - calib_mode = (calib_data[4] & TSENS_8994_REDUN_SEL_MASK); - pr_debug("calib mode is %d\n", calib_mode); - if (calib_mode == TSENS_TWO_POINT_CALIB) { - tsens_base0_data = (calib_data[0] & - TSENS_BASE0_8994_REDUN_MASK) >> - TSENS_BASE0_8994_REDUN_MASK_SHIFT; - tsens_base1_data = (calib_data[0] & - TSENS_BASE1_BIT0_8994_REDUN_MASK) >> - TSENS_BASE1_BIT0_SHIFT_COMPUTE; - tsens_base1_data |= (calib_data[1] & - TSENS_BASE1_BIT1_9_8994_REDUN_MASK); - tsens0_point = (calib_data[1] & - TSENS0_OFFSET_8994_REDUN_MASK) >> - TSENS0_OFFSET_8994_REDUN_SHIFT; - tsens1_point = (calib_data[1] & - TSENS1_OFFSET_8994_REDUN_MASK) >> - TSENS1_OFFSET_8994_REDUN_SHIFT; - tsens2_point = (calib_data[1] & - TSENS2_OFFSET_8994_REDUN_MASK) >> - TSENS2_OFFSET_8994_REDUN_SHIFT; - tsens3_point = (calib_data[1] & - TSENS3_OFFSET_8994_REDUN_MASK) >> - TSENS3_OFFSET_8994_REDUN_SHIFT; - tsens4_point = (calib_data[1] & - TSENS4_OFFSET_8994_REDUN_MASK) >> - TSENS4_OFFSET_8994_REDUN_SHIFT; - tsens5_point = (calib_data[1] & - TSENS5_OFFSET_8994_REDUN_MASK_BIT0_2) >> - TSENS5_OFFSET_8994_REDUN_SHIFT_BIT0_2; - tsens5_point |= ((calib_data[2] & - TSENS5_OFFSET_8994_REDUN_MASK_BIT3) >> - TSENS5_OFFSET_8994_REDUN_SHIFT_BIT3); - tsens6_point = (calib_data[2] & - TSENS6_OFFSET_8994_REDUN_MASK) >> - TSENS6_OFFSET_8994_REDUN_SHIFT; - tsens7_point = (calib_data[2] & - TSENS7_OFFSET_8994_REDUN_MASK) >> - TSENS7_OFFSET_8994_REDUN_SHIFT; - tsens8_point = (calib_data[3] & - TSENS8_OFFSET_8994_REDUN_MASK); - tsens9_point = (calib_data[3] & - TSENS9_OFFSET_8994_REDUN_MASK) >> - TSENS9_OFFSET_8994_REDUN_SHIFT; - tsens10_point = (calib_data[3] & - TSENS10_OFFSET_8994_REDUN_MASK) >> - TSENS10_OFFSET_8994_REDUN_SHIFT; - tsens11_point = (calib_data[3] & - TSENS11_OFFSET_8994_REDUN_MASK) >> - TSENS11_OFFSET_8994_REDUN_SHIFT; - tsens12_point = (calib_data[3] & - TSENS12_OFFSET_8994_REDUN_MASK) >> - TSENS12_OFFSET_8994_REDUN_SHIFT; - tsens13_point = (calib_data[3] & - TSENS13_OFFSET_8994_REDUN_MASK) >> - TSENS13_OFFSET_8994_REDUN_SHIFT; - tsens14_point = (calib_data[3] & - TSENS14_OFFSET_8994_REDUN_MASK) >> - TSENS14_OFFSET_8994_REDUN_SHIFT; - tsens15_point = (calib_data[3] & - TSENS15_OFFSET_8994_REDUN_MASK) >> - TSENS15_OFFSET_8994_REDUN_SHIFT; - calib_tsens_point_data[0] = tsens0_point; - calib_tsens_point_data[1] = tsens1_point; - calib_tsens_point_data[2] = tsens2_point; - calib_tsens_point_data[3] = tsens3_point; - calib_tsens_point_data[4] = tsens4_point; - calib_tsens_point_data[5] = tsens5_point; - calib_tsens_point_data[6] = tsens6_point; - calib_tsens_point_data[7] = tsens7_point; - calib_tsens_point_data[8] = tsens8_point; - calib_tsens_point_data[9] = tsens9_point; - calib_tsens_point_data[10] = tsens10_point; - calib_tsens_point_data[11] = tsens11_point; - calib_tsens_point_data[12] = tsens12_point; - calib_tsens_point_data[13] = tsens13_point; - calib_tsens_point_data[14] = tsens14_point; - calib_tsens_point_data[15] = tsens15_point; - } else - goto calibration_less_mode; - } else { - calib_data[0] = readl_relaxed( - TSENS_8994_EEPROM(tmdev->tsens_calib_addr)); - calib_data[1] = readl_relaxed( - (TSENS_8994_EEPROM(tmdev->tsens_calib_addr) + 0x4)); - calib_data[2] = readl_relaxed( - (TSENS_8994_EEPROM(tmdev->tsens_calib_addr) + 0x8)); - - calib_mode = (calib_data[2] & TSENS_8994_CAL_SEL_MASK) >> - TSENS_8994_CAL_SEL_SHIFT; - pr_debug("calib mode is %d\n", calib_mode); - if (calib_mode == TSENS_TWO_POINT_CALIB) { - tsens_base0_data = (calib_data[0] & - TSENS_BASE0_8994_MASK); - tsens_base1_data = (calib_data[0] & - TSENS_BASE1_8994_MASK) >> - TSENS_BASE1_8994_SHIFT; - tsens0_point = (calib_data[0] & - TSENS0_OFFSET_8994_MASK) >> - TSENS0_OFFSET_8994_SHIFT; - tsens1_point = (calib_data[0] & - TSENS1_OFFSET_8994_MASK) >> - TSENS1_OFFSET_8994_SHIFT; - tsens2_point = (calib_data[0] & - TSENS2_OFFSET_8994_MASK) >> - TSENS2_OFFSET_8994_SHIFT; - tsens3_point = (calib_data[1] & - TSENS3_OFFSET_8994_MASK); - tsens4_point = (calib_data[1] & - TSENS4_OFFSET_8994_MASK) >> - TSENS4_OFFSET_8994_SHIFT; - tsens5_point = (calib_data[1] & - TSENS5_OFFSET_8994_MASK) >> - TSENS5_OFFSET_8994_SHIFT; - tsens6_point = (calib_data[1] & - TSENS6_OFFSET_8994_MASK) >> - TSENS6_OFFSET_8994_SHIFT; - tsens7_point = (calib_data[1] & - TSENS7_OFFSET_8994_MASK) >> - TSENS7_OFFSET_8994_SHIFT; - tsens8_point = (calib_data[1] & - TSENS8_OFFSET_8994_MASK) >> - TSENS8_OFFSET_8994_SHIFT; - tsens9_point = (calib_data[1] & - TSENS9_OFFSET_8994_MASK) >> - TSENS9_OFFSET_8994_SHIFT; - tsens10_point = (calib_data[1] & - TSENS10_OFFSET_8994_MASK) >> - TSENS10_OFFSET_8994_SHIFT; - tsens11_point = (calib_data[2] & - TSENS11_OFFSET_8994_MASK); - tsens12_point = (calib_data[2] & - TSENS12_OFFSET_8994_MASK) >> - TSENS12_OFFSET_8994_SHIFT; - tsens13_point = (calib_data[2] & - TSENS13_OFFSET_8994_MASK) >> - TSENS13_OFFSET_8994_SHIFT; - tsens14_point = (calib_data[2] & - TSENS14_OFFSET_8994_MASK) >> - TSENS14_OFFSET_8994_SHIFT; - tsens15_point = (calib_data[2] & - TSENS15_OFFSET_8994_MASK) >> - TSENS15_OFFSET_8994_SHIFT; - calib_tsens_point_data[0] = tsens0_point; - calib_tsens_point_data[1] = tsens1_point; - calib_tsens_point_data[2] = tsens2_point; - calib_tsens_point_data[3] = tsens3_point; - calib_tsens_point_data[4] = tsens4_point; - calib_tsens_point_data[5] = tsens5_point; - calib_tsens_point_data[6] = tsens6_point; - calib_tsens_point_data[7] = tsens7_point; - calib_tsens_point_data[8] = tsens8_point; - calib_tsens_point_data[9] = tsens9_point; - calib_tsens_point_data[10] = tsens10_point; - calib_tsens_point_data[11] = tsens11_point; - calib_tsens_point_data[12] = tsens12_point; - calib_tsens_point_data[13] = tsens13_point; - calib_tsens_point_data[14] = tsens14_point; - calib_tsens_point_data[15] = tsens15_point; - } else { -calibration_less_mode: - pr_debug("TSENS is calibrationless mode\n"); - calib_tsens_point_data[0] = 532; - calib_tsens_point_data[1] = 532; - calib_tsens_point_data[2] = 532; - calib_tsens_point_data[3] = 532; - calib_tsens_point_data[4] = 532; - calib_tsens_point_data[5] = 532; - calib_tsens_point_data[6] = 532; - calib_tsens_point_data[7] = 532; - calib_tsens_point_data[8] = 532; - calib_tsens_point_data[9] = 532; - calib_tsens_point_data[10] = 532; - calib_tsens_point_data[11] = 532; - calib_tsens_point_data[12] = 532; - calib_tsens_point_data[13] = 532; - calib_tsens_point_data[14] = 532; - calib_tsens_point_data[15] = 532; - } - } - - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0, adc_code_of_tempx = 0; - - tmdev->sensor[i].calib_data_point2 = tsens_base1_data; - tmdev->sensor[i].calib_data_point1 = tsens_base0_data; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (calib_mode == TSENS_TWO_POINT_CALIB) { - /* slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - temp_120_degc - temp_30_degc (x2 - x1) */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - adc_code_of_tempx = - tsens_base0_data + calib_tsens_point_data[i]; - pr_debug("offset_adc_code_of_tempx:0x%x\n", - adc_code_of_tempx); - tmdev->sensor[i].offset = (adc_code_of_tempx * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d and slope:%d\n", tmdev->sensor[i].offset, - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - - return 0; -} - -static int tsens_calib_8992_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base0_data = 0, tsens0_point = 0, tsens1_point = 0; - int tsens2_point = 0, tsens3_point = 0, tsens4_point = 0; - int tsens5_point = 0, tsens6_point = 0, tsens7_point = 0; - int tsens8_point = 0, tsens9_point = 0, tsens10_point = 0; - int tsens11_point = 0, tsens12_point = 0, tsens13_point = 0; - int tsens14_point = 0, tsens15_point = 0; - int tsens_base1_data = 0, calib_mode = 0; - uint32_t calib_data[6], calib_tsens_point_data[16], calib_redun_sel; - - if (tmdev->calibration_less_mode) - goto calibration_less_mode; - - calib_redun_sel = readl_relaxed( - TSENS_8994_EEPROM_REDUN_SEL(tmdev->tsens_calib_addr)); - calib_redun_sel = calib_redun_sel & TSENS_8994_CAL_SEL_REDUN_MASK; - calib_redun_sel >>= TSENS_8994_CAL_SEL_REDUN_SHIFT; - - if (calib_redun_sel == TSENS_QFPROM_BACKUP_SEL) { - calib_data[0] = readl_relaxed( - TSENS_REDUN_REGION1_EEPROM(tmdev->tsens_calib_addr)); - calib_data[1] = readl_relaxed( - TSENS_REDUN_REGION2_EEPROM(tmdev->tsens_calib_addr)); - calib_data[2] = readl_relaxed( - TSENS_REDUN_REGION3_EEPROM(tmdev->tsens_calib_addr)); - calib_data[3] = readl_relaxed( - TSENS_REDUN_REGION4_EEPROM(tmdev->tsens_calib_addr)); - calib_data[4] = readl_relaxed( - TSENS_REDUN_REGION5_EEPROM(tmdev->tsens_calib_addr)); - - calib_mode = (calib_data[4] & TSENS_8994_REDUN_SEL_MASK); - pr_debug("calib mode is %d\n", calib_mode); - if (calib_mode == TSENS_TWO_POINT_CALIB) { - tsens_base0_data = (calib_data[0] & - TSENS_BASE0_8994_REDUN_MASK) >> - TSENS_BASE0_8994_REDUN_MASK_SHIFT; - tsens_base1_data = (calib_data[0] & - TSENS_BASE1_BIT0_8994_REDUN_MASK) >> - TSENS_BASE1_BIT0_SHIFT_COMPUTE; - tsens_base1_data |= (calib_data[1] & - TSENS_BASE1_BIT1_9_8994_REDUN_MASK); - tsens0_point = (calib_data[1] & - TSENS0_OFFSET_8994_REDUN_MASK) >> - TSENS0_OFFSET_8994_REDUN_SHIFT; - tsens1_point = (calib_data[1] & - TSENS1_OFFSET_8994_REDUN_MASK) >> - TSENS1_OFFSET_8994_REDUN_SHIFT; - tsens2_point = (calib_data[1] & - TSENS2_OFFSET_8994_REDUN_MASK) >> - TSENS2_OFFSET_8994_REDUN_SHIFT; - tsens3_point = (calib_data[1] & - TSENS3_OFFSET_8994_REDUN_MASK) >> - TSENS3_OFFSET_8994_REDUN_SHIFT; - tsens4_point = (calib_data[1] & - TSENS4_OFFSET_8994_REDUN_MASK) >> - TSENS4_OFFSET_8994_REDUN_SHIFT; - tsens5_point = (calib_data[1] & - TSENS5_OFFSET_8994_REDUN_MASK_BIT0_2) >> - TSENS5_OFFSET_8994_REDUN_SHIFT_BIT0_2; - tsens5_point |= ((calib_data[2] & - TSENS5_OFFSET_8994_REDUN_MASK_BIT3) >> - TSENS5_OFFSET_8994_REDUN_SHIFT_BIT3); - tsens6_point = (calib_data[2] & - TSENS6_OFFSET_8994_REDUN_MASK) >> - TSENS6_OFFSET_8994_REDUN_SHIFT; - tsens7_point = (calib_data[2] & - TSENS7_OFFSET_8994_REDUN_MASK) >> - TSENS7_OFFSET_8994_REDUN_SHIFT; - tsens8_point = (calib_data[3] & - TSENS8_OFFSET_8994_REDUN_MASK); - tsens9_point = (calib_data[3] & - TSENS9_OFFSET_8994_REDUN_MASK) >> - TSENS9_OFFSET_8994_REDUN_SHIFT; - tsens10_point = (calib_data[3] & - TSENS10_OFFSET_8994_REDUN_MASK) >> - TSENS10_OFFSET_8994_REDUN_SHIFT; - tsens11_point = (calib_data[3] & - TSENS11_OFFSET_8994_REDUN_MASK) >> - TSENS11_OFFSET_8994_REDUN_SHIFT; - tsens12_point = (calib_data[3] & - TSENS12_OFFSET_8994_REDUN_MASK) >> - TSENS12_OFFSET_8994_REDUN_SHIFT; - tsens13_point = (calib_data[3] & - TSENS13_OFFSET_8994_REDUN_MASK) >> - TSENS13_OFFSET_8994_REDUN_SHIFT; - tsens14_point = (calib_data[3] & - TSENS14_OFFSET_8994_REDUN_MASK) >> - TSENS14_OFFSET_8994_REDUN_SHIFT; - tsens15_point = (calib_data[3] & - TSENS15_OFFSET_8994_REDUN_MASK) >> - TSENS15_OFFSET_8994_REDUN_SHIFT; - calib_tsens_point_data[0] = tsens0_point; - calib_tsens_point_data[1] = tsens1_point; - calib_tsens_point_data[2] = tsens2_point; - calib_tsens_point_data[3] = tsens3_point; - calib_tsens_point_data[4] = tsens4_point; - calib_tsens_point_data[5] = tsens5_point; - calib_tsens_point_data[6] = tsens7_point; - calib_tsens_point_data[7] = tsens9_point; - calib_tsens_point_data[8] = tsens10_point; - calib_tsens_point_data[9] = tsens11_point; - calib_tsens_point_data[10] = tsens12_point; - calib_tsens_point_data[11] = tsens13_point; - calib_tsens_point_data[12] = tsens14_point; - } else - goto calibration_less_mode; - } else { - calib_data[0] = readl_relaxed( - TSENS_8994_EEPROM(tmdev->tsens_calib_addr)); - calib_data[1] = readl_relaxed( - (TSENS_8994_EEPROM(tmdev->tsens_calib_addr) + 0x4)); - calib_data[2] = readl_relaxed( - (TSENS_8994_EEPROM(tmdev->tsens_calib_addr) + 0x8)); - - calib_mode = (calib_data[2] & TSENS_8994_CAL_SEL_MASK) >> - TSENS_8994_CAL_SEL_SHIFT; - pr_debug("calib mode is %d\n", calib_mode); - if (calib_mode == TSENS_TWO_POINT_CALIB) { - tsens_base0_data = (calib_data[0] & - TSENS_BASE0_8994_MASK); - tsens_base1_data = (calib_data[0] & - TSENS_BASE1_8994_MASK) >> - TSENS_BASE1_8994_SHIFT; - tsens0_point = (calib_data[0] & - TSENS0_OFFSET_8994_MASK) >> - TSENS0_OFFSET_8994_SHIFT; - tsens1_point = (calib_data[0] & - TSENS1_OFFSET_8994_MASK) >> - TSENS1_OFFSET_8994_SHIFT; - tsens2_point = (calib_data[0] & - TSENS2_OFFSET_8994_MASK) >> - TSENS2_OFFSET_8994_SHIFT; - tsens3_point = (calib_data[1] & - TSENS3_OFFSET_8994_MASK); - tsens4_point = (calib_data[1] & - TSENS4_OFFSET_8994_MASK) >> - TSENS4_OFFSET_8994_SHIFT; - tsens5_point = (calib_data[1] & - TSENS5_OFFSET_8994_MASK) >> - TSENS5_OFFSET_8994_SHIFT; - tsens7_point = (calib_data[1] & - TSENS6_OFFSET_8994_MASK) >> - TSENS6_OFFSET_8994_SHIFT; - tsens9_point = (calib_data[1] & - TSENS7_OFFSET_8994_MASK) >> - TSENS7_OFFSET_8994_SHIFT; - tsens10_point = (calib_data[1] & - TSENS8_OFFSET_8994_MASK) >> - TSENS8_OFFSET_8994_SHIFT; - tsens11_point = (calib_data[1] & - TSENS9_OFFSET_8994_MASK) >> - TSENS9_OFFSET_8994_SHIFT; - tsens12_point = (calib_data[1] & - TSENS10_OFFSET_8994_MASK) >> - TSENS10_OFFSET_8994_SHIFT; - tsens13_point = (calib_data[2] & - TSENS11_OFFSET_8994_MASK); - tsens14_point = (calib_data[2] & - TSENS12_OFFSET_8994_MASK) >> - TSENS12_OFFSET_8994_SHIFT; - calib_tsens_point_data[0] = tsens0_point; - calib_tsens_point_data[1] = tsens1_point; - calib_tsens_point_data[2] = tsens2_point; - calib_tsens_point_data[3] = tsens3_point; - calib_tsens_point_data[4] = tsens4_point; - calib_tsens_point_data[5] = tsens5_point; - calib_tsens_point_data[6] = tsens7_point; - calib_tsens_point_data[7] = tsens9_point; - calib_tsens_point_data[8] = tsens10_point; - calib_tsens_point_data[9] = tsens11_point; - calib_tsens_point_data[10] = tsens12_point; - calib_tsens_point_data[11] = tsens13_point; - calib_tsens_point_data[12] = tsens14_point; - } else { -calibration_less_mode: - pr_debug("TSENS is calibrationless mode\n"); - calib_tsens_point_data[0] = 532; - calib_tsens_point_data[1] = 532; - calib_tsens_point_data[2] = 532; - calib_tsens_point_data[3] = 532; - calib_tsens_point_data[4] = 532; - calib_tsens_point_data[5] = 532; - calib_tsens_point_data[6] = 532; - calib_tsens_point_data[7] = 532; - calib_tsens_point_data[8] = 532; - calib_tsens_point_data[9] = 532; - calib_tsens_point_data[10] = 532; - calib_tsens_point_data[11] = 532; - calib_tsens_point_data[12] = 532; - calib_tsens_point_data[13] = 532; - calib_tsens_point_data[14] = 532; - calib_tsens_point_data[15] = 532; - } - } - - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0, adc_code_of_tempx = 0; - - tmdev->sensor[i].calib_data_point2 = tsens_base1_data; - tmdev->sensor[i].calib_data_point1 = tsens_base0_data; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (calib_mode == TSENS_TWO_POINT_CALIB) { - /* slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - temp_120_degc - temp_30_degc (x2 - x1) */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - adc_code_of_tempx = - tsens_base0_data + calib_tsens_point_data[i]; - pr_debug("offset_adc_code_of_tempx:0x%x\n", - adc_code_of_tempx); - tmdev->sensor[i].offset = (adc_code_of_tempx * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d and slope:%d\n", tmdev->sensor[i].offset, - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - - return 0; -} - -static int tsens_calib_8x10_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base0_data = 0, tsens0_point1 = 0, tsens1_point1 = 0; - int tsens0_point2 = 0, tsens1_point2 = 0; - int tsens_base1_data = 0, tsens_calibration_mode = 0; - uint32_t calib_data[2], calib_redun_sel; - uint32_t calib_tsens_point1_data[2], calib_tsens_point2_data[2]; - - if (tmdev->calibration_less_mode) - goto calibration_less_mode; - - calib_redun_sel = readl_relaxed( - TSENS_EEPROM_8X10_2(tmdev->tsens_calib_addr)); - calib_redun_sel = calib_redun_sel & TSENS_8X10_REDUN_SEL_MASK; - calib_redun_sel >>= TSENS_8X10_REDUN_SEL_SHIFT; - pr_debug("calib_redun_sel:%x\n", calib_redun_sel); - - if (calib_redun_sel == TSENS_QFPROM_BACKUP_SEL) { - calib_data[0] = readl_relaxed( - TSENS_EEPROM_8X10_SPARE_1(tmdev->tsens_calib_addr)); - calib_data[1] = readl_relaxed( - TSENS_EEPROM_8X10_SPARE_2(tmdev->tsens_calib_addr)); - } else { - calib_data[0] = readl_relaxed( - TSENS_EEPROM_8X10_1(tmdev->tsens_calib_addr)); - calib_data[1] = readl_relaxed( - (TSENS_EEPROM_8X10_1(tmdev->tsens_calib_addr) + - TSENS_EEPROM_8X10_1_OFFSET)); - } - - tsens_calibration_mode = (calib_data[0] & TSENS_8X10_TSENS_CAL_SEL) - >> TSENS_8X10_CAL_SEL_SHIFT; - pr_debug("calib mode scheme:%x\n", tsens_calibration_mode); - - if ((tsens_calibration_mode == TSENS_TWO_POINT_CALIB) || - (tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2)) { - tsens_base0_data = (calib_data[0] & TSENS_8X10_BASE0_MASK); - tsens0_point1 = (calib_data[0] & TSENS0_8X10_POINT1_MASK) >> - TSENS0_8X10_POINT1_SHIFT; - tsens1_point1 = calib_data[1] & TSENS1_8X10_POINT1_MASK; - } else - goto calibration_less_mode; - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base1_data = (calib_data[0] & TSENS_8X10_BASE1_MASK) >> - TSENS_8X10_BASE1_SHIFT; - tsens0_point2 = (calib_data[0] & TSENS0_8X10_POINT2_MASK) >> - TSENS0_8X10_POINT2_SHIFT; - tsens1_point2 = (calib_data[1] & TSENS1_8X10_POINT2_MASK) >> - TSENS1_8X10_POINT2_SHIFT; - } - - if (tsens_calibration_mode == 0) { -calibration_less_mode: - pr_debug("TSENS is calibrationless mode\n"); - for (i = 0; i < tmdev->tsens_num_sensor; i++) - calib_tsens_point2_data[i] = 780; - calib_tsens_point1_data[0] = 595; - calib_tsens_point1_data[1] = 629; - goto compute_intercept_slope; - } - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - calib_tsens_point1_data[0] = - ((((tsens_base0_data) + tsens0_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[1] = - ((((tsens_base0_data) + tsens1_point1) << 2) | - TSENS_BIT_APPEND); - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - pr_debug("two point calibration calculation\n"); - calib_tsens_point2_data[0] = - (((tsens_base1_data + tsens0_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[1] = - (((tsens_base1_data + tsens1_point2) << 2) | - TSENS_BIT_APPEND); - } - -compute_intercept_slope: - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0; - - tmdev->sensor[i].calib_data_point2 = calib_tsens_point2_data[i]; - tmdev->sensor[i].calib_data_point1 = calib_tsens_point1_data[i]; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - temp_120_degc - temp_30_degc (x2 - x1) */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - tmdev->sensor[i].offset = (tmdev->sensor[i].calib_data_point1 * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - - return 0; -} - -static int tsens_calib_8x26_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base0_data = 0, tsens0_point1 = 0, tsens1_point1 = 0; - int tsens2_point1 = 0, tsens3_point1 = 0, tsens4_point1 = 0; - int tsens5_point1 = 0, tsens6_point1 = 0, tsens6_point2 = 0; - int tsens0_point2 = 0, tsens1_point2 = 0, tsens2_point2 = 0; - int tsens3_point2 = 0, tsens4_point2 = 0, tsens5_point2 = 0; - int tsens_base1_data = 0, tsens_calibration_mode = 0; - uint32_t calib_data[6]; - uint32_t calib_tsens_point1_data[7], calib_tsens_point2_data[7]; - - if (tmdev->calibration_less_mode) - goto calibration_less_mode; - - for (i = 0; i < TSENS_8X26_MAIN_CALIB_ADDR_RANGE; i++) - calib_data[i] = readl_relaxed( - (TSENS_EEPROM_8X26_1(tmdev->tsens_calib_addr)) - + (i * TSENS_SN_ADDR_OFFSET)); - calib_data[4] = readl_relaxed( - (TSENS_EEPROM_8X26_2(tmdev->tsens_calib_addr))); - calib_data[5] = readl_relaxed( - (TSENS_EEPROM_8X26_2(tmdev->tsens_calib_addr)) + 0x8); - - tsens_calibration_mode = (calib_data[5] & TSENS_8X26_TSENS_CAL_SEL) - >> TSENS_8X26_CAL_SEL_SHIFT; - pr_debug("calib mode scheme:%x\n", tsens_calibration_mode); - - if ((tsens_calibration_mode == TSENS_TWO_POINT_CALIB) || - (tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2)) { - tsens_base0_data = (calib_data[0] & TSENS_8X26_BASE0_MASK) - >> TSENS_8X26_BASE0_SHIFT; - tsens0_point1 = (calib_data[0] & TSENS0_8X26_POINT1_MASK) >> - TSENS0_8X26_POINT1_SHIFT; - tsens1_point1 = calib_data[1] & TSENS1_8X26_POINT1_MASK; - tsens2_point1 = (calib_data[1] & TSENS2_8X26_POINT1_MASK) >> - TSENS2_8X26_POINT1_SHIFT; - tsens3_point1 = (calib_data[1] & TSENS3_8X26_POINT1_MASK) >> - TSENS3_8X26_POINT1_SHIFT; - tsens4_point1 = (calib_data[1] & TSENS4_8X26_POINT1_MASK) >> - TSENS4_8X26_POINT1_SHIFT; - tsens5_point1 = (calib_data[1] & TSENS5_8X26_POINT1_MASK) >> - TSENS5_8X26_POINT1_SHIFT; - tsens6_point1 = (calib_data[2] & TSENS6_8X26_POINT1_MASK) >> - TSENS6_8X26_POINT1_SHIFT; - } else - goto calibration_less_mode; - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base1_data = (calib_data[3] & TSENS_8X26_BASE1_MASK); - tsens0_point2 = (calib_data[3] & TSENS0_8X26_POINT2_MASK) >> - TSENS0_8X26_POINT2_SHIFT; - tsens1_point2 = (calib_data[3] & TSENS1_8X26_POINT2_MASK) >> - TSENS1_8X26_POINT2_SHIFT; - tsens2_point2 = (calib_data[3] & TSENS2_8X26_POINT2_MASK) >> - TSENS2_8X26_POINT2_SHIFT; - tsens3_point2 = (calib_data[3] & TSENS3_8X26_POINT2_MASK) >> - TSENS3_8X26_POINT2_SHIFT; - tsens4_point2 = (calib_data[4] & TSENS4_8X26_POINT2_MASK) >> - TSENS4_8X26_POINT2_SHIFT; - tsens5_point2 = (calib_data[4] & TSENS5_8X26_POINT2_MASK) >> - TSENS5_8X26_POINT2_SHIFT; - tsens6_point2 = (calib_data[5] & TSENS6_8X26_POINT2_MASK) >> - TSENS6_8X26_POINT2_SHIFT; - } - - if (tsens_calibration_mode == 0) { -calibration_less_mode: - pr_debug("TSENS is calibrationless mode\n"); - for (i = 0; i < tmdev->tsens_num_sensor; i++) - calib_tsens_point2_data[i] = 780; - calib_tsens_point1_data[0] = 595; - calib_tsens_point1_data[1] = 625; - calib_tsens_point1_data[2] = 553; - calib_tsens_point1_data[3] = 578; - calib_tsens_point1_data[4] = 505; - calib_tsens_point1_data[5] = 509; - calib_tsens_point1_data[6] = 507; - goto compute_intercept_slope; - } - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - calib_tsens_point1_data[0] = - ((((tsens_base0_data) + tsens0_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[1] = - ((((tsens_base0_data) + tsens1_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[2] = - ((((tsens_base0_data) + tsens2_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[3] = - ((((tsens_base0_data) + tsens3_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[4] = - ((((tsens_base0_data) + tsens4_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[5] = - ((((tsens_base0_data) + tsens5_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[6] = - ((((tsens_base0_data) + tsens6_point1) << 2) | - TSENS_BIT_APPEND); - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - pr_debug("two point calibration calculation\n"); - calib_tsens_point2_data[0] = - (((tsens_base1_data + tsens0_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[1] = - (((tsens_base1_data + tsens1_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[2] = - (((tsens_base1_data + tsens2_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[3] = - (((tsens_base1_data + tsens3_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[4] = - (((tsens_base1_data + tsens4_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[5] = - (((tsens_base1_data + tsens5_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[6] = - (((tsens_base1_data + tsens6_point2) << 2) | - TSENS_BIT_APPEND); - } - -compute_intercept_slope: - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0; - - tmdev->sensor[i].calib_data_point2 = calib_tsens_point2_data[i]; - tmdev->sensor[i].calib_data_point1 = calib_tsens_point1_data[i]; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - temp_120_degc - temp_30_degc (x2 - x1) */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - tmdev->sensor[i].offset = (tmdev->sensor[i].calib_data_point1 * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - - return 0; -} - -static int tsens_calib_8974_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base1_data = 0, tsens0_point1 = 0, tsens1_point1 = 0; - int tsens2_point1 = 0, tsens3_point1 = 0, tsens4_point1 = 0; - int tsens5_point1 = 0, tsens6_point1 = 0, tsens7_point1 = 0; - int tsens8_point1 = 0, tsens9_point1 = 0, tsens10_point1 = 0; - int tsens0_point2 = 0, tsens1_point2 = 0, tsens2_point2 = 0; - int tsens3_point2 = 0, tsens4_point2 = 0, tsens5_point2 = 0; - int tsens6_point2 = 0, tsens7_point2 = 0, tsens8_point2 = 0; - int tsens9_point2 = 0, tsens10_point2 = 0; - int tsens_base2_data = 0, tsens_calibration_mode = 0, temp = 0; - uint32_t calib_data[6], calib_redun_sel, calib_data_backup[4]; - uint32_t calib_tsens_point1_data[11], calib_tsens_point2_data[11]; - - if (tmdev->calibration_less_mode) - goto calibration_less_mode; - - calib_redun_sel = readl_relaxed( - TSENS_EEPROM_REDUNDANCY_SEL(tmdev->tsens_calib_addr)); - calib_redun_sel = calib_redun_sel & TSENS_QFPROM_BACKUP_REDUN_SEL; - calib_redun_sel >>= TSENS_QFPROM_BACKUP_REDUN_SHIFT; - pr_debug("calib_redun_sel:%x\n", calib_redun_sel); - - for (i = 0; i < TSENS_MAIN_CALIB_ADDR_RANGE; i++) { - calib_data[i] = readl_relaxed( - (TSENS_EEPROM(tmdev->tsens_calib_addr)) - + (i * TSENS_SN_ADDR_OFFSET)); - pr_debug("calib raw data row%d:0x%x\n", i, calib_data[i]); - } - - if (calib_redun_sel == TSENS_QFPROM_BACKUP_SEL) { - tsens_calibration_mode = (calib_data[4] & TSENS_CAL_SEL_0_1) - >> TSENS_CAL_SEL_SHIFT; - temp = (calib_data[5] & TSENS_CAL_SEL_2) - >> TSENS_CAL_SEL_SHIFT_2; - tsens_calibration_mode |= temp; - pr_debug("backup calib mode:%x\n", calib_redun_sel); - - for (i = 0; i < TSENS_BACKUP_CALIB_ADDR_RANGE; i++) - calib_data_backup[i] = readl_relaxed( - (TSENS_EEPROM_BACKUP_REGION( - tmdev->tsens_calib_addr)) - + (i * TSENS_SN_ADDR_OFFSET)); - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB) - || (tsens_calibration_mode == - TSENS_TWO_POINT_CALIB) || - (tsens_calibration_mode == - TSENS_ONE_POINT_CALIB_OPTION_2)) { - tsens_base1_data = (calib_data_backup[0] & - TSENS_BASE1_MASK); - tsens0_point1 = (calib_data_backup[0] & - TSENS0_POINT1_MASK) >> - TSENS0_POINT1_SHIFT; - tsens1_point1 = (calib_data_backup[0] & - TSENS1_POINT1_MASK) >> TSENS1_POINT1_SHIFT; - tsens2_point1 = (calib_data_backup[0] & - TSENS2_POINT1_MASK) >> TSENS2_POINT1_SHIFT; - tsens3_point1 = (calib_data_backup[0] & - TSENS3_POINT1_MASK) >> TSENS3_POINT1_SHIFT; - tsens4_point1 = (calib_data_backup[1] & - TSENS4_POINT1_MASK); - tsens5_point1 = (calib_data_backup[1] & - TSENS5_POINT1_MASK) >> TSENS5_POINT1_SHIFT; - tsens6_point1 = (calib_data_backup[1] & - TSENS6_POINT1_MASK) >> TSENS6_POINT1_SHIFT; - tsens7_point1 = (calib_data_backup[1] & - TSENS7_POINT1_MASK) >> TSENS7_POINT1_SHIFT; - tsens8_point1 = (calib_data_backup[2] & - TSENS8_POINT1_MASK_BACKUP) >> - TSENS8_POINT1_SHIFT; - tsens9_point1 = (calib_data_backup[2] & - TSENS9_POINT1_MASK_BACKUP) >> - TSENS9_POINT1_BACKUP_SHIFT; - tsens10_point1 = (calib_data_backup[2] & - TSENS10_POINT1_MASK_BACKUP) >> - TSENS10_POINT1_BACKUP_SHIFT; - } else - goto calibration_less_mode; - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base2_data = (calib_data_backup[2] & - TSENS_BASE2_BACKUP_MASK) >> - TSENS_POINT2_BASE_BACKUP_SHIFT; - tsens0_point2 = (calib_data_backup[2] & - TSENS0_POINT2_BACKUP_MASK) >> - TSENS0_POINT2_BACKUP_SHIFT; - tsens1_point2 = (calib_data_backup[3] & - TSENS1_POINT2_BACKUP_MASK); - tsens2_point2 = (calib_data_backup[3] & - TSENS2_POINT2_BACKUP_MASK) >> - TSENS2_POINT2_BACKUP_SHIFT; - tsens3_point2 = (calib_data_backup[3] & - TSENS3_POINT2_BACKUP_MASK) >> - TSENS3_POINT2_BACKUP_SHIFT; - tsens4_point2 = (calib_data_backup[3] & - TSENS4_POINT2_BACKUP_MASK) >> - TSENS4_POINT2_BACKUP_SHIFT; - tsens5_point2 = (calib_data[4] & - TSENS5_POINT2_BACKUP_MASK) >> - TSENS5_POINT2_BACKUP_SHIFT; - tsens6_point2 = (calib_data[5] & - TSENS6_POINT2_BACKUP_MASK); - tsens7_point2 = (calib_data[5] & - TSENS7_POINT2_BACKUP_MASK) >> - TSENS7_POINT2_BACKUP_SHIFT; - tsens8_point2 = (calib_data[5] & - TSENS8_POINT2_BACKUP_MASK) >> - TSENS8_POINT2_BACKUP_SHIFT; - tsens9_point2 = (calib_data[5] & - TSENS9_POINT2_BACKUP_MASK) >> - TSENS9_POINT2_BACKUP_SHIFT; - tsens10_point2 = (calib_data[5] & - TSENS10_POINT2_BACKUP_MASK) - >> TSENS10_POINT2_BACKUP_SHIFT; - } - } else { - tsens_calibration_mode = (calib_data[1] & TSENS_CAL_SEL_0_1) - >> TSENS_CAL_SEL_SHIFT; - temp = (calib_data[3] & TSENS_CAL_SEL_2) - >> TSENS_CAL_SEL_SHIFT_2; - tsens_calibration_mode |= temp; - pr_debug("calib mode scheme:%x\n", tsens_calibration_mode); - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB) || - (tsens_calibration_mode == - TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - tsens_base1_data = (calib_data[0] & TSENS_BASE1_MASK); - tsens0_point1 = (calib_data[0] & TSENS0_POINT1_MASK) >> - TSENS0_POINT1_SHIFT; - tsens1_point1 = (calib_data[0] & TSENS1_POINT1_MASK) >> - TSENS1_POINT1_SHIFT; - tsens2_point1 = (calib_data[0] & TSENS2_POINT1_MASK) >> - TSENS2_POINT1_SHIFT; - tsens3_point1 = (calib_data[0] & TSENS3_POINT1_MASK) >> - TSENS3_POINT1_SHIFT; - tsens4_point1 = (calib_data[1] & TSENS4_POINT1_MASK); - tsens5_point1 = (calib_data[1] & TSENS5_POINT1_MASK) >> - TSENS5_POINT1_SHIFT; - tsens6_point1 = (calib_data[1] & TSENS6_POINT1_MASK) >> - TSENS6_POINT1_SHIFT; - tsens7_point1 = (calib_data[1] & TSENS7_POINT1_MASK) >> - TSENS7_POINT1_SHIFT; - tsens8_point1 = (calib_data[1] & TSENS8_POINT1_MASK) >> - TSENS8_POINT1_SHIFT; - tsens9_point1 = (calib_data[2] & TSENS9_POINT1_MASK); - tsens10_point1 = (calib_data[2] & TSENS10_POINT1_MASK) - >> TSENS10_POINT1_SHIFT; - } else - goto calibration_less_mode; - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base2_data = (calib_data[2] & TSENS_BASE2_MASK) >> - TSENS_POINT2_BASE_SHIFT; - tsens0_point2 = (calib_data[2] & TSENS0_POINT2_MASK) >> - TSENS0_POINT2_SHIFT; - tsens1_point2 = (calib_data[2] & TSENS1_POINT2_MASK) >> - TSENS1_POINT2_SHIFT; - tsens2_point2 = (calib_data[3] & TSENS2_POINT2_MASK); - tsens3_point2 = (calib_data[3] & TSENS3_POINT2_MASK) >> - TSENS3_POINT2_SHIFT; - tsens4_point2 = (calib_data[3] & TSENS4_POINT2_MASK) >> - TSENS4_POINT2_SHIFT; - tsens5_point2 = (calib_data[3] & TSENS5_POINT2_MASK) >> - TSENS5_POINT2_SHIFT; - tsens6_point2 = (calib_data[3] & TSENS6_POINT2_MASK) >> - TSENS6_POINT2_SHIFT; - tsens7_point2 = (calib_data[4] & TSENS7_POINT2_MASK); - tsens8_point2 = (calib_data[4] & TSENS8_POINT2_MASK) >> - TSENS8_POINT2_SHIFT; - tsens9_point2 = (calib_data[4] & TSENS9_POINT2_MASK) >> - TSENS9_POINT2_SHIFT; - tsens10_point2 = (calib_data[4] & TSENS10_POINT2_MASK) - >> TSENS10_POINT2_SHIFT; - } - - if (tsens_calibration_mode == 0) { -calibration_less_mode: - pr_debug("TSENS is calibrationless mode\n"); - for (i = 0; i < tmdev->tsens_num_sensor; i++) - calib_tsens_point2_data[i] = 780; - calib_tsens_point1_data[0] = 502; - calib_tsens_point1_data[1] = 509; - calib_tsens_point1_data[2] = 503; - calib_tsens_point1_data[3] = 509; - calib_tsens_point1_data[4] = 505; - calib_tsens_point1_data[5] = 509; - calib_tsens_point1_data[6] = 507; - calib_tsens_point1_data[7] = 510; - calib_tsens_point1_data[8] = 508; - calib_tsens_point1_data[9] = 509; - calib_tsens_point1_data[10] = 508; - goto compute_intercept_slope; - } - } - - if (tsens_calibration_mode == TSENS_ONE_POINT_CALIB) { - calib_tsens_point1_data[0] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens0_point1; - calib_tsens_point1_data[1] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens1_point1; - calib_tsens_point1_data[2] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens2_point1; - calib_tsens_point1_data[3] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens3_point1; - calib_tsens_point1_data[4] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens4_point1; - calib_tsens_point1_data[5] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens5_point1; - calib_tsens_point1_data[6] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens6_point1; - calib_tsens_point1_data[7] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens7_point1; - calib_tsens_point1_data[8] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens8_point1; - calib_tsens_point1_data[9] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens9_point1; - calib_tsens_point1_data[10] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens10_point1; - } - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - pr_debug("one point calibration calculation\n"); - calib_tsens_point1_data[0] = - ((((tsens_base1_data) + tsens0_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[1] = - ((((tsens_base1_data) + tsens1_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[2] = - ((((tsens_base1_data) + tsens2_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[3] = - ((((tsens_base1_data) + tsens3_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[4] = - ((((tsens_base1_data) + tsens4_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[5] = - ((((tsens_base1_data) + tsens5_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[6] = - ((((tsens_base1_data) + tsens6_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[7] = - ((((tsens_base1_data) + tsens7_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[8] = - ((((tsens_base1_data) + tsens8_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[9] = - ((((tsens_base1_data) + tsens9_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[10] = - ((((tsens_base1_data) + tsens10_point1) << 2) | - TSENS_BIT_APPEND); - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - pr_debug("two point calibration calculation\n"); - calib_tsens_point2_data[0] = - (((tsens_base2_data + tsens0_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[1] = - (((tsens_base2_data + tsens1_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[2] = - (((tsens_base2_data + tsens2_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[3] = - (((tsens_base2_data + tsens3_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[4] = - (((tsens_base2_data + tsens4_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[5] = - (((tsens_base2_data + tsens5_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[6] = - (((tsens_base2_data + tsens6_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[7] = - (((tsens_base2_data + tsens7_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[8] = - (((tsens_base2_data + tsens8_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[9] = - (((tsens_base2_data + tsens9_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[10] = - (((tsens_base2_data + tsens10_point2) << 2) | - TSENS_BIT_APPEND); - } - -compute_intercept_slope: - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0; - - tmdev->sensor[i].calib_data_point2 = calib_tsens_point2_data[i]; - tmdev->sensor[i].calib_data_point1 = calib_tsens_point1_data[i]; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - temp_120_degc - temp_30_degc (x2 - x1) */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - tmdev->sensor[i].offset = (tmdev->sensor[i].calib_data_point1 * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d\n", tmdev->sensor[i].offset); - tmdev->prev_reading_avail = false; - } - - return 0; -} - -static int tsens_calib_9900_sensors(struct tsens_tm_device *tmdev) -{ - int i, tsens_base1_data = 0, tsens0_point1 = 0, tsens1_point1 = 0; - int tsens2_point1 = 0, tsens3_point1 = 0, tsens4_point1 = 0; - int tsens5_point1 = 0, tsens6_point1 = 0, tsens0_point2 = 0; - int tsens1_point2 = 0, tsens2_point2 = 0, tsens3_point2 = 0; - int tsens4_point2 = 0, tsens5_point2 = 0, tsens6_point2 = 0; - int tsens_base2_data = 0, tsens_calibration_mode = 0; - uint32_t calib_data[4], calib_redun_sel, calib_data_backup[4]; - uint32_t calib_tsens_point1_data[7], calib_tsens_point2_data[7]; - - if (tmdev->calibration_less_mode) - goto calibration_less_mode; - - calib_redun_sel = readl_relaxed( - TSENS_9900_EEPROM_REDUNDANCY_SEL(tmdev->tsens_calib_addr)); - calib_redun_sel = calib_redun_sel & TSENS_QFPROM_BACKUP_9900_REDUN_SEL; - calib_redun_sel >>= TSENS_QFPROM_BACKUP_9900_REDUN_SHIFT; - pr_debug("calib_redun_sel:%x\n", calib_redun_sel); - - if (calib_redun_sel == TSENS_QFPROM_BACKUP_SEL) { - for (i = 0; i < TSENS_9900_CALIB_ADDR_RANGE; i++) { - calib_data_backup[i] = readl_relaxed( - (TSENS_9900_EEPROM_BACKUP_REGION( - tmdev->tsens_calib_addr)) - + (i * TSENS_SN_ADDR_OFFSET)); - pr_debug("backup calib raw data row%d:0x%x\n", - i, calib_data_backup[i]); - } - - tsens_calibration_mode = (calib_data_backup[0] & - TSENS_9900_TSENS_CAL_SEL) >> TSENS_9900_CAL_SEL_SHIFT; - pr_debug("backup calib mode:%x\n", tsens_calibration_mode); - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB) - || (tsens_calibration_mode == - TSENS_TWO_POINT_CALIB) || - (tsens_calibration_mode == - TSENS_ONE_POINT_CALIB_OPTION_2)) { - tsens_base1_data = (calib_data_backup[0] & - TSENS_9900_BASE1_MASK); - tsens0_point1 = (calib_data_backup[0] & - TSENS0_9900_POINT1_MASK) >> - TSENS0_9900_POINT1_SHIFT; - tsens1_point1 = (calib_data_backup[1] & - TSENS1_9900_POINT1_MASK); - tsens2_point1 = (calib_data_backup[1] & - TSENS2_9900_POINT1_MASK) >> - TSENS2_9900_POINT1_SHIFT; - tsens3_point1 = (calib_data_backup[1] & - TSENS3_9900_POINT1_MASK) >> - TSENS3_9900_POINT1_SHIFT; - tsens4_point1 = (calib_data_backup[2] & - TSENS4_9900_POINT1_MASK) >> - TSENS4_9900_POINT1_SHIFT; - tsens5_point1 = (calib_data_backup[2] & - TSENS5_9900_POINT1_MASK) >> - TSENS5_9900_POINT1_SHIFT; - tsens6_point1 = (calib_data_backup[3] & - TSENS6_9900_POINT1_MASK); - } else - goto calibration_less_mode; - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base2_data = (calib_data_backup[0] & - TSENS_9900_BASE2_MASK) >> - TSENS_9900_BASE2_SHIFT; - tsens0_point2 = (calib_data_backup[0] & - TSENS0_9900_POINT2_MASK) >> - TSENS0_9900_POINT2_SHIFT; - tsens1_point2 = (calib_data_backup[1] & - TSENS1_9900_POINT2_MASK)>> - TSENS1_9900_POINT2_SHIFT; - tsens2_point2 = (calib_data_backup[1] & - TSENS2_9900_POINT2_MASK) >> - TSENS2_9900_POINT2_SHIFT; - tsens3_point2 = (calib_data_backup[2] & - TSENS3_9900_POINT2_MASK); - tsens4_point2 = (calib_data_backup[2] & - TSENS4_9900_POINT2_MASK) >> - TSENS4_9900_POINT2_SHIFT; - tsens5_point2 = (calib_data_backup[2] & - TSENS5_9900_POINT2_MASK) >> - TSENS5_9900_POINT2_SHIFT; - tsens6_point2 = (calib_data_backup[3] & - TSENS6_9900_POINT2_MASK) >> - TSENS6_9900_POINT2_SHIFT; - } - } else { - for (i = 0; i < TSENS_9900_CALIB_ADDR_RANGE; i++) { - calib_data[i] = readl_relaxed( - (TSENS_9900_EEPROM(tmdev->tsens_calib_addr)) - + (i * TSENS_SN_ADDR_OFFSET)); - pr_debug("calib raw data row%d:0x%x\n", i , calib_data[i]); - } - - tsens_calibration_mode = (calib_data[0] & - TSENS_9900_TSENS_CAL_SEL) >> TSENS_9900_CAL_SEL_SHIFT; - pr_debug("calib mode:%x\n", tsens_calibration_mode); - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB) || - (tsens_calibration_mode == - TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - tsens_base1_data = (calib_data[0] & - TSENS_9900_BASE1_MASK); - tsens0_point1 = (calib_data[0] & - TSENS0_9900_POINT1_MASK) >> - TSENS0_9900_POINT1_SHIFT; - tsens1_point1 = (calib_data[1] & - TSENS1_9900_POINT1_MASK); - tsens2_point1 = (calib_data[1] & - TSENS2_9900_POINT1_MASK) >> - TSENS2_9900_POINT1_SHIFT; - tsens3_point1 = (calib_data[1] & - TSENS3_9900_POINT1_MASK) >> - TSENS3_9900_POINT1_SHIFT; - tsens4_point1 = (calib_data[2] & - TSENS4_9900_POINT1_MASK) >> - TSENS4_9900_POINT1_SHIFT; - tsens5_point1 = (calib_data[2] & - TSENS5_9900_POINT1_MASK) >> - TSENS5_9900_POINT1_SHIFT; - tsens6_point1 = (calib_data[3] & - TSENS6_9900_POINT1_MASK); - } else - goto calibration_less_mode; - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base2_data = (calib_data[0] & - TSENS_9900_BASE2_MASK) >> - TSENS_9900_BASE2_SHIFT; - tsens0_point2 = (calib_data[0] & - TSENS0_9900_POINT2_MASK) >> - TSENS0_9900_POINT2_SHIFT; - tsens1_point2 = (calib_data[1] & - TSENS1_9900_POINT2_MASK) >> - TSENS1_9900_POINT2_SHIFT; - tsens2_point2 = (calib_data[1] & - TSENS2_9900_POINT2_MASK)>> - TSENS2_9900_POINT2_SHIFT; - tsens3_point2 = (calib_data[2] & - TSENS3_9900_POINT2_MASK); - tsens4_point2 = (calib_data[2] & - TSENS4_9900_POINT2_MASK) >> - TSENS4_9900_POINT2_SHIFT; - tsens5_point2 = (calib_data[2] & - TSENS5_9900_POINT2_MASK) >> - TSENS5_9900_POINT2_SHIFT; - tsens6_point2 = (calib_data[3] & - TSENS6_9900_POINT2_MASK) >> - TSENS6_9900_POINT2_SHIFT; - } - - if (tsens_calibration_mode == 0) { -calibration_less_mode: - pr_debug("TSENS is calibrationless mode\n"); - for (i = 0; i < tmdev->tsens_num_sensor; i++) - calib_tsens_point2_data[i] = 780; - calib_tsens_point1_data[0] = 502; - calib_tsens_point1_data[1] = 509; - calib_tsens_point1_data[2] = 503; - calib_tsens_point1_data[3] = 509; - calib_tsens_point1_data[4] = 505; - calib_tsens_point1_data[5] = 509; - calib_tsens_point1_data[6] = 507; - goto compute_intercept_slope; - } - } - - if (tsens_calibration_mode == TSENS_ONE_POINT_CALIB) { - calib_tsens_point1_data[0] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens0_point1; - calib_tsens_point1_data[1] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens1_point1; - calib_tsens_point1_data[2] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens2_point1; - calib_tsens_point1_data[3] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens3_point1; - calib_tsens_point1_data[4] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens4_point1; - calib_tsens_point1_data[5] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens5_point1; - calib_tsens_point1_data[6] = - (((tsens_base1_data) << 2) | TSENS_BIT_APPEND) - + tsens6_point1; - } - - if ((tsens_calibration_mode == TSENS_ONE_POINT_CALIB_OPTION_2) || - (tsens_calibration_mode == TSENS_TWO_POINT_CALIB)) { - pr_debug("one point calibration calculation\n"); - calib_tsens_point1_data[0] = - ((((tsens_base1_data) + tsens0_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[1] = - ((((tsens_base1_data) + tsens1_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[2] = - ((((tsens_base1_data) + tsens2_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[3] = - ((((tsens_base1_data) + tsens3_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[4] = - ((((tsens_base1_data) + tsens4_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[5] = - ((((tsens_base1_data) + tsens5_point1) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point1_data[6] = - ((((tsens_base1_data) + tsens6_point1) << 2) | - TSENS_BIT_APPEND); - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - pr_debug("two point calibration calculation\n"); - calib_tsens_point2_data[0] = - (((tsens_base2_data + tsens0_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[1] = - (((tsens_base2_data + tsens1_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[2] = - (((tsens_base2_data + tsens2_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[3] = - (((tsens_base2_data + tsens3_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[4] = - (((tsens_base2_data + tsens4_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[5] = - (((tsens_base2_data + tsens5_point2) << 2) | - TSENS_BIT_APPEND); - calib_tsens_point2_data[6] = - (((tsens_base2_data + tsens6_point2) << 2) | - TSENS_BIT_APPEND); - } - -compute_intercept_slope: - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0; - - tmdev->sensor[i].calib_data_point2 = calib_tsens_point2_data[i]; - tmdev->sensor[i].calib_data_point1 = calib_tsens_point1_data[i]; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - temp_120_degc - temp_30_degc (x2 - x1) */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - tmdev->sensor[i].offset = (tmdev->sensor[i].calib_data_point1 * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d\n", tmdev->sensor[i].offset); - tmdev->prev_reading_avail = false; - } - - return 0; -} - -static int tsens_calib_msmzirc_sensors(struct tsens_tm_device *tmdev) -{ - int i = 0, tsens_base0_data = 0, tsens_base1_data = 0; - int tsens0_point = 0, tsens1_point = 0, tsens2_point = 0; - int tsens3_point = 0, tsens4_point = 0; - int tsens_calibration_mode = 0; - uint32_t calib_data[2] = {0, 0}; - uint32_t calib_tsens_point_data[5]; - - if (!tmdev->calibration_less_mode) { - calib_data[0] = readl_relaxed( - TSENS_EEPROM(tmdev->tsens_calib_addr)); - calib_data[1] = readl_relaxed( - (TSENS_EEPROM(tmdev->tsens_calib_addr) + 0x4)); - - tsens_calibration_mode = - (calib_data[1] & TSENS_ZIRC_CAL_SEL) >> - TSENS_ZIRC_CAL_SEL_SHIFT; - pr_debug("calib mode is %d\n", tsens_calibration_mode); - } - - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - tsens_base0_data = (calib_data[0] & TSENS_BASE0_ZIRC_MASK); - tsens_base1_data = (calib_data[0] & TSENS_BASE1_ZIRC_MASK) >> - TSENS_BASE1_ZIRC_SHIFT; - tsens0_point = (calib_data[0] & TSENS0_OFFSET_ZIRC_MASK) >> - TSENS0_OFFSET_ZIRC_SHIFT; - tsens1_point = (calib_data[0] & TSENS1_OFFSET_ZIRC_MASK) >> - TSENS1_OFFSET_ZIRC_SHIFT; - tsens2_point = (calib_data[0] & TSENS2_OFFSET_ZIRC_MASK) >> - TSENS2_OFFSET_ZIRC_SHIFT; - tsens3_point = (calib_data[1] & TSENS3_OFFSET_ZIRC_MASK); - tsens4_point = (calib_data[1] & TSENS4_OFFSET_ZIRC_MASK) >> - TSENS4_OFFSET_ZIRC_SHIFT; - calib_tsens_point_data[0] = tsens0_point; - calib_tsens_point_data[1] = tsens1_point; - calib_tsens_point_data[2] = tsens2_point; - calib_tsens_point_data[3] = tsens3_point; - calib_tsens_point_data[4] = tsens4_point; - } else { - if (tsens_calibration_mode == 0) { - pr_debug("TSENS is calibrationless mode\n"); - calib_tsens_point_data[0] = 532; - calib_tsens_point_data[1] = 532; - calib_tsens_point_data[2] = 532; - calib_tsens_point_data[3] = 532; - calib_tsens_point_data[4] = 532; - } - } - - for (i = 0; i < tmdev->tsens_num_sensor; i++) { - int32_t num = 0, den = 0, adc_code_of_tempx = 0; - - tmdev->sensor[i].calib_data_point2 = tsens_base1_data; - tmdev->sensor[i].calib_data_point1 = tsens_base0_data; - pr_debug("sensor:%d - calib_data_point1:0x%x, calib_data_point2:0x%x\n", - i, tmdev->sensor[i].calib_data_point1, - tmdev->sensor[i].calib_data_point2); - if (tsens_calibration_mode == TSENS_TWO_POINT_CALIB) { - /* slope (m) = adc_code2 - adc_code1 (y2 - y1)/ - * temp_120_degc - temp_30_degc (x2 - x1) */ - num = tmdev->sensor[i].calib_data_point2 - - tmdev->sensor[i].calib_data_point1; - num *= tmdev->tsens_factor; - den = TSENS_CAL_DEGC_POINT2 - TSENS_CAL_DEGC_POINT1; - tmdev->sensor[i].slope_mul_tsens_factor = num/den; - } - adc_code_of_tempx = - tsens_base0_data + calib_tsens_point_data[i]; - pr_debug("offset_adc_code_of_tempx:0x%x\n", - adc_code_of_tempx); - tmdev->sensor[i].offset = (adc_code_of_tempx * - tmdev->tsens_factor) - (TSENS_CAL_DEGC_POINT1 * - tmdev->sensor[i].slope_mul_tsens_factor); - pr_debug("offset:%d and slope:%d\n", tmdev->sensor[i].offset, - tmdev->sensor[i].slope_mul_tsens_factor); - tmdev->prev_reading_avail = false; - } - - return 0; -} -static int tsens_calib_sensors(struct tsens_tm_device *tmdev) -{ - int rc = 0; - - pr_debug("%s\n", __func__); - - if (!tmdev) - return -ENODEV; - - if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_8974) - rc = tsens_calib_8974_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_8X26) - rc = tsens_calib_8x26_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_8X10) - rc = tsens_calib_8x10_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_9900) - rc = tsens_calib_9900_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_9630) - rc = tsens_calib_9630_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_8916) - rc = tsens_calib_8916_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_8939) - rc = tsens_calib_8939_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_8994) - rc = tsens_calib_8994_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_MSM8909) - rc = tsens_calib_msm8909_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_MSMZIRC) - rc = tsens_calib_msmzirc_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_8992) - rc = tsens_calib_8992_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_MSM8952) - rc = tsens_calib_msm8952_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_MDM9607) - rc = tsens_calib_mdm9607_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_MSM8937) - rc = tsens_calib_msm8937_msmgold_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_MSMGOLD) - rc = tsens_calib_msm8937_msmgold_sensors(tmdev); - else if (tmdev->calib_mode == TSENS_CALIB_FUSE_MAP_NONE) { - pr_debug("Fuse map info not required\n"); - rc = 0; - } else { - pr_err("TSENS Calib fuse not found\n"); - rc = -ENODEV; - } - - return rc; -} - static int get_device_tree_data(struct platform_device *pdev, struct tsens_tm_device *tmdev) { @@ -5436,7 +2176,6 @@ static int get_device_tree_data(struct platform_device *pdev, "qcom,calibration-less-mode"); tmdev->tsens_local_init = of_property_read_bool(of_node, "qcom,tsens-local-init"); - tmdev->calib_mode = (u32)(uintptr_t) id->data; sensor_id = devm_kzalloc(&pdev->dev, tsens_num_sensors * sizeof(u32), GFP_KERNEL); @@ -5498,41 +2237,27 @@ static int get_device_tree_data(struct platform_device *pdev, tmdev->wd_bark_val = wd_bark; } - if (!strcmp(id->compatible, "qcom,mdm9630-tsens") || - (!strcmp(id->compatible, "qcom,msmzirc-tsens")) || - (!strcmp(id->compatible, "qcom,msm8994-tsens")) || - (!strcmp(id->compatible, "qcom,msm8992-tsens"))) - tmdev->tsens_type = TSENS_TYPE2; - else if (!strcmp(id->compatible, "qcom,msm8996-tsens") || + if (!strcmp(id->compatible, "qcom,msm8996-tsens") || (!strcmp(id->compatible, "qcom,msm8998-tsens"))) tmdev->tsens_type = TSENS_TYPE3; else if (!strcmp(id->compatible, "qcom,msmtitanium-tsens") || - (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || - (!strcmp(id->compatible, "qcom,msmtriton-tsens") || - (!strcmp(id->compatible, "qcom,msmhamster-tsens"))))) { + (!strcmp(id->compatible, "qcom,sdm660-tsens")) || + (!strcmp(id->compatible, "qcom,sdm630-tsens")) || + (!strcmp(id->compatible, "qcom,msmhamster-tsens"))) { tmdev->tsens_type = TSENS_TYPE3; tsens_poll_check = 0; - } else if (!strcmp(id->compatible, "qcom,msm8952-tsens") || - (!strcmp(id->compatible, "qcom,msmgold-tsens")) || - (!strcmp(id->compatible, "qcom,msm8937-tsens"))) - tmdev->tsens_type = TSENS_TYPE4; - else + } else tmdev->tsens_type = TSENS_TYPE0; tmdev->tsens_valid_status_check = of_property_read_bool(of_node, "qcom,valid-status-check"); if (!tmdev->tsens_valid_status_check) { - if (!strcmp(id->compatible, "qcom,msm8994-tsens") || - (!strcmp(id->compatible, "qcom,msmzirc-tsens")) || - (!strcmp(id->compatible, "qcom,msm8992-tsens")) || - (!strcmp(id->compatible, "qcom,msm8996-tsens")) || - (!strcmp(id->compatible, "qcom,msm8952-tsens")) || - (!strcmp(id->compatible, "qcom,msm8937-tsens")) || + if (!strcmp(id->compatible, "qcom,msm8996-tsens") || (!strcmp(id->compatible, "qcom,msmtitanium-tsens")) || (!strcmp(id->compatible, "qcom,msm8998-tsens")) || - (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || - (!strcmp(id->compatible, "qcom,msmtriton-tsens") || - (!strcmp(id->compatible, "qcom,msmhamster-tsens"))))) + (!strcmp(id->compatible, "qcom,sdm660-tsens")) || + (!strcmp(id->compatible, "qcom,sdm630-tsens")) || + (!strcmp(id->compatible, "qcom,msmhamster-tsens"))) tmdev->tsens_valid_status_check = true; } @@ -5547,9 +2272,9 @@ static int get_device_tree_data(struct platform_device *pdev, if (!strcmp(id->compatible, "qcom,msm8996-tsens") || (!strcmp(id->compatible, "qcom,msm8998-tsens")) || (!strcmp(id->compatible, "qcom,msmhamster-tsens")) || - (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || - (!strcmp(id->compatible, "qcom,msmtriton-tsens") || - (!strcmp(id->compatible, "qcom,msmtitanium-tsens"))))) { + (!strcmp(id->compatible, "qcom,sdm660-tsens")) || + (!strcmp(id->compatible, "qcom,sdm630-tsens")) || + (!strcmp(id->compatible, "qcom,msmtitanium-tsens"))) { tmdev->tsens_critical_irq = platform_get_irq_byname(pdev, "tsens-critical"); @@ -5690,12 +2415,6 @@ static int tsens_tm_probe(struct platform_device *pdev) goto fail; } - rc = tsens_calib_sensors(tmdev); - if (rc < 0) { - pr_err("Calibration failed\n"); - goto fail; - } - rc = tsens_hw_init(tmdev); if (rc) return rc; diff --git a/drivers/video/fbdev/msm/mdss.h b/drivers/video/fbdev/msm/mdss.h index 23a5ef2af249..0cdf91da920c 100644 --- a/drivers/video/fbdev/msm/mdss.h +++ b/drivers/video/fbdev/msm/mdss.h @@ -164,6 +164,7 @@ enum mdss_hw_quirk { MDSS_QUIRK_SRC_SPLIT_ALWAYS, MDSS_QUIRK_MMSS_GDSC_COLLAPSE, MDSS_QUIRK_MDP_CLK_SET_RATE, + MDSS_QUIRK_HDR_SUPPORT_ENABLED, MDSS_QUIRK_MAX, }; diff --git a/drivers/video/fbdev/msm/mdss_compat_utils.c b/drivers/video/fbdev/msm/mdss_compat_utils.c index 9f1a24431de9..f499cdfd85ef 100644 --- a/drivers/video/fbdev/msm/mdss_compat_utils.c +++ b/drivers/video/fbdev/msm/mdss_compat_utils.c @@ -225,6 +225,7 @@ static struct mdp_input_layer *__create_layer_list( layer->transp_mask = layer32->transp_mask; layer->bg_color = layer32->bg_color; layer->blend_op = layer32->blend_op; + layer->color_space = layer32->color_space; layer->src_rect = layer32->src_rect; layer->dst_rect = layer32->dst_rect; layer->buffer = layer32->buffer; @@ -312,6 +313,8 @@ static int __compat_atomic_commit(struct fb_info *info, unsigned int cmd, ret = -EFAULT; return ret; } + + memset(&commit, 0, sizeof(struct mdp_layer_commit)); __copy_atomic_commit_struct(&commit, &commit32); if (commit32.commit_v1.output_layer) { diff --git a/drivers/video/fbdev/msm/mdss_compat_utils.h b/drivers/video/fbdev/msm/mdss_compat_utils.h index d6f85a493315..626792925cb6 100644 --- a/drivers/video/fbdev/msm/mdss_compat_utils.h +++ b/drivers/video/fbdev/msm/mdss_compat_utils.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,6 +15,15 @@ #ifndef MDSS_COMPAT_UTILS_H #define MDSS_COMPAT_UTILS_H +/* + * To allow proper structure padding for 64bit/32bit target + */ +#ifdef __LP64 +#define MDP_LAYER_COMMIT_V1_PAD 3 +#else +#define MDP_LAYER_COMMIT_V1_PAD 4 +#endif + struct mdp_buf_sync32 { u32 flags; u32 acq_fen_fd_cnt; @@ -498,7 +507,8 @@ struct mdp_input_layer32 { uint16_t z_order; uint32_t transp_mask; uint32_t bg_color; - enum mdss_mdp_blend_op blend_op; + enum mdss_mdp_blend_op blend_op; + enum mdp_color_space color_space; struct mdp_rect src_rect; struct mdp_rect dst_rect; compat_caddr_t scale; @@ -512,7 +522,8 @@ struct mdp_output_layer32 { uint32_t flags; uint32_t writeback_ndx; struct mdp_layer_buffer buffer; - uint32_t reserved[6]; + enum mdp_color_space color_space; + uint32_t reserved[5]; }; struct mdp_layer_commit_v1_32 { uint32_t flags; @@ -523,7 +534,10 @@ struct mdp_layer_commit_v1_32 { uint32_t input_layer_cnt; compat_caddr_t output_layer; int retire_fence; - uint32_t reserved[6]; + compat_caddr_t dest_scaler; + uint32_t dest_scaler_cnt; + compat_caddr_t frc_info; + uint32_t reserved[MDP_LAYER_COMMIT_V1_PAD]; }; struct mdp_layer_commit32 { diff --git a/drivers/video/fbdev/msm/mdss_debug.c b/drivers/video/fbdev/msm/mdss_debug.c index 9ab88d4a7a52..8d06edf01d1d 100644 --- a/drivers/video/fbdev/msm/mdss_debug.c +++ b/drivers/video/fbdev/msm/mdss_debug.c @@ -169,7 +169,8 @@ static ssize_t panel_debug_base_reg_write(struct file *file, break; } /* End of a hex value in given string */ - bufp[NEXT_VALUE_OFFSET - 1] = 0; + if ((bufp + NEXT_VALUE_OFFSET - 1) < (buf + count)) + bufp[NEXT_VALUE_OFFSET - 1] = 0; } if (len < PANEL_CMD_MIN_TX_COUNT) { pr_err("wrong input reg len\n"); diff --git a/drivers/video/fbdev/msm/mdss_dp.c b/drivers/video/fbdev/msm/mdss_dp.c index 7076b36bb6b6..ccf8a0d34a6c 100644 --- a/drivers/video/fbdev/msm/mdss_dp.c +++ b/drivers/video/fbdev/msm/mdss_dp.c @@ -53,21 +53,12 @@ struct mdss_dp_attention_node { }; #define DEFAULT_VIDEO_RESOLUTION HDMI_VFRMT_640x480p60_4_3 -static u32 supported_modes[] = { - HDMI_VFRMT_640x480p60_4_3, - HDMI_VFRMT_720x480p60_4_3, HDMI_VFRMT_720x480p60_16_9, - HDMI_VFRMT_1280x720p60_16_9, - HDMI_VFRMT_1920x1080p60_16_9, - HDMI_VFRMT_3840x2160p24_16_9, HDMI_VFRMT_3840x2160p30_16_9, - HDMI_VFRMT_3840x2160p60_16_9, - HDMI_VFRMT_4096x2160p24_256_135, HDMI_VFRMT_4096x2160p30_256_135, - HDMI_VFRMT_4096x2160p60_256_135, HDMI_EVFRMT_4096x2160p24_16_9 -}; static int mdss_dp_off_irq(struct mdss_dp_drv_pdata *dp_drv); static void mdss_dp_mainlink_push_idle(struct mdss_panel_data *pdata); static inline void mdss_dp_link_retraining(struct mdss_dp_drv_pdata *dp); static void mdss_dp_handle_attention(struct mdss_dp_drv_pdata *dp_drv); +static void dp_send_events(struct mdss_dp_drv_pdata *dp, u32 events); static void mdss_dp_put_dt_clk_data(struct device *dev, struct dss_module_power *module_power) @@ -1003,7 +994,7 @@ static int dp_init_panel_info(struct mdss_dp_drv_pdata *dp_drv, u32 vic) return -EINVAL; } - ret = hdmi_get_supported_mode(&timing, &dp_drv->ds_data, vic); + ret = hdmi_get_supported_mode(&timing, 0, vic); pinfo = &dp_drv->panel_data.panel_info; if (ret || !timing.supported || !pinfo) { @@ -1234,6 +1225,15 @@ static int mdss_dp_on_irq(struct mdss_dp_drv_pdata *dp_drv) dp_drv->power_on = true; + if (dp_drv->psm_enabled) { + ret = mdss_dp_aux_send_psm_request(dp_drv, false); + if (ret) { + pr_err("Failed to exit low power mode, rc=%d\n", + ret); + goto exit; + } + } + ret = mdss_dp_train_main_link(dp_drv); mutex_unlock(&dp_drv->train_mutex); @@ -1301,6 +1301,15 @@ int mdss_dp_on_hpd(struct mdss_dp_drv_pdata *dp_drv) mdss_dp_configure_source_params(dp_drv, &ln_map); + if (dp_drv->psm_enabled) { + ret = mdss_dp_aux_send_psm_request(dp_drv, false); + if (ret) { + pr_err("Failed to exit low power mode, rc=%d\n", ret); + goto exit; + } + } + + link_training: dp_drv->power_on = true; @@ -1387,6 +1396,7 @@ static int mdss_dp_off_irq(struct mdss_dp_drv_pdata *dp_drv) wmb(); mdss_dp_disable_mainlink_clocks(dp_drv); dp_drv->power_on = false; + dp_drv->sink_info_read = false; mutex_unlock(&dp_drv->train_mutex); complete_all(&dp_drv->irq_comp); @@ -1434,6 +1444,8 @@ static int mdss_dp_off_hpd(struct mdss_dp_drv_pdata *dp_drv) dp_drv->dp_initialized = false; dp_drv->power_on = false; + dp_drv->sink_info_read = false; + mdss_dp_ack_state(dp_drv, false); mutex_unlock(&dp_drv->train_mutex); pr_debug("DP off done\n"); @@ -1506,13 +1518,8 @@ static int mdss_dp_edid_init(struct mdss_panel_data *pdata) dp_drv = container_of(pdata, struct mdss_dp_drv_pdata, panel_data); - dp_drv->ds_data.ds_registered = true; - dp_drv->ds_data.modes_num = ARRAY_SIZE(supported_modes); - dp_drv->ds_data.modes = supported_modes; - dp_drv->max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ; edid_init_data.kobj = dp_drv->kobj; - edid_init_data.ds_data = dp_drv->ds_data; edid_init_data.max_pclk_khz = dp_drv->max_pclk_khz; edid_data = hdmi_edid_init(&edid_init_data); @@ -1545,7 +1552,7 @@ static int mdss_dp_host_init(struct mdss_panel_data *pdata) panel_data); if (dp_drv->dp_initialized) { - pr_err("%s: host init done already\n", __func__); + pr_debug("%s: host init done already\n", __func__); return 0; } @@ -1588,37 +1595,47 @@ static int mdss_dp_host_init(struct mdss_panel_data *pdata) mdss_dp_phy_aux_setup(&dp_drv->phy_io); mdss_dp_irq_enable(dp_drv); - pr_debug("irq enabled\n"); - mdss_dp_dpcd_cap_read(dp_drv); + dp_drv->dp_initialized = true; - ret = mdss_dp_edid_read(dp_drv); + return 0; + +clk_error: + mdss_dp_regulator_ctrl(dp_drv, false); + mdss_dp_config_gpios(dp_drv, false); +vreg_error: + return ret; +} + +static int mdss_dp_process_hpd_high(struct mdss_dp_drv_pdata *dp) +{ + int ret; + + if (dp->sink_info_read) + return 0; + + mdss_dp_dpcd_cap_read(dp); + + ret = mdss_dp_edid_read(dp); if (ret) { - pr_info("edid read error, setting default resolution\n"); - mdss_dp_set_default_resolution(dp_drv); - goto edid_error; - } + pr_debug("edid read error, setting default resolution\n"); - pr_debug("edid_read success. buf_size=%d\n", - dp_drv->edid_buf_size); + mdss_dp_set_default_resolution(dp); + goto end; + } - ret = hdmi_edid_parser(dp_drv->panel_data.panel_info.edid_data); + ret = hdmi_edid_parser(dp->panel_data.panel_info.edid_data); if (ret) { - DEV_ERR("%s: edid parse failed\n", __func__); - goto edid_error; + pr_err("edid parse failed\n"); + goto end; } -edid_error: - mdss_dp_update_cable_status(dp_drv, true); - mdss_dp_notify_clients(dp_drv, true); - dp_drv->dp_initialized = true; + dp->sink_info_read = true; +end: + mdss_dp_update_cable_status(dp, true); + mdss_dp_notify_clients(dp, true); return ret; -clk_error: - mdss_dp_regulator_ctrl(dp_drv, false); - mdss_dp_config_gpios(dp_drv, false); -vreg_error: - return ret; } static int mdss_dp_check_params(struct mdss_dp_drv_pdata *dp, void *arg) @@ -1637,7 +1654,7 @@ static int mdss_dp_check_params(struct mdss_dp_drv_pdata *dp, void *arg) var_pinfo->xres, var_pinfo->yres, pinfo->xres, pinfo->yres); - new_vic = hdmi_panel_get_vic(var_pinfo, &dp->ds_data); + new_vic = hdmi_panel_get_vic(var_pinfo, 0); if ((new_vic < 0) || (new_vic > HDMI_VFRMT_MAX)) { DEV_ERR("%s: invalid or not supported vic\n", __func__); @@ -1855,13 +1872,191 @@ static ssize_t mdss_dp_sysfs_rda_s3d_mode(struct device *dev, return ret; } +static bool mdss_dp_is_test_ongoing(struct mdss_dp_drv_pdata *dp) +{ + return dp->hpd_irq_clients_notified; +} + +/** + * mdss_dp_psm_config() - Downstream device uPacket RX Power Management + * @dp: Display Port Driver data + * + * Perform required steps to configure the uPacket RX of a downstream + * connected device in a power-save mode. + */ +static int mdss_dp_psm_config(struct mdss_dp_drv_pdata *dp, bool enable) +{ + int ret = 0; + + if (!dp) { + pr_err("invalid data\n"); + return -EINVAL; + } + + if (dp->psm_enabled == enable) { + pr_debug("No change in psm requested\n"); + goto end; + } + + pr_debug("Power save mode %s requested\n", enable ? "entry" : "exit"); + + if (enable) { + ret = mdss_dp_aux_send_psm_request(dp, true); + if (ret) + goto end; + + /* + * If this configuration is requested as part of an + * automated test, then HPD notification has already been + * sent out. Just disable the main-link and turn off DP Tx. + * + * Otherwise, trigger a complete shutdown of the pipeline. + */ + if (mdss_dp_is_test_ongoing(dp)) { + mdss_dp_mainlink_push_idle(&dp->panel_data); + mdss_dp_off_irq(dp); + } else { + mdss_dp_notify_clients(dp, false); + } + } else { + /* + * If this configuration is requested as part of an + * automated test, then just perform a link retraining. + * + * Otherwise, re-initialize the host and setup the complete + * pipeline from scratch by sending a connection notification + * to user modules. + */ + if (mdss_dp_is_test_ongoing(dp)) { + mdss_dp_link_retraining(dp); + } else { + mdss_dp_host_init(&dp->panel_data); + mdss_dp_notify_clients(dp, true); + } + } + +end: + pr_debug("Power save mode %s %s\n", + dp->psm_enabled ? "entry" : "exit", + ret ? "failed" : "successful"); + + return ret; +} + +static ssize_t mdss_dp_wta_psm(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int psm; + int rc; + ssize_t ret = strnlen(buf, PAGE_SIZE); + struct mdss_dp_drv_pdata *dp = mdss_dp_get_drvdata(dev); + + if (!dp) { + pr_err("invalid data\n"); + ret = -EINVAL; + goto end; + } + + rc = kstrtoint(buf, 10, &psm); + if (rc) { + pr_err("kstrtoint failed. ret=%d\n", (int)ret); + goto end; + } + + rc = mdss_dp_psm_config(dp, psm ? true : false); + if (rc) { + pr_err("failed to config Power Save Mode\n"); + goto end; + } + +end: + return ret; +} + +static ssize_t mdss_dp_rda_psm(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t ret; + struct mdss_dp_drv_pdata *dp = mdss_dp_get_drvdata(dev); + + if (!dp) { + pr_err("invalid input\n"); + return -EINVAL; + } + + ret = snprintf(buf, PAGE_SIZE, "%d\n", dp->psm_enabled ? 1 : 0); + pr_debug("psm: %s\n", dp->psm_enabled ? "enabled" : "disabled"); + + return ret; +} + +static ssize_t mdss_dp_wta_hpd(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int hpd; + ssize_t ret = strnlen(buf, PAGE_SIZE); + struct mdss_dp_drv_pdata *dp = mdss_dp_get_drvdata(dev); + + if (!dp) { + pr_err("invalid data\n"); + ret = -EINVAL; + goto end; + } + + ret = kstrtoint(buf, 10, &hpd); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", (int)ret); + goto end; + } + + dp->hpd = !!hpd; + pr_debug("hpd=%d\n", dp->hpd); + + if (dp->hpd && dp->cable_connected) { + if (dp->alt_mode.current_state & DP_CONFIGURE_DONE) { + mdss_dp_host_init(&dp->panel_data); + mdss_dp_process_hpd_high(dp); + } else { + dp_send_events(dp, EV_USBPD_DISCOVER_MODES); + } + } else if (!dp->hpd && dp->power_on) { + mdss_dp_notify_clients(dp, false); + } +end: + return ret; +} + +static ssize_t mdss_dp_rda_hpd(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t ret; + struct mdss_dp_drv_pdata *dp = mdss_dp_get_drvdata(dev); + + if (!dp) { + pr_err("invalid input\n"); + return -EINVAL; + } + + ret = snprintf(buf, PAGE_SIZE, "%d\n", dp->hpd); + pr_debug("hpd: %d\n", dp->hpd); + + return ret; +} + static DEVICE_ATTR(connected, S_IRUGO, mdss_dp_rda_connected, NULL); static DEVICE_ATTR(s3d_mode, S_IRUGO | S_IWUSR, mdss_dp_sysfs_rda_s3d_mode, mdss_dp_sysfs_wta_s3d_mode); +static DEVICE_ATTR(hpd, S_IRUGO | S_IWUSR, mdss_dp_rda_hpd, + mdss_dp_wta_hpd); +static DEVICE_ATTR(psm, S_IRUGO | S_IWUSR, mdss_dp_rda_psm, + mdss_dp_wta_psm); + static struct attribute *mdss_dp_fs_attrs[] = { &dev_attr_connected.attr, &dev_attr_s3d_mode.attr, + &dev_attr_hpd.attr, + &dev_attr_psm.attr, NULL, }; @@ -2328,8 +2523,9 @@ static void usbpd_connect_callback(struct usbpd_svid_handler *hdlr) } mdss_dp_update_cable_status(dp_drv, true); - dp_send_events(dp_drv, EV_USBPD_DISCOVER_MODES); - pr_debug("discover_mode event sent\n"); + + if (dp_drv->hpd) + dp_send_events(dp_drv, EV_USBPD_DISCOVER_MODES); } static void usbpd_disconnect_callback(struct usbpd_svid_handler *hdlr) @@ -2681,6 +2877,8 @@ static void usbpd_response_callback(struct usbpd_svid_handler *hdlr, u8 cmd, break; case USBPD_SVDM_ATTENTION: node = kzalloc(sizeof(*node), GFP_KERNEL); + if (!node) + return; node->vdo = *vdos; mutex_lock(&dp_drv->attention_lock); @@ -2703,8 +2901,10 @@ static void usbpd_response_callback(struct usbpd_svid_handler *hdlr, u8 cmd, dp_drv->alt_mode.current_state |= DP_CONFIGURE_DONE; pr_debug("Configure: config USBPD to DP done\n"); + mdss_dp_host_init(&dp_drv->panel_data); + if (dp_drv->alt_mode.dp_status.hpd_high) - mdss_dp_host_init(&dp_drv->panel_data); + mdss_dp_process_hpd_high(dp_drv); break; default: pr_err("unknown cmd: %d\n", cmd); @@ -2752,12 +2952,12 @@ static void mdss_dp_process_attention(struct mdss_dp_drv_pdata *dp_drv) dp_drv->alt_mode.current_state |= DP_STATUS_DONE; - if (dp_drv->alt_mode.current_state & DP_CONFIGURE_DONE) + if (dp_drv->alt_mode.current_state & DP_CONFIGURE_DONE) { mdss_dp_host_init(&dp_drv->panel_data); - else + mdss_dp_process_hpd_high(dp_drv); + } else { dp_send_events(dp_drv, EV_USBPD_DP_CONFIGURE); - - pr_debug("exit\n"); + } } static void mdss_dp_handle_attention(struct mdss_dp_drv_pdata *dp) diff --git a/drivers/video/fbdev/msm/mdss_dp.h b/drivers/video/fbdev/msm/mdss_dp.h index 399ca61e0f46..b7a8583e5864 100644 --- a/drivers/video/fbdev/msm/mdss_dp.h +++ b/drivers/video/fbdev/msm/mdss_dp.h @@ -399,6 +399,9 @@ struct mdss_dp_drv_pdata { bool core_clks_on; bool link_clks_on; bool power_on; + bool sink_info_read; + bool hpd; + bool psm_enabled; /* dp specific */ unsigned char *base; @@ -488,7 +491,6 @@ struct mdss_dp_drv_pdata { u32 current_event; spinlock_t event_lock; spinlock_t lock; - struct hdmi_util_ds_data ds_data; struct switch_dev sdev; struct kobject *kobj; u32 max_pclk_khz; @@ -681,6 +683,7 @@ void mdss_dp_lane_power_ctrl(struct mdss_dp_drv_pdata *ep, int up); void mdss_dp_config_ctrl(struct mdss_dp_drv_pdata *ep); char mdss_dp_gen_link_clk(struct mdss_panel_info *pinfo, char lane_cnt); int mdss_dp_aux_set_sink_power_state(struct mdss_dp_drv_pdata *ep, char state); +int mdss_dp_aux_send_psm_request(struct mdss_dp_drv_pdata *dp, bool enable); void mdss_dp_aux_send_test_response(struct mdss_dp_drv_pdata *ep); void *mdss_dp_get_hdcp_data(struct device *dev); int mdss_dp_hdcp2p2_init(struct mdss_dp_drv_pdata *dp_drv); diff --git a/drivers/video/fbdev/msm/mdss_dp_aux.c b/drivers/video/fbdev/msm/mdss_dp_aux.c index b8be110f04f0..fa1af0d392e7 100644 --- a/drivers/video/fbdev/msm/mdss_dp_aux.c +++ b/drivers/video/fbdev/msm/mdss_dp_aux.c @@ -148,8 +148,11 @@ static int dp_cmd_fifo_tx(struct edp_buf *tp, unsigned char *base) } data = (tp->trans_num - 1); - if (tp->i2c) + if (tp->i2c) { data |= BIT(8); /* I2C */ + data |= BIT(10); /* NO SEND ADDR */ + data |= BIT(11); /* NO SEND STOP */ + } data |= BIT(9); /* GO */ dp_write(base + DP_AUX_TRANS_CTRL, data); @@ -213,7 +216,7 @@ static int dp_aux_write_cmds(struct mdss_dp_drv_pdata *ep, len = dp_cmd_fifo_tx(&ep->txp, ep->base); - wait_for_completion(&ep->aux_comp); + wait_for_completion_timeout(&ep->aux_comp, HZ/4); if (ep->aux_error_num == EDP_AUX_ERR_NONE) ret = len; @@ -269,7 +272,7 @@ static int dp_aux_read_cmds(struct mdss_dp_drv_pdata *ep, dp_cmd_fifo_tx(tp, ep->base); - wait_for_completion(&ep->aux_comp); + wait_for_completion_timeout(&ep->aux_comp, HZ/4); if (ep->aux_error_num == EDP_AUX_ERR_NONE) { ret = dp_cmd_fifo_rx(rp, len, ep->base); @@ -731,8 +734,10 @@ int mdss_dp_edid_read(struct mdss_dp_drv_pdata *dp) int rlen, ret = 0; int edid_blk = 0, blk_num = 0, retries = 10; bool edid_parsing_done = false; - const u8 cea_tag = 0x02; + const u8 cea_tag = 0x02, start_ext_blk = 0x1; + u32 const segment_addr = 0x30; u32 checksum = 0; + char segment = 0x1; ret = dp_aux_chan_ready(dp); if (ret) { @@ -761,7 +766,7 @@ int mdss_dp_edid_read(struct mdss_dp_drv_pdata *dp) ret = dp_edid_buf_error(rp->data, rp->len); if (ret) { pr_err("corrupt edid block detected\n"); - goto end; + continue; } if (edid_parsing_done) { @@ -779,7 +784,6 @@ int mdss_dp_edid_read(struct mdss_dp_drv_pdata *dp) rp->data); edid_parsing_done = true; - checksum = rp->data[rp->len - 1]; } else { edid_blk++; blk_num++; @@ -797,11 +801,17 @@ int mdss_dp_edid_read(struct mdss_dp_drv_pdata *dp) memcpy(dp->edid_buf + (edid_blk * EDID_BLOCK_SIZE), rp->data, EDID_BLOCK_SIZE); + checksum = rp->data[rp->len - 1]; + + /* break if no more extension blocks present */ if (edid_blk == dp->edid.ext_block_cnt) - goto end; + break; + + /* write segment number to read block 3 onwards */ + if (edid_blk == start_ext_blk) + dp_aux_write_buf(dp, segment_addr, &segment, 1, 1); } while (retries--); -end: if (dp->test_data.test_requested == TEST_EDID_READ) { pr_debug("sending checksum %d\n", checksum); dp_aux_send_checksum(dp, checksum); @@ -1016,6 +1026,51 @@ int mdss_dp_aux_link_status_read(struct mdss_dp_drv_pdata *ep, int len) return len; } +/* + * mdss_dp_aux_send_psm_request() - sends a power save mode messge to sink + * @dp: Display Port Driver data + */ +int mdss_dp_aux_send_psm_request(struct mdss_dp_drv_pdata *dp, bool enable) +{ + u8 psm_request[4]; + int rc = 0; + + psm_request[0] = enable ? 2 : 1; + + pr_debug("sending psm %s request\n", enable ? "entry" : "exit"); + if (enable) { + dp_aux_write_buf(dp, 0x600, psm_request, 1, 0); + } else { + ktime_t timeout = ktime_add_ms(ktime_get(), 20); + + /* + * It could take up to 1ms (20 ms of embedded sinks) till + * the sink is ready to reply to this AUX transaction. It is + * expected that the source keep retrying periodically during + * this time. + */ + for (;;) { + rc = dp_aux_write_buf(dp, 0x600, psm_request, 1, 0); + if ((rc >= 0) || + (ktime_compare(ktime_get(), timeout) > 0)) + break; + usleep_range(100, 120); + } + + /* + * if the aux transmission succeeded, then the function would + * return the number of bytes transmitted. + */ + if (rc > 0) + rc = 0; + } + + if (!rc) + dp->psm_enabled = enable; + + return rc; +} + /** * mdss_dp_aux_send_test_response() - sends a test response to the sink * @dp: Display Port Driver data @@ -1499,18 +1554,18 @@ static void dp_host_train_set(struct mdss_dp_drv_pdata *ep, int train) } char vm_pre_emphasis[4][4] = { - {0x00, 0x09, 0x11, 0x0C}, /* pe0, 0 db */ - {0x00, 0x0A, 0x10, 0xFF}, /* pe1, 3.5 db */ - {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */ - {0x00, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */ + {0x00, 0x0B, 0x12, 0xFF}, /* pe0, 0 db */ + {0x00, 0x0A, 0x12, 0xFF}, /* pe1, 3.5 db */ + {0x00, 0x0C, 0xFF, 0xFF}, /* pe2, 6.0 db */ + {0xFF, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */ }; /* voltage swing, 0.2v and 1.0v are not support */ char vm_voltage_swing[4][4] = { - {0x07, 0x0f, 0x12, 0x1E}, /* sw0, 0.4v */ + {0x07, 0x0F, 0x14, 0xFF}, /* sw0, 0.4v */ {0x11, 0x1D, 0x1F, 0xFF}, /* sw1, 0.6 v */ {0x18, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */ - {0x1E, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */ + {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */ }; static void dp_aux_set_voltage_and_pre_emphasis_lvl( @@ -1524,6 +1579,14 @@ static void dp_aux_set_voltage_and_pre_emphasis_lvl( value0 = vm_voltage_swing[(int)(dp->v_level)][(int)(dp->p_level)]; value1 = vm_pre_emphasis[(int)(dp->v_level)][(int)(dp->p_level)]; + /* program default setting first */ + dp_write(dp->phy_io.base + QSERDES_TX0_OFFSET + TXn_TX_DRV_LVL, 0x2A); + dp_write(dp->phy_io.base + QSERDES_TX1_OFFSET + TXn_TX_DRV_LVL, 0x2A); + dp_write(dp->phy_io.base + QSERDES_TX0_OFFSET + TXn_TX_EMP_POST1_LVL, + 0x20); + dp_write(dp->phy_io.base + QSERDES_TX1_OFFSET + TXn_TX_EMP_POST1_LVL, + 0x20); + /* Enable MUX to use Cursor values from these registers */ value0 |= BIT(5); value1 |= BIT(5); @@ -1590,10 +1653,10 @@ static int dp_start_link_train_1(struct mdss_dp_drv_pdata *ep) pr_debug("Entered++"); - dp_host_train_set(ep, 0x01); /* train_1 */ dp_cap_lane_rate_set(ep); dp_train_pattern_set_write(ep, 0x21); /* train_1 */ dp_aux_set_voltage_and_pre_emphasis_lvl(ep); + dp_host_train_set(ep, 0x01); /* train_1 */ tries = 0; old_v_level = ep->v_level; @@ -1648,7 +1711,6 @@ static int dp_start_link_train_2(struct mdss_dp_drv_pdata *ep) dp_train_pattern_set_write(ep, pattern | 0x20);/* train_2 */ do { - dp_aux_set_voltage_and_pre_emphasis_lvl(ep); dp_host_train_set(ep, pattern); usleep_time = ep->dpcd.training_read_interval; @@ -1668,6 +1730,7 @@ static int dp_start_link_train_2(struct mdss_dp_drv_pdata *ep) } dp_sink_train_set_adjust(ep); + dp_aux_set_voltage_and_pre_emphasis_lvl(ep); } while (1); return ret; @@ -1773,7 +1836,8 @@ clear: mdss_dp_config_misc_settings(&dp->ctrl_io, &dp->panel_data.panel_info); mdss_dp_setup_tr_unit(&dp->ctrl_io, dp->link_rate, - dp->lane_cnt, dp->vic); + dp->lane_cnt, dp->vic, + &dp->panel_data.panel_info); mdss_dp_state_ctrl(&dp->ctrl_io, ST_SEND_VIDEO); pr_debug("State_ctrl set to SEND_VIDEO\n"); } diff --git a/drivers/video/fbdev/msm/mdss_dp_util.c b/drivers/video/fbdev/msm/mdss_dp_util.c index 3b294a11f555..a7f42ba8c261 100644 --- a/drivers/video/fbdev/msm/mdss_dp_util.c +++ b/drivers/video/fbdev/msm/mdss_dp_util.c @@ -208,6 +208,499 @@ void mdss_dp_state_ctrl(struct dss_io_data *ctrl_io, u32 data) writel_relaxed(data, ctrl_io->base + DP_STATE_CTRL); } +static void mdss_dp_get_extra_req_bytes(u64 result_valid, + int valid_bdary_link, + u64 value1, u64 value2, + bool *negative, u64 *result, + u64 compare) +{ + *negative = false; + if (result_valid >= compare) { + if (valid_bdary_link + >= compare) + *result = value1 + value2; + else { + if (value1 < value2) + *negative = true; + *result = (value1 >= value2) ? + (value1 - value2) : (value2 - value1); + } + } else { + if (valid_bdary_link + >= compare) { + if (value1 >= value2) + *negative = true; + *result = (value1 >= value2) ? + (value1 - value2) : (value2 - value1); + } else { + *result = value1 + value2; + *negative = true; + } + } +} + +static u64 roundup_u64(u64 x, u64 y) +{ + x += (y - 1); + return (div64_ul(x, y) * y); +} + +static u64 rounddown_u64(u64 x, u64 y) +{ + u64 rem; + + div64_u64_rem(x, y, &rem); + return (x - rem); +} + +static void mdss_dp_calc_tu_parameters(u8 link_rate, u8 ln_cnt, + struct dp_vc_tu_mapping_table *tu_table, + struct mdss_panel_info *pinfo) +{ + u32 const multiplier = 1000000; + u64 pclk, lclk; + u8 bpp; + int run_idx = 0; + u32 lwidth, h_blank; + u32 fifo_empty = 0; + u32 ratio_scale = 1001; + u64 temp, ratio, original_ratio; + u64 temp2, reminder; + u64 temp3, temp4, result = 0; + + u64 err = multiplier; + u64 n_err = 0, n_n_err = 0; + bool n_err_neg, nn_err_neg; + u8 hblank_margin = 16; + + u8 tu_size, tu_size_desired, tu_size_minus1; + int valid_boundary_link; + u64 resulting_valid; + u64 total_valid; + u64 effective_valid; + u64 effective_valid_recorded; + int n_tus; + int n_tus_per_lane; + int paired_tus; + int remainder_tus; + int remainder_tus_upper, remainder_tus_lower; + int extra_bytes; + int filler_size; + int delay_start_link; + int boundary_moderation_en = 0; + int upper_bdry_cnt = 0; + int lower_bdry_cnt = 0; + int i_upper_bdry_cnt = 0; + int i_lower_bdry_cnt = 0; + int valid_lower_boundary_link = 0; + int even_distribution_bf = 0; + int even_distribution_legacy = 0; + int even_distribution = 0; + int min_hblank = 0; + int extra_pclk_cycles; + u8 extra_pclk_cycle_delay = 4; + int extra_pclk_cycles_in_link_clk; + u64 ratio_by_tu; + u64 average_valid2; + u64 extra_buffer_margin; + int new_valid_boundary_link; + + u64 resulting_valid_tmp; + u64 ratio_by_tu_tmp; + int n_tus_tmp; + int extra_pclk_cycles_tmp; + int extra_pclk_cycles_in_lclk_tmp; + int extra_req_bytes_new_tmp; + int filler_size_tmp; + int lower_filler_size_tmp; + int delay_start_link_tmp; + int min_hblank_tmp = 0; + bool extra_req_bytes_is_neg = false; + + u8 dp_brute_force = 1; + u64 brute_force_threshold = 10; + u64 diff_abs; + + bpp = pinfo->bpp; + lwidth = pinfo->xres; /* active width */ + h_blank = pinfo->lcdc.h_back_porch + pinfo->lcdc.h_front_porch + + pinfo->lcdc.h_pulse_width; + pclk = pinfo->clk_rate; + + boundary_moderation_en = 0; + upper_bdry_cnt = 0; + lower_bdry_cnt = 0; + i_upper_bdry_cnt = 0; + i_lower_bdry_cnt = 0; + valid_lower_boundary_link = 0; + even_distribution_bf = 0; + even_distribution_legacy = 0; + even_distribution = 0; + min_hblank = 0; + + lclk = link_rate * DP_LINK_RATE_MULTIPLIER; + + pr_debug("pclk=%lld, active_width=%d, h_blank=%d\n", + pclk, lwidth, h_blank); + pr_debug("lclk = %lld, ln_cnt = %d\n", lclk, ln_cnt); + ratio = div64_u64_rem(pclk * bpp * multiplier, + 8 * ln_cnt * lclk, &reminder); + ratio = div64_u64((pclk * bpp * multiplier), (8 * ln_cnt * lclk)); + original_ratio = ratio; + + extra_buffer_margin = roundup_u64(div64_u64(extra_pclk_cycle_delay + * lclk * multiplier, pclk), multiplier); + extra_buffer_margin = div64_u64(extra_buffer_margin, multiplier); + + /* To deal with cases where lines are not distributable */ + if (((lwidth % ln_cnt) != 0) && ratio < multiplier) { + ratio = ratio * ratio_scale; + ratio = ratio < (1000 * multiplier) + ? ratio : (1000 * multiplier); + } + pr_debug("ratio = %lld\n", ratio); + + for (tu_size = 32; tu_size <= 64; tu_size++) { + temp = ratio * tu_size; + temp2 = ((temp / multiplier) + 1) * multiplier; + n_err = roundup_u64(temp, multiplier) - temp; + + if (n_err < err) { + err = n_err; + tu_size_desired = tu_size; + } + } + pr_debug("Info: tu_size_desired = %d\n", tu_size_desired); + + tu_size_minus1 = tu_size_desired - 1; + + valid_boundary_link = roundup_u64(ratio * tu_size_desired, multiplier); + valid_boundary_link /= multiplier; + n_tus = rounddown((lwidth * bpp * multiplier) + / (8 * valid_boundary_link), multiplier) / multiplier; + even_distribution_legacy = n_tus % ln_cnt == 0 ? 1 : 0; + pr_debug("Info: n_symbol_per_tu=%d, number_of_tus=%d\n", + valid_boundary_link, n_tus); + + extra_bytes = roundup_u64((n_tus + 1) + * ((valid_boundary_link * multiplier) + - (original_ratio * tu_size_desired)), multiplier); + extra_bytes /= multiplier; + extra_pclk_cycles = roundup(extra_bytes * 8 * multiplier / bpp, + multiplier); + extra_pclk_cycles /= multiplier; + extra_pclk_cycles_in_link_clk = roundup_u64(div64_u64(extra_pclk_cycles + * lclk * multiplier, pclk), multiplier); + extra_pclk_cycles_in_link_clk /= multiplier; + filler_size = roundup_u64((tu_size_desired - valid_boundary_link) + * multiplier, multiplier); + filler_size /= multiplier; + ratio_by_tu = div64_u64(ratio * tu_size_desired, multiplier); + + pr_debug("extra_pclk_cycles_in_link_clk=%d, extra_bytes=%d\n", + extra_pclk_cycles_in_link_clk, extra_bytes); + pr_debug("extra_pclk_cycles_in_link_clk=%d\n", + extra_pclk_cycles_in_link_clk); + pr_debug("filler_size=%d, extra_buffer_margin=%lld\n", + filler_size, extra_buffer_margin); + + delay_start_link = ((extra_bytes > extra_pclk_cycles_in_link_clk) + ? extra_bytes + : extra_pclk_cycles_in_link_clk) + + filler_size + extra_buffer_margin; + resulting_valid = valid_boundary_link; + pr_debug("Info: delay_start_link=%d, filler_size=%d\n", + delay_start_link, filler_size); + pr_debug("valid_boundary_link=%d ratio_by_tu=%lld\n", + valid_boundary_link, ratio_by_tu); + + diff_abs = (resulting_valid >= ratio_by_tu) + ? (resulting_valid - ratio_by_tu) + : (ratio_by_tu - resulting_valid); + + if (err != 0 && ((diff_abs > brute_force_threshold) + || (even_distribution_legacy == 0) + || (dp_brute_force == 1))) { + err = multiplier; + for (tu_size = 32; tu_size <= 64; tu_size++) { + for (i_upper_bdry_cnt = 1; i_upper_bdry_cnt <= 15; + i_upper_bdry_cnt++) { + for (i_lower_bdry_cnt = 1; + i_lower_bdry_cnt <= 15; + i_lower_bdry_cnt++) { + new_valid_boundary_link = + roundup_u64(ratio + * tu_size, multiplier); + average_valid2 = (i_upper_bdry_cnt + * new_valid_boundary_link + + i_lower_bdry_cnt + * (new_valid_boundary_link + - multiplier)) + / (i_upper_bdry_cnt + + i_lower_bdry_cnt); + n_tus = rounddown_u64(div64_u64(lwidth + * multiplier * multiplier + * (bpp / 8), average_valid2), + multiplier); + n_tus /= multiplier; + n_tus_per_lane + = rounddown(n_tus + * multiplier + / ln_cnt, multiplier); + n_tus_per_lane /= multiplier; + paired_tus = + rounddown((n_tus_per_lane) + * multiplier + / (i_upper_bdry_cnt + + i_lower_bdry_cnt), + multiplier); + paired_tus /= multiplier; + remainder_tus = n_tus_per_lane + - paired_tus + * (i_upper_bdry_cnt + + i_lower_bdry_cnt); + if ((remainder_tus + - i_upper_bdry_cnt) > 0) { + remainder_tus_upper + = i_upper_bdry_cnt; + remainder_tus_lower = + remainder_tus + - i_upper_bdry_cnt; + } else { + remainder_tus_upper + = remainder_tus; + remainder_tus_lower = 0; + } + total_valid = paired_tus + * (i_upper_bdry_cnt + * new_valid_boundary_link + + i_lower_bdry_cnt + * (new_valid_boundary_link + - multiplier)) + + (remainder_tus_upper + * new_valid_boundary_link) + + (remainder_tus_lower + * (new_valid_boundary_link + - multiplier)); + n_err_neg = nn_err_neg = false; + effective_valid + = div_u64(total_valid, + n_tus_per_lane); + n_n_err = (effective_valid + >= (ratio * tu_size)) + ? (effective_valid + - (ratio * tu_size)) + : ((ratio * tu_size) + - effective_valid); + if (effective_valid < (ratio * tu_size)) + nn_err_neg = true; + n_err = (average_valid2 + >= (ratio * tu_size)) + ? (average_valid2 + - (ratio * tu_size)) + : ((ratio * tu_size) + - average_valid2); + if (average_valid2 < (ratio * tu_size)) + n_err_neg = true; + even_distribution = + n_tus % ln_cnt == 0 ? 1 : 0; + diff_abs = + resulting_valid >= ratio_by_tu + ? (resulting_valid + - ratio_by_tu) + : (ratio_by_tu + - resulting_valid); + + resulting_valid_tmp = div64_u64( + (i_upper_bdry_cnt + * new_valid_boundary_link + + i_lower_bdry_cnt + * (new_valid_boundary_link + - multiplier)), + (i_upper_bdry_cnt + + i_lower_bdry_cnt)); + ratio_by_tu_tmp = + original_ratio * tu_size; + ratio_by_tu_tmp /= multiplier; + n_tus_tmp = rounddown_u64( + div64_u64(lwidth + * multiplier * multiplier + * bpp / 8, + resulting_valid_tmp), + multiplier); + n_tus_tmp /= multiplier; + + temp3 = (resulting_valid_tmp + >= (original_ratio * tu_size)) + ? (resulting_valid_tmp + - original_ratio * tu_size) + : (original_ratio * tu_size) + - resulting_valid_tmp; + temp3 = (n_tus_tmp + 1) * temp3; + temp4 = (new_valid_boundary_link + >= (original_ratio * tu_size)) + ? (new_valid_boundary_link + - original_ratio + * tu_size) + : (original_ratio * tu_size) + - new_valid_boundary_link; + temp4 = (i_upper_bdry_cnt + * ln_cnt * temp4); + + temp3 = roundup_u64(temp3, multiplier); + temp4 = roundup_u64(temp4, multiplier); + mdss_dp_get_extra_req_bytes + (resulting_valid_tmp, + new_valid_boundary_link, + temp3, temp4, + &extra_req_bytes_is_neg, + &result, + (original_ratio * tu_size)); + extra_req_bytes_new_tmp + = div64_ul(result, multiplier); + if ((extra_req_bytes_is_neg) + && (extra_req_bytes_new_tmp + > 1)) + extra_req_bytes_new_tmp + = extra_req_bytes_new_tmp - 1; + if (extra_req_bytes_new_tmp == 0) + extra_req_bytes_new_tmp = 1; + extra_pclk_cycles_tmp = + (u64)(extra_req_bytes_new_tmp + * 8 * multiplier) / bpp; + extra_pclk_cycles_tmp /= multiplier; + + if (extra_pclk_cycles_tmp <= 0) + extra_pclk_cycles_tmp = 1; + extra_pclk_cycles_in_lclk_tmp = + roundup_u64(div64_u64( + extra_pclk_cycles_tmp + * lclk * multiplier, + pclk), multiplier); + extra_pclk_cycles_in_lclk_tmp + /= multiplier; + filler_size_tmp = roundup_u64( + (tu_size * multiplier * + new_valid_boundary_link), + multiplier); + filler_size_tmp /= multiplier; + lower_filler_size_tmp = + filler_size_tmp + 1; + if (extra_req_bytes_is_neg) + temp3 = (extra_req_bytes_new_tmp + > extra_pclk_cycles_in_lclk_tmp + ? extra_pclk_cycles_in_lclk_tmp + : extra_req_bytes_new_tmp); + else + temp3 = (extra_req_bytes_new_tmp + > extra_pclk_cycles_in_lclk_tmp + ? extra_req_bytes_new_tmp : + extra_pclk_cycles_in_lclk_tmp); + + temp4 = lower_filler_size_tmp + + extra_buffer_margin; + if (extra_req_bytes_is_neg) + delay_start_link_tmp + = (temp3 >= temp4) + ? (temp3 - temp4) + : (temp4 - temp3); + else + delay_start_link_tmp + = temp3 + temp4; + + min_hblank_tmp = (int)div64_u64( + roundup_u64( + div64_u64(delay_start_link_tmp + * pclk * multiplier, lclk), + multiplier), multiplier) + + hblank_margin; + + if (((even_distribution == 1) + || ((even_distribution_bf == 0) + && (even_distribution_legacy + == 0))) + && !n_err_neg && !nn_err_neg + && n_n_err < err + && (n_n_err < diff_abs + || (dp_brute_force == 1)) + && (new_valid_boundary_link + - 1) > 0 + && (h_blank >= + (u32)min_hblank_tmp)) { + upper_bdry_cnt = + i_upper_bdry_cnt; + lower_bdry_cnt = + i_lower_bdry_cnt; + err = n_n_err; + boundary_moderation_en = 1; + tu_size_desired = tu_size; + valid_boundary_link = + new_valid_boundary_link; + effective_valid_recorded + = effective_valid; + delay_start_link + = delay_start_link_tmp; + filler_size = filler_size_tmp; + min_hblank = min_hblank_tmp; + n_tus = n_tus_tmp; + even_distribution_bf = 1; + + pr_debug("upper_bdry_cnt=%d, lower_boundary_cnt=%d, err=%lld, tu_size_desired=%d, valid_boundary_link=%d, effective_valid=%lld\n", + upper_bdry_cnt, + lower_bdry_cnt, err, + tu_size_desired, + valid_boundary_link, + effective_valid); + } + } + } + } + + if (boundary_moderation_en == 1) { + resulting_valid = (u64)(upper_bdry_cnt + *valid_boundary_link + lower_bdry_cnt + * (valid_boundary_link - 1)) + / (upper_bdry_cnt + lower_bdry_cnt); + ratio_by_tu = original_ratio * tu_size_desired; + valid_lower_boundary_link = + (valid_boundary_link / multiplier) - 1; + + tu_size_minus1 = tu_size_desired - 1; + even_distribution_bf = 1; + valid_boundary_link /= multiplier; + pr_debug("Info: Boundary_moderation enabled\n"); + } + } + + min_hblank = ((int) roundup_u64(div64_u64(delay_start_link * pclk + * multiplier, lclk), multiplier)) + / multiplier + hblank_margin; + if (h_blank < (u32)min_hblank) { + pr_err(" WARNING: run_idx=%d Programmed h_blank %d is smaller than the min_hblank %d supported.\n", + run_idx, h_blank, min_hblank); + } + + if (fifo_empty) { + tu_size_minus1 = 31; + valid_boundary_link = 32; + delay_start_link = 0; + boundary_moderation_en = 0; + } + + pr_debug("tu_size_minus1=%d valid_boundary_link=%d delay_start_link=%d boundary_moderation_en=%d\n upper_boundary_cnt=%d lower_boundary_cnt=%d valid_lower_boundary_link=%d min_hblank=%d\n", + tu_size_minus1, valid_boundary_link, delay_start_link, + boundary_moderation_en, upper_bdry_cnt, lower_bdry_cnt, + valid_lower_boundary_link, min_hblank); + + tu_table->valid_boundary_link = valid_boundary_link; + tu_table->delay_start_link = delay_start_link; + tu_table->boundary_moderation_en = boundary_moderation_en; + tu_table->valid_lower_boundary_link = valid_lower_boundary_link; + tu_table->upper_boundary_count = upper_bdry_cnt; + tu_table->lower_boundary_count = lower_bdry_cnt; + tu_table->tu_size_minus1 = tu_size_minus1; +} + void mdss_dp_timing_cfg(struct dss_io_data *ctrl_io, struct mdss_panel_info *pinfo) { @@ -297,12 +790,13 @@ void mdss_dp_config_misc_settings(struct dss_io_data *ctrl_io, } void mdss_dp_setup_tr_unit(struct dss_io_data *ctrl_io, u8 link_rate, - u8 ln_cnt, u32 res) + u8 ln_cnt, u32 res, struct mdss_panel_info *pinfo) { u32 dp_tu = 0x0; u32 valid_boundary = 0x0; u32 valid_boundary2 = 0x0; struct dp_vc_tu_mapping_table const *tu_entry = tu_table; + struct dp_vc_tu_mapping_table tu_calc_table; for (; tu_entry != tu_table + ARRAY_SIZE(tu_table); ++tu_entry) { if ((tu_entry->vic == res) && @@ -314,18 +808,18 @@ void mdss_dp_setup_tr_unit(struct dss_io_data *ctrl_io, u8 link_rate, if (tu_entry == tu_table + ARRAY_SIZE(tu_table)) { pr_err("requested res=%d, ln_cnt=%d, lrate=0x%x not supported\n", res, ln_cnt, link_rate); - return; } - dp_tu |= tu_entry->tu_size_minus1; - valid_boundary |= tu_entry->valid_boundary_link; - valid_boundary |= (tu_entry->delay_start_link << 16); + mdss_dp_calc_tu_parameters(link_rate, ln_cnt, &tu_calc_table, pinfo); + dp_tu |= tu_calc_table.tu_size_minus1; + valid_boundary |= tu_calc_table.valid_boundary_link; + valid_boundary |= (tu_calc_table.delay_start_link << 16); - valid_boundary2 |= (tu_entry->valid_lower_boundary_link << 1); - valid_boundary2 |= (tu_entry->upper_boundary_count << 16); - valid_boundary2 |= (tu_entry->lower_boundary_count << 20); + valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1); + valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16); + valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20); - if (tu_entry->boundary_moderation_en) + if (tu_calc_table.boundary_moderation_en) valid_boundary2 |= BIT(0); writel_relaxed(valid_boundary, ctrl_io->base + DP_VALID_BOUNDARY); diff --git a/drivers/video/fbdev/msm/mdss_dp_util.h b/drivers/video/fbdev/msm/mdss_dp_util.h index c046deef48a3..fcb9a77db67c 100644 --- a/drivers/video/fbdev/msm/mdss_dp_util.h +++ b/drivers/video/fbdev/msm/mdss_dp_util.h @@ -284,7 +284,7 @@ void mdss_dp_phy_reset(struct dss_io_data *ctrl_io); void mdss_dp_switch_usb3_phy_to_dp_mode(struct dss_io_data *tcsr_reg_io); void mdss_dp_assert_phy_reset(struct dss_io_data *ctrl_io, bool assert); void mdss_dp_setup_tr_unit(struct dss_io_data *ctrl_io, u8 link_rate, - u8 ln_cnt, u32 res); + u8 ln_cnt, u32 res, struct mdss_panel_info *pinfo); void mdss_dp_config_misc_settings(struct dss_io_data *ctrl_io, struct mdss_panel_info *pinfo); void mdss_dp_phy_aux_setup(struct dss_io_data *phy_io); diff --git a/drivers/video/fbdev/msm/mdss_dsi_host.c b/drivers/video/fbdev/msm/mdss_dsi_host.c index 635ef68b4e94..22a424cc15b8 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_host.c +++ b/drivers/video/fbdev/msm/mdss_dsi_host.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1216,6 +1216,15 @@ void mdss_dsi_dsc_config(struct mdss_dsi_ctrl_pdata *ctrl, struct dsc_desc *dsc) { u32 data, offset; + if (!dsc) { + if (ctrl->panel_mode == DSI_VIDEO_MODE) + offset = MDSS_DSI_VIDEO_COMPRESSION_MODE_CTRL; + else + offset = MDSS_DSI_COMMAND_COMPRESSION_MODE_CTRL; + MIPI_OUTP((ctrl->ctrl_base) + offset, 0); + return; + } + if (dsc->pkt_per_line <= 0) { pr_err("%s: Error: pkt_per_line cannot be negative or 0\n", __func__); @@ -1404,8 +1413,7 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata) MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x5C, stream_total); } - if (dsc) /* compressed */ - mdss_dsi_dsc_config(ctrl_pdata, dsc); + mdss_dsi_dsc_config(ctrl_pdata, dsc); } void mdss_dsi_ctrl_setup(struct mdss_dsi_ctrl_pdata *ctrl) diff --git a/drivers/video/fbdev/msm/mdss_dsi_panel.c b/drivers/video/fbdev/msm/mdss_dsi_panel.c index 79e74df12988..c3ae4c1f8c17 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_panel.c +++ b/drivers/video/fbdev/msm/mdss_dsi_panel.c @@ -1494,8 +1494,9 @@ static int mdss_dsi_parse_topology_config(struct device_node *np, goto end; } } - rc = of_property_read_string(cfg_np, "qcom,split-mode", &data); - if (!rc && !strcmp(data, "pingpong-split")) + + if (!of_property_read_string(cfg_np, "qcom,split-mode", + &data) && !strcmp(data, "pingpong-split")) pinfo->use_pingpong_split = true; if (((timing->lm_widths[0]) || (timing->lm_widths[1])) && @@ -2366,9 +2367,9 @@ static int mdss_dsi_panel_timing_from_dt(struct device_node *np, phy_timings_present = true; } - data = of_get_property(np, "qcom,mdss-dsi-panel-timings-8996", &len); + data = of_get_property(np, "qcom,mdss-dsi-panel-timings-phy-v2", &len); if ((!data) || (len != 40)) { - pr_debug("%s:%d, Unable to read 8996 Phy lane timing settings", + pr_debug("%s:%d, Unable to read phy-v2 lane timing settings", __func__, __LINE__); } else { for (i = 0; i < len; i++) diff --git a/drivers/video/fbdev/msm/mdss_fb.c b/drivers/video/fbdev/msm/mdss_fb.c index 35913a26317d..082986b0ade7 100644 --- a/drivers/video/fbdev/msm/mdss_fb.c +++ b/drivers/video/fbdev/msm/mdss_fb.c @@ -76,6 +76,12 @@ #define BLANK_FLAG_ULP FB_BLANK_NORMAL #endif +/* + * Time period for fps calulation in micro seconds. + * Default value is set to 1 sec. + */ +#define MDP_TIME_PERIOD_CALC_FPS_US 1000000 + static struct fb_info *fbi_list[MAX_FBI_LIST]; static int fbi_list_index; @@ -502,6 +508,22 @@ static void __mdss_fb_idle_notify_work(struct work_struct *work) mfd->idle_state = MDSS_FB_IDLE; } + +static ssize_t mdss_fb_get_fps_info(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fb_info *fbi = dev_get_drvdata(dev); + struct msm_fb_data_type *mfd = fbi->par; + unsigned int fps_int, fps_float; + + if (mfd->panel_power_state != MDSS_PANEL_POWER_ON) + mfd->fps_info.measured_fps = 0; + fps_int = (unsigned int) mfd->fps_info.measured_fps; + fps_float = do_div(fps_int, 10); + return scnprintf(buf, PAGE_SIZE, "%d.%d\n", fps_int, fps_float); + +} + static ssize_t mdss_fb_get_idle_time(struct device *dev, struct device_attribute *attr, char *buf) { @@ -815,6 +837,8 @@ static DEVICE_ATTR(msm_fb_panel_status, S_IRUGO | S_IWUSR, mdss_fb_get_panel_status, mdss_fb_force_panel_dead); static DEVICE_ATTR(msm_fb_dfps_mode, S_IRUGO | S_IWUSR, mdss_fb_get_dfps_mode, mdss_fb_change_dfps_mode); +static DEVICE_ATTR(measured_fps, S_IRUGO | S_IWUSR | S_IWGRP, + mdss_fb_get_fps_info, NULL); static struct attribute *mdss_fb_attrs[] = { &dev_attr_msm_fb_type.attr, &dev_attr_msm_fb_split.attr, @@ -826,6 +850,7 @@ static struct attribute *mdss_fb_attrs[] = { &dev_attr_msm_fb_thermal_level.attr, &dev_attr_msm_fb_panel_status.attr, &dev_attr_msm_fb_dfps_mode.attr, + &dev_attr_measured_fps.attr, NULL, }; @@ -1196,6 +1221,7 @@ static int mdss_fb_probe(struct platform_device *pdev) return rc; } } + mdss_fb_init_fps_info(mfd); rc = pm_runtime_set_active(mfd->fbi->dev); if (rc < 0) @@ -2098,6 +2124,10 @@ err_put: dma_buf_put(mfd->fbmem_buf); fb_mmap_failed: ion_free(mfd->fb_ion_client, mfd->fb_ion_handle); + mfd->fb_attachment = NULL; + mfd->fb_table = NULL; + mfd->fb_ion_handle = NULL; + mfd->fbmem_buf = NULL; return rc; } @@ -2825,7 +2855,7 @@ static int __mdss_fb_wait_for_fence_sub(struct msm_sync_pt_data *sync_pt_data, wait_ms); pr_warn("%s: sync_fence_wait timed out! ", - sync_pt_data->fence_name); + fences[i]->name); pr_cont("Waiting %ld.%ld more seconds\n", (wait_ms/MSEC_PER_SEC), (wait_ms%MSEC_PER_SEC)); @@ -2977,6 +3007,7 @@ static int __mdss_fb_sync_buf_done_callback(struct notifier_block *p, case MDP_NOTIFY_FRAME_DONE: pr_debug("%s: frame done\n", sync_pt_data->fence_name); mdss_fb_signal_timeline(sync_pt_data); + mdss_fb_calc_fps(mfd); break; case MDP_NOTIFY_FRAME_CFG_DONE: if (sync_pt_data->async_wait_fences) @@ -3076,7 +3107,7 @@ static int mdss_fb_pan_display_ex(struct fb_info *info, if (var->yoffset > (info->var.yres_virtual - info->var.yres)) return -EINVAL; - ret = mdss_fb_wait_for_kickoff(mfd); + ret = mdss_fb_pan_idle(mfd); if (ret) { pr_err("wait_for_kick failed. rc=%d\n", ret); return ret; @@ -5031,3 +5062,34 @@ void mdss_fb_report_panel_dead(struct msm_fb_data_type *mfd) KOBJ_CHANGE, envp); pr_err("Panel has gone bad, sending uevent - %s\n", envp[0]); } + + +/* + * mdss_fb_calc_fps() - Calculates fps value. + * @mfd : frame buffer structure associated with fb device. + * + * This function is called at frame done. It counts the number + * of frames done for every 1 sec. Stores the value in measured_fps. + * measured_fps value is 10 times the calculated fps value. + * For example, measured_fps= 594 for calculated fps of 59.4 + */ +void mdss_fb_calc_fps(struct msm_fb_data_type *mfd) +{ + ktime_t current_time_us; + u64 fps, diff_us; + + current_time_us = ktime_get(); + diff_us = (u64)ktime_us_delta(current_time_us, + mfd->fps_info.last_sampled_time_us); + mfd->fps_info.frame_count++; + + if (diff_us >= MDP_TIME_PERIOD_CALC_FPS_US) { + fps = ((u64)mfd->fps_info.frame_count) * 10000000; + do_div(fps, diff_us); + mfd->fps_info.measured_fps = (unsigned int)fps; + pr_debug(" MDP_FPS for fb%d is %d.%d\n", + mfd->index, (unsigned int)fps/10, (unsigned int)fps%10); + mfd->fps_info.last_sampled_time_us = current_time_us; + mfd->fps_info.frame_count = 0; + } +} diff --git a/drivers/video/fbdev/msm/mdss_fb.h b/drivers/video/fbdev/msm/mdss_fb.h index 2eb6c6456f29..1487c4e7f6e2 100644 --- a/drivers/video/fbdev/msm/mdss_fb.h +++ b/drivers/video/fbdev/msm/mdss_fb.h @@ -253,6 +253,12 @@ struct msm_fb_backup_type { bool atomic_commit; }; +struct msm_fb_fps_info { + u32 frame_count; + ktime_t last_sampled_time_us; + u32 measured_fps; +}; + struct msm_fb_data_type { u32 key; u32 index; @@ -271,6 +277,7 @@ struct msm_fb_data_type { int idle_time; u32 idle_state; + struct msm_fb_fps_info fps_info; struct delayed_work idle_notify_work; bool atomic_commit_pending; @@ -426,6 +433,10 @@ static inline bool mdss_fb_is_hdmi_primary(struct msm_fb_data_type *mfd) (mfd->panel_info->type == DTV_PANEL)); } +static inline void mdss_fb_init_fps_info(struct msm_fb_data_type *mfd) +{ + memset(&mfd->fps_info, 0, sizeof(mfd->fps_info)); +} int mdss_fb_get_phys_info(dma_addr_t *start, unsigned long *len, int fb_num); void mdss_fb_set_backlight(struct msm_fb_data_type *mfd, u32 bkl_lvl); void mdss_fb_update_backlight(struct msm_fb_data_type *mfd); @@ -449,4 +460,5 @@ u32 mdss_fb_get_mode_switch(struct msm_fb_data_type *mfd); void mdss_fb_report_panel_dead(struct msm_fb_data_type *mfd); void mdss_panelinfo_to_fb_var(struct mdss_panel_info *pinfo, struct fb_var_screeninfo *var); +void mdss_fb_calc_fps(struct msm_fb_data_type *mfd); #endif /* MDSS_FB_H */ diff --git a/drivers/video/fbdev/msm/mdss_hdcp_1x.c b/drivers/video/fbdev/msm/mdss_hdcp_1x.c index 212f3be96bf2..08307fe8eb16 100644 --- a/drivers/video/fbdev/msm/mdss_hdcp_1x.c +++ b/drivers/video/fbdev/msm/mdss_hdcp_1x.c @@ -195,7 +195,7 @@ struct hdcp_reg_set { #define HDCP_DP_SINK_ADDR_MAP \ {{"bcaps", 0x68028, 1}, {"bksv", 0x68000, 5}, {"r0'", 0x68005, 2}, \ - {"binfo", 0x6802A, 2}, {"cp_irq_status", 0x68029, 2}, \ + {"binfo", 0x6802A, 2}, {"cp_irq_status", 0x68029, 1}, \ {"ksv-fifo", 0x6802C, 0}, {"v_h0", 0x68014, 4}, {"v_h1", 0x68018, 4}, \ {"v_h2", 0x6801C, 4}, {"v_h3", 0x68020, 4}, {"v_h4", 0x68024, 4}, \ {"an", 0x6800C, 8}, {"aksv", 0x68007, 5}, {"ainfo", 0x6803B, 1} } @@ -1763,6 +1763,30 @@ static void hdcp_1x_update_client_reg_set(struct hdcp_1x *hdcp) } } +static bool hdcp_1x_is_cp_irq_raised(struct hdcp_1x *hdcp) +{ + int ret; + u8 buf = 0; + struct hdcp_sink_addr sink = {"irq", 0x201, 1}; + + ret = hdcp_1x_read(hdcp, &sink, &buf, false); + if (IS_ERR_VALUE(ret)) + pr_err("error reading irq_vector\n"); + + return buf & BIT(2) ? true : false; +} + +static void hdcp_1x_clear_cp_irq(struct hdcp_1x *hdcp) +{ + int ret; + u8 buf = BIT(2); + struct hdcp_sink_addr sink = {"irq", 0x201, 1}; + + ret = hdcp_1x_write(hdcp, &sink, &buf); + if (IS_ERR_VALUE(ret)) + pr_err("error clearing irq_vector\n"); +} + static int hdcp_1x_cp_irq(void *input) { struct hdcp_1x *hdcp = (struct hdcp_1x *)input; @@ -1771,14 +1795,19 @@ static int hdcp_1x_cp_irq(void *input) if (!hdcp) { pr_err("invalid input\n"); - goto end; + goto irq_not_handled; + } + + if (!hdcp_1x_is_cp_irq_raised(hdcp)) { + pr_debug("cp_irq not raised\n"); + goto irq_not_handled; } ret = hdcp_1x_read(hdcp, &hdcp->sink_addr.cp_irq_status, &buf, false); if (IS_ERR_VALUE(ret)) { pr_err("error reading cp_irq_status\n"); - return ret; + goto irq_not_handled; } if ((buf & BIT(2)) || (buf & BIT(3))) { @@ -1793,27 +1822,23 @@ static int hdcp_1x_cp_irq(void *input) complete_all(&hdcp->sink_r0_available); hdcp_1x_update_auth_status(hdcp); - - goto end; - } - - if (buf & BIT(1)) { + } else if (buf & BIT(1)) { pr_debug("R0' AVAILABLE\n"); hdcp->sink_r0_ready = true; complete_all(&hdcp->sink_r0_available); - goto end; - } - - if ((buf & BIT(0))) { + } else if ((buf & BIT(0))) { pr_debug("KSVs READY\n"); hdcp->ksv_ready = true; - goto end; + } else { + pr_debug("spurious interrupt\n"); } - return -EINVAL; -end: + hdcp_1x_clear_cp_irq(hdcp); return 0; + +irq_not_handled: + return -EINVAL; } void *hdcp_1x_init(struct hdcp_init_data *init_data) diff --git a/drivers/video/fbdev/msm/mdss_mdp.c b/drivers/video/fbdev/msm/mdss_mdp.c index d9cfd2360ab3..7ed4b5404868 100644 --- a/drivers/video/fbdev/msm/mdss_mdp.c +++ b/drivers/video/fbdev/msm/mdss_mdp.c @@ -2146,6 +2146,7 @@ static void mdss_mdp_hw_rev_caps_init(struct mdss_data_type *mdata) mdata->has_wb_ubwc = true; set_bit(MDSS_CAPS_10_BIT_SUPPORTED, mdata->mdss_caps_map); set_bit(MDSS_CAPS_SEC_DETACH_SMMU, mdata->mdss_caps_map); + mdss_set_quirk(mdata, MDSS_QUIRK_HDR_SUPPORT_ENABLED); break; default: mdata->max_target_zorder = 4; /* excluding base layer */ @@ -2416,13 +2417,16 @@ static int mdss_mdp_get_pan_cfg(struct mdss_panel_cfg *pan_cfg) char *t = NULL; char pan_intf_str[MDSS_MAX_PANEL_LEN]; int rc, i, panel_len; - char pan_name[MDSS_MAX_PANEL_LEN]; + char pan_name[MDSS_MAX_PANEL_LEN] = {'\0'}; if (!pan_cfg) return -EINVAL; if (mdss_mdp_panel[0] == '0') { + pr_debug("panel name is not set\n"); pan_cfg->lk_cfg = false; + pan_cfg->pan_intf = MDSS_PANEL_INTF_INVALID; + return -EINVAL; } else if (mdss_mdp_panel[0] == '1') { pan_cfg->lk_cfg = true; } else { @@ -2432,7 +2436,7 @@ static int mdss_mdp_get_pan_cfg(struct mdss_panel_cfg *pan_cfg) return -EINVAL; } - /* skip lk cfg and delimiter; ex: "0:" */ + /* skip lk cfg and delimiter; ex: "1:" */ strlcpy(pan_name, &mdss_mdp_panel[2], MDSS_MAX_PANEL_LEN); t = strnstr(pan_name, ":", MDSS_MAX_PANEL_LEN); if (!t) { @@ -2689,6 +2693,8 @@ ssize_t mdss_mdp_show_capabilities(struct device *dev, SPRINT(" concurrent_writeback"); if (test_bit(MDSS_CAPS_AVR_SUPPORTED, mdata->mdss_caps_map)) SPRINT(" avr"); + if (mdss_has_quirk(mdata, MDSS_QUIRK_HDR_SUPPORT_ENABLED)) + SPRINT(" hdr"); SPRINT("\n"); #undef SPRINT @@ -2814,7 +2820,10 @@ static int mdss_mdp_probe(struct platform_device *pdev) struct resource *res; int rc; struct mdss_data_type *mdata; - bool display_on = false; + uint32_t intf_sel = 0; + uint32_t split_display = 0; + int num_of_display_on = 0; + int i = 0; if (!pdev->dev.of_node) { pr_err("MDP driver only supports device tree probe\n"); @@ -2941,7 +2950,6 @@ static int mdss_mdp_probe(struct platform_device *pdev) */ mdss_mdp_footswitch_ctrl_splash(true); mdss_hw_rev_init(mdata); - display_on = true; /*populate hw iomem base info from device tree*/ rc = mdss_mdp_parse_dt(pdev); @@ -3010,10 +3018,34 @@ static int mdss_mdp_probe(struct platform_device *pdev) * clk/regulator votes else turn off clk/regulators because purpose * here is to get mdp_rev. */ - display_on = (bool)readl_relaxed(mdata->mdp_base + + intf_sel = readl_relaxed(mdata->mdp_base + MDSS_MDP_REG_DISP_INTF_SEL); - if (!display_on) + split_display = readl_relaxed(mdata->mdp_base + + MDSS_MDP_REG_SPLIT_DISPLAY_EN); + if (intf_sel != 0) { + for (i = 0; i < 4; i++) + num_of_display_on += ((intf_sel >> i*8) & 0x000000FF); + + /* + * For split display enabled - DSI0, DSI1 interfaces are + * considered as single display. So decrement + * 'num_of_display_on' by 1 + */ + if (split_display) + num_of_display_on--; + } + if (!num_of_display_on) { mdss_mdp_footswitch_ctrl_splash(false); + } else { + mdata->handoff_pending = true; + /* + * If multiple displays are enabled in LK, ctrl_splash off will + * be called multiple times during splash_cleanup. Need to + * enable it symmetrically + */ + for (i = 1; i < num_of_display_on; i++) + mdss_mdp_footswitch_ctrl_splash(true); + } mdp_intr_cb = kcalloc(ARRAY_SIZE(mdp_irq_map), sizeof(struct intr_callback), GFP_KERNEL); @@ -3055,12 +3087,13 @@ static int mdss_mdp_probe(struct platform_device *pdev) mdss_res->mdp_irq_export[0] = MDSS_MDP_INTR_WB_0_DONE | MDSS_MDP_INTR_WB_1_DONE; - pr_info("mdss version = 0x%x, bootloader display is %s\n", - mdata->mdp_rev, display_on ? "on" : "off"); + pr_info("mdss version = 0x%x, bootloader display is %s, num %d, intf_sel=0x%08x\n", + mdata->mdp_rev, num_of_display_on ? "on" : "off", + num_of_display_on, intf_sel); probe_done: if (IS_ERR_VALUE(rc)) { - if (display_on) + if (!num_of_display_on) mdss_mdp_footswitch_ctrl_splash(false); if (mdata->regulator_notif_register) @@ -4800,6 +4833,14 @@ static void apply_dynamic_ot_limit(u32 *ot_lim, else *ot_lim = 6; break; + case MDSS_MDP_HW_REV_320: + if ((res <= RES_1080p) && (params->frame_rate <= 30)) + *ot_lim = 2; + else if ((res <= RES_1080p) && (params->frame_rate <= 60)) + *ot_lim = 6; + else if ((res <= RES_UHD) && (params->frame_rate <= 30)) + *ot_lim = 16; + break; default: if (res <= RES_1080p) { *ot_lim = 2; diff --git a/drivers/video/fbdev/msm/mdss_mdp.h b/drivers/video/fbdev/msm/mdss_mdp.h index ab2a7184aa45..d3d332d780d5 100644 --- a/drivers/video/fbdev/msm/mdss_mdp.h +++ b/drivers/video/fbdev/msm/mdss_mdp.h @@ -424,6 +424,7 @@ struct mdss_mdp_ctl_intfs_ops { struct mdss_mdp_cwb { struct mutex queue_lock; struct list_head data_queue; + struct list_head cleanup_queue; int valid; u32 wb_idx; struct mdp_output_layer layer; @@ -1322,12 +1323,21 @@ static inline int mdss_mdp_get_wb_ctl_support(struct mdss_data_type *mdata, bool rotator_session) { /* - * Initial control paths are used for primary and external - * interfaces and remaining control paths are used for WB - * interfaces. + * Any control path can be routed to any of the hardware datapaths. + * But there is a HW restriction for 3D Mux block. As the 3D Mux + * settings in the CTL registers are double buffered, if an interface + * uses it and disconnects, then the subsequent interface which gets + * connected should use the same control path in order to clear the + * 3D MUX settings. + * To handle this restriction, we are allowing WB also, to loop through + * all the avialable control paths, so that it can reuse the control + * path left by the external interface, thereby clearing the 3D Mux + * settings. + * The initial control paths can be used by Primary, External and WB. + * The rotator can use the remaining available control paths. */ return rotator_session ? (mdata->nctl - mdata->nmixers_wb) : - (mdata->nctl - mdata->nwb); + MDSS_MDP_CTL0; } static inline bool mdss_mdp_is_nrt_vbif_client(struct mdss_data_type *mdata, diff --git a/drivers/video/fbdev/msm/mdss_mdp_ctl.c b/drivers/video/fbdev/msm/mdss_mdp_ctl.c index bb8227a74a04..5246e5d1166c 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_ctl.c +++ b/drivers/video/fbdev/msm/mdss_mdp_ctl.c @@ -703,6 +703,7 @@ int mdss_mdp_get_panel_params(struct mdss_mdp_pipe *pipe, *v_total = mixer->height; *xres = mixer->width; *h_total = mixer->width; + *fps = DEFAULT_FRAME_RATE; } return 0; @@ -714,7 +715,8 @@ int mdss_mdp_get_pipe_overlap_bw(struct mdss_mdp_pipe *pipe, struct mdss_data_type *mdata = mdss_mdp_get_mdata(); struct mdss_mdp_mixer *mixer = pipe->mixer_left; struct mdss_rect src, dst; - u32 v_total, fps, h_total, xres, src_h; + u32 v_total = 0, h_total = 0, xres = 0, src_h = 0; + u32 fps = DEFAULT_FRAME_RATE; *quota = 0; *quota_nocr = 0; @@ -3513,7 +3515,6 @@ int mdss_mdp_cwb_setup(struct mdss_mdp_ctl *ctl) struct mdss_overlay_private *mdp5_data = NULL; struct mdss_mdp_wb_data *cwb_data; struct mdss_mdp_writeback_arg wb_args; - struct mdss_mdp_ctl *sctl = NULL; struct mdss_data_type *mdata = mdss_mdp_get_mdata(); u32 opmode, data_point; @@ -3564,6 +3565,11 @@ int mdss_mdp_cwb_setup(struct mdss_mdp_ctl *ctl) goto cwb_setup_fail; } + /* Add to cleanup list */ + mutex_lock(&cwb->queue_lock); + list_add_tail(&cwb_data->next, &mdp5_data->cwb.cleanup_queue); + mutex_unlock(&cwb->queue_lock); + memset(&wb_args, 0, sizeof(wb_args)); wb_args.data = &cwb_data->data; @@ -3575,14 +3581,11 @@ int mdss_mdp_cwb_setup(struct mdss_mdp_ctl *ctl) /* Select MEM_SEL to WB */ ctl->opmode |= MDSS_MDP_CTL_OP_WFD_MODE; - sctl = mdss_mdp_get_split_ctl(ctl); - if (sctl) - sctl->opmode |= MDSS_MDP_CTL_OP_WFD_MODE; /* Select CWB data point */ data_point = (cwb->layer.flags & MDP_COMMIT_CWB_DSPP) ? 0x4 : 0; writel_relaxed(data_point, mdata->mdp_base + mdata->ppb_ctl[2]); - if (sctl) + if (ctl->mixer_right) writel_relaxed(data_point + 1, mdata->mdp_base + mdata->ppb_ctl[3]); @@ -3591,11 +3594,6 @@ int mdss_mdp_cwb_setup(struct mdss_mdp_ctl *ctl) opmode = mdss_mdp_ctl_read(ctl, MDSS_MDP_REG_CTL_TOP) | ctl->opmode; mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_TOP, opmode); - if (sctl) { - opmode = mdss_mdp_ctl_read(sctl, MDSS_MDP_REG_CTL_TOP) | - sctl->opmode; - mdss_mdp_ctl_write(sctl, MDSS_MDP_REG_CTL_TOP, opmode); - } /* Increase commit count to signal CWB release fence */ atomic_inc(&cwb->cwb_sync_pt_data.commit_cnt); diff --git a/drivers/video/fbdev/msm/mdss_mdp_intf_cmd.c b/drivers/video/fbdev/msm/mdss_mdp_intf_cmd.c index 4852fc73f040..c249cac87b8a 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_intf_cmd.c +++ b/drivers/video/fbdev/msm/mdss_mdp_intf_cmd.c @@ -35,6 +35,8 @@ static DEFINE_MUTEX(cmd_clk_mtx); +static DEFINE_MUTEX(cmd_off_mtx); + enum mdss_mdp_cmd_autorefresh_state { MDP_AUTOREFRESH_OFF, MDP_AUTOREFRESH_ON_REQUESTED, @@ -1351,7 +1353,7 @@ static int mdss_mdp_cmd_add_lineptr_handler(struct mdss_mdp_ctl *ctl, unsigned long flags; int ret = 0; - mutex_lock(&ctl->offlock); + mutex_lock(&cmd_off_mtx); ctx = (struct mdss_mdp_cmd_ctx *) ctl->intf_ctx[MASTER_CTX]; if (!ctx || !ctl->is_master) { ret = -EINVAL; @@ -1379,7 +1381,7 @@ static int mdss_mdp_cmd_add_lineptr_handler(struct mdss_mdp_ctl *ctl, if (ctl->mfd->split_mode == MDP_DUAL_LM_DUAL_DISPLAY) mutex_unlock(&cmd_clk_mtx); done: - mutex_unlock(&ctl->offlock); + mutex_unlock(&cmd_off_mtx); return ret; } @@ -1820,7 +1822,7 @@ static int mdss_mdp_cmd_add_vsync_handler(struct mdss_mdp_ctl *ctl, bool enable_rdptr = false; int ret = 0; - mutex_lock(&ctl->offlock); + mutex_lock(&cmd_off_mtx); ctx = (struct mdss_mdp_cmd_ctx *) ctl->intf_ctx[MASTER_CTX]; if (!ctx) { pr_err("%s: invalid ctx\n", __func__); @@ -1857,7 +1859,7 @@ static int mdss_mdp_cmd_add_vsync_handler(struct mdss_mdp_ctl *ctl, } done: - mutex_unlock(&ctl->offlock); + mutex_unlock(&cmd_off_mtx); return ret; } @@ -2110,8 +2112,10 @@ static void mdss_mdp_cmd_dsc_reconfig(struct mdss_mdp_ctl *ctl) } } - changed = ctl->mixer_left->roi_changed; - if (is_split_lm(ctl->mfd)) + if (ctl->mixer_left) + changed |= ctl->mixer_left->roi_changed; + if (is_split_lm(ctl->mfd) && + ctl->mixer_right) changed |= ctl->mixer_right->roi_changed; if (changed) @@ -3188,6 +3192,7 @@ int mdss_mdp_cmd_stop(struct mdss_mdp_ctl *ctl, int panel_power_state) MDSS_XLOG(ctx->panel_power_state, panel_power_state); mutex_lock(&ctl->offlock); + mutex_lock(&cmd_off_mtx); if (mdss_panel_is_power_off(panel_power_state)) { /* Transition to display off */ send_panel_events = true; @@ -3307,6 +3312,7 @@ end: } MDSS_XLOG(ctl->num, atomic_read(&ctx->koff_cnt), XLOG_FUNC_EXIT); + mutex_unlock(&cmd_off_mtx); mutex_unlock(&ctl->offlock); pr_debug("%s:-\n", __func__); diff --git a/drivers/video/fbdev/msm/mdss_mdp_intf_writeback.c b/drivers/video/fbdev/msm/mdss_mdp_intf_writeback.c index 80549908beb6..9bebd72dce61 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_intf_writeback.c +++ b/drivers/video/fbdev/msm/mdss_mdp_intf_writeback.c @@ -262,7 +262,7 @@ static void mdss_mdp_writeback_cwb_overflow(void *arg) mdss_mdp_set_intr_callback_nosync(MDSS_MDP_IRQ_TYPE_CWB_OVERFLOW, CWB_PPB_0, NULL, NULL); - if (mdss_mdp_get_split_ctl(ctl)) { + if (ctl->mixer_right) { mdss_mdp_irq_disable_nosync(MDSS_MDP_IRQ_TYPE_CWB_OVERFLOW, CWB_PPB_1); mdss_mdp_set_intr_callback_nosync( @@ -297,7 +297,7 @@ static void mdss_mdp_writeback_cwb_intr_done(void *arg) mdss_mdp_set_intr_callback_nosync(MDSS_MDP_IRQ_TYPE_CWB_OVERFLOW, CWB_PPB_0, NULL, NULL); - if (mdss_mdp_get_split_ctl(ctl)) { + if (ctl->mixer_right) { mdss_mdp_irq_disable_nosync(MDSS_MDP_IRQ_TYPE_CWB_OVERFLOW, CWB_PPB_1); mdss_mdp_set_intr_callback_nosync( @@ -477,21 +477,34 @@ int mdss_mdp_writeback_prepare_cwb(struct mdss_mdp_ctl *ctl, struct mdss_mdp_writeback_ctx *ctx = NULL; struct mdp_layer_buffer *buffer = NULL; struct mdss_mdp_cwb *cwb = NULL; - struct mdss_mdp_ctl *sctl = NULL; - int ret = 0; + int i, ret = 0; + unsigned long total_buf_len = 0; + struct mdss_mdp_data *data = NULL; + struct mdss_mdp_plane_sizes ps; + struct mdss_mdp_format_params *fmt; + + if (!wb_arg->data) + return -EINVAL; mdp5_data = mfd_to_mdp5_data(ctl->mfd); cwb = &mdp5_data->cwb; ctx = (struct mdss_mdp_writeback_ctx *)cwb->priv_data; + data = wb_arg->data; buffer = &cwb->layer.buffer; - ctx->opmode = 0; - ctx->img_width = buffer->width; + /* + * client can program CWB output dimensions as only primary + * resolution, but output buffer allocated can be with bigger stride + * aligned for platform specific reasons & can interpret the output + * buffer in same stride. Program output stride based on client request + */ + ctx->img_width = buffer->planes[0].stride; ctx->img_height = buffer->height; ctx->width = buffer->width; ctx->height = buffer->height; ctx->frame_rate = ctl->frame_rate; + ctx->opmode = 0; ctx->dst_rect.x = 0; ctx->dst_rect.y = 0; ctx->dst_rect.w = ctx->width; @@ -503,6 +516,23 @@ int mdss_mdp_writeback_prepare_cwb(struct mdss_mdp_ctl *ctl, return ret; } + /* + * Need additional buffer size validation as we are + * updating img_width with buffer->planes[0].stride + */ + fmt = mdss_mdp_get_format_params(buffer->format); + mdss_mdp_get_plane_sizes(fmt, ctx->img_width, + buffer->height, &ps, 0, 0); + + for (i = 0; i < buffer->plane_count ; i++) + total_buf_len += data->p[i].len; + + if (total_buf_len < ps.total_size) { + pr_err("Buffer size=%lu, expected size=%d\n", total_buf_len, + ps.total_size); + return -EINVAL; + } + ret = mdss_mdp_writeback_addr_setup(ctx, wb_arg->data); if (ret) { pr_err("cwb writeback data setup error\n"); @@ -516,11 +546,10 @@ int mdss_mdp_writeback_prepare_cwb(struct mdss_mdp_ctl *ctl, CWB_PPB_0, mdss_mdp_writeback_cwb_overflow, ctl); mdss_mdp_irq_enable(MDSS_MDP_IRQ_TYPE_CWB_OVERFLOW, CWB_PPB_0); - sctl = mdss_mdp_get_split_ctl(ctl); - if (sctl) { + if (ctl->mixer_right) { mdss_mdp_set_intr_callback(MDSS_MDP_IRQ_TYPE_CWB_OVERFLOW, CWB_PPB_1, mdss_mdp_writeback_cwb_overflow, - sctl); + ctl); mdss_mdp_irq_enable(MDSS_MDP_IRQ_TYPE_CWB_OVERFLOW, CWB_PPB_1); } diff --git a/drivers/video/fbdev/msm/mdss_mdp_layer.c b/drivers/video/fbdev/msm/mdss_mdp_layer.c index 0731cbcafe7c..c53c8d293539 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_layer.c +++ b/drivers/video/fbdev/msm/mdss_mdp_layer.c @@ -2823,6 +2823,8 @@ int mdss_mdp_layer_pre_commit_cwb(struct msm_fb_data_type *mfd, } mdp5_data->cwb.layer = *commit->output_layer; + mdp5_data->cwb.layer.flags |= (commit->flags & MDP_COMMIT_CWB_DSPP) ? + MDP_COMMIT_CWB_DSPP : 0; mdp5_data->cwb.wb_idx = commit->output_layer->writeback_ndx; mutex_lock(&mdp5_data->cwb.queue_lock); diff --git a/drivers/video/fbdev/msm/mdss_mdp_overlay.c b/drivers/video/fbdev/msm/mdss_mdp_overlay.c index 59a25ee95900..8f48956680fc 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_overlay.c +++ b/drivers/video/fbdev/msm/mdss_mdp_overlay.c @@ -1931,8 +1931,7 @@ static void __restore_pipe(struct mdss_mdp_pipe *pipe) } /** - * __crop_adjust_pipe_rect() - Adjust pipe roi for dual partial - * update feature. + * __adjust_pipe_rect() - Adjust pipe roi for dual partial update feature. * @pipe: pipe to check against. * @dual_roi: roi's for the dual partial roi. * @@ -1940,53 +1939,54 @@ static void __restore_pipe(struct mdss_mdp_pipe *pipe) * by merging the two width aligned ROIs (first_roi and * second_roi) vertically. So, the y-offset of all the * pipes belonging to the second_roi needs to adjusted - * accordingly. Also the cropping of the pipe's src/dst - * rect has to be done with respect to the ROI the pipe - * is intersecting with, before the adjustment. + * accordingly. Also check, if the pipe dest rect is + * totally within first or second ROI. */ -static int __crop_adjust_pipe_rect(struct mdss_mdp_pipe *pipe, +static int __adjust_pipe_rect(struct mdss_mdp_pipe *pipe, struct mdss_dsi_dual_pu_roi *dual_roi) { u32 adjust_h; - u32 roi_y_pos; int ret = 0; + struct mdss_rect res_rect; if (mdss_rect_overlap_check(&pipe->dst, &dual_roi->first_roi)) { - mdss_mdp_crop_rect(&pipe->src, &pipe->dst, - &dual_roi->first_roi, false); - pipe->restore_roi = true; + mdss_mdp_intersect_rect(&res_rect, &pipe->dst, + &dual_roi->first_roi); + if (!mdss_rect_cmp(&res_rect, &pipe->dst)) { + ret = -EINVAL; + goto end; + } } else if (mdss_rect_overlap_check(&pipe->dst, &dual_roi->second_roi)) { - mdss_mdp_crop_rect(&pipe->src, &pipe->dst, - &dual_roi->second_roi, false); - adjust_h = dual_roi->second_roi.y; - roi_y_pos = dual_roi->first_roi.y + dual_roi->first_roi.h; - - if (adjust_h > roi_y_pos) { - adjust_h = adjust_h - roi_y_pos; - pipe->dst.y -= adjust_h; - } else { - pr_err("wrong y-pos adjust_y:%d roi_y_pos:%d\n", - adjust_h, roi_y_pos); + mdss_mdp_intersect_rect(&res_rect, &pipe->dst, + &dual_roi->second_roi); + if (!mdss_rect_cmp(&res_rect, &pipe->dst)) { ret = -EINVAL; + goto end; } + + adjust_h = dual_roi->second_roi.y - + (dual_roi->first_roi.y + dual_roi->first_roi.h); + pipe->dst.y -= adjust_h; pipe->restore_roi = true; } else { ret = -EINVAL; + goto end; } - pr_debug("crop/adjusted p:%d src:{%d,%d,%d,%d} dst:{%d,%d,%d,%d} r:%d\n", + pr_debug("adjusted p:%d src:{%d,%d,%d,%d} dst:{%d,%d,%d,%d} r:%d\n", pipe->num, pipe->src.x, pipe->src.y, pipe->src.w, pipe->src.h, pipe->dst.x, pipe->dst.y, pipe->dst.w, pipe->dst.h, pipe->restore_roi); +end: if (ret) { - pr_err("dual roi error p%d dst{%d,%d,%d,%d}", - pipe->num, pipe->dst.x, pipe->dst.y, pipe->dst.w, - pipe->dst.h); - pr_err(" roi1{%d,%d,%d,%d} roi2{%d,%d,%d,%d}\n", + pr_err("pipe:%d dst:{%d,%d,%d,%d} - not cropped for any PU ROI", + pipe->num, pipe->dst.x, pipe->dst.y, + pipe->dst.w, pipe->dst.h); + pr_err("ROI0:{%d,%d,%d,%d} ROI1:{%d,%d,%d,%d}\n", dual_roi->first_roi.x, dual_roi->first_roi.y, dual_roi->first_roi.w, dual_roi->first_roi.h, dual_roi->second_roi.x, dual_roi->second_roi.y, @@ -2109,7 +2109,7 @@ static void __validate_and_set_roi(struct msm_fb_data_type *mfd, pipe->dst.y, pipe->dst.w, pipe->dst.h); if (dual_roi->enabled) { - if (__crop_adjust_pipe_rect(pipe, dual_roi)) { + if (__adjust_pipe_rect(pipe, dual_roi)) { skip_partial_update = true; break; } @@ -2117,7 +2117,7 @@ static void __validate_and_set_roi(struct msm_fb_data_type *mfd, if (!__is_roi_valid(pipe, &l_roi, &r_roi)) { skip_partial_update = true; - pr_err("error. invalid pu config for pipe%d: %d,%d,%d,%d, dual_pu_roi:%d\n", + pr_err("error. invalid pu config for pipe:%d dst:{%d,%d,%d,%d} dual_pu_roi:%d\n", pipe->num, pipe->dst.x, pipe->dst.y, pipe->dst.w, pipe->dst.h, dual_roi->enabled); @@ -2288,7 +2288,7 @@ int mdss_mdp_overlay_kickoff(struct msm_fb_data_type *mfd, int ret = 0; struct mdss_mdp_commit_cb commit_cb; - if (!ctl) + if (!ctl || !ctl->mixer_left) return -ENODEV; ATRACE_BEGIN(__func__); @@ -2325,7 +2325,6 @@ int mdss_mdp_overlay_kickoff(struct msm_fb_data_type *mfd, mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON); mdss_mdp_check_ctl_reset_status(ctl); - __vsync_set_vsync_handler(mfd); __validate_and_set_roi(mfd, data); if (ctl->ops.wait_pingpong && mdp5_data->mdata->serialize_wait4pp) @@ -2374,6 +2373,7 @@ int mdss_mdp_overlay_kickoff(struct msm_fb_data_type *mfd, &commit_cb); ATRACE_END("display_commit"); } + __vsync_set_vsync_handler(mfd); /* * release the commit pending flag; we are releasing this flag @@ -3228,6 +3228,7 @@ int mdss_mdp_dfps_update_params(struct msm_fb_data_type *mfd, pr_warn("Unsupported FPS. Configuring to max_fps = %d\n", pdata->panel_info.max_fps); dfps = pdata->panel_info.max_fps; + dfps_data->fps = dfps; } dfps_update_panel_params(pdata, dfps_data); @@ -5872,10 +5873,24 @@ __vsync_retire_get_fence(struct msm_sync_pt_data *sync_pt_data) static void __cwb_wq_handler(struct work_struct *cwb_work) { struct mdss_mdp_cwb *cwb = NULL; + struct mdss_mdp_wb_data *cwb_data = NULL; cwb = container_of(cwb_work, struct mdss_mdp_cwb, cwb_work); blocking_notifier_call_chain(&cwb->notifier_head, MDP_NOTIFY_FRAME_DONE, NULL); + + /* free the buffer from cleanup queue */ + mutex_lock(&cwb->queue_lock); + cwb_data = list_first_entry_or_null(&cwb->cleanup_queue, + struct mdss_mdp_wb_data, next); + __list_del_entry(&cwb_data->next); + mutex_unlock(&cwb->queue_lock); + if (cwb_data == NULL) { + pr_err("no output buffer for cwb cleanup\n"); + return; + } + mdss_mdp_data_free(&cwb_data->data, true, DMA_FROM_DEVICE); + kfree(cwb_data); } static int __vsync_set_vsync_handler(struct msm_fb_data_type *mfd) @@ -6106,6 +6121,7 @@ int mdss_mdp_overlay_init(struct msm_fb_data_type *mfd) mutex_init(&mdp5_data->cwb.queue_lock); mutex_init(&mdp5_data->cwb.cwb_sync_pt_data.sync_mutex); INIT_LIST_HEAD(&mdp5_data->cwb.data_queue); + INIT_LIST_HEAD(&mdp5_data->cwb.cleanup_queue); snprintf(timeline_name, sizeof(timeline_name), "cwb%d", mfd->index); mdp5_data->cwb.cwb_sync_pt_data.fence_name = "cwb-fence"; diff --git a/drivers/video/fbdev/msm/mdss_mdp_pp.c b/drivers/video/fbdev/msm/mdss_mdp_pp.c index 917e6889124d..30dd3c856c7f 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_pp.c +++ b/drivers/video/fbdev/msm/mdss_mdp_pp.c @@ -1655,10 +1655,6 @@ int mdss_mdp_scaler_lut_cfg(struct mdp_scale_data_v2 *scaler, } } - if (scaler->lut_flag & SCALER_LUT_SWAP) - writel_relaxed(BIT(0), MDSS_MDP_REG_SCALER_COEF_LUT_CTRL + - offset); - return 0; } @@ -1795,6 +1791,10 @@ int mdss_mdp_qseed3_setup(struct mdp_scale_data_v2 *scaler, __func__); return -EINVAL; } + if (scaler->lut_flag & SCALER_LUT_SWAP) + writel_relaxed(BIT(0), + MDSS_MDP_REG_SCALER_COEF_LUT_CTRL + + offset); } writel_relaxed(phase_init, diff --git a/drivers/video/fbdev/msm/mdss_mdp_pp_cache_config.c b/drivers/video/fbdev/msm/mdss_mdp_pp_cache_config.c index e51cf44c2de2..017a2f10dfbc 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_pp_cache_config.c +++ b/drivers/video/fbdev/msm/mdss_mdp_pp_cache_config.c @@ -1394,7 +1394,6 @@ exit: ret = -EFAULT; kfree(cfg_payload); cfg_payload = NULL; - goto exit; } pp_info->igc_cfg.cfg_payload = cfg_payload; return ret; diff --git a/drivers/video/fbdev/msm/mdss_rotator.c b/drivers/video/fbdev/msm/mdss_rotator.c index 8612d60deeca..d001f148b443 100644 --- a/drivers/video/fbdev/msm/mdss_rotator.c +++ b/drivers/video/fbdev/msm/mdss_rotator.c @@ -2386,6 +2386,31 @@ handle_request32_err: return ret; } +static unsigned int __do_compat_ioctl_rot(unsigned int cmd32) +{ + unsigned int cmd; + + switch (cmd32) { + case MDSS_ROTATION_REQUEST32: + cmd = MDSS_ROTATION_REQUEST; + break; + case MDSS_ROTATION_OPEN32: + cmd = MDSS_ROTATION_OPEN; + break; + case MDSS_ROTATION_CLOSE32: + cmd = MDSS_ROTATION_CLOSE; + break; + case MDSS_ROTATION_CONFIG32: + cmd = MDSS_ROTATION_CONFIG; + break; + default: + cmd = cmd32; + break; + } + + return cmd; +} + static long mdss_rotator_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { @@ -2408,6 +2433,8 @@ static long mdss_rotator_compat_ioctl(struct file *file, unsigned int cmd, return -EINVAL; } + cmd = __do_compat_ioctl_rot(cmd); + switch (cmd) { case MDSS_ROTATION_REQUEST: ATRACE_BEGIN("rotator_request32"); diff --git a/drivers/video/fbdev/msm/mdss_rotator_internal.h b/drivers/video/fbdev/msm/mdss_rotator_internal.h index dae5f5cb117e..30d460abf5b7 100644 --- a/drivers/video/fbdev/msm/mdss_rotator_internal.h +++ b/drivers/video/fbdev/msm/mdss_rotator_internal.h @@ -187,6 +187,23 @@ struct mdss_rot_mgr { }; #ifdef CONFIG_COMPAT + +/* open a rotation session */ +#define MDSS_ROTATION_OPEN32 \ + _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 1, compat_caddr_t) + +/* change the rotation session configuration */ +#define MDSS_ROTATION_CONFIG32 \ + _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 2, compat_caddr_t) + +/* queue the rotation request */ +#define MDSS_ROTATION_REQUEST32 \ + _IOWR(MDSS_ROTATOR_IOCTL_MAGIC, 3, compat_caddr_t) + +/* close a rotation session with the specified rotation session ID */ +#define MDSS_ROTATION_CLOSE32 \ + _IOW(MDSS_ROTATOR_IOCTL_MAGIC, 4, unsigned int) + struct mdp_rotation_request32 { uint32_t version; uint32_t flags; diff --git a/drivers/video/fbdev/msm/mdss_smmu.c b/drivers/video/fbdev/msm/mdss_smmu.c index 2239791fdad0..a08eec8e1606 100644 --- a/drivers/video/fbdev/msm/mdss_smmu.c +++ b/drivers/video/fbdev/msm/mdss_smmu.c @@ -177,7 +177,6 @@ static int mdss_smmu_attach_v2(struct mdss_data_type *mdata) struct mdss_smmu_client *mdss_smmu; int i, rc = 0; - mutex_lock(&mdp_iommu_lock); for (i = 0; i < MDSS_IOMMU_MAX_DOMAIN; i++) { if (!mdss_smmu_is_valid_domain_type(mdata, i)) continue; @@ -211,11 +210,9 @@ static int mdss_smmu_attach_v2(struct mdss_data_type *mdata) } } else { pr_err("iommu device not attached for domain[%d]\n", i); - mutex_unlock(&mdp_iommu_lock); return -ENODEV; } } - mutex_unlock(&mdp_iommu_lock); return 0; @@ -228,7 +225,6 @@ err: mdss_smmu->domain_attached = false; } } - mutex_unlock(&mdp_iommu_lock); return rc; } @@ -245,7 +241,6 @@ static int mdss_smmu_detach_v2(struct mdss_data_type *mdata) struct mdss_smmu_client *mdss_smmu; int i; - mutex_lock(&mdp_iommu_lock); for (i = 0; i < MDSS_IOMMU_MAX_DOMAIN; i++) { if (!mdss_smmu_is_valid_domain_type(mdata, i)) continue; @@ -270,7 +265,6 @@ static int mdss_smmu_detach_v2(struct mdss_data_type *mdata) } } } - mutex_unlock(&mdp_iommu_lock); return 0; } diff --git a/drivers/video/fbdev/msm/mdss_smmu.h b/drivers/video/fbdev/msm/mdss_smmu.h index f7e6e275c16a..73b978b72f0e 100644 --- a/drivers/video/fbdev/msm/mdss_smmu.h +++ b/drivers/video/fbdev/msm/mdss_smmu.h @@ -150,18 +150,26 @@ static inline int mdss_smmu_attach(struct mdss_data_type *mdata) { int rc; + mdata->mdss_util->iommu_lock(); MDSS_XLOG(mdata->iommu_attached); + if (mdata->iommu_attached) { pr_debug("mdp iommu already attached\n"); - return 0; + rc = 0; + goto end; } - if (!mdata->smmu_ops.smmu_attach) - return -ENOSYS; + if (!mdata->smmu_ops.smmu_attach) { + rc = -ENODEV; + goto end; + } rc = mdata->smmu_ops.smmu_attach(mdata); if (!rc) mdata->iommu_attached = true; + +end: + mdata->mdss_util->iommu_unlock(); return rc; } @@ -169,19 +177,26 @@ static inline int mdss_smmu_detach(struct mdss_data_type *mdata) { int rc; + mdata->mdss_util->iommu_lock(); MDSS_XLOG(mdata->iommu_attached); if (!mdata->iommu_attached) { pr_debug("mdp iommu already dettached\n"); - return 0; + rc = 0; + goto end; } - if (!mdata->smmu_ops.smmu_detach) - return -ENOSYS; + if (!mdata->smmu_ops.smmu_detach) { + rc = -ENODEV; + goto end; + } rc = mdata->smmu_ops.smmu_detach(mdata); if (!rc) mdata->iommu_attached = false; + +end: + mdata->mdss_util->iommu_unlock(); return rc; } @@ -247,7 +262,7 @@ static inline void mdss_smmu_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t phys, dma_addr_t iova, int domain) { struct mdss_data_type *mdata = mdss_mdp_get_mdata(); - if (mdata->smmu_ops.smmu_dma_free_coherent) + if (mdata && mdata->smmu_ops.smmu_dma_free_coherent) mdata->smmu_ops.smmu_dma_free_coherent(dev, size, cpu_addr, phys, iova, domain); } diff --git a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h index aa76fbad5083..4bf87f6c08bf 100644 --- a/include/dt-bindings/clock/qcom,gcc-msmfalcon.h +++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ -#ifndef _DT_BINDINGS_CLK_MSM_GCC_FALCON_H -#define _DT_BINDINGS_CLK_MSM_GCC_FALCON_H +#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H +#define _DT_BINDINGS_CLK_MSM_GCC_660_H /* Hardware/Dummy/Voter clocks */ #define GCC_XO 0 diff --git a/include/dt-bindings/clock/qcom,gpu-msmfalcon.h b/include/dt-bindings/clock/qcom,gpu-sdm660.h index 2ef1e34db3a1..80b49d3420e3 100644 --- a/include/dt-bindings/clock/qcom,gpu-msmfalcon.h +++ b/include/dt-bindings/clock/qcom,gpu-sdm660.h @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ -#ifndef _DT_BINDINGS_CLK_MSM_GPU_FALCON_H -#define _DT_BINDINGS_CLK_MSM_GPU_FALCON_H +#ifndef _DT_BINDINGS_CLK_MSM_GPU_660_H +#define _DT_BINDINGS_CLK_MSM_GPU_660_H #define GFX3D_CLK_SRC 0 #define GPU_PLL0_PLL 1 diff --git a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h b/include/dt-bindings/clock/qcom,mmcc-sdm660.h index 91309b4616a6..cc7c0033d6ea 100644 --- a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h +++ b/include/dt-bindings/clock/qcom,mmcc-sdm660.h @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ -#ifndef _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H -#define _DT_BINDINGS_CLK_MSM_MMCC_FALCON_H +#ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H +#define _DT_BINDINGS_CLK_MSM_MMCC_660_H #define MMSS_CAMSS_JPEG0_VOTE_CLK 0 #define MMSS_CAMSS_JPEG0_DMA_VOTE_CLK 1 diff --git a/include/linux/qpnp/power-on.h b/include/linux/input/qpnp-power-on.h index da8f5a8622dd..a2624ab57826 100644 --- a/include/linux/qpnp/power-on.h +++ b/include/linux/input/qpnp-power-on.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2015, 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -60,7 +60,7 @@ enum pon_restart_reason { PON_RESTART_REASON_KEYS_CLEAR = 0x06, }; -#ifdef CONFIG_QPNP_POWER_ON +#ifdef CONFIG_INPUT_QPNP_POWER_ON int qpnp_pon_system_pwr_off(enum pon_power_off_type type); int qpnp_pon_is_warm_reset(void); int qpnp_pon_trigger_config(enum pon_trigger_source pon_src, bool enable); diff --git a/include/linux/qpnp/qpnp-revid.h b/include/linux/qpnp/qpnp-revid.h index 8d9bbfd67992..4023e3a683d3 100644 --- a/include/linux/qpnp/qpnp-revid.h +++ b/include/linux/qpnp/qpnp-revid.h @@ -177,9 +177,9 @@ /* PMI8998 */ #define PMI8998_SUBTYPE 0x15 -/* PMFALCON */ -#define PM2FALCON_SUBTYPE 0x1A -#define PMFALCON_SUBTYPE 0x1B +/* PM660 */ +#define PM660L_SUBTYPE 0x1A +#define PM660_SUBTYPE 0x1B #define PMI8998_V1P0_REV1 0x00 #define PMI8998_V1P0_REV2 0x00 diff --git a/include/media/msm_vidc.h b/include/media/msm_vidc.h index 0a089c4faee1..003adc38eb14 100644 --- a/include/media/msm_vidc.h +++ b/include/media/msm_vidc.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -68,6 +68,7 @@ struct msm_smem { void *smem_priv; enum hal_buffer buffer_type; struct dma_mapping_info mapping_info; + unsigned int offset; }; enum smem_cache_ops { diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index 733a479f3f17..94ace231b3bd 100644 --- a/include/net/cfg80211.h +++ b/include/net/cfg80211.h @@ -68,6 +68,7 @@ struct wiphy; #define CFG80211_CONNECT_BSS 1 #define CFG80211_ABORT_SCAN 1 #define CFG80211_UPDATE_CONNECT_PARAMS 1 +#define CFG80211_BEACON_TX_RATE_CUSTOM_BACKPORT 1 /* * wireless hardware capability structures diff --git a/include/soc/qcom/icnss.h b/include/soc/qcom/icnss.h index 9c38b9aa5627..14892a05bd19 100644 --- a/include/soc/qcom/icnss.h +++ b/include/soc/qcom/icnss.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -124,6 +124,7 @@ extern int icnss_get_wlan_unsafe_channel(u16 *unsafe_ch_list, u16 *ch_count, extern int icnss_wlan_set_dfs_nol(const void *info, u16 info_len); extern int icnss_wlan_get_dfs_nol(void *info, u16 info_len); extern bool icnss_is_qmi_disable(void); +extern bool icnss_is_fw_ready(void); extern int icnss_set_wlan_mac_address(const u8 *in, const uint32_t len); extern u8 *icnss_get_wlan_mac_address(struct device *dev, uint32_t *num); diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h index 3e5f7be53204..ac36df5769ee 100644 --- a/include/soc/qcom/socinfo.h +++ b/include/soc/qcom/socinfo.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -94,12 +94,18 @@ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,apq8998") #define early_machine_is_msmhamster() \ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmhamster") -#define early_machine_is_msmfalcon() \ - of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmfalcon") -#define early_machine_is_apqfalcon() \ - of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,apqfalcon") -#define early_machine_is_msmtriton() \ - of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmtriton") +#define early_machine_is_sdm660() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sdm660") +#define early_machine_is_sda660() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sda660") +#define early_machine_is_sdm658() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sdm658") +#define early_machine_is_sda658() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sda658") +#define early_machine_is_sdm630() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sdm630") +#define early_machine_is_sda630() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sda630") #else #define of_board_is_sim() 0 #define of_board_is_rumi() 0 @@ -136,9 +142,12 @@ #define early_machine_is_msm8998() 0 #define early_machine_is_apq8998() 0 #define early_machine_is_msmhamster() 0 -#define early_machine_is_msmfalcon() 0 -#define early_machine_is_apqfalcon() 0 -#define early_machine_is_msmtriton() 0 +#define early_machine_is_sdm660() 0 +#define early_machine_is_sda660() 0 +#define early_machine_is_sdm658() 0 +#define early_machine_is_sda658() 0 +#define early_machine_is_sdm630() 0 +#define early_machine_is_sda630() 0 #endif #define PLATFORM_SUBTYPE_MDM 1 @@ -197,8 +206,8 @@ enum msm_cpu { MSM_CPU_8929, MSM_CPU_8998, MSM_CPU_HAMSTER, - MSM_CPU_FALCON, - MSM_CPU_TRITON, + MSM_CPU_660, + MSM_CPU_630, }; struct msm_soc_info { diff --git a/include/trace/events/msm_cam.h b/include/trace/events/msm_cam.h new file mode 100644 index 000000000000..b52845407ef0 --- /dev/null +++ b/include/trace/events/msm_cam.h @@ -0,0 +1,136 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM msm_cam + +#if !defined(_TRACE_MSM_VFE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_MSM_VFE_H + +#include "msm_isp.h" +#include <linux/types.h> +#include <linux/tracepoint.h> + +#define STRING_LEN 80 + + +TRACE_EVENT(msm_cam_string, + TP_PROTO(const char *str), + TP_ARGS(str), + TP_STRUCT__entry( + __array(char, str, STRING_LEN) + ), + TP_fast_assign( + strlcpy(__entry->str, str, STRING_LEN); + ), + TP_printk("msm_cam: %s", __entry->str) +); + +TRACE_EVENT(msm_cam_tasklet_debug_dump, + TP_PROTO(struct msm_vfe_irq_debug_info tasklet_state), + TP_ARGS(tasklet_state), + TP_STRUCT__entry( + __field(unsigned int, vfe_id) + __field(unsigned int, core_id) + __field(unsigned int, irq_status0) + __field(unsigned int, irq_status1) + __field(unsigned int, ping_pong_status) + __field(long, tv_sec) + __field(long, tv_usec) + ), + TP_fast_assign( + __entry->vfe_id = tasklet_state.vfe_id; + __entry->irq_status0 = + tasklet_state.irq_status0[tasklet_state.vfe_id]; + __entry->irq_status1 = + tasklet_state.irq_status1[tasklet_state.vfe_id]; + __entry->core_id = tasklet_state.core_id; + __entry->ping_pong_status = + tasklet_state.ping_pong_status[tasklet_state.vfe_id]; + __entry->tv_sec = + tasklet_state.ts.buf_time.tv_sec; + __entry->tv_usec = + tasklet_state.ts.buf_time.tv_usec; + ), + TP_printk("vfe_id %d, core %d, irq_st0 0x%x, irq_st1 0x%x\n" + "pi_po_st 0x%x, time %ld:%ld", + __entry->vfe_id, + __entry->core_id, + __entry->irq_status0, + __entry->irq_status1, + __entry->ping_pong_status, + __entry->tv_sec, + __entry->tv_usec + ) +); + +TRACE_EVENT(msm_cam_ping_pong_debug_dump, + TP_PROTO(struct msm_vfe_irq_debug_info ping_pong_state), + TP_ARGS(ping_pong_state), + TP_STRUCT__entry( + __field(unsigned int, curr_vfe_id) + __field(unsigned int, curr_irq_status0) + __field(unsigned int, curr_irq_status1) + __field(unsigned int, curr_ping_pong_status) + __field(unsigned int, othr_vfe_id) + __field(unsigned int, othr_irq_status0) + __field(unsigned int, othr_irq_status1) + __field(unsigned int, othr_ping_pong_status) + __field(long, othr_tv_sec) + __field(long, othr_tv_usec) + __field(unsigned int, core_id) + ), + TP_fast_assign( + __entry->curr_vfe_id = + ping_pong_state.vfe_id; + __entry->curr_irq_status0 = + ping_pong_state.irq_status0[ping_pong_state.vfe_id]; + __entry->curr_irq_status1 = + ping_pong_state.irq_status1[ping_pong_state.vfe_id]; + __entry->curr_ping_pong_status = + ping_pong_state. + ping_pong_status[ping_pong_state.vfe_id]; + __entry->othr_vfe_id = + !ping_pong_state.vfe_id; + __entry->othr_irq_status0 = + ping_pong_state.irq_status0[!ping_pong_state.vfe_id]; + __entry->othr_irq_status1 = + ping_pong_state.irq_status1[!ping_pong_state.vfe_id]; + __entry->othr_ping_pong_status = + ping_pong_state. + ping_pong_status[!ping_pong_state.vfe_id]; + __entry->othr_tv_sec = + ping_pong_state.ts.buf_time.tv_sec; + __entry->othr_tv_usec = + ping_pong_state.ts.buf_time.tv_usec; + __entry->core_id = ping_pong_state.core_id; + ), + TP_printk("vfe_id %d, irq_st0 0x%x, irq_st1 0x%x, pi_po_st 0x%x\n" + "other vfe_id %d, irq_st0 0x%x, irq_st1 0x%x\n" + "pi_po_st 0x%x, time %ld:%ld core %d", + __entry->curr_vfe_id, + __entry->curr_irq_status0, + __entry->curr_irq_status1, + __entry->curr_ping_pong_status, + __entry->othr_vfe_id, + __entry->othr_irq_status0, + __entry->othr_irq_status1, + __entry->othr_ping_pong_status, + __entry->othr_tv_sec, + __entry->othr_tv_usec, + __entry->core_id + ) +); + +#endif /* _MSM_CAM_TRACE_H */ +/* This part must be outside protection */ +#include <trace/define_trace.h> diff --git a/include/uapi/linux/msm_mdp.h b/include/uapi/linux/msm_mdp.h index 4df3845c159c..fca2a3c2d494 100644 --- a/include/uapi/linux/msm_mdp.h +++ b/include/uapi/linux/msm_mdp.h @@ -118,7 +118,7 @@ #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msmtitanium */ #define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msm8998 */ #define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msm8998 v1.0 */ -#define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) /* msmfalcon */ +#define MDSS_MDP_HW_REV_320 MDSS_MDP_REV(3, 2, 0) /* sdm660 */ enum { NOTIFY_UPDATE_INIT, diff --git a/include/uapi/media/msm_media_info.h b/include/uapi/media/msm_media_info.h index 50b8fc32b129..746eee61ad0e 100644 --- a/include/uapi/media/msm_media_info.h +++ b/include/uapi/media/msm_media_info.h @@ -986,6 +986,22 @@ static inline unsigned int VENUS_BUFFER_SIZE( MSM_MEDIA_MAX(extra_size + 8192, 48 * y_stride); size = MSM_MEDIA_ALIGN(size, 4096); break; + case COLOR_FMT_P010_UBWC: + y_ubwc_plane = MSM_MEDIA_ALIGN(y_stride * y_sclines, 4096); + uv_ubwc_plane = MSM_MEDIA_ALIGN(uv_stride * uv_sclines, 4096); + y_meta_stride = VENUS_Y_META_STRIDE(color_fmt, width); + y_meta_scanlines = VENUS_Y_META_SCANLINES(color_fmt, height); + y_meta_plane = MSM_MEDIA_ALIGN( + y_meta_stride * y_meta_scanlines, 4096); + uv_meta_stride = VENUS_UV_META_STRIDE(color_fmt, width); + uv_meta_scanlines = VENUS_UV_META_SCANLINES(color_fmt, height); + uv_meta_plane = MSM_MEDIA_ALIGN(uv_meta_stride * + uv_meta_scanlines, 4096); + + size = y_ubwc_plane + uv_ubwc_plane + y_meta_plane + + uv_meta_plane; + size = MSM_MEDIA_ALIGN(size, 4096); + break; case COLOR_FMT_RGBA8888: rgb_plane = MSM_MEDIA_ALIGN(rgb_stride * rgb_scanlines, 4096); size = rgb_plane; diff --git a/kernel/sched/hmp.c b/kernel/sched/hmp.c index a8bf39c6d7d7..d3547391b937 100644 --- a/kernel/sched/hmp.c +++ b/kernel/sched/hmp.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -774,13 +774,6 @@ __read_mostly unsigned int sched_ravg_window = MIN_SCHED_RAVG_WINDOW; /* Temporarily disable window-stats activity on all cpus */ unsigned int __read_mostly sched_disable_window_stats; -/* - * Major task runtime. If a task runs for more than sched_major_task_runtime - * in a window, it's considered to be generating majority of workload - * for this window. Prediction could be adjusted for such tasks. - */ -__read_mostly unsigned int sched_major_task_runtime = 10000000; - static unsigned int sync_cpu; struct related_thread_group *related_thread_groups[MAX_NUM_CGROUP_COLOC_ID]; @@ -1015,9 +1008,6 @@ void set_hmp_defaults(void) update_up_down_migrate(); - sched_major_task_runtime = - mult_frac(sched_ravg_window, MAJOR_TASK_PCT, 100); - sched_init_task_load_windows = div64_u64((u64)sysctl_sched_init_task_load_pct * (u64)sched_ravg_window, 100); @@ -1470,7 +1460,20 @@ int sched_hmp_proc_update_handler(struct ctl_table *table, int write, int ret; unsigned int old_val; unsigned int *data = (unsigned int *)table->data; - int update_min_nice = 0; + int update_task_count = 0; + + if (!sched_enable_hmp) + return 0; + + /* + * The policy mutex is acquired with cpu_hotplug.lock + * held from cpu_up()->cpufreq_governor_interactive()-> + * sched_set_window(). So enforce the same order here. + */ + if (write && (data == &sysctl_sched_upmigrate_pct)) { + update_task_count = 1; + get_online_cpus(); + } mutex_lock(&policy_mutex); @@ -1478,7 +1481,7 @@ int sched_hmp_proc_update_handler(struct ctl_table *table, int write, ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); - if (ret || !write || !sched_enable_hmp) + if (ret || !write) goto done; if (write && (old_val == *data)) @@ -1500,20 +1503,18 @@ int sched_hmp_proc_update_handler(struct ctl_table *table, int write, * includes taking runqueue lock of all online cpus and re-initiatizing * their big counter values based on changed criteria. */ - if ((data == &sysctl_sched_upmigrate_pct || update_min_nice)) { - get_online_cpus(); + if (update_task_count) pre_big_task_count_change(cpu_online_mask); - } set_hmp_defaults(); - if ((data == &sysctl_sched_upmigrate_pct || update_min_nice)) { + if (update_task_count) post_big_task_count_change(cpu_online_mask); - put_online_cpus(); - } done: mutex_unlock(&policy_mutex); + if (update_task_count) + put_online_cpus(); return ret; } @@ -1950,8 +1951,6 @@ scale_load_to_freq(u64 load, unsigned int src_freq, unsigned int dst_freq) return div64_u64(load * (u64)src_freq, (u64)dst_freq); } -#define HEAVY_TASK_SKIP 2 -#define HEAVY_TASK_SKIP_LIMIT 4 /* * get_pred_busy - calculate predicted demand for a task on runqueue * @@ -1979,7 +1978,7 @@ static u32 get_pred_busy(struct rq *rq, struct task_struct *p, u32 *hist = p->ravg.sum_history; u32 dmin, dmax; u64 cur_freq_runtime = 0; - int first = NUM_BUSY_BUCKETS, final, skip_to; + int first = NUM_BUSY_BUCKETS, final; u32 ret = runtime; /* skip prediction for new tasks due to lack of history */ @@ -1999,36 +1998,6 @@ static u32 get_pred_busy(struct rq *rq, struct task_struct *p, /* compute the bucket for prediction */ final = first; - if (first < HEAVY_TASK_SKIP_LIMIT) { - /* compute runtime at current CPU frequency */ - cur_freq_runtime = mult_frac(runtime, max_possible_efficiency, - rq->cluster->efficiency); - cur_freq_runtime = scale_load_to_freq(cur_freq_runtime, - max_possible_freq, rq->cluster->cur_freq); - /* - * if the task runs for majority of the window, try to - * pick higher buckets. - */ - if (cur_freq_runtime >= sched_major_task_runtime) { - int next = NUM_BUSY_BUCKETS; - /* - * if there is a higher bucket that's consistently - * hit, don't jump beyond that. - */ - for (i = start + 1; i <= HEAVY_TASK_SKIP_LIMIT && - i < NUM_BUSY_BUCKETS; i++) { - if (buckets[i] > CONSISTENT_THRES) { - next = i; - break; - } - } - skip_to = min(next, start + HEAVY_TASK_SKIP); - /* don't jump beyond HEAVY_TASK_SKIP_LIMIT */ - skip_to = min(HEAVY_TASK_SKIP_LIMIT, skip_to); - /* don't go below first non-empty bucket, if any */ - final = max(first, skip_to); - } - } /* determine demand range for the predicted bucket */ if (final < 2) { @@ -3897,7 +3866,7 @@ static void transfer_busy_time(struct rq *rq, struct related_thread_group *grp, struct migration_sum_data d; int migrate_type; int cpu = cpu_of(rq); - bool new_task = is_new_task(p); + bool new_task; int i; if (!sched_freq_aggregate) @@ -3907,6 +3876,7 @@ static void transfer_busy_time(struct rq *rq, struct related_thread_group *grp, update_task_ravg(rq->curr, rq, TASK_UPDATE, wallclock, 0); update_task_ravg(p, rq, TASK_UPDATE, wallclock, 0); + new_task = is_new_task(p); /* cpu_time protected by related_thread_group_lock, grp->lock rq_lock */ cpu_time = _group_cpu_time(grp, cpu); @@ -4001,6 +3971,8 @@ static void transfer_busy_time(struct rq *rq, struct related_thread_group *grp, BUG_ON((s64)*src_curr_runnable_sum < 0); BUG_ON((s64)*src_prev_runnable_sum < 0); + BUG_ON((s64)*src_nt_curr_runnable_sum < 0); + BUG_ON((s64)*src_nt_prev_runnable_sum < 0); } static inline struct group_cpu_time * diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index afccfd0878b1..a3abdf19ff4c 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -1066,7 +1066,6 @@ static inline void sched_ttwu_pending(void) { } #define FREQ_REPORT_CPU_LOAD 1 #define FREQ_REPORT_TOP_TASK 2 -#define MAJOR_TASK_PCT 85 #define SCHED_UPMIGRATE_MIN_NICE 15 #define EXITING_TASK_MARKER 0xdeaddead @@ -1093,7 +1092,6 @@ extern unsigned int sched_init_task_load_windows; extern unsigned int up_down_migrate_scale_factor; extern unsigned int sysctl_sched_restrict_cluster_spill; extern unsigned int sched_pred_alert_load; -extern unsigned int sched_major_task_runtime; extern struct sched_cluster init_cluster; extern unsigned int __read_mostly sched_short_sleep_task_threshold; extern unsigned int __read_mostly sched_long_cpu_selection_threshold; diff --git a/kernel/time/hrtimer.c b/kernel/time/hrtimer.c index 271d83e30d19..bf7fc4989e5c 100644 --- a/kernel/time/hrtimer.c +++ b/kernel/time/hrtimer.c @@ -1850,15 +1850,19 @@ schedule_hrtimeout_range_clock(ktime_t *expires, u64 delta, * You can set the task state as follows - * * %TASK_UNINTERRUPTIBLE - at least @timeout time is guaranteed to - * pass before the routine returns. + * pass before the routine returns unless the current task is explicitly + * woken up, (e.g. by wake_up_process()). * * %TASK_INTERRUPTIBLE - the routine may return early if a signal is - * delivered to the current task. + * delivered to the current task or the current task is explicitly woken + * up. * * The current task state is guaranteed to be TASK_RUNNING when this * routine returns. * - * Returns 0 when the timer has expired otherwise -EINTR + * Returns 0 when the timer has expired. If the task was woken before the + * timer expired by a signal (only possible in state TASK_INTERRUPTIBLE) or + * by an explicit wakeup, it returns -EINTR. */ int __sched schedule_hrtimeout_range(ktime_t *expires, u64 delta, const enum hrtimer_mode mode) @@ -1880,15 +1884,19 @@ EXPORT_SYMBOL_GPL(schedule_hrtimeout_range); * You can set the task state as follows - * * %TASK_UNINTERRUPTIBLE - at least @timeout time is guaranteed to - * pass before the routine returns. + * pass before the routine returns unless the current task is explicitly + * woken up, (e.g. by wake_up_process()). * * %TASK_INTERRUPTIBLE - the routine may return early if a signal is - * delivered to the current task. + * delivered to the current task or the current task is explicitly woken + * up. * * The current task state is guaranteed to be TASK_RUNNING when this * routine returns. * - * Returns 0 when the timer has expired otherwise -EINTR + * Returns 0 when the timer has expired. If the task was woken before the + * timer expired by a signal (only possible in state TASK_INTERRUPTIBLE) or + * by an explicit wakeup, it returns -EINTR. */ int __sched schedule_hrtimeout(ktime_t *expires, const enum hrtimer_mode mode) diff --git a/kernel/time/timer.c b/kernel/time/timer.c index 5ebefc7cfa4f..2bde2c2b1cb3 100644 --- a/kernel/time/timer.c +++ b/kernel/time/timer.c @@ -811,8 +811,15 @@ static struct tvec_base *lock_timer_base(struct timer_list *timer, __acquires(timer->base->lock) { for (;;) { - u32 tf = timer->flags; struct tvec_base *base; + u32 tf; + + /* + * We need to use READ_ONCE() here, otherwise the compiler + * might re-read @tf between the check for TIMER_MIGRATING + * and spin_lock(). + */ + tf = READ_ONCE(timer->flags); if (!(tf & TIMER_MIGRATING)) { base = get_timer_base(tf); @@ -1529,11 +1536,12 @@ static void process_timeout(unsigned long __data) * You can set the task state as follows - * * %TASK_UNINTERRUPTIBLE - at least @timeout jiffies are guaranteed to - * pass before the routine returns. The routine will return 0 + * pass before the routine returns unless the current task is explicitly + * woken up, (e.g. by wake_up_process())". * * %TASK_INTERRUPTIBLE - the routine may return early if a signal is - * delivered to the current task. In this case the remaining time - * in jiffies will be returned, or 0 if the timer expired in time + * delivered to the current task or the current task is explicitly woken + * up. * * The current task state is guaranteed to be TASK_RUNNING when this * routine returns. @@ -1542,7 +1550,9 @@ static void process_timeout(unsigned long __data) * the CPU away without a bound on the timeout. In this case the return * value will be %MAX_SCHEDULE_TIMEOUT. * - * In all cases the return value is guaranteed to be non-negative. + * Returns 0 when the timer has expired otherwise the remaining time in + * jiffies will be returned. In all cases the return value is guaranteed + * to be non-negative. */ signed long __sched schedule_timeout(signed long timeout) { @@ -1777,16 +1787,6 @@ unsigned long msleep_interruptible(unsigned int msecs) EXPORT_SYMBOL(msleep_interruptible); -static void __sched do_usleep_range(unsigned long min, unsigned long max) -{ - ktime_t kmin; - u64 delta; - - kmin = ktime_set(0, min * NSEC_PER_USEC); - delta = (u64)(max - min) * NSEC_PER_USEC; - schedule_hrtimeout_range(&kmin, delta, HRTIMER_MODE_REL); -} - /** * usleep_range - Drop in replacement for udelay where wakeup is flexible * @min: Minimum time in usecs to sleep @@ -1794,7 +1794,14 @@ static void __sched do_usleep_range(unsigned long min, unsigned long max) */ void __sched usleep_range(unsigned long min, unsigned long max) { - __set_current_state(TASK_UNINTERRUPTIBLE); - do_usleep_range(min, max); + ktime_t exp = ktime_add_us(ktime_get(), min); + u64 delta = (u64)(max - min) * NSEC_PER_USEC; + + for (;;) { + __set_current_state(TASK_UNINTERRUPTIBLE); + /* Do not return before the requested sleep time has elapsed */ + if (!schedule_hrtimeout_range(&exp, delta, HRTIMER_MODE_ABS)) + break; + } } EXPORT_SYMBOL(usleep_range); diff --git a/net/ipc_router/ipc_router_core.c b/net/ipc_router/ipc_router_core.c index 008d034fcf8f..d23799a5b260 100644 --- a/net/ipc_router/ipc_router_core.c +++ b/net/ipc_router/ipc_router_core.c @@ -2809,6 +2809,9 @@ int msm_ipc_router_register_server(struct msm_ipc_port *port_ptr, if (!port_ptr || !name) return -EINVAL; + if (port_ptr->type != CLIENT_PORT) + return -EINVAL; + if (name->addrtype != MSM_IPC_ADDR_NAME) return -EINVAL; diff --git a/net/netfilter/xt_IDLETIMER.c b/net/netfilter/xt_IDLETIMER.c index 456a1dff692d..80b32de1d99c 100644 --- a/net/netfilter/xt_IDLETIMER.c +++ b/net/netfilter/xt_IDLETIMER.c @@ -49,6 +49,7 @@ #include <linux/notifier.h> #include <net/net_namespace.h> #include <net/sock.h> +#include <net/inet_sock.h> struct idletimer_tg_attr { struct attribute attr; @@ -360,8 +361,8 @@ static void reset_timer(const struct idletimer_tg_info *info, /* Stores the uid resposible for waking up the radio */ if (skb && (skb->sk)) { - timer->uid = from_kuid_munged(current_user_ns(), - sock_i_uid(skb->sk)); + timer->uid = from_kuid_munged + (current_user_ns(), sock_i_uid(skb_to_full_sk(skb))); } /* checks if there is a pending inactive notification*/ diff --git a/net/rmnet_data/rmnet_map_command.c b/net/rmnet_data/rmnet_map_command.c index 055d5f402957..9dac2b27d4c3 100644 --- a/net/rmnet_data/rmnet_map_command.c +++ b/net/rmnet_data/rmnet_map_command.c @@ -121,6 +121,7 @@ static void rmnet_map_send_ack(struct sk_buff *skb, { struct rmnet_map_control_command_s *cmd; int xmit_status; + int rc; if (unlikely(!skb)) BUG(); @@ -149,6 +150,15 @@ static void rmnet_map_send_ack(struct sk_buff *skb, netif_tx_unlock(skb->dev); LOGD("MAP command ACK=%hhu sent with rc: %d", type & 0x03, xmit_status); + + if (xmit_status != NETDEV_TX_OK) { + rc = dev_queue_xmit(skb); + if (rc != 0) { + LOGD("Failed to queue packet for transmission on [%s]", + skb->dev->name); + } + } + } /** diff --git a/scripts/build-all.py b/scripts/build-all.py index 9e4942d21da9..4f02c33d4248 100755 --- a/scripts/build-all.py +++ b/scripts/build-all.py @@ -303,9 +303,11 @@ def scan_configs(): r'apq*_defconfig', r'qsd*_defconfig', r'mpq*_defconfig', + r'sdm[0-9]*_defconfig', ) arch64_pats = ( r'msm*_defconfig', + r'sdm[0-9]*_defconfig', ) for p in arch_pats: for n in glob.glob('arch/arm/configs/' + p): diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 26a5356fb30e..8d623d01425b 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -765,11 +765,11 @@ config SND_SOC_WCD_CPE config AUDIO_EXT_CLK tristate - default y if SND_SOC_WCD9335=y || SND_SOC_WCD9330=y || SND_SOC_MSMFALCON_CDC=y + default y if SND_SOC_WCD9335=y || SND_SOC_WCD9330=y || SND_SOC_SDM660_CDC=y config SND_SOC_WCD_MBHC tristate - default y if (SND_SOC_MSM8909_WCD=y || SND_SOC_MSMFALCON_CDC=y || SND_SOC_WCD9335=y) && SND_SOC_MDMCALIFORNIUM!=y + default y if (SND_SOC_MSM8909_WCD=y || SND_SOC_SDM660_CDC=y || SND_SOC_WCD9335=y) && SND_SOC_MDMCALIFORNIUM!=y config SND_SOC_WCD_DSP_MGR tristate @@ -994,7 +994,7 @@ config SND_SOC_MSM_HDMI_CODEC_RX HDMI audio drivers should be built only if the platform supports hdmi panel. -source "sound/soc/codecs/msmfalcon_cdc/Kconfig" +source "sound/soc/codecs/sdm660_cdc/Kconfig" source "sound/soc/codecs/msm_sdw/Kconfig" endmenu diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 9dcdc517b9ea..5305cc6071e8 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -425,5 +425,5 @@ obj-$(CONFIG_SND_SOC_MSM_STUB) += snd-soc-msm-stub.o # Amp obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o -obj-y += msmfalcon_cdc/ +obj-y += sdm660_cdc/ obj-y += msm_sdw/ diff --git a/sound/soc/codecs/msmfalcon_cdc/Makefile b/sound/soc/codecs/msmfalcon_cdc/Makefile deleted file mode 100644 index 814308d9f5b0..000000000000 --- a/sound/soc/codecs/msmfalcon_cdc/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -snd-soc-msmfalcon-cdc-objs := msm-analog-cdc.o msm-digital-cdc.o msmfalcon-regmap.o -obj-$(CONFIG_SND_SOC_MSMFALCON_CDC) += snd-soc-msmfalcon-cdc.o msmfalcon-cdc-irq.o diff --git a/sound/soc/codecs/msmfalcon_cdc/Kconfig b/sound/soc/codecs/sdm660_cdc/Kconfig index dc461a619781..d370da3d2ad5 100644 --- a/sound/soc/codecs/msmfalcon_cdc/Kconfig +++ b/sound/soc/codecs/sdm660_cdc/Kconfig @@ -1,3 +1,3 @@ -config SND_SOC_MSMFALCON_CDC +config SND_SOC_SDM660_CDC tristate "MSM Internal PMIC based codec" diff --git a/sound/soc/codecs/sdm660_cdc/Makefile b/sound/soc/codecs/sdm660_cdc/Makefile new file mode 100644 index 000000000000..d846fae26054 --- /dev/null +++ b/sound/soc/codecs/sdm660_cdc/Makefile @@ -0,0 +1,2 @@ +snd-soc-sdm660-cdc-objs := msm-analog-cdc.o msm-digital-cdc.o sdm660-regmap.o +obj-$(CONFIG_SND_SOC_SDM660_CDC) += snd-soc-sdm660-cdc.o sdm660-cdc-irq.o diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.c b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.c index 33c5e103dfe7..cee4720bbe31 100644 --- a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.c +++ b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.c @@ -28,17 +28,17 @@ #include <sound/tlv.h> #include <sound/q6core.h> #include "msm-analog-cdc.h" -#include "msmfalcon-cdc-irq.h" -#include "msmfalcon-cdc-registers.h" +#include "sdm660-cdc-irq.h" +#include "sdm660-cdc-registers.h" #include "msm-cdc-common.h" -#include "../../msm/msmfalcon-common.h" +#include "../../msm/sdm660-common.h" #include "../wcd-mbhc-v2.h" #define DRV_NAME "pmic_analog_codec" -#define MSMFALCON_CDC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ +#define SDM660_CDC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ SNDRV_PCM_RATE_48000) -#define MSMFALCON_CDC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ +#define SDM660_CDC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ SNDRV_PCM_FMTBIT_S24_LE) #define MSM_DIG_CDC_STRING_LEN 80 #define MSM_ANLG_CDC_VERSION_ENTRY_SIZE 32 @@ -74,8 +74,8 @@ enum { #define MAX_BOOST_VOLTAGE 5550 #define BOOST_VOLTAGE_STEP 50 -#define MSMFALCON_CDC_MBHC_BTN_COARSE_ADJ 100 /* in mV */ -#define MSMFALCON_CDC_MBHC_BTN_FINE_ADJ 12 /* in mV */ +#define SDM660_CDC_MBHC_BTN_COARSE_ADJ 100 /* in mV */ +#define SDM660_CDC_MBHC_BTN_FINE_ADJ 12 /* in mV */ #define VOLTAGE_CONVERTER(value, min_value, step_size)\ ((value - min_value)/step_size) @@ -192,10 +192,10 @@ static const struct wcd_mbhc_intr intr_ids = { }; static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev, - struct msmfalcon_cdc_regulator *vreg, + struct sdm660_cdc_regulator *vreg, const char *vreg_name, bool ondemand); -static struct msmfalcon_cdc_pdata *msm_anlg_cdc_populate_dt_pdata( +static struct sdm660_cdc_pdata *msm_anlg_cdc_populate_dt_pdata( struct device *dev); static int msm_anlg_cdc_enable_ext_mb_source(struct wcd_mbhc *wcd_mbhc, bool turn_on); @@ -208,21 +208,21 @@ static void msm_anlg_cdc_configure_cap(struct snd_soc_codec *codec, bool micbias1, bool micbias2); static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec); -static int get_codec_version(struct msmfalcon_cdc_priv *msmfalcon_cdc) +static int get_codec_version(struct sdm660_cdc_priv *sdm660_cdc) { - if (msmfalcon_cdc->codec_version == DRAX_CDC) + if (sdm660_cdc->codec_version == DRAX_CDC) return DRAX_CDC; - else if (msmfalcon_cdc->codec_version == DIANGU) + else if (sdm660_cdc->codec_version == DIANGU) return DIANGU; - else if (msmfalcon_cdc->codec_version == CAJON_2_0) + else if (sdm660_cdc->codec_version == CAJON_2_0) return CAJON_2_0; - else if (msmfalcon_cdc->codec_version == CAJON) + else if (sdm660_cdc->codec_version == CAJON) return CAJON; - else if (msmfalcon_cdc->codec_version == CONGA) + else if (sdm660_cdc->codec_version == CONGA) return CONGA; - else if (msmfalcon_cdc->pmic_rev == TOMBAK_2_0) + else if (sdm660_cdc->pmic_rev == TOMBAK_2_0) return TOMBAK_2_0; - else if (msmfalcon_cdc->pmic_rev == TOMBAK_1_0) + else if (sdm660_cdc->pmic_rev == TOMBAK_1_0) return TOMBAK_1_0; pr_err("%s: unsupported codec version\n", __func__); @@ -232,11 +232,11 @@ static int get_codec_version(struct msmfalcon_cdc_priv *msmfalcon_cdc) static void wcd_mbhc_meas_imped(struct snd_soc_codec *codec, s16 *impedance_l, s16 *impedance_r) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if ((msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) || - (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHL)) { + if ((sdm660_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) || + (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL)) { /* Enable ZDET_L_MEAS_EN */ snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, @@ -251,8 +251,8 @@ static void wcd_mbhc_meas_imped(struct snd_soc_codec *codec, MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x08, 0x00); } - if ((msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) || - (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)) { + if ((sdm660_cdc->imped_det_pin == WCD_MBHC_DET_BOTH) || + (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR)) { snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x04, 0x04); @@ -270,16 +270,16 @@ static void wcd_mbhc_meas_imped(struct snd_soc_codec *codec, static void msm_anlg_cdc_set_ref_current(struct snd_soc_codec *codec, enum wcd_curr_ref curr_ref) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: curr_ref: %d\n", __func__, curr_ref); - if (get_codec_version(msmfalcon_cdc) < CAJON) + if (get_codec_version(sdm660_cdc) < CAJON) dev_dbg(codec->dev, "%s: Setting ref current not required\n", __func__); - msmfalcon_cdc->imped_i_ref = imped_i_ref[curr_ref]; + sdm660_cdc->imped_i_ref = imped_i_ref[curr_ref]; switch (curr_ref) { case I_h4_UA: @@ -318,15 +318,15 @@ static bool msm_anlg_cdc_adj_ref_current(struct snd_soc_codec *codec, { int i = 2; s16 compare_imp = 0; - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) + if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) compare_imp = *impedance_r; else compare_imp = *impedance_l; - if (get_codec_version(msmfalcon_cdc) < CAJON) { + if (get_codec_version(sdm660_cdc) < CAJON) { dev_dbg(codec->dev, "%s: Reference current adjustment not required\n", __func__); @@ -336,7 +336,7 @@ static bool msm_anlg_cdc_adj_ref_current(struct snd_soc_codec *codec, while (compare_imp < imped_i_ref[i].min_val) { msm_anlg_cdc_set_ref_current(codec, imped_i_ref[++i].curr_ref); wcd_mbhc_meas_imped(codec, impedance_l, impedance_r); - compare_imp = (msmfalcon_cdc->imped_det_pin == + compare_imp = (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) ? *impedance_r : *impedance_l; if (i >= I_1_UA) break; @@ -348,28 +348,28 @@ void msm_anlg_cdc_spk_ext_pa_cb( int (*codec_spk_ext_pa)(struct snd_soc_codec *codec, int enable), struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc; + struct sdm660_cdc_priv *sdm660_cdc; if (!codec) { pr_err("%s: NULL codec pointer!\n", __func__); return; } - msmfalcon_cdc = snd_soc_codec_get_drvdata(codec); + sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: Enter\n", __func__); - msmfalcon_cdc->codec_spk_ext_pa_cb = codec_spk_ext_pa; + sdm660_cdc->codec_spk_ext_pa_cb = codec_spk_ext_pa; } static void msm_anlg_cdc_compute_impedance(struct snd_soc_codec *codec, s16 l, s16 r, uint32_t *zl, uint32_t *zr, bool high) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); uint32_t rl = 0, rr = 0; - struct wcd_imped_i_ref R = msmfalcon_cdc->imped_i_ref; - int codec_ver = get_codec_version(msmfalcon_cdc); + struct wcd_imped_i_ref R = sdm660_cdc->imped_i_ref; + int codec_ver = get_codec_version(sdm660_cdc); switch (codec_ver) { case TOMBAK_1_0: @@ -393,17 +393,17 @@ static void msm_anlg_cdc_compute_impedance(struct snd_soc_codec *codec, s16 l, case CAJON_2_0: case DIANGU: case DRAX_CDC: - if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHL) { + if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL) { rr = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * r - 5)) - (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN); rl = (uint32_t)(((10000 * (R.multiplier * (10 * l - 5))) - R.offset * R.gain_adj)/(R.gain_adj * 100)); - } else if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) { + } else if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) { rr = (uint32_t)(((10000 * (R.multiplier * (10 * r - 5))) - R.offset * R.gain_adj)/(R.gain_adj * 100)); rl = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * l - 5))- (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN); - } else if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_NONE) { + } else if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_NONE) { rr = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * r - 5)) - (DEFAULT_OFFSET * DEFAULT_GAIN))/DEFAULT_GAIN); rl = (uint32_t)(((DEFAULT_MULTIPLIER * (10 * l - 5))- @@ -427,7 +427,7 @@ static struct firmware_cal *msm_anlg_cdc_get_hwdep_fw_cal( struct wcd_mbhc *wcd_mbhc, enum wcd_cal_type type) { - struct msmfalcon_cdc_priv *msmfalcon_cdc; + struct sdm660_cdc_priv *sdm660_cdc; struct firmware_cal *hwdep_cal; struct snd_soc_codec *codec = wcd_mbhc->codec; @@ -435,8 +435,8 @@ static struct firmware_cal *msm_anlg_cdc_get_hwdep_fw_cal( pr_err("%s: NULL codec pointer\n", __func__); return NULL; } - msmfalcon_cdc = snd_soc_codec_get_drvdata(codec); - hwdep_cal = wcdcal_get_fw_cal(msmfalcon_cdc->fw_data, type); + sdm660_cdc = snd_soc_codec_get_drvdata(codec); + hwdep_cal = wcdcal_get_fw_cal(sdm660_cdc->fw_data, type); if (!hwdep_cal) { dev_err(codec->dev, "%s: cal not sent by %d\n", __func__, type); @@ -595,9 +595,9 @@ static void msm_anlg_cdc_mbhc_program_btn_thr(struct snd_soc_codec *codec, btn_voltage = ((is_micbias) ? btn_high : btn_low); for (i = 0; i < num_btn; i++) { - course = (btn_voltage[i] / MSMFALCON_CDC_MBHC_BTN_COARSE_ADJ); - fine = ((btn_voltage[i] % MSMFALCON_CDC_MBHC_BTN_COARSE_ADJ) / - MSMFALCON_CDC_MBHC_BTN_FINE_ADJ); + course = (btn_voltage[i] / SDM660_CDC_MBHC_BTN_COARSE_ADJ); + fine = ((btn_voltage[i] % SDM660_CDC_MBHC_BTN_COARSE_ADJ) / + SDM660_CDC_MBHC_BTN_FINE_ADJ); reg_val = (course << 5) | (fine << 2); snd_soc_update_bits(codec, reg_addr, 0xFC, reg_val); @@ -612,7 +612,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc, uint32_t *zl, uint32_t *zr) { struct snd_soc_codec *codec = mbhc->codec; - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); s16 impedance_l, impedance_r; s16 impedance_l_fixed; @@ -627,7 +627,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc, reg3 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MICB_2_EN); reg4 = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL); - msmfalcon_cdc->imped_det_pin = WCD_MBHC_DET_BOTH; + sdm660_cdc->imped_det_pin = WCD_MBHC_DET_BOTH; mbhc->hph_type = WCD_MBHC_HPH_NONE; /* disable FSM and micbias and enable pullup*/ @@ -673,21 +673,21 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc, snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, 0x03, 0x00); - msmfalcon_cdc->imped_det_pin = (impedance_l > 2 && + sdm660_cdc->imped_det_pin = (impedance_l > 2 && impedance_r > 2) ? WCD_MBHC_DET_NONE : ((impedance_l > 2) ? WCD_MBHC_DET_HPHR : WCD_MBHC_DET_HPHL); - if (msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_NONE) + if (sdm660_cdc->imped_det_pin == WCD_MBHC_DET_NONE) goto exit; } else { - if (get_codec_version(msmfalcon_cdc) >= CAJON) { + if (get_codec_version(sdm660_cdc) >= CAJON) { if (impedance_l == 63 && impedance_r == 63) { dev_dbg(codec->dev, "%s: HPHL and HPHR are floating\n", __func__); - msmfalcon_cdc->imped_det_pin = + sdm660_cdc->imped_det_pin = WCD_MBHC_DET_NONE; mbhc->hph_type = WCD_MBHC_HPH_NONE; } else if (impedance_l == 63 @@ -695,7 +695,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc, dev_dbg(codec->dev, "%s: Mono HS with HPHL floating\n", __func__); - msmfalcon_cdc->imped_det_pin = + sdm660_cdc->imped_det_pin = WCD_MBHC_DET_HPHR; mbhc->hph_type = WCD_MBHC_HPH_MONO; } else if (impedance_r == 63 && @@ -703,7 +703,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc, dev_dbg(codec->dev, "%s: Mono HS with HPHR floating\n", __func__); - msmfalcon_cdc->imped_det_pin = + sdm660_cdc->imped_det_pin = WCD_MBHC_DET_HPHL; mbhc->hph_type = WCD_MBHC_HPH_MONO; } else if (impedance_l > 3 && impedance_r > 3 && @@ -717,7 +717,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc, dev_dbg(codec->dev, "%s: Mono Headset\n", __func__); - msmfalcon_cdc->imped_det_pin = + sdm660_cdc->imped_det_pin = WCD_MBHC_DET_NONE; mbhc->hph_type = WCD_MBHC_HPH_MONO; @@ -725,7 +725,7 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc, dev_dbg(codec->dev, "%s: STEREO headset is found\n", __func__); - msmfalcon_cdc->imped_det_pin = + sdm660_cdc->imped_det_pin = WCD_MBHC_DET_BOTH; mbhc->hph_type = WCD_MBHC_HPH_STEREO; } @@ -777,8 +777,8 @@ static void msm_anlg_cdc_mbhc_calc_impedance(struct wcd_mbhc *mbhc, */ if (!min_range_used || - msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHL || - msmfalcon_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) + sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHL || + sdm660_cdc->imped_det_pin == WCD_MBHC_DET_HPHR) goto exit; @@ -875,7 +875,7 @@ static int msm_anlg_cdc_dig_register_notifier(void *handle, struct notifier_block *nblock, bool enable) { - struct msmfalcon_cdc *handle_cdc = handle; + struct sdm660_cdc *handle_cdc = handle; if (enable) return blocking_notifier_chain_register(&handle_cdc->notifier, @@ -889,15 +889,15 @@ static int msm_anlg_cdc_mbhc_register_notifier(struct wcd_mbhc *wcd_mbhc, bool enable) { struct snd_soc_codec *codec = wcd_mbhc->codec; - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); if (enable) return blocking_notifier_chain_register( - &msmfalcon_cdc->notifier, + &sdm660_cdc->notifier, nblock); - return blocking_notifier_chain_unregister(&msmfalcon_cdc->notifier, + return blocking_notifier_chain_unregister(&sdm660_cdc->notifier, nblock); } @@ -945,27 +945,27 @@ static const uint32_t wcd_imped_val[] = {4, 8, 12, 13, 16, static void msm_anlg_cdc_dig_notifier_call(struct snd_soc_codec *codec, const enum dig_cdc_notify_event event) { - struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data; + struct sdm660_cdc *sdm660_cdc = codec->control_data; pr_debug("%s: notifier call event %d\n", __func__, event); - blocking_notifier_call_chain(&msmfalcon_cdc->notifier, + blocking_notifier_call_chain(&sdm660_cdc->notifier, event, NULL); } static void msm_anlg_cdc_notifier_call(struct snd_soc_codec *codec, const enum wcd_notify_event event) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: notifier call event %d\n", __func__, event); - blocking_notifier_call_chain(&msmfalcon_cdc->notifier, event, - &msmfalcon_cdc->mbhc); + blocking_notifier_call_chain(&sdm660_cdc->notifier, event, + &sdm660_cdc->mbhc); } static void msm_anlg_cdc_boost_on(struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); snd_soc_update_bits(codec, @@ -973,7 +973,7 @@ static void msm_anlg_cdc_boost_on(struct snd_soc_codec *codec) snd_soc_write(codec, MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5); snd_soc_write(codec, MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x0F); snd_soc_write(codec, MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x30); - if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) + if (get_codec_version(sdm660_cdc) < CAJON_2_0) snd_soc_write(codec, MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82); else snd_soc_write(codec, MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0xA2); @@ -987,7 +987,7 @@ static void msm_anlg_cdc_boost_on(struct snd_soc_codec *codec) 0x03, 0x03); snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1, 0xE1); - if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) { + if (get_codec_version(sdm660_cdc) < CAJON_2_0) { snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x20, 0x20); /* Wait for 1ms after clock ctl enable */ @@ -1021,10 +1021,10 @@ static void msm_anlg_cdc_boost_off(struct snd_soc_codec *codec) static void msm_anlg_cdc_bypass_on(struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) { + if (get_codec_version(sdm660_cdc) < CAJON_2_0) { snd_soc_write(codec, MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5); @@ -1058,10 +1058,10 @@ static void msm_anlg_cdc_bypass_on(struct snd_soc_codec *codec) static void msm_anlg_cdc_bypass_off(struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) { + if (get_codec_version(sdm660_cdc) < CAJON_2_0) { snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, 0x80, 0x00); @@ -1087,13 +1087,13 @@ static void msm_anlg_cdc_bypass_off(struct snd_soc_codec *codec) static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec, int flag) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); if (flag == EAR_PMU) { - switch (msmfalcon_cdc->boost_option) { + switch (sdm660_cdc->boost_option) { case BOOST_SWITCH: - if (msmfalcon_cdc->ear_pa_boost_set) { + if (sdm660_cdc->ear_pa_boost_set) { msm_anlg_cdc_boost_off(codec); msm_anlg_cdc_bypass_on(codec); } @@ -1110,13 +1110,13 @@ static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec, default: dev_err(codec->dev, "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); + sdm660_cdc->boost_option); break; } } else if (flag == EAR_PMD) { - switch (msmfalcon_cdc->boost_option) { + switch (sdm660_cdc->boost_option) { case BOOST_SWITCH: - if (msmfalcon_cdc->ear_pa_boost_set) + if (sdm660_cdc->ear_pa_boost_set) msm_anlg_cdc_bypass_off(codec); break; case BOOST_ALWAYS: @@ -1133,13 +1133,13 @@ static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec, default: dev_err(codec->dev, "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); + sdm660_cdc->boost_option); break; } } else if (flag == SPK_PMU) { - switch (msmfalcon_cdc->boost_option) { + switch (sdm660_cdc->boost_option) { case BOOST_SWITCH: - if (msmfalcon_cdc->spk_boost_set) { + if (sdm660_cdc->spk_boost_set) { msm_anlg_cdc_bypass_off(codec); msm_anlg_cdc_boost_on(codec); } @@ -1156,13 +1156,13 @@ static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec, default: dev_err(codec->dev, "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); + sdm660_cdc->boost_option); break; } } else if (flag == SPK_PMD) { - switch (msmfalcon_cdc->boost_option) { + switch (sdm660_cdc->boost_option) { case BOOST_SWITCH: - if (msmfalcon_cdc->spk_boost_set) { + if (sdm660_cdc->spk_boost_set) { msm_anlg_cdc_boost_off(codec); /* * Add 40 ms sleep for the spk @@ -1188,14 +1188,14 @@ static void msm_anlg_cdc_boost_mode_sequence(struct snd_soc_codec *codec, default: dev_err(codec->dev, "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); + sdm660_cdc->boost_option); break; } } } static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev, - struct msmfalcon_cdc_regulator *vreg, const char *vreg_name, + struct sdm660_cdc_regulator *vreg, const char *vreg_name, bool ondemand) { int len, ret = 0; @@ -1250,7 +1250,7 @@ static int msm_anlg_cdc_dt_parse_vreg_info(struct device *dev, static void msm_anlg_cdc_dt_parse_boost_info(struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = + struct sdm660_cdc_priv *sdm660_cdc_priv = snd_soc_codec_get_drvdata(codec); const char *prop_name = "qcom,cdc-boost-voltage"; int boost_voltage, ret; @@ -1269,7 +1269,7 @@ static void msm_anlg_cdc_dt_parse_boost_info(struct snd_soc_codec *codec) boost_voltage = DEFAULT_BOOST_VOLTAGE; } - msmfalcon_cdc_priv->boost_voltage = + sdm660_cdc_priv->boost_voltage = VOLTAGE_CONVERTER(boost_voltage, MIN_BOOST_VOLTAGE, BOOST_VOLTAGE_STEP); dev_dbg(codec->dev, "Boost voltage value is: %d\n", @@ -1291,10 +1291,10 @@ static void msm_anlg_cdc_dt_parse_micbias_info(struct device *dev, } } -static struct msmfalcon_cdc_pdata *msm_anlg_cdc_populate_dt_pdata( +static struct sdm660_cdc_pdata *msm_anlg_cdc_populate_dt_pdata( struct device *dev) { - struct msmfalcon_cdc_pdata *pdata; + struct sdm660_cdc_pdata *pdata; int ret, static_cnt, ond_cnt, idx, i; const char *name = NULL; const char *static_prop_name = "qcom,cdc-static-supplies"; @@ -1384,7 +1384,7 @@ static int msm_anlg_cdc_codec_enable_on_demand_supply( { int ret = 0; struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); struct on_demand_supply *supply; @@ -1396,9 +1396,9 @@ static int msm_anlg_cdc_codec_enable_on_demand_supply( } dev_dbg(codec->dev, "%s: supply: %s event: %d ref: %d\n", __func__, on_demand_supply_name[w->shift], event, - atomic_read(&msmfalcon_cdc->on_demand_list[w->shift].ref)); + atomic_read(&sdm660_cdc->on_demand_list[w->shift].ref)); - supply = &msmfalcon_cdc->on_demand_list[w->shift]; + supply = &sdm660_cdc->on_demand_list[w->shift]; WARN_ONCE(!supply->supply, "%s isn't defined\n", on_demand_supply_name[w->shift]); if (!supply->supply) { @@ -1462,7 +1462,7 @@ static int msm_anlg_cdc_codec_enable_charge_pump(struct snd_soc_dapm_widget *w, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: event = %d\n", __func__, event); @@ -1474,7 +1474,7 @@ static int msm_anlg_cdc_codec_enable_charge_pump(struct snd_soc_dapm_widget *w, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80); msm_anlg_cdc_boost_mode_sequence(codec, EAR_PMU); - } else if (get_codec_version(msmfalcon_cdc) >= DIANGU) { + } else if (get_codec_version(sdm660_cdc) >= DIANGU) { snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x80); @@ -1495,10 +1495,10 @@ static int msm_anlg_cdc_codec_enable_charge_pump(struct snd_soc_dapm_widget *w, snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00); - if (msmfalcon_cdc->boost_option != BOOST_ALWAYS) { + if (sdm660_cdc->boost_option != BOOST_ALWAYS) { dev_dbg(codec->dev, "%s: boost_option:%d, tear down ear\n", - __func__, msmfalcon_cdc->boost_option); + __func__, sdm660_cdc->boost_option); msm_anlg_cdc_boost_mode_sequence(codec, EAR_PMD); } @@ -1510,16 +1510,16 @@ static int msm_anlg_cdc_codec_enable_charge_pump(struct snd_soc_dapm_widget *w, snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x80, 0x00); } else { - if (get_codec_version(msmfalcon_cdc) < DIANGU) + if (get_codec_version(sdm660_cdc) < DIANGU) snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x00); - if (msmfalcon_cdc->rx_bias_count == 0) + if (sdm660_cdc->rx_bias_count == 0) snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00); dev_dbg(codec->dev, "%s: rx_bias_count = %d\n", - __func__, msmfalcon_cdc->rx_bias_count); + __func__, sdm660_cdc->rx_bias_count); } break; } @@ -1530,13 +1530,13 @@ static int msm_anlg_cdc_ear_pa_boost_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); ucontrol->value.integer.value[0] = - (msmfalcon_cdc->ear_pa_boost_set ? 1 : 0); - dev_dbg(codec->dev, "%s: msmfalcon_cdc->ear_pa_boost_set = %d\n", - __func__, msmfalcon_cdc->ear_pa_boost_set); + (sdm660_cdc->ear_pa_boost_set ? 1 : 0); + dev_dbg(codec->dev, "%s: sdm660_cdc->ear_pa_boost_set = %d\n", + __func__, sdm660_cdc->ear_pa_boost_set); return 0; } @@ -1544,12 +1544,12 @@ static int msm_anlg_cdc_ear_pa_boost_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", __func__, ucontrol->value.integer.value[0]); - msmfalcon_cdc->ear_pa_boost_set = + sdm660_cdc->ear_pa_boost_set = (ucontrol->value.integer.value[0] ? true : false); return 0; } @@ -1596,10 +1596,10 @@ static int msm_anlg_cdc_pa_gain_get(struct snd_kcontrol *kcontrol, { u8 ear_pa_gain; struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if (get_codec_version(msmfalcon_cdc) >= DIANGU) { + if (get_codec_version(sdm660_cdc) >= DIANGU) { ear_pa_gain = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC); ear_pa_gain = (ear_pa_gain >> 1) & 0x3; @@ -1643,13 +1643,13 @@ static int msm_anlg_cdc_pa_gain_put(struct snd_kcontrol *kcontrol, { u8 ear_pa_gain; struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", __func__, ucontrol->value.integer.value[0]); - if (get_codec_version(msmfalcon_cdc) >= DIANGU) { + if (get_codec_version(sdm660_cdc) >= DIANGU) { switch (ucontrol->value.integer.value[0]) { case 0: ear_pa_gain = 0x06; @@ -1691,20 +1691,20 @@ static int msm_anlg_cdc_hph_mode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if (msmfalcon_cdc->hph_mode == NORMAL_MODE) { + if (sdm660_cdc->hph_mode == NORMAL_MODE) { ucontrol->value.integer.value[0] = 0; - } else if (msmfalcon_cdc->hph_mode == HD2_MODE) { + } else if (sdm660_cdc->hph_mode == HD2_MODE) { ucontrol->value.integer.value[0] = 1; } else { dev_err(codec->dev, "%s: ERROR: Default HPH Mode= %d\n", - __func__, msmfalcon_cdc->hph_mode); + __func__, sdm660_cdc->hph_mode); } - dev_dbg(codec->dev, "%s: msmfalcon_cdc->hph_mode = %d\n", __func__, - msmfalcon_cdc->hph_mode); + dev_dbg(codec->dev, "%s: sdm660_cdc->hph_mode = %d\n", __func__, + sdm660_cdc->hph_mode); return 0; } @@ -1712,7 +1712,7 @@ static int msm_anlg_cdc_hph_mode_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", @@ -1720,18 +1720,18 @@ static int msm_anlg_cdc_hph_mode_set(struct snd_kcontrol *kcontrol, switch (ucontrol->value.integer.value[0]) { case 0: - msmfalcon_cdc->hph_mode = NORMAL_MODE; + sdm660_cdc->hph_mode = NORMAL_MODE; break; case 1: - if (get_codec_version(msmfalcon_cdc) >= DIANGU) - msmfalcon_cdc->hph_mode = HD2_MODE; + if (get_codec_version(sdm660_cdc) >= DIANGU) + sdm660_cdc->hph_mode = HD2_MODE; break; default: - msmfalcon_cdc->hph_mode = NORMAL_MODE; + sdm660_cdc->hph_mode = NORMAL_MODE; break; } - dev_dbg(codec->dev, "%s: msmfalcon_cdc->hph_mode_set = %d\n", - __func__, msmfalcon_cdc->hph_mode); + dev_dbg(codec->dev, "%s: sdm660_cdc->hph_mode_set = %d\n", + __func__, sdm660_cdc->hph_mode); return 0; } @@ -1739,25 +1739,25 @@ static int msm_anlg_cdc_boost_option_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if (msmfalcon_cdc->boost_option == BOOST_SWITCH) { + if (sdm660_cdc->boost_option == BOOST_SWITCH) { ucontrol->value.integer.value[0] = 0; - } else if (msmfalcon_cdc->boost_option == BOOST_ALWAYS) { + } else if (sdm660_cdc->boost_option == BOOST_ALWAYS) { ucontrol->value.integer.value[0] = 1; - } else if (msmfalcon_cdc->boost_option == BYPASS_ALWAYS) { + } else if (sdm660_cdc->boost_option == BYPASS_ALWAYS) { ucontrol->value.integer.value[0] = 2; - } else if (msmfalcon_cdc->boost_option == BOOST_ON_FOREVER) { + } else if (sdm660_cdc->boost_option == BOOST_ON_FOREVER) { ucontrol->value.integer.value[0] = 3; } else { dev_err(codec->dev, "%s: ERROR: Unsupported Boost option= %d\n", - __func__, msmfalcon_cdc->boost_option); + __func__, sdm660_cdc->boost_option); return -EINVAL; } - dev_dbg(codec->dev, "%s: msmfalcon_cdc->boost_option = %d\n", __func__, - msmfalcon_cdc->boost_option); + dev_dbg(codec->dev, "%s: sdm660_cdc->boost_option = %d\n", __func__, + sdm660_cdc->boost_option); return 0; } @@ -1765,7 +1765,7 @@ static int msm_anlg_cdc_boost_option_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", @@ -1773,26 +1773,26 @@ static int msm_anlg_cdc_boost_option_set(struct snd_kcontrol *kcontrol, switch (ucontrol->value.integer.value[0]) { case 0: - msmfalcon_cdc->boost_option = BOOST_SWITCH; + sdm660_cdc->boost_option = BOOST_SWITCH; break; case 1: - msmfalcon_cdc->boost_option = BOOST_ALWAYS; + sdm660_cdc->boost_option = BOOST_ALWAYS; break; case 2: - msmfalcon_cdc->boost_option = BYPASS_ALWAYS; + sdm660_cdc->boost_option = BYPASS_ALWAYS; msm_anlg_cdc_bypass_on(codec); break; case 3: - msmfalcon_cdc->boost_option = BOOST_ON_FOREVER; + sdm660_cdc->boost_option = BOOST_ON_FOREVER; msm_anlg_cdc_boost_on(codec); break; default: pr_err("%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); + sdm660_cdc->boost_option); return -EINVAL; } - dev_dbg(codec->dev, "%s: msmfalcon_cdc->boost_option_set = %d\n", - __func__, msmfalcon_cdc->boost_option); + dev_dbg(codec->dev, "%s: sdm660_cdc->boost_option_set = %d\n", + __func__, sdm660_cdc->boost_option); return 0; } @@ -1800,21 +1800,21 @@ static int msm_anlg_cdc_spk_boost_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if (msmfalcon_cdc->spk_boost_set == false) { + if (sdm660_cdc->spk_boost_set == false) { ucontrol->value.integer.value[0] = 0; - } else if (msmfalcon_cdc->spk_boost_set == true) { + } else if (sdm660_cdc->spk_boost_set == true) { ucontrol->value.integer.value[0] = 1; } else { dev_err(codec->dev, "%s: ERROR: Unsupported Speaker Boost = %d\n", - __func__, msmfalcon_cdc->spk_boost_set); + __func__, sdm660_cdc->spk_boost_set); return -EINVAL; } - dev_dbg(codec->dev, "%s: msmfalcon_cdc->spk_boost_set = %d\n", __func__, - msmfalcon_cdc->spk_boost_set); + dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n", __func__, + sdm660_cdc->spk_boost_set); return 0; } @@ -1822,7 +1822,7 @@ static int msm_anlg_cdc_spk_boost_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", @@ -1830,16 +1830,16 @@ static int msm_anlg_cdc_spk_boost_set(struct snd_kcontrol *kcontrol, switch (ucontrol->value.integer.value[0]) { case 0: - msmfalcon_cdc->spk_boost_set = false; + sdm660_cdc->spk_boost_set = false; break; case 1: - msmfalcon_cdc->spk_boost_set = true; + sdm660_cdc->spk_boost_set = true; break; default: return -EINVAL; } - dev_dbg(codec->dev, "%s: msmfalcon_cdc->spk_boost_set = %d\n", - __func__, msmfalcon_cdc->spk_boost_set); + dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n", + __func__, sdm660_cdc->spk_boost_set); return 0; } @@ -1847,16 +1847,16 @@ static int msm_anlg_cdc_ext_spk_boost_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if (msmfalcon_cdc->ext_spk_boost_set == false) + if (sdm660_cdc->ext_spk_boost_set == false) ucontrol->value.integer.value[0] = 0; else ucontrol->value.integer.value[0] = 1; - dev_dbg(codec->dev, "%s: msmfalcon_cdc->ext_spk_boost_set = %d\n", - __func__, msmfalcon_cdc->ext_spk_boost_set); + dev_dbg(codec->dev, "%s: sdm660_cdc->ext_spk_boost_set = %d\n", + __func__, sdm660_cdc->ext_spk_boost_set); return 0; } @@ -1864,7 +1864,7 @@ static int msm_anlg_cdc_ext_spk_boost_set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", @@ -1872,16 +1872,16 @@ static int msm_anlg_cdc_ext_spk_boost_set(struct snd_kcontrol *kcontrol, switch (ucontrol->value.integer.value[0]) { case 0: - msmfalcon_cdc->ext_spk_boost_set = false; + sdm660_cdc->ext_spk_boost_set = false; break; case 1: - msmfalcon_cdc->ext_spk_boost_set = true; + sdm660_cdc->ext_spk_boost_set = true; break; default: return -EINVAL; } - dev_dbg(codec->dev, "%s: msmfalcon_cdc->spk_boost_set = %d\n", - __func__, msmfalcon_cdc->spk_boost_set); + dev_dbg(codec->dev, "%s: sdm660_cdc->spk_boost_set = %d\n", + __func__, sdm660_cdc->spk_boost_set); return 0; } @@ -1975,7 +1975,7 @@ static int tombak_hph_impedance_get(struct snd_kcontrol *kcontrol, bool hphr; struct soc_multi_mixer_control *mc; struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *priv = snd_soc_codec_get_drvdata(codec); + struct sdm660_cdc_priv *priv = snd_soc_codec_get_drvdata(codec); mc = (struct soc_multi_mixer_control *)(kcontrol->private_value); @@ -2000,12 +2000,12 @@ static int tombak_get_hph_type(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct msmfalcon_cdc_priv *priv = snd_soc_codec_get_drvdata(codec); + struct sdm660_cdc_priv *priv = snd_soc_codec_get_drvdata(codec); struct wcd_mbhc *mbhc; if (!priv) { dev_err(codec->dev, - "%s: msmfalcon_cdc-wcd private data is NULL\n", + "%s: sdm660_cdc-wcd private data is NULL\n", __func__); return -EINVAL; } @@ -2129,7 +2129,7 @@ static const struct snd_kcontrol_new lo_mux[] = { static void msm_anlg_cdc_codec_enable_adc_block(struct snd_soc_codec *codec, int enable) { - struct msmfalcon_cdc_priv *wcd8x16 = snd_soc_codec_get_drvdata(codec); + struct sdm660_cdc_priv *wcd8x16 = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s %d\n", __func__, enable); @@ -2238,7 +2238,7 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name); @@ -2248,9 +2248,9 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w, MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10); snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x01); - switch (msmfalcon_cdc->boost_option) { + switch (sdm660_cdc->boost_option) { case BOOST_SWITCH: - if (!msmfalcon_cdc->spk_boost_set) + if (!sdm660_cdc->spk_boost_set) snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x10); @@ -2266,23 +2266,23 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w, default: dev_err(codec->dev, "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); + sdm660_cdc->boost_option); break; } /* Wait for 1ms after SPK_DAC CTL setting */ usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0xE0); - if (get_codec_version(msmfalcon_cdc) != TOMBAK_1_0) + if (get_codec_version(sdm660_cdc) != TOMBAK_1_0) snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x01, 0x01); break; case SND_SOC_DAPM_POST_PMU: /* Wait for 1ms after SPK_VBAT_LDO Enable */ usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); - switch (msmfalcon_cdc->boost_option) { + switch (sdm660_cdc->boost_option) { case BOOST_SWITCH: - if (msmfalcon_cdc->spk_boost_set) + if (sdm660_cdc->spk_boost_set) snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0xEF, 0xEF); @@ -2304,7 +2304,7 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w, default: dev_err(codec->dev, "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); + sdm660_cdc->boost_option); break; } msm_anlg_cdc_dig_notifier_call(codec, @@ -2320,12 +2320,12 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w, usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS); snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x10); - if (get_codec_version(msmfalcon_cdc) < CAJON_2_0) + if (get_codec_version(sdm660_cdc) < CAJON_2_0) msm_anlg_cdc_boost_mode_sequence(codec, SPK_PMD); snd_soc_update_bits(codec, w->reg, 0x80, 0x00); - switch (msmfalcon_cdc->boost_option) { + switch (sdm660_cdc->boost_option) { case BOOST_SWITCH: - if (msmfalcon_cdc->spk_boost_set) + if (sdm660_cdc->spk_boost_set) snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0xEF, 0x69); @@ -2341,7 +2341,7 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w, default: dev_err(codec->dev, "%s: invalid boost option: %d\n", __func__, - msmfalcon_cdc->boost_option); + sdm660_cdc->boost_option); break; } break; @@ -2354,12 +2354,12 @@ static int msm_anlg_cdc_codec_enable_spk_pa(struct snd_soc_dapm_widget *w, MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x00); snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x10, 0x00); - if (get_codec_version(msmfalcon_cdc) != TOMBAK_1_0) + if (get_codec_version(sdm660_cdc) != TOMBAK_1_0) snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x01, 0x00); snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00); - if (get_codec_version(msmfalcon_cdc) >= CAJON_2_0) + if (get_codec_version(sdm660_cdc) >= CAJON_2_0) msm_anlg_cdc_boost_mode_sequence(codec, SPK_PMD); break; } @@ -2371,7 +2371,7 @@ static int msm_anlg_cdc_codec_enable_dig_clk(struct snd_soc_dapm_widget *w, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); struct msm_asoc_mach_data *pdata = NULL; @@ -2385,7 +2385,7 @@ static int msm_anlg_cdc_codec_enable_dig_clk(struct snd_soc_dapm_widget *w, snd_soc_update_bits(codec, w->reg, 0x80, 0x80); break; case SND_SOC_DAPM_POST_PMD: - if (msmfalcon_cdc->rx_bias_count == 0) + if (sdm660_cdc->rx_bias_count == 0) snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x80, 0x00); @@ -2397,10 +2397,10 @@ static int msm_anlg_cdc_codec_enable_dig_clk(struct snd_soc_dapm_widget *w, static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if (get_codec_version(msmfalcon_cdc) < CAJON) + if (get_codec_version(sdm660_cdc) < CAJON) return true; else return false; @@ -2409,10 +2409,10 @@ static bool msm_anlg_cdc_use_mb(struct snd_soc_codec *codec) static void msm_anlg_cdc_set_auto_zeroing(struct snd_soc_codec *codec, bool enable) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if (get_codec_version(msmfalcon_cdc) < CONGA) { + if (get_codec_version(sdm660_cdc) < CONGA) { if (enable) /* * Set autozeroing for special headset detection and @@ -2435,10 +2435,10 @@ static void msm_anlg_cdc_set_auto_zeroing(struct snd_soc_codec *codec, static void msm_anlg_cdc_trim_btn_reg(struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - if (get_codec_version(msmfalcon_cdc) == TOMBAK_1_0) { + if (get_codec_version(sdm660_cdc) == TOMBAK_1_0) { pr_debug("%s: This device needs to be trimmed\n", __func__); /* * Calculate the trim value for each device used @@ -2498,7 +2498,7 @@ static int msm_anlg_cdc_codec_enable_micbias(struct snd_soc_dapm_widget *w, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); u16 micb_int_reg; char *internal1_text = "Internal1"; @@ -2525,7 +2525,7 @@ static int msm_anlg_cdc_codec_enable_micbias(struct snd_soc_dapm_widget *w, switch (event) { case SND_SOC_DAPM_PRE_PMU: if (strnstr(w->name, internal1_text, strlen(w->name))) { - if (get_codec_version(msmfalcon_cdc) >= CAJON) + if (get_codec_version(sdm660_cdc) >= CAJON) snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2, 0x02, 0x02); @@ -2554,7 +2554,7 @@ static int msm_anlg_cdc_codec_enable_micbias(struct snd_soc_dapm_widget *w, break; case SND_SOC_DAPM_POST_PMU: - if (get_codec_version(msmfalcon_cdc) <= TOMBAK_2_0) + if (get_codec_version(sdm660_cdc) <= TOMBAK_2_0) /* * Wait for 20ms post micbias enable * for version < tombak 2.0. @@ -2599,7 +2599,7 @@ static int msm_anlg_cdc_codec_enable_micbias(struct snd_soc_dapm_widget *w, static void update_clkdiv(void *handle, int val) { - struct msmfalcon_cdc *handle_cdc = handle; + struct sdm660_cdc *handle_cdc = handle; struct snd_soc_codec *codec = handle_cdc->codec; snd_soc_update_bits(codec, @@ -2609,24 +2609,24 @@ static void update_clkdiv(void *handle, int val) static int get_cdc_version(void *handle) { - struct msmfalcon_cdc *handle_cdc = handle; + struct sdm660_cdc *handle_cdc = handle; struct snd_soc_codec *codec = handle_cdc->codec; - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - return get_codec_version(msmfalcon_cdc); + return get_codec_version(sdm660_cdc); } -static int msmfalcon_wcd_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w, +static int sdm660_wcd_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); int ret = 0; - if (!msmfalcon_cdc->ext_spk_boost_set) { + if (!sdm660_cdc->ext_spk_boost_set) { dev_dbg(codec->dev, "%s: ext_boost not supported/disabled\n", __func__); return 0; @@ -2634,8 +2634,8 @@ static int msmfalcon_wcd_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w, dev_dbg(codec->dev, "%s: %s %d\n", __func__, w->name, event); switch (event) { case SND_SOC_DAPM_PRE_PMU: - if (msmfalcon_cdc->spkdrv_reg) { - ret = regulator_enable(msmfalcon_cdc->spkdrv_reg); + if (sdm660_cdc->spkdrv_reg) { + ret = regulator_enable(sdm660_cdc->spkdrv_reg); if (ret) dev_err(codec->dev, "%s Failed to enable spkdrv reg %s\n", @@ -2643,8 +2643,8 @@ static int msmfalcon_wcd_codec_enable_vdd_spkr(struct snd_soc_dapm_widget *w, } break; case SND_SOC_DAPM_POST_PMD: - if (msmfalcon_cdc->spkdrv_reg) { - ret = regulator_disable(msmfalcon_cdc->spkdrv_reg); + if (sdm660_cdc->spkdrv_reg) { + ret = regulator_disable(sdm660_cdc->spkdrv_reg); if (ret) dev_err(codec->dev, "%s: Failed to disable spkdrv_reg %s\n", @@ -2662,15 +2662,15 @@ static int msm_anlg_cdc_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s %d\n", __func__, event); switch (event) { case SND_SOC_DAPM_PRE_PMU: - msmfalcon_cdc->rx_bias_count++; - if (msmfalcon_cdc->rx_bias_count == 1) { + sdm660_cdc->rx_bias_count++; + if (sdm660_cdc->rx_bias_count == 1) { snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x80, 0x80); @@ -2680,8 +2680,8 @@ static int msm_anlg_cdc_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, } break; case SND_SOC_DAPM_POST_PMD: - msmfalcon_cdc->rx_bias_count--; - if (msmfalcon_cdc->rx_bias_count == 0) { + sdm660_cdc->rx_bias_count--; + if (sdm660_cdc->rx_bias_count == 0) { snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x01, 0x00); @@ -2692,7 +2692,7 @@ static int msm_anlg_cdc_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, break; } dev_dbg(codec->dev, "%s rx_bias_count = %d\n", - __func__, msmfalcon_cdc->rx_bias_count); + __func__, sdm660_cdc->rx_bias_count); return 0; } @@ -2716,7 +2716,7 @@ static void wcd_imped_config(struct snd_soc_codec *codec, { uint32_t value; int codec_version; - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); value = wcd_get_impedance_value(imped); @@ -2728,7 +2728,7 @@ static void wcd_imped_config(struct snd_soc_codec *codec, return; } - codec_version = get_codec_version(msmfalcon_cdc); + codec_version = get_codec_version(sdm660_cdc); if (set_gain) { switch (codec_version) { @@ -2789,22 +2789,22 @@ static int msm_anlg_cdc_hphl_dac_event(struct snd_soc_dapm_widget *w, { uint32_t impedl, impedr; struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); int ret; dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event); - ret = wcd_mbhc_get_impedance(&msmfalcon_cdc->mbhc, + ret = wcd_mbhc_get_impedance(&sdm660_cdc->mbhc, &impedl, &impedr); switch (event) { case SND_SOC_DAPM_PRE_PMU: - if (get_codec_version(msmfalcon_cdc) > CAJON) + if (get_codec_version(sdm660_cdc) > CAJON) snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x08, 0x08); - if (get_codec_version(msmfalcon_cdc) == CAJON || - get_codec_version(msmfalcon_cdc) == CAJON_2_0) { + if (get_codec_version(sdm660_cdc) == CAJON || + get_codec_version(sdm660_cdc) == CAJON_2_0) { snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x80, 0x80); @@ -2812,11 +2812,11 @@ static int msm_anlg_cdc_hphl_dac_event(struct snd_soc_dapm_widget *w, MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x80, 0x80); } - if (get_codec_version(msmfalcon_cdc) > CAJON) + if (get_codec_version(sdm660_cdc) > CAJON) snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x08, 0x00); - if (msmfalcon_cdc->hph_mode == HD2_MODE) + if (sdm660_cdc->hph_mode == HD2_MODE) msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_PRE_RX1_INT_ON); snd_soc_update_bits(codec, @@ -2841,7 +2841,7 @@ static int msm_anlg_cdc_hphl_dac_event(struct snd_soc_dapm_widget *w, MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00); snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00); - if (msmfalcon_cdc->hph_mode == HD2_MODE) + if (sdm660_cdc->hph_mode == HD2_MODE) msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_POST_RX1_INT_OFF); break; @@ -2905,14 +2905,14 @@ static int msm_anlg_cdc_hphr_dac_event(struct snd_soc_dapm_widget *w, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s %s %d\n", __func__, w->name, event); switch (event) { case SND_SOC_DAPM_PRE_PMU: - if (msmfalcon_cdc->hph_mode == HD2_MODE) + if (sdm660_cdc->hph_mode == HD2_MODE) msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_PRE_RX2_INT_ON); snd_soc_update_bits(codec, @@ -2931,7 +2931,7 @@ static int msm_anlg_cdc_hphr_dac_event(struct snd_soc_dapm_widget *w, MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00); snd_soc_update_bits(codec, MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x00); - if (msmfalcon_cdc->hph_mode == HD2_MODE) + if (sdm660_cdc->hph_mode == HD2_MODE) msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_POST_RX2_INT_OFF); break; @@ -2944,7 +2944,7 @@ static int msm_anlg_cdc_hph_pa_event(struct snd_soc_dapm_widget *w, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event); @@ -2997,7 +2997,7 @@ static int msm_anlg_cdc_hph_pa_event(struct snd_soc_dapm_widget *w, msm_anlg_cdc_notifier_call(codec, WCD_EVENT_PRE_HPHR_PA_OFF); } - if (get_codec_version(msmfalcon_cdc) >= CAJON) { + if (get_codec_version(sdm660_cdc) >= CAJON) { snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP, 0xF0, 0x30); @@ -3006,12 +3006,12 @@ static int msm_anlg_cdc_hph_pa_event(struct snd_soc_dapm_widget *w, case SND_SOC_DAPM_POST_PMD: if (w->shift == 5) { clear_bit(WCD_MBHC_HPHL_PA_OFF_ACK, - &msmfalcon_cdc->mbhc.hph_pa_dac_state); + &sdm660_cdc->mbhc.hph_pa_dac_state); msm_anlg_cdc_notifier_call(codec, WCD_EVENT_POST_HPHL_PA_OFF); } else if (w->shift == 4) { clear_bit(WCD_MBHC_HPHR_PA_OFF_ACK, - &msmfalcon_cdc->mbhc.hph_pa_dac_state); + &sdm660_cdc->mbhc.hph_pa_dac_state); msm_anlg_cdc_notifier_call(codec, WCD_EVENT_POST_HPHR_PA_OFF); } @@ -3106,7 +3106,7 @@ static const struct snd_soc_dapm_route audio_map[] = { static int msm_anlg_cdc_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(dai->codec); dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n", @@ -3116,7 +3116,7 @@ static int msm_anlg_cdc_startup(struct snd_pcm_substream *substream, * If status_mask is BUS_DOWN it means SSR is not complete. * So return error. */ - if (test_bit(BUS_DOWN, &msmfalcon_cdc->status_mask)) { + if (test_bit(BUS_DOWN, &sdm660_cdc->status_mask)) { dev_err(dai->codec->dev, "Error, Device is not up post SSR\n"); return -EINVAL; } @@ -3134,20 +3134,20 @@ static void msm_anlg_cdc_shutdown(struct snd_pcm_substream *substream, int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec, int mclk_enable, bool dapm) { - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: mclk_enable = %u, dapm = %d\n", __func__, mclk_enable, dapm); if (mclk_enable) { - msmfalcon_cdc->int_mclk0_enabled = true; + sdm660_cdc->int_mclk0_enabled = true; msm_anlg_cdc_codec_enable_clock_block(codec, 1); } else { - if (!msmfalcon_cdc->int_mclk0_enabled) { + if (!sdm660_cdc->int_mclk0_enabled) { dev_err(codec->dev, "Error, MCLK already diabled\n"); return -EINVAL; } - msmfalcon_cdc->int_mclk0_enabled = false; + sdm660_cdc->int_mclk0_enabled = false; msm_anlg_cdc_codec_enable_clock_block(codec, 0); } return 0; @@ -3199,8 +3199,8 @@ static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[] = { .id = AIF1_PB, .playback = { .stream_name = "Playback", - .rates = MSMFALCON_CDC_RATES, - .formats = MSMFALCON_CDC_FORMATS, + .rates = SDM660_CDC_RATES, + .formats = SDM660_CDC_FORMATS, .rate_max = 192000, .rate_min = 8000, .channels_min = 1, @@ -3213,8 +3213,8 @@ static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[] = { .id = AIF1_CAP, .capture = { .stream_name = "Record", - .rates = MSMFALCON_CDC_RATES, - .formats = MSMFALCON_CDC_FORMATS, + .rates = SDM660_CDC_RATES, + .formats = SDM660_CDC_FORMATS, .rate_max = 48000, .rate_min = 8000, .channels_min = 1, @@ -3227,8 +3227,8 @@ static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[] = { .id = AIF3_SVA, .capture = { .stream_name = "RecordSVA", - .rates = MSMFALCON_CDC_RATES, - .formats = MSMFALCON_CDC_FORMATS, + .rates = SDM660_CDC_RATES, + .formats = SDM660_CDC_FORMATS, .rate_max = 48000, .rate_min = 8000, .channels_min = 1, @@ -3241,8 +3241,8 @@ static struct snd_soc_dai_driver msm_anlg_cdc_i2s_dai[] = { .id = AIF2_VIFEED, .capture = { .stream_name = "VIfeed", - .rates = MSMFALCON_CDC_RATES, - .formats = MSMFALCON_CDC_FORMATS, + .rates = SDM660_CDC_RATES, + .formats = SDM660_CDC_FORMATS, .rate_max = 48000, .rate_min = 48000, .channels_min = 2, @@ -3279,7 +3279,7 @@ static int msm_anlg_cdc_codec_enable_spk_ext_pa(struct snd_soc_dapm_widget *w, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); dev_dbg(codec->dev, "%s: %s event = %d\n", __func__, w->name, event); @@ -3287,14 +3287,14 @@ static int msm_anlg_cdc_codec_enable_spk_ext_pa(struct snd_soc_dapm_widget *w, case SND_SOC_DAPM_POST_PMU: dev_dbg(codec->dev, "%s: enable external speaker PA\n", __func__); - if (msmfalcon_cdc->codec_spk_ext_pa_cb) - msmfalcon_cdc->codec_spk_ext_pa_cb(codec, 1); + if (sdm660_cdc->codec_spk_ext_pa_cb) + sdm660_cdc->codec_spk_ext_pa_cb(codec, 1); break; case SND_SOC_DAPM_PRE_PMD: dev_dbg(codec->dev, "%s: enable external speaker PA\n", __func__); - if (msmfalcon_cdc->codec_spk_ext_pa_cb) - msmfalcon_cdc->codec_spk_ext_pa_cb(codec, 0); + if (sdm660_cdc->codec_spk_ext_pa_cb) + sdm660_cdc->codec_spk_ext_pa_cb(codec, 0); break; } return 0; @@ -3305,7 +3305,7 @@ static int msm_anlg_cdc_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, int event) { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); switch (event) { @@ -3315,10 +3315,10 @@ static int msm_anlg_cdc_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, __func__); snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x80, 0x80); - if (get_codec_version(msmfalcon_cdc) < CONGA) + if (get_codec_version(sdm660_cdc) < CONGA) snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFF, 0x2A); - if (get_codec_version(msmfalcon_cdc) >= DIANGU) { + if (get_codec_version(sdm660_cdc) >= DIANGU) { snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x08, 0x00); snd_soc_update_bits(codec, @@ -3343,13 +3343,13 @@ static int msm_anlg_cdc_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, DIG_CDC_EVENT_RX1_MUTE_ON); /* Wait for 20ms for RX digital mute to take effect */ msleep(20); - if (msmfalcon_cdc->boost_option == BOOST_ALWAYS) { + if (sdm660_cdc->boost_option == BOOST_ALWAYS) { dev_dbg(codec->dev, "%s: boost_option:%d, tear down ear\n", - __func__, msmfalcon_cdc->boost_option); + __func__, sdm660_cdc->boost_option); msm_anlg_cdc_boost_mode_sequence(codec, EAR_PMD); } - if (get_codec_version(msmfalcon_cdc) >= DIANGU) { + if (get_codec_version(sdm660_cdc) >= DIANGU) { snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x04, 0x0); snd_soc_update_bits(codec, @@ -3364,10 +3364,10 @@ static int msm_anlg_cdc_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 0x40, 0x00); /* Wait for 7ms after EAR PA teardown */ usleep_range(7000, 7100); - if (get_codec_version(msmfalcon_cdc) < CONGA) + if (get_codec_version(sdm660_cdc) < CONGA) snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0xFF, 0x16); - if (get_codec_version(msmfalcon_cdc) >= DIANGU) + if (get_codec_version(sdm660_cdc) >= DIANGU) snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x08, 0x08); break; @@ -3452,7 +3452,7 @@ static const struct snd_soc_dapm_widget msm_anlg_cdc_dapm_widgets[] = { msm_anlg_cdc_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_SUPPLY("VDD_SPKDRV", SND_SOC_NOPM, 0, 0, - msmfalcon_wcd_codec_enable_vdd_spkr, + sdm660_wcd_codec_enable_vdd_spkr, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0), SND_SOC_DAPM_SUPPLY("MICBIAS_REGULATOR", SND_SOC_NOPM, @@ -3512,13 +3512,13 @@ static const struct snd_soc_dapm_widget msm_anlg_cdc_dapm_widgets[] = { SND_SOC_DAPM_OUTPUT("ADC3_OUT"), }; -static const struct msmfalcon_cdc_reg_mask_val msm_anlg_cdc_reg_defaults[] = { +static const struct sdm660_cdc_reg_mask_val msm_anlg_cdc_reg_defaults[] = { MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x03), MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x82), MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1), }; -static const struct msmfalcon_cdc_reg_mask_val +static const struct sdm660_cdc_reg_mask_val msm_anlg_cdc_reg_defaults_2_0[] = { MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), @@ -3536,7 +3536,7 @@ static const struct msmfalcon_cdc_reg_mask_val MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80), }; -static const struct msmfalcon_cdc_reg_mask_val conga_wcd_reg_defaults[] = { +static const struct sdm660_cdc_reg_mask_val conga_wcd_reg_defaults[] = { MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5), @@ -3551,7 +3551,7 @@ static const struct msmfalcon_cdc_reg_mask_val conga_wcd_reg_defaults[] = { MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80), }; -static const struct msmfalcon_cdc_reg_mask_val cajon_wcd_reg_defaults[] = { +static const struct sdm660_cdc_reg_mask_val cajon_wcd_reg_defaults[] = { MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5), @@ -3569,7 +3569,7 @@ static const struct msmfalcon_cdc_reg_mask_val cajon_wcd_reg_defaults[] = { MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x80), }; -static const struct msmfalcon_cdc_reg_mask_val cajon2p0_wcd_reg_defaults[] = { +static const struct sdm660_cdc_reg_mask_val cajon2p0_wcd_reg_defaults[] = { MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0xA5), MSM89XX_REG_VAL(MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x0F), MSM89XX_REG_VAL(MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0xA5), @@ -3592,10 +3592,10 @@ static const struct msmfalcon_cdc_reg_mask_val cajon2p0_wcd_reg_defaults[] = { static void msm_anlg_cdc_update_reg_defaults(struct snd_soc_codec *codec) { u32 i, version; - struct msmfalcon_cdc_priv *msmfalcon_cdc = + struct sdm660_cdc_priv *sdm660_cdc = snd_soc_codec_get_drvdata(codec); - version = get_codec_version(msmfalcon_cdc); + version = get_codec_version(sdm660_cdc); if (version == TOMBAK_1_0) { for (i = 0; i < ARRAY_SIZE(msm_anlg_cdc_reg_defaults); i++) snd_soc_write(codec, msm_anlg_cdc_reg_defaults[i].reg, @@ -3624,7 +3624,7 @@ static void msm_anlg_cdc_update_reg_defaults(struct snd_soc_codec *codec) } } -static const struct msmfalcon_cdc_reg_mask_val +static const struct sdm660_cdc_reg_mask_val msm_anlg_cdc_codec_reg_init_val[] = { /* Initialize current threshold to 350MA @@ -3679,18 +3679,18 @@ static int msm_anlg_cdc_bringup(struct snd_soc_codec *codec) } static struct regulator *msm_anlg_cdc_find_regulator( - const struct msmfalcon_cdc *msmfalcon_cdc, + const struct sdm660_cdc *sdm660_cdc, const char *name) { int i; - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { - if (msmfalcon_cdc->supplies[i].supply && - !strcmp(msmfalcon_cdc->supplies[i].supply, name)) - return msmfalcon_cdc->supplies[i].consumer; + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { + if (sdm660_cdc->supplies[i].supply && + !strcmp(sdm660_cdc->supplies[i].supply, name)) + return sdm660_cdc->supplies[i].consumer; } - dev_err(msmfalcon_cdc->dev, "Error: regulator not found:%s\n" + dev_err(sdm660_cdc->dev, "Error: regulator not found:%s\n" , name); return NULL; } @@ -3698,7 +3698,7 @@ static struct regulator *msm_anlg_cdc_find_regulator( static int msm_anlg_cdc_device_down(struct snd_soc_codec *codec) { struct msm_asoc_mach_data *pdata = NULL; - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = + struct sdm660_cdc_priv *sdm660_cdc_priv = snd_soc_codec_get_drvdata(codec); unsigned int tx_1_en; unsigned int tx_2_en; @@ -3714,7 +3714,7 @@ static int msm_anlg_cdc_device_down(struct snd_soc_codec *codec) MSM89XX_PMIC_ANALOG_TX_1_EN, tx_1_en); snd_soc_write(codec, MSM89XX_PMIC_ANALOG_TX_2_EN, tx_2_en); - if (msmfalcon_cdc_priv->boost_option == BOOST_ON_FOREVER) { + if (sdm660_cdc_priv->boost_option == BOOST_ON_FOREVER) { if ((snd_soc_read(codec, MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL) & 0x80) == 0) { msm_anlg_cdc_dig_notifier_call(codec, @@ -3752,7 +3752,7 @@ static int msm_anlg_cdc_device_down(struct snd_soc_codec *codec) } } msm_anlg_cdc_boost_off(codec); - msmfalcon_cdc_priv->hph_mode = NORMAL_MODE; + sdm660_cdc_priv->hph_mode = NORMAL_MODE; /* 40ms to allow boost to discharge */ msleep(40); @@ -3773,21 +3773,21 @@ static int msm_anlg_cdc_device_down(struct snd_soc_codec *codec) msm_anlg_cdc_bringup(codec); atomic_set(&pdata->int_mclk0_enabled, false); msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_SSR_DOWN); - set_bit(BUS_DOWN, &msmfalcon_cdc_priv->status_mask); + set_bit(BUS_DOWN, &sdm660_cdc_priv->status_mask); snd_soc_card_change_online_state(codec->component.card, 0); return 0; } static int msm_anlg_cdc_device_up(struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = + struct sdm660_cdc_priv *sdm660_cdc_priv = snd_soc_codec_get_drvdata(codec); int ret = 0; dev_dbg(codec->dev, "%s: device up!\n", __func__); msm_anlg_cdc_dig_notifier_call(codec, DIG_CDC_EVENT_SSR_UP); - clear_bit(BUS_DOWN, &msmfalcon_cdc_priv->status_mask); + clear_bit(BUS_DOWN, &sdm660_cdc_priv->status_mask); snd_soc_card_change_online_state(codec->component.card, 1); /* delay is required to make sure sound card state updated */ usleep_range(5000, 5100); @@ -3807,38 +3807,38 @@ static int msm_anlg_cdc_device_up(struct snd_soc_codec *codec) msm_anlg_cdc_set_boost_v(codec); msm_anlg_cdc_set_micb_v(codec); - if (msmfalcon_cdc_priv->boost_option == BOOST_ON_FOREVER) + if (sdm660_cdc_priv->boost_option == BOOST_ON_FOREVER) msm_anlg_cdc_boost_on(codec); - else if (msmfalcon_cdc_priv->boost_option == BYPASS_ALWAYS) + else if (sdm660_cdc_priv->boost_option == BYPASS_ALWAYS) msm_anlg_cdc_bypass_on(codec); msm_anlg_cdc_configure_cap(codec, false, false); - wcd_mbhc_stop(&msmfalcon_cdc_priv->mbhc); - wcd_mbhc_deinit(&msmfalcon_cdc_priv->mbhc); - ret = wcd_mbhc_init(&msmfalcon_cdc_priv->mbhc, codec, &mbhc_cb, + wcd_mbhc_stop(&sdm660_cdc_priv->mbhc); + wcd_mbhc_deinit(&sdm660_cdc_priv->mbhc); + ret = wcd_mbhc_init(&sdm660_cdc_priv->mbhc, codec, &mbhc_cb, &intr_ids, wcd_mbhc_registers, true); if (ret) dev_err(codec->dev, "%s: mbhc initialization failed\n", __func__); else - wcd_mbhc_start(&msmfalcon_cdc_priv->mbhc, - msmfalcon_cdc_priv->mbhc.mbhc_cfg); + wcd_mbhc_start(&sdm660_cdc_priv->mbhc, + sdm660_cdc_priv->mbhc.mbhc_cfg); return 0; } -static int msmfalcon_cdc_notifier_service_cb(struct notifier_block *nb, +static int sdm660_cdc_notifier_service_cb(struct notifier_block *nb, unsigned long opcode, void *ptr) { struct snd_soc_codec *codec; - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = - container_of(nb, struct msmfalcon_cdc_priv, + struct sdm660_cdc_priv *sdm660_cdc_priv = + container_of(nb, struct sdm660_cdc_priv, audio_ssr_nb); bool adsp_ready = false; bool timedout; unsigned long timeout; - codec = msmfalcon_cdc_priv->codec; + codec = sdm660_cdc_priv->codec; dev_dbg(codec->dev, "%s: Service opcode 0x%lx\n", __func__, opcode); switch (opcode) { @@ -3888,19 +3888,19 @@ powerup: int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec, struct wcd_mbhc_config *mbhc_cfg) { - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = + struct sdm660_cdc_priv *sdm660_cdc_priv = snd_soc_codec_get_drvdata(codec); - return wcd_mbhc_start(&msmfalcon_cdc_priv->mbhc, mbhc_cfg); + return wcd_mbhc_start(&sdm660_cdc_priv->mbhc, mbhc_cfg); } EXPORT_SYMBOL(msm_anlg_cdc_hs_detect); void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = + struct sdm660_cdc_priv *sdm660_cdc_priv = snd_soc_codec_get_drvdata(codec); - wcd_mbhc_stop(&msmfalcon_cdc_priv->mbhc); + wcd_mbhc_stop(&sdm660_cdc_priv->mbhc); } EXPORT_SYMBOL(msm_anlg_cdc_hs_detect_exit); @@ -3914,8 +3914,8 @@ EXPORT_SYMBOL(msm_anlg_cdc_update_int_spk_boost); static void msm_anlg_cdc_set_micb_v(struct snd_soc_codec *codec) { - struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data; - struct msmfalcon_cdc_pdata *pdata = msmfalcon_cdc->dev->platform_data; + struct sdm660_cdc *sdm660_cdc = codec->control_data; + struct sdm660_cdc_pdata *pdata = sdm660_cdc->dev->platform_data; u8 reg_val; reg_val = VOLTAGE_CONVERTER(pdata->micbias.cfilt1_mv, MICBIAS_MIN_VAL, @@ -3928,11 +3928,11 @@ static void msm_anlg_cdc_set_micb_v(struct snd_soc_codec *codec) static void msm_anlg_cdc_set_boost_v(struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = + struct sdm660_cdc_priv *sdm660_cdc_priv = snd_soc_codec_get_drvdata(codec); snd_soc_update_bits(codec, MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE, - 0x1F, msmfalcon_cdc_priv->boost_voltage); + 0x1F, sdm660_cdc_priv->boost_voltage); } static void msm_anlg_cdc_configure_cap(struct snd_soc_codec *codec, @@ -3975,17 +3975,17 @@ static ssize_t msm_anlg_codec_version_read(struct snd_info_entry *entry, char __user *buf, size_t count, loff_t pos) { - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv; + struct sdm660_cdc_priv *sdm660_cdc_priv; char buffer[MSM_ANLG_CDC_VERSION_ENTRY_SIZE]; int len = 0; - msmfalcon_cdc_priv = (struct msmfalcon_cdc_priv *) entry->private_data; - if (!msmfalcon_cdc_priv) { - pr_err("%s: msmfalcon_cdc_priv is null\n", __func__); + sdm660_cdc_priv = (struct sdm660_cdc_priv *) entry->private_data; + if (!sdm660_cdc_priv) { + pr_err("%s: sdm660_cdc_priv is null\n", __func__); return -EINVAL; } - switch (get_codec_version(msmfalcon_cdc_priv)) { + switch (get_codec_version(sdm660_cdc_priv)) { case DRAX_CDC: len = snprintf(buffer, sizeof(buffer), "DRAX_CDC_1_0\n"); break; @@ -4014,18 +4014,18 @@ int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root, struct snd_soc_codec *codec) { struct snd_info_entry *version_entry; - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv; + struct sdm660_cdc_priv *sdm660_cdc_priv; struct snd_soc_card *card; if (!codec_root || !codec) return -EINVAL; - msmfalcon_cdc_priv = snd_soc_codec_get_drvdata(codec); + sdm660_cdc_priv = snd_soc_codec_get_drvdata(codec); card = codec->component.card; - msmfalcon_cdc_priv->entry = snd_register_module_info(codec_root->module, + sdm660_cdc_priv->entry = snd_register_module_info(codec_root->module, "pmic_analog", codec_root); - if (!msmfalcon_cdc_priv->entry) { + if (!sdm660_cdc_priv->entry) { dev_dbg(codec->dev, "%s: failed to create pmic_analog entry\n", __func__); return -ENOMEM; @@ -4033,14 +4033,14 @@ int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root, version_entry = snd_info_create_card_entry(card->snd_card, "version", - msmfalcon_cdc_priv->entry); + sdm660_cdc_priv->entry); if (!version_entry) { dev_dbg(codec->dev, "%s: failed to create pmic_analog version entry\n", __func__); return -ENOMEM; } - version_entry->private_data = msmfalcon_cdc_priv; + version_entry->private_data = sdm660_cdc_priv; version_entry->size = MSM_ANLG_CDC_VERSION_ENTRY_SIZE; version_entry->content = SNDRV_INFO_CONTENT_DATA; version_entry->c.ops = &msm_anlg_codec_info_ops; @@ -4049,70 +4049,70 @@ int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root, snd_info_free_entry(version_entry); return -ENOMEM; } - msmfalcon_cdc_priv->version_entry = version_entry; + sdm660_cdc_priv->version_entry = version_entry; return 0; } EXPORT_SYMBOL(msm_anlg_codec_info_create_codec_entry); static int msm_anlg_cdc_soc_probe(struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv; - struct msmfalcon_cdc *handle_cdc; + struct sdm660_cdc_priv *sdm660_cdc_priv; + struct sdm660_cdc *handle_cdc; int ret; - msmfalcon_cdc_priv = devm_kzalloc(codec->dev, - sizeof(struct msmfalcon_cdc_priv), + sdm660_cdc_priv = devm_kzalloc(codec->dev, + sizeof(struct sdm660_cdc_priv), GFP_KERNEL); - if (!msmfalcon_cdc_priv) + if (!sdm660_cdc_priv) return -ENOMEM; codec->control_data = dev_get_drvdata(codec->dev); - snd_soc_codec_set_drvdata(codec, msmfalcon_cdc_priv); - msmfalcon_cdc_priv->codec = codec; + snd_soc_codec_set_drvdata(codec, sdm660_cdc_priv); + sdm660_cdc_priv->codec = codec; handle_cdc = codec->control_data; handle_cdc->codec = codec; /* codec resmgr module init */ - msmfalcon_cdc_priv->spkdrv_reg = + sdm660_cdc_priv->spkdrv_reg = msm_anlg_cdc_find_regulator(codec->control_data, MSM89XX_VDD_SPKDRV_NAME); - msmfalcon_cdc_priv->pmic_rev = + sdm660_cdc_priv->pmic_rev = snd_soc_read(codec, MSM89XX_PMIC_DIGITAL_REVISION1); - msmfalcon_cdc_priv->codec_version = + sdm660_cdc_priv->codec_version = snd_soc_read(codec, MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE); - msmfalcon_cdc_priv->analog_major_rev = + sdm660_cdc_priv->analog_major_rev = snd_soc_read(codec, MSM89XX_PMIC_ANALOG_REVISION4); - if (msmfalcon_cdc_priv->codec_version == CONGA) { + if (sdm660_cdc_priv->codec_version == CONGA) { dev_dbg(codec->dev, "%s :Conga REV: %d\n", __func__, - msmfalcon_cdc_priv->codec_version); - msmfalcon_cdc_priv->ext_spk_boost_set = true; + sdm660_cdc_priv->codec_version); + sdm660_cdc_priv->ext_spk_boost_set = true; } else { dev_dbg(codec->dev, "%s :PMIC REV: %d\n", __func__, - msmfalcon_cdc_priv->pmic_rev); - if (msmfalcon_cdc_priv->pmic_rev == TOMBAK_1_0 && - msmfalcon_cdc_priv->codec_version == CAJON_2_0) { - if (msmfalcon_cdc_priv->analog_major_rev == 0x02) { - msmfalcon_cdc_priv->codec_version = DRAX_CDC; + sdm660_cdc_priv->pmic_rev); + if (sdm660_cdc_priv->pmic_rev == TOMBAK_1_0 && + sdm660_cdc_priv->codec_version == CAJON_2_0) { + if (sdm660_cdc_priv->analog_major_rev == 0x02) { + sdm660_cdc_priv->codec_version = DRAX_CDC; dev_dbg(codec->dev, "%s : Drax codec detected\n", __func__); } else { - msmfalcon_cdc_priv->codec_version = DIANGU; + sdm660_cdc_priv->codec_version = DIANGU; dev_dbg(codec->dev, "%s : Diangu detected\n", __func__); } - } else if (msmfalcon_cdc_priv->pmic_rev == TOMBAK_1_0 && + } else if (sdm660_cdc_priv->pmic_rev == TOMBAK_1_0 && (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_NCP_FBCTRL) & 0x80)) { - msmfalcon_cdc_priv->codec_version = CAJON; + sdm660_cdc_priv->codec_version = CAJON; dev_dbg(codec->dev, "%s : Cajon detected\n", __func__); - } else if (msmfalcon_cdc_priv->pmic_rev == TOMBAK_2_0 && + } else if (sdm660_cdc_priv->pmic_rev == TOMBAK_2_0 && (snd_soc_read(codec, MSM89XX_PMIC_ANALOG_NCP_FBCTRL) & 0x80)) { - msmfalcon_cdc_priv->codec_version = CAJON_2_0; + sdm660_cdc_priv->codec_version = CAJON_2_0; dev_dbg(codec->dev, "%s : Cajon 2.0 detected\n", __func__); } @@ -4121,8 +4121,8 @@ static int msm_anlg_cdc_soc_probe(struct snd_soc_codec *codec) * set to default boost option BOOST_SWITCH, user mixer path can change * it to BOOST_ALWAYS or BOOST_BYPASS based on solution chosen. */ - msmfalcon_cdc_priv->boost_option = BOOST_SWITCH; - msmfalcon_cdc_priv->hph_mode = NORMAL_MODE; + sdm660_cdc_priv->boost_option = BOOST_SWITCH; + sdm660_cdc_priv->hph_mode = NORMAL_MODE; msm_anlg_cdc_dt_parse_boost_info(codec); msm_anlg_cdc_set_boost_v(codec); @@ -4139,52 +4139,52 @@ static int msm_anlg_cdc_soc_probe(struct snd_soc_codec *codec) wcd9xxx_spmi_set_codec(codec); - msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply = + sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply = msm_anlg_cdc_find_regulator( codec->control_data, on_demand_supply_name[ON_DEMAND_MICBIAS]); - atomic_set(&msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref, + atomic_set(&sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref, 0); - BLOCKING_INIT_NOTIFIER_HEAD(&msmfalcon_cdc_priv->notifier); + BLOCKING_INIT_NOTIFIER_HEAD(&sdm660_cdc_priv->notifier); - msmfalcon_cdc_priv->fw_data = devm_kzalloc(codec->dev, - sizeof(*(msmfalcon_cdc_priv->fw_data)), + sdm660_cdc_priv->fw_data = devm_kzalloc(codec->dev, + sizeof(*(sdm660_cdc_priv->fw_data)), GFP_KERNEL); - if (!msmfalcon_cdc_priv->fw_data) + if (!sdm660_cdc_priv->fw_data) return -ENOMEM; - set_bit(WCD9XXX_MBHC_CAL, msmfalcon_cdc_priv->fw_data->cal_bit); - ret = wcd_cal_create_hwdep(msmfalcon_cdc_priv->fw_data, + set_bit(WCD9XXX_MBHC_CAL, sdm660_cdc_priv->fw_data->cal_bit); + ret = wcd_cal_create_hwdep(sdm660_cdc_priv->fw_data, WCD9XXX_CODEC_HWDEP_NODE, codec); if (ret < 0) { dev_err(codec->dev, "%s hwdep failed %d\n", __func__, ret); return ret; } - wcd_mbhc_init(&msmfalcon_cdc_priv->mbhc, codec, &mbhc_cb, &intr_ids, + wcd_mbhc_init(&sdm660_cdc_priv->mbhc, codec, &mbhc_cb, &intr_ids, wcd_mbhc_registers, true); - msmfalcon_cdc_priv->int_mclk0_enabled = false; + sdm660_cdc_priv->int_mclk0_enabled = false; /*Update speaker boost configuration*/ - msmfalcon_cdc_priv->spk_boost_set = spkr_boost_en; + sdm660_cdc_priv->spk_boost_set = spkr_boost_en; pr_debug("%s: speaker boost configured = %d\n", - __func__, msmfalcon_cdc_priv->spk_boost_set); + __func__, sdm660_cdc_priv->spk_boost_set); /* Set initial MICBIAS voltage level */ msm_anlg_cdc_set_micb_v(codec); /* Set initial cap mode */ msm_anlg_cdc_configure_cap(codec, false, false); - msmfalcon_cdc_priv->audio_ssr_nb.notifier_call = - msmfalcon_cdc_notifier_service_cb; + sdm660_cdc_priv->audio_ssr_nb.notifier_call = + sdm660_cdc_notifier_service_cb; ret = audio_notifier_register("pmic_analog_cdc", AUDIO_NOTIFIER_ADSP_DOMAIN, - &msmfalcon_cdc_priv->audio_ssr_nb); + &sdm660_cdc_priv->audio_ssr_nb); if (ret < 0) { pr_err("%s: Audio notifier register failed ret = %d\n", __func__, ret); - wcd_mbhc_deinit(&msmfalcon_cdc_priv->mbhc); + wcd_mbhc_deinit(&sdm660_cdc_priv->mbhc); return ret; } return 0; @@ -4192,69 +4192,69 @@ static int msm_anlg_cdc_soc_probe(struct snd_soc_codec *codec) static int msm_anlg_cdc_soc_remove(struct snd_soc_codec *codec) { - struct msmfalcon_cdc_priv *msmfalcon_cdc_priv = + struct sdm660_cdc_priv *sdm660_cdc_priv = snd_soc_codec_get_drvdata(codec); - msmfalcon_cdc_priv->spkdrv_reg = NULL; - msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply = NULL; - atomic_set(&msmfalcon_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref, + sdm660_cdc_priv->spkdrv_reg = NULL; + sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].supply = NULL; + atomic_set(&sdm660_cdc_priv->on_demand_list[ON_DEMAND_MICBIAS].ref, 0); - wcd_mbhc_deinit(&msmfalcon_cdc_priv->mbhc); + wcd_mbhc_deinit(&sdm660_cdc_priv->mbhc); return 0; } static int msm_anlg_cdc_enable_static_supplies_to_optimum( - struct msmfalcon_cdc *msmfalcon_cdc, - struct msmfalcon_cdc_pdata *pdata) + struct sdm660_cdc *sdm660_cdc, + struct sdm660_cdc_pdata *pdata) { int i; int ret = 0; - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { if (pdata->regulator[i].ondemand) continue; if (regulator_count_voltages( - msmfalcon_cdc->supplies[i].consumer) <= 0) + sdm660_cdc->supplies[i].consumer) <= 0) continue; ret = regulator_set_voltage( - msmfalcon_cdc->supplies[i].consumer, + sdm660_cdc->supplies[i].consumer, pdata->regulator[i].min_uv, pdata->regulator[i].max_uv); if (ret) { - dev_err(msmfalcon_cdc->dev, + dev_err(sdm660_cdc->dev, "Setting volt failed for regulator %s err %d\n", - msmfalcon_cdc->supplies[i].supply, ret); + sdm660_cdc->supplies[i].supply, ret); } - ret = regulator_set_load(msmfalcon_cdc->supplies[i].consumer, + ret = regulator_set_load(sdm660_cdc->supplies[i].consumer, pdata->regulator[i].optimum_ua); - dev_dbg(msmfalcon_cdc->dev, "Regulator %s set optimum mode\n", - msmfalcon_cdc->supplies[i].supply); + dev_dbg(sdm660_cdc->dev, "Regulator %s set optimum mode\n", + sdm660_cdc->supplies[i].supply); } return ret; } static int msm_anlg_cdc_disable_static_supplies_to_optimum( - struct msmfalcon_cdc *msmfalcon_cdc, - struct msmfalcon_cdc_pdata *pdata) + struct sdm660_cdc *sdm660_cdc, + struct sdm660_cdc_pdata *pdata) { int i; int ret = 0; - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { if (pdata->regulator[i].ondemand) continue; if (regulator_count_voltages( - msmfalcon_cdc->supplies[i].consumer) <= 0) + sdm660_cdc->supplies[i].consumer) <= 0) continue; - regulator_set_voltage(msmfalcon_cdc->supplies[i].consumer, 0, + regulator_set_voltage(sdm660_cdc->supplies[i].consumer, 0, pdata->regulator[i].max_uv); - regulator_set_load(msmfalcon_cdc->supplies[i].consumer, 0); - dev_dbg(msmfalcon_cdc->dev, "Regulator %s set optimum mode\n", - msmfalcon_cdc->supplies[i].supply); + regulator_set_load(sdm660_cdc->supplies[i].consumer, 0); + dev_dbg(sdm660_cdc->dev, "Regulator %s set optimum mode\n", + sdm660_cdc->supplies[i].supply); } return ret; @@ -4263,9 +4263,9 @@ static int msm_anlg_cdc_disable_static_supplies_to_optimum( static int msm_anlg_cdc_suspend(struct snd_soc_codec *codec) { struct msm_asoc_mach_data *pdata = NULL; - struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data; - struct msmfalcon_cdc_pdata *msmfalcon_cdc_pdata = - msmfalcon_cdc->dev->platform_data; + struct sdm660_cdc *sdm660_cdc = codec->control_data; + struct sdm660_cdc_pdata *sdm660_cdc_pdata = + sdm660_cdc->dev->platform_data; pdata = snd_soc_card_get_drvdata(codec->component.card); pr_debug("%s: mclk cnt = %d, mclk_enabled = %d\n", @@ -4280,21 +4280,21 @@ static int msm_anlg_cdc_suspend(struct snd_soc_codec *codec) atomic_set(&pdata->int_mclk0_enabled, false); mutex_unlock(&pdata->cdc_int_mclk0_mutex); } - msm_anlg_cdc_disable_static_supplies_to_optimum(msmfalcon_cdc, - msmfalcon_cdc_pdata); + msm_anlg_cdc_disable_static_supplies_to_optimum(sdm660_cdc, + sdm660_cdc_pdata); return 0; } static int msm_anlg_cdc_resume(struct snd_soc_codec *codec) { struct msm_asoc_mach_data *pdata = NULL; - struct msmfalcon_cdc *msmfalcon_cdc = codec->control_data; - struct msmfalcon_cdc_pdata *msmfalcon_cdc_pdata = - msmfalcon_cdc->dev->platform_data; + struct sdm660_cdc *sdm660_cdc = codec->control_data; + struct sdm660_cdc_pdata *sdm660_cdc_pdata = + sdm660_cdc->dev->platform_data; pdata = snd_soc_card_get_drvdata(codec->component.card); - msm_anlg_cdc_enable_static_supplies_to_optimum(msmfalcon_cdc, - msmfalcon_cdc_pdata); + msm_anlg_cdc_enable_static_supplies_to_optimum(sdm660_cdc, + sdm660_cdc_pdata); return 0; } @@ -4303,7 +4303,7 @@ static struct regmap *msm_anlg_get_regmap(struct device *dev) return dev_get_regmap(dev->parent, NULL); } -static struct snd_soc_codec_driver soc_codec_dev_msmfalcon_cdc = { +static struct snd_soc_codec_driver soc_codec_dev_sdm660_cdc = { .probe = msm_anlg_cdc_soc_probe, .remove = msm_anlg_cdc_soc_remove, .suspend = msm_anlg_cdc_suspend, @@ -4318,24 +4318,24 @@ static struct snd_soc_codec_driver soc_codec_dev_msmfalcon_cdc = { .get_regmap = msm_anlg_get_regmap, }; -static int msm_anlg_cdc_init_supplies(struct msmfalcon_cdc *msmfalcon_cdc, - struct msmfalcon_cdc_pdata *pdata) +static int msm_anlg_cdc_init_supplies(struct sdm660_cdc *sdm660_cdc, + struct sdm660_cdc_pdata *pdata) { int ret; int i; - msmfalcon_cdc->supplies = devm_kzalloc(msmfalcon_cdc->dev, + sdm660_cdc->supplies = devm_kzalloc(sdm660_cdc->dev, sizeof(struct regulator_bulk_data) * ARRAY_SIZE(pdata->regulator), GFP_KERNEL); - if (!msmfalcon_cdc->supplies) { + if (!sdm660_cdc->supplies) { ret = -ENOMEM; goto err; } - msmfalcon_cdc->num_of_supplies = 0; + sdm660_cdc->num_of_supplies = 0; if (ARRAY_SIZE(pdata->regulator) > MAX_REGULATOR) { - dev_err(msmfalcon_cdc->dev, "%s: Array Size out of bound\n", + dev_err(sdm660_cdc->dev, "%s: Array Size out of bound\n", __func__); ret = -EINVAL; goto err; @@ -4343,41 +4343,41 @@ static int msm_anlg_cdc_init_supplies(struct msmfalcon_cdc *msmfalcon_cdc, for (i = 0; i < ARRAY_SIZE(pdata->regulator); i++) { if (pdata->regulator[i].name) { - msmfalcon_cdc->supplies[i].supply = + sdm660_cdc->supplies[i].supply = pdata->regulator[i].name; - msmfalcon_cdc->num_of_supplies++; + sdm660_cdc->num_of_supplies++; } } - ret = devm_regulator_bulk_get(msmfalcon_cdc->dev, - msmfalcon_cdc->num_of_supplies, - msmfalcon_cdc->supplies); + ret = devm_regulator_bulk_get(sdm660_cdc->dev, + sdm660_cdc->num_of_supplies, + sdm660_cdc->supplies); if (ret != 0) { - dev_err(msmfalcon_cdc->dev, + dev_err(sdm660_cdc->dev, "Failed to get supplies: err = %d\n", ret); goto err_supplies; } - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { if (regulator_count_voltages( - msmfalcon_cdc->supplies[i].consumer) <= 0) + sdm660_cdc->supplies[i].consumer) <= 0) continue; - ret = regulator_set_voltage(msmfalcon_cdc->supplies[i].consumer, + ret = regulator_set_voltage(sdm660_cdc->supplies[i].consumer, pdata->regulator[i].min_uv, pdata->regulator[i].max_uv); if (ret) { - dev_err(msmfalcon_cdc->dev, + dev_err(sdm660_cdc->dev, "Setting regulator voltage failed for regulator %s err = %d\n", - msmfalcon_cdc->supplies[i].supply, ret); + sdm660_cdc->supplies[i].supply, ret); goto err_supplies; } - ret = regulator_set_load(msmfalcon_cdc->supplies[i].consumer, + ret = regulator_set_load(sdm660_cdc->supplies[i].consumer, pdata->regulator[i].optimum_ua); if (ret < 0) { - dev_err(msmfalcon_cdc->dev, + dev_err(sdm660_cdc->dev, "Setting regulator optimum mode failed for regulator %s err = %d\n", - msmfalcon_cdc->supplies[i].supply, ret); + sdm660_cdc->supplies[i].supply, ret); goto err_supplies; } else { ret = 0; @@ -4387,65 +4387,65 @@ static int msm_anlg_cdc_init_supplies(struct msmfalcon_cdc *msmfalcon_cdc, return ret; err_supplies: - kfree(msmfalcon_cdc->supplies); + kfree(sdm660_cdc->supplies); err: return ret; } static int msm_anlg_cdc_enable_static_supplies( - struct msmfalcon_cdc *msmfalcon_cdc, - struct msmfalcon_cdc_pdata *pdata) + struct sdm660_cdc *sdm660_cdc, + struct sdm660_cdc_pdata *pdata) { int i; int ret = 0; - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { if (pdata->regulator[i].ondemand) continue; - ret = regulator_enable(msmfalcon_cdc->supplies[i].consumer); + ret = regulator_enable(sdm660_cdc->supplies[i].consumer); if (ret) { - dev_err(msmfalcon_cdc->dev, "Failed to enable %s\n", - msmfalcon_cdc->supplies[i].supply); + dev_err(sdm660_cdc->dev, "Failed to enable %s\n", + sdm660_cdc->supplies[i].supply); break; } - dev_dbg(msmfalcon_cdc->dev, "Enabled regulator %s\n", - msmfalcon_cdc->supplies[i].supply); + dev_dbg(sdm660_cdc->dev, "Enabled regulator %s\n", + sdm660_cdc->supplies[i].supply); } while (ret && --i) if (!pdata->regulator[i].ondemand) - regulator_disable(msmfalcon_cdc->supplies[i].consumer); + regulator_disable(sdm660_cdc->supplies[i].consumer); return ret; } -static void msm_anlg_cdc_disable_supplies(struct msmfalcon_cdc *msmfalcon_cdc, - struct msmfalcon_cdc_pdata *pdata) +static void msm_anlg_cdc_disable_supplies(struct sdm660_cdc *sdm660_cdc, + struct sdm660_cdc_pdata *pdata) { int i; - regulator_bulk_disable(msmfalcon_cdc->num_of_supplies, - msmfalcon_cdc->supplies); - for (i = 0; i < msmfalcon_cdc->num_of_supplies; i++) { + regulator_bulk_disable(sdm660_cdc->num_of_supplies, + sdm660_cdc->supplies); + for (i = 0; i < sdm660_cdc->num_of_supplies; i++) { if (regulator_count_voltages( - msmfalcon_cdc->supplies[i].consumer) <= 0) + sdm660_cdc->supplies[i].consumer) <= 0) continue; - regulator_set_voltage(msmfalcon_cdc->supplies[i].consumer, 0, + regulator_set_voltage(sdm660_cdc->supplies[i].consumer, 0, pdata->regulator[i].max_uv); - regulator_set_load(msmfalcon_cdc->supplies[i].consumer, 0); + regulator_set_load(sdm660_cdc->supplies[i].consumer, 0); } - regulator_bulk_free(msmfalcon_cdc->num_of_supplies, - msmfalcon_cdc->supplies); - kfree(msmfalcon_cdc->supplies); + regulator_bulk_free(sdm660_cdc->num_of_supplies, + sdm660_cdc->supplies); + kfree(sdm660_cdc->supplies); } -static const struct of_device_id msmfalcon_codec_of_match[] = { +static const struct of_device_id sdm660_codec_of_match[] = { { .compatible = "qcom,pmic-analog-codec", }, {}, }; static void msm_anlg_add_child_devices(struct work_struct *work) { - struct msmfalcon_cdc *pdata; + struct sdm660_cdc *pdata; struct platform_device *pdev; struct device_node *node; struct msm_dig_ctrl_data *dig_ctrl_data = NULL, *temp; @@ -4453,7 +4453,7 @@ static void msm_anlg_add_child_devices(struct work_struct *work) struct msm_dig_ctrl_platform_data *platdata; char plat_dev_name[MSM_DIG_CDC_STRING_LEN]; - pdata = container_of(work, struct msmfalcon_cdc, + pdata = container_of(work, struct sdm660_cdc, msm_anlg_add_child_devices_work); if (!pdata) { pr_err("%s: Memory for pdata does not exist\n", @@ -4534,8 +4534,8 @@ err: static int msm_anlg_cdc_probe(struct platform_device *pdev) { int ret = 0; - struct msmfalcon_cdc *msmfalcon_cdc = NULL; - struct msmfalcon_cdc_pdata *pdata; + struct sdm660_cdc *sdm660_cdc = NULL; + struct sdm660_cdc_pdata *pdata; int adsp_state; adsp_state = apr_get_subsys_state(); @@ -4561,21 +4561,21 @@ static int msm_anlg_cdc_probe(struct platform_device *pdev) __func__); goto rtn; } - msmfalcon_cdc = devm_kzalloc(&pdev->dev, sizeof(struct msmfalcon_cdc), + sdm660_cdc = devm_kzalloc(&pdev->dev, sizeof(struct sdm660_cdc), GFP_KERNEL); - if (msmfalcon_cdc == NULL) { + if (sdm660_cdc == NULL) { ret = -ENOMEM; goto rtn; } - msmfalcon_cdc->dev = &pdev->dev; - ret = msm_anlg_cdc_init_supplies(msmfalcon_cdc, pdata); + sdm660_cdc->dev = &pdev->dev; + ret = msm_anlg_cdc_init_supplies(sdm660_cdc, pdata); if (ret) { dev_err(&pdev->dev, "%s: Fail to enable Codec supplies\n", __func__); goto rtn; } - ret = msm_anlg_cdc_enable_static_supplies(msmfalcon_cdc, pdata); + ret = msm_anlg_cdc_enable_static_supplies(sdm660_cdc, pdata); if (ret) { dev_err(&pdev->dev, "%s: Fail to enable Codec pre-reset supplies\n", @@ -4585,7 +4585,7 @@ static int msm_anlg_cdc_probe(struct platform_device *pdev) /* Allow supplies to be ready */ usleep_range(5, 6); - dev_set_drvdata(&pdev->dev, msmfalcon_cdc); + dev_set_drvdata(&pdev->dev, sdm660_cdc); if (wcd9xxx_spmi_irq_init()) { dev_err(&pdev->dev, "%s: irq initialization failed\n", __func__); @@ -4595,7 +4595,7 @@ static int msm_anlg_cdc_probe(struct platform_device *pdev) } ret = snd_soc_register_codec(&pdev->dev, - &soc_codec_dev_msmfalcon_cdc, + &soc_codec_dev_sdm660_cdc, msm_anlg_cdc_i2s_dai, ARRAY_SIZE(msm_anlg_cdc_i2s_dai)); if (ret) { @@ -4604,29 +4604,29 @@ static int msm_anlg_cdc_probe(struct platform_device *pdev) __func__, ret); goto err_supplies; } - msmfalcon_cdc->dig_plat_data.handle = (void *) msmfalcon_cdc; - msmfalcon_cdc->dig_plat_data.update_clkdiv = update_clkdiv; - msmfalcon_cdc->dig_plat_data.get_cdc_version = get_cdc_version; - msmfalcon_cdc->dig_plat_data.register_notifier = + sdm660_cdc->dig_plat_data.handle = (void *) sdm660_cdc; + sdm660_cdc->dig_plat_data.update_clkdiv = update_clkdiv; + sdm660_cdc->dig_plat_data.get_cdc_version = get_cdc_version; + sdm660_cdc->dig_plat_data.register_notifier = msm_anlg_cdc_dig_register_notifier; - INIT_WORK(&msmfalcon_cdc->msm_anlg_add_child_devices_work, + INIT_WORK(&sdm660_cdc->msm_anlg_add_child_devices_work, msm_anlg_add_child_devices); - schedule_work(&msmfalcon_cdc->msm_anlg_add_child_devices_work); + schedule_work(&sdm660_cdc->msm_anlg_add_child_devices_work); return ret; err_supplies: - msm_anlg_cdc_disable_supplies(msmfalcon_cdc, pdata); + msm_anlg_cdc_disable_supplies(sdm660_cdc, pdata); rtn: return ret; } static int msm_anlg_cdc_remove(struct platform_device *pdev) { - struct msmfalcon_cdc *msmfalcon_cdc = dev_get_drvdata(&pdev->dev); - struct msmfalcon_cdc_pdata *pdata = msmfalcon_cdc->dev->platform_data; + struct sdm660_cdc *sdm660_cdc = dev_get_drvdata(&pdev->dev); + struct sdm660_cdc_pdata *pdata = sdm660_cdc->dev->platform_data; snd_soc_unregister_codec(&pdev->dev); - msm_anlg_cdc_disable_supplies(msmfalcon_cdc, pdata); + msm_anlg_cdc_disable_supplies(sdm660_cdc, pdata); return 0; } @@ -4634,7 +4634,7 @@ static struct platform_driver msm_anlg_codec_driver = { .driver = { .owner = THIS_MODULE, .name = DRV_NAME, - .of_match_table = of_match_ptr(msmfalcon_codec_of_match) + .of_match_table = of_match_ptr(sdm660_codec_of_match) }, .probe = msm_anlg_cdc_probe, .remove = msm_anlg_cdc_remove, diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.h b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.h index 112b544b7de8..e0626d3be971 100644 --- a/sound/soc/codecs/msmfalcon_cdc/msm-analog-cdc.h +++ b/sound/soc/codecs/sdm660_cdc/msm-analog-cdc.h @@ -17,7 +17,7 @@ #include <sound/q6afe-v2.h> #include "../wcd-mbhc-v2.h" #include "../wcdcal-hwdep.h" -#include "msmfalcon-cdc-registers.h" +#include "sdm660-cdc-registers.h" #define MICBIAS_EXT_BYP_CAP 0x00 #define MICBIAS_NO_EXT_BYP_CAP 0x01 @@ -83,14 +83,14 @@ struct wcd_micbias_setting { bool bias2_is_headset_only; }; -enum msmfalcon_cdc_pid_current { +enum sdm660_cdc_pid_current { MSM89XX_PID_MIC_2P5_UA, MSM89XX_PID_MIC_5_UA, MSM89XX_PID_MIC_10_UA, MSM89XX_PID_MIC_20_UA, }; -struct msmfalcon_cdc_reg_mask_val { +struct sdm660_cdc_reg_mask_val { u16 reg; u8 mask; u8 val; @@ -132,7 +132,7 @@ enum { CODEC_DELAY_1_1_MS = 1100, }; -struct msmfalcon_cdc_regulator { +struct sdm660_cdc_regulator { const char *name; int min_uv; int max_uv; @@ -154,7 +154,7 @@ struct wcd_imped_i_ref { int offset; }; -enum msmfalcon_cdc_micbias_num { +enum sdm660_cdc_micbias_num { MSM89XX_MICBIAS1 = 0, }; @@ -172,7 +172,7 @@ struct msm_dig_ctrl_platform_data { bool enable); }; -struct msmfalcon_cdc { +struct sdm660_cdc { struct device *dev; u32 num_of_supplies; struct regulator_bulk_data *supplies; @@ -184,12 +184,12 @@ struct msmfalcon_cdc { struct blocking_notifier_head notifier; }; -struct msmfalcon_cdc_pdata { +struct sdm660_cdc_pdata { struct wcd_micbias_setting micbias; - struct msmfalcon_cdc_regulator regulator[MAX_REGULATOR]; + struct sdm660_cdc_regulator regulator[MAX_REGULATOR]; }; -struct msmfalcon_cdc_priv { +struct sdm660_cdc_priv { struct snd_soc_codec *codec; u16 pmic_rev; u16 codec_version; @@ -230,7 +230,7 @@ extern int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec, extern void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec); -extern void msmfalcon_cdc_update_int_spk_boost(bool enable); +extern void sdm660_cdc_update_int_spk_boost(bool enable); extern void msm_anlg_cdc_spk_ext_pa_cb( int (*codec_spk_ext_pa)(struct snd_soc_codec *codec, diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-cdc-common.h b/sound/soc/codecs/sdm660_cdc/msm-cdc-common.h index 9f2e9355197b..7a63a71ceeb1 100644 --- a/sound/soc/codecs/msmfalcon_cdc/msm-cdc-common.h +++ b/sound/soc/codecs/sdm660_cdc/msm-cdc-common.h @@ -11,7 +11,7 @@ */ #include <linux/regmap.h> -#include "msmfalcon-cdc-registers.h" +#include "sdm660-cdc-registers.h" extern struct reg_default msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE]; diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.c b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c index d036b82654f0..ac71e3c6d6a1 100644 --- a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.c +++ b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.c @@ -26,10 +26,10 @@ #include <sound/soc.h> #include <sound/soc-dapm.h> #include <sound/tlv.h> -#include "msmfalcon-cdc-registers.h" +#include "sdm660-cdc-registers.h" #include "msm-digital-cdc.h" #include "msm-cdc-common.h" -#include "../../msm/msmfalcon-common.h" +#include "../../msm/sdm660-common.h" #define DRV_NAME "msm_digital_codec" #define MCLK_RATE_9P6MHZ 9600000 diff --git a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.h b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.h index 4cb82cd421b0..4cb82cd421b0 100644 --- a/sound/soc/codecs/msmfalcon_cdc/msm-digital-cdc.h +++ b/sound/soc/codecs/sdm660_cdc/msm-digital-cdc.h diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.c b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.c index 5ba2dac1ec20..63a715c5248c 100644 --- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.c +++ b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.c @@ -26,8 +26,8 @@ #include <soc/qcom/pm.h> #include <sound/soc.h> #include "msm-analog-cdc.h" -#include "msmfalcon-cdc-irq.h" -#include "msmfalcon-cdc-registers.h" +#include "sdm660-cdc-irq.h" +#include "sdm660-cdc-registers.h" #define MAX_NUM_IRQS 14 #define NUM_IRQ_REGS 2 diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.h b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.h index 659e52cc2a5e..659e52cc2a5e 100644 --- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-irq.h +++ b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-irq.h diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-registers.h b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-registers.h index 34c3d3333d6e..5e042e2d466a 100644 --- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-cdc-registers.h +++ b/sound/soc/codecs/sdm660_cdc/sdm660-cdc-registers.h @@ -9,8 +9,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#ifndef MSMFALCON_WCD_REGISTERS_H -#define MSMFALCON_WCD_REGISTERS_H +#ifndef SDM660_WCD_REGISTERS_H +#define SDM660_WCD_REGISTERS_H #define CDC_DIG_BASE 0xF000 #define CDC_ANA_BASE 0xF100 diff --git a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-regmap.c b/sound/soc/codecs/sdm660_cdc/sdm660-regmap.c index 5001c8da9877..1c3a8d2c2fd9 100644 --- a/sound/soc/codecs/msmfalcon_cdc/msmfalcon-regmap.c +++ b/sound/soc/codecs/sdm660_cdc/sdm660-regmap.c @@ -12,7 +12,7 @@ */ #include <linux/regmap.h> -#include "msmfalcon-cdc-registers.h" +#include "sdm660-cdc-registers.h" /* * Default register reset values that are common across different versions diff --git a/sound/soc/codecs/wcd9330.c b/sound/soc/codecs/wcd9330.c index fa396aa55ac9..1258c83e26a1 100644 --- a/sound/soc/codecs/wcd9330.c +++ b/sound/soc/codecs/wcd9330.c @@ -1536,6 +1536,13 @@ static int tomtom_mad_input_put(struct snd_kcontrol *kcontrol, tomtom_mad_input = ucontrol->value.integer.value[0]; micb_4_int_reg = tomtom->resmgr.reg_addr->micb_4_int_rbias; + if (tomtom_mad_input >= ARRAY_SIZE(tomtom_conn_mad_text)) { + dev_err(codec->dev, + "%s: tomtom_mad_input = %d out of bounds\n", + __func__, tomtom_mad_input); + return -EINVAL; + } + pr_debug("%s: tomtom_mad_input = %s\n", __func__, tomtom_conn_mad_text[tomtom_mad_input]); diff --git a/sound/soc/codecs/wcd9335.c b/sound/soc/codecs/wcd9335.c index 71858e268232..89357f32d288 100644 --- a/sound/soc/codecs/wcd9335.c +++ b/sound/soc/codecs/wcd9335.c @@ -7931,6 +7931,13 @@ static int tasha_mad_input_put(struct snd_kcontrol *kcontrol, tasha_mad_input = ucontrol->value.integer.value[0]; + if (tasha_mad_input >= ARRAY_SIZE(tasha_conn_mad_text)) { + dev_err(codec->dev, + "%s: tasha_mad_input = %d out of bounds\n", + __func__, tasha_mad_input); + return -EINVAL; + } + if (!strcmp(tasha_conn_mad_text[tasha_mad_input], "NOTUSED1") || !strcmp(tasha_conn_mad_text[tasha_mad_input], "NOTUSED2") || !strcmp(tasha_conn_mad_text[tasha_mad_input], "NOTUSED3") || @@ -13441,8 +13448,6 @@ static int tasha_post_reset_cb(struct wcd9xxx *wcd9xxx) /* Class-H Init*/ wcd_clsh_init(&tasha->clsh_d); - /* Default HPH Mode to Class-H HiFi */ - tasha->hph_mode = CLS_H_HIFI; for (i = 0; i < TASHA_MAX_MICBIAS; i++) tasha->micb_ref[i] = 0; @@ -13450,8 +13455,6 @@ static int tasha_post_reset_cb(struct wcd9xxx *wcd9xxx) tasha_update_reg_defaults(tasha); tasha->codec = codec; - for (i = 0; i < COMPANDER_MAX; i++) - tasha->comp_enabled[i] = 0; dev_dbg(codec->dev, "%s: MCLK Rate = %x\n", __func__, control->mclk_rate); diff --git a/sound/soc/codecs/wcd934x/wcd934x.c b/sound/soc/codecs/wcd934x/wcd934x.c index 9b45db43ffb2..f2850d5e5ed3 100644 --- a/sound/soc/codecs/wcd934x/wcd934x.c +++ b/sound/soc/codecs/wcd934x/wcd934x.c @@ -5204,6 +5204,14 @@ static int tavil_mad_input_put(struct snd_kcontrol *kcontrol, tavil_mad_input = ucontrol->value.integer.value[0]; + if (tavil_mad_input >= sizeof(tavil_conn_mad_text)/ + sizeof(tavil_conn_mad_text[0])) { + dev_err(codec->dev, + "%s: tavil_mad_input = %d out of bounds\n", + __func__, tavil_mad_input); + return -EINVAL; + } + if (strnstr(tavil_conn_mad_text[tavil_mad_input], "NOTUSED", sizeof("NOTUSED"))) { dev_dbg(codec->dev, diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig index 69d74a8703b6..835022b76b78 100644 --- a/sound/soc/msm/Kconfig +++ b/sound/soc/msm/Kconfig @@ -108,7 +108,7 @@ config SND_SOC_CPE listen on codec. config SND_SOC_INT_CODEC - tristate "SoC Machine driver for MSMFALCON_INT" + tristate "SoC Machine driver for SDM660_INT" depends on ARCH_QCOM select SND_SOC_QDSP6V2 select SND_SOC_MSM_STUB @@ -121,7 +121,7 @@ config SND_SOC_INT_CODEC select MSM_QDSP6V2_CODECS select MSM_CDC_PINCTRL select SND_SOC_MSM_SDW - select SND_SOC_MSMFALCON_CDC + select SND_SOC_SDM660_CDC select QTI_PP select DTS_SRS_TM select DOLBY_DAP @@ -129,7 +129,7 @@ config SND_SOC_INT_CODEC select SND_HWDEP select MSM_ULTRASOUND select DTS_EAGLE - select SND_SOC_MSMFALCON_COMMON + select SND_SOC_SDM660_COMMON select SND_SOC_COMPRESS select PINCTRL_LPI help @@ -140,7 +140,7 @@ config SND_SOC_INT_CODEC DAI-links config SND_SOC_EXT_CODEC - tristate "SoC Machine driver for MSMFALCON_EXT" + tristate "SoC Machine driver for SDM660_EXT" depends on ARCH_QCOM select SND_SOC_QDSP6V2 select SND_SOC_MSM_STUB @@ -164,7 +164,7 @@ config SND_SOC_EXT_CODEC select SND_HWDEP select MSM_ULTRASOUND select DTS_EAGLE - select SND_SOC_MSMFALCON_COMMON + select SND_SOC_SDM660_COMMON select SND_SOC_COMPRESS select PINCTRL_LPI help @@ -233,13 +233,13 @@ config SND_SOC_MSM8998 the machine driver and the corresponding DAI-links -config SND_SOC_FALCON - tristate "SoC Machine driver for MSMFALCON boards" - depends on ARCH_MSMFALCON +config SND_SOC_660 + tristate "SoC Machine driver for SDM660 boards" + depends on ARCH_SDM660 select SND_SOC_INT_CODEC select SND_SOC_EXT_CODEC help - To add support for SoC audio on MSMFALCON. + To add support for SoC audio on SDM660. This will enable sound soc drivers which interfaces with DSP, also it will enable the machine driver and the corresponding diff --git a/sound/soc/msm/Makefile b/sound/soc/msm/Makefile index d66f9eb79cea..cd63b491285c 100644 --- a/sound/soc/msm/Makefile +++ b/sound/soc/msm/Makefile @@ -20,16 +20,16 @@ obj-$(CONFIG_SND_SOC_MSM8996) += snd-soc-msm8996.o snd-soc-msm8998-objs := msm8998.o obj-$(CONFIG_SND_SOC_MSM8998) += snd-soc-msm8998.o -# for MSMFALCON sound card driver -snd-soc-msmfalcon-common-objs := msmfalcon-common.o -obj-$(CONFIG_SND_SOC_MSMFALCON_COMMON) += snd-soc-msmfalcon-common.o +# for SDM660 sound card driver +snd-soc-sdm660-common-objs := sdm660-common.o +obj-$(CONFIG_SND_SOC_SDM660_COMMON) += snd-soc-sdm660-common.o -# for MSMFALCON sound card driver -snd-soc-int-codec-objs := msmfalcon-internal.o -obj-$(CONFIG_SND_SOC_INT_CODEC) += snd-soc-msmfalcon-common.o +# for SDM660 sound card driver +snd-soc-int-codec-objs := sdm660-internal.o +obj-$(CONFIG_SND_SOC_INT_CODEC) += snd-soc-sdm660-common.o obj-$(CONFIG_SND_SOC_INT_CODEC) += snd-soc-int-codec.o -# for MSMFALCON sound card driver -snd-soc-ext-codec-objs := msmfalcon-external.o msmfalcon-ext-dai-links.o -obj-$(CONFIG_SND_SOC_EXT_CODEC) += snd-soc-msmfalcon-common.o +# for SDM660 sound card driver +snd-soc-ext-codec-objs := sdm660-external.o sdm660-ext-dai-links.o +obj-$(CONFIG_SND_SOC_EXT_CODEC) += snd-soc-sdm660-common.o obj-$(CONFIG_SND_SOC_EXT_CODEC) += snd-soc-ext-codec.o diff --git a/sound/soc/msm/msm-cpe-lsm.c b/sound/soc/msm/msm-cpe-lsm.c index ef4c9b01d91e..5b90cc11548e 100644 --- a/sound/soc/msm/msm-cpe-lsm.c +++ b/sound/soc/msm/msm-cpe-lsm.c @@ -1878,6 +1878,13 @@ static int msm_cpe_lsm_reg_model(struct snd_pcm_substream *substream, lsm_ops->lsm_get_snd_model_offset(cpe->core_handle, session, &offset); + /* Check if 'p_info->param_size + offset' crosses U32_MAX. */ + if (p_info->param_size > U32_MAX - offset) { + dev_err(rtd->dev, + "%s: Invalid param_size %d\n", + __func__, p_info->param_size); + return -EINVAL; + } session->snd_model_size = p_info->param_size + offset; session->snd_model_data = vzalloc(session->snd_model_size); diff --git a/sound/soc/msm/qdsp6v2/msm-dolby-dap-config.c b/sound/soc/msm/qdsp6v2/msm-dolby-dap-config.c index bb0f890d300f..5866e46cc6a2 100644 --- a/sound/soc/msm/qdsp6v2/msm-dolby-dap-config.c +++ b/sound/soc/msm/qdsp6v2/msm-dolby-dap-config.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2014, 2016, The Linux Foundation. All rights reserved. * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. @@ -18,6 +18,10 @@ #include "msm-dolby-dap-config.h" +#ifndef DOLBY_PARAM_VCNB_MAX_LENGTH +#define DOLBY_PARAM_VCNB_MAX_LENGTH 40 +#endif + /* dolby endp based parameters */ struct dolby_dap_endp_params_s { int device; @@ -896,6 +900,11 @@ int msm_dolby_dap_param_visualizer_control_get(struct snd_kcontrol *kcontrol, uint32_t param_payload_len = DOLBY_PARAM_PAYLOAD_SIZE * sizeof(uint32_t); int port_id, copp_idx, idx; + if (length > DOLBY_PARAM_VCNB_MAX_LENGTH || length <= 0) { + pr_err("%s Incorrect VCNB length", __func__); + ucontrol->value.integer.value[0] = 0; + return -EINVAL; + } for (idx = 0; idx < AFE_MAX_PORTS; idx++) { port_id = dolby_dap_params_states.port_id[idx]; copp_idx = dolby_dap_params_states.copp_idx[idx]; diff --git a/sound/soc/msm/qdsp6v2/msm-lsm-client.c b/sound/soc/msm/qdsp6v2/msm-lsm-client.c index 52830c9cbecb..efb6644e551f 100644 --- a/sound/soc/msm/qdsp6v2/msm-lsm-client.c +++ b/sound/soc/msm/qdsp6v2/msm-lsm-client.c @@ -730,8 +730,13 @@ static int msm_lsm_ioctl_shared(struct snd_pcm_substream *substream, switch (cmd) { case SNDRV_LSM_SET_SESSION_DATA: dev_dbg(rtd->dev, "%s: set session data\n", __func__); - memcpy(&session_data, arg, - sizeof(struct snd_lsm_session_data)); + if (copy_from_user(&session_data, arg, + sizeof(session_data))) { + dev_err(rtd->dev, "%s: %s: copy_from_user failed\n", + __func__, "LSM_SET_SESSION_DATA"); + return -EFAULT; + } + if (session_data.app_id != LSM_VOICE_WAKEUP_APP_ID_V2) { dev_err(rtd->dev, "%s:Invalid App id %d for Listen client\n", @@ -820,13 +825,6 @@ static int msm_lsm_ioctl_shared(struct snd_pcm_substream *substream, break; case SNDRV_LSM_SET_PARAMS: - if (!arg) { - dev_err(rtd->dev, - "%s: %s Invalid argument\n", - __func__, "SNDRV_LSM_SET_PARAMS"); - return -EINVAL; - } - dev_dbg(rtd->dev, "%s: set_params\n", __func__); memcpy(&det_params, arg, sizeof(det_params)); @@ -978,45 +976,43 @@ static int msm_lsm_ioctl_shared(struct snd_pcm_substream *substream, break; } case SNDRV_LSM_LAB_CONTROL: { - u32 *enable = NULL; - if (!arg) { - dev_err(rtd->dev, - "%s: Invalid param arg for ioctl %s session %d\n", - __func__, "SNDRV_LSM_LAB_CONTROL", - prtd->lsm_client->session); - rc = -EINVAL; - break; + u32 enable; + + if (copy_from_user(&enable, arg, sizeof(enable))) { + dev_err(rtd->dev, "%s: %s: copy_frm_user failed\n", + __func__, "LSM_LAB_CONTROL"); + return -EFAULT; } - enable = (int *)arg; + dev_dbg(rtd->dev, "%s: ioctl %s, enable = %d\n", - __func__, "SNDRV_LSM_LAB_CONTROL", *enable); + __func__, "SNDRV_LSM_LAB_CONTROL", enable); if (!prtd->lsm_client->started) { - if (prtd->lsm_client->lab_enable == *enable) { + if (prtd->lsm_client->lab_enable == enable) { dev_dbg(rtd->dev, "%s: Lab for session %d already %s\n", __func__, prtd->lsm_client->session, - ((*enable) ? "enabled" : "disabled")); + enable ? "enabled" : "disabled"); rc = 0; break; } - rc = q6lsm_lab_control(prtd->lsm_client, *enable); + rc = q6lsm_lab_control(prtd->lsm_client, enable); if (rc) { dev_err(rtd->dev, "%s: ioctl %s failed rc %d to %s lab for session %d\n", __func__, "SNDRV_LAB_CONTROL", rc, - ((*enable) ? "enable" : "disable"), + enable ? "enable" : "disable", prtd->lsm_client->session); } else { rc = msm_lsm_lab_buffer_alloc(prtd, - ((*enable) ? LAB_BUFFER_ALLOC - : LAB_BUFFER_DEALLOC)); + enable ? LAB_BUFFER_ALLOC + : LAB_BUFFER_DEALLOC); if (rc) dev_err(rtd->dev, "%s: msm_lsm_lab_buffer_alloc failed rc %d for %s", __func__, rc, - ((*enable) ? "ALLOC" : "DEALLOC")); + enable ? "ALLOC" : "DEALLOC"); if (!rc) - prtd->lsm_client->lab_enable = *enable; + prtd->lsm_client->lab_enable = enable; } } else { dev_err(rtd->dev, "%s: ioctl %s issued after start", @@ -1057,12 +1053,6 @@ static int msm_lsm_ioctl_shared(struct snd_pcm_substream *substream, return rc; } #ifdef CONFIG_COMPAT -struct snd_lsm_event_status32 { - u16 status; - u16 payload_size; - u8 payload[0]; -}; - struct snd_lsm_sound_model_v2_32 { compat_uptr_t data; compat_uptr_t confidence_level; @@ -1094,8 +1084,6 @@ struct snd_lsm_module_params_32 { }; enum { - SNDRV_LSM_EVENT_STATUS32 = - _IOW('U', 0x02, struct snd_lsm_event_status32), SNDRV_LSM_REG_SND_MODEL_V2_32 = _IOW('U', 0x07, struct snd_lsm_sound_model_v2_32), SNDRV_LSM_SET_PARAMS_32 = @@ -1126,12 +1114,12 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, prtd = runtime->private_data; switch (cmd) { - case SNDRV_LSM_EVENT_STATUS32: { - struct snd_lsm_event_status32 userarg32, *user32 = NULL; - struct snd_lsm_event_status *user = NULL; + case SNDRV_LSM_EVENT_STATUS: { + struct snd_lsm_event_status *user = NULL, userarg32; + struct snd_lsm_event_status *user32 = NULL; if (copy_from_user(&userarg32, arg, sizeof(userarg32))) { dev_err(rtd->dev, "%s: err copyuser ioctl %s\n", - __func__, "SNDRV_LSM_EVENT_STATUS32"); + __func__, "SNDRV_LSM_EVENT_STATUS"); return -EFAULT; } @@ -1285,13 +1273,6 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, return -EINVAL; } - if (!arg) { - dev_err(rtd->dev, - "%s: %s: No Param data to set\n", - __func__, "SET_MODULE_PARAMS_32"); - return -EINVAL; - } - if (copy_from_user(&p_data_32, arg, sizeof(p_data_32))) { dev_err(rtd->dev, @@ -1376,6 +1357,19 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, kfree(params32); break; } + case SNDRV_LSM_REG_SND_MODEL_V2: + case SNDRV_LSM_SET_PARAMS: + case SNDRV_LSM_SET_MODULE_PARAMS: + /* + * In ideal cases, the compat_ioctl should never be called + * with the above unlocked ioctl commands. Print error + * and return error if it does. + */ + dev_err(rtd->dev, + "%s: Invalid cmd for compat_ioctl\n", + __func__); + err = -EINVAL; + break; default: err = msm_lsm_ioctl_shared(substream, cmd, arg); break; @@ -1391,7 +1385,6 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, { int err = 0; u32 size = 0; - struct snd_lsm_session_data session_data; struct snd_pcm_runtime *runtime; struct snd_soc_pcm_runtime *rtd; struct lsm_priv *prtd; @@ -1406,26 +1399,6 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, rtd = substream->private_data; switch (cmd) { - case SNDRV_LSM_SET_SESSION_DATA: - dev_dbg(rtd->dev, - "%s: SNDRV_LSM_SET_SESSION_DATA\n", - __func__); - if (copy_from_user(&session_data, (void *)arg, - sizeof(struct snd_lsm_session_data))) { - err = -EFAULT; - dev_err(rtd->dev, - "%s: copy from user failed, size %zd\n", - __func__, sizeof(struct snd_lsm_session_data)); - break; - } - if (!err) - err = msm_lsm_ioctl_shared(substream, - cmd, &session_data); - if (err) - dev_err(rtd->dev, - "%s REG_SND_MODEL failed err %d\n", - __func__, err); - break; case SNDRV_LSM_REG_SND_MODEL_V2: { struct snd_lsm_sound_model_v2 snd_model_v2; @@ -1436,11 +1409,6 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, return -EINVAL; } - if (!arg) { - dev_err(rtd->dev, - "%s: Invalid params snd_model\n", __func__); - return -EINVAL; - } if (copy_from_user(&snd_model_v2, arg, sizeof(snd_model_v2))) { err = -EFAULT; dev_err(rtd->dev, @@ -1469,12 +1437,6 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, } pr_debug("%s: SNDRV_LSM_SET_PARAMS\n", __func__); - if (!arg) { - dev_err(rtd->dev, - "%s: %s, Invalid params\n", - __func__, "SNDRV_LSM_SET_PARAMS"); - return -EINVAL; - } if (copy_from_user(&det_params, arg, sizeof(det_params))) { @@ -1507,13 +1469,6 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, return -EINVAL; } - if (!arg) { - dev_err(rtd->dev, - "%s: %s: No Param data to set\n", - __func__, "SET_MODULE_PARAMS"); - return -EINVAL; - } - if (copy_from_user(&p_data, arg, sizeof(p_data))) { dev_err(rtd->dev, @@ -1571,12 +1526,6 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, struct snd_lsm_event_status *user = NULL, userarg; dev_dbg(rtd->dev, "%s: SNDRV_LSM_EVENT_STATUS\n", __func__); - if (!arg) { - dev_err(rtd->dev, - "%s: Invalid params event status\n", - __func__); - return -EINVAL; - } if (copy_from_user(&userarg, arg, sizeof(userarg))) { dev_err(rtd->dev, "%s: err copyuser event_status\n", diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c index 2639bfd5b8fd..dc57ae804dfa 100644 --- a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c +++ b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c @@ -10982,6 +10982,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"TERT_MI2S_UL_HL", NULL, "TERT_MI2S_TX"}, {"SEC_I2S_RX", NULL, "SEC_I2S_DL_HL"}, {"PRI_MI2S_UL_HL", NULL, "PRI_MI2S_TX"}, + {"SEC_MI2S_UL_HL", NULL, "SEC_MI2S_TX"}, {"SEC_MI2S_RX", NULL, "SEC_MI2S_DL_HL"}, {"PRI_MI2S_RX", NULL, "PRI_MI2S_DL_HL"}, {"TERT_MI2S_RX", NULL, "TERT_MI2S_DL_HL"}, diff --git a/sound/soc/msm/qdsp6v2/msm-qti-pp-config.c b/sound/soc/msm/qdsp6v2/msm-qti-pp-config.c index 7c8af09a8793..832d7c0170f4 100644 --- a/sound/soc/msm/qdsp6v2/msm-qti-pp-config.c +++ b/sound/soc/msm/qdsp6v2/msm-qti-pp-config.c @@ -579,7 +579,7 @@ static int msm_qti_pp_set_sec_auxpcm_lb_vol_mixer( static int msm_qti_pp_get_channel_map_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { - char channel_map[PCM_FORMAT_MAX_NUM_CHANNEL]; + char channel_map[PCM_FORMAT_MAX_NUM_CHANNEL] = {0}; int i; adm_get_multi_ch_map(channel_map, ADM_PATH_PLAYBACK); diff --git a/sound/soc/msm/qdsp6v2/q6core.c b/sound/soc/msm/qdsp6v2/q6core.c index 9782fa26a2e9..5399a101ba62 100644 --- a/sound/soc/msm/qdsp6v2/q6core.c +++ b/sound/soc/msm/qdsp6v2/q6core.c @@ -221,7 +221,6 @@ struct cal_block_data *cal_utils_get_cal_block_by_key( int32_t core_set_license(uint32_t key, uint32_t module_id) { struct avcs_cmd_set_license *cmd_setl = NULL; - struct audio_cal_info_metainfo *metainfo = NULL; struct cal_block_data *cal_block = NULL; int rc = 0, packet_size = 0; @@ -278,9 +277,9 @@ int32_t core_set_license(uint32_t key, uint32_t module_id) memcpy((uint8_t *)cmd_setl + sizeof(struct avcs_cmd_set_license), cal_block->cal_data.kvaddr, cal_block->cal_data.size); - pr_info("%s: Set license opcode=0x%x ,key=0x%x, id =0x%x, size = %d\n", + pr_info("%s: Set license opcode=0x%x, id =0x%x, size = %d\n", __func__, cmd_setl->hdr.opcode, - metainfo->nKey, cmd_setl->id, cmd_setl->size); + cmd_setl->id, cmd_setl->size); rc = apr_send_pkt(q6core_lcl.core_handle_q, (uint32_t *)cmd_setl); if (rc < 0) pr_err("%s: SET_LICENSE failed op[0x%x]rc[%d]\n", diff --git a/sound/soc/msm/msmfalcon-common.c b/sound/soc/msm/sdm660-common.c index 013127c48984..1497ddcca61f 100644 --- a/sound/soc/msm/msmfalcon-common.c +++ b/sound/soc/msm/sdm660-common.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -16,13 +16,13 @@ #include <sound/pcm_params.h> #include <sound/q6afe-v2.h> #include "qdsp6v2/msm-pcm-routing-v2.h" -#include "msmfalcon-common.h" -#include "msmfalcon-internal.h" -#include "msmfalcon-external.h" -#include "../codecs/msmfalcon_cdc/msm-analog-cdc.h" +#include "sdm660-common.h" +#include "sdm660-internal.h" +#include "sdm660-external.h" +#include "../codecs/sdm660_cdc/msm-analog-cdc.h" #include "../codecs/wsa881x.h" -#define DRV_NAME "msmfalcon-asoc-snd" +#define DRV_NAME "sdm660-asoc-snd" #define MSM_INT_DIGITAL_CODEC "msm-dig-codec" #define PMIC_INT_ANALOG_CODEC "analog-codec" @@ -169,6 +169,7 @@ struct mi2s_conf { struct mutex lock; u32 ref_cnt; u32 msm_is_mi2s_master; + u32 msm_is_ext_mclk; }; struct auxpcm_conf { @@ -176,6 +177,13 @@ struct auxpcm_conf { u32 ref_cnt; }; +static u32 mi2s_ebit_clk[MI2S_MAX] = { + Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT, + Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT, + Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT, + Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT +}; + struct msm_wsa881x_dev_info { struct device_node *of_node; u32 index; @@ -340,6 +348,43 @@ static struct afe_clk_set mi2s_clk[MI2S_MAX] = { } }; +static struct afe_clk_set mi2s_mclk[MI2S_MAX] = { + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_MCLK_1, + Q6AFE_LPASS_OSR_CLK_9_P600_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_MCLK_2, + Q6AFE_LPASS_OSR_CLK_9_P600_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_MCLK_3, + Q6AFE_LPASS_OSR_CLK_9_P600_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + }, + { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_MCLK_4, + Q6AFE_LPASS_OSR_CLK_9_P600_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, + } +}; + + + static struct mi2s_aux_pcm_common_conf mi2s_auxpcm_conf[PCM_I2S_SEL_MAX]; static struct mi2s_conf mi2s_intf_conf[MI2S_MAX]; static struct auxpcm_conf auxpcm_intf_conf[AUX_PCM_MAX]; @@ -1638,6 +1683,17 @@ const struct snd_kcontrol_new msm_common_snd_controls[] = { tdm_tx_ch_put), }; +/** + * msm_common_snd_controls_size - to return controls size + * + * Return: returns size of common controls array + */ +int msm_common_snd_controls_size(void) +{ + return ARRAY_SIZE(msm_common_snd_controls); +} +EXPORT_SYMBOL(msm_common_snd_controls_size); + static inline int param_is_mask(int p) { return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && @@ -2095,6 +2151,7 @@ int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) int ret = 0; struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int port_id = msm_get_port_id(rtd->dai_link->be_id); int index = cpu_dai->id; unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS; @@ -2117,6 +2174,11 @@ int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) */ mutex_lock(&mi2s_intf_conf[index].lock); if (++mi2s_intf_conf[index].ref_cnt == 1) { + /* Check if msm needs to provide the clock to the interface */ + if (!mi2s_intf_conf[index].msm_is_mi2s_master) { + mi2s_clk[index].clk_id = mi2s_ebit_clk[index]; + fmt = SND_SOC_DAIFMT_CBM_CFM; + } ret = msm_mi2s_set_sclk(substream, true); if (IS_ERR_VALUE(ret)) { dev_err(rtd->card->dev, @@ -2136,9 +2198,6 @@ int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) ret = -EINVAL; goto clk_off; } - /* Check if msm needs to provide the clock to the interface */ - if (!mi2s_intf_conf[index].msm_is_mi2s_master) - fmt = SND_SOC_DAIFMT_CBM_CFM; ret = snd_soc_dai_set_fmt(cpu_dai, fmt); if (IS_ERR_VALUE(ret)) { dev_err(rtd->card->dev, @@ -2146,7 +2205,21 @@ int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) __func__, index, ret); goto clk_off; } + if (mi2s_intf_conf[index].msm_is_ext_mclk) { + mi2s_mclk[index].enable = 1; + pr_debug("%s: Enabling mclk, clk_freq_in_hz = %u\n", + __func__, mi2s_mclk[index].clk_freq_in_hz); + ret = afe_set_lpass_clock_v2(port_id, + &mi2s_mclk[index]); + if (ret < 0) { + pr_err("%s: afe lpass mclk failed, err:%d\n", + __func__, ret); + goto clk_off; + } + } } + mutex_unlock(&mi2s_intf_conf[index].lock); + return 0; clk_off: if (IS_ERR_VALUE(ret)) msm_mi2s_set_sclk(substream, false); @@ -2168,6 +2241,7 @@ void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream) { int ret; struct snd_soc_pcm_runtime *rtd = substream->private_data; + int port_id = msm_get_port_id(rtd->dai_link->be_id); int index = rtd->cpu_dai->id; pr_debug("%s(): substream = %s stream = %d\n", __func__, @@ -2185,6 +2259,17 @@ void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream) __func__, index, ret); mi2s_intf_conf[index].ref_cnt++; } + if (mi2s_intf_conf[index].msm_is_ext_mclk) { + mi2s_mclk[index].enable = 0; + pr_debug("%s: Disabling mclk, clk_freq_in_hz = %u\n", + __func__, mi2s_mclk[index].clk_freq_in_hz); + ret = afe_set_lpass_clock_v2(port_id, + &mi2s_mclk[index]); + if (ret < 0) { + pr_err("%s: mclk disable failed for MCLK (%d); ret=%d\n", + __func__, index, ret); + } + } } mutex_unlock(&mi2s_intf_conf[index].lock); } @@ -2601,6 +2686,7 @@ static void i2s_auxpcm_init(struct platform_device *pdev) struct resource *muxsel; int count; u32 mi2s_master_slave[MI2S_MAX]; + u32 mi2s_ext_mclk[MI2S_MAX]; int ret; char *str[PCM_I2S_SEL_MAX] = { "lpaif_pri_mode_muxsel", @@ -2634,8 +2720,8 @@ static void i2s_auxpcm_init(struct platform_device *pdev) } ret = of_property_read_u32_array(pdev->dev.of_node, - "qcom,msm-mi2s-master", - mi2s_master_slave, MI2S_MAX); + "qcom,msm-mi2s-master", + mi2s_master_slave, MI2S_MAX); if (ret) { dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n", __func__); @@ -2645,6 +2731,18 @@ static void i2s_auxpcm_init(struct platform_device *pdev) mi2s_master_slave[count]; } } + + ret = of_property_read_u32_array(pdev->dev.of_node, + "qcom,msm-mi2s-ext-mclk", + mi2s_ext_mclk, MI2S_MAX); + if (ret) { + dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-ext-mclk in DT node\n", + __func__); + } else { + for (count = 0; count < MI2S_MAX; count++) + mi2s_intf_conf[count].msm_is_ext_mclk = + mi2s_ext_mclk[count]; + } } static void i2s_auxpcm_deinit(void) @@ -2658,12 +2756,12 @@ static void i2s_auxpcm_deinit(void) mi2s_auxpcm_conf[count].pcm_i2s_sel_vt_addr); } -static const struct of_device_id msmfalcon_asoc_machine_of_match[] = { - { .compatible = "qcom,msmfalcon-asoc-snd", +static const struct of_device_id sdm660_asoc_machine_of_match[] = { + { .compatible = "qcom,sdm660-asoc-snd", .data = "internal_codec"}, - { .compatible = "qcom,msmfalcon-asoc-snd-tasha", + { .compatible = "qcom,sdm660-asoc-snd-tasha", .data = "tasha_codec"}, - { .compatible = "qcom,msmfalcon-asoc-snd-tavil", + { .compatible = "qcom,sdm660-asoc-snd-tavil", .data = "tavil_codec"}, {}, }; @@ -2682,7 +2780,7 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) if (!pdata) return -ENOMEM; - match = of_match_node(msmfalcon_asoc_machine_of_match, + match = of_match_node(sdm660_asoc_machine_of_match, pdev->dev.of_node); if (!match) goto err; @@ -2772,11 +2870,24 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) ret = devm_snd_soc_register_card(&pdev->dev, card); - if (ret) { + if (ret == -EPROBE_DEFER) { + if (codec_reg_done) { + /* + * return failure as EINVAL since other codec + * registered sound card successfully. + * This avoids any further probe calls. + */ + ret = -EINVAL; + } + goto err; + } else if (ret) { dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); goto err; } + if (pdata->snd_card_val != INT_SND_CARD) + msm_ext_register_audio_notifier(pdev); + return 0; err: if (pdata->us_euro_gpio > 0) { @@ -2821,19 +2932,19 @@ static int msm_asoc_machine_remove(struct platform_device *pdev) return 0; } -static struct platform_driver msmfalcon_asoc_machine_driver = { +static struct platform_driver sdm660_asoc_machine_driver = { .driver = { .name = DRV_NAME, .owner = THIS_MODULE, .pm = &snd_soc_pm_ops, - .of_match_table = msmfalcon_asoc_machine_of_match, + .of_match_table = sdm660_asoc_machine_of_match, }, .probe = msm_asoc_machine_probe, .remove = msm_asoc_machine_remove, }; -module_platform_driver(msmfalcon_asoc_machine_driver); +module_platform_driver(sdm660_asoc_machine_driver); MODULE_DESCRIPTION("ALSA SoC msm"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:" DRV_NAME); -MODULE_DEVICE_TABLE(of, msmfalcon_asoc_machine_of_match); +MODULE_DEVICE_TABLE(of, sdm660_asoc_machine_of_match); diff --git a/sound/soc/msm/msmfalcon-common.h b/sound/soc/msm/sdm660-common.h index 3c18852cf897..36c2d9b7ca4e 100644 --- a/sound/soc/msm/msmfalcon-common.h +++ b/sound/soc/msm/sdm660-common.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -66,7 +66,8 @@ enum { }; extern const struct snd_kcontrol_new msm_common_snd_controls[]; -struct msmfalcon_codec { +extern bool codec_reg_done; +struct sdm660_codec { void* (*get_afe_config_fn)(struct snd_soc_codec *codec, enum afe_config_type config_type); }; @@ -90,7 +91,7 @@ struct msm_asoc_mach_data { struct device_node *dmic_gpio_p; /* used by pinctrl API */ struct device_node *ext_spk_gpio_p; /* used by pinctrl API */ struct snd_soc_codec *codec; - struct msmfalcon_codec msmfalcon_codec_fn; + struct sdm660_codec sdm660_codec_fn; struct snd_info_entry *codec_root; int spk_ext_pa_gpio; int mclk_freq; @@ -112,4 +113,5 @@ int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream); void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream); int msm_mi2s_snd_startup(struct snd_pcm_substream *substream); void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream); +int msm_common_snd_controls_size(void); #endif diff --git a/sound/soc/msm/msmfalcon-ext-dai-links.c b/sound/soc/msm/sdm660-ext-dai-links.c index fc6d52233a33..3e29221fe00f 100644 --- a/sound/soc/msm/msmfalcon-ext-dai-links.c +++ b/sound/soc/msm/sdm660-ext-dai-links.c @@ -19,11 +19,11 @@ #include <sound/pcm_params.h> #include "qdsp6v2/msm-pcm-routing-v2.h" #include "../codecs/wcd9335.h" -#include "msmfalcon-common.h" -#include "msmfalcon-external.h" +#include "sdm660-common.h" +#include "sdm660-external.h" #define DEV_NAME_STR_LEN 32 -#define __CHIPSET__ "MSMFALCON " +#define __CHIPSET__ "SDM660 " #define MSM_DAILINK_NAME(name) (__CHIPSET__#name) #define WCN_CDC_SLIM_RX_CH_MAX 2 @@ -1882,7 +1882,7 @@ struct snd_soc_card *populate_snd_card_dailinks(struct device *dev, if (strnstr(card->name, "tasha", strlen(card->name))) { codec_ver = tasha_codec_ver(); if (codec_ver == WCD9326) - card->name = "msmfalcon-tashalite-snd-card"; + card->name = "sdm660-tashalite-snd-card"; len1 = ARRAY_SIZE(msm_ext_common_fe_dai); len2 = len1 + ARRAY_SIZE(msm_ext_tasha_fe_dai); diff --git a/sound/soc/msm/msmfalcon-external.c b/sound/soc/msm/sdm660-external.c index ef0b23e2e51e..c900ce1a0fe9 100644 --- a/sound/soc/msm/msmfalcon-external.c +++ b/sound/soc/msm/sdm660-external.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -21,14 +21,14 @@ #include <linux/qdsp6v2/audio_notifier.h> #include "qdsp6v2/msm-pcm-routing-v2.h" #include "msm-audio-pinctrl.h" -#include "msmfalcon-common.h" -#include "msmfalcon-external.h" +#include "sdm660-common.h" +#include "sdm660-external.h" #include "../codecs/wcd9335.h" #include "../codecs/wcd934x/wcd934x.h" #include "../codecs/wcd934x/wcd934x-mbhc.h" -#define MSMFALCON_SPK_ON 1 -#define MSMFALCON_SPK_OFF 0 +#define SDM660_SPK_ON 1 +#define SDM660_SPK_OFF 0 #define WCD9XXX_MBHC_DEF_BUTTONS 8 #define WCD9XXX_MBHC_DEF_RLOADS 5 @@ -56,6 +56,7 @@ static int msm_ext_spk_control = 1; static struct wcd_mbhc_config *wcd_mbhc_cfg_ptr; +bool codec_reg_done; struct msm_asoc_wcd93xx_codec { void* (*get_afe_config_fn)(struct snd_soc_codec *codec, @@ -663,7 +664,7 @@ static void msm_ext_control(struct snd_soc_codec *codec) snd_soc_codec_get_dapm(codec); pr_debug("%s: msm_ext_spk_control = %d", __func__, msm_ext_spk_control); - if (msm_ext_spk_control == MSMFALCON_SPK_ON) { + if (msm_ext_spk_control == SDM660_SPK_ON) { snd_soc_dapm_enable_pin(dapm, "Lineout_1 amp"); snd_soc_dapm_enable_pin(dapm, "Lineout_3 amp"); } else { @@ -1281,7 +1282,7 @@ err_fail: return ret; } -static int msmfalcon_notifier_service_cb(struct notifier_block *this, +static int sdm660_notifier_service_cb(struct notifier_block *this, unsigned long opcode, void *ptr) { int ret; @@ -1339,7 +1340,7 @@ done: } static struct notifier_block service_nb = { - .notifier_call = msmfalcon_notifier_service_cb, + .notifier_call = sdm660_notifier_service_cb, .priority = -INT_MAX, }; @@ -1529,6 +1530,14 @@ int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) return ret; } + ret = snd_soc_add_codec_controls(codec, msm_common_snd_controls, + msm_common_snd_controls_size()); + if (ret < 0) { + pr_err("%s: add_common_snd_controls failed: %d\n", + __func__, ret); + return ret; + } + snd_soc_dapm_new_controls(dapm, msm_dapm_widgets, ARRAY_SIZE(msm_dapm_widgets)); @@ -1722,6 +1731,7 @@ int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) } } + codec_reg_done = true; done: return 0; @@ -1735,11 +1745,13 @@ EXPORT_SYMBOL(msm_audrx_init); /** * msm_ext_register_audio_notifier - register SSR notifier. */ -void msm_ext_register_audio_notifier(void) +void msm_ext_register_audio_notifier(struct platform_device *pdev) { int ret; - ret = audio_notifier_register("msmfalcon", AUDIO_NOTIFIER_ADSP_DOMAIN, + is_initial_boot = true; + spdev = pdev; + ret = audio_notifier_register("sdm660", AUDIO_NOTIFIER_ADSP_DOMAIN, &service_nb); if (ret < 0) pr_err("%s: Audio notifier register failed ret = %d\n", @@ -1777,10 +1789,8 @@ int msm_ext_cdc_init(struct platform_device *pdev, ret = -EPROBE_DEFER; goto err; } - spdev = pdev; platform_set_drvdata(pdev, *card); snd_soc_card_set_drvdata(*card, pdata); - is_initial_boot = true; pdata->hph_en1_gpio = of_get_named_gpio(pdev->dev.of_node, "qcom,hph-en1-gpio", 0); if (!gpio_is_valid(pdata->hph_en1_gpio)) diff --git a/sound/soc/msm/msmfalcon-external.h b/sound/soc/msm/sdm660-external.h index fc82b628dfac..7625a24e8fae 100644 --- a/sound/soc/msm/msmfalcon-external.h +++ b/sound/soc/msm/sdm660-external.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -10,8 +10,8 @@ * GNU General Public License for more details. */ -#ifndef __MSMFALCON_EXTERNAL -#define __MSMFALCON_EXTERNAL +#ifndef __SDM660_EXTERNAL +#define __SDM660_EXTERNAL int msm_snd_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params); @@ -33,7 +33,7 @@ int msm_ext_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, #ifdef CONFIG_SND_SOC_EXT_CODEC int msm_ext_cdc_init(struct platform_device *, struct msm_asoc_mach_data *, struct snd_soc_card **, struct wcd_mbhc_config *); -void msm_ext_register_audio_notifier(void); +void msm_ext_register_audio_notifier(struct platform_device *pdev); void msm_ext_cdc_deinit(void); #else inline int msm_ext_cdc_init(struct platform_device *pdev, @@ -44,7 +44,7 @@ inline int msm_ext_cdc_init(struct platform_device *pdev, return 0; } -inline void msm_ext_register_audio_notifier(void) +inline void msm_ext_register_audio_notifier(struct platform_device *pdev) { } inline void msm_ext_cdc_deinit(void) diff --git a/sound/soc/msm/msmfalcon-internal.c b/sound/soc/msm/sdm660-internal.c index 5226e791fcff..5d3ec356343e 100644 --- a/sound/soc/msm/msmfalcon-internal.c +++ b/sound/soc/msm/sdm660-internal.c @@ -16,12 +16,12 @@ #include <linux/mfd/msm-cdc-pinctrl.h> #include <sound/pcm_params.h> #include "qdsp6v2/msm-pcm-routing-v2.h" -#include "msmfalcon-common.h" -#include "../codecs/msmfalcon_cdc/msm-digital-cdc.h" -#include "../codecs/msmfalcon_cdc/msm-analog-cdc.h" +#include "sdm660-common.h" +#include "../codecs/sdm660_cdc/msm-digital-cdc.h" +#include "../codecs/sdm660_cdc/msm-analog-cdc.h" #include "../codecs/msm_sdw/msm_sdw.h" -#define __CHIPSET__ "MSMFALCON " +#define __CHIPSET__ "SDM660 " #define MSM_DAILINK_NAME(name) (__CHIPSET__#name) #define DEFAULT_MCLK_RATE 9600000 @@ -1300,8 +1300,20 @@ static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) pr_debug("%s(),dev_name%s\n", __func__, dev_name(cpu_dai->dev)); - snd_soc_add_codec_controls(ana_cdc, msm_snd_controls, + ret = snd_soc_add_codec_controls(ana_cdc, msm_snd_controls, ARRAY_SIZE(msm_snd_controls)); + if (ret < 0) { + pr_err("%s: add_codec_controls failed: %d\n", + __func__, ret); + return ret; + } + ret = snd_soc_add_codec_controls(ana_cdc, msm_common_snd_controls, + msm_common_snd_controls_size()); + if (ret < 0) { + pr_err("%s: add common snd controls failed: %d\n", + __func__, ret); + return ret; + } snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets, ARRAY_SIZE(msm_int_dapm_widgets)); @@ -2911,9 +2923,9 @@ ARRAY_SIZE(msm_mi2s_be_dai_links) + ARRAY_SIZE(msm_auxpcm_be_dai_links)+ ARRAY_SIZE(msm_wcn_be_dai_links)]; -static struct snd_soc_card msmfalcon_card = { - /* snd_soc_card_msmfalcon */ - .name = "msmfalcon-snd-card", +static struct snd_soc_card sdm660_card = { + /* snd_soc_card_sdm660 */ + .name = "sdm660-snd-card", .dai_link = msm_int_dai, .num_links = ARRAY_SIZE(msm_int_dai), }; @@ -2964,7 +2976,7 @@ static void msm_int_dt_parse_cap_info(struct platform_device *pdev, static struct snd_soc_card *msm_int_populate_sndcard_dailinks( struct device *dev) { - struct snd_soc_card *card = &msmfalcon_card; + struct snd_soc_card *card = &sdm660_card; struct snd_soc_dai_link *dailink; int len1; @@ -3033,7 +3045,7 @@ static int msm_internal_init(struct platform_device *pdev, AFE_API_VERSION_I2S_CONFIG; pdata->digital_cdc_core_clk.clk_id = Q6AFE_LPASS_CLK_ID_INT_MCLK_0; - pdata->digital_cdc_core_clk.clk_freq_in_hz = 0; + pdata->digital_cdc_core_clk.clk_freq_in_hz = pdata->mclk_freq; pdata->digital_cdc_core_clk.clk_attri = Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO; pdata->digital_cdc_core_clk.clk_root = diff --git a/sound/soc/msm/msmfalcon-internal.h b/sound/soc/msm/sdm660-internal.h index e5e3e7c66246..ccc62b8f33dc 100644 --- a/sound/soc/msm/msmfalcon-internal.h +++ b/sound/soc/msm/sdm660-internal.h @@ -10,8 +10,8 @@ * GNU General Public License for more details. */ -#ifndef __MSMFALCON_INTERNAL -#define __MSMFALCON_INTERNAL +#ifndef __SDM660_INTERNAL +#define __SDM660_INTERNAL #include <sound/soc.h> |