3 files changed, 477 insertions, 272 deletions

diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 0f39bf278cd4..51c85e08372c 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -31,9 +31,12 @@
 #include "clk-rcg.h"
 #include "clk-branch.h"
 #include "reset.h"
+#include "vdd-level-8996.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 
+static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner);
+
 enum {
 	P_XO,
 	P_GPLL0,
@@ -89,7 +92,7 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 static const char * const gcc_xo_gpll0_gpll4[] = {
 	"xo",
 	"gpll0",
-	"gpll4"
+	"gpll4_early"
 };
 
 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
@@ -128,7 +131,7 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
 static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
 	"xo",
 	"gpll0",
-	"gpll4",
+	"gpll4_early",
 	"gpll0_early_div"
 };
 
@@ -162,7 +165,7 @@ static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_d
 	"gpll0",
 	"gpll1_early_div",
 	"gpll1",
-	"gpll4",
+	"gpll4_early",
 	"gpll0_early_div"
 };
 
@@ -202,10 +205,24 @@ static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[]
 	"gpll2",
 	"gpll3",
 	"gpll1",
-	"gpll4",
+	"gpll4_early",
 	"gpll0_early_div"
 };
 
+static struct clk_fixed_factor gcc_ce1_ahb_m_clk = {
+	.hw.init = &(struct clk_init_data){
+		.name = "gcc_ce1_ahb_m_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
+static struct clk_fixed_factor gcc_ce1_axi_m_clk = {
+	.hw.init = &(struct clk_init_data){
+		.name = "gcc_ce1_axi_m_clk",
+		.ops = &clk_dummy_ops,
+	},
+};
+
 static struct clk_fixed_factor xo = {
 	.mult = 1,
 	.div = 1,
@@ -294,6 +311,8 @@ static struct clk_rcg2 usb30_master_clk_src = {
 		.parent_names = gcc_xo_gpll0_gpll0_early_div,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 60000000, LOW, 120000000,
+						NOMINAL, 150000000),
 	},
 };
 
@@ -312,6 +331,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 		.parent_names = gcc_xo_gpll0_gpll0_early_div,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 40000000, LOW, 60000000),
 	},
 };
 
@@ -330,6 +350,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
 		.parent_names = gcc_xo_sleep_clk,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP1(LOWER, 1200000),
 	},
 };
 
@@ -349,6 +370,8 @@ static struct clk_rcg2 usb20_master_clk_src = {
 		.parent_names = gcc_xo_gpll0_gpll0_early_div,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 60000000,
+						NOMINAL, 120000000),
 	},
 };
 
@@ -362,6 +385,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
 		.parent_names = gcc_xo_gpll0_gpll0_early_div,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 60000000),
 	},
 };
 
@@ -388,6 +412,8 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 200000000,
+						NOMINAL, 400000000),
 	},
 };
 
@@ -408,6 +434,8 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 150000000,
+						NOMINAL, 300000000),
 	},
 };
 
@@ -433,6 +461,8 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0_gpll4,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 100000000,
+						NOMINAL, 200000000),
 	},
 };
 
@@ -447,6 +477,8 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0_gpll4,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 100000000,
+						NOMINAL, 200000000),
 	},
 };
 
@@ -471,6 +503,8 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 50000000,
+						NOMINAL, 100000000),
 	},
 };
 
@@ -496,6 +530,8 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -515,6 +551,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -548,6 +585,8 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -562,6 +601,8 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -575,6 +616,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -589,6 +631,8 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -603,6 +647,8 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -616,6 +662,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -630,6 +677,8 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -644,6 +693,8 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -657,6 +708,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -671,6 +723,8 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -685,6 +739,8 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -698,6 +754,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -712,6 +769,8 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -726,6 +785,8 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -739,6 +800,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -753,6 +815,8 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -767,6 +831,8 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -780,6 +846,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -794,6 +861,8 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -808,6 +877,8 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -821,6 +892,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -835,6 +907,8 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -849,6 +923,8 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -862,6 +938,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -876,6 +953,8 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -890,6 +969,8 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -903,6 +984,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -917,6 +999,8 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -931,6 +1015,8 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -944,6 +1030,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -958,6 +1045,8 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -972,6 +1061,8 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 25000000,
+						NOMINAL, 50000000),
 	},
 };
 
@@ -985,6 +1076,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 50000000),
 	},
 };
 
@@ -999,6 +1091,8 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 31580000,
+						NOMINAL, 63160000),
 	},
 };
 
@@ -1017,6 +1111,7 @@ static struct clk_rcg2 pdm2_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 60000000),
 	},
 };
 
@@ -1036,6 +1131,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
 		.parent_names = gcc_xo_gpll0_aud_ref_clk,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP1(LOWER, 19200000),
 	},
 };
 
@@ -1082,6 +1178,8 @@ static struct clk_rcg2 gp1_clk_src = {
 		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
+						NOMINAL, 200000000),
 	},
 };
 
@@ -1096,6 +1194,8 @@ static struct clk_rcg2 gp2_clk_src = {
 		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
+						NOMINAL, 200000000),
 	},
 };
 
@@ -1110,6 +1210,8 @@ static struct clk_rcg2 gp3_clk_src = {
 		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000,
+						NOMINAL, 200000000),
 	},
 };
 
@@ -1129,6 +1231,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
 		.parent_names = gcc_xo_sleep_clk,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP1(LOWER, 1011000),
 	},
 };
 
@@ -1150,6 +1253,8 @@ static struct clk_rcg2 ufs_axi_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP4(LOWER, 19200000, LOW, 100000000,
+				NOMINAL, 200000000, HIGH, 240000000),
 	},
 };
 
@@ -1170,6 +1275,8 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
 		.parent_names = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 150000000,
+				NOMINAL, 300000000),
 	},
 };
 
@@ -1191,6 +1298,8 @@ static struct clk_rcg2 qspi_ser_clk_src = {
 		.parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
 		.num_parents = 6,
 		.ops = &clk_rcg2_ops,
+		VDD_DIG_FMAX_MAP3(LOWER, 80200000, LOW, 160400000,
+						NOMINAL, 320000000),
 	},
 };
 
@@ -1321,25 +1430,25 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
 	},
 };
 
-static struct clk_gate2 gcc_usb3_phy_pipe_clk = {
-	.udelay = 50,
+static struct clk_gate2 gpll0_out_msscc_clk = {
+	.udelay = 1,
 	.clkr = {
-		.enable_reg = 0x50004,
-		.enable_mask = BIT(0),
+		.enable_reg = 0x5200c,
+		.enable_mask = BIT(2),
 		.hw.init = &(struct clk_init_data){
-			.name = "gcc_usb3_phy_pipe_clk",
+			.name = "gpll0_out_msscc_clk",
 			.ops = &clk_gate2_ops,
 		},
 	},
 };
 
-static struct clk_gate2 gpll0_out_msscc = {
-	.udelay = 1,
+static struct clk_gate2 gcc_usb3_phy_pipe_clk = {
+	.udelay = 50,
 	.clkr = {
-		.enable_reg = 0x5200c,
-		.enable_mask = BIT(2),
+		.enable_reg = 0x50004,
+		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
-			.name = "gpll0_out_msscc",
+			.name = "gcc_usb3_phy_pipe_clk",
 			.ops = &clk_gate2_ops,
 		},
 	},
@@ -1826,6 +1935,7 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
 		.enable_mask = BIT(15),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_ahb_clk",
+			.flags = CLK_ENABLE_HAND_OFF,
 			.ops = &clk_branch2_ops,
 		},
 	},
@@ -2728,18 +2838,6 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
 	},
 };
 
-static struct clk_branch gcc_aggre1_pnoc_ahb_clk = {
-	.halt_reg = 0x82014,
-	.clkr = {
-		.enable_reg = 0x82014,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "gcc_aggre1_pnoc_ahb_clk",
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
 	.halt_reg = 0x83014,
 	.clkr = {
@@ -2995,11 +3093,13 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = {
 };
 
 static struct clk_hw *gcc_msm8996_hws[] = {
-	&xo.hw,
-	&gpll0_early_div.hw,
-	&ufs_tx_cfg_clk_src.hw,
-	&ufs_rx_cfg_clk_src.hw,
-	&ufs_ice_core_postdiv_clk_src.hw,
+	[GCC_XO] = &xo.hw,
+	[GCC_CE1_AHB_M_CLK] = &gcc_ce1_ahb_m_clk.hw,
+	[GCC_CE1_AXI_M_CLK] = &gcc_ce1_axi_m_clk.hw,
+	[GCC_GPLL0_EARLY_DIV] = &gpll0_early_div.hw,
+	[GCC_UFS_TX_CFG_CLK_SRC] = &ufs_tx_cfg_clk_src.hw,
+	[GCC_UFS_RX_CFG_CLK_SRC] = &ufs_rx_cfg_clk_src.hw,
+	[GCC_UFS_ICE_CORE_PDIV_CLK_SRC] = &ufs_ice_core_postdiv_clk_src.hw,
 };
 
 static struct clk_regmap *gcc_msm8996_clocks[] = {
@@ -3170,7 +3270,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
 	[GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
 	[GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
 	[GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
-	[GCC_AGGRE1_PNOC_AHB_CLK] = &gcc_aggre1_pnoc_ahb_clk.clkr,
 	[GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
 	[GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
 	[GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
@@ -3192,10 +3291,10 @@ static struct clk_regmap *gcc_msm8996_clocks[] = {
 	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
 	[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
 	[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
-	[GCC_DCC_AHB_ALK] = &gcc_dcc_ahb_clk.clkr,
+	[GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
 	[GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
 	[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
-	[GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr,
+	[GPLL0_OUT_MSSCC_CLK] = &gpll0_out_msscc_clk.clkr,
 };
 
 static const struct qcom_reset_map gcc_msm8996_resets[] = {
@@ -3317,6 +3416,8 @@ static const struct regmap_config gcc_msm8996_regmap_config = {
 static const struct qcom_cc_desc gcc_msm8996_desc = {
 	.config = &gcc_msm8996_regmap_config,
 	.clks = gcc_msm8996_clocks,
+	.hwclks = gcc_msm8996_hws,
+	.num_hwclks = ARRAY_SIZE(gcc_msm8996_hws),
 	.num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
 	.resets = gcc_msm8996_resets,
 	.num_resets = ARRAY_SIZE(gcc_msm8996_resets),
@@ -3330,9 +3431,7 @@ MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
 
 static int gcc_msm8996_probe(struct platform_device *pdev)
 {
-	struct clk *clk;
-	struct device *dev = &pdev->dev;
-	int i, ret = 0;
+	int ret = 0;
 	struct regmap *regmap;
 
 	regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
@@ -3342,10 +3441,14 @@ static int gcc_msm8996_probe(struct platform_device *pdev)
 	/* Set the HMSS_AHB_CLK_ENA bit to enable the hmss_ahb_clk */
 	regmap_update_bits(regmap, 0x52004, BIT(21), BIT(21));
 
-	for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
-		clk = devm_clk_register(dev, gcc_msm8996_hws[i]);
-		if (IS_ERR(clk))
-			return PTR_ERR(clk);
+	vdd_dig.vdd_uv[1] = RPM_REGULATOR_CORNER_SVS_KRAIT;
+
+	vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig");
+	if (IS_ERR(vdd_dig.regulator[0])) {
+		if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER))
+			dev_err(&pdev->dev,
+				"Unable to get vdd_dig regulator!");
+		return PTR_ERR(vdd_dig.regulator[0]);
 	}
 
 	ret = qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
@@ -3358,6 +3461,12 @@ static int gcc_msm8996_probe(struct platform_device *pdev)
 	/* This clock is used for all MMSS register access */
 	clk_prepare_enable(gcc_mmss_noc_cfg_ahb_clk.clkr.hw.clk);
 
+	/*
+	 * Keep the core memory settings enabled at all times for
+	 * gcc_mmss_bimc_gfx_clk.
+	 */
+	clk_set_flags(gcc_mmss_bimc_gfx_clk.clkr.hw.clk, CLKFLAG_RETAIN_MEM);
+
 	dev_info(&pdev->dev, "Registered GCC clocks\n");
 
 	return ret;
diff --git a/drivers/clk/qcom/vdd-level-8996.h b/drivers/clk/qcom/vdd-level-8996.h
new file mode 100644
index 000000000000..f93dd1638b1b
--- /dev/null
+++ b/drivers/clk/qcom/vdd-level-8996.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __QCOM_VDD_LEVEL_8996_H__
+#define __QCOM_VDD_LEVEL_8996_H__
+
+#include <linux/regulator/rpm-smd-regulator.h>
+#include <linux/regulator/consumer.h>
+
+#define VDD_DIG_FMAX_MAP1(l1, f1) \
+	.vdd_class = &vdd_dig,			\
+	.rate_max = (unsigned long[VDD_DIG_NUM]) {	\
+		[VDD_DIG_##l1] = (f1),		\
+	},					\
+	.num_rate_max = VDD_DIG_NUM
+
+#define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \
+	.vdd_class = &vdd_dig,			\
+	.rate_max = (unsigned long[VDD_DIG_NUM]) {	\
+		[VDD_DIG_##l1] = (f1),		\
+		[VDD_DIG_##l2] = (f2),		\
+	},					\
+	.num_rate_max = VDD_DIG_NUM
+
+#define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
+	.vdd_class = &vdd_dig,			\
+	.rate_max = (unsigned long[VDD_DIG_NUM]) {	\
+		[VDD_DIG_##l1] = (f1),		\
+		[VDD_DIG_##l2] = (f2),		\
+		[VDD_DIG_##l3] = (f3),		\
+	},					\
+	.num_rate_max = VDD_DIG_NUM
+
+#define VDD_DIG_FMAX_MAP4(l1, f1, l2, f2, l3, f3, l4, f4) \
+	.vdd_class = &vdd_dig,			\
+	.rate_max = (unsigned long[VDD_DIG_NUM]) {	\
+		[VDD_DIG_##l1] = (f1),		\
+		[VDD_DIG_##l2] = (f2),		\
+		[VDD_DIG_##l3] = (f3),		\
+		[VDD_DIG_##l4] = (f4),		\
+	},					\
+	.num_rate_max = VDD_DIG_NUM
+
+#define VDD_MMPLL4_FMAX_MAP1(l1, f1) \
+	.vdd_class = &vdd_mmpll4,		\
+	.rate_max = (unsigned long[VDD_DIG_NUM]) {	\
+		[VDD_DIG_##l1] = (f1),		\
+	},					\
+	.num_rate_max = VDD_DIG_NUM
+
+#define VDD_MMPLL4_FMAX_MAP2(l1, f1, l2, f2) \
+	.vdd_class = &vdd_mmpll4,		\
+	.rate_max = (unsigned long[VDD_DIG_NUM]) {	\
+		[VDD_DIG_##l1] = (f1),		\
+		[VDD_DIG_##l2] = (f2),		\
+	},					\
+	.num_rate_max = VDD_DIG_NUM
+
+#define VDD_MMPLL4_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \
+	.vdd_class = &vdd_mmpll4,		\
+	.rate_max = (unsigned long[VDD_DIG_NUM]) {	\
+		[VDD_DIG_##l1] = (f1),		\
+		[VDD_DIG_##l2] = (f2),		\
+		[VDD_DIG_##l3] = (f3),		\
+	},					\
+	.num_rate_max = VDD_DIG_NUM
+
+enum vdd_dig_levels {
+	VDD_DIG_NONE,
+	VDD_DIG_LOWER,		/* SVS2 */
+	VDD_DIG_LOW,		/* SVS */
+	VDD_DIG_NOMINAL,	/* NOMINAL */
+	VDD_DIG_HIGH,		/* Turbo */
+	VDD_DIG_NUM
+};
+
+static int vdd_corner[] = {
+	RPM_REGULATOR_CORNER_NONE,		/* VDD_DIG_NONE */
+	RPM_REGULATOR_CORNER_SVS_SOC,		/* SVS2 is remapped to SVS */
+	RPM_REGULATOR_CORNER_SVS_SOC,		/* VDD_DIG_SVS */
+	RPM_REGULATOR_CORNER_NORMAL,		/* VDD_DIG_NOMINAL */
+	RPM_REGULATOR_CORNER_SUPER_TURBO,	/* VDD_DIG_TURBO */
+};
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h
index f66264a2beb4..efed312fe914 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8996.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h
@@ -14,238 +14,239 @@
 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
 #define _DT_BINDINGS_CLK_MSM_GCC_8996_H
 
-#define GPLL0_EARLY						0
-#define GPLL0							1
-#define GPLL1_EARLY						2
-#define GPLL1							3
-#define GPLL2_EARLY						4
-#define GPLL2							5
-#define GPLL3_EARLY						6
-#define GPLL3							7
-#define GPLL4_EARLY						8
-#define GPLL4							9
-#define SYSTEM_NOC_CLK_SRC					10
-#define CONFIG_NOC_CLK_SRC					11
-#define PERIPH_NOC_CLK_SRC					12
-#define MMSS_BIMC_GFX_CLK_SRC					13
-#define USB30_MASTER_CLK_SRC					14
-#define USB30_MOCK_UTMI_CLK_SRC					15
-#define USB3_PHY_AUX_CLK_SRC					16
-#define USB20_MASTER_CLK_SRC					17
-#define USB20_MOCK_UTMI_CLK_SRC					18
-#define SDCC1_APPS_CLK_SRC					19
-#define SDCC1_ICE_CORE_CLK_SRC					20
-#define SDCC2_APPS_CLK_SRC					21
-#define SDCC3_APPS_CLK_SRC					22
-#define SDCC4_APPS_CLK_SRC					23
-#define BLSP1_QUP1_SPI_APPS_CLK_SRC				24
-#define BLSP1_QUP1_I2C_APPS_CLK_SRC				25
-#define BLSP1_UART1_APPS_CLK_SRC				26
-#define BLSP1_QUP2_SPI_APPS_CLK_SRC				27
-#define BLSP1_QUP2_I2C_APPS_CLK_SRC				28
-#define BLSP1_UART2_APPS_CLK_SRC				29
-#define BLSP1_QUP3_SPI_APPS_CLK_SRC				30
-#define BLSP1_QUP3_I2C_APPS_CLK_SRC				31
-#define BLSP1_UART3_APPS_CLK_SRC				32
-#define BLSP1_QUP4_SPI_APPS_CLK_SRC				33
-#define BLSP1_QUP4_I2C_APPS_CLK_SRC				34
-#define BLSP1_UART4_APPS_CLK_SRC				35
-#define BLSP1_QUP5_SPI_APPS_CLK_SRC				36
-#define BLSP1_QUP5_I2C_APPS_CLK_SRC				37
-#define BLSP1_UART5_APPS_CLK_SRC				38
-#define BLSP1_QUP6_SPI_APPS_CLK_SRC				39
-#define BLSP1_QUP6_I2C_APPS_CLK_SRC				40
-#define BLSP1_UART6_APPS_CLK_SRC				41
-#define BLSP2_QUP1_SPI_APPS_CLK_SRC				42
-#define BLSP2_QUP1_I2C_APPS_CLK_SRC				43
-#define BLSP2_UART1_APPS_CLK_SRC				44
-#define BLSP2_QUP2_SPI_APPS_CLK_SRC				45
-#define BLSP2_QUP2_I2C_APPS_CLK_SRC				46
-#define BLSP2_UART2_APPS_CLK_SRC				47
-#define BLSP2_QUP3_SPI_APPS_CLK_SRC				48
-#define BLSP2_QUP3_I2C_APPS_CLK_SRC				49
-#define BLSP2_UART3_APPS_CLK_SRC				50
-#define BLSP2_QUP4_SPI_APPS_CLK_SRC				51
-#define BLSP2_QUP4_I2C_APPS_CLK_SRC				52
-#define BLSP2_UART4_APPS_CLK_SRC				53
-#define BLSP2_QUP5_SPI_APPS_CLK_SRC				54
-#define BLSP2_QUP5_I2C_APPS_CLK_SRC				55
-#define BLSP2_UART5_APPS_CLK_SRC				56
-#define BLSP2_QUP6_SPI_APPS_CLK_SRC				57
-#define BLSP2_QUP6_I2C_APPS_CLK_SRC				58
-#define BLSP2_UART6_APPS_CLK_SRC				59
-#define PDM2_CLK_SRC						60
-#define TSIF_REF_CLK_SRC					61
-#define CE1_CLK_SRC						62
-#define GCC_SLEEP_CLK_SRC					63
-#define BIMC_CLK_SRC						64
-#define HMSS_AHB_CLK_SRC					65
-#define BIMC_HMSS_AXI_CLK_SRC					66
-#define HMSS_RBCPR_CLK_SRC					67
-#define HMSS_GPLL0_CLK_SRC					68
-#define GP1_CLK_SRC						69
-#define GP2_CLK_SRC						70
-#define GP3_CLK_SRC						71
-#define PCIE_AUX_CLK_SRC					72
-#define UFS_AXI_CLK_SRC						73
-#define UFS_ICE_CORE_CLK_SRC					74
-#define QSPI_SER_CLK_SRC					75
-#define GCC_SYS_NOC_AXI_CLK					76
-#define GCC_SYS_NOC_HMSS_AHB_CLK				77
-#define GCC_SNOC_CNOC_AHB_CLK					78
-#define GCC_SNOC_PNOC_AHB_CLK					79
-#define GCC_SYS_NOC_AT_CLK					80
-#define GCC_SYS_NOC_USB3_AXI_CLK				81
-#define GCC_SYS_NOC_UFS_AXI_CLK					82
-#define GCC_CFG_NOC_AHB_CLK					83
-#define GCC_PERIPH_NOC_AHB_CLK					84
-#define GCC_PERIPH_NOC_USB20_AHB_CLK				85
-#define GCC_TIC_CLK						86
-#define GCC_IMEM_AXI_CLK					87
-#define GCC_MMSS_SYS_NOC_AXI_CLK				88
-#define GCC_MMSS_NOC_CFG_AHB_CLK				89
-#define GCC_MMSS_BIMC_GFX_CLK					90
-#define GCC_USB30_MASTER_CLK					91
-#define GCC_USB30_SLEEP_CLK					92
-#define GCC_USB30_MOCK_UTMI_CLK					93
-#define GCC_USB3_PHY_AUX_CLK					94
-#define GCC_USB3_PHY_PIPE_CLK					95
-#define GCC_USB20_MASTER_CLK					96
-#define GCC_USB20_SLEEP_CLK					97
-#define GCC_USB20_MOCK_UTMI_CLK					98
-#define GCC_USB_PHY_CFG_AHB2PHY_CLK				99
-#define GCC_SDCC1_APPS_CLK					100
-#define GCC_SDCC1_AHB_CLK					101
-#define GCC_SDCC1_ICE_CORE_CLK					102
-#define GCC_SDCC2_APPS_CLK					103
-#define GCC_SDCC2_AHB_CLK					104
-#define GCC_SDCC3_APPS_CLK					105
-#define GCC_SDCC3_AHB_CLK					106
-#define GCC_SDCC4_APPS_CLK					107
-#define GCC_SDCC4_AHB_CLK					108
-#define GCC_BLSP1_AHB_CLK					109
-#define GCC_BLSP1_SLEEP_CLK					110
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK				111
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK				112
-#define GCC_BLSP1_UART1_APPS_CLK				113
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK				114
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK				115
-#define GCC_BLSP1_UART2_APPS_CLK				116
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK				117
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK				118
-#define GCC_BLSP1_UART3_APPS_CLK				119
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK				120
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK				121
-#define GCC_BLSP1_UART4_APPS_CLK				122
-#define GCC_BLSP1_QUP5_SPI_APPS_CLK				123
-#define GCC_BLSP1_QUP5_I2C_APPS_CLK				124
-#define GCC_BLSP1_UART5_APPS_CLK				125
-#define GCC_BLSP1_QUP6_SPI_APPS_CLK				126
-#define GCC_BLSP1_QUP6_I2C_APPS_CLK				127
-#define GCC_BLSP1_UART6_APPS_CLK				128
-#define GCC_BLSP2_AHB_CLK					129
-#define GCC_BLSP2_SLEEP_CLK					130
-#define GCC_BLSP2_QUP1_SPI_APPS_CLK				131
-#define GCC_BLSP2_QUP1_I2C_APPS_CLK				132
-#define GCC_BLSP2_UART1_APPS_CLK				133
-#define GCC_BLSP2_QUP2_SPI_APPS_CLK				134
-#define GCC_BLSP2_QUP2_I2C_APPS_CLK				135
-#define GCC_BLSP2_UART2_APPS_CLK				136
-#define GCC_BLSP2_QUP3_SPI_APPS_CLK				137
-#define GCC_BLSP2_QUP3_I2C_APPS_CLK				138
-#define GCC_BLSP2_UART3_APPS_CLK				139
-#define GCC_BLSP2_QUP4_SPI_APPS_CLK				140
-#define GCC_BLSP2_QUP4_I2C_APPS_CLK				141
-#define GCC_BLSP2_UART4_APPS_CLK				142
-#define GCC_BLSP2_QUP5_SPI_APPS_CLK				143
-#define GCC_BLSP2_QUP5_I2C_APPS_CLK				144
-#define GCC_BLSP2_UART5_APPS_CLK				145
-#define GCC_BLSP2_QUP6_SPI_APPS_CLK				146
-#define GCC_BLSP2_QUP6_I2C_APPS_CLK				147
-#define GCC_BLSP2_UART6_APPS_CLK				148
-#define GCC_PDM_AHB_CLK						149
-#define GCC_PDM_XO4_CLK						150
-#define GCC_PDM2_CLK						151
-#define GCC_PRNG_AHB_CLK					152
-#define GCC_TSIF_AHB_CLK					153
-#define GCC_TSIF_REF_CLK					154
-#define GCC_TSIF_INACTIVITY_TIMERS_CLK				155
-#define GCC_TCSR_AHB_CLK					156
-#define GCC_BOOT_ROM_AHB_CLK					157
-#define GCC_MSG_RAM_AHB_CLK					158
-#define GCC_TLMM_AHB_CLK					159
-#define GCC_TLMM_CLK						160
-#define GCC_MPM_AHB_CLK						161
-#define GCC_SPMI_SER_CLK					162
-#define GCC_SPMI_CNOC_AHB_CLK					163
-#define GCC_CE1_CLK						164
-#define GCC_CE1_AXI_CLK						165
-#define GCC_CE1_AHB_CLK						166
-#define GCC_BIMC_HMSS_AXI_CLK					167
-#define GCC_BIMC_GFX_CLK					168
-#define GCC_HMSS_AHB_CLK					169
-#define GCC_HMSS_SLV_AXI_CLK					170
-#define GCC_HMSS_MSTR_AXI_CLK					171
-#define GCC_HMSS_RBCPR_CLK					172
-#define GCC_GP1_CLK						173
-#define GCC_GP2_CLK						174
-#define GCC_GP3_CLK						175
-#define GCC_PCIE_0_SLV_AXI_CLK					176
-#define GCC_PCIE_0_MSTR_AXI_CLK					177
-#define GCC_PCIE_0_CFG_AHB_CLK					178
-#define GCC_PCIE_0_AUX_CLK					179
-#define GCC_PCIE_0_PIPE_CLK					180
-#define GCC_PCIE_1_SLV_AXI_CLK					181
-#define GCC_PCIE_1_MSTR_AXI_CLK					182
-#define GCC_PCIE_1_CFG_AHB_CLK					183
-#define GCC_PCIE_1_AUX_CLK					184
-#define GCC_PCIE_1_PIPE_CLK					185
-#define GCC_PCIE_2_SLV_AXI_CLK					186
-#define GCC_PCIE_2_MSTR_AXI_CLK					187
-#define GCC_PCIE_2_CFG_AHB_CLK					188
-#define GCC_PCIE_2_AUX_CLK					189
-#define GCC_PCIE_2_PIPE_CLK					190
-#define GCC_PCIE_PHY_CFG_AHB_CLK				191
-#define GCC_PCIE_PHY_AUX_CLK					192
-#define GCC_UFS_AXI_CLK						193
-#define GCC_UFS_AHB_CLK						194
-#define GCC_UFS_TX_CFG_CLK					195
-#define GCC_UFS_RX_CFG_CLK					196
-#define GCC_UFS_TX_SYMBOL_0_CLK					197
-#define GCC_UFS_RX_SYMBOL_0_CLK					198
-#define GCC_UFS_RX_SYMBOL_1_CLK					199
-#define GCC_UFS_UNIPRO_CORE_CLK					200
-#define GCC_UFS_ICE_CORE_CLK					201
-#define GCC_UFS_SYS_CLK_CORE_CLK				202
-#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK				203
-#define GCC_AGGRE0_SNOC_AXI_CLK					204
-#define GCC_AGGRE0_CNOC_AHB_CLK					205
-#define GCC_SMMU_AGGRE0_AXI_CLK					206
-#define GCC_SMMU_AGGRE0_AHB_CLK					207
-#define GCC_AGGRE1_PNOC_AHB_CLK					208
-#define GCC_AGGRE2_UFS_AXI_CLK					209
-#define GCC_AGGRE2_USB3_AXI_CLK					210
-#define GCC_QSPI_AHB_CLK					211
-#define GCC_QSPI_SER_CLK					212
-#define GCC_USB3_CLKREF_CLK					213
-#define GCC_HDMI_CLKREF_CLK					214
-#define GCC_UFS_CLKREF_CLK					215
-#define GCC_PCIE_CLKREF_CLK					216
-#define GCC_RX2_USB2_CLKREF_CLK					217
-#define GCC_RX1_USB2_CLKREF_CLK					218
-#define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CLK			219
-#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK			220
-#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK			221
-#define GCC_EDP_CLKREF_CLK					222
-#define GCC_MSS_CFG_AHB_CLK					223
-#define GCC_MSS_Q6_BIMC_AXI_CLK					224
-#define GCC_MSS_SNOC_AXI_CLK					225
-#define GCC_MSS_MNOC_BIMC_AXI_CLK				226
-#define GCC_DCC_AHB_ALK						227
-#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK				228
-#define GCC_MMSS_GPLL0_DIV_CLK					229
-#define GPLL0_OUT_MSSCC						230
+/* Hardware/Dummy/Voter clocks */
+#define GCC_XO							0
+#define GCC_CE1_AHB_M_CLK					1
+#define GCC_CE1_AXI_M_CLK					2
+#define GCC_GPLL0_EARLY_DIV					3
+#define GCC_UFS_TX_CFG_CLK_SRC					4
+#define GCC_UFS_RX_CFG_CLK_SRC					5
+#define GCC_UFS_ICE_CORE_PDIV_CLK_SRC				6
 
+/* RCGs and Branches */
+#define GPLL0_EARLY						7
+#define GPLL0							8
+#define GPLL4_EARLY						9
+#define GPLL4							10
+#define SYSTEM_NOC_CLK_SRC					11
+#define CONFIG_NOC_CLK_SRC					12
+#define PERIPH_NOC_CLK_SRC					13
+#define MMSS_BIMC_GFX_CLK_SRC					14
+#define USB30_MASTER_CLK_SRC					15
+#define USB30_MOCK_UTMI_CLK_SRC					16
+#define USB3_PHY_AUX_CLK_SRC					17
+#define USB20_MASTER_CLK_SRC					18
+#define USB20_MOCK_UTMI_CLK_SRC					19
+#define SDCC1_APPS_CLK_SRC					20
+#define SDCC1_ICE_CORE_CLK_SRC					21
+#define SDCC2_APPS_CLK_SRC					22
+#define SDCC3_APPS_CLK_SRC					23
+#define SDCC4_APPS_CLK_SRC					24
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC				25
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC				26
+#define BLSP1_UART1_APPS_CLK_SRC				27
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC				28
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC				29
+#define BLSP1_UART2_APPS_CLK_SRC				30
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC				31
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC				32
+#define BLSP1_UART3_APPS_CLK_SRC				33
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC				34
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC				35
+#define BLSP1_UART4_APPS_CLK_SRC				36
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC				37
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC				38
+#define BLSP1_UART5_APPS_CLK_SRC				39
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC				40
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC				41
+#define BLSP1_UART6_APPS_CLK_SRC				42
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC				43
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC				44
+#define BLSP2_UART1_APPS_CLK_SRC				45
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC				46
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC				47
+#define BLSP2_UART2_APPS_CLK_SRC				48
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC				49
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC				50
+#define BLSP2_UART3_APPS_CLK_SRC				51
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC				52
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC				53
+#define BLSP2_UART4_APPS_CLK_SRC				54
+#define BLSP2_QUP5_SPI_APPS_CLK_SRC				55
+#define BLSP2_QUP5_I2C_APPS_CLK_SRC				56
+#define BLSP2_UART5_APPS_CLK_SRC				57
+#define BLSP2_QUP6_SPI_APPS_CLK_SRC				58
+#define BLSP2_QUP6_I2C_APPS_CLK_SRC				59
+#define BLSP2_UART6_APPS_CLK_SRC				60
+#define PDM2_CLK_SRC						61
+#define TSIF_REF_CLK_SRC					62
+#define CE1_CLK_SRC						63
+#define GCC_SLEEP_CLK_SRC					64
+#define BIMC_CLK_SRC						65
+#define HMSS_AHB_CLK_SRC					66
+#define BIMC_HMSS_AXI_CLK_SRC					67
+#define HMSS_RBCPR_CLK_SRC					68
+#define HMSS_GPLL0_CLK_SRC					69
+#define GP1_CLK_SRC						70
+#define GP2_CLK_SRC						71
+#define GP3_CLK_SRC						72
+#define PCIE_AUX_CLK_SRC					73
+#define UFS_AXI_CLK_SRC						74
+#define UFS_ICE_CORE_CLK_SRC					75
+#define QSPI_SER_CLK_SRC					76
+#define GCC_SYS_NOC_AXI_CLK					77
+#define GCC_SYS_NOC_HMSS_AHB_CLK				78
+#define GCC_SNOC_CNOC_AHB_CLK					79
+#define GCC_SNOC_PNOC_AHB_CLK					80
+#define GCC_SYS_NOC_AT_CLK					81
+#define GCC_SYS_NOC_USB3_AXI_CLK				82
+#define GCC_SYS_NOC_UFS_AXI_CLK					83
+#define GCC_CFG_NOC_AHB_CLK					84
+#define GCC_PERIPH_NOC_AHB_CLK					85
+#define GCC_PERIPH_NOC_USB20_AHB_CLK				86
+#define GCC_TIC_CLK						87
+#define GCC_IMEM_AXI_CLK					88
+#define GCC_MMSS_SYS_NOC_AXI_CLK				89
+#define GCC_MMSS_NOC_CFG_AHB_CLK				90
+#define GCC_MMSS_BIMC_GFX_CLK					91
+#define GCC_USB30_MASTER_CLK					92
+#define GCC_USB30_SLEEP_CLK					93
+#define GCC_USB30_MOCK_UTMI_CLK					94
+#define GCC_USB3_PHY_AUX_CLK					95
+#define GCC_USB3_PHY_PIPE_CLK					96
+#define GCC_USB20_MASTER_CLK					97
+#define GCC_USB20_SLEEP_CLK					98
+#define GCC_USB20_MOCK_UTMI_CLK					99
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK				100
+#define GCC_SDCC1_APPS_CLK					101
+#define GCC_SDCC1_AHB_CLK					102
+#define GCC_SDCC1_ICE_CORE_CLK					103
+#define GCC_SDCC2_APPS_CLK					104
+#define GCC_SDCC2_AHB_CLK					105
+#define GCC_SDCC3_APPS_CLK					106
+#define GCC_SDCC3_AHB_CLK					107
+#define GCC_SDCC4_APPS_CLK					108
+#define GCC_SDCC4_AHB_CLK					109
+#define GCC_BLSP1_AHB_CLK					110
+#define GCC_BLSP1_SLEEP_CLK					111
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK				112
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK				113
+#define GCC_BLSP1_UART1_APPS_CLK				114
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK				115
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK				116
+#define GCC_BLSP1_UART2_APPS_CLK				117
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK				118
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK				119
+#define GCC_BLSP1_UART3_APPS_CLK				120
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK				121
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK				122
+#define GCC_BLSP1_UART4_APPS_CLK				123
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK				124
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK				125
+#define GCC_BLSP1_UART5_APPS_CLK				126
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK				127
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK				128
+#define GCC_BLSP1_UART6_APPS_CLK				129
+#define GCC_BLSP2_AHB_CLK					130
+#define GCC_BLSP2_SLEEP_CLK					131
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK				132
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK				133
+#define GCC_BLSP2_UART1_APPS_CLK				134
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK				135
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK				136
+#define GCC_BLSP2_UART2_APPS_CLK				137
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK				138
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK				139
+#define GCC_BLSP2_UART3_APPS_CLK				140
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK				141
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK				142
+#define GCC_BLSP2_UART4_APPS_CLK				143
+#define GCC_BLSP2_QUP5_SPI_APPS_CLK				144
+#define GCC_BLSP2_QUP5_I2C_APPS_CLK				145
+#define GCC_BLSP2_UART5_APPS_CLK				146
+#define GCC_BLSP2_QUP6_SPI_APPS_CLK				147
+#define GCC_BLSP2_QUP6_I2C_APPS_CLK				148
+#define GCC_BLSP2_UART6_APPS_CLK				149
+#define GCC_PDM_AHB_CLK						150
+#define GCC_PDM_XO4_CLK						151
+#define GCC_PDM2_CLK						152
+#define GCC_PRNG_AHB_CLK					153
+#define GCC_TSIF_AHB_CLK					154
+#define GCC_TSIF_REF_CLK					155
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK				156
+#define GCC_TCSR_AHB_CLK					157
+#define GCC_BOOT_ROM_AHB_CLK					158
+#define GCC_MSG_RAM_AHB_CLK					159
+#define GCC_TLMM_AHB_CLK					160
+#define GCC_TLMM_CLK						161
+#define GCC_MPM_AHB_CLK						162
+#define GCC_SPMI_SER_CLK					163
+#define GCC_SPMI_CNOC_AHB_CLK					164
+#define GCC_BIMC_HMSS_AXI_CLK					165
+#define GCC_BIMC_GFX_CLK					166
+#define GCC_HMSS_AHB_CLK					167
+#define GCC_HMSS_SLV_AXI_CLK					168
+#define GCC_HMSS_MSTR_AXI_CLK					169
+#define GCC_HMSS_RBCPR_CLK					170
+#define GCC_GP1_CLK						171
+#define GCC_GP2_CLK						172
+#define GCC_GP3_CLK						173
+#define GCC_PCIE_0_SLV_AXI_CLK					174
+#define GCC_PCIE_0_MSTR_AXI_CLK					175
+#define GCC_PCIE_0_CFG_AHB_CLK					176
+#define GCC_PCIE_0_AUX_CLK					177
+#define GCC_PCIE_0_PIPE_CLK					178
+#define GCC_PCIE_1_SLV_AXI_CLK					179
+#define GCC_PCIE_1_MSTR_AXI_CLK					180
+#define GCC_PCIE_1_CFG_AHB_CLK					181
+#define GCC_PCIE_1_AUX_CLK					182
+#define GCC_PCIE_1_PIPE_CLK					183
+#define GCC_PCIE_2_SLV_AXI_CLK					184
+#define GCC_PCIE_2_MSTR_AXI_CLK					185
+#define GCC_PCIE_2_CFG_AHB_CLK					186
+#define GCC_PCIE_2_AUX_CLK					187
+#define GCC_PCIE_2_PIPE_CLK					188
+#define GCC_PCIE_PHY_CFG_AHB_CLK				189
+#define GCC_PCIE_PHY_AUX_CLK					190
+#define GCC_UFS_AXI_CLK						191
+#define GCC_UFS_AHB_CLK						192
+#define GCC_UFS_TX_CFG_CLK					193
+#define GCC_UFS_RX_CFG_CLK					194
+#define GCC_UFS_TX_SYMBOL_0_CLK					195
+#define GCC_UFS_RX_SYMBOL_0_CLK					196
+#define GCC_UFS_RX_SYMBOL_1_CLK					197
+#define GCC_UFS_UNIPRO_CORE_CLK					198
+#define GCC_UFS_ICE_CORE_CLK					199
+#define GCC_UFS_SYS_CLK_CORE_CLK				200
+#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK				201
+#define GCC_AGGRE0_SNOC_AXI_CLK					202
+#define GCC_AGGRE0_CNOC_AHB_CLK					203
+#define GCC_SMMU_AGGRE0_AXI_CLK					204
+#define GCC_SMMU_AGGRE0_AHB_CLK					205
+#define GCC_AGGRE2_UFS_AXI_CLK					206
+#define GCC_AGGRE2_USB3_AXI_CLK					207
+#define GCC_QSPI_AHB_CLK					208
+#define GCC_QSPI_SER_CLK					209
+#define GCC_USB3_CLKREF_CLK					210
+#define GCC_HDMI_CLKREF_CLK					211
+#define GCC_UFS_CLKREF_CLK					212
+#define GCC_PCIE_CLKREF_CLK					213
+#define GCC_RX2_USB2_CLKREF_CLK					214
+#define GCC_RX1_USB2_CLKREF_CLK					215
+#define GCC_AGGRE0_NOC_QOSGEN_EXTREF_CLK			216
+#define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK			217
+#define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK			218
+#define GCC_EDP_CLKREF_CLK					219
+#define GCC_MSS_CFG_AHB_CLK					220
+#define GCC_MSS_Q6_BIMC_AXI_CLK					221
+#define GCC_MSS_SNOC_AXI_CLK					222
+#define GCC_MSS_MNOC_BIMC_AXI_CLK				223
+#define GCC_DCC_AHB_CLK						224
+#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK				225
+#define GCC_MMSS_GPLL0_DIV_CLK					226
+#define GPLL0_OUT_MSSCC_CLK					227
+
+/* Block resets */
 #define GCC_SYSTEM_NOC_BCR					0
 #define GCC_CONFIG_NOC_BCR					1
 #define GCC_PERIPH_NOC_BCR					2