diff options
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,gpucc.txt | 13 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/sdm660-gpu.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/sdm660-regulator.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/sdm660.dtsi | 9 | ||||
| -rw-r--r-- | drivers/clk/qcom/gpucc-sdm660.c | 90 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,gpu-sdm660.h | 42 |
6 files changed, 123 insertions, 37 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt index 12e0164a8bcc..2f8fb22439f9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -5,7 +5,8 @@ Required properties : - compatible : shall contain only one of the following: "qcom,gpucc-sdm660", - "qcom,gpucc-sdm630" + "qcom,gpucc-sdm630", + "qcom,gpu-sdm660", - reg : shall contain base register location and length - #clock-cells : shall contain 1 @@ -17,7 +18,15 @@ Optional properties : Example: clock-controller@4000000 { compatible = "qcom,gpucc-sdm660"; - reg = <<0x5065000 0x10000>; + reg = <0x5065000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpu-clock-controller@4000000 { + compatible = "qcom,gpu-sdm660"; + reg = <0x5065000 0x10000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi b/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi index 5c11131b9ddf..e3a3835ae809 100644 --- a/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-gpu.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -76,7 +76,7 @@ <&clock_gfx GPUCC_RBBMTIMER_CLK>, <&clock_gcc GCC_GPU_BIMC_GFX_CLK>, <&clock_gcc GCC_GPU_BIMC_GFX_SRC_CLK>, - <&clock_gfx GPUCC_RBCPR_CLK>; + <&clock_gpu GPUCC_RBCPR_CLK>; clock-names = "core_clk", "iface_clk", "rbbmtimer_clk", "mem_clk", "mem_iface_clk", "rbcpr_clk"; diff --git a/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi b/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi index 479a9fdd91ca..c00595934cf0 100644 --- a/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi @@ -532,7 +532,7 @@ compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator"; reg = <0x05061000 0x4000>, <0x00784000 0x1000>; reg-names = "cpr_ctrl", "fuse_base"; - clocks = <&clock_gfx GPUCC_RBCPR_CLK>, + clocks = <&clock_gpu GPUCC_RBCPR_CLK>, <&clock_rpmcc RPM_CNOC_CLK>; clock-names = "core_clk", "bus_clk"; interrupts = <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>; diff --git a/arch/arm/boot/dts/qcom/sdm660.dtsi b/arch/arm/boot/dts/qcom/sdm660.dtsi index 54aa729352a3..4a13675a07bb 100644 --- a/arch/arm/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm/boot/dts/qcom/sdm660.dtsi @@ -906,7 +906,14 @@ #reset-cells = <1>; }; - clock_gfx: clock-controller@5065000 { + clock_gpu: clock-controller@5065000 { + compatible = "qcom,gpu-sdm660"; + reg = <0x5065000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + clock_gfx: gfx@5065000 { compatible = "qcom,gpucc-sdm660"; reg = <0x5065000 0x10000>; vdd_dig_gfx-supply = <&pm660l_s3_level>; diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c index fee5e73a1f88..0f7ec18e477a 100644 --- a/drivers/clk/qcom/gpucc-sdm660.c +++ b/drivers/clk/qcom/gpucc-sdm660.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -247,9 +247,6 @@ static struct clk_rcg2 rbcpr_clk_src = { .parent_names = gpucc_parent_names_0, .num_parents = 4, .ops = &clk_rcg2_ops, - VDD_DIG_FMAX_MAP2( - MIN, 19200000, - NOMINAL, 50000000), }, }; @@ -317,15 +314,13 @@ static struct clk_branch gpucc_rbcpr_clk = { }; static struct clk_regmap *gpucc_660_clocks[] = { - [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, [GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr, [GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr, - [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr, + [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, [GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr, [GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr, - [GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr, [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, - [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, + [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr, }; static const struct regmap_config gpucc_660_regmap_config = { @@ -411,13 +406,25 @@ static int gpucc_660_probe(struct platform_device *pdev) { int ret = 0; struct regmap *regmap; + struct resource *res; + void __iomem *base; bool is_630 = 0; - regmap = qcom_cc_map(pdev, &gpucc_660_desc); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "Failed to get resources\n"); + return -EINVAL; + } + + base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, gpucc_660_desc.config); if (IS_ERR(regmap)) return PTR_ERR(regmap); - /* CX Regulator for RBBMTimer and RBCPR clock */ + /* CX Regulator for RBBMTimer clock */ vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_gfx"); if (IS_ERR(vdd_dig.regulator[0])) { if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) @@ -489,10 +496,71 @@ static int __init gpucc_660_init(void) { return platform_driver_register(&gpucc_660_driver); } -core_initcall_sync(gpucc_660_init); +arch_initcall(gpucc_660_init); static void __exit gpucc_660_exit(void) { platform_driver_unregister(&gpucc_660_driver); } module_exit(gpucc_660_exit); + +/* GPU RBCPR Clocks */ +static struct clk_regmap *gpucc_rbcpr_660_clocks[] = { + [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, + [GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr, +}; + +static const struct qcom_cc_desc gpu_660_desc = { + .config = &gpucc_660_regmap_config, + .clks = gpucc_rbcpr_660_clocks, + .num_clks = ARRAY_SIZE(gpucc_rbcpr_660_clocks), +}; + +static const struct of_device_id gpucc_rbcpr_660_match_table[] = { + { .compatible = "qcom,gpu-sdm660" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpucc_rbcpr_660_match_table); + +static int gpu_660_probe(struct platform_device *pdev) +{ + int ret = 0; + + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_660_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ret = qcom_cc_really_probe(pdev, &gpu_660_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register GPU RBCPR clocks\n"); + return ret; + } + + + dev_info(&pdev->dev, "Registered GPU RBCPR clocks\n"); + + return ret; +} + +static struct platform_driver gpu_660_driver = { + .probe = gpu_660_probe, + .driver = { + .name = "gpu-sdm660", + .of_match_table = gpucc_rbcpr_660_match_table, + }, +}; + +static int __init gpu_660_init(void) +{ + return platform_driver_register(&gpu_660_driver); +} +core_initcall(gpu_660_init); + +static void __exit gpu_660_exit(void) +{ + platform_driver_unregister(&gpu_660_driver); +} +module_exit(gpu_660_exit); + diff --git a/include/dt-bindings/clock/qcom,gpu-sdm660.h b/include/dt-bindings/clock/qcom,gpu-sdm660.h index 80b49d3420e3..fd5328c056b8 100644 --- a/include/dt-bindings/clock/qcom,gpu-sdm660.h +++ b/include/dt-bindings/clock/qcom,gpu-sdm660.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,25 +14,27 @@ #ifndef _DT_BINDINGS_CLK_MSM_GPU_660_H #define _DT_BINDINGS_CLK_MSM_GPU_660_H -#define GFX3D_CLK_SRC 0 -#define GPU_PLL0_PLL 1 -#define GPU_PLL0_PLL_OUT_AUX 2 -#define GPU_PLL0_PLL_OUT_AUX2 3 -#define GPU_PLL0_PLL_OUT_EARLY 4 -#define GPU_PLL0_PLL_OUT_MAIN 5 -#define GPU_PLL0_PLL_OUT_TEST 6 -#define GPU_PLL1_PLL 7 -#define GPU_PLL1_PLL_OUT_AUX 8 -#define GPU_PLL1_PLL_OUT_AUX2 9 -#define GPU_PLL1_PLL_OUT_EARLY 10 -#define GPU_PLL1_PLL_OUT_MAIN 11 -#define GPU_PLL1_PLL_OUT_TEST 12 -#define GPUCC_CXO_CLK 13 -#define GPUCC_GFX3D_CLK 14 -#define GPUCC_RBBMTIMER_CLK 15 -#define GPUCC_RBCPR_CLK 16 -#define RBBMTIMER_CLK_SRC 17 -#define RBCPR_CLK_SRC 18 +#define GPU_PLL0_PLL 0 +#define GPU_PLL0_PLL_OUT_AUX 1 +#define GPU_PLL0_PLL_OUT_AUX2 2 +#define GPU_PLL0_PLL_OUT_EARLY 3 +#define GPU_PLL0_PLL_OUT_MAIN 4 +#define GPU_PLL0_PLL_OUT_TEST 5 +#define GPU_PLL1_PLL 6 +#define GPU_PLL1_PLL_OUT_AUX 7 +#define GPU_PLL1_PLL_OUT_AUX2 8 +#define GPU_PLL1_PLL_OUT_EARLY 9 +#define GPU_PLL1_PLL_OUT_MAIN 10 +#define GPU_PLL1_PLL_OUT_TEST 11 +#define GFX3D_CLK_SRC 12 +#define GPUCC_GFX3D_CLK 13 +#define GPUCC_RBBMTIMER_CLK 14 +#define RBBMTIMER_CLK_SRC 15 +#define GPUCC_CXO_CLK 16 + +/* RBCPR GPUCC clocks */ +#define RBCPR_CLK_SRC 0 +#define GPUCC_RBCPR_CLK 1 #define GPU_CX_GDSC 0 #define GPU_GX_GDSC 1 |