diff options
| -rw-r--r-- | drivers/clk/qcom/mmcc-msm8996.c | 729 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,mmcc-msm8996.h | 485 |
2 files changed, 557 insertions, 657 deletions
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c index 2af5c1a1d7ca..51faccc7c26c 100644 --- a/drivers/clk/qcom/mmcc-msm8996.c +++ b/drivers/clk/qcom/mmcc-msm8996.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -31,11 +31,25 @@ #include "clk-alpha-pll.h" #include "clk-rcg.h" #include "clk-branch.h" +#include "clk-voter.h" #include "reset.h" #include "gdsc.h" +#include "vdd-level-8996.h" #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); + +static int vdd_mmpll4_levels[] = { + RPM_REGULATOR_CORNER_NONE, 0, + RPM_REGULATOR_CORNER_SVS_KRAIT, 1800000, + RPM_REGULATOR_CORNER_SVS_SOC, 1800000, + RPM_REGULATOR_CORNER_NORMAL, 1800000, + RPM_REGULATOR_CORNER_SUPER_TURBO, 1800000, +}; + +static DEFINE_VDD_REGULATORS(vdd_mmpll4, VDD_DIG_NUM, 2, vdd_mmpll4_levels); + enum { P_XO, P_MMPLL0, @@ -73,8 +87,8 @@ static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { static const char * const mmss_xo_dsi0pll_dsi1pll[] = { "xo", - "dsi0pll", - "dsi1pll" + "dsi0pll_pixel_clk_mux", + "dsi1pll_pixel_clk_mux" }; static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { @@ -97,8 +111,8 @@ static const struct parent_map mmss_xo_dsibyte_map[] = { static const char * const mmss_xo_dsibyte[] = { "xo", - "dsi0pllbyte", - "dsi1pllbyte" + "dsi0pll_byte_clk_mux", + "dsi1pll_byte_clk_mux" }; static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { @@ -265,6 +279,18 @@ static struct pll_vco mmpll_t_vco[] = { { 500000000, 1500000000, 0 }, }; +/* Initial configuration for 800MHz rate */ +static const struct pll_config mmpll0_config = { + .l = 0x29, + .config_ctl_val = 0x4001051b, + .alpha = 0xaaaaab00, + .alpha_u = 0xaa, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + static struct clk_alpha_pll mmpll0_early = { .offset = 0x0, .vco_table = mmpll_p_vco, @@ -277,6 +303,7 @@ static struct clk_alpha_pll mmpll0_early = { .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_ops, + VDD_DIG_FMAX_MAP2(LOWER, 400000000, NOMINAL, 800000000), }, }, }; @@ -293,6 +320,18 @@ static struct clk_alpha_pll_postdiv mmpll0 = { }, }; +/* Initial configuration for 810MHz rate */ +static const struct pll_config mmpll1_config = { + .l = 0x2a, + .config_ctl_val = 0x4001051b, + .alpha = 0x00, + .alpha_u = 0x30, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + static struct clk_alpha_pll mmpll1_early = { .offset = 0x30, .vco_table = mmpll_p_vco, @@ -305,6 +344,7 @@ static struct clk_alpha_pll mmpll1_early = { .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_ops, + VDD_DIG_FMAX_MAP2(LOWER, 405000000, NOMINAL, 810000000), } }, }; @@ -321,6 +361,18 @@ static struct clk_alpha_pll_postdiv mmpll1 = { }, }; +/* Initial configuration for 400MHz rate */ +static const struct pll_config mmpll2_config = { + .l = 0x14, + .config_ctl_val = 0x4001051b, + .alpha = 0x55555600, + .alpha_u = 0xd5, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + static struct clk_alpha_pll mmpll2_early = { .offset = 0x4100, .vco_table = mmpll_gfx_vco, @@ -330,6 +382,7 @@ static struct clk_alpha_pll mmpll2_early = { .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_ops, + VDD_DIG_FMAX_MAP1(LOWER, 1000000000), }, }; @@ -345,6 +398,18 @@ static struct clk_alpha_pll_postdiv mmpll2 = { }, }; +/* Initial configuration for 1040MHz rate */ +static const struct pll_config mmpll3_config = { + .l = 0x36, + .config_ctl_val = 0x4001051b, + .alpha = 0xaaaaab00, + .alpha_u = 0x2a, + .alpha_en_mask = BIT(24), + .vco_val = 0x1 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + static struct clk_alpha_pll mmpll3_early = { .offset = 0x60, .vco_table = mmpll_p_vco, @@ -354,6 +419,7 @@ static struct clk_alpha_pll mmpll3_early = { .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_ops, + VDD_DIG_FMAX_MAP2(LOWER, 520000000, NOMINAL, 1040000000), }, }; @@ -369,6 +435,18 @@ static struct clk_alpha_pll_postdiv mmpll3 = { }, }; +/* Initial configuration for 960MHz rate */ +static const struct pll_config mmpll4_config = { + .l = 0x32, + .config_ctl_val = 0x4289, + .alpha = 0x00, + .alpha_u = 0x00, + .alpha_en_mask = BIT(24), + .vco_val = 0x0 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + static struct clk_alpha_pll mmpll4_early = { .offset = 0x90, .vco_table = mmpll_t_vco, @@ -378,6 +456,7 @@ static struct clk_alpha_pll mmpll4_early = { .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_ops, + VDD_DIG_FMAX_MAP2(LOWER, 480000000, NOMINAL, 960000000), }, }; @@ -393,6 +472,18 @@ static struct clk_alpha_pll_postdiv mmpll4 = { }, }; +/* Initial configuration for 825MHz rate */ +static const struct pll_config mmpll5_config = { + .l = 0x2a, + .config_ctl_val = 0x4001051b, + .alpha = 0x00, + .alpha_u = 0xf8, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + static struct clk_alpha_pll mmpll5_early = { .offset = 0xc0, .vco_table = mmpll_p_vco, @@ -402,6 +493,7 @@ static struct clk_alpha_pll mmpll5_early = { .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_ops, + VDD_DIG_FMAX_MAP2(LOWER, 412500000, LOW, 825000000), }, }; @@ -417,6 +509,18 @@ static struct clk_alpha_pll_postdiv mmpll5 = { }, }; +/* Initial configuration for 532MHz rate */ +static const struct pll_config mmpll8_config = { + .l = 0x1b, + .config_ctl_val = 0x4001051b, + .alpha = 0x55555600, + .alpha_u = 0xb5, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + static struct clk_alpha_pll mmpll8_early = { .offset = 0x4130, .vco_table = mmpll_gfx_vco, @@ -426,6 +530,7 @@ static struct clk_alpha_pll mmpll8_early = { .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_ops, + VDD_DIG_FMAX_MAP1(LOWER, 1000000000), }, }; @@ -441,15 +546,30 @@ static struct clk_alpha_pll_postdiv mmpll8 = { }, }; +/* Initial configuration for 1248MHz rate */ +static const struct pll_config mmpll9_config = { + .l = 0x41, + .config_ctl_val = 0x4289, + .alpha = 0x00, + .alpha_u = 0x00, + .alpha_en_mask = BIT(24), + .vco_val = 0x0 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + static struct clk_alpha_pll mmpll9_early = { .offset = 0x4200, .vco_table = mmpll_t_vco, .num_vco = ARRAY_SIZE(mmpll_t_vco), + .flags = SUPPORTS_DYNAMIC_UPDATE, + .min_supported_freq = 1248000000, .clkr.hw.init = &(struct clk_init_data){ .name = "mmpll9_early", .parent_names = (const char *[]){ "xo" }, .num_parents = 1, .ops = &clk_alpha_pll_ops, + VDD_DIG_FMAX_MAP2(LOWER, 652000000, NOMINAL, 1305600000), }, }; @@ -482,6 +602,7 @@ static struct clk_rcg2 ahb_clk_src = { .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, .num_parents = 4, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2(LOWER, 40000000, NOMINAL, 80000000), }, }; @@ -489,26 +610,13 @@ static const struct freq_tbl ftbl_axi_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(75000000, P_GPLL0_DIV, 4, 0, 0), F(100000000, P_GPLL0, 6, 0, 0), - F(171430000, P_GPLL0, 3.5, 0, 0), + F(171428571, P_GPLL0, 3.5, 0, 0), F(200000000, P_GPLL0, 3, 0, 0), F(320000000, P_MMPLL0, 2.5, 0, 0), - F(400000000, P_MMPLL0, 2, 0, 0), + F(405000000, P_MMPLL1, 2, 0, 0), { } }; -static struct clk_rcg2 axi_clk_src = { - .cmd_rcgr = 0x5040, - .hid_width = 5, - .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, - .freq_tbl = ftbl_axi_clk_src, - .clkr.hw.init = &(struct clk_init_data){ - .name = "axi_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, - .num_parents = 5, - .ops = &clk_rcg2_ops, - }, -}; - static struct clk_rcg2 maxi_clk_src = { .cmd_rcgr = 0x5090, .hid_width = 5, @@ -519,6 +627,8 @@ static struct clk_rcg2 maxi_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 171430000, + NOMINAL, 320000000, HIGH, 405000000), }, }; @@ -526,11 +636,13 @@ static struct clk_rcg2 gfx3d_clk_src = { .cmd_rcgr = 0x4000, .hid_width = 5, .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map, + .flags = FORCE_ENABLE_RCGR, .clkr.hw.init = &(struct clk_init_data){ .name = "gfx3d_clk_src", .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0, .num_parents = 6, .ops = &clk_gfx3d_ops, + .vdd_class = &vdd_gfx, .flags = CLK_SET_RATE_PARENT, }, }; @@ -550,18 +662,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = { .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, .num_parents = 4, .ops = &clk_rcg2_ops, - }, -}; - -static struct clk_rcg2 isense_clk_src = { - .cmd_rcgr = 0x4010, - .hid_width = 5, - .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map, - .clkr.hw.init = &(struct clk_init_data){ - .name = "isense_clk_src", - .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div, - .num_parents = 7, - .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1(LOWER, 19200000), }, }; @@ -580,7 +681,9 @@ static struct clk_rcg2 rbcpr_clk_src = { .name = "rbcpr_clk_src", .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div, .num_parents = 4, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2(LOWER, 19200000, NOMINAL, 50000000), }, }; @@ -603,6 +706,8 @@ static struct clk_rcg2 video_core_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 150000000, + NOMINAL, 346666667, HIGH, 520000000), }, }; @@ -617,6 +722,8 @@ static struct clk_rcg2 video_subcore0_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 150000000, + NOMINAL, 346666667, HIGH, 520000000), }, }; @@ -631,6 +738,8 @@ static struct clk_rcg2 video_subcore1_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 150000000, + NOMINAL, 346666667, HIGH, 520000000), }, }; @@ -645,6 +754,8 @@ static struct clk_rcg2 pclk0_clk_src = { .num_parents = 3, .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, + VDD_DIG_FMAX_MAP3(LOWER, 175000000, LOW, 280000000, + NOMINAL, 350000000), }, }; @@ -659,6 +770,8 @@ static struct clk_rcg2 pclk1_clk_src = { .num_parents = 3, .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, + VDD_DIG_FMAX_MAP3(LOWER, 175000000, LOW, 280000000, + NOMINAL, 350000000), }, }; @@ -685,6 +798,8 @@ static struct clk_rcg2 mdp_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 171430000, LOW, 275000000, + NOMINAL, 330000000, HIGH, 412500000), }, }; @@ -704,6 +819,8 @@ static struct clk_rcg2 extpclk_clk_src = { .num_parents = 2, .ops = &clk_byte_ops, .flags = CLK_SET_RATE_PARENT, + VDD_DIG_FMAX_MAP3(LOWER, 150000000, LOW, 300000000, + NOMINAL, 600000000), }, }; @@ -722,6 +839,7 @@ static struct clk_rcg2 vsync_clk_src = { .parent_names = mmss_xo_gpll0_gpll0_div, .num_parents = 3, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1(LOWER, 19200000), }, }; @@ -740,6 +858,7 @@ static struct clk_rcg2 hdmi_clk_src = { .parent_names = mmss_xo_gpll0_gpll0_div, .num_parents = 3, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1(LOWER, 19200000), }, }; @@ -753,6 +872,8 @@ static struct clk_rcg2 byte0_clk_src = { .num_parents = 3, .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, + VDD_DIG_FMAX_MAP3(LOWER, 131250000, LOW, 210000000, + NOMINAL, 262500000), }, }; @@ -766,6 +887,8 @@ static struct clk_rcg2 byte1_clk_src = { .num_parents = 3, .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, + VDD_DIG_FMAX_MAP3(LOWER, 131250000, LOW, 210000000, + NOMINAL, 262500000), }, }; @@ -784,6 +907,7 @@ static struct clk_rcg2 esc0_clk_src = { .parent_names = mmss_xo_dsibyte, .num_parents = 3, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1(LOWER, 19200000), }, }; @@ -797,6 +921,7 @@ static struct clk_rcg2 esc1_clk_src = { .parent_names = mmss_xo_dsibyte, .num_parents = 3, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1(LOWER, 19200000), }, }; @@ -821,6 +946,8 @@ static struct clk_rcg2 camss_gp0_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000, + NOMINAL, 200000000), }, }; @@ -835,6 +962,8 @@ static struct clk_rcg2 camss_gp1_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3(LOWER, 50000000, LOW, 100000000, + NOMINAL, 200000000), }, }; @@ -863,6 +992,8 @@ static struct clk_rcg2 mclk0_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68570000), }, }; @@ -877,6 +1008,8 @@ static struct clk_rcg2 mclk1_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68570000), }, }; @@ -891,6 +1024,8 @@ static struct clk_rcg2 mclk2_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68570000), }, }; @@ -905,6 +1040,8 @@ static struct clk_rcg2 mclk3_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3(LOWER, 33333333, LOW, 66666667, + NOMINAL, 68570000), }, }; @@ -927,6 +1064,8 @@ static struct clk_rcg2 cci_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3(LOWER, 19200000, LOW, 50000000, + NOMINAL, 100000000), }, }; @@ -947,6 +1086,8 @@ static struct clk_rcg2 csi0phytimer_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000, + NOMINAL, 266666667), }, }; @@ -960,6 +1101,8 @@ static struct clk_rcg2 csi1phytimer_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000, + NOMINAL, 266666667), }, }; @@ -973,6 +1116,8 @@ static struct clk_rcg2 csi2phytimer_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000, + NOMINAL, 266666667), }, }; @@ -994,6 +1139,8 @@ static struct clk_rcg2 csiphy0_3p_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000, + NOMINAL, 320000000, HIGH, 384000000), }, }; @@ -1007,6 +1154,8 @@ static struct clk_rcg2 csiphy1_3p_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000, + NOMINAL, 320000000, HIGH, 384000000), }, }; @@ -1020,6 +1169,8 @@ static struct clk_rcg2 csiphy2_3p_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000, + NOMINAL, 320000000, HIGH, 384000000), }, }; @@ -1043,6 +1194,8 @@ static struct clk_rcg2 jpeg0_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 150000000, + NOMINAL, 320000000, HIGH, 480000000), }, }; @@ -1065,6 +1218,8 @@ static struct clk_rcg2 jpeg2_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 150000000, + NOMINAL, 266666667, HIGH, 320000000), }, }; @@ -1078,6 +1233,8 @@ static struct clk_rcg2 jpeg_dma_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 75000000, LOW, 150000000, + NOMINAL, 320000000, HIGH, 480000000), }, }; @@ -1101,6 +1258,8 @@ static struct clk_rcg2 vfe0_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 300000000, + NOMINAL, 480000000, HIGH, 600000000), }, }; @@ -1114,6 +1273,8 @@ static struct clk_rcg2 vfe1_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 300000000, + NOMINAL, 480000000, HIGH, 600000000), }, }; @@ -1136,6 +1297,8 @@ static struct clk_rcg2 cpp_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000, + NOMINAL, 480000000, HIGH, 640000000), }, }; @@ -1143,6 +1306,7 @@ static const struct freq_tbl ftbl_csi0_clk_src[] = { F(100000000, P_GPLL0_DIV, 3, 0, 0), F(200000000, P_GPLL0, 3, 0, 0), F(266666667, P_MMPLL0, 3, 0, 0), + F(320000000, P_MMPLL4, 3, 0, 0), F(480000000, P_MMPLL4, 2, 0, 0), F(600000000, P_GPLL0, 1, 0, 0), { } @@ -1158,6 +1322,8 @@ static struct clk_rcg2 csi0_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000, + NOMINAL, 480000000, HIGH, 600000000), }, }; @@ -1171,6 +1337,8 @@ static struct clk_rcg2 csi1_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000, + NOMINAL, 480000000, HIGH, 600000000), }, }; @@ -1184,6 +1352,8 @@ static struct clk_rcg2 csi2_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000, + NOMINAL, 480000000, HIGH, 600000000), }, }; @@ -1197,6 +1367,8 @@ static struct clk_rcg2 csi3_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div, .num_parents = 7, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4(LOWER, 100000000, LOW, 200000000, + NOMINAL, 480000000, HIGH, 600000000), }, }; @@ -1217,11 +1389,14 @@ static struct clk_rcg2 fd_core_clk_src = { .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div, .num_parents = 5, .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 200000000, + NOMINAL, 400000000), }, }; static struct clk_branch mmss_mmagic_ahb_clk = { .halt_reg = 0x5024, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x5024, .enable_mask = BIT(0), @@ -1229,7 +1404,6 @@ static struct clk_branch mmss_mmagic_ahb_clk = { .name = "mmss_mmagic_ahb_clk", .parent_names = (const char *[]){ "ahb_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, .ops = &clk_branch2_ops, }, }, @@ -1237,14 +1411,16 @@ static struct clk_branch mmss_mmagic_ahb_clk = { static struct clk_branch mmss_mmagic_cfg_ahb_clk = { .halt_reg = 0x5054, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x5054, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_mmagic_cfg_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1257,9 +1433,10 @@ static struct clk_branch mmss_misc_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_misc_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1279,21 +1456,6 @@ static struct clk_branch mmss_misc_cxo_clk = { }, }; -static struct clk_branch mmss_mmagic_axi_clk = { - .halt_reg = 0x506c, - .clkr = { - .enable_reg = 0x506c, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmss_mmagic_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch mmss_mmagic_maxi_clk = { .halt_reg = 0x5074, .clkr = { @@ -1316,9 +1478,6 @@ static struct clk_branch mmagic_camss_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_camss_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1331,9 +1490,6 @@ static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_camss_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1341,14 +1497,16 @@ static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = { static struct clk_branch smmu_vfe_ahb_clk = { .halt_reg = 0x3c04, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x3c04, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_vfe_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1356,14 +1514,12 @@ static struct clk_branch smmu_vfe_ahb_clk = { static struct clk_branch smmu_vfe_axi_clk = { .halt_reg = 0x3c08, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x3c08, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_vfe_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1371,14 +1527,16 @@ static struct clk_branch smmu_vfe_axi_clk = { static struct clk_branch smmu_cpp_ahb_clk = { .halt_reg = 0x3c14, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x3c14, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_cpp_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1386,14 +1544,12 @@ static struct clk_branch smmu_cpp_ahb_clk = { static struct clk_branch smmu_cpp_axi_clk = { .halt_reg = 0x3c18, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x3c18, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_cpp_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1401,14 +1557,16 @@ static struct clk_branch smmu_cpp_axi_clk = { static struct clk_branch smmu_jpeg_ahb_clk = { .halt_reg = 0x3c24, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x3c24, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_jpeg_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1416,14 +1574,12 @@ static struct clk_branch smmu_jpeg_ahb_clk = { static struct clk_branch smmu_jpeg_axi_clk = { .halt_reg = 0x3c28, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x3c28, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_jpeg_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1436,9 +1592,7 @@ static struct clk_branch mmagic_mdss_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_mdss_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_ENABLE_HAND_OFF, .ops = &clk_branch2_ops, }, }, @@ -1451,9 +1605,7 @@ static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_mdss_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_ENABLE_HAND_OFF, .ops = &clk_branch2_ops, }, }, @@ -1461,14 +1613,16 @@ static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = { static struct clk_branch smmu_rot_ahb_clk = { .halt_reg = 0x2444, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x2444, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_rot_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1476,14 +1630,12 @@ static struct clk_branch smmu_rot_ahb_clk = { static struct clk_branch smmu_rot_axi_clk = { .halt_reg = 0x2448, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x2448, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_rot_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1491,14 +1643,17 @@ static struct clk_branch smmu_rot_axi_clk = { static struct clk_branch smmu_mdp_ahb_clk = { .halt_reg = 0x2454, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x2454, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_mdp_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, + .flags = CLK_ENABLE_HAND_OFF, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1506,14 +1661,13 @@ static struct clk_branch smmu_mdp_ahb_clk = { static struct clk_branch smmu_mdp_axi_clk = { .halt_reg = 0x2458, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x2458, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_mdp_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_ENABLE_HAND_OFF, .ops = &clk_branch2_ops, }, }, @@ -1526,9 +1680,6 @@ static struct clk_branch mmagic_video_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_video_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1541,9 +1692,6 @@ static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_video_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1551,14 +1699,16 @@ static struct clk_branch mmagic_video_noc_cfg_ahb_clk = { static struct clk_branch smmu_video_ahb_clk = { .halt_reg = 0x1174, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x1174, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_video_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1566,29 +1716,12 @@ static struct clk_branch smmu_video_ahb_clk = { static struct clk_branch smmu_video_axi_clk = { .halt_reg = 0x1178, + .halt_check = BRANCH_VOTED, .clkr = { .enable_reg = 0x1178, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "smmu_video_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch mmagic_bimc_axi_clk = { - .halt_reg = 0x5294, - .clkr = { - .enable_reg = 0x5294, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmagic_bimc_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1601,9 +1734,6 @@ static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmagic_bimc_noc_cfg_ahb_clk", - .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1678,7 +1808,6 @@ static struct clk_branch vmem_maxi_clk = { .name = "vmem_maxi_clk", .parent_names = (const char *[]){ "maxi_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1691,9 +1820,10 @@ static struct clk_branch vmem_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "vmem_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1721,9 +1851,10 @@ static struct clk_branch mmss_rbcpr_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mmss_rbcpr_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1751,9 +1882,6 @@ static struct clk_branch video_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1768,7 +1896,6 @@ static struct clk_branch video_maxi_clk = { .name = "video_maxi_clk", .parent_names = (const char *[]){ "maxi_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1781,9 +1908,10 @@ static struct clk_branch video_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "video_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1826,9 +1954,11 @@ static struct clk_branch mdss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, + .flags = CLK_ENABLE_HAND_OFF, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1843,7 +1973,6 @@ static struct clk_branch mdss_hdmi_ahb_clk = { .name = "mdss_hdmi_ahb_clk", .parent_names = (const char *[]){ "ahb_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1856,9 +1985,6 @@ static struct clk_branch mdss_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "mdss_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -1903,12 +2029,15 @@ static struct clk_branch mdss_mdp_clk = { .name = "mdss_mdp_clk", .parent_names = (const char *[]){ "mdp_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_ENABLE_HAND_OFF, .ops = &clk_branch2_ops, }, }, }; +static DEFINE_CLK_VOTER(mdss_mdp_vote_clk, mdss_mdp_clk, 0); +static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, mdss_mdp_clk, 0); + static struct clk_branch mdss_extpclk_clk = { .halt_reg = 0x2324, .clkr = { @@ -2021,9 +2150,6 @@ static struct clk_branch camss_top_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_top_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2036,9 +2162,10 @@ static struct clk_branch camss_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, + .parent_names = (const char *[]){ + "mmss_mmagic_ahb_clk" + }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2051,9 +2178,6 @@ static struct clk_branch camss_micro_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_micro_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2171,9 +2295,6 @@ static struct clk_branch camss_cci_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cci_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2321,9 +2442,6 @@ static struct clk_branch camss_jpeg_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2336,9 +2454,6 @@ static struct clk_branch camss_jpeg_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_jpeg_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2351,9 +2466,6 @@ static struct clk_branch camss_vfe_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2366,9 +2478,6 @@ static struct clk_branch camss_vfe_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2398,7 +2507,6 @@ static struct clk_branch camss_vfe0_stream_clk = { .name = "camss_vfe0_stream_clk", .parent_names = (const char *[]){ "vfe0_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2411,9 +2519,6 @@ static struct clk_branch camss_vfe0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe0_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2443,7 +2548,6 @@ static struct clk_branch camss_vfe1_stream_clk = { .name = "camss_vfe1_stream_clk", .parent_names = (const char *[]){ "vfe1_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2456,9 +2560,6 @@ static struct clk_branch camss_vfe1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_vfe1_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2473,7 +2574,6 @@ static struct clk_branch camss_csi_vfe0_clk = { .name = "camss_csi_vfe0_clk", .parent_names = (const char *[]){ "vfe0_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2488,7 +2588,6 @@ static struct clk_branch camss_csi_vfe1_clk = { .name = "camss_csi_vfe1_clk", .parent_names = (const char *[]){ "vfe1_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2501,9 +2600,6 @@ static struct clk_branch camss_cpp_vbif_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cpp_vbif_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2516,9 +2612,6 @@ static struct clk_branch camss_cpp_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cpp_axi_clk", - .parent_names = (const char *[]){ "axi_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2546,9 +2639,6 @@ static struct clk_branch camss_cpp_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_cpp_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2576,9 +2666,6 @@ static struct clk_branch camss_csi0_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi0_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2593,7 +2680,6 @@ static struct clk_branch camss_csi0phy_clk = { .name = "camss_csi0phy_clk", .parent_names = (const char *[]){ "csi0_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2608,7 +2694,6 @@ static struct clk_branch camss_csi0rdi_clk = { .name = "camss_csi0rdi_clk", .parent_names = (const char *[]){ "csi0_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2623,7 +2708,6 @@ static struct clk_branch camss_csi0pix_clk = { .name = "camss_csi0pix_clk", .parent_names = (const char *[]){ "csi0_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2651,9 +2735,6 @@ static struct clk_branch camss_csi1_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi1_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2668,7 +2749,6 @@ static struct clk_branch camss_csi1phy_clk = { .name = "camss_csi1phy_clk", .parent_names = (const char *[]){ "csi1_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2683,7 +2763,6 @@ static struct clk_branch camss_csi1rdi_clk = { .name = "camss_csi1rdi_clk", .parent_names = (const char *[]){ "csi1_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2698,7 +2777,6 @@ static struct clk_branch camss_csi1pix_clk = { .name = "camss_csi1pix_clk", .parent_names = (const char *[]){ "csi1_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2726,9 +2804,6 @@ static struct clk_branch camss_csi2_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi2_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2743,7 +2818,6 @@ static struct clk_branch camss_csi2phy_clk = { .name = "camss_csi2phy_clk", .parent_names = (const char *[]){ "csi2_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2758,7 +2832,6 @@ static struct clk_branch camss_csi2rdi_clk = { .name = "camss_csi2rdi_clk", .parent_names = (const char *[]){ "csi2_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2773,7 +2846,6 @@ static struct clk_branch camss_csi2pix_clk = { .name = "camss_csi2pix_clk", .parent_names = (const char *[]){ "csi2_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2801,9 +2873,6 @@ static struct clk_branch camss_csi3_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_csi3_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2818,7 +2887,6 @@ static struct clk_branch camss_csi3phy_clk = { .name = "camss_csi3phy_clk", .parent_names = (const char *[]){ "csi3_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2833,7 +2901,6 @@ static struct clk_branch camss_csi3rdi_clk = { .name = "camss_csi3rdi_clk", .parent_names = (const char *[]){ "csi3_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2848,7 +2915,6 @@ static struct clk_branch camss_csi3pix_clk = { .name = "camss_csi3pix_clk", .parent_names = (const char *[]){ "csi3_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2861,9 +2927,6 @@ static struct clk_branch camss_ispif_ahb_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "camss_ispif_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -2893,175 +2956,27 @@ static struct clk_branch fd_core_uar_clk = { .name = "fd_core_uar_clk", .parent_names = (const char *[]){ "fd_core_clk_src" }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch fd_ahb_clk = { - .halt_reg = 0x3ba74, + .halt_reg = 0x3b74, .clkr = { - .enable_reg = 0x3ba74, + .enable_reg = 0x3b74, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "fd_ahb_clk", - .parent_names = (const char *[]){ "ahb_clk_src" }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_hw *mmcc_msm8996_hws[] = { - &gpll0_div.hw, -}; - -static struct gdsc mmagic_bimc_gdsc = { - .gdscr = 0x529c, - .pd = { - .name = "mmagic_bimc", - }, - .pwrsts = PWRSTS_OFF_ON, -}; - -static struct gdsc mmagic_video_gdsc = { - .gdscr = 0x119c, - .gds_hw_ctrl = 0x120c, - .pd = { - .name = "mmagic_video", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, -}; - -static struct gdsc mmagic_mdss_gdsc = { - .gdscr = 0x247c, - .gds_hw_ctrl = 0x2480, - .pd = { - .name = "mmagic_mdss", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, -}; - -static struct gdsc mmagic_camss_gdsc = { - .gdscr = 0x3c4c, - .gds_hw_ctrl = 0x3c50, - .pd = { - .name = "mmagic_camss", - }, - .pwrsts = PWRSTS_OFF_ON, - .flags = VOTABLE, -}; - -static struct gdsc venus_gdsc = { - .gdscr = 0x1024, - .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 }, - .cxc_count = 3, - .pd = { - .name = "venus", - }, - .parent = &mmagic_video_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, -}; - -static struct gdsc venus_core0_gdsc = { - .gdscr = 0x1040, - .cxcs = (unsigned int []){ 0x1048 }, - .cxc_count = 1, - .pd = { - .name = "venus_core0", - }, - .pwrsts = PWRSTS_OFF_ON, -}; - -static struct gdsc venus_core1_gdsc = { - .gdscr = 0x1044, - .cxcs = (unsigned int []){ 0x104c }, - .cxc_count = 1, - .pd = { - .name = "venus_core1", - }, - .pwrsts = PWRSTS_OFF_ON, -}; - -static struct gdsc camss_gdsc = { - .gdscr = 0x34a0, - .cxcs = (unsigned int []){ 0x36bc, 0x36c4 }, - .cxc_count = 2, - .pd = { - .name = "camss", - }, - .parent = &mmagic_camss_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, -}; - -static struct gdsc vfe0_gdsc = { - .gdscr = 0x3664, - .cxcs = (unsigned int []){ 0x36a8 }, - .cxc_count = 1, - .pd = { - .name = "vfe0", - }, - .parent = &camss_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, -}; - -static struct gdsc vfe1_gdsc = { - .gdscr = 0x3674, - .cxcs = (unsigned int []){ 0x36ac }, - .cxc_count = 1, - .pd = { - .name = "vfe0", - }, - .parent = &camss_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, -}; - -static struct gdsc jpeg_gdsc = { - .gdscr = 0x35a4, - .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 }, - .cxc_count = 4, - .pd = { - .name = "jpeg", - }, - .parent = &camss_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, -}; - -static struct gdsc cpp_gdsc = { - .gdscr = 0x36d4, - .cxcs = (unsigned int []){ 0x36b0 }, - .cxc_count = 1, - .pd = { - .name = "cpp", - }, - .parent = &camss_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, -}; - -static struct gdsc fd_gdsc = { - .gdscr = 0x3b64, - .cxcs = (unsigned int []){ 0x3b68, 0x3b6c }, - .cxc_count = 2, - .pd = { - .name = "fd", - }, - .parent = &camss_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, -}; - -static struct gdsc mdss_gdsc = { - .gdscr = 0x2304, - .cxcs = (unsigned int []){ 0x2310, 0x231c }, - .cxc_count = 2, - .pd = { - .name = "mdss", - }, - .parent = &mmagic_mdss_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, + [GPLL0_DIV] = &gpll0_div.hw, + [MDSS_MDP_VOTE_CLK] = &mdss_mdp_vote_clk.hw, + [MDSS_ROTATOR_VOTE_CLK] = &mdss_rotator_vote_clk.hw, }; static struct clk_regmap *mmcc_msm8996_clocks[] = { @@ -3082,11 +2997,9 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = { [MMPLL9_EARLY] = &mmpll9_early.clkr, [MMPLL9_PLL] = &mmpll9.clkr, [AHB_CLK_SRC] = &ahb_clk_src.clkr, - [AXI_CLK_SRC] = &axi_clk_src.clkr, [MAXI_CLK_SRC] = &maxi_clk_src.clkr, [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr, - [ISENSE_CLK_SRC] = &isense_clk_src.clkr, [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr, [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr, @@ -3129,7 +3042,6 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = { [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr, [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, - [MMSS_MMAGIC_AXI_CLK] = &mmss_mmagic_axi_clk.clkr, [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr, [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr, [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr, @@ -3149,7 +3061,6 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = { [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr, [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr, [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr, - [MMAGIC_BIMC_AXI_CLK] = &mmagic_bimc_axi_clk.clkr, [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr, [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr, [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr, @@ -3240,23 +3151,6 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = { [FD_AHB_CLK] = &fd_ahb_clk.clkr, }; -static struct gdsc *mmcc_msm8996_gdscs[] = { - [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc, - [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc, - [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc, - [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc, - [VENUS_GDSC] = &venus_gdsc, - [VENUS_CORE0_GDSC] = &venus_core0_gdsc, - [VENUS_CORE1_GDSC] = &venus_core1_gdsc, - [CAMSS_GDSC] = &camss_gdsc, - [VFE0_GDSC] = &vfe0_gdsc, - [VFE1_GDSC] = &vfe1_gdsc, - [JPEG_GDSC] = &jpeg_gdsc, - [CPP_GDSC] = &cpp_gdsc, - [FD_GDSC] = &fd_gdsc, - [MDSS_GDSC] = &mdss_gdsc, -}; - static const struct qcom_reset_map mmcc_msm8996_resets[] = { [MMAGICAHB_BCR] = { 0x5020 }, [MMAGIC_CFG_BCR] = { 0x5050 }, @@ -3321,21 +3215,21 @@ static const struct qcom_reset_map mmcc_msm8996_resets[] = { }; static const struct regmap_config mmcc_msm8996_regmap_config = { - .reg_bits = 32, - .reg_stride = 4, - .val_bits = 32, - .max_register = 0xb008, - .fast_io = true, + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xb008, + .fast_io = true, }; static const struct qcom_cc_desc mmcc_msm8996_desc = { .config = &mmcc_msm8996_regmap_config, .clks = mmcc_msm8996_clocks, + .hwclks = mmcc_msm8996_hws, + .num_hwclks = ARRAY_SIZE(mmcc_msm8996_hws), .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks), .resets = mmcc_msm8996_resets, .num_resets = ARRAY_SIZE(mmcc_msm8996_resets), - .gdscs = mmcc_msm8996_gdscs, - .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs), }; static const struct of_device_id mmcc_msm8996_match_table[] = { @@ -3346,10 +3240,9 @@ MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table); static int mmcc_msm8996_probe(struct platform_device *pdev) { - struct clk *clk; - struct device *dev = &pdev->dev; - int i; struct regmap *regmap; + struct regulator *reg; + int ret = 0; regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc); if (IS_ERR(regmap)) @@ -3360,13 +3253,48 @@ static int mmcc_msm8996_probe(struct platform_device *pdev) /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */ regmap_update_bits(regmap, 0x5054, BIT(15), 0); - for (i = 0; i < ARRAY_SIZE(mmcc_msm8996_hws); i++) { - clk = devm_clk_register(dev, mmcc_msm8996_hws[i]); - if (IS_ERR(clk)) - return PTR_ERR(clk); + vdd_dig.vdd_uv[1] = RPM_REGULATOR_CORNER_SVS_KRAIT; + reg = vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); + if (IS_ERR(reg)) { + if (PTR_ERR(reg) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get vdd_dig regulator!"); + return PTR_ERR(reg); + } + + reg = vdd_mmpll4.regulator[0] = devm_regulator_get(&pdev->dev, + "mmpll4_dig"); + if (IS_ERR(reg)) { + if (PTR_ERR(reg) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get mmpll4_dig regulator!"); + return PTR_ERR(reg); + } + + reg = vdd_mmpll4.regulator[1] = devm_regulator_get(&pdev->dev, + "mmpll4_analog"); + if (IS_ERR(reg)) { + if (PTR_ERR(reg) != -EPROBE_DEFER) + dev_err(&pdev->dev, "Unable to get mmpll4_analog regulator!"); + return PTR_ERR(reg); + } + + clk_alpha_pll_configure(&mmpll0_early, regmap, &mmpll0_config); + clk_alpha_pll_configure(&mmpll1_early, regmap, &mmpll1_config); + clk_alpha_pll_configure(&mmpll2_early, regmap, &mmpll2_config); + clk_alpha_pll_configure(&mmpll3_early, regmap, &mmpll3_config); + clk_alpha_pll_configure(&mmpll4_early, regmap, &mmpll4_config); + clk_alpha_pll_configure(&mmpll5_early, regmap, &mmpll5_config); + clk_alpha_pll_configure(&mmpll8_early, regmap, &mmpll8_config); + clk_alpha_pll_configure(&mmpll9_early, regmap, &mmpll9_config); + + ret = qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register MMCC clocks\n"); + return ret; } - return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap); + dev_info(&pdev->dev, "Registered MMCC clocks\n"); + + return ret; } static struct platform_driver mmcc_msm8996_driver = { @@ -3376,7 +3304,18 @@ static struct platform_driver mmcc_msm8996_driver = { .of_match_table = mmcc_msm8996_match_table, }, }; -module_platform_driver(mmcc_msm8996_driver); + +static int __init msm_mmcc_8996_init(void) +{ + return platform_driver_register(&mmcc_msm8996_driver); +} +arch_initcall(msm_mmcc_8996_init); + +static void __exit mmcc_msm8996_exit(void) +{ + platform_driver_unregister(&mmcc_msm8996_driver); +} +module_exit(mmcc_msm8996_exit); MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver"); MODULE_LICENSE("GPL v2"); diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8996.h b/include/dt-bindings/clock/qcom,mmcc-msm8996.h index f924b92b0188..436badbaad7d 100644 --- a/include/dt-bindings/clock/qcom,mmcc-msm8996.h +++ b/include/dt-bindings/clock/qcom,mmcc-msm8996.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -14,213 +14,177 @@ #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H #define _DT_BINDINGS_CLK_MSM_MMCC_8996_H -#define MMPLL0_EARLY 0 -#define MMPLL0_PLL 1 -#define MMPLL1_EARLY 2 -#define MMPLL1_PLL 3 -#define MMPLL2_EARLY 4 -#define MMPLL2_PLL 5 -#define MMPLL3_EARLY 6 -#define MMPLL3_PLL 7 -#define MMPLL4_EARLY 8 -#define MMPLL4_PLL 9 -#define MMPLL5_EARLY 10 -#define MMPLL5_PLL 11 -#define MMPLL8_EARLY 12 -#define MMPLL8_PLL 13 -#define MMPLL9_EARLY 14 -#define MMPLL9_PLL 15 -#define AHB_CLK_SRC 16 -#define AXI_CLK_SRC 17 -#define MAXI_CLK_SRC 18 -#define DSA_CORE_CLK_SRC 19 -#define GFX3D_CLK_SRC 20 -#define RBBMTIMER_CLK_SRC 21 -#define ISENSE_CLK_SRC 22 -#define RBCPR_CLK_SRC 23 -#define VIDEO_CORE_CLK_SRC 24 -#define VIDEO_SUBCORE0_CLK_SRC 25 -#define VIDEO_SUBCORE1_CLK_SRC 26 -#define PCLK0_CLK_SRC 27 -#define PCLK1_CLK_SRC 28 -#define MDP_CLK_SRC 29 -#define EXTPCLK_CLK_SRC 30 -#define VSYNC_CLK_SRC 31 -#define HDMI_CLK_SRC 32 -#define BYTE0_CLK_SRC 33 -#define BYTE1_CLK_SRC 34 -#define ESC0_CLK_SRC 35 -#define ESC1_CLK_SRC 36 -#define CAMSS_GP0_CLK_SRC 37 -#define CAMSS_GP1_CLK_SRC 38 -#define MCLK0_CLK_SRC 39 -#define MCLK1_CLK_SRC 40 -#define MCLK2_CLK_SRC 41 -#define MCLK3_CLK_SRC 42 -#define CCI_CLK_SRC 43 -#define CSI0PHYTIMER_CLK_SRC 44 -#define CSI1PHYTIMER_CLK_SRC 45 -#define CSI2PHYTIMER_CLK_SRC 46 -#define CSIPHY0_3P_CLK_SRC 47 -#define CSIPHY1_3P_CLK_SRC 48 -#define CSIPHY2_3P_CLK_SRC 49 -#define JPEG0_CLK_SRC 50 -#define JPEG2_CLK_SRC 51 -#define JPEG_DMA_CLK_SRC 52 -#define VFE0_CLK_SRC 53 -#define VFE1_CLK_SRC 54 -#define CPP_CLK_SRC 55 -#define CSI0_CLK_SRC 56 -#define CSI1_CLK_SRC 57 -#define CSI2_CLK_SRC 58 -#define CSI3_CLK_SRC 59 -#define FD_CORE_CLK_SRC 60 -#define MMSS_CXO_CLK 61 -#define MMSS_SLEEPCLK_CLK 62 -#define MMSS_MMAGIC_AHB_CLK 63 -#define MMSS_MMAGIC_CFG_AHB_CLK 64 -#define MMSS_MISC_AHB_CLK 65 -#define MMSS_MISC_CXO_CLK 66 -#define MMSS_BTO_AHB_CLK 67 -#define MMSS_MMAGIC_AXI_CLK 68 -#define MMSS_S0_AXI_CLK 69 +/* Hardware/Dummy/Voter clocks */ +#define GPLL0_DIV 0 +#define MDSS_MDP_VOTE_CLK 1 +#define MDSS_ROTATOR_VOTE_CLK 2 + +/* RCG and Branches */ +#define MMPLL0_EARLY 10 +#define MMPLL0_PLL 11 +#define MMPLL1_EARLY 12 +#define MMPLL1_PLL 13 +#define MMPLL2_EARLY 14 +#define MMPLL2_PLL 15 +#define MMPLL3_EARLY 16 +#define MMPLL3_PLL 17 +#define MMPLL4_EARLY 18 +#define MMPLL4_PLL 19 +#define MMPLL5_EARLY 20 +#define MMPLL5_PLL 21 +#define MMPLL8_EARLY 22 +#define MMPLL8_PLL 23 +#define MMPLL9_EARLY 24 +#define MMPLL9_PLL 25 +#define AHB_CLK_SRC 26 +#define MAXI_CLK_SRC 27 +#define RBCPR_CLK_SRC 28 +#define VIDEO_CORE_CLK_SRC 29 +#define VIDEO_SUBCORE0_CLK_SRC 30 +#define VIDEO_SUBCORE1_CLK_SRC 31 +#define PCLK0_CLK_SRC 32 +#define PCLK1_CLK_SRC 33 +#define MDP_CLK_SRC 34 +#define EXTPCLK_CLK_SRC 35 +#define VSYNC_CLK_SRC 36 +#define HDMI_CLK_SRC 37 +#define BYTE0_CLK_SRC 38 +#define BYTE1_CLK_SRC 39 +#define ESC0_CLK_SRC 40 +#define ESC1_CLK_SRC 41 +#define CAMSS_GP0_CLK_SRC 42 +#define CAMSS_GP1_CLK_SRC 43 +#define MCLK0_CLK_SRC 44 +#define MCLK1_CLK_SRC 45 +#define MCLK2_CLK_SRC 46 +#define MCLK3_CLK_SRC 47 +#define CCI_CLK_SRC 48 +#define CSI0PHYTIMER_CLK_SRC 49 +#define CSI1PHYTIMER_CLK_SRC 50 +#define CSI2PHYTIMER_CLK_SRC 51 +#define CSIPHY0_3P_CLK_SRC 52 +#define CSIPHY1_3P_CLK_SRC 53 +#define CSIPHY2_3P_CLK_SRC 54 +#define JPEG0_CLK_SRC 55 +#define JPEG2_CLK_SRC 56 +#define JPEG_DMA_CLK_SRC 57 +#define VFE0_CLK_SRC 58 +#define VFE1_CLK_SRC 59 +#define CPP_CLK_SRC 60 +#define CSI0_CLK_SRC 61 +#define CSI1_CLK_SRC 62 +#define CSI2_CLK_SRC 63 +#define CSI3_CLK_SRC 64 +#define FD_CORE_CLK_SRC 65 +#define MMSS_MMAGIC_AHB_CLK 66 +#define MMSS_MMAGIC_CFG_AHB_CLK 67 +#define MMSS_MISC_AHB_CLK 68 +#define MMSS_MISC_CXO_CLK 69 #define MMSS_MMAGIC_MAXI_CLK 70 -#define DSA_CORE_CLK 71 -#define DSA_NOC_CFG_AHB_CLK 72 -#define MMAGIC_CAMSS_AXI_CLK 73 -#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74 -#define THROTTLE_CAMSS_CXO_CLK 75 -#define THROTTLE_CAMSS_AHB_CLK 76 -#define THROTTLE_CAMSS_AXI_CLK 77 -#define SMMU_VFE_AHB_CLK 78 -#define SMMU_VFE_AXI_CLK 79 -#define SMMU_CPP_AHB_CLK 80 -#define SMMU_CPP_AXI_CLK 81 -#define SMMU_JPEG_AHB_CLK 82 -#define SMMU_JPEG_AXI_CLK 83 -#define MMAGIC_MDSS_AXI_CLK 84 -#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85 -#define THROTTLE_MDSS_CXO_CLK 86 -#define THROTTLE_MDSS_AHB_CLK 87 -#define THROTTLE_MDSS_AXI_CLK 88 -#define SMMU_ROT_AHB_CLK 89 -#define SMMU_ROT_AXI_CLK 90 -#define SMMU_MDP_AHB_CLK 91 -#define SMMU_MDP_AXI_CLK 92 -#define MMAGIC_VIDEO_AXI_CLK 93 -#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94 -#define THROTTLE_VIDEO_CXO_CLK 95 -#define THROTTLE_VIDEO_AHB_CLK 96 -#define THROTTLE_VIDEO_AXI_CLK 97 -#define SMMU_VIDEO_AHB_CLK 98 -#define SMMU_VIDEO_AXI_CLK 99 -#define MMAGIC_BIMC_AXI_CLK 100 -#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101 -#define GPU_GX_GFX3D_CLK 102 -#define GPU_GX_RBBMTIMER_CLK 103 -#define GPU_AHB_CLK 104 -#define GPU_AON_ISENSE_CLK 105 -#define VMEM_MAXI_CLK 106 -#define VMEM_AHB_CLK 107 -#define MMSS_RBCPR_CLK 108 -#define MMSS_RBCPR_AHB_CLK 109 -#define VIDEO_CORE_CLK 110 -#define VIDEO_AXI_CLK 111 -#define VIDEO_MAXI_CLK 112 -#define VIDEO_AHB_CLK 113 -#define VIDEO_SUBCORE0_CLK 114 -#define VIDEO_SUBCORE1_CLK 115 -#define MDSS_AHB_CLK 116 -#define MDSS_HDMI_AHB_CLK 117 -#define MDSS_AXI_CLK 118 -#define MDSS_PCLK0_CLK 119 -#define MDSS_PCLK1_CLK 120 -#define MDSS_MDP_CLK 121 -#define MDSS_EXTPCLK_CLK 122 -#define MDSS_VSYNC_CLK 123 -#define MDSS_HDMI_CLK 124 -#define MDSS_BYTE0_CLK 125 -#define MDSS_BYTE1_CLK 126 -#define MDSS_ESC0_CLK 127 -#define MDSS_ESC1_CLK 128 -#define CAMSS_TOP_AHB_CLK 129 -#define CAMSS_AHB_CLK 130 -#define CAMSS_MICRO_AHB_CLK 131 -#define CAMSS_GP0_CLK 132 -#define CAMSS_GP1_CLK 133 -#define CAMSS_MCLK0_CLK 134 -#define CAMSS_MCLK1_CLK 135 -#define CAMSS_MCLK2_CLK 136 -#define CAMSS_MCLK3_CLK 137 -#define CAMSS_CCI_CLK 138 -#define CAMSS_CCI_AHB_CLK 139 -#define CAMSS_CSI0PHYTIMER_CLK 140 -#define CAMSS_CSI1PHYTIMER_CLK 141 -#define CAMSS_CSI2PHYTIMER_CLK 142 -#define CAMSS_CSIPHY0_3P_CLK 143 -#define CAMSS_CSIPHY1_3P_CLK 144 -#define CAMSS_CSIPHY2_3P_CLK 145 -#define CAMSS_JPEG0_CLK 146 -#define CAMSS_JPEG2_CLK 147 -#define CAMSS_JPEG_DMA_CLK 148 -#define CAMSS_JPEG_AHB_CLK 149 -#define CAMSS_JPEG_AXI_CLK 150 -#define CAMSS_VFE_AHB_CLK 151 -#define CAMSS_VFE_AXI_CLK 152 -#define CAMSS_VFE0_CLK 153 -#define CAMSS_VFE0_STREAM_CLK 154 -#define CAMSS_VFE0_AHB_CLK 155 -#define CAMSS_VFE1_CLK 156 -#define CAMSS_VFE1_STREAM_CLK 157 -#define CAMSS_VFE1_AHB_CLK 158 -#define CAMSS_CSI_VFE0_CLK 159 -#define CAMSS_CSI_VFE1_CLK 160 -#define CAMSS_CPP_VBIF_AHB_CLK 161 -#define CAMSS_CPP_AXI_CLK 162 -#define CAMSS_CPP_CLK 163 -#define CAMSS_CPP_AHB_CLK 164 -#define CAMSS_CSI0_CLK 165 -#define CAMSS_CSI0_AHB_CLK 166 -#define CAMSS_CSI0PHY_CLK 167 -#define CAMSS_CSI0RDI_CLK 168 -#define CAMSS_CSI0PIX_CLK 169 -#define CAMSS_CSI1_CLK 170 -#define CAMSS_CSI1_AHB_CLK 171 -#define CAMSS_CSI1PHY_CLK 172 -#define CAMSS_CSI1RDI_CLK 173 -#define CAMSS_CSI1PIX_CLK 174 -#define CAMSS_CSI2_CLK 175 -#define CAMSS_CSI2_AHB_CLK 176 -#define CAMSS_CSI2PHY_CLK 177 -#define CAMSS_CSI2RDI_CLK 178 -#define CAMSS_CSI2PIX_CLK 179 -#define CAMSS_CSI3_CLK 180 -#define CAMSS_CSI3_AHB_CLK 181 -#define CAMSS_CSI3PHY_CLK 182 -#define CAMSS_CSI3RDI_CLK 183 -#define CAMSS_CSI3PIX_CLK 184 -#define CAMSS_ISPIF_AHB_CLK 185 -#define FD_CORE_CLK 186 -#define FD_CORE_UAR_CLK 187 -#define FD_AHB_CLK 188 -#define MMSS_SPDM_CSI0_CLK 189 -#define MMSS_SPDM_JPEG_DMA_CLK 190 -#define MMSS_SPDM_CPP_CLK 191 -#define MMSS_SPDM_PCLK0_CLK 192 -#define MMSS_SPDM_AHB_CLK 193 -#define MMSS_SPDM_GFX3D_CLK 194 -#define MMSS_SPDM_PCLK1_CLK 195 -#define MMSS_SPDM_JPEG2_CLK 196 -#define MMSS_SPDM_DEBUG_CLK 197 -#define MMSS_SPDM_VFE1_CLK 198 -#define MMSS_SPDM_VFE0_CLK 199 -#define MMSS_SPDM_VIDEO_CORE_CLK 200 -#define MMSS_SPDM_AXI_CLK 201 -#define MMSS_SPDM_MDP_CLK 202 -#define MMSS_SPDM_JPEG0_CLK 203 -#define MMSS_SPDM_RM_AXI_CLK 204 -#define MMSS_SPDM_RM_MAXI_CLK 205 +#define MMAGIC_CAMSS_AXI_CLK 71 +#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 72 +#define SMMU_VFE_AHB_CLK 73 +#define SMMU_VFE_AXI_CLK 74 +#define SMMU_CPP_AHB_CLK 75 +#define SMMU_CPP_AXI_CLK 76 +#define SMMU_JPEG_AHB_CLK 77 +#define SMMU_JPEG_AXI_CLK 78 +#define MMAGIC_MDSS_AXI_CLK 79 +#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 80 +#define SMMU_ROT_AHB_CLK 81 +#define SMMU_ROT_AXI_CLK 82 +#define SMMU_MDP_AHB_CLK 83 +#define SMMU_MDP_AXI_CLK 84 +#define MMAGIC_VIDEO_AXI_CLK 85 +#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 86 +#define SMMU_VIDEO_AHB_CLK 87 +#define SMMU_VIDEO_AXI_CLK 88 +#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 89 +#define VMEM_MAXI_CLK 90 +#define VMEM_AHB_CLK 91 +#define MMSS_RBCPR_CLK 92 +#define MMSS_RBCPR_AHB_CLK 93 +#define VIDEO_CORE_CLK 94 +#define VIDEO_AXI_CLK 95 +#define VIDEO_MAXI_CLK 96 +#define VIDEO_AHB_CLK 97 +#define VIDEO_SUBCORE0_CLK 98 +#define VIDEO_SUBCORE1_CLK 99 +#define MDSS_AHB_CLK 100 +#define MDSS_HDMI_AHB_CLK 101 +#define MDSS_AXI_CLK 102 +#define MDSS_PCLK0_CLK 103 +#define MDSS_PCLK1_CLK 104 +#define MDSS_MDP_CLK 105 +#define MDSS_EXTPCLK_CLK 106 +#define MDSS_VSYNC_CLK 107 +#define MDSS_HDMI_CLK 108 +#define MDSS_BYTE0_CLK 109 +#define MDSS_BYTE1_CLK 110 +#define MDSS_ESC0_CLK 111 +#define MDSS_ESC1_CLK 112 +#define CAMSS_TOP_AHB_CLK 113 +#define CAMSS_AHB_CLK 114 +#define CAMSS_MICRO_AHB_CLK 115 +#define CAMSS_GP0_CLK 116 +#define CAMSS_GP1_CLK 117 +#define CAMSS_MCLK0_CLK 118 +#define CAMSS_MCLK1_CLK 119 +#define CAMSS_MCLK2_CLK 120 +#define CAMSS_MCLK3_CLK 121 +#define CAMSS_CCI_CLK 122 +#define CAMSS_CCI_AHB_CLK 123 +#define CAMSS_CSI0PHYTIMER_CLK 124 +#define CAMSS_CSI1PHYTIMER_CLK 125 +#define CAMSS_CSI2PHYTIMER_CLK 126 +#define CAMSS_CSIPHY0_3P_CLK 127 +#define CAMSS_CSIPHY1_3P_CLK 128 +#define CAMSS_CSIPHY2_3P_CLK 129 +#define CAMSS_JPEG0_CLK 130 +#define CAMSS_JPEG2_CLK 131 +#define CAMSS_JPEG_DMA_CLK 132 +#define CAMSS_JPEG_AHB_CLK 133 +#define CAMSS_JPEG_AXI_CLK 134 +#define CAMSS_VFE_AHB_CLK 135 +#define CAMSS_VFE_AXI_CLK 136 +#define CAMSS_VFE0_CLK 137 +#define CAMSS_VFE0_STREAM_CLK 138 +#define CAMSS_VFE0_AHB_CLK 139 +#define CAMSS_VFE1_CLK 140 +#define CAMSS_VFE1_STREAM_CLK 141 +#define CAMSS_VFE1_AHB_CLK 142 +#define CAMSS_CSI_VFE0_CLK 143 +#define CAMSS_CSI_VFE1_CLK 144 +#define CAMSS_CPP_VBIF_AHB_CLK 145 +#define CAMSS_CPP_AXI_CLK 146 +#define CAMSS_CPP_CLK 147 +#define CAMSS_CPP_AHB_CLK 148 +#define CAMSS_CSI0_CLK 149 +#define CAMSS_CSI0_AHB_CLK 150 +#define CAMSS_CSI0PHY_CLK 151 +#define CAMSS_CSI0RDI_CLK 152 +#define CAMSS_CSI0PIX_CLK 153 +#define CAMSS_CSI1_CLK 154 +#define CAMSS_CSI1_AHB_CLK 155 +#define CAMSS_CSI1PHY_CLK 156 +#define CAMSS_CSI1RDI_CLK 157 +#define CAMSS_CSI1PIX_CLK 158 +#define CAMSS_CSI2_CLK 159 +#define CAMSS_CSI2_AHB_CLK 160 +#define CAMSS_CSI2PHY_CLK 161 +#define CAMSS_CSI2RDI_CLK 162 +#define CAMSS_CSI2PIX_CLK 163 +#define CAMSS_CSI3_CLK 164 +#define CAMSS_CSI3_AHB_CLK 165 +#define CAMSS_CSI3PHY_CLK 166 +#define CAMSS_CSI3RDI_CLK 167 +#define CAMSS_CSI3PIX_CLK 168 +#define CAMSS_ISPIF_AHB_CLK 169 +#define FD_CORE_CLK 170 +#define FD_CORE_UAR_CLK 171 +#define FD_AHB_CLK 172 +/* Block resets */ #define MMAGICAHB_BCR 0 #define MMAGIC_CFG_BCR 1 #define MISC_BCR 2 @@ -241,63 +205,60 @@ #define THROTTLE_VIDEO_BCR 17 #define SMMU_VIDEO_BCR 18 #define MMAGIC_BIMC_BCR 19 -#define GPU_GX_BCR 20 -#define GPU_BCR 21 -#define GPU_AON_BCR 22 -#define VMEM_BCR 23 -#define MMSS_RBCPR_BCR 24 -#define VIDEO_BCR 25 -#define MDSS_BCR 26 -#define CAMSS_TOP_BCR 27 -#define CAMSS_AHB_BCR 28 -#define CAMSS_MICRO_BCR 29 -#define CAMSS_CCI_BCR 30 -#define CAMSS_PHY0_BCR 31 -#define CAMSS_PHY1_BCR 32 -#define CAMSS_PHY2_BCR 33 -#define CAMSS_CSIPHY0_3P_BCR 34 -#define CAMSS_CSIPHY1_3P_BCR 35 -#define CAMSS_CSIPHY2_3P_BCR 36 -#define CAMSS_JPEG_BCR 37 -#define CAMSS_VFE_BCR 38 -#define CAMSS_VFE0_BCR 39 -#define CAMSS_VFE1_BCR 40 -#define CAMSS_CSI_VFE0_BCR 41 -#define CAMSS_CSI_VFE1_BCR 42 -#define CAMSS_CPP_TOP_BCR 43 -#define CAMSS_CPP_BCR 44 -#define CAMSS_CSI0_BCR 45 -#define CAMSS_CSI0RDI_BCR 46 -#define CAMSS_CSI0PIX_BCR 47 -#define CAMSS_CSI1_BCR 48 -#define CAMSS_CSI1RDI_BCR 49 -#define CAMSS_CSI1PIX_BCR 50 -#define CAMSS_CSI2_BCR 51 -#define CAMSS_CSI2RDI_BCR 52 -#define CAMSS_CSI2PIX_BCR 53 -#define CAMSS_CSI3_BCR 54 -#define CAMSS_CSI3RDI_BCR 55 -#define CAMSS_CSI3PIX_BCR 56 -#define CAMSS_ISPIF_BCR 57 -#define FD_BCR 58 -#define MMSS_SPDM_RM_BCR 59 +#define VMEM_BCR 20 +#define MMSS_RBCPR_BCR 21 +#define VIDEO_BCR 22 +#define MDSS_BCR 23 +#define CAMSS_TOP_BCR 24 +#define CAMSS_AHB_BCR 25 +#define CAMSS_MICRO_BCR 26 +#define CAMSS_CCI_BCR 27 +#define CAMSS_PHY0_BCR 28 +#define CAMSS_PHY1_BCR 29 +#define CAMSS_PHY2_BCR 30 +#define CAMSS_CSIPHY0_3P_BCR 31 +#define CAMSS_CSIPHY1_3P_BCR 32 +#define CAMSS_CSIPHY2_3P_BCR 33 +#define CAMSS_JPEG_BCR 34 +#define CAMSS_VFE_BCR 35 +#define CAMSS_VFE0_BCR 36 +#define CAMSS_VFE1_BCR 37 +#define CAMSS_CSI_VFE0_BCR 38 +#define CAMSS_CSI_VFE1_BCR 39 +#define CAMSS_CPP_TOP_BCR 40 +#define CAMSS_CPP_BCR 41 +#define CAMSS_CSI0_BCR 42 +#define CAMSS_CSI0RDI_BCR 43 +#define CAMSS_CSI0PIX_BCR 44 +#define CAMSS_CSI1_BCR 45 +#define CAMSS_CSI1RDI_BCR 46 +#define CAMSS_CSI1PIX_BCR 47 +#define CAMSS_CSI2_BCR 48 +#define CAMSS_CSI2RDI_BCR 49 +#define CAMSS_CSI2PIX_BCR 50 +#define CAMSS_CSI3_BCR 51 +#define CAMSS_CSI3RDI_BCR 52 +#define CAMSS_CSI3PIX_BCR 53 +#define CAMSS_ISPIF_BCR 54 +#define FD_BCR 55 +#define MMSS_SPDM_RM_BCR 56 /* Indexes for GDSCs */ -#define MMAGIC_VIDEO_GDSC 0 -#define MMAGIC_MDSS_GDSC 1 -#define MMAGIC_CAMSS_GDSC 2 -#define GPU_GDSC 3 -#define VENUS_GDSC 4 -#define VENUS_CORE0_GDSC 5 -#define VENUS_CORE1_GDSC 6 -#define CAMSS_GDSC 7 -#define VFE0_GDSC 8 -#define VFE1_GDSC 9 -#define JPEG_GDSC 10 -#define CPP_GDSC 11 -#define FD_GDSC 12 -#define MDSS_GDSC 13 -#define GPU_GX_GDSC 14 -#define MMAGIC_BIMC_GDSC 15 +#define MMAGIC_VIDEO_GDSC 0 +#define MMAGIC_MDSS_GDSC 1 +#define MMAGIC_CAMSS_GDSC 2 +#define GPU_GDSC 3 +#define VENUS_GDSC 4 +#define VENUS_CORE0_GDSC 5 +#define VENUS_CORE1_GDSC 6 +#define CAMSS_GDSC 7 +#define VFE0_GDSC 8 +#define VFE1_GDSC 9 +#define JPEG_GDSC 10 +#define CPP_GDSC 11 +#define FD_GDSC 12 +#define MDSS_GDSC 13 +#define GPU_GX_GDSC 14 +#define MMAGIC_BIMC_GDSC 15 #endif |