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-rw-r--r--drivers/gpu/drm/msm/adreno/a5xx_gpu.c10
-rw-r--r--drivers/gpu/drm/msm/adreno/a5xx_gpu.h2
2 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 666da8fbb50c..37323e962c2c 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -774,6 +774,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1);
gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
+ a5xx_gpu->timestamp_counter = adreno_get_counter(gpu,
+ MSM_COUNTER_GROUP_CP, 0, NULL, NULL);
+
/* Load the GPMU firmware before starting the HW init */
a5xx_gpmu_ucode_init(gpu);
@@ -1218,8 +1221,11 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu)
static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
{
- *value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_CP_0_LO,
- REG_A5XX_RBBM_PERFCTR_CP_0_HI);
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
+
+ *value = adreno_read_counter(gpu, MSM_COUNTER_GROUP_CP,
+ a5xx_gpu->timestamp_counter);
return 0;
}
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
index 8eb3838ffe90..f8b00982fe86 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
@@ -56,6 +56,8 @@ struct a5xx_gpu {
struct a5xx_smmu_info *smmu_info;
struct drm_gem_object *smmu_info_bo;
uint64_t smmu_info_iova;
+
+ int timestamp_counter;
};
#define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base)