diff options
| -rw-r--r-- | Documentation/devicetree/bindings/arm/msm/clock-controller.txt | 18 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/arm/msm/msm.txt | 24 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/arm/msm/msm_gladiator_hang_detect.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/arm/msm/qcom,osm.txt | 8 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,mmcc.txt | 1 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/cnss/icnss.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/fb/mdss-dp.txt | 4 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/fb/mdss-pll.txt | 4 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt | 4 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt | 8 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/nfc/nq-nci.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt | 6 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/power/qcom-charger/qpnp-qnovo.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/power/qcom-charger/qpnp-smb2.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/qbt1000/qbt1000.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/qdsp/msm-ssc-sensors.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/regulator/cpr3-mmss-regulator.txt | 14 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt | 10 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/sound/qcom-audio-dev.txt | 16 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt | 4 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/thermal/tsens.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/usb/qpnp-pdphy.txt | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/Makefile | 58 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998-cdp.dts (renamed from arch/arm/boot/dts/qcom/apqcobalt-cdp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998-mtp.dts (renamed from arch/arm/boot/dts/qcom/apqcobalt-mtp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998-v2-cdp.dts (renamed from arch/arm/boot/dts/qcom/apqcobalt-v2-cdp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998-v2-mtp.dts (renamed from arch/arm/boot/dts/qcom/apqcobalt-v2-mtp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998-v2-qrd.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2-qrd.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998-v2.1-cdp.dts (renamed from arch/arm/boot/dts/qcom/apqcobalt-v2.1-cdp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998-v2.1-mediabox.dts (renamed from arch/arm/boot/dts/qcom/apqcobalt-v2.1-mediabox.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998-v2.1-mtp.dts (renamed from arch/arm/boot/dts/qcom/apqcobalt-v2.1-mtp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998-v2.1-qrd.dts (renamed from arch/arm/boot/dts/qcom/apqcobalt-v2-qrd.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998-v2.1.dtsi (renamed from arch/arm/boot/dts/qcom/apqcobalt-v2.1.dtsi) | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998-v2.dtsi (renamed from arch/arm/boot/dts/qcom/apqcobalt-v2.dtsi) | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/apq8998.dtsi (renamed from arch/arm/boot/dts/qcom/apqcobalt.dtsi) | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/batterydata-qrd-skuk-4v4-3000mah.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi (renamed from arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi) | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-8998.dtsi (renamed from arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-cobalt.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm-gdsc-8998.dtsi (renamed from arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm-pm8998-rpm-regulator.dtsi (renamed from arch/arm/boot/dts/qcom/msm-pmcobalt-rpm-regulator.dtsi) | 82 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm-pm8998.dtsi (renamed from arch/arm/boot/dts/qcom/msm-pmcobalt.dtsi) | 28 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm-pmi8998.dtsi (renamed from arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi) | 84 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-audio.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi) | 32 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-blsp.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-blsp.dtsi) | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-bus.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-bus.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-camera-sensor-cdp.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-cdp.dtsi) | 58 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-camera-sensor-mtp.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-mtp.dtsi) | 58 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-camera-sensor-qrd-vr1.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-qrd-vr1.dtsi) | 52 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-camera-sensor-qrd.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-qrd.dtsi) | 58 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-camera-sensor-skuk.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-skuk.dtsi) | 54 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-camera.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi) | 16 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-cdp.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-cdp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-cdp.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi) | 58 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-coresight.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-gpu.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon-cdp.dtsi) | 46 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon-mtp.dtsi) | 42 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon.dtsi) | 116 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-interposer-pmfalcon.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-ion.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-ion.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-mdss-panels.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-mdss-pll.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-mdss-pll.dtsi) | 12 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-mdss.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi) | 16 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-mtp.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-mtp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-mtp.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi) | 54 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi) | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-pm.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-pm.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi) | 32 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-qrd-vr1.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-qrd-vr1.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-qrd-vr1.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-qrd-vr1.dtsi) | 30 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-qrd.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-qrd.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-qrd.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-qrd.dtsi) | 55 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-regulator.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi) | 172 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-rumi.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-rumi.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-rumi.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi) | 22 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-sim.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-sim.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-sim.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi) | 24 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-smp2p.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-smp2p.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2-camera.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2-cdp.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2-cdp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2-interposer-msmfalcon.dtsi) | 28 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2-mtp.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2-mtp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2-qrd-skuk.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2-qrd-skuk.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2-qrd-vr1.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2-qrd-vr1.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2-qrd.dts (renamed from arch/arm/boot/dts/qcom/apqcobalt-v2.1-qrd.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2-rumi.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2-rumi.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2-sim.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2-sim.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2.1-cdp.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2.1-cdp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-cdp.dts) | 10 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-mtp.dts) | 10 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dts) | 6 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dtsi) | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon.dtsi) | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2.1-mtp.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2.1-mtp.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2.1-qrd.dts (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2.1-qrd.dts) | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2.1.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2.1.dtsi) | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi) | 47 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-vidc.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi) | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-wcd.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-wcd.dtsi) | 0 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-wsa881x.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt-wsa881x.dtsi) | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998.dtsi (renamed from arch/arm/boot/dts/qcom/msmcobalt.dtsi) | 135 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmfalcon-rumi.dts | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmfalcon.dtsi | 23 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmhamster-cdp.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmhamster-mtp.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmhamster-rumi.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmhamster.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmtriton-rumi.dts | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmtriton.dtsi | 23 | ||||
| -rw-r--r-- | arch/arm/configs/msmcortex_defconfig | 2 | ||||
| -rw-r--r-- | arch/arm/configs/msmfalcon_defconfig | 4 | ||||
| -rw-r--r-- | arch/arm64/Kconfig.platforms | 6 | ||||
| -rw-r--r-- | arch/arm64/configs/msmcortex-perf_defconfig | 6 | ||||
| -rw-r--r-- | arch/arm64/configs/msmcortex_defconfig | 6 | ||||
| -rw-r--r-- | arch/arm64/configs/msmfalcon-perf_defconfig | 6 | ||||
| -rw-r--r-- | arch/arm64/configs/msmfalcon_defconfig | 5 | ||||
| -rw-r--r-- | block/genhd.c | 1 | ||||
| -rw-r--r-- | block/ioprio.c | 2 | ||||
| -rw-r--r-- | drivers/clk/msm/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/clk/msm/Makefile | 10 | ||||
| -rw-r--r-- | drivers/clk/msm/clock-gcc-8998.c (renamed from drivers/clk/msm/clock-gcc-cobalt.c) | 68 | ||||
| -rw-r--r-- | drivers/clk/msm/clock-gpu-8998.c (renamed from drivers/clk/msm/clock-gpu-cobalt.c) | 48 | ||||
| -rw-r--r-- | drivers/clk/msm/clock-mmss-8998.c (renamed from drivers/clk/msm/clock-mmss-cobalt.c) | 34 | ||||
| -rw-r--r-- | drivers/clk/msm/clock-osm.c | 54 | ||||
| -rw-r--r-- | drivers/clk/msm/mdss/Makefile | 8 | ||||
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c (renamed from drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c) | 2 | ||||
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dp-pll-8998.c (renamed from drivers/clk/msm/mdss/mdss-dp-pll-cobalt.c) | 18 | ||||
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dp-pll-8998.h (renamed from drivers/clk/msm/mdss/mdss-dp-pll-cobalt.h) | 6 | ||||
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dp-pll.h | 2 | ||||
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dsi-pll-8998.c (renamed from drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c) | 66 | ||||
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dsi-pll.h | 2 | ||||
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-hdmi-pll-8998.c (renamed from drivers/clk/msm/mdss/mdss-hdmi-pll-cobalt.c) | 72 | ||||
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-hdmi-pll.h | 2 | ||||
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-pll.c | 30 | ||||
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-pll.h | 6 | ||||
| -rw-r--r-- | drivers/clk/msm/vdd-level-8998.h (renamed from drivers/clk/msm/vdd-level-cobalt.h) | 4 | ||||
| -rw-r--r-- | drivers/clk/qcom/Kconfig | 10 | ||||
| -rw-r--r-- | drivers/clk/qcom/Makefile | 1 | ||||
| -rw-r--r-- | drivers/clk/qcom/clk-smd-rpm.c | 10 | ||||
| -rw-r--r-- | drivers/clk/qcom/mdss/mdss-dsi-pll.h | 2 | ||||
| -rw-r--r-- | drivers/clk/qcom/mdss/mdss-hdmi-pll.h | 2 | ||||
| -rw-r--r-- | drivers/clk/qcom/mdss/mdss-pll.c | 30 | ||||
| -rw-r--r-- | drivers/clk/qcom/mdss/mdss-pll.h | 6 | ||||
| -rw-r--r-- | drivers/clk/qcom/mmcc-msmfalcon.c | 3036 | ||||
| -rw-r--r-- | drivers/clk/qcom/vdd-level-falcon.h | 15 | ||||
| -rw-r--r-- | drivers/crypto/Kconfig | 8 | ||||
| -rw-r--r-- | drivers/hid/hid-core.c | 3 | ||||
| -rw-r--r-- | drivers/leds/leds-qpnp-wled.c | 64 | ||||
| -rw-r--r-- | drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c | 20 | ||||
| -rw-r--r-- | drivers/media/tuners/tuner-xc2028.c | 3 | ||||
| -rw-r--r-- | drivers/pci/host/pci-msm.c | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/qcom/Kconfig | 6 | ||||
| -rw-r--r-- | drivers/pinctrl/qcom/Makefile | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/qcom/pinctrl-msm8998.c (renamed from drivers/pinctrl/qcom/pinctrl-msmcobalt.c) | 54 | ||||
| -rw-r--r-- | drivers/platform/msm/qpnp-revid.c | 4 | ||||
| -rw-r--r-- | drivers/power/qcom-charger/bcl_peripheral.c | 102 | ||||
| -rw-r--r-- | drivers/power/qcom-charger/qpnp-fg-gen3.c | 42 | ||||
| -rw-r--r-- | drivers/power/qcom-charger/qpnp-qnovo.c | 4 | ||||
| -rw-r--r-- | drivers/power/qcom-charger/qpnp-smb2.c | 6 | ||||
| -rw-r--r-- | drivers/regulator/cpr3-mmss-regulator.c | 180 | ||||
| -rw-r--r-- | drivers/regulator/cprh-kbss-regulator.c | 294 | ||||
| -rw-r--r-- | drivers/regulator/qpnp-labibb-regulator.c | 20 | ||||
| -rw-r--r-- | drivers/soc/qcom/socinfo.c | 12 | ||||
| -rw-r--r-- | drivers/thermal/msm-tsens.c | 12 | ||||
| -rw-r--r-- | drivers/tty/tty_ldisc.c | 7 | ||||
| -rw-r--r-- | drivers/usb/gadget/function/f_fs.c | 10 | ||||
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_dsi_phy_v3.c | 4 | ||||
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_hdmi_tx.c | 2 | ||||
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp_debug.c | 12 | ||||
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp_pp.c | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-8998.h (renamed from include/dt-bindings/clock/msm-clocks-cobalt.h) | 4 | ||||
| -rw-r--r-- | include/dt-bindings/clock/msm-clocks-hwio-8998.h (renamed from include/dt-bindings/clock/msm-clocks-hwio-cobalt.h) | 0 | ||||
| -rw-r--r-- | include/dt-bindings/clock/qcom,mmcc-msmfalcon.h | 82 | ||||
| -rw-r--r-- | include/linux/qpnp/qpnp-revid.h | 32 | ||||
| -rw-r--r-- | include/net/cfg80211.h | 17 | ||||
| -rw-r--r-- | include/net/tcp.h | 2 | ||||
| -rw-r--r-- | include/soc/qcom/socinfo.h | 14 | ||||
| -rw-r--r-- | include/uapi/linux/msm_mdp.h | 4 | ||||
| -rw-r--r-- | kernel/cgroup.c | 2 | ||||
| -rw-r--r-- | net/netfilter/nfnetlink.c | 10 | ||||
| -rw-r--r-- | net/wireless/chan.c | 2 | ||||
| -rw-r--r-- | net/wireless/core.c | 17 | ||||
| -rw-r--r-- | net/wireless/core.h | 3 | ||||
| -rw-r--r-- | net/wireless/nl80211.c | 35 | ||||
| -rw-r--r-- | net/wireless/reg.c | 2 | ||||
| -rw-r--r-- | net/wireless/sme.c | 6 | ||||
| -rw-r--r-- | net/wireless/util.c | 91 | ||||
| -rw-r--r-- | sound/soc/codecs/Kconfig | 2 | ||||
| -rw-r--r-- | sound/soc/msm/Kconfig | 6 | ||||
| -rw-r--r-- | sound/soc/msm/Makefile | 7 | ||||
| -rw-r--r-- | sound/soc/msm/msm8998.c (renamed from sound/soc/msm/msmcobalt.c) | 36 | ||||
| -rw-r--r-- | sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c | 12 |
194 files changed, 4969 insertions, 1822 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/clock-controller.txt b/Documentation/devicetree/bindings/arm/msm/clock-controller.txt index 20506e132727..17250cceea4c 100644 --- a/Documentation/devicetree/bindings/arm/msm/clock-controller.txt +++ b/Documentation/devicetree/bindings/arm/msm/clock-controller.txt @@ -65,18 +65,18 @@ Required properties: "qcom,cc-debug-californium" "qcom,gcc-mdm9607" "qcom,cc-debug-mdm9607" - "qcom,gcc-cobalt" - "qcom,gcc-cobalt-v2" + "qcom,gcc-8998" + "qcom,gcc-8998-v2" "qcom,gcc-hamster" - "qcom,cc-debug-cobalt" - "qcom,gpucc-cobalt" - "qcom,gfxcc-cobalt" - "qcom,gpucc-cobalt-v2" - "qcom,gfxcc-cobalt-v2" + "qcom,cc-debug-8998" + "qcom,gpucc-8998" + "qcom,gfxcc-8998" + "qcom,gpucc-8998-v2" + "qcom,gfxcc-8998-v2" "qcom,gpucc-hamster" "qcom,gfxcc-hamster" - "qcom,mmsscc-cobalt" - "qcom,mmsscc-cobalt-v2" + "qcom,mmsscc-8998" + "qcom,mmsscc-8998-v2" "qcom,mmsscc-hamster" - reg: Pairs of physical base addresses and region sizes of diff --git a/Documentation/devicetree/bindings/arm/msm/msm.txt b/Documentation/devicetree/bindings/arm/msm/msm.txt index 7b1c081ef586..de99a5636ef3 100644 --- a/Documentation/devicetree/bindings/arm/msm/msm.txt +++ b/Documentation/devicetree/bindings/arm/msm/msm.txt @@ -47,8 +47,8 @@ SoCs: - APQTITANIUM compatible = "qcom,apqtitanium" -- APQCOBALT - compatible = "qcom,apqcobalt" +- APQ8998 + compatible = "qcom,apq8998" - MDM9630 compatible = "qcom,mdm9630" @@ -83,8 +83,8 @@ SoCs: - MSM8996 compatible = "qcom,msm8996" -- MSMCOBALT - compatible = "qcom,msmcobalt" +- MSM8998 + compatible = "qcom,msm8998" - MSMHAMSTER compatible = "qcom,msmhamster" @@ -183,9 +183,9 @@ compatible = "qcom,apq8037-cdp" compatible = "qcom,apq8037-mtp" compatible = "qcom,apqtitanium-cdp" compatible = "qcom,apqtitanium-mtp" -compatible = "qcom,apqcobalt-cdp" -compatible = "qcom,apqcobalt-mtp" -compatible = "qcom,apqcobalt-qrd" +compatible = "qcom,apq8998-cdp" +compatible = "qcom,apq8998-mtp" +compatible = "qcom,apq8998-qrd" compatible = "qcom,mdm9630-cdp" compatible = "qcom,mdm9630-mtp" compatible = "qcom,mdm9630-sim" @@ -252,11 +252,11 @@ compatible = "qcom,msm8996-fluid" compatible = "qcom,msm8996-liquid" compatible = "qcom,msm8996-mtp" compatible = "qcom,msm8996-adp" -compatible = "qcom,msmcobalt-sim" -compatible = "qcom,msmcobalt-rumi" -compatible = "qcom,msmcobalt-cdp" -compatible = "qcom,msmcobalt-mtp" -compatible = "qcom,msmcobalt-qrd" +compatible = "qcom,msm8998-sim" +compatible = "qcom,msm8998-rumi" +compatible = "qcom,msm8998-cdp" +compatible = "qcom,msm8998-mtp" +compatible = "qcom,msm8998-qrd" compatible = "qcom,msmhamster-rumi" compatible = "qcom,msmhamster-cdp" compatible = "qcom,msmhamster-mtp" diff --git a/Documentation/devicetree/bindings/arm/msm/msm_gladiator_hang_detect.txt b/Documentation/devicetree/bindings/arm/msm/msm_gladiator_hang_detect.txt index d35bb84ad2cc..1935a092f857 100644 --- a/Documentation/devicetree/bindings/arm/msm/msm_gladiator_hang_detect.txt +++ b/Documentation/devicetree/bindings/arm/msm/msm_gladiator_hang_detect.txt @@ -31,7 +31,7 @@ Required properties: Optional properties: Example: - For msmcobalt: + For msm8998: qcom,ghd { compatible = "qcom,gladiator-hang-detect"; qcom,threshold-arr = <0x179d141c 0x179d1420 diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt index 782fb6c4124d..adcaa6444ab8 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt +++ b/Documentation/devicetree/bindings/arm/msm/qcom,osm.txt @@ -9,8 +9,8 @@ Properties: - compatible Usage: required Value type: <string> - Definition: must be "qcom,cpu-clock-osm-msmcobalt-v1" or - "qcom,cpu-clock-osm-msmcobalt-v2". + Definition: must be "qcom,cpu-clock-osm-msm8998-v1" or + "qcom,cpu-clock-osm-msm8998-v2". - reg Usage: required @@ -342,8 +342,8 @@ Properties: Example: - clock_cpu: qcom,cpu-clock-cobalt@179c0000 { - compatible = "qcom,cpu-clock-osm-msmcobalt-v1"; + clock_cpu: qcom,cpu-clock-8998@179c0000 { + compatible = "qcom,cpu-clock-osm-msm8998-v1"; reg = <0x179C0000 0x4000>, <0x17916000 0x1000>, <0x17816000 0x1000>, diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt index 8b0f7841af8d..6aaf89c47781 100644 --- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt @@ -10,6 +10,7 @@ Required properties : "qcom,mmcc-msm8960" "qcom,mmcc-msm8974" "qcom,mmcc-msm8996" + "qcom,mmcc-msmfalcon" - reg : shall contain base register location and length - #clock-cells : shall contain 1 diff --git a/Documentation/devicetree/bindings/cnss/icnss.txt b/Documentation/devicetree/bindings/cnss/icnss.txt index 505966fb9226..e19a43446357 100644 --- a/Documentation/devicetree/bindings/cnss/icnss.txt +++ b/Documentation/devicetree/bindings/cnss/icnss.txt @@ -53,6 +53,6 @@ Example: <0 140 0 /* CE10 */ >, <0 141 0 /* CE11 */ >; qcom,wlan-msa-memory = <0x200000>; - vdd-0.8-cx-mx-supply = <&pmcobalt_l5>; + vdd-0.8-cx-mx-supply = <&pm8998_l5>; qcom,vdd-0.8-cx-mx-config = <800000 800000 2400 1000>; }; diff --git a/Documentation/devicetree/bindings/fb/mdss-dp.txt b/Documentation/devicetree/bindings/fb/mdss-dp.txt index 85656e312acc..27516d3b54a5 100644 --- a/Documentation/devicetree/bindings/fb/mdss-dp.txt +++ b/Documentation/devicetree/bindings/fb/mdss-dp.txt @@ -59,8 +59,8 @@ Example: qcom,mdss-fb-map = <&mdss_fb3>; gdsc-supply = <&gdsc_mdss>; - vdda-1p2-supply = <&pmcobalt_l2>; - vdda-0p9-supply = <&pmcobalt_l1>; + vdda-1p2-supply = <&pm8998_l2>; + vdda-0p9-supply = <&pm8998_l1>; reg = <0xc990000 0xa84>, <0xc011000 0x910>, diff --git a/Documentation/devicetree/bindings/fb/mdss-pll.txt b/Documentation/devicetree/bindings/fb/mdss-pll.txt index 37ca97021ed0..945d79825695 100644 --- a/Documentation/devicetree/bindings/fb/mdss-pll.txt +++ b/Documentation/devicetree/bindings/fb/mdss-pll.txt @@ -14,8 +14,8 @@ Required properties: "qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996", "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2", "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8", - "qcom,mdss_dsi_pll_cobalt", "qcom,mdss_dp_pll_cobalt", - "qcom,mdss_hdmi_pll_cobalt" + "qcom,mdss_dsi_pll_8998", "qcom,mdss_dp_pll_8998", + "qcom,mdss_hdmi_pll_8998" - cell-index: Specifies the controller used - reg: offset and length of the register set for the device. - reg-names : names to refer to register sets related to this device diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt index 4808d1dda5c1..581f1128355c 100644 --- a/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt +++ b/Documentation/devicetree/bindings/leds/leds-qpnp-flash-v2.txt @@ -97,7 +97,7 @@ Optional properties: hysteresis. Unit is in deciDegC. It is only used if qcom,thermal-derate-en is specified. Allowed values are: - 0, 15, 30, 45 for pmicobalt. + 0, 15, 30, 45 for pmi8998. 0, 20, 40, 60 for pm2falcon. - qcom,thermal-thrsh1 : Integer property to specify OTST1 threshold for thermal mitigation. Unit is in Celsius. @@ -200,7 +200,7 @@ Example: qcom,hdrm-auto-mode; qcom,isc-delay = <192>; - switch0-supply = <&pmicobalt_bob>; + switch0-supply = <&pmi8998_bob>; pmi8998_flash0: qcom,flash_0 { label = "flash"; diff --git a/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt b/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt index 4b23cb1e9a9c..74cee0d6ba0d 100644 --- a/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt +++ b/Documentation/devicetree/bindings/leds/leds-qpnp-wled.txt @@ -28,13 +28,13 @@ Optional properties for WLED: - qcom,vref-uv : maximum reference voltage in uV. For pmi8994/8952/8996, supported values are from 300000 to 675000 with a step size of 25000, the default value is 350000. - For pmicobalt/pm2falcon, supported values are from 60000 to 397500 + For pmi8998/pm2falcon, supported values are from 60000 to 397500 with a step size of 22500, the default value is 127500. - qcom,switch-freq-khz : switch frequency in khz. default is 800. - qcom,ovp-mv : Over voltage protection threshold in mV. Default is 29500. Supported values are: - 31000, 29500, 19400, 17800 for pmi8994/8952/8996. - - 31100, 29600, 19600, 18100 for pmicobalt/pm2falcon. + - 31100, 29600, 19600, 18100 for pmi8998/pm2falcon. Should only be used if qcom,disp-type-amoled is not specified. - qcom,ilim-ma : Current limit threshold in mA. @@ -42,7 +42,7 @@ Optional properties for WLED: and AMOLED is 385mA. Supported values are: - 105, 385, 660, 980, 1150, 1420, 1700, 1980. - For pmicobalt/pm2falcon, default value for LCD is + For pmi8998/pm2falcon, default value for LCD is 970mA and AMOLED is 620mA. Supported values are: - 105, 280, 450, 620, 970, 1150, 1300, 1500. @@ -81,7 +81,7 @@ Optional properties if 'qcom,disp-type-amoled' is mentioned in DT: - qcom,vref-psm-mv : reference psm voltage in mv. default for amoled is 450. - qcom,avdd-mode-spmi: Boolean property to enable AMOLED_VOUT programming via SPMI. If not specified, AMOLED_VOUT is programmed via S-wire. This can be specified only for newer - PMICs like pmicobalt/pm2falcon. + PMICs like pmi8998/pm2falcon. - qcom,avdd-target-voltage-mv: The voltage required for AMOLED_VOUT. Accepted values are in the range of 5650 to 7900 in steps of 150. Default value is 7600. Unit is in mV. For old revisions, accepted values are: 7900, 7600, 7300, 6400, 6100, diff --git a/Documentation/devicetree/bindings/nfc/nq-nci.txt b/Documentation/devicetree/bindings/nfc/nq-nci.txt index af8b81e56333..b85e0701bbae 100644 --- a/Documentation/devicetree/bindings/nfc/nq-nci.txt +++ b/Documentation/devicetree/bindings/nfc/nq-nci.txt @@ -34,7 +34,7 @@ Example: qcom,nq-irq = <&tlmm 29 0x00>; qcom,nq-ven = <&tlmm 30 0x00>; qcom,nq-firm = <&tlmm 93 0x00>; - qcom,nq-clkreq = <&pmcobalt_gpios 21 0x00>; + qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; qcom,nq-esepwr = <&tlmm 116 0x00>; qcom,clk-src = "BBCLK2"; interrupt-parent = <&tlmm>; diff --git a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt index 4f5e0a117b2d..421379116989 100644 --- a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt +++ b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-fg-gen3.txt @@ -275,12 +275,12 @@ Second Level Nodes - Peripherals managed by FG Gen3 driver Example ======== -pmicobalt_fg: qpnp,fg { +pmi8998_fg: qpnp,fg { compatible = "qcom,fg-gen3"; #address-cells = <1>; #size-cells = <1>; - qcom,pmic-revid = <&pmicobalt_revid>; - io-channels = <&pmicobalt_rradc 3>; + qcom,pmic-revid = <&pmi8998_revid>; + io-channels = <&pmi8998_rradc 3>; io-channel-names = "rradc_batt_id"; qcom,ki-coeff-soc-dischg = <30 60 90>; qcom,ki-coeff-med-dischg = <800 1000 1400>; diff --git a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-qnovo.txt b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-qnovo.txt index 438bd68b0e05..96b7dd517231 100644 --- a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-qnovo.txt +++ b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-qnovo.txt @@ -28,5 +28,5 @@ Example: reg = <0x1500 0x100>; interrupts = <0x2 0x15 0x0 IRQ_TYPE_NONE>; interrupt-names = "ptrain-done"; - qcom,pmic-revid = <&pmicobalt_revid>; + qcom,pmic-revid = <&pmi8998_revid>; }; diff --git a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-smb2.txt b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-smb2.txt index 7090426c68f8..9d8670c7594b 100644 --- a/Documentation/devicetree/bindings/power/qcom-charger/qpnp-smb2.txt +++ b/Documentation/devicetree/bindings/power/qcom-charger/qpnp-smb2.txt @@ -163,7 +163,7 @@ Peripheral specific properties: Example ======= -pmicobalt_charger: qcom,qpnp-smb2 { +pmi8998_charger: qcom,qpnp-smb2 { compatible = "qcom,qpnp-smb2"; #address-cells = <1>; #size-cells = <1>; diff --git a/Documentation/devicetree/bindings/qbt1000/qbt1000.txt b/Documentation/devicetree/bindings/qbt1000/qbt1000.txt index c9861e4948f9..4a18b79e9ba1 100644 --- a/Documentation/devicetree/bindings/qbt1000/qbt1000.txt +++ b/Documentation/devicetree/bindings/qbt1000/qbt1000.txt @@ -50,5 +50,5 @@ qcom,qbt1000 { <&clock_gcc clk_gcc_blsp2_ahb_clk>; clock-frequency = <15000000>; qcom,ipc-gpio = <&tlmm 121 0>; - qcom,finger-detect-gpio = <&pmcobalt_gpios 2 0>; + qcom,finger-detect-gpio = <&pm8998_gpios 2 0>; }; diff --git a/Documentation/devicetree/bindings/qdsp/msm-ssc-sensors.txt b/Documentation/devicetree/bindings/qdsp/msm-ssc-sensors.txt index ea671a1ff14a..2fb34fd16258 100644 --- a/Documentation/devicetree/bindings/qdsp/msm-ssc-sensors.txt +++ b/Documentation/devicetree/bindings/qdsp/msm-ssc-sensors.txt @@ -8,7 +8,7 @@ Required properties: - qcom,firmware-name: SLPI firmware name, must be "slpi_v1" or "slpi_v2" Example: - The following for msmcobalt version 1. + The following for msm8998 version 1. qcom,msm-ssc-sensors { compatible = "qcom,msm-ssc-sensors"; diff --git a/Documentation/devicetree/bindings/regulator/cpr3-mmss-regulator.txt b/Documentation/devicetree/bindings/regulator/cpr3-mmss-regulator.txt index 19873f877a30..baa0cd2d6f1a 100644 --- a/Documentation/devicetree/bindings/regulator/cpr3-mmss-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/cpr3-mmss-regulator.txt @@ -33,12 +33,12 @@ MMSS specific properties: "qcom,cpr3-msm8996-v3-mmss-regulator", "qcom,cpr3-msm8996-mmss-regulator", "qcom,cpr3-msm8996pro-mmss-regulator", - "qcom,cpr4-msmcobalt-v1-mmss-regulator", - "qcom,cpr4-msmcobalt-v2-mmss-regulator", - "qcom,cpr4-msmcobalt-mmss-regulator". + "qcom,cpr4-msm8998-v1-mmss-regulator", + "qcom,cpr4-msm8998-v2-mmss-regulator", + "qcom,cpr4-msm8998-mmss-regulator". If the SoC revision is not specified, then it is assumed to be the most recent revision (i.e v3 for MSM8996 and v2 - for MSMCOBALT). + for MSM8998). - clocks Usage: required @@ -55,7 +55,7 @@ MMSS specific properties: specified in the 'clocks' property. "core_clk", "iface_clk", and "bus_clk" must be specified. Note that "iface_clk" is not required for devices with compatible = - "qcom,cpr4-msmcobalt-mmss-regulator". + "qcom,cpr4-msm8998-mmss-regulator". - qcom,cpr-temp-point-map Usage: Required if qcom,corner-allow-temp-adjustment is specified @@ -77,7 +77,7 @@ MMSS specific properties: - qcom,cpr-step-quot-fixed Usage: Optional for controllers with compatible = - "qcom,cpr4-msmcobalt-mmss-regulator"; unsupported for + "qcom,cpr4-msm8998-mmss-regulator"; unsupported for all others. Value type: <u32> Definition: Fixed step quotient value used by controller for applying @@ -200,7 +200,7 @@ MMSS specific properties: - qcom,corner-allow-temp-adjustment Usage: Optional for controllers with compatible = - "qcom,cpr4-msmcobalt-mmss-regulator"; unsupported for + "qcom,cpr4-msm8998-mmss-regulator"; unsupported for all others. Value type: <prop-encoded-array> Definition: A list of integer tuples which each define the CPR diff --git a/Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt b/Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt index b286b0838643..8b806f4828bd 100644 --- a/Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/cprh-kbss-regulator.txt @@ -31,11 +31,11 @@ KBSS specific properties: Usage: required Value type: <string> Definition: should be one of the following: - "qcom,cprh-msmcobalt-v1-kbss-regulator", - "qcom,cprh-msmcobalt-v2-kbss-regulator", - "qcom,cprh-msmcobalt-kbss-regulator". + "qcom,cprh-msm8998-v1-kbss-regulator", + "qcom,cprh-msm8998-v2-kbss-regulator", + "qcom,cprh-msm8998-kbss-regulator". If the SoC revision is not specified, then it is assumed to - be the most recent revision of MSMCOBALT, i.e. v2. + be the most recent revision of MSM8998, i.e. v2. - qcom,cpr-controller-id Usage: required @@ -335,7 +335,7 @@ Example ======= apc0_cpr: cprh-ctrl@179c8000 { - compatible = "qcom,cprh-msmcobalt-kbss-regulator"; + compatible = "qcom,cprh-msm8998-kbss-regulator"; reg = <0x179c8000 0x4000>, <0x00784000 0x1000>; reg-names = "cpr_ctrl", "fuse_base"; clocks = <&clock_gcc clk_gcc_hmss_rbcpr_clk>; diff --git a/Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt b/Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt index 0545f6b7b59a..c039caca22c8 100644 --- a/Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/qpnp-labibb-regulator.txt @@ -98,7 +98,7 @@ LAB subnode required properties: - interrupts: Specify the interrupts as per the interrupt encoding. Currently "lab-vreg-ok" is required for - LCD mode in pmicobalt. For AMOLED mode, + LCD mode in pmi8998. For AMOLED mode, "lab-vreg-ok" is required only when SWIRE control is enabled and skipping 2nd SWIRE pulse is required in pmi8952/8996. diff --git a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt index c3d58ce2c864..336b9f0087a5 100644 --- a/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt +++ b/Documentation/devicetree/bindings/sound/qcom-audio-dev.txt @@ -2289,11 +2289,11 @@ Example: "SpkrRight", "SpkrLeft"; }; -* MSMCOBALT ASoC Machine driver +* MSM8998 ASoC Machine driver Required properties: -- compatible : "qcom,msmcobalt-asoc-snd-tasha" for tasha codec, - "qcom,msmcobalt-asoc-snd-tavil" for tavil codec. +- compatible : "qcom,msm8998-asoc-snd-tasha" for tasha codec, + "qcom,msm8998-asoc-snd-tavil" for tavil codec. - qcom,model : The user-visible name of this sound card. - qcom,tasha-mclk-clk-freq : MCLK frequency value for tasha codec - qcom,tavil-mclk-clk-freq : MCLK frequency value for tavil codec @@ -2333,8 +2333,8 @@ Optional properties: Example: sound-9335 { - compatible = "qcom,msmcobalt-asoc-snd"; - qcom,model = "msmcobalt-tasha-snd-card"; + compatible = "qcom,msm8998-asoc-snd"; + qcom,model = "msm8998-tasha-snd-card"; qcom,audio-routing = "RX_BIAS", "MCLK", @@ -2407,7 +2407,7 @@ Example: * MSMSTUB ASoC Machine driver Required properties: -- compatible : "qcom,msmcobalt-asoc-snd-stub" +- compatible : "qcom,msm8998-asoc-snd-stub" - qcom,model : The user-visible name of this sound card. - qcom,tasha-mclk-clk-freq : MCLK frequency value for tasha codec - asoc-platform: This is phandle list containing the references to platform device @@ -2433,8 +2433,8 @@ Optional properties: Example: sound_msm:sound-9335 { - compatible = "qcom,msmcobalt-asoc-snd"; - qcom,model = "msmcobalt-stub-snd-card"; + compatible = "qcom,msm8998-asoc-snd"; + qcom,model = "msm8998-stub-snd-card"; qcom,tasha-mclk-clk-freq = <9600000>; asoc-platform = <&pcm0>; diff --git a/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt b/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt index 3aaa339e1b22..07e4374956f1 100644 --- a/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt +++ b/Documentation/devicetree/bindings/thermal/qpnp-adc-tm.txt @@ -203,7 +203,7 @@ Example for "qcom,qpnp-adc-tm" device: Example for "qcom,qpnp-adc-tm-hc" device: /* Main Node */ - pmcobalt_adc_tm: vadc@3400 { + pm8998_adc_tm: vadc@3400 { compatible = "qcom,qpnp-adc-tm-hc"; reg = <0x3400 0x100>; #address-cells = <1>; @@ -212,7 +212,7 @@ Example for "qcom,qpnp-adc-tm-hc" device: interrupt-names = "eoc-int-en-set"; qcom,adc-bit-resolution = <15>; qcom,adc-vdd-reference = <1875>; - qcom,adc_tm-vadc = <&pmcobalt_vadc>; + qcom,adc_tm-vadc = <&pm8998_vadc>; qcom,decimation = <0>; qcom,fast-avg-setup = <0>; diff --git a/Documentation/devicetree/bindings/thermal/tsens.txt b/Documentation/devicetree/bindings/thermal/tsens.txt index 7189edbf8c5c..fc697e843fbb 100644 --- a/Documentation/devicetree/bindings/thermal/tsens.txt +++ b/Documentation/devicetree/bindings/thermal/tsens.txt @@ -29,7 +29,7 @@ Required properties: should be "qcom,msmtitanium-tsens" for titanium TSENS driver. should be "qcom,msm8937-tsens" for 8937 TSENS driver. should be "qcom,msmgold-tsens" for gold TSENS driver. - should be "qcom,msmcobalt-tsens" for cobalt TSENS driver. + should be "qcom,msm8998-tsens" for 8998 TSENS driver. should be "qcom,msmhamster-tsens" for hamster TSENS driver. should be "qcom,msmfalcon-tsens" for falcon TSENS driver. should be "qcom,msmtriton-tsens" for triton TSENS driver. diff --git a/Documentation/devicetree/bindings/usb/qpnp-pdphy.txt b/Documentation/devicetree/bindings/usb/qpnp-pdphy.txt index cd1386512bd3..f3c3163f0a3f 100644 --- a/Documentation/devicetree/bindings/usb/qpnp-pdphy.txt +++ b/Documentation/devicetree/bindings/usb/qpnp-pdphy.txt @@ -48,7 +48,7 @@ Example: qcom,qpnp-pdphy@1700 { compatible = "qcom,qpnp-pdphy"; reg = <0x1700 0x100>; - vdd-pdphy-supply = <&pmcobalt_l24>; + vdd-pdphy-supply = <&pm8998_l24>; interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>, <0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>, <0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>, diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 88346d84096d..730b76846c9d 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -102,35 +102,35 @@ dtb-$(CONFIG_ARCH_MSM8996) += msm8996-v2-pmi8994-cdp.dtb \ apq8096-v3-pmi8996-mdm9x55-slimbus-mtp.dtb \ apq8096-v3-pmi8996-dragonboard.dtb -dtb-$(CONFIG_ARCH_MSMCOBALT) += msmcobalt-sim.dtb \ - msmcobalt-rumi.dtb \ - msmcobalt-cdp.dtb \ - msmcobalt-mtp.dtb \ - msmcobalt-qrd.dtb \ - msmcobalt-v2-sim.dtb \ - msmcobalt-v2-rumi.dtb \ - msmcobalt-v2-mtp.dtb \ - msmcobalt-v2-cdp.dtb \ - msmcobalt-v2-qrd.dtb \ - msmcobalt-qrd-skuk.dtb \ - msmcobalt-v2-qrd-skuk.dtb \ - msmcobalt-qrd-vr1.dtb \ - msmcobalt-v2-qrd-vr1.dtb \ - apqcobalt-mtp.dtb \ - apqcobalt-cdp.dtb \ - apqcobalt-v2-mtp.dtb \ - apqcobalt-v2-cdp.dtb \ - apqcobalt-v2-qrd.dtb \ - msmcobalt-v2.1-mtp.dtb \ - msmcobalt-v2.1-cdp.dtb \ - msmcobalt-v2.1-qrd.dtb \ - apqcobalt-v2.1-mtp.dtb \ - apqcobalt-v2.1-cdp.dtb \ - apqcobalt-v2.1-qrd.dtb \ - apqcobalt-v2.1-mediabox.dtb \ - msmcobalt-v2.1-interposer-msmfalcon-cdp.dtb \ - msmcobalt-v2.1-interposer-msmfalcon-mtp.dtb \ - msmcobalt-v2.1-interposer-msmfalcon-qrd.dtb +dtb-$(CONFIG_ARCH_MSM8998) += msm8998-sim.dtb \ + msm8998-rumi.dtb \ + msm8998-cdp.dtb \ + msm8998-mtp.dtb \ + msm8998-qrd.dtb \ + msm8998-v2-sim.dtb \ + msm8998-v2-rumi.dtb \ + msm8998-v2-mtp.dtb \ + msm8998-v2-cdp.dtb \ + msm8998-v2-qrd.dtb \ + msm8998-qrd-skuk.dtb \ + msm8998-v2-qrd-skuk.dtb \ + msm8998-qrd-vr1.dtb \ + msm8998-v2-qrd-vr1.dtb \ + apq8998-mtp.dtb \ + apq8998-cdp.dtb \ + apq8998-v2-mtp.dtb \ + apq8998-v2-cdp.dtb \ + apq8998-v2-qrd.dtb \ + msm8998-v2.1-mtp.dtb \ + msm8998-v2.1-cdp.dtb \ + msm8998-v2.1-qrd.dtb \ + apq8998-v2.1-mtp.dtb \ + apq8998-v2.1-cdp.dtb \ + apq8998-v2.1-qrd.dtb \ + apq8998-v2.1-mediabox.dtb \ + msm8998-v2.1-interposer-msmfalcon-cdp.dtb \ + msm8998-v2.1-interposer-msmfalcon-mtp.dtb \ + msm8998-v2.1-interposer-msmfalcon-qrd.dtb dtb-$(CONFIG_ARCH_MSMHAMSTER) += msmhamster-rumi.dtb diff --git a/arch/arm/boot/dts/qcom/apqcobalt-cdp.dts b/arch/arm/boot/dts/qcom/apq8998-cdp.dts index 1f0066d15aaa..8acd2dabe18a 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt-cdp.dts +++ b/arch/arm/boot/dts/qcom/apq8998-cdp.dts @@ -12,11 +12,11 @@ /dts-v1/; -#include "apqcobalt.dtsi" -#include "msmcobalt-cdp.dtsi" +#include "apq8998.dtsi" +#include "msm8998-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT CDP"; - compatible = "qcom,apqcobalt-cdp", "qcom,apqcobalt", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. APQ 8998 CDP"; + compatible = "qcom,apq8998-cdp", "qcom,apq8998", "qcom,cdp"; qcom,board-id = <1 0>; }; diff --git a/arch/arm/boot/dts/qcom/apqcobalt-mtp.dts b/arch/arm/boot/dts/qcom/apq8998-mtp.dts index b63e9e027797..5bed816f77d6 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt-mtp.dts +++ b/arch/arm/boot/dts/qcom/apq8998-mtp.dts @@ -12,11 +12,11 @@ /dts-v1/; -#include "apqcobalt.dtsi" -#include "msmcobalt-mtp.dtsi" +#include "apq8998.dtsi" +#include "msm8998-mtp.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT MTP"; - compatible = "qcom,apqcobalt-mtp", "qcom,apqcobalt", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. APQ 8998 MTP"; + compatible = "qcom,apq8998-mtp", "qcom,apq8998", "qcom,mtp"; qcom,board-id = <8 0>; }; diff --git a/arch/arm/boot/dts/qcom/apqcobalt-v2-cdp.dts b/arch/arm/boot/dts/qcom/apq8998-v2-cdp.dts index 69eb9ef15c46..397892dbb540 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt-v2-cdp.dts +++ b/arch/arm/boot/dts/qcom/apq8998-v2-cdp.dts @@ -12,11 +12,11 @@ /dts-v1/; -#include "apqcobalt-v2.dtsi" -#include "msmcobalt-cdp.dtsi" +#include "apq8998-v2.dtsi" +#include "msm8998-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT V2 CDP"; - compatible = "qcom,apqcobalt-cdp", "qcom,apqcobalt", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. APQ 8998 V2 CDP"; + compatible = "qcom,apq8998-cdp", "qcom,apq8998", "qcom,cdp"; qcom,board-id = <1 0>; }; diff --git a/arch/arm/boot/dts/qcom/apqcobalt-v2-mtp.dts b/arch/arm/boot/dts/qcom/apq8998-v2-mtp.dts index 8587b56b289a..4dc735c8d182 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt-v2-mtp.dts +++ b/arch/arm/boot/dts/qcom/apq8998-v2-mtp.dts @@ -12,11 +12,11 @@ /dts-v1/; -#include "apqcobalt-v2.dtsi" -#include "msmcobalt-mtp.dtsi" +#include "apq8998-v2.dtsi" +#include "msm8998-mtp.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT V2 MTP"; - compatible = "qcom,apqcobalt-mtp", "qcom,apqcobalt", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. APQ 8998 V2 MTP"; + compatible = "qcom,apq8998-mtp", "qcom,apq8998", "qcom,mtp"; qcom,board-id = <8 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-qrd.dts b/arch/arm/boot/dts/qcom/apq8998-v2-qrd.dts index 81c17c2077e4..4f7efa7b4357 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2-qrd.dts +++ b/arch/arm/boot/dts/qcom/apq8998-v2-qrd.dts @@ -12,11 +12,11 @@ /dts-v1/; -#include "msmcobalt-v2.dtsi" -#include "msmcobalt-qrd.dtsi" +#include "apq8998-v2.dtsi" +#include "msm8998-qrd.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT v2 QRD"; - compatible = "qcom,msmcobalt-qrd", "qcom,msmcobalt", "qcom,qrd"; + model = "Qualcomm Technologies, Inc. APQ 8998 V2 QRD"; + compatible = "qcom,apq8998-qrd", "qcom,apq8998", "qcom,qrd"; qcom,board-id = <11 0>; }; diff --git a/arch/arm/boot/dts/qcom/apqcobalt-v2.1-cdp.dts b/arch/arm/boot/dts/qcom/apq8998-v2.1-cdp.dts index f0ab8e0afc78..94c6031854fa 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt-v2.1-cdp.dts +++ b/arch/arm/boot/dts/qcom/apq8998-v2.1-cdp.dts @@ -12,11 +12,11 @@ /dts-v1/; -#include "apqcobalt-v2.1.dtsi" -#include "msmcobalt-cdp.dtsi" +#include "apq8998-v2.1.dtsi" +#include "msm8998-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT V2.1 CDP"; - compatible = "qcom,apqcobalt-cdp", "qcom,apqcobalt", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. APQ 8998 V2.1 CDP"; + compatible = "qcom,apq8998-cdp", "qcom,apq8998", "qcom,cdp"; qcom,board-id = <1 0>; }; diff --git a/arch/arm/boot/dts/qcom/apqcobalt-v2.1-mediabox.dts b/arch/arm/boot/dts/qcom/apq8998-v2.1-mediabox.dts index 86df23dbb486..bc60d9a08c0b 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt-v2.1-mediabox.dts +++ b/arch/arm/boot/dts/qcom/apq8998-v2.1-mediabox.dts @@ -12,12 +12,12 @@ /dts-v1/; -#include "apqcobalt-v2.1.dtsi" -#include "msmcobalt-cdp.dtsi" +#include "apq8998-v2.1.dtsi" +#include "msm8998-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT V2.1 mediabox"; - compatible = "qcom,apqcobalt-cdp", "qcom,apqcobalt", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. APQ 8998 V2.1 mediabox"; + compatible = "qcom,apq8998-cdp", "qcom,apq8998", "qcom,cdp"; qcom,board-id = <8 1>; }; diff --git a/arch/arm/boot/dts/qcom/apqcobalt-v2.1-mtp.dts b/arch/arm/boot/dts/qcom/apq8998-v2.1-mtp.dts index e23134f8897b..fa4e28e515b5 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt-v2.1-mtp.dts +++ b/arch/arm/boot/dts/qcom/apq8998-v2.1-mtp.dts @@ -12,11 +12,11 @@ /dts-v1/; -#include "apqcobalt-v2.1.dtsi" -#include "msmcobalt-mtp.dtsi" +#include "apq8998-v2.1.dtsi" +#include "msm8998-mtp.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT V2.1 MTP"; - compatible = "qcom,apqcobalt-mtp", "qcom,apqcobalt", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. APQ 8998 V2.1 MTP"; + compatible = "qcom,apq8998-mtp", "qcom,apq8998", "qcom,mtp"; qcom,board-id = <8 0>; }; diff --git a/arch/arm/boot/dts/qcom/apqcobalt-v2-qrd.dts b/arch/arm/boot/dts/qcom/apq8998-v2.1-qrd.dts index 5a26313f9d59..6a91b966a9b7 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt-v2-qrd.dts +++ b/arch/arm/boot/dts/qcom/apq8998-v2.1-qrd.dts @@ -12,11 +12,11 @@ /dts-v1/; -#include "apqcobalt-v2.dtsi" -#include "msmcobalt-qrd.dtsi" +#include "apq8998-v2.1.dtsi" +#include "msm8998-qrd.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT V2 QRD"; - compatible = "qcom,apqcobalt-qrd", "qcom,apqcobalt", "qcom,qrd"; + model = "Qualcomm Technologies, Inc. APQ 8998 V2.1 QRD"; + compatible = "qcom,apq8998-qrd", "qcom,apq8998", "qcom,qrd"; qcom,board-id = <11 0>; }; diff --git a/arch/arm/boot/dts/qcom/apqcobalt-v2.1.dtsi b/arch/arm/boot/dts/qcom/apq8998-v2.1.dtsi index 5a49afecd60b..c7d44816c7d6 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt-v2.1.dtsi +++ b/arch/arm/boot/dts/qcom/apq8998-v2.1.dtsi @@ -10,9 +10,9 @@ * GNU General Public License for more details. */ -#include "msmcobalt-v2.1.dtsi" +#include "msm8998-v2.1.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT V2.1"; + model = "Qualcomm Technologies, Inc. APQ 8998 V2.1"; qcom,msm-id = <319 0x20001>; }; diff --git a/arch/arm/boot/dts/qcom/apqcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/apq8998-v2.dtsi index 58abca9859d9..2be3db45bf37 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt-v2.dtsi +++ b/arch/arm/boot/dts/qcom/apq8998-v2.dtsi @@ -10,9 +10,9 @@ * GNU General Public License for more details. */ -#include "msmcobalt-v2.dtsi" +#include "msm8998-v2.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT V2"; + model = "Qualcomm Technologies, Inc. APQ 8998 V2"; qcom,msm-id = <319 0x20000>; }; diff --git a/arch/arm/boot/dts/qcom/apqcobalt.dtsi b/arch/arm/boot/dts/qcom/apq8998.dtsi index dcc1601245f5..99d3459e39ce 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/apq8998.dtsi @@ -10,10 +10,10 @@ * GNU General Public License for more details. */ -#include "msmcobalt.dtsi" +#include "msm8998.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT"; + model = "Qualcomm Technologies, Inc. APQ 8998"; qcom,msm-id = <319 0x10000>; }; diff --git a/arch/arm/boot/dts/qcom/batterydata-qrd-skuk-4v4-3000mah.dtsi b/arch/arm/boot/dts/qcom/batterydata-qrd-skuk-4v4-3000mah.dtsi index 8bf98d83d381..ba3b33361ba1 100644 --- a/arch/arm/boot/dts/qcom/batterydata-qrd-skuk-4v4-3000mah.dtsi +++ b/arch/arm/boot/dts/qcom/batterydata-qrd-skuk-4v4-3000mah.dtsi @@ -10,12 +10,12 @@ * GNU General Public License for more details. */ -qcom,qrd_msmcobalt_skuk_3000mah { +qcom,qrd_msm8998_skuk_3000mah { qcom,max-voltage-uv = <4400000>; qcom,nom-batt-capacity-mah = <3000>; qcom,batt-id-kohm = <68>; qcom,battery-beta = <3380>; - qcom,battery-type = "qrd_msmcobalt_skuk_300mah"; + qcom,battery-type = "qrd_msm8998_skuk_300mah"; qcom,checksum = <0x0F19>; qcom,fg-profile-data = [ 6F 1F B2 05 diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi index 1ad8f99e4186..0ba86e81887f 100644 --- a/arch/arm/boot/dts/qcom/msm-arm-smmu-cobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi @@ -10,7 +10,7 @@ * GNU General Public License for more details. */ -#include <dt-bindings/clock/msm-clocks-cobalt.h> +#include <dt-bindings/clock/msm-clocks-8998.h> #include <dt-bindings/msm/msm-bus-ids.h> #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-cobalt.dtsi b/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-8998.dtsi index 4fbf1e126842..4fbf1e126842 100644 --- a/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-cobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msm-arm-smmu-impl-defs-8998.dtsi diff --git a/arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi b/arch/arm/boot/dts/qcom/msm-gdsc-8998.dtsi index c86351e48d5f..c86351e48d5f 100644 --- a/arch/arm/boot/dts/qcom/msm-gdsc-cobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msm-gdsc-8998.dtsi diff --git a/arch/arm/boot/dts/qcom/msm-pmcobalt-rpm-regulator.dtsi b/arch/arm/boot/dts/qcom/msm-pm8998-rpm-regulator.dtsi index 7243a6b1d6d4..5ad84dbfcff6 100644 --- a/arch/arm/boot/dts/qcom/msm-pmcobalt-rpm-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pm8998-rpm-regulator.dtsi @@ -11,7 +11,7 @@ */ &rpm_bus { - /* PMCOBALT S1 + S6 = VDD_CX supply */ + /* PM8998 S1 + S6 = VDD_CX supply */ rpm-regulator-smpa1 { compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "rwcx"; @@ -21,7 +21,7 @@ regulator-s1 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s1"; + regulator-name = "pm8998_s1"; qcom,set = <3>; status = "disabled"; }; @@ -36,7 +36,7 @@ regulator-s2 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s2"; + regulator-name = "pm8998_s2"; qcom,set = <3>; status = "disabled"; }; @@ -51,7 +51,7 @@ regulator-s3 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s3"; + regulator-name = "pm8998_s3"; qcom,set = <3>; status = "disabled"; }; @@ -66,7 +66,7 @@ regulator-s4 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s4"; + regulator-name = "pm8998_s4"; qcom,set = <3>; status = "disabled"; }; @@ -81,7 +81,7 @@ regulator-s5 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s5"; + regulator-name = "pm8998_s5"; qcom,set = <3>; status = "disabled"; }; @@ -96,7 +96,7 @@ regulator-s7 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s7"; + regulator-name = "pm8998_s7"; qcom,set = <3>; status = "disabled"; }; @@ -111,13 +111,13 @@ regulator-s8 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s8"; + regulator-name = "pm8998_s8"; qcom,set = <3>; status = "disabled"; }; }; - /* PMCOBALT S9 = VDD_MX supply */ + /* PM8998 S9 = VDD_MX supply */ rpm-regulator-smpa9 { compatible = "qcom,rpm-smd-regulator-resource"; qcom,resource-name = "rwmx"; @@ -127,7 +127,7 @@ regulator-s9 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s9"; + regulator-name = "pm8998_s9"; qcom,set = <3>; status = "disabled"; }; @@ -142,7 +142,7 @@ regulator-l1 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l1"; + regulator-name = "pm8998_l1"; qcom,set = <3>; status = "disabled"; }; @@ -157,7 +157,7 @@ regulator-l2 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l2"; + regulator-name = "pm8998_l2"; qcom,set = <3>; status = "disabled"; }; @@ -172,7 +172,7 @@ regulator-l3 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l3"; + regulator-name = "pm8998_l3"; qcom,set = <3>; status = "disabled"; }; @@ -187,7 +187,7 @@ regulator-l4 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l4"; + regulator-name = "pm8998_l4"; qcom,set = <3>; status = "disabled"; }; @@ -202,7 +202,7 @@ regulator-l5 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l5"; + regulator-name = "pm8998_l5"; qcom,set = <3>; status = "disabled"; }; @@ -217,7 +217,7 @@ regulator-l6 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l6"; + regulator-name = "pm8998_l6"; qcom,set = <3>; status = "disabled"; }; @@ -232,7 +232,7 @@ regulator-l7 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l7"; + regulator-name = "pm8998_l7"; qcom,set = <3>; status = "disabled"; }; @@ -247,7 +247,7 @@ regulator-l8 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l8"; + regulator-name = "pm8998_l8"; qcom,set = <3>; status = "disabled"; }; @@ -262,7 +262,7 @@ regulator-l9 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l9"; + regulator-name = "pm8998_l9"; qcom,set = <3>; status = "disabled"; }; @@ -277,7 +277,7 @@ regulator-l10 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l10"; + regulator-name = "pm8998_l10"; qcom,set = <3>; status = "disabled"; }; @@ -292,7 +292,7 @@ regulator-l11 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l11"; + regulator-name = "pm8998_l11"; qcom,set = <3>; status = "disabled"; }; @@ -307,7 +307,7 @@ regulator-l12 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l12"; + regulator-name = "pm8998_l12"; qcom,set = <3>; status = "disabled"; }; @@ -322,7 +322,7 @@ regulator-l13 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l13"; + regulator-name = "pm8998_l13"; qcom,set = <3>; status = "disabled"; }; @@ -337,7 +337,7 @@ regulator-l14 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l14"; + regulator-name = "pm8998_l14"; qcom,set = <3>; status = "disabled"; }; @@ -352,7 +352,7 @@ regulator-l15 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l15"; + regulator-name = "pm8998_l15"; qcom,set = <3>; status = "disabled"; }; @@ -367,7 +367,7 @@ regulator-l16 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l16"; + regulator-name = "pm8998_l16"; qcom,set = <3>; status = "disabled"; }; @@ -382,7 +382,7 @@ regulator-l17 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l17"; + regulator-name = "pm8998_l17"; qcom,set = <3>; status = "disabled"; }; @@ -397,7 +397,7 @@ regulator-l18 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l18"; + regulator-name = "pm8998_l18"; qcom,set = <3>; status = "disabled"; }; @@ -412,7 +412,7 @@ regulator-l19 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l19"; + regulator-name = "pm8998_l19"; qcom,set = <3>; status = "disabled"; }; @@ -427,7 +427,7 @@ regulator-l20 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l20"; + regulator-name = "pm8998_l20"; qcom,set = <3>; status = "disabled"; }; @@ -442,7 +442,7 @@ regulator-l21 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l21"; + regulator-name = "pm8998_l21"; qcom,set = <3>; status = "disabled"; }; @@ -457,7 +457,7 @@ regulator-l22 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l22"; + regulator-name = "pm8998_l22"; qcom,set = <3>; status = "disabled"; }; @@ -472,7 +472,7 @@ regulator-l23 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l23"; + regulator-name = "pm8998_l23"; qcom,set = <3>; status = "disabled"; }; @@ -487,7 +487,7 @@ regulator-l24 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l24"; + regulator-name = "pm8998_l24"; qcom,set = <3>; status = "disabled"; }; @@ -502,7 +502,7 @@ regulator-l25 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l25"; + regulator-name = "pm8998_l25"; qcom,set = <3>; status = "disabled"; }; @@ -517,7 +517,7 @@ regulator-l26 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l26"; + regulator-name = "pm8998_l26"; qcom,set = <3>; status = "disabled"; }; @@ -532,7 +532,7 @@ regulator-l27 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l27"; + regulator-name = "pm8998_l27"; qcom,set = <3>; status = "disabled"; }; @@ -547,7 +547,7 @@ regulator-l28 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l28"; + regulator-name = "pm8998_l28"; qcom,set = <3>; status = "disabled"; }; @@ -562,7 +562,7 @@ regulator-lvs1 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_lvs1"; + regulator-name = "pm8998_lvs1"; qcom,set = <3>; status = "disabled"; }; @@ -577,7 +577,7 @@ regulator-lvs2 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_lvs2"; + regulator-name = "pm8998_lvs2"; qcom,set = <3>; status = "disabled"; }; @@ -592,7 +592,7 @@ regulator-bob { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmicobalt_bob"; + regulator-name = "pm8998_bob"; qcom,set = <3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/qcom/msm-pmcobalt.dtsi b/arch/arm/boot/dts/qcom/msm-pm8998.dtsi index eb5208a8d983..e91fc68d2c52 100644 --- a/arch/arm/boot/dts/qcom/msm-pmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pm8998.dtsi @@ -14,13 +14,13 @@ #include <dt-bindings/interrupt-controller/irq.h> &spmi_bus { - qcom,pmcobalt@0 { + qcom,pm8998@0 { compatible ="qcom,spmi-pmic"; reg = <0x0 SPMI_USID>; #address-cells = <2>; #size-cells = <0>; - pmcobalt_revid: qcom,revid@100 { + pm8998_revid: qcom,revid@100 { compatible = "qcom,qpnp-revid"; reg = <0x100 0x100>; }; @@ -69,18 +69,18 @@ compatible = "qcom,qpnp-temp-alarm"; reg = <0x2400 0x100>; interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - label = "pmcobalt_tz"; + label = "pm8998_tz"; qcom,channel-num = <6>; - qcom,temp_alarm-vadc = <&pmcobalt_vadc>; + qcom,temp_alarm-vadc = <&pm8998_vadc>; }; - pmcobalt_gpios: gpios { + pm8998_gpios: gpios { compatible = "qcom,qpnp-pin"; gpio-controller; #gpio-cells = <2>; #address-cells = <1>; #size-cells = <1>; - label = "pmcobalt-gpio"; + label = "pm8998-gpio"; gpio@c000 { reg = <0xc000 0x100>; @@ -239,28 +239,28 @@ }; }; - pmcobalt_coincell: qcom,coincell@2800 { + pm8998_coincell: qcom,coincell@2800 { compatible = "qcom,qpnp-coincell"; reg = <0x2800 0x100>; }; - pmcobalt_rtc: qcom,pmcobalt_rtc { + pm8998_rtc: qcom,pm8998_rtc { compatible = "qcom,qpnp-rtc"; #address-cells = <1>; #size-cells = <1>; qcom,qpnp-rtc-write = <0>; qcom,qpnp-rtc-alarm-pwrup = <0>; - qcom,pmcobalt_rtc_rw@6000 { + qcom,pm8998_rtc_rw@6000 { reg = <0x6000 0x100>; }; - qcom,pmcobalt_rtc_alarm@6100 { + qcom,pm8998_rtc_alarm@6100 { reg = <0x6100 0x100>; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; }; - pmcobalt_vadc: vadc@3100 { + pm8998_vadc: vadc@3100 { compatible = "qcom,qpnp-vadc-hc"; reg = <0x3100 0x100>; #address-cells = <1>; @@ -307,7 +307,7 @@ }; }; - pmcobalt_adc_tm: vadc@3400 { + pm8998_adc_tm: vadc@3400 { compatible = "qcom,qpnp-adc-tm-hc"; reg = <0x3400 0x100>; #address-cells = <1>; @@ -316,13 +316,13 @@ interrupt-names = "eoc-int-en-set"; qcom,adc-bit-resolution = <15>; qcom,adc-vdd-reference = <1875>; - qcom,adc_tm-vadc = <&pmcobalt_vadc>; + qcom,adc_tm-vadc = <&pm8998_vadc>; qcom,decimation = <0>; qcom,fast-avg-setup = <0>; }; }; - qcom,pmcobalt@1 { + qcom,pm8998@1 { compatible ="qcom,spmi-pmic"; reg = <0x1 SPMI_USID>; #address-cells = <2>; diff --git a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi b/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi index baeda86bc976..725c129a28da 100644 --- a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msm-pmi8998.dtsi @@ -14,13 +14,13 @@ #include <dt-bindings/spmi/spmi.h> &spmi_bus { - qcom,pmicobalt@2 { + qcom,pmi8998@2 { compatible = "qcom,spmi-pmic"; reg = <0x2 SPMI_USID>; #address-cells = <2>; #size-cells = <0>; - pmicobalt_revid: qcom,revid@100 { + pmi8998_revid: qcom,revid@100 { compatible = "qcom,qpnp-revid"; reg = <0x100 0x100>; qcom,fab-id-valid; @@ -35,16 +35,16 @@ compatible = "qcom,qpnp-temp-alarm"; reg = <0x2400 0x100>; interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_RISING>; - label = "pmicobalt_tz"; + label = "pmi8998_tz"; }; - pmicobalt_gpios: gpios { + pmi8998_gpios: gpios { compatible = "qcom,qpnp-pin"; gpio-controller; #gpio-cells = <2>; #address-cells = <1>; #size-cells = <1>; - label = "pmicobalt-gpio"; + label = "pmi8998-gpio"; gpio@c000 { reg = <0xc000 0x100>; @@ -136,20 +136,20 @@ reg = <0x1500 0x100>; interrupts = <0x2 0x15 0x0 IRQ_TYPE_NONE>; interrupt-names = "ptrain-done"; - qcom,pmic-revid = <&pmicobalt_revid>; + qcom,pmic-revid = <&pmi8998_revid>; }; - pmicobalt_charger: qcom,qpnp-smb2 { + pmi8998_charger: qcom,qpnp-smb2 { compatible = "qcom,qpnp-smb2"; #address-cells = <1>; #size-cells = <1>; - qcom,pmic-revid = <&pmicobalt_revid>; + qcom,pmic-revid = <&pmi8998_revid>; - io-channels = <&pmicobalt_rradc 8>, - <&pmicobalt_rradc 10>, - <&pmicobalt_rradc 3>, - <&pmicobalt_rradc 4>; + io-channels = <&pmi8998_rradc 8>, + <&pmi8998_rradc 10>, + <&pmi8998_rradc 3>, + <&pmi8998_rradc 4>; io-channel-names = "charger_temp", "charger_temp_max", "usbin_i", @@ -268,10 +268,10 @@ }; }; - pmicobalt_pdphy: qcom,usb-pdphy@1700 { + pmi8998_pdphy: qcom,usb-pdphy@1700 { compatible = "qcom,qpnp-pdphy"; reg = <0x1700 0x100>; - vdd-pdphy-supply = <&pmcobalt_l24>; + vdd-pdphy-supply = <&pm8998_l24>; vbus-supply = <&smb2_vbus>; vconn-supply = <&smb2_vconn>; interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>, @@ -305,21 +305,21 @@ qcom,ibat-polling-delay-ms = <100>; }; - pmicobalt_rradc: rradc@4500 { + pmi8998_rradc: rradc@4500 { compatible = "qcom,rradc"; reg = <0x4500 0x100>; #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; - qcom,pmic-revid = <&pmicobalt_revid>; + qcom,pmic-revid = <&pmi8998_revid>; }; - pmicobalt_fg: qpnp,fg { + pmi8998_fg: qpnp,fg { compatible = "qcom,fg-gen3"; #address-cells = <1>; #size-cells = <1>; - qcom,pmic-revid = <&pmicobalt_revid>; - io-channels = <&pmicobalt_rradc 0>; + qcom,pmic-revid = <&pmi8998_revid>; + io-channels = <&pmi8998_rradc 0>; io-channel-names = "rradc_batt_id"; qcom,fg-esr-timer-awake = <96>; qcom,fg-esr-timer-asleep = <256>; @@ -376,13 +376,13 @@ }; }; - qcom,pmicobalt@3 { + qcom,pmi8998@3 { compatible ="qcom,spmi-pmic"; reg = <0x3 SPMI_USID>; #address-cells = <2>; #size-cells = <0>; - pmicobalt_pwm_1: pwm@b100 { + pmi8998_pwm_1: pwm@b100 { compatible = "qcom,qpnp-pwm"; reg = <0xb100 0x100>, <0xb042 0x7e>; @@ -396,7 +396,7 @@ status = "disabled"; }; - pmicobalt_pwm_2: pwm@b200 { + pmi8998_pwm_2: pwm@b200 { compatible = "qcom,qpnp-pwm"; reg = <0xb200 0x100>, <0xb042 0x7e>; @@ -410,7 +410,7 @@ status = "disabled"; }; - pmicobalt_pwm_3: pwm@b300 { + pmi8998_pwm_3: pwm@b300 { compatible = "qcom,qpnp-pwm"; reg = <0xb300 0x100>, <0xb042 0x7e>; @@ -423,7 +423,7 @@ #pwm-cells = <2>; }; - pmicobalt_pwm_4: pwm@b400 { + pmi8998_pwm_4: pwm@b400 { compatible = "qcom,qpnp-pwm"; reg = <0xb400 0x100>, <0xb042 0x7e>; @@ -436,7 +436,7 @@ #pwm-cells = <2>; }; - pmicobalt_pwm_5: pwm@b500 { + pmi8998_pwm_5: pwm@b500 { compatible = "qcom,qpnp-pwm"; reg = <0xb500 0x100>, <0xb042 0x7e>; @@ -449,7 +449,7 @@ #pwm-cells = <2>; }; - pmicobalt_pwm_6: pwm@b600 { + pmi8998_pwm_6: pwm@b600 { compatible = "qcom,qpnp-pwm"; reg = <0xb600 0x100>, <0xb042 0x7e>; @@ -473,7 +473,7 @@ label = "rgb"; qcom,id = <3>; qcom,mode = "pwm"; - pwms = <&pmicobalt_pwm_5 0 0>; + pwms = <&pmi8998_pwm_5 0 0>; qcom,pwm-us = <1000>; qcom,max-current = <12>; qcom,default-state = "off"; @@ -486,7 +486,7 @@ label = "rgb"; qcom,id = <4>; qcom,mode = "pwm"; - pwms = <&pmicobalt_pwm_4 0 0>; + pwms = <&pmi8998_pwm_4 0 0>; qcom,pwm-us = <1000>; qcom,max-current = <12>; qcom,default-state = "off"; @@ -498,7 +498,7 @@ label = "rgb"; qcom,id = <5>; qcom,mode = "pwm"; - pwms = <&pmicobalt_pwm_3 0 0>; + pwms = <&pmi8998_pwm_3 0 0>; qcom,pwm-us = <1000>; qcom,max-current = <12>; qcom,default-state = "off"; @@ -511,7 +511,7 @@ compatible = "qcom,qpnp-labibb-regulator"; #address-cells = <1>; #size-cells = <1>; - qcom,pmic-revid = <&pmicobalt_revid>; + qcom,pmic-revid = <&pmi8998_revid>; status = "disabled"; ibb_regulator: qcom,ibb@dc00 { @@ -582,7 +582,7 @@ }; }; - pmicobalt_wled: qcom,leds@d800 { + pmi8998_wled: qcom,leds@d800 { compatible = "qcom,qpnp-wled"; reg = <0xd800 0x100>, <0xd900 0x100>, @@ -612,11 +612,11 @@ qcom,en-phase-stag; qcom,led-strings-list = [00 01 02 03]; qcom,en-ext-pfet-sc-pro; - qcom,pmic-revid = <&pmicobalt_revid>; + qcom,pmic-revid = <&pmi8998_revid>; qcom,loop-auto-gm-en; }; - pmicobalt_haptics: qcom,haptic@c000 { + pmi8998_haptics: qcom,haptic@c000 { status = "disabled"; compatible = "qcom,qpnp-haptic"; reg = <0xc000 0x100>; @@ -658,9 +658,9 @@ qcom,thermal-derate-en; qcom,thermal-derate-current = <200 500 1000>; qcom,isc-delay = <192>; - qcom,pmic-revid = <&pmicobalt_revid>; + qcom,pmic-revid = <&pmi8998_revid>; - pmicobalt_flash0: qcom,flash_0 { + pmi8998_flash0: qcom,flash_0 { label = "flash"; qcom,led-name = "led:flash_0"; qcom,max-current = <1500>; @@ -673,7 +673,7 @@ qcom,hdrm-vol-hi-lo-win-mv = <100>; }; - pmicobalt_flash1: qcom,flash_1 { + pmi8998_flash1: qcom,flash_1 { label = "flash"; qcom,led-name = "led:flash_1"; qcom,max-current = <1500>; @@ -686,7 +686,7 @@ qcom,hdrm-vol-hi-lo-win-mv = <100>; }; - pmicobalt_flash2: qcom,flash_2 { + pmi8998_flash2: qcom,flash_2 { label = "flash"; qcom,led-name = "led:flash_2"; qcom,max-current = <750>; @@ -702,7 +702,7 @@ pinctrl-1 = <&led_disable>; }; - pmicobalt_torch0: qcom,torch_0 { + pmi8998_torch0: qcom,torch_0 { label = "torch"; qcom,led-name = "led:torch_0"; qcom,max-current = <500>; @@ -714,7 +714,7 @@ qcom,hdrm-vol-hi-lo-win-mv = <100>; }; - pmicobalt_torch1: qcom,torch_1 { + pmi8998_torch1: qcom,torch_1 { label = "torch"; qcom,led-name = "led:torch_1"; qcom,max-current = <500>; @@ -726,7 +726,7 @@ qcom,hdrm-vol-hi-lo-win-mv = <100>; }; - pmicobalt_torch2: qcom,torch_2 { + pmi8998_torch2: qcom,torch_2 { label = "torch"; qcom,led-name = "led:torch_2"; qcom,max-current = <500>; @@ -741,14 +741,14 @@ pinctrl-1 = <&led_disable>; }; - pmicobalt_switch0: qcom,led_switch_0 { + pmi8998_switch0: qcom,led_switch_0 { label = "switch"; qcom,led-name = "led:switch_0"; qcom,led-mask = <3>; qcom,default-led-trigger = "switch0_trigger"; }; - pmicobalt_switch1: qcom,led_switch_1 { + pmi8998_switch1: qcom,led_switch_1 { label = "switch"; qcom,led-name = "led:switch_1"; qcom,led-mask = <4>; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi b/arch/arm/boot/dts/qcom/msm8998-audio.dtsi index ca12a520c2aa..506e37c2349a 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-audio.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-audio.dtsi @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#include "msmcobalt-wsa881x.dtsi" +#include "msm8998-wsa881x.dtsi" &msm_audio_ion { qcom,smmu-version = <2>; @@ -32,8 +32,8 @@ }; sound-9335 { - compatible = "qcom,msmcobalt-asoc-snd-tasha"; - qcom,model = "msmcobalt-tasha-snd-card"; + compatible = "qcom,msm8998-asoc-snd-tasha"; + qcom,model = "msm8998-tasha-snd-card"; qcom,ext-disp-audio-rx; qcom,wcn-btfm; qcom,mi2s-audio-intf; @@ -145,8 +145,8 @@ }; sound-tavil { - compatible = "qcom,msmcobalt-asoc-snd-tavil"; - qcom,model = "msmcobalt-tavil-snd-card"; + compatible = "qcom,msm8998-asoc-snd-tavil"; + qcom,model = "msm8998-tavil-snd-card"; qcom,ext-disp-audio-rx; qcom,wcn-btfm; qcom,mi2s-audio-intf; @@ -294,7 +294,7 @@ clock_audio: audio_ext_clk { status = "ok"; compatible = "qcom,audio-ref-clk"; - qcom,audio-ref-clk-gpio = <&pmcobalt_gpios 13 0>; + qcom,audio-ref-clk-gpio = <&pm8998_gpios 13 0>; clock-names = "osr_clk"; clocks = <&clock_gcc clk_div_clk1>; qcom,node_has_rpm_clock; @@ -347,23 +347,23 @@ clocks = <&clock_audio clk_audio_pmi_clk>, <&clock_audio clk_audio_ap_clk2>; - cdc-vdd-buck-supply = <&pmcobalt_s4>; + cdc-vdd-buck-supply = <&pm8998_s4>; qcom,cdc-vdd-buck-voltage = <1800000 1800000>; qcom,cdc-vdd-buck-current = <650000>; - cdc-buck-sido-supply = <&pmcobalt_s4>; + cdc-buck-sido-supply = <&pm8998_s4>; qcom,cdc-buck-sido-voltage = <1800000 1800000>; qcom,cdc-buck-sido-current = <250000>; - cdc-vdd-tx-h-supply = <&pmcobalt_s4>; + cdc-vdd-tx-h-supply = <&pm8998_s4>; qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; qcom,cdc-vdd-tx-h-current = <25000>; - cdc-vdd-rx-h-supply = <&pmcobalt_s4>; + cdc-vdd-rx-h-supply = <&pm8998_s4>; qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; qcom,cdc-vdd-rx-h-current = <25000>; - cdc-vddpx-1-supply = <&pmcobalt_s4>; + cdc-vddpx-1-supply = <&pm8998_s4>; qcom,cdc-vddpx-1-voltage = <1800000 1800000>; qcom,cdc-vddpx-1-current = <10000>; @@ -400,23 +400,23 @@ clock-names = "wcd_clk"; clocks = <&clock_audio_lnbb clk_audio_pmi_lnbb_clk>; - cdc-vdd-buck-supply = <&pmcobalt_s4>; + cdc-vdd-buck-supply = <&pm8998_s4>; qcom,cdc-vdd-buck-voltage = <1800000 1800000>; qcom,cdc-vdd-buck-current = <650000>; - cdc-buck-sido-supply = <&pmcobalt_s4>; + cdc-buck-sido-supply = <&pm8998_s4>; qcom,cdc-buck-sido-voltage = <1800000 1800000>; qcom,cdc-buck-sido-current = <250000>; - cdc-vdd-tx-h-supply = <&pmcobalt_s4>; + cdc-vdd-tx-h-supply = <&pm8998_s4>; qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; qcom,cdc-vdd-tx-h-current = <25000>; - cdc-vdd-rx-h-supply = <&pmcobalt_s4>; + cdc-vdd-rx-h-supply = <&pm8998_s4>; qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; qcom,cdc-vdd-rx-h-current = <25000>; - cdc-vddpx-1-supply = <&pmcobalt_s4>; + cdc-vddpx-1-supply = <&pm8998_s4>; qcom,cdc-vddpx-1-voltage = <1800000 1800000>; qcom,cdc-vddpx-1-current = <10000>; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-blsp.dtsi b/arch/arm/boot/dts/qcom/msm8998-blsp.dtsi index a660ea06795e..b9e323d894c3 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-blsp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-blsp.dtsi @@ -39,7 +39,7 @@ }; }; -#include "msmcobalt-pinctrl.dtsi" +#include "msm8998-pinctrl.dtsi" &soc { dma_blsp1: qcom,sps-dma@0xc144000 { /* BLSP1 */ diff --git a/arch/arm/boot/dts/qcom/msmcobalt-bus.dtsi b/arch/arm/boot/dts/qcom/msm8998-bus.dtsi index edf7e7b9cbb0..edf7e7b9cbb0 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-bus.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-bus.dtsi diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-cdp.dtsi index ed8eb8459e51..61fc31a17e52 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-cdp.dtsi @@ -15,18 +15,18 @@ led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pmicobalt_flash0 &pmicobalt_flash1>; - qcom,torch-source = <&pmicobalt_torch0 &pmicobalt_torch1>; - qcom,switch-source = <&pmicobalt_switch0>; + qcom,flash-source = <&pmi8998_flash0 &pmi8998_flash1>; + qcom,torch-source = <&pmi8998_torch0 &pmi8998_torch1>; + qcom,switch-source = <&pmi8998_switch0>; status = "ok"; }; led_flash1: qcom,camera-flash@1 { cell-index = <1>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pmicobalt_flash2>; - qcom,torch-source = <&pmicobalt_torch2>; - qcom,switch-source = <&pmicobalt_switch1>; + qcom,flash-source = <&pmi8998_flash2>; + qcom,torch-source = <&pmi8998_torch2>; + qcom,switch-source = <&pmi8998_switch1>; status = "ok"; }; }; @@ -82,9 +82,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 3312000 1352000>; qcom,cam-vreg-max-voltage = <0 3600000 1352000>; @@ -99,7 +99,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmcobalt_gpios 20 0>, + <&pm8998_gpios 20 0>, <&tlmm 29 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -127,9 +127,9 @@ cell-index = <1>; reg = <0x1>; compatible = "qcom,eeprom"; - cam_vdig-supply = <&pmcobalt_lvs1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; + cam_vdig-supply = <&pm8998_lvs1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; qcom,cam-vreg-min-voltage = <0 0 3312000>; qcom,cam-vreg-max-voltage = <0 0 3600000>; @@ -164,9 +164,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmcobalt_l22>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pm8998_l22>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 2864000 1352000>; @@ -181,7 +181,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmcobalt_gpios 9 0>; + <&pm8998_gpios 9 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-req-tbl-num = <0 1 2>; @@ -210,9 +210,9 @@ qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 3312000 1352000>; qcom,cam-vreg-max-voltage = <0 3600000 1352000>; @@ -225,7 +225,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmcobalt_gpios 20 0>, + <&pm8998_gpios 20 0>, <&tlmm 29 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -254,9 +254,9 @@ qcom,csid-sd-index = <1>; qcom,mount-angle = <90>; qcom,eeprom-src = <&eeprom1>; - cam_vdig-supply = <&pmcobalt_lvs1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; + cam_vdig-supply = <&pm8998_lvs1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; qcom,cam-vreg-min-voltage = <0 0 3312000>; qcom,cam-vreg-max-voltage = <0 0 3600000>; @@ -297,9 +297,9 @@ qcom,eeprom-src = <&eeprom2>; qcom,led-flash-src = <&led_flash1>; qcom,actuator-src = <&actuator1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmcobalt_l22>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pm8998_l22>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 2864000 1352000>; @@ -314,7 +314,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmcobalt_gpios 9 0>; + <&pm8998_gpios 9 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-req-tbl-num = <0 1 2>; @@ -332,7 +332,7 @@ qcom,clock-rates = <24000000 0>; }; }; -&pmcobalt_gpios { +&pm8998_gpios { gpio@c800 { /* GPIO 9 - CAMERA SENSOR 2 VDIG */ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-mtp.dtsi index 2be67ab52ba7..0bd9ab40e8f1 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-mtp.dtsi @@ -15,18 +15,18 @@ led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pmicobalt_flash0 &pmicobalt_flash1>; - qcom,torch-source = <&pmicobalt_torch0 &pmicobalt_torch1>; - qcom,switch-source = <&pmicobalt_switch0>; + qcom,flash-source = <&pmi8998_flash0 &pmi8998_flash1>; + qcom,torch-source = <&pmi8998_torch0 &pmi8998_torch1>; + qcom,switch-source = <&pmi8998_switch0>; status = "ok"; }; led_flash1: qcom,camera-flash@1 { cell-index = <1>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pmicobalt_flash2>; - qcom,torch-source = <&pmicobalt_torch2>; - qcom,switch-source = <&pmicobalt_switch1>; + qcom,flash-source = <&pmi8998_flash2>; + qcom,torch-source = <&pmi8998_torch2>; + qcom,switch-source = <&pmi8998_switch1>; status = "ok"; }; }; @@ -82,9 +82,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 3312000 1352000>; qcom,cam-vreg-max-voltage = <0 3600000 1352000>; @@ -99,7 +99,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmcobalt_gpios 20 0>, + <&pm8998_gpios 20 0>, <&tlmm 29 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -127,9 +127,9 @@ cell-index = <1>; reg = <0x1>; compatible = "qcom,eeprom"; - cam_vdig-supply = <&pmcobalt_lvs1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; + cam_vdig-supply = <&pm8998_lvs1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; qcom,cam-vreg-min-voltage = <0 0 3312000>; qcom,cam-vreg-max-voltage = <0 0 3600000>; @@ -164,9 +164,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmcobalt_l22>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pm8998_l22>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 2864000 1352000>; @@ -181,7 +181,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmcobalt_gpios 9 0>; + <&pm8998_gpios 9 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-req-tbl-num = <0 1 2>; @@ -210,9 +210,9 @@ qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 3312000 1352000>; qcom,cam-vreg-max-voltage = <0 3600000 1352000>; @@ -225,7 +225,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmcobalt_gpios 20 0>, + <&pm8998_gpios 20 0>, <&tlmm 29 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -254,9 +254,9 @@ qcom,csid-sd-index = <1>; qcom,mount-angle = <90>; qcom,eeprom-src = <&eeprom1>; - cam_vdig-supply = <&pmcobalt_lvs1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; + cam_vdig-supply = <&pm8998_lvs1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; qcom,cam-vreg-min-voltage = <0 0 3312000>; qcom,cam-vreg-max-voltage = <0 0 3600000>; @@ -297,9 +297,9 @@ qcom,eeprom-src = <&eeprom2>; qcom,led-flash-src = <&led_flash1>; qcom,actuator-src = <&actuator1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmcobalt_l22>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pm8998_l22>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 2864000 1352000>; @@ -314,7 +314,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmcobalt_gpios 9 0>; + <&pm8998_gpios 9 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-req-tbl-num = <0 1 2>; @@ -332,7 +332,7 @@ qcom,clock-rates = <24000000 0>; }; }; -&pmcobalt_gpios { +&pm8998_gpios { gpio@c800 { /* GPIO 9 - CAMERA SENSOR 2 VDIG */ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-qrd-vr1.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-qrd-vr1.dtsi index 0fb1a0425dd5..a56e9836784c 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-qrd-vr1.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-qrd-vr1.dtsi @@ -15,16 +15,16 @@ led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pmicobalt_flash0 &pmicobalt_flash1>; - qcom,switch-source = <&pmicobalt_switch0>; + qcom,flash-source = <&pmi8998_flash0 &pmi8998_flash1>; + qcom,switch-source = <&pmi8998_switch0>; status = "ok"; }; led_flash1: qcom,camera-flash@1 { cell-index = <1>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pmicobalt_flash2>; - qcom,switch-source = <&pmicobalt_switch1>; + qcom,flash-source = <&pmi8998_flash2>; + qcom,switch-source = <&pmi8998_switch1>; status = "ok"; }; }; @@ -106,9 +106,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 3312000 1352000>; qcom,cam-vreg-max-voltage = <0 3600000 1352000>; @@ -121,7 +121,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmcobalt_gpios 20 0>, + <&pm8998_gpios 20 0>, <&tlmm 29 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -146,9 +146,9 @@ cell-index = <1>; reg = <0x1>; compatible = "qcom,eeprom"; - cam_vdig-supply = <&pmcobalt_lvs1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; + cam_vdig-supply = <&pm8998_lvs1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; qcom,cam-vreg-min-voltage = <0 0 3312000>; qcom,cam-vreg-max-voltage = <0 0 3600000>; @@ -183,9 +183,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmcobalt_l22>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pm8998_l22>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 2864000 1352000>; qcom,cam-vreg-max-voltage = <0 2864000 1352000>; @@ -198,7 +198,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 15 0>, <&tlmm 9 0>, - <&pmcobalt_gpios 9 0>; + <&pm8998_gpios 9 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-req-tbl-num = <0 1 2>; @@ -226,9 +226,9 @@ qcom,led-flash-src = <&led_flash0>; qcom,actuator-src = <&actuator0>; qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 3312000 1352000>; qcom,cam-vreg-max-voltage = <0 3600000 1352000>; @@ -241,7 +241,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmcobalt_gpios 20 0>, + <&pm8998_gpios 20 0>, <&tlmm 29 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -270,8 +270,8 @@ qcom,csid-sd-index = <1>; qcom,mount-angle = <90>; qcom,eeprom-src = <&eeprom1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; qcom,cam-vreg-name = "cam_vio", "cam_vana"; qcom,cam-vreg-min-voltage = <0 3312000>; qcom,cam-vreg-max-voltage = <0 3600000>; @@ -312,9 +312,9 @@ qcom,eeprom-src = <&eeprom2>; qcom,led-flash-src = <&led_flash1>; qcom,actuator-src = <&actuator1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmcobalt_l22>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pm8998_l22>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 2864000 1352000>; qcom,cam-vreg-max-voltage = <0 2864000 1352000>; @@ -327,7 +327,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 15 0>, <&tlmm 9 0>, - <&pmcobalt_gpios 9 0>; + <&pm8998_gpios 9 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-req-tbl-num = <0 1 2>; @@ -346,7 +346,7 @@ }; }; -&pmcobalt_gpios { +&pm8998_gpios { gpio@c800 { /* GPIO 9 - CAMERA SENSOR 2 VDIG */ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-qrd.dtsi index 4b435aee73b0..03abb5d69b52 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-qrd.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-qrd.dtsi @@ -16,18 +16,18 @@ led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pmicobalt_flash0 &pmicobalt_flash1>; - qcom,torch-source = <&pmicobalt_torch0 &pmicobalt_torch1>; - qcom,switch-source = <&pmicobalt_switch0>; + qcom,flash-source = <&pmi8998_flash0 &pmi8998_flash1>; + qcom,torch-source = <&pmi8998_torch0 &pmi8998_torch1>; + qcom,switch-source = <&pmi8998_switch0>; status = "ok"; }; led_flash1: qcom,camera-flash@1 { cell-index = <1>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pmicobalt_flash2>; - qcom,torch-source = <&pmicobalt_torch2>; - qcom,switch-source = <&pmicobalt_switch1>; + qcom,flash-source = <&pmi8998_flash2>; + qcom,torch-source = <&pmi8998_torch2>; + qcom,switch-source = <&pmi8998_switch1>; status = "ok"; }; }; @@ -83,9 +83,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 3312000 1352000>; qcom,cam-vreg-max-voltage = <0 3312000 1352000>; @@ -100,7 +100,7 @@ &cam_actuator_vaf_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmcobalt_gpios 20 0>, + <&pm8998_gpios 20 0>, <&tlmm 29 0>, <&tlmm 27 0>; qcom,gpio-reset = <1>; @@ -128,9 +128,9 @@ cell-index = <1>; reg = <0x1>; compatible = "qcom,eeprom"; - cam_vdig-supply = <&pmcobalt_lvs1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; + cam_vdig-supply = <&pm8998_lvs1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; qcom,cam-vreg-min-voltage = <0 0 3312000>; qcom,cam-vreg-max-voltage = <0 0 3312000>; @@ -165,9 +165,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmcobalt_l22>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pm8998_l22>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 2864000 1352000>; @@ -182,7 +182,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmcobalt_gpios 9 0>; + <&pm8998_gpios 9 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-req-tbl-num = <0 1 2>; @@ -211,9 +211,9 @@ qcom,actuator-src = <&actuator0>; qcom,ois-src = <&ois0>; qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 3312000 1352000>; qcom,cam-vreg-max-voltage = <0 3312000 1352000>; @@ -226,7 +226,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmcobalt_gpios 20 0>, + <&pm8998_gpios 20 0>, <&tlmm 29 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -255,9 +255,9 @@ qcom,csid-sd-index = <1>; qcom,mount-angle = <90>; qcom,eeprom-src = <&eeprom1>; - cam_vdig-supply = <&pmcobalt_lvs1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; + cam_vdig-supply = <&pm8998_lvs1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; qcom,cam-vreg-min-voltage = <0 0 3312000>; qcom,cam-vreg-max-voltage = <0 0 3312000>; @@ -298,9 +298,9 @@ qcom,eeprom-src = <&eeprom2>; qcom,led-flash-src = <&led_flash1>; qcom,actuator-src = <&actuator1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmcobalt_l22>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pm8998_l22>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 2864000 1352000>; @@ -315,7 +315,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmcobalt_gpios 9 0>; + <&pm8998_gpios 9 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-req-tbl-num = <0 1 2>; @@ -333,7 +333,7 @@ qcom,clock-rates = <24000000 0>; }; }; -&pmcobalt_gpios { +&pm8998_gpios { gpio@c800 { /* GPIO 9 - CAMERA SENSOR 2 VDIG */ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-skuk.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-skuk.dtsi index a432f0710fe2..da568fd8979c 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-skuk.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera-sensor-skuk.dtsi @@ -15,16 +15,16 @@ led_flash0: qcom,camera-flash@0 { cell-index = <0>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pmicobalt_flash0 &pmicobalt_flash1>; - qcom,switch-source = <&pmicobalt_switch0>; + qcom,flash-source = <&pmi8998_flash0 &pmi8998_flash1>; + qcom,switch-source = <&pmi8998_switch0>; status = "ok"; }; led_flash1: qcom,camera-flash@1 { cell-index = <1>; compatible = "qcom,camera-flash"; - qcom,flash-source = <&pmicobalt_flash2>; - qcom,switch-source = <&pmicobalt_switch1>; + qcom,flash-source = <&pmi8998_flash2>; + qcom,switch-source = <&pmi8998_switch1>; status = "ok"; }; }; @@ -64,9 +64,9 @@ cell-index = <0>; reg = <0>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 3312000 1352000>; qcom,cam-vreg-max-voltage = <0 3600000 1352000>; @@ -79,7 +79,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmcobalt_gpios 20 0>, + <&pm8998_gpios 20 0>, <&tlmm 29 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -104,9 +104,9 @@ cell-index = <1>; reg = <0x1>; compatible = "qcom,eeprom"; - cam_vdig-supply = <&pmcobalt_lvs1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; + cam_vdig-supply = <&pm8998_lvs1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; qcom,cam-vreg-min-voltage = <0 0 3312000>; qcom,cam-vreg-max-voltage = <0 0 3600000>; @@ -141,9 +141,9 @@ cell-index = <2>; reg = <0x2>; compatible = "qcom,eeprom"; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmcobalt_l22>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pm8998_l22>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 2864000 1352000>; @@ -158,7 +158,7 @@ &cam_sensor_front_suspend>; gpios = <&tlmm 14 0>, <&tlmm 28 0>, - <&pmcobalt_gpios 9 0>; + <&pm8998_gpios 9 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-req-tbl-num = <0 1 2>; @@ -185,9 +185,9 @@ qcom,csid-sd-index = <0>; qcom,mount-angle = <270>; qcom,eeprom-src = <&eeprom0>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 3312000 1352000>; qcom,cam-vreg-max-voltage = <0 3600000 1352000>; @@ -200,7 +200,7 @@ &cam_sensor_rear_suspend>; gpios = <&tlmm 13 0>, <&tlmm 30 0>, - <&pmcobalt_gpios 20 0>, + <&pm8998_gpios 20 0>, <&tlmm 29 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; @@ -229,9 +229,9 @@ qcom,csid-sd-index = <1>; qcom,mount-angle = <90>; qcom,eeprom-src = <&eeprom1>; - cam_vdig-supply = <&pmcobalt_lvs1>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmicobalt_bob>; + cam_vdig-supply = <&pm8998_lvs1>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pmi8998_bob>; qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana"; qcom,cam-vreg-min-voltage = <0 0 3312000>; qcom,cam-vreg-max-voltage = <0 0 3600000>; @@ -269,9 +269,9 @@ qcom,csiphy-sd-index = <2>; qcom,csid-sd-index = <2>; qcom,mount-angle = <90>; - cam_vio-supply = <&pmcobalt_lvs1>; - cam_vana-supply = <&pmcobalt_l22>; - cam_vdig-supply = <&pmcobalt_s3>; + cam_vio-supply = <&pm8998_lvs1>; + cam_vana-supply = <&pm8998_l22>; + cam_vdig-supply = <&pm8998_s3>; qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; qcom,cam-vreg-min-voltage = <0 2864000 1352000>; @@ -286,7 +286,7 @@ &cam_sensor_rear2_suspend>; gpios = <&tlmm 15 0>, <&tlmm 9 0>, - <&pmcobalt_gpios 9 0>; + <&pm8998_gpios 9 0>; qcom,gpio-reset = <1>; qcom,gpio-vdig = <2>; qcom,gpio-req-tbl-num = <0 1 2>; @@ -304,7 +304,7 @@ qcom,clock-rates = <24000000 0>; }; }; -&pmcobalt_gpios { +&pm8998_gpios { gpio@c800 { /* GPIO 9 - CAMERA SENSOR 2 VDIG */ qcom,mode = <1>; /* Output */ qcom,pull = <5>; /* No Pull */ diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera.dtsi index 6a0061e206ca..d0fa9921da3f 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera.dtsi @@ -134,9 +134,9 @@ interrupts = <0 296 0>; interrupt-names = "csid"; qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pmcobalt_l1>; + vdd_sec-supply = <&pm8998_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; clocks = <&clock_gcc clk_mmssnoc_axi_clk>, @@ -172,9 +172,9 @@ interrupts = <0 297 0>; interrupt-names = "csid"; qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pmcobalt_l1>; + vdd_sec-supply = <&pm8998_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; clocks = <&clock_gcc clk_mmssnoc_axi_clk>, @@ -210,9 +210,9 @@ interrupts = <0 298 0>; interrupt-names = "csid"; qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pmcobalt_l1>; + vdd_sec-supply = <&pm8998_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; clocks = <&clock_gcc clk_mmssnoc_axi_clk>, @@ -248,9 +248,9 @@ interrupts = <0 299 0>; interrupt-names = "csid"; qcom,csi-vdd-voltage = <1200000>; - qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>; + qcom,mipi-csi-vdd-supply = <&pm8998_l2>; gdscr-supply = <&gdsc_camss_top>; - vdd_sec-supply = <&pmcobalt_l1>; + vdd_sec-supply = <&pm8998_l1>; bimc_smmu-supply = <&gdsc_bimc_smmu>; qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; clocks = <&clock_gcc clk_mmssnoc_axi_clk>, diff --git a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dts b/arch/arm/boot/dts/qcom/msm8998-cdp.dts index 10edf71da2f3..487d71d4b6a8 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-cdp.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmcobalt.dtsi" -#include "msmcobalt-cdp.dtsi" +#include "msm8998.dtsi" +#include "msm8998-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT v1 CDP"; - compatible = "qcom,msmcobalt-cdp", "qcom,msmcobalt", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. MSM 8998 v1 CDP"; + compatible = "qcom,msm8998-cdp", "qcom,msm8998", "qcom,cdp"; qcom,board-id = <1 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-cdp.dtsi index ca504a798659..ec57ab601d46 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-cdp.dtsi @@ -10,17 +10,17 @@ * GNU General Public License for more details. */ -#include "msmcobalt-pinctrl.dtsi" -#include "msmcobalt-camera-sensor-cdp.dtsi" +#include "msm8998-pinctrl.dtsi" +#include "msm8998-camera-sensor-cdp.dtsi" / { bluetooth: bt_wcn3990 { compatible = "qca,wcn3990"; - qca,bt-vdd-io-supply = <&pmcobalt_s3>; - qca,bt-vdd-xtal-supply = <&pmcobalt_s5>; - qca,bt-vdd-core-supply = <&pmcobalt_l7>; - qca,bt-vdd-pa-supply = <&pmcobalt_l17>; - qca,bt-vdd-ldo-supply = <&pmcobalt_l25>; - qca,bt-chip-pwd-supply = <&pmicobalt_bob_pin1>; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7>; + qca,bt-vdd-pa-supply = <&pm8998_l17>; + qca,bt-vdd-ldo-supply = <&pm8998_l25>; + qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; clocks = <&clock_gcc clk_rf_clk2_pin>; clock-names = "rf_clk2"; @@ -44,9 +44,9 @@ }; &ufsphy1 { - vdda-phy-supply = <&pmcobalt_l1>; - vdda-pll-supply = <&pmcobalt_l2>; - vddp-ref-clk-supply = <&pmcobalt_l26>; + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; @@ -57,9 +57,9 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pmcobalt_l20>; - vccq-supply = <&pmcobalt_l26>; - vccq2-supply = <&pmcobalt_s4>; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; @@ -71,11 +71,11 @@ }; &sdhc_2 { - vdd-supply = <&pmcobalt_l21>; + vdd-supply = <&pm8998_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pmcobalt_l13>; + vdd-io-supply = <&pm8998_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; @@ -98,7 +98,7 @@ pinctrl-0 = <&uart_console_active>; }; -&pmcobalt_gpios { +&pm8998_gpios { /* GPIO 5 for Home Key */ gpio@c400 { status = "okay"; @@ -167,8 +167,8 @@ reg = <0x20>; interrupt-parent = <&tlmm>; interrupts = <125 0x2008>; - vdd-supply = <&pmcobalt_l6>; - avdd-supply = <&pmcobalt_l28>; + vdd-supply = <&pm8998_l6>; + avdd-supply = <&pm8998_l28>; synaptics,vdd-voltage = <1808000 1808000>; synaptics,avdd-voltage = <3008000 3008000>; synaptics,vdd-current = <40000>; @@ -193,7 +193,7 @@ qcom,nq-irq = <&tlmm 92 0x00>; qcom,nq-ven = <&tlmm 12 0x00>; qcom,nq-firm = <&tlmm 93 0x00>; - qcom,nq-clkreq = <&pmcobalt_gpios 21 0x00>; + qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; qcom,nq-esepwr = <&tlmm 116 0x00>; interrupt-parent = <&tlmm>; qcom,clk-src = "BBCLK3"; @@ -302,7 +302,7 @@ qcom,qpnp-labibb-mode = "lcd"; }; -&pmicobalt_wled { +&pmi8998_wled { qcom,led-strings-list = [00 01]; }; @@ -432,15 +432,15 @@ qcom,usbplug-cc-gpio = <&tlmm 38 0>; }; -&pmicobalt_charger { +&pmi8998_charger { qcom,batteryless-platform; }; -&pmicobalt_haptics { +&pmi8998_haptics { status = "okay"; }; -&pmcobalt_vadc { +&pm8998_vadc { chan@83 { label = "vph_pwr"; reg = <0x83>; @@ -497,7 +497,7 @@ }; }; -&pmcobalt_adc_tm { +&pm8998_adc_tm { chan@83 { label = "vph_pwr"; reg = <0x83>; @@ -554,7 +554,7 @@ home { label = "home"; - gpios = <&pmcobalt_gpios 5 0x1>; + gpios = <&pm8998_gpios 5 0x1>; linux,input-type = <1>; linux,code = <102>; gpio-key,wakeup; @@ -564,7 +564,7 @@ vol_up { label = "volume_up"; - gpios = <&pmcobalt_gpios 6 0x1>; + gpios = <&pm8998_gpios 6 0x1>; linux,input-type = <1>; linux,code = <115>; gpio-key,wakeup; @@ -573,7 +573,7 @@ cam_snapshot { label = "cam_snapshot"; - gpios = <&pmcobalt_gpios 7 0x1>; + gpios = <&pm8998_gpios 7 0x1>; linux,input-type = <1>; linux,code = <766>; gpio-key,wakeup; @@ -582,7 +582,7 @@ cam_focus { label = "cam_focus"; - gpios = <&pmcobalt_gpios 8 0x1>; + gpios = <&pm8998_gpios 8 0x1>; linux,input-type = <1>; linux,code = <528>; gpio-key,wakeup; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi b/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi index aeb6bf6141d8..aeb6bf6141d8 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-coresight.dtsi diff --git a/arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi b/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi index 8739e8f22549..8739e8f22549 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-gpu.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-gpu.dtsi diff --git a/arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi index 9663ef5a383f..32f9dcdecb0c 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-cdp.dtsi @@ -10,17 +10,17 @@ * GNU General Public License for more details. */ -#include "msmcobalt-pinctrl.dtsi" -#include "msmcobalt-camera-sensor-cdp.dtsi" +#include "msm8998-pinctrl.dtsi" +#include "msm8998-camera-sensor-cdp.dtsi" / { bluetooth: bt_wcn3990 { compatible = "qca,wcn3990"; - qca,bt-vdd-io-supply = <&pmcobalt_s3>; - qca,bt-vdd-xtal-supply = <&pmcobalt_s5>; - qca,bt-vdd-core-supply = <&pmcobalt_l7_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmcobalt_l17_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmcobalt_l25_pin_ctrl>; - qca,bt-chip-pwd-supply = <&pmicobalt_bob_pin1>; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pm8998_l17_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pm8998_l25_pin_ctrl>; + qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; clocks = <&clock_gcc clk_rf_clk2>; clock-names = "rf_clk2"; @@ -69,11 +69,11 @@ }; &sdhc_2 { - vdd-supply = <&pmcobalt_l21>; + vdd-supply = <&pm8998_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pmcobalt_l13>; + vdd-io-supply = <&pm8998_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; @@ -96,7 +96,7 @@ pinctrl-0 = <&uart_console_active>; }; -&pmcobalt_gpios { +&pm8998_gpios { /* GPIO 5 for Home Key */ gpio@c400 { status = "okay"; @@ -165,8 +165,8 @@ reg = <0x20>; interrupt-parent = <&tlmm>; interrupts = <125 0x2008>; - vdd-supply = <&pmcobalt_l6>; - avdd-supply = <&pmcobalt_l28>; + vdd-supply = <&pm8998_l6>; + avdd-supply = <&pm8998_l28>; synaptics,vdd-voltage = <1808000 1808000>; synaptics,avdd-voltage = <3008000 3008000>; synaptics,vdd-current = <40000>; @@ -191,7 +191,7 @@ qcom,nq-irq = <&tlmm 92 0x00>; qcom,nq-ven = <&tlmm 12 0x00>; qcom,nq-firm = <&tlmm 93 0x00>; - qcom,nq-clkreq = <&pmcobalt_gpios 21 0x00>; + qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; qcom,nq-esepwr = <&tlmm 116 0x00>; interrupt-parent = <&tlmm>; qcom,clk-src = "BBCLK3"; @@ -308,7 +308,7 @@ qpnp,qpnp-labibb-mode = "lcd"; }; -&pmicobalt_wled { +&pmi8998_wled { qcom,led-strings-list = [00 01]; }; @@ -440,15 +440,15 @@ qcom,usbplug-cc-gpio = <&tlmm 38 0>; }; -&pmicobalt_charger { +&pmi8998_charger { qcom,batteryless-platform; }; -&pmicobalt_haptics { +&pmi8998_haptics { status = "okay"; }; -&pmcobalt_vadc { +&pm8998_vadc { chan@83 { label = "vph_pwr"; reg = <0x83>; @@ -505,7 +505,7 @@ }; }; -&pmcobalt_adc_tm { +&pm8998_adc_tm { chan@83 { label = "vph_pwr"; reg = <0x83>; @@ -562,7 +562,7 @@ home { label = "home"; - gpios = <&pmcobalt_gpios 5 0x1>; + gpios = <&pm8998_gpios 5 0x1>; linux,input-type = <1>; linux,code = <102>; gpio-key,wakeup; @@ -572,7 +572,7 @@ vol_up { label = "volume_up"; - gpios = <&pmcobalt_gpios 6 0x1>; + gpios = <&pm8998_gpios 6 0x1>; linux,input-type = <1>; linux,code = <115>; gpio-key,wakeup; @@ -581,7 +581,7 @@ cam_snapshot { label = "cam_snapshot"; - gpios = <&pmcobalt_gpios 7 0x1>; + gpios = <&pm8998_gpios 7 0x1>; linux,input-type = <1>; linux,code = <766>; gpio-key,wakeup; @@ -590,7 +590,7 @@ cam_focus { label = "cam_focus"; - gpios = <&pmcobalt_gpios 8 0x1>; + gpios = <&pm8998_gpios 8 0x1>; linux,input-type = <1>; linux,code = <528>; gpio-key,wakeup; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi index 0c8b6ff56124..e73ffc884210 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon-mtp.dtsi @@ -11,17 +11,17 @@ */ #include <dt-bindings/interrupt-controller/irq.h> -#include "msmcobalt-pinctrl.dtsi" -#include "msmcobalt-camera-sensor-mtp.dtsi" +#include "msm8998-pinctrl.dtsi" +#include "msm8998-camera-sensor-mtp.dtsi" / { bluetooth: bt_wcn3990 { compatible = "qca,wcn3990"; - qca,bt-vdd-io-supply = <&pmcobalt_s3>; - qca,bt-vdd-xtal-supply = <&pmcobalt_s5>; - qca,bt-vdd-core-supply = <&pmcobalt_l7_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmcobalt_l17_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmcobalt_l25_pin_ctrl>; - qca,bt-chip-pwd-supply = <&pmicobalt_bob_pin1>; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pm8998_l17_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pm8998_l25_pin_ctrl>; + qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; clocks = <&clock_gcc clk_rf_clk2>; clock-names = "rf_clk2"; @@ -70,11 +70,11 @@ }; &sdhc_2 { - vdd-supply = <&pmcobalt_l21>; + vdd-supply = <&pm8998_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pmcobalt_l13>; + vdd-io-supply = <&pm8998_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; @@ -97,7 +97,7 @@ pinctrl-0 = <&uart_console_active>; }; -&pmcobalt_gpios { +&pm8998_gpios { /* GPIO 6 for Vol+ Key */ gpio@c500 { status = "okay"; @@ -166,8 +166,8 @@ reg = <0x20>; interrupt-parent = <&tlmm>; interrupts = <125 0x2008>; - vdd-supply = <&pmcobalt_l6>; - avdd-supply = <&pmcobalt_l28>; + vdd-supply = <&pm8998_l6>; + avdd-supply = <&pm8998_l28>; synaptics,vdd-voltage = <1808000 1808000>; synaptics,avdd-voltage = <3008000 3008000>; synaptics,vdd-current = <40000>; @@ -192,7 +192,7 @@ qcom,nq-irq = <&tlmm 92 0x00>; qcom,nq-ven = <&tlmm 12 0x00>; qcom,nq-firm = <&tlmm 93 0x00>; - qcom,nq-clkreq = <&pmcobalt_gpios 21 0x00>; + qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; qcom,nq-esepwr = <&tlmm 116 0x00>; interrupt-parent = <&tlmm>; qcom,clk-src = "BBCLK3"; @@ -363,7 +363,7 @@ qpnp,qpnp-labibb-mode = "lcd"; }; -&pmicobalt_wled { +&pmi8998_wled { qcom,led-strings-list = [00 01]; }; @@ -467,11 +467,11 @@ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; }; -&pmicobalt_haptics { +&pmi8998_haptics { status = "okay"; }; -&pmcobalt_vadc { +&pm8998_vadc { chan@83 { label = "vph_pwr"; reg = <0x83>; @@ -528,7 +528,7 @@ }; }; -&pmcobalt_adc_tm { +&pm8998_adc_tm { chan@83 { label = "vph_pwr"; reg = <0x83>; @@ -585,7 +585,7 @@ vol_up { label = "volume_up"; - gpios = <&pmcobalt_gpios 6 0x1>; + gpios = <&pm8998_gpios 6 0x1>; linux,input-type = <1>; linux,code = <115>; gpio-key,wakeup; @@ -594,7 +594,7 @@ cam_snapshot { label = "cam_snapshot"; - gpios = <&pmcobalt_gpios 7 0x1>; + gpios = <&pm8998_gpios 7 0x1>; linux,input-type = <1>; linux,code = <766>; gpio-key,wakeup; @@ -603,7 +603,7 @@ cam_focus { label = "cam_focus"; - gpios = <&pmcobalt_gpios 8 0x1>; + gpios = <&pm8998_gpios 8 0x1>; linux,input-type = <1>; linux,code = <528>; gpio-key,wakeup; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi index ffb42576ffd3..861be92a7bc2 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-interposer-msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-msmfalcon.dtsi @@ -11,13 +11,13 @@ */ #include "skeleton64.dtsi" -#include <dt-bindings/clock/msm-clocks-cobalt.h> +#include <dt-bindings/clock/msm-clocks-8998.h> #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { - model = "Qualcomm Technologies, Inc. MSM COBALT"; - compatible = "qcom,msmcobalt"; + model = "Qualcomm Technologies, Inc. MSM 8998"; + compatible = "qcom,msm8998"; qcom,msm-id = <292 0x0>; interrupt-parent = <&intc>; @@ -342,8 +342,8 @@ }; }; -#include "msmcobalt-smp2p.dtsi" -#include "msm-gdsc-cobalt.dtsi" +#include "msm8998-smp2p.dtsi" +#include "msm-gdsc-8998.dtsi" &soc { #address-cells = <1>; @@ -732,21 +732,21 @@ }; clock_gcc: qcom,gcc@100000 { - compatible = "qcom,gcc-cobalt"; + compatible = "qcom,gcc-8998"; reg = <0x100000 0xb0000>; reg-names = "cc_base"; - vdd_dig-supply = <&pmcobalt_s1_level>; - vdd_dig_ao-supply = <&pmcobalt_s1_level_ao>; + vdd_dig-supply = <&pm8998_s1_level>; + vdd_dig_ao-supply = <&pm8998_s1_level_ao>; #clock-cells = <1>; #reset-cells = <1>; }; clock_mmss: qcom,mmsscc@c8c0000 { - compatible = "qcom,mmsscc-cobalt"; + compatible = "qcom,mmsscc-8998"; reg = <0xc8c0000 0x40000>; reg-names = "cc_base"; - vdd_dig-supply = <&pmcobalt_s1_level>; - vdd_mmsscc_mx-supply = <&pmcobalt_s9_level>; + vdd_dig-supply = <&pm8998_s1_level>; + vdd_mmsscc_mx-supply = <&pm8998_s9_level>; clock-names = "xo", "gpll0", "gpll0_div", "pclk0_src", "pclk1_src", "byte0_src", "byte1_src", @@ -767,10 +767,10 @@ }; clock_gpu: qcom,gpucc@5065000 { - compatible = "qcom,gpucc-cobalt"; + compatible = "qcom,gpucc-8998"; reg = <0x5065000 0x9000>; reg-names = "cc_base"; - vdd_dig-supply = <&pmcobalt_s1_level>; + vdd_dig-supply = <&pm8998_s1_level>; clock-names = "xo_ao", "gpll0"; clocks = <&clock_gcc clk_cxo_clk_src_ao>, <&clock_gcc clk_gcc_gpu_gpll0_clk>; @@ -778,12 +778,12 @@ }; clock_gfx: qcom,gfxcc@5065000 { - compatible = "qcom,gfxcc-cobalt"; + compatible = "qcom,gfxcc-8998"; reg = <0x5065000 0x9000>; reg-names = "cc_base"; vdd_gpucc-supply = <&gfx_vreg>; - vdd_mx-supply = <&pmcobalt_s9_level>; - vdd_gpu_mx-supply = <&pmcobalt_s9_level>; + vdd_mx-supply = <&pm8998_s9_level>; + vdd_gpu_mx-supply = <&pm8998_s9_level>; qcom,gfx3d_clk_src-opp-handle = <&msm_gpu>; qcom,gfxfreq-speedbin0 = < 0 0 0 >, @@ -804,8 +804,8 @@ #clock-cells = <1>; }; - clock_cpu: qcom,cpu-clock-cobalt@179c0000 { - compatible = "qcom,cpu-clock-osm-msmcobalt-v1"; + clock_cpu: qcom,cpu-clock-8998@179c0000 { + compatible = "qcom,cpu-clock-osm-msm8998-v1"; reg = <0x179c0000 0x4000>, <0x17916000 0x1000>, <0x17816000 0x1000>, @@ -942,7 +942,7 @@ }; clock_debug: qcom,debugcc@162000 { - compatible = "qcom,cc-debug-cobalt"; + compatible = "qcom,cc-debug-8998"; reg = <0x162000 0x4>; reg-names = "cc_base"; clock-names = "debug_gpu_clk", "debug_gfx_clk", @@ -1560,9 +1560,9 @@ wake-gpio = <&tlmm 37 0>; gdsc-vdd-supply = <&gdsc_pcie_0>; - vreg-1.8-supply = <&pmcobalt_l2>; - vreg-0.9-supply = <&pmcobalt_l1>; - vreg-cx-supply = <&pmcobalt_s1_level>; + vreg-1.8-supply = <&pm8998_l2>; + vreg-0.9-supply = <&pm8998_l1>; + vreg-cx-supply = <&pm8998_s1_level>; qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; qcom,vreg-0.9-voltage-level = <880000 880000 24000>; @@ -1853,7 +1853,7 @@ <61 512 240000 800000>; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; - extcon = <&pmicobalt_pdphy>; + extcon = <&pmi8998_pdphy>; clocks = <&clock_gcc clk_gcc_usb30_master_clk>, <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>, @@ -1921,9 +1921,9 @@ <0x01fcb24c 0x4>; reg-names = "qusb_phy_base", "tcsr_clamp_dig_n_1p8"; - vdd-supply = <&pmcobalt_l1>; - vdda18-supply = <&pmcobalt_l12>; - vdda33-supply = <&pmcobalt_l24>; + vdd-supply = <&pm8998_l1>; + vdda18-supply = <&pm8998_l12>; + vdda33-supply = <&pm8998_l24>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,qusb-phy-init-seq = /* <value reg_offset> */ @@ -1951,8 +1951,8 @@ reg-names = "qmp_phy_base", "vls_clamp_reg", "tcsr_usb3_dp_phymode"; - vdd-supply = <&pmcobalt_l1>; - core-supply = <&pmcobalt_l2>; + vdd-supply = <&pm8998_l1>; + core-supply = <&pm8998_l2>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,vbus-valid-override; qcom,qmp-phy-init-seq = @@ -2121,7 +2121,7 @@ reg = <0x17300000 0x00100>; interrupts = <0 162 1>; - vdd_cx-supply = <&pmcobalt_s1_level>; + vdd_cx-supply = <&pm8998_s1_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; @@ -2176,9 +2176,9 @@ "mnoc_axi_clk"; interrupts = <0 448 1>; - vdd_cx-supply = <&pmcobalt_s1_level>; + vdd_cx-supply = <&pm8998_s1_level>; vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - vdd_mx-supply = <&pmcobalt_s9_level>; + vdd_mx-supply = <&pm8998_s9_level>; vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; qcom,firmware-name = "modem"; qcom,pil-self-auth; @@ -2202,7 +2202,7 @@ }; tsens0: tsens@10aa000 { - compatible = "qcom,msmcobalt-tsens"; + compatible = "qcom,msm8998-tsens"; reg = <0x10aa000 0x2000>; reg-names = "tsens_physical"; interrupts = <0 458 0>, <0 445 0>; @@ -2213,7 +2213,7 @@ }; tsens1: tsens@10ad000 { - compatible = "qcom,msmcobalt-tsens"; + compatible = "qcom,msm8998-tsens"; reg = <0x10ad000 0x2000>; reg-names = "tsens_physical"; interrupts = <0 184 0>, <0 430 0>; @@ -2538,7 +2538,7 @@ qcom,vdd-restriction-temp = <5>; qcom,vdd-restriction-temp-hysteresis = <10>; - vdd-dig-supply = <&pmcobalt_s1_floor_level>; + vdd-dig-supply = <&pm8998_s1_floor_level>; vdd-gfx-supply = <&gfx_vreg>; qcom,vdd-dig-rstr{ @@ -2587,8 +2587,8 @@ reg = <0x5c00000 0x4000>; interrupts = <0 390 1>; - vdd_cx-supply = <&pmcobalt_l27_level>; - vdd_px-supply = <&pmcobalt_lvs2>; + vdd_cx-supply = <&pm8998_l27_level>; + vdd_px-supply = <&pm8998_lvs2>; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 0>; qcom,proxy-reg-names = "vdd_cx", "vdd_px"; qcom,keep-proxy-regs-on; @@ -2671,7 +2671,7 @@ "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; interrupts = <0 352 1>; - vdd_cx-supply = <&pmcobalt_s1_level>; + vdd_cx-supply = <&pm8998_s1_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; @@ -2953,8 +2953,8 @@ <45 512 0 0>, <45 512 600000 800000>; /* ~4.6Gbps (MCS12) */ qcom,use-ext-supply; - vdd-supply= <&pmcobalt_s7>; - vddio-supply= <&pmcobalt_s5>; + vdd-supply= <&pm8998_s7>; + vddio-supply= <&pm8998_s5>; qcom,use-ext-clocks; clocks = <&clock_gcc clk_rf_clk3>, <&clock_gcc clk_rf_clk3_pin>; @@ -3067,27 +3067,27 @@ status = "ok"; }; -#include "msm-pmcobalt.dtsi" -#include "msm-pmicobalt.dtsi" +#include "msm-pm8998.dtsi" +#include "msm-pmi8998.dtsi" #include "msm-pm8005.dtsi" -#include "msm-pmcobalt-rpm-regulator.dtsi" -#include "msmcobalt-regulator.dtsi" - -#include "msmcobalt-pm.dtsi" -#include "msm-arm-smmu-cobalt.dtsi" -#include "msm-arm-smmu-impl-defs-cobalt.dtsi" -#include "msmcobalt-ion.dtsi" -#include "msmcobalt-camera.dtsi" -#include "msmcobalt-vidc.dtsi" -#include "msmcobalt-coresight.dtsi" -#include "msmcobalt-bus.dtsi" -#include "msmcobalt-gpu.dtsi" -#include "msmcobalt-pinctrl.dtsi" +#include "msm-pm8998-rpm-regulator.dtsi" +#include "msm8998-regulator.dtsi" + +#include "msm8998-pm.dtsi" +#include "msm-arm-smmu-8998.dtsi" +#include "msm-arm-smmu-impl-defs-8998.dtsi" +#include "msm8998-ion.dtsi" +#include "msm8998-camera.dtsi" +#include "msm8998-vidc.dtsi" +#include "msm8998-coresight.dtsi" +#include "msm8998-bus.dtsi" +#include "msm8998-gpu.dtsi" +#include "msm8998-pinctrl.dtsi" #include "msm-audio-lpass.dtsi" -#include "msmcobalt-mdss.dtsi" -#include "msmcobalt-mdss-pll.dtsi" -#include "msmcobalt-blsp.dtsi" -#include "msmcobalt-audio.dtsi" +#include "msm8998-mdss.dtsi" +#include "msm8998-mdss-pll.dtsi" +#include "msm8998-blsp.dtsi" +#include "msm8998-audio.dtsi" /* GPU overrides */ diff --git a/arch/arm/boot/dts/qcom/msmcobalt-interposer-pmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi index f5d5c7f400f9..f5d5c7f400f9 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-interposer-pmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-interposer-pmfalcon.dtsi diff --git a/arch/arm/boot/dts/qcom/msmcobalt-ion.dtsi b/arch/arm/boot/dts/qcom/msm8998-ion.dtsi index 7b15fd81c710..7b15fd81c710 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-ion.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-ion.dtsi diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi b/arch/arm/boot/dts/qcom/msm8998-mdss-panels.dtsi index 6afd593f9610..6afd593f9610 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mdss-panels.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-mdss-panels.dtsi diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mdss-pll.dtsi b/arch/arm/boot/dts/qcom/msm8998-mdss-pll.dtsi index af0eb60818fb..d12b0ea1a9cc 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mdss-pll.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-mdss-pll.dtsi @@ -12,7 +12,7 @@ &soc { mdss_dsi0_pll: qcom,mdss_dsi_pll@c994400 { - compatible = "qcom,mdss_dsi_pll_cobalt"; + compatible = "qcom,mdss_dsi_pll_8998"; status = "ok"; label = "MDSS DSI 0 PLL"; cell-index = <0>; @@ -48,7 +48,7 @@ }; mdss_dsi1_pll: qcom,mdss_dsi_pll@c996400 { - compatible = "qcom,mdss_dsi_pll_cobalt"; + compatible = "qcom,mdss_dsi_pll_8998"; status = "ok"; label = "MDSS DSI 1 PLL"; cell-index = <1>; @@ -83,7 +83,7 @@ }; mdss_dp_pll: qcom,mdss_dp_pll@c011000 { - compatible = "qcom,mdss_dp_pll_cobalt"; + compatible = "qcom,mdss_dp_pll_8998"; status = "ok"; label = "MDSS DP PLL"; cell-index = <0>; @@ -119,7 +119,7 @@ }; mdss_hdmi_pll: qcom,mdss_hdmi_pll@0xc9a0600 { - compatible = "qcom,mdss_hdmi_pll_cobalt"; + compatible = "qcom,mdss_hdmi_pll_8998"; label = "MDSS HDMI PLL"; cell-index = <2>; #clock-cells = <1>; @@ -130,8 +130,8 @@ reg-names = "pll_base", "phy_base", "gdsc_base"; gdsc-supply = <&gdsc_mdss>; - vdda-pll-supply = <&pmcobalt_l2>; - vdda-phy-supply = <&pmcobalt_l12>; + vdda-pll-supply = <&pm8998_l2>; + vdda-phy-supply = <&pm8998_l12>; clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>, <&clock_gcc clk_gcc_hdmi_clkref_clk>, diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi b/arch/arm/boot/dts/qcom/msm8998-mdss.dtsi index 75c985189842..dd2efefe264f 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mdss.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-mdss.dtsi @@ -284,8 +284,8 @@ #address-cells = <1>; #size-cells = <1>; gdsc-supply = <&gdsc_mdss>; - vdda-1p2-supply = <&pmcobalt_l2>; - vdda-0p9-supply = <&pmcobalt_l1>; + vdda-1p2-supply = <&pm8998_l2>; + vdda-0p9-supply = <&pm8998_l1>; ranges = <0xc994000 0xc994000 0x400 0xc994400 0xc994400 0x7c0 0xc828000 0xc828000 0xac @@ -373,7 +373,7 @@ reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; qcom,timing-db-mode; - wqhd-vddio-supply = <&pmcobalt_l14>; + wqhd-vddio-supply = <&pm8998_l14>; lab-supply = <&lab_regulator>; ibb-supply = <&ibb_regulator>; qcom,mdss-mdp = <&mdss_mdp>; @@ -411,7 +411,7 @@ reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; qcom,timing-db-mode; - wqhd-vddio-supply = <&pmcobalt_l14>; + wqhd-vddio-supply = <&pm8998_l14>; lab-supply = <&lab_regulator>; ibb-supply = <&ibb_regulator>; qcom,mdss-mdp = <&mdss_mdp>; @@ -462,8 +462,8 @@ qcom,mdss-fb-map = <&mdss_fb3>; gdsc-supply = <&gdsc_mdss>; - vdda-1p2-supply = <&pmcobalt_l2>; - vdda-0p9-supply = <&pmcobalt_l1>; + vdda-1p2-supply = <&pm8998_l2>; + vdda-0p9-supply = <&pm8998_l1>; reg = <0xc990000 0xa84>, <0xc011000 0x910>, @@ -492,7 +492,7 @@ "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk", "ctrl_pixel_clk"; - qcom,dp-usbpd-detection = <&pmicobalt_pdphy>; + qcom,dp-usbpd-detection = <&pmi8998_pdphy>; qcom,msm_ext_disp = <&msm_ext_disp>; @@ -643,4 +643,4 @@ }; }; -#include "msmcobalt-mdss-panels.dtsi" +#include "msm8998-mdss-panels.dtsi" diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dts b/arch/arm/boot/dts/qcom/msm8998-mtp.dts index ea4047df25f6..f608f5f59a80 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-mtp.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmcobalt.dtsi" -#include "msmcobalt-mtp.dtsi" +#include "msm8998.dtsi" +#include "msm8998-mtp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT v1 MTP"; - compatible = "qcom,msmcobalt-mtp", "qcom,msmcobalt", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. MSM 8998 v1 MTP"; + compatible = "qcom,msm8998-mtp", "qcom,msm8998", "qcom,mtp"; qcom,board-id = <8 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi b/arch/arm/boot/dts/qcom/msm8998-mtp.dtsi index 0cd6d0ab1f1d..76124833dc36 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-mtp.dtsi @@ -11,17 +11,17 @@ */ #include <dt-bindings/interrupt-controller/irq.h> -#include "msmcobalt-pinctrl.dtsi" -#include "msmcobalt-camera-sensor-mtp.dtsi" +#include "msm8998-pinctrl.dtsi" +#include "msm8998-camera-sensor-mtp.dtsi" / { bluetooth: bt_wcn3990 { compatible = "qca,wcn3990"; - qca,bt-vdd-io-supply = <&pmcobalt_s3>; - qca,bt-vdd-xtal-supply = <&pmcobalt_s5>; - qca,bt-vdd-core-supply = <&pmcobalt_l7>; - qca,bt-vdd-pa-supply = <&pmcobalt_l17>; - qca,bt-vdd-ldo-supply = <&pmcobalt_l25>; - qca,bt-chip-pwd-supply = <&pmicobalt_bob_pin1>; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7>; + qca,bt-vdd-pa-supply = <&pm8998_l17>; + qca,bt-vdd-ldo-supply = <&pm8998_l25>; + qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; clocks = <&clock_gcc clk_rf_clk2_pin>; clock-names = "rf_clk2"; @@ -45,9 +45,9 @@ }; &ufsphy1 { - vdda-phy-supply = <&pmcobalt_l1>; - vdda-pll-supply = <&pmcobalt_l2>; - vddp-ref-clk-supply = <&pmcobalt_l26>; + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; @@ -58,9 +58,9 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pmcobalt_l20>; - vccq-supply = <&pmcobalt_l26>; - vccq2-supply = <&pmcobalt_s4>; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; @@ -72,11 +72,11 @@ }; &sdhc_2 { - vdd-supply = <&pmcobalt_l21>; + vdd-supply = <&pm8998_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pmcobalt_l13>; + vdd-io-supply = <&pm8998_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; @@ -99,7 +99,7 @@ pinctrl-0 = <&uart_console_active>; }; -&pmcobalt_gpios { +&pm8998_gpios { /* GPIO 2 for Home Key */ gpio@c100 { status = "okay"; @@ -178,8 +178,8 @@ reg = <0x20>; interrupt-parent = <&tlmm>; interrupts = <125 0x2008>; - vdd-supply = <&pmcobalt_l6>; - avdd-supply = <&pmcobalt_l28>; + vdd-supply = <&pm8998_l6>; + avdd-supply = <&pm8998_l28>; synaptics,vdd-voltage = <1808000 1808000>; synaptics,avdd-voltage = <3008000 3008000>; synaptics,vdd-current = <40000>; @@ -204,7 +204,7 @@ qcom,nq-irq = <&tlmm 92 0x00>; qcom,nq-ven = <&tlmm 12 0x00>; qcom,nq-firm = <&tlmm 93 0x00>; - qcom,nq-clkreq = <&pmcobalt_gpios 21 0x00>; + qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; qcom,nq-esepwr = <&tlmm 116 0x00>; interrupt-parent = <&tlmm>; qcom,clk-src = "BBCLK3"; @@ -365,7 +365,7 @@ qcom,qpnp-labibb-mode = "lcd"; }; -&pmicobalt_wled { +&pmi8998_wled { qcom,led-strings-list = [00 01]; }; @@ -473,11 +473,11 @@ qcom,peripheral-size = <0x500000>; }; -&pmicobalt_haptics { +&pmi8998_haptics { status = "okay"; }; -&pmcobalt_vadc { +&pm8998_vadc { chan@83 { label = "vph_pwr"; reg = <0x83>; @@ -534,7 +534,7 @@ }; }; -&pmcobalt_adc_tm { +&pm8998_adc_tm { chan@83 { label = "vph_pwr"; reg = <0x83>; @@ -591,7 +591,7 @@ vol_up { label = "volume_up"; - gpios = <&pmcobalt_gpios 6 0x1>; + gpios = <&pm8998_gpios 6 0x1>; linux,input-type = <1>; linux,code = <115>; gpio-key,wakeup; @@ -600,7 +600,7 @@ cam_snapshot { label = "cam_snapshot"; - gpios = <&pmcobalt_gpios 7 0x1>; + gpios = <&pm8998_gpios 7 0x1>; linux,input-type = <1>; linux,code = <766>; gpio-key,wakeup; @@ -609,7 +609,7 @@ cam_focus { label = "cam_focus"; - gpios = <&pmcobalt_gpios 8 0x1>; + gpios = <&pm8998_gpios 8 0x1>; linux,input-type = <1>; linux,code = <528>; gpio-key,wakeup; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi index e5fd988dccce..1f5facd5cde5 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-pinctrl.dtsi @@ -12,7 +12,7 @@ &soc { tlmm: pinctrl@03400000 { - compatible = "qcom,msmcobalt-pinctrl"; + compatible = "qcom,msm8998-pinctrl"; reg = <0x03400000 0xc00000>; interrupts = <0 208 0>; gpio-controller; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-pm.dtsi b/arch/arm/boot/dts/qcom/msm8998-pm.dtsi index c6d7defbf35c..c6d7defbf35c 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-pm.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-pm.dtsi diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dts b/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dts index 88a5e945436c..d9afddd0ab46 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dts +++ b/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dts @@ -13,11 +13,11 @@ /dts-v1/; -#include "msmcobalt.dtsi" -#include "msmcobalt-qrd-skuk.dtsi" +#include "msm8998.dtsi" +#include "msm8998-qrd-skuk.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT SKUK"; - compatible = "qcom,msmcobalt-qrd", "qcom,msmcobalt", "qcom,qrd"; + model = "Qualcomm Technologies, Inc. MSM 8998 SKUK"; + compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd"; qcom,board-id = <0x01000b 0x80>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi b/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi index 15756d13d2e0..cead74b02528 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd-skuk.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-qrd-skuk.dtsi @@ -11,18 +11,18 @@ */ #include <dt-bindings/interrupt-controller/irq.h> -#include "msmcobalt-pinctrl.dtsi" -#include "msmcobalt-audio.dtsi" -#include "msmcobalt-camera-sensor-skuk.dtsi" +#include "msm8998-pinctrl.dtsi" +#include "msm8998-audio.dtsi" +#include "msm8998-camera-sensor-skuk.dtsi" &blsp1_uart3_hs { status = "ok"; }; &ufsphy1 { - vdda-phy-supply = <&pmcobalt_l1>; - vdda-pll-supply = <&pmcobalt_l2>; - vddp-ref-clk-supply = <&pmcobalt_l26>; + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; @@ -33,9 +33,9 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pmcobalt_l20>; - vccq-supply = <&pmcobalt_l26>; - vccq2-supply = <&pmcobalt_s4>; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; @@ -47,11 +47,11 @@ }; &sdhc_2 { - vdd-supply = <&pmcobalt_l21>; + vdd-supply = <&pm8998_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pmcobalt_l13>; + vdd-io-supply = <&pm8998_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; @@ -74,7 +74,7 @@ pinctrl-0 = <&uart_console_active>; }; -&pmcobalt_gpios { +&pm8998_gpios { /* GPIO 6 for Vol+ Key */ gpio@c500 { status = "okay"; @@ -94,7 +94,7 @@ vol_up { label = "volume_up"; - gpios = <&pmcobalt_gpios 6 0x1>; + gpios = <&pm8998_gpios 6 0x1>; linux,input-type = <1>; linux,code = <115>; gpio-key,wakeup; @@ -103,7 +103,7 @@ }; sound-tavil { - qcom,model = "msmcobalt-skuk-tavil-snd-card"; + qcom,model = "msm8998-skuk-tavil-snd-card"; qcom,audio-routing = "AIF4 VI", "MCLK", @@ -203,10 +203,10 @@ }; }; -&pmicobalt_fg { +&pmi8998_fg { qcom,battery-data = <&qrd_batterydata>; }; -&pmicobalt_haptics { +&pmi8998_haptics { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd-vr1.dts b/arch/arm/boot/dts/qcom/msm8998-qrd-vr1.dts index e53912071502..f5780529c99a 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd-vr1.dts +++ b/arch/arm/boot/dts/qcom/msm8998-qrd-vr1.dts @@ -13,11 +13,11 @@ /dts-v1/; -#include "msmcobalt.dtsi" -#include "msmcobalt-qrd-vr1.dtsi" +#include "msm8998.dtsi" +#include "msm8998-qrd-vr1.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT VR1 Board"; - compatible = "qcom,msmcobalt-qrd", "qcom,msmcobalt", "qcom,qrd"; + model = "Qualcomm Technologies, Inc. MSM 8998 VR1 Board"; + compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd"; qcom,board-id = <0x02000b 0x80>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd-vr1.dtsi b/arch/arm/boot/dts/qcom/msm8998-qrd-vr1.dtsi index 71fd5cc1383f..ccdfe7ee03f6 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd-vr1.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-qrd-vr1.dtsi @@ -11,17 +11,17 @@ */ #include <dt-bindings/interrupt-controller/irq.h> -#include "msmcobalt-pinctrl.dtsi" -#include "msmcobalt-camera-sensor-qrd-vr1.dtsi" +#include "msm8998-pinctrl.dtsi" +#include "msm8998-camera-sensor-qrd-vr1.dtsi" &blsp1_uart3_hs { status = "ok"; }; &ufsphy1 { - vdda-phy-supply = <&pmcobalt_l1>; - vdda-pll-supply = <&pmcobalt_l2>; - vddp-ref-clk-supply = <&pmcobalt_l26>; + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; @@ -32,9 +32,9 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pmcobalt_l20>; - vccq-supply = <&pmcobalt_l26>; - vccq2-supply = <&pmcobalt_s4>; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; @@ -46,11 +46,11 @@ }; &sdhc_2 { - vdd-supply = <&pmcobalt_l21>; + vdd-supply = <&pm8998_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pmcobalt_l13>; + vdd-io-supply = <&pm8998_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; @@ -73,7 +73,7 @@ pinctrl-0 = <&uart_console_active>; }; -&pmcobalt_gpios { +&pm8998_gpios { /* GPIO 6 for Vol+ Key */ gpio@c500 { status = "okay"; @@ -93,7 +93,7 @@ vol_up { label = "volume_up"; - gpios = <&pmcobalt_gpios 6 0x1>; + gpios = <&pm8998_gpios 6 0x1>; linux,input-type = <1>; linux,code = <115>; gpio-key,wakeup; @@ -102,7 +102,7 @@ }; sound-tavil { - qcom,model = "msmcobalt-qvr-tavil-snd-card"; + qcom,model = "msm8998-qvr-tavil-snd-card"; qcom,audio-routing = "RX_BIAS", "MCLK", "MADINPUT", "MCLK", @@ -137,10 +137,10 @@ }; }; -&pmicobalt_fg { +&pmi8998_fg { qcom,battery-data = <&qrd_batterydata>; }; -&pmicobalt_haptics { +&pmi8998_haptics { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd.dts b/arch/arm/boot/dts/qcom/msm8998-qrd.dts index d95507b505c2..952b9a5cec6f 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd.dts +++ b/arch/arm/boot/dts/qcom/msm8998-qrd.dts @@ -13,11 +13,11 @@ /dts-v1/; -#include "msmcobalt.dtsi" -#include "msmcobalt-qrd.dtsi" +#include "msm8998.dtsi" +#include "msm8998-qrd.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT QRD"; - compatible = "qcom,msmcobalt-qrd", "qcom,msmcobalt", "qcom,qrd"; + model = "Qualcomm Technologies, Inc. MSM 8998 QRD"; + compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd"; qcom,board-id = <11 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-qrd.dtsi index 6483453ec5fa..41f9c3c69fe9 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-qrd.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-qrd.dtsi @@ -11,17 +11,18 @@ */ #include <dt-bindings/interrupt-controller/irq.h> -#include "msmcobalt-pinctrl.dtsi" -#include "msmcobalt-camera-sensor-qrd.dtsi" +#include "msm8998-mtp.dtsi" +#include "msm8998-pinctrl.dtsi" +#include "msm8998-camera-sensor-qrd.dtsi" / { bluetooth: bt_wcn3990 { compatible = "qca,wcn3990"; - qca,bt-vdd-io-supply = <&pmcobalt_s3>; - qca,bt-vdd-xtal-supply = <&pmcobalt_s5>; - qca,bt-vdd-core-supply = <&pmcobalt_l7_pin_ctrl>; - qca,bt-vdd-pa-supply = <&pmcobalt_l17_pin_ctrl>; - qca,bt-vdd-ldo-supply = <&pmcobalt_l25_pin_ctrl>; - qca,bt-chip-pwd-supply = <&pmicobalt_bob_pin1>; + qca,bt-vdd-io-supply = <&pm8998_s3>; + qca,bt-vdd-xtal-supply = <&pm8998_s5>; + qca,bt-vdd-core-supply = <&pm8998_l7_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pm8998_l17_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pm8998_l25_pin_ctrl>; + qca,bt-chip-pwd-supply = <&pmi8998_bob_pin1>; qca,bt-vdd-io-voltage-level = <1352000 1352000>; qca,bt-vdd-xtal-voltage-level = <2040000 2040000>; @@ -43,9 +44,9 @@ }; &ufsphy1 { - vdda-phy-supply = <&pmcobalt_l1>; - vdda-pll-supply = <&pmcobalt_l2>; - vddp-ref-clk-supply = <&pmcobalt_l26>; + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; @@ -56,9 +57,9 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pmcobalt_l20>; - vccq-supply = <&pmcobalt_l26>; - vccq2-supply = <&pmcobalt_s4>; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; @@ -70,11 +71,11 @@ }; &sdhc_2 { - vdd-supply = <&pmcobalt_l21>; + vdd-supply = <&pm8998_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pmcobalt_l13>; + vdd-io-supply = <&pm8998_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; @@ -97,7 +98,7 @@ pinctrl-0 = <&uart_console_active>; }; -&pmcobalt_gpios { +&pm8998_gpios { /* GPIO 6 for Vol+ Key */ gpio@c500 { status = "okay"; @@ -166,8 +167,8 @@ reg = <0x20>; interrupt-parent = <&tlmm>; interrupts = <125 0x2008>; - vdd-supply = <&pmcobalt_l6>; - avdd-supply = <&pmcobalt_l28>; + vdd-supply = <&pm8998_l6>; + avdd-supply = <&pm8998_l28>; synaptics,vdd-voltage = <1808000 1808000>; synaptics,avdd-voltage = <3008000 3008000>; synaptics,vdd-current = <40000>; @@ -192,7 +193,7 @@ qcom,nq-irq = <&tlmm 92 0x00>; qcom,nq-ven = <&tlmm 12 0x00>; qcom,nq-firm = <&tlmm 93 0x00>; - qcom,nq-clkreq = <&pmcobalt_gpios 21 0x00>; + qcom,nq-clkreq = <&pm8998_gpios 21 0x00>; qcom,nq-esepwr = <&tlmm 116 0x00>; interrupt-parent = <&tlmm>; qcom,clk-src = "BBCLK3"; @@ -263,7 +264,7 @@ qcom,qpnp-labibb-mode = "lcd"; }; -&pmicobalt_wled { +&pmi8998_wled { qcom,led-strings-list = [01 02]; }; @@ -381,11 +382,11 @@ }; }; -&pmicobalt_haptics { +&pmi8998_haptics { status = "okay"; }; -&pmcobalt_vadc { +&pm8998_vadc { chan@83 { label = "vph_pwr"; reg = <0x83>; @@ -442,7 +443,7 @@ }; }; -&pmcobalt_adc_tm { +&pm8998_adc_tm { chan@83 { label = "vph_pwr"; reg = <0x83>; @@ -503,7 +504,7 @@ vol_up { label = "volume_up"; - gpios = <&pmcobalt_gpios 6 0x1>; + gpios = <&pm8998_gpios 6 0x1>; linux,input-type = <1>; linux,code = <115>; gpio-key,wakeup; @@ -512,7 +513,7 @@ cam_snapshot { label = "cam_snapshot"; - gpios = <&pmcobalt_gpios 7 0x1>; + gpios = <&pm8998_gpios 7 0x1>; linux,input-type = <1>; linux,code = <766>; gpio-key,wakeup; @@ -521,7 +522,7 @@ cam_focus { label = "cam_focus"; - gpios = <&pmcobalt_gpios 8 0x1>; + gpios = <&pm8998_gpios 8 0x1>; linux,input-type = <1>; linux,code = <528>; gpio-key,wakeup; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8998-regulator.dtsi index 32cf1663cf43..518ad33c63ea 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-regulator.dtsi @@ -10,16 +10,16 @@ * GNU General Public License for more details. */ -#include <dt-bindings/clock/msm-clocks-cobalt.h> +#include <dt-bindings/clock/msm-clocks-8998.h> #include <dt-bindings/interrupt-controller/arm-gic.h> &rpm_bus { - /* PMCOBALT S1 + S6 = VDD_CX supply */ + /* PM8998 S1 + S6 = VDD_CX supply */ rpm-regulator-smpa1 { status = "okay"; - pmcobalt_s1_level: regulator-s1-level { + pm8998_s1_level: regulator-s1-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s1_level"; + regulator-name = "pm8998_s1_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -28,9 +28,9 @@ qcom,use-voltage-level; }; - pmcobalt_s1_floor_level: regulator-s1-floor-level { + pm8998_s1_floor_level: regulator-s1-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s1_floor_level"; + regulator-name = "pm8998_s1_floor_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -40,9 +40,9 @@ qcom,always-send-voltage; }; - pmcobalt_s1_level_ao: regulator-s1-level-ao { + pm8998_s1_level_ao: regulator-s1-level-ao { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s1_level_ao"; + regulator-name = "pm8998_s1_level_ao"; qcom,set = <1>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -54,7 +54,7 @@ rpm-regulator-smpa2 { status = "okay"; - pmcobalt_s2: regulator-s2 { + pm8998_s2: regulator-s2 { regulator-min-microvolt = <1128000>; regulator-max-microvolt = <1128000>; status = "okay"; @@ -63,7 +63,7 @@ rpm-regulator-smpa3 { status = "okay"; - pmcobalt_s3: regulator-s3 { + pm8998_s3: regulator-s3 { regulator-min-microvolt = <1352000>; regulator-max-microvolt = <1352000>; status = "okay"; @@ -72,7 +72,7 @@ rpm-regulator-smpa4 { status = "okay"; - pmcobalt_s4: regulator-s4 { + pm8998_s4: regulator-s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; status = "okay"; @@ -81,7 +81,7 @@ rpm-regulator-smpa5 { status = "okay"; - pmcobalt_s5: regulator-s5 { + pm8998_s5: regulator-s5 { regulator-min-microvolt = <1904000>; regulator-max-microvolt = <2040000>; status = "okay"; @@ -90,7 +90,7 @@ rpm-regulator-smpa7 { status = "okay"; - pmcobalt_s7: regulator-s7 { + pm8998_s7: regulator-s7 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1028000>; status = "okay"; @@ -99,19 +99,19 @@ rpm-regulator-smpa8 { status = "okay"; - pmcobalt_s8: regulator-s8 { + pm8998_s8: regulator-s8 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <800000>; status = "okay"; }; }; - /* PMCOBALT S9 = VDD_MX supply */ + /* PM8998 S9 = VDD_MX supply */ rpm-regulator-smpa9 { status = "okay"; - pmcobalt_s9_level: regulator-s9-level { + pm8998_s9_level: regulator-s9-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s9_level"; + regulator-name = "pm8998_s9_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -120,9 +120,9 @@ qcom,use-voltage-level; }; - pmcobalt_s9_floor_level: regulator-s9-floor-level { + pm8998_s9_floor_level: regulator-s9-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s9_floor_level"; + regulator-name = "pm8998_s9_floor_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -132,9 +132,9 @@ qcom,always-send-voltage; }; - pmcobalt_s9_level_ao: regulator-s9-level-ao { + pm8998_s9_level_ao: regulator-s9-level-ao { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_s9_level_ao"; + regulator-name = "pm8998_s9_level_ao"; qcom,set = <1>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -146,10 +146,10 @@ rpm-regulator-ldoa1 { status = "okay"; - pmcobalt_l1: regulator-l1 { + pm8998_l1: regulator-l1 { regulator-min-microvolt = <880000>; regulator-max-microvolt = <880000>; - proxy-supply = <&pmcobalt_l1>; + proxy-supply = <&pm8998_l1>; qcom,proxy-consumer-enable; qcom,proxy-consumer-current = <73400>; status = "okay"; @@ -158,10 +158,10 @@ rpm-regulator-ldoa2 { status = "okay"; - pmcobalt_l2: regulator-l2 { + pm8998_l2: regulator-l2 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - proxy-supply = <&pmcobalt_l2>; + proxy-supply = <&pm8998_l2>; qcom,proxy-consumer-enable; qcom,proxy-consumer-current = <12560>; status = "okay"; @@ -170,19 +170,19 @@ rpm-regulator-ldoa3 { status = "okay"; - pmcobalt_l3: regulator-l3 { + pm8998_l3: regulator-l3 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; status = "okay"; }; }; - /* PMCOBALT L4 = VDD_SSC_MX supply */ + /* PM8998 L4 = VDD_SSC_MX supply */ rpm-regulator-ldoa4 { status = "okay"; - pmcobalt_l4_level: regulator-l4-level { + pm8998_l4_level: regulator-l4-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l4_level"; + regulator-name = "pm8998_l4_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -191,9 +191,9 @@ qcom,use-voltage-level; }; - pmcobalt_l4_floor_level: regulator-l4-floor-level { + pm8998_l4_floor_level: regulator-l4-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l4_floor_level"; + regulator-name = "pm8998_l4_floor_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -206,7 +206,7 @@ rpm-regulator-ldoa5 { status = "okay"; - pmcobalt_l5: regulator-l5 { + pm8998_l5: regulator-l5 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <800000>; /* Force NPM follows HW0_EN */ @@ -217,7 +217,7 @@ rpm-regulator-ldoa6 { status = "okay"; - pmcobalt_l6: regulator-l6 { + pm8998_l6: regulator-l6 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <1808000>; status = "okay"; @@ -226,15 +226,15 @@ rpm-regulator-ldoa7 { status = "okay"; - pmcobalt_l7: regulator-l7 { + pm8998_l7: regulator-l7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; status = "okay"; }; - pmcobalt_l7_pin_ctrl: regulator-l7-pin-ctrl { + pm8998_l7_pin_ctrl: regulator-l7-pin-ctrl { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l7_pin_ctrl"; + regulator-name = "pm8998_l7_pin_ctrl"; qcom,set = <3>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -247,7 +247,7 @@ rpm-regulator-ldoa8 { status = "okay"; - pmcobalt_l8: regulator-l8 { + pm8998_l8: regulator-l8 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; status = "okay"; @@ -256,7 +256,7 @@ rpm-regulator-ldoa9 { status = "okay"; - pmcobalt_l9: regulator-l9 { + pm8998_l9: regulator-l9 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; status = "okay"; @@ -265,7 +265,7 @@ rpm-regulator-ldoa10 { status = "okay"; - pmcobalt_l10: regulator-l10 { + pm8998_l10: regulator-l10 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; status = "okay"; @@ -274,7 +274,7 @@ rpm-regulator-ldoa11 { status = "okay"; - pmcobalt_l11: regulator-l11 { + pm8998_l11: regulator-l11 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; status = "okay"; @@ -283,7 +283,7 @@ rpm-regulator-ldoa12 { status = "okay"; - pmcobalt_l12: regulator-l12 { + pm8998_l12: regulator-l12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; status = "okay"; @@ -292,7 +292,7 @@ rpm-regulator-ldoa13 { status = "okay"; - pmcobalt_l13: regulator-l13 { + pm8998_l13: regulator-l13 { regulator-min-microvolt = <1808000>; regulator-max-microvolt = <2960000>; status = "okay"; @@ -301,10 +301,10 @@ rpm-regulator-ldoa14 { status = "okay"; - pmcobalt_l14: regulator-l14 { + pm8998_l14: regulator-l14 { regulator-min-microvolt = <1880000>; regulator-max-microvolt = <1880000>; - proxy-supply = <&pmcobalt_l14>; + proxy-supply = <&pm8998_l14>; qcom,proxy-consumer-enable; qcom,proxy-consumer-current = <32000>; status = "okay"; @@ -313,7 +313,7 @@ rpm-regulator-ldoa15 { status = "okay"; - pmcobalt_l15: regulator-l15 { + pm8998_l15: regulator-l15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; status = "okay"; @@ -322,7 +322,7 @@ rpm-regulator-ldoa16 { status = "okay"; - pmcobalt_l16: regulator-l16 { + pm8998_l16: regulator-l16 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; status = "okay"; @@ -331,15 +331,15 @@ rpm-regulator-ldoa17 { status = "okay"; - pmcobalt_l17: regulator-l17 { + pm8998_l17: regulator-l17 { regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; status = "okay"; }; - pmcobalt_l17_pin_ctrl: regulator-l17-pin-ctrl { + pm8998_l17_pin_ctrl: regulator-l17-pin-ctrl { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l17_pin_ctrl"; + regulator-name = "pm8998_l17_pin_ctrl"; qcom,set = <3>; regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; @@ -352,7 +352,7 @@ rpm-regulator-ldoa18 { status = "okay"; - pmcobalt_l18: regulator-l18 { + pm8998_l18: regulator-l18 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; status = "okay"; @@ -361,7 +361,7 @@ rpm-regulator-ldoa19 { status = "okay"; - pmcobalt_l19: regulator-l19 { + pm8998_l19: regulator-l19 { regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3008000>; status = "okay"; @@ -370,7 +370,7 @@ rpm-regulator-ldoa20 { status = "okay"; - pmcobalt_l20: regulator-l20 { + pm8998_l20: regulator-l20 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; status = "okay"; @@ -379,7 +379,7 @@ rpm-regulator-ldoa21 { status = "okay"; - pmcobalt_l21: regulator-l21 { + pm8998_l21: regulator-l21 { regulator-min-microvolt = <2960000>; regulator-max-microvolt = <2960000>; status = "okay"; @@ -388,7 +388,7 @@ rpm-regulator-ldoa22 { status = "okay"; - pmcobalt_l22: regulator-l22 { + pm8998_l22: regulator-l22 { regulator-min-microvolt = <2864000>; regulator-max-microvolt = <2864000>; status = "okay"; @@ -397,7 +397,7 @@ rpm-regulator-ldoa23 { status = "okay"; - pmcobalt_l23: regulator-l23 { + pm8998_l23: regulator-l23 { regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3312000>; status = "okay"; @@ -406,7 +406,7 @@ rpm-regulator-ldoa24 { status = "okay"; - pmcobalt_l24: regulator-l24 { + pm8998_l24: regulator-l24 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; status = "okay"; @@ -414,15 +414,15 @@ }; rpm-regulator-ldoa25 { status = "okay"; - pmcobalt_l25: regulator-l25 { + pm8998_l25: regulator-l25 { regulator-min-microvolt = <3104000>; regulator-max-microvolt = <3312000>; status = "okay"; }; - pmcobalt_l25_pin_ctrl: regulator-l25-pin-ctrl { + pm8998_l25_pin_ctrl: regulator-l25-pin-ctrl { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l25_pin_ctrl"; + regulator-name = "pm8998_l25_pin_ctrl"; qcom,set = <3>; regulator-min-microvolt = <3104000>; regulator-max-microvolt = <3312000>; @@ -435,19 +435,19 @@ rpm-regulator-ldoa26 { status = "okay"; - pmcobalt_l26: regulator-l26 { + pm8998_l26: regulator-l26 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; status = "okay"; }; }; - /* PMCOBALT L27 = VDD_SSC_CX supply */ + /* PM8998 L27 = VDD_SSC_CX supply */ rpm-regulator-ldoa27 { status = "okay"; - pmcobalt_l27_level: regulator-l27-level { + pm8998_l27_level: regulator-l27-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l27_level"; + regulator-name = "pm8998_l27_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -456,9 +456,9 @@ qcom,use-voltage-level; }; - pmcobalt_l27_floor_level: regulator-l27-floor-level { + pm8998_l27_floor_level: regulator-l27-floor-level { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmcobalt_l27_floor_level"; + regulator-name = "pm8998_l27_floor_level"; qcom,set = <3>; regulator-min-microvolt = <RPM_SMD_REGULATOR_LEVEL_RETENTION>; @@ -471,7 +471,7 @@ rpm-regulator-ldoa28 { status = "okay"; - pmcobalt_l28: regulator-l28 { + pm8998_l28: regulator-l28 { regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3008000>; status = "okay"; @@ -480,44 +480,44 @@ rpm-regulator-vsa1 { status = "okay"; - pmcobalt_lvs1: regulator-lvs1 { + pm8998_lvs1: regulator-lvs1 { status = "okay"; }; }; rpm-regulator-vsa2 { status = "okay"; - pmcobalt_lvs2: regulator-lvs2 { + pm8998_lvs2: regulator-lvs2 { status = "okay"; }; }; rpm-regulator-bobb { status = "okay"; - pmicobalt_bob: regulator-bob { + pmi8998_bob: regulator-bob { regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3600000>; status = "okay"; }; - pmicobalt_bob_pin1: regulator-bob-pin1 { + pmi8998_bob_pin1: regulator-bob-pin1 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmicobalt_bob_pin1"; + regulator-name = "pm8998_bob_pin1"; qcom,set = <3>; regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3600000>; qcom,use-pin-ctrl-voltage1; }; - pmicobalt_bob_pin2: regulator-bob-pin2 { + pmi8998_bob_pin2: regulator-bob-pin2 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmicobalt_bob_pin2"; + regulator-name = "pm8998_bob_pin2"; qcom,set = <3>; regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3600000>; qcom,use-pin-ctrl-voltage2; }; - pmicobalt_bob_pin3: regulator-bob-pin3 { + pmi8998_bob_pin3: regulator-bob-pin3 { compatible = "qcom,rpm-smd-regulator"; - regulator-name = "pmicobalt_bob_pin3"; + regulator-name = "pm8998_bob_pin3"; qcom,set = <3>; regulator-min-microvolt = <3312000>; regulator-max-microvolt = <3600000>; @@ -538,21 +538,21 @@ }; }; - qcom,pmcobalt@1 { - pmcobalt_s10: regulator@2f00 { + qcom,pm8998@1 { + pm8998_s10: regulator@2f00 { compatible = "qcom,qpnp-regulator"; reg = <0x2f00 0x100>; - regulator-name = "pmcobalt_s10"; + regulator-name = "pm8998_s10"; regulator-min-microvolt = <572000>; regulator-max-microvolt = <1112000>; qcom,enable-time = <500>; regulator-always-on; }; - pmcobalt_s13: regulator@3800 { + pm8998_s13: regulator@3800 { compatible = "qcom,qpnp-regulator"; reg = <0x3800 0x100>; - regulator-name = "pmcobalt_s13"; + regulator-name = "pm8998_s13"; regulator-min-microvolt = <572000>; regulator-max-microvolt = <1112000>; qcom,enable-time = <500>; @@ -577,7 +577,7 @@ &soc { /* CPR controller regulators */ apc0_cpr: cprh-ctrl@179c8000 { - compatible = "qcom,cprh-msmcobalt-v1-kbss-regulator"; + compatible = "qcom,cprh-msm8998-v1-kbss-regulator"; reg = <0x179c8000 0x4000>, <0x00784000 0x1000>; reg-names = "cpr_ctrl", "fuse_base"; clocks = <&clock_gcc clk_gcc_hmss_rbcpr_clk>; @@ -614,7 +614,7 @@ "PWR_CPRH_STATUS", "APCLUS0_L2_SAW4_PMIC_STS"; qcom,cpr-aging-ref-voltage = <1112000>; - vdd-supply = <&pmcobalt_s10>; + vdd-supply = <&pm8998_s10>; thread@0 { qcom,cpr-thread-id = <0>; @@ -750,7 +750,7 @@ }; apc1_cpr: cprh-ctrl@179c4000{ - compatible = "qcom,cprh-msmcobalt-v1-kbss-regulator"; + compatible = "qcom,cprh-msm8998-v1-kbss-regulator"; reg = <0x179c4000 0x4000>, <0x00784000 0x1000>; reg-names = "cpr_ctrl", "fuse_base"; clocks = <&clock_gcc clk_gcc_hmss_rbcpr_clk>; @@ -787,7 +787,7 @@ "PERF_CPRH_STATUS", "APCLUS1_L2_SAW4_PMIC_STS"; qcom,cpr-aging-ref-voltage = <1112000>; - vdd-supply = <&pmcobalt_s13>; + vdd-supply = <&pm8998_s13>; thread@0 { qcom,cpr-thread-id = <0>; @@ -943,7 +943,7 @@ }; gfx_cpr: cpr4-ctrl@5061000 { - compatible = "qcom,cpr4-msmcobalt-v1-mmss-regulator"; + compatible = "qcom,cpr4-msm8998-v1-mmss-regulator"; reg = <0x05061000 0x4000>, <0x00784000 0x1000>, <0x05065204 0x4>; @@ -1121,7 +1121,7 @@ }; }; -&pmicobalt_charger { +&pmi8998_charger { smb2_vbus: qcom,smb2-vbus { regulator-name = "smb2-vbus"; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-rumi.dts b/arch/arm/boot/dts/qcom/msm8998-rumi.dts index 81927abd6886..eaeb711efba6 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-rumi.dts +++ b/arch/arm/boot/dts/qcom/msm8998-rumi.dts @@ -14,12 +14,12 @@ /dts-v1/; /memreserve/ 0x90000000 0x00000100; -#include "msmcobalt.dtsi" -#include "msmcobalt-rumi.dtsi" +#include "msm8998.dtsi" +#include "msm8998-rumi.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT RUMI"; - compatible = "qcom,msmcobalt-rumi", "qcom,msmcobalt", "qcom,rumi"; + model = "Qualcomm Technologies, Inc. MSM 8998 RUMI"; + compatible = "qcom,msm8998-rumi", "qcom,msm8998", "qcom,rumi"; qcom,board-id = <15 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi b/arch/arm/boot/dts/qcom/msm8998-rumi.dtsi index 105a83b56056..d5fd190c938d 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-rumi.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-rumi.dtsi @@ -10,7 +10,7 @@ * GNU General Public License for more details. */ -#include "msmcobalt-pinctrl.dtsi" +#include "msm8998-pinctrl.dtsi" &uartblsp2dm1 { status = "ok"; }; @@ -20,9 +20,9 @@ reg = <0x1da7000 0xda8>, /* PHY regs */ <0x1db8000 0x100>; /* U11 user regs */ reg-names = "phy_mem", "u11_user"; - vdda-phy-supply = <&pmcobalt_l1>; - vdda-pll-supply = <&pmcobalt_l2>; - vddp-ref-clk-supply = <&pmcobalt_l26>; + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; @@ -77,9 +77,9 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pmcobalt_l20>; - vccq-supply = <&pmcobalt_l26>; - vccq2-supply = <&pmcobalt_s4>; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; @@ -95,11 +95,11 @@ }; &sdhc_2 { - vdd-supply = <&pmcobalt_l21>; + vdd-supply = <&pm8998_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pmcobalt_l13>; + vdd-io-supply = <&pm8998_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; @@ -267,14 +267,14 @@ }; &spmi_bus { - qcom,pmicobalt@3 { + qcom,pmi8998@3 { flash_led: qcom,leds@d300 { status = "disabled"; }; }; }; -&pmicobalt_charger { +&pmi8998_charger { qcom,suspend-input; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-sim.dts b/arch/arm/boot/dts/qcom/msm8998-sim.dts index 69c047994c98..c92050ab20d6 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-sim.dts +++ b/arch/arm/boot/dts/qcom/msm8998-sim.dts @@ -14,12 +14,12 @@ /dts-v1/; /memreserve/ 0x90000000 0x00000100; -#include "msmcobalt.dtsi" -#include "msmcobalt-sim.dtsi" +#include "msm8998.dtsi" +#include "msm8998-sim.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT SIM"; - compatible = "qcom,msmcobalt-sim", "qcom,msmcobalt", "qcom,sim"; + model = "Qualcomm Technologies, Inc. MSM 8998 SIM"; + compatible = "qcom,msm8998-sim", "qcom,msm8998", "qcom,sim"; qcom,board-id = <16 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi b/arch/arm/boot/dts/qcom/msm8998-sim.dtsi index 4e6b1dd9211a..8a0f4b30121c 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-sim.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-sim.dtsi @@ -10,7 +10,7 @@ * GNU General Public License for more details. */ -#include "msmcobalt-pinctrl.dtsi" +#include "msm8998-pinctrl.dtsi" &uartblsp2dm1 { status = "ok"; @@ -19,9 +19,9 @@ }; &ufsphy1 { - vdda-phy-supply = <&pmcobalt_l1>; - vdda-pll-supply = <&pmcobalt_l2>; - vddp-ref-clk-supply = <&pmcobalt_l26>; + vdda-phy-supply = <&pm8998_l1>; + vdda-pll-supply = <&pm8998_l2>; + vddp-ref-clk-supply = <&pm8998_l26>; vdda-phy-max-microamp = <51400>; vdda-pll-max-microamp = <14600>; vddp-ref-clk-max-microamp = <100>; @@ -32,9 +32,9 @@ &ufs1 { vdd-hba-supply = <&gdsc_ufs>; vdd-hba-fixed-regulator; - vcc-supply = <&pmcobalt_l20>; - vccq-supply = <&pmcobalt_l26>; - vccq2-supply = <&pmcobalt_s4>; + vcc-supply = <&pm8998_l20>; + vccq-supply = <&pm8998_l26>; + vccq2-supply = <&pm8998_s4>; vcc-max-microamp = <750000>; vccq-max-microamp = <560000>; vccq2-max-microamp = <750000>; @@ -50,11 +50,11 @@ }; &sdhc_2 { - vdd-supply = <&pmcobalt_l21>; + vdd-supply = <&pm8998_l21>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; - vdd-io-supply = <&pmcobalt_l13>; + vdd-io-supply = <&pm8998_l13>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; @@ -85,8 +85,8 @@ &soc { sound_sim { - compatible = "qcom,msmcobalt-asoc-snd-stub"; - qcom,model = "msmcobalt-stub-snd-card"; + compatible = "qcom,msm8998-asoc-snd-stub"; + qcom,model = "msm8998-stub-snd-card"; qcom,audio-routing = "AIF4 VI", "MCLK", @@ -111,7 +111,7 @@ interrupt-names = "cdc-int"; }; -&pmicobalt_charger { +&pmi8998_charger { qcom,suspend-input; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-smp2p.dtsi b/arch/arm/boot/dts/qcom/msm8998-smp2p.dtsi index 2926a6889395..2926a6889395 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-smp2p.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-smp2p.dtsi diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2-camera.dtsi index a81287c36266..a81287c36266 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2-camera.dtsi diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-cdp.dts b/arch/arm/boot/dts/qcom/msm8998-v2-cdp.dts index 7cb8f107abc4..0f5ad5366c84 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2-cdp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2-cdp.dts @@ -13,11 +13,11 @@ /dts-v1/; -#include "msmcobalt-v2.dtsi" -#include "msmcobalt-cdp.dtsi" +#include "msm8998-v2.dtsi" +#include "msm8998-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT v2 CDP"; - compatible = "qcom,msmcobalt-cdp", "qcom,msmcobalt", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. MSM 8998 v2 CDP"; + compatible = "qcom,msm8998-cdp", "qcom,msm8998", "qcom,cdp"; qcom,board-id = <1 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi index 46ed1f219970..d207628f06a1 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2-interposer-msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2-interposer-msmfalcon.dtsi @@ -13,19 +13,19 @@ /* * As a general rule, only version-specific property overrides should be placed * inside this file. Common device definitions should be placed inside the - * msmcobalt.dtsi file. + * msm8998.dtsi file. */ -#include "msmcobalt-interposer-msmfalcon.dtsi" -#include "msmcobalt-v2-camera.dtsi" +#include "msm8998-interposer-msmfalcon.dtsi" +#include "msm8998-v2-camera.dtsi" / { - model = "Qualcomm Technologies, Inc. MSMCOBALT v2"; + model = "Qualcomm Technologies, Inc. MSM8998 v2"; qcom,msm-id = <292 0x20000>; }; &clock_cpu { - compatible = "qcom,cpu-clock-osm-msmcobalt-v2"; + compatible = "qcom,cpu-clock-osm-msm8998-v2"; /delete-property/ qcom,llm-sw-overr; qcom,pwrcl-speedbin0-v0 = < 300000000 0x0004000f 0x01200020 0x1 1 >, @@ -187,19 +187,19 @@ }; &clock_gcc { - compatible = "qcom,gcc-cobalt-v2"; + compatible = "qcom,gcc-8998-v2"; }; &clock_mmss { - compatible = "qcom,mmsscc-cobalt-v2"; + compatible = "qcom,mmsscc-8998-v2"; }; &clock_gpu { - compatible = "qcom,gpucc-cobalt-v2"; + compatible = "qcom,gpucc-8998-v2"; }; &clock_gfx { - compatible = "qcom,gfxcc-cobalt-v2"; + compatible = "qcom,gfxcc-8998-v2"; qcom,gfxfreq-speedbin0 = < 0 0 0 >, < 180000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >, @@ -227,18 +227,18 @@ qcom,max-bandwidth-per-pipe-kbps = <4700000>; }; -&pmcobalt_s10 { +&pm8998_s10 { regulator-min-microvolt = <568000>; regulator-max-microvolt = <1056000>; }; -&pmcobalt_s13 { +&pm8998_s13 { regulator-min-microvolt = <568000>; regulator-max-microvolt = <1056000>; }; &apc0_cpr { - compatible = "qcom,cprh-msmcobalt-v2-kbss-regulator"; + compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; qcom,cpr-corner-switch-delay-time = <1042>; qcom,cpr-aging-ref-voltage = <1056000>; }; @@ -389,7 +389,7 @@ }; &apc1_cpr { - compatible = "qcom,cprh-msmcobalt-v2-kbss-regulator"; + compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; qcom,cpr-corner-switch-delay-time = <1042>; qcom,cpr-aging-ref-voltage = <1056000>; }; @@ -555,7 +555,7 @@ }; &gfx_cpr { - compatible = "qcom,cpr4-msmcobalt-v2-mmss-regulator"; + compatible = "qcom,cpr4-msm8998-v2-mmss-regulator"; qcom,cpr-aging-ref-voltage = <1024000>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-mtp.dts b/arch/arm/boot/dts/qcom/msm8998-v2-mtp.dts index 96e671f04df3..0708573934f3 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2-mtp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2-mtp.dts @@ -13,11 +13,11 @@ /dts-v1/; -#include "msmcobalt-v2.dtsi" -#include "msmcobalt-mtp.dtsi" +#include "msm8998-v2.dtsi" +#include "msm8998-mtp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT v2 MTP"; - compatible = "qcom,msmcobalt-mtp", "qcom,msmcobalt", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. MSM 8998 v2 MTP"; + compatible = "qcom,msm8998-mtp", "qcom,msm8998", "qcom,mtp"; qcom,board-id = <8 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-qrd-skuk.dts b/arch/arm/boot/dts/qcom/msm8998-v2-qrd-skuk.dts index 581e9fef1aeb..471602ac80b9 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2-qrd-skuk.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2-qrd-skuk.dts @@ -13,11 +13,11 @@ /dts-v1/; -#include "msmcobalt-v2.dtsi" -#include "msmcobalt-qrd-skuk.dtsi" +#include "msm8998-v2.dtsi" +#include "msm8998-qrd-skuk.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT V2 SKUK"; - compatible = "qcom,msmcobalt-qrd", "qcom,msmcobalt", "qcom,qrd"; + model = "Qualcomm Technologies, Inc. MSM 8998 V2 SKUK"; + compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd"; qcom,board-id = <0x01000b 0x10>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-qrd-vr1.dts b/arch/arm/boot/dts/qcom/msm8998-v2-qrd-vr1.dts index 15dd2d550b31..58c7dc3bac11 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2-qrd-vr1.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2-qrd-vr1.dts @@ -13,11 +13,11 @@ /dts-v1/; -#include "msmcobalt-v2.dtsi" -#include "msmcobalt-qrd-vr1.dtsi" +#include "msm8998-v2.dtsi" +#include "msm8998-qrd-vr1.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT V2 VR1 Board"; - compatible = "qcom,msmcobalt-qrd", "qcom,msmcobalt", "qcom,qrd"; + model = "Qualcomm Technologies, Inc. MSM 8998 V2 VR1 Board"; + compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd"; qcom,board-id = <0x02000b 0x80>; }; diff --git a/arch/arm/boot/dts/qcom/apqcobalt-v2.1-qrd.dts b/arch/arm/boot/dts/qcom/msm8998-v2-qrd.dts index 8da6f90958d2..37ad18278e5c 100644 --- a/arch/arm/boot/dts/qcom/apqcobalt-v2.1-qrd.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2-qrd.dts @@ -12,11 +12,11 @@ /dts-v1/; -#include "apqcobalt-v2.1.dtsi" -#include "msmcobalt-qrd.dtsi" +#include "msm8998-v2.dtsi" +#include "msm8998-qrd.dtsi" / { - model = "Qualcomm Technologies, Inc. APQ COBALT V2.1 QRD"; - compatible = "qcom,apqcobalt-qrd", "qcom,apqcobalt", "qcom,qrd"; + model = "Qualcomm Technologies, Inc. MSM 8998 v2 QRD"; + compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd"; qcom,board-id = <11 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-rumi.dts b/arch/arm/boot/dts/qcom/msm8998-v2-rumi.dts index cabfb135ca81..e6cf24e593ce 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2-rumi.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2-rumi.dts @@ -14,12 +14,12 @@ /dts-v1/; /memreserve/ 0x90000000 0x00000100; -#include "msmcobalt-v2.dtsi" -#include "msmcobalt-rumi.dtsi" +#include "msm8998-v2.dtsi" +#include "msm8998-rumi.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT V2 RUMI"; - compatible = "qcom,msmcobalt-rumi", "qcom,msmcobalt", "qcom,rumi"; + model = "Qualcomm Technologies, Inc. MSM 8998 V2 RUMI"; + compatible = "qcom,msm8998-rumi", "qcom,msm8998", "qcom,rumi"; qcom,board-id = <15 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2-sim.dts b/arch/arm/boot/dts/qcom/msm8998-v2-sim.dts index 2789b27c9381..91c583df7ff3 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2-sim.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2-sim.dts @@ -14,12 +14,12 @@ /dts-v1/; /memreserve/ 0x90000000 0x00000100; -#include "msmcobalt-v2.dtsi" -#include "msmcobalt-sim.dtsi" +#include "msm8998-v2.dtsi" +#include "msm8998-sim.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT V2 SIM"; - compatible = "qcom,msmcobalt-sim", "qcom,msmcobalt", "qcom,sim"; + model = "Qualcomm Technologies, Inc. MSM 8998 V2 SIM"; + compatible = "qcom,msm8998-sim", "qcom,msm8998", "qcom,sim"; qcom,board-id = <16 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-cdp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-cdp.dts index d5afb1d3c151..871d13bdaa1a 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-cdp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-cdp.dts @@ -13,11 +13,11 @@ /dts-v1/; -#include "msmcobalt-v2.1.dtsi" -#include "msmcobalt-cdp.dtsi" +#include "msm8998-v2.1.dtsi" +#include "msm8998-cdp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT v2.1 CDP"; - compatible = "qcom,msmcobalt-cdp", "qcom,msmcobalt", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 CDP"; + compatible = "qcom,msm8998-cdp", "qcom,msm8998", "qcom,cdp"; qcom,board-id = <1 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-cdp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts index 73bf279052e3..3a7767cf2f2e 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-cdp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-cdp.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "msmcobalt-v2.1-interposer-msmfalcon.dtsi" -#include "msmcobalt-interposer-msmfalcon-cdp.dtsi" -#include "msmcobalt-interposer-pmfalcon.dtsi" +#include "msm8998-v2.1-interposer-msmfalcon.dtsi" +#include "msm8998-interposer-msmfalcon-cdp.dtsi" +#include "msm8998-interposer-pmfalcon.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT v2.1 MSM FALCON Interposer CDP"; - compatible = "qcom,msmcobalt-cdp", "qcom,msmcobalt", "qcom,cdp"; + model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer CDP"; + compatible = "qcom,msm8998-cdp", "qcom,msm8998", "qcom,cdp"; qcom,board-id = <1 1>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-mtp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts index 7807a13489d1..662086f0190f 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-mtp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-mtp.dts @@ -13,13 +13,13 @@ /dts-v1/; -#include "msmcobalt-v2.1-interposer-msmfalcon.dtsi" -#include "msmcobalt-interposer-msmfalcon-mtp.dtsi" -#include "msmcobalt-interposer-pmfalcon.dtsi" +#include "msm8998-v2.1-interposer-msmfalcon.dtsi" +#include "msm8998-interposer-msmfalcon-mtp.dtsi" +#include "msm8998-interposer-pmfalcon.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT v2.1 MSM FALCON Interposer MTP"; - compatible = "qcom,msmcobalt-mtp", "qcom,msmcobalt", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer MTP"; + compatible = "qcom,msm8998-mtp", "qcom,msm8998", "qcom,mtp"; qcom,board-id = <8 2>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts index e5ad123f52a7..ddae02812731 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts @@ -13,12 +13,12 @@ /dts-v1/; -#include "msmcobalt-v2.1-interposer-msmfalcon-qrd.dtsi" +#include "msm8998-v2.1-interposer-msmfalcon-qrd.dtsi" / { model = - "Qualcomm Technologies, Inc. MSM COBALT v2.1 MSM FALCON Interposer QRD"; - compatible = "qcom,msmcobalt-qrd", "qcom,msmcobalt", "qcom,qrd"; + "Qualcomm Technologies, Inc. MSM 8998 v2.1 MSM FALCON Interposer QRD"; + compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd"; qcom,board-id = <0x03000b 0x80>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi index a7d421638dfa..cd0e20a295d9 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon-qrd.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi @@ -11,7 +11,7 @@ */ #include <dt-bindings/interrupt-controller/irq.h> -#include "msmcobalt-v2.1-interposer-msmfalcon.dtsi" +#include "msm8998-v2.1-interposer-msmfalcon.dtsi" &uartblsp2dm1 { status = "ok"; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon.dtsi index 96ff7f70788f..c2a393bd019d 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-interposer-msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon.dtsi @@ -10,9 +10,9 @@ * GNU General Public License for more details. */ -#include "msmcobalt-v2-interposer-msmfalcon.dtsi" +#include "msm8998-v2-interposer-msmfalcon.dtsi" / { - model = "Qualcomm Technologies, Inc. MSMCOBALT v2.1"; + model = "Qualcomm Technologies, Inc. MSM8998 v2.1"; qcom,msm-id = <292 0x20001>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-mtp.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-mtp.dts index f49b43420a06..9d7cbc93d9df 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-mtp.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-mtp.dts @@ -13,11 +13,11 @@ /dts-v1/; -#include "msmcobalt-v2.1.dtsi" -#include "msmcobalt-mtp.dtsi" +#include "msm8998-v2.1.dtsi" +#include "msm8998-mtp.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT v2.1 MTP"; - compatible = "qcom,msmcobalt-mtp", "qcom,msmcobalt", "qcom,mtp"; + model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 MTP"; + compatible = "qcom,msm8998-mtp", "qcom,msm8998", "qcom,mtp"; qcom,board-id = <8 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-qrd.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-qrd.dts index 7a3b6f50932b..b20c888ad933 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.1-qrd.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-qrd.dts @@ -13,11 +13,11 @@ /dts-v1/; -#include "msmcobalt-v2.1.dtsi" -#include "msmcobalt-qrd.dtsi" +#include "msm8998-v2.1.dtsi" +#include "msm8998-qrd.dtsi" / { - model = "Qualcomm Technologies, Inc. MSM COBALT v2.1 QRD"; - compatible = "qcom,msmcobalt-qrd", "qcom,msmcobalt", "qcom,qrd"; + model = "Qualcomm Technologies, Inc. MSM 8998 v2.1 QRD"; + compatible = "qcom,msm8998-qrd", "qcom,msm8998", "qcom,qrd"; qcom,board-id = <11 0>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.1.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1.dtsi index 3f5c42ae8cc8..563157df40a8 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.1.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1.dtsi @@ -10,9 +10,9 @@ * GNU General Public License for more details. */ -#include "msmcobalt-v2.dtsi" +#include "msm8998-v2.dtsi" / { - model = "Qualcomm Technologies, Inc. MSMCOBALT v2.1"; + model = "Qualcomm Technologies, Inc. MSM8998 v2.1"; qcom,msm-id = <292 0x20001>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.dtsi index 93b586df5640..dc1922851a77 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2.dtsi @@ -13,38 +13,19 @@ /* * As a general rule, only version-specific property overrides should be placed * inside this file. Common device definitions should be placed inside the - * msmcobalt.dtsi file. + * msm8998.dtsi file. */ -#include "msmcobalt.dtsi" -#include "msmcobalt-v2-camera.dtsi" +#include "msm8998.dtsi" +#include "msm8998-v2-camera.dtsi" / { - model = "Qualcomm Technologies, Inc. MSMCOBALT v2"; + model = "Qualcomm Technologies, Inc. MSM8998 v2"; qcom,msm-id = <292 0x20000>; }; &clock_cpu { - compatible = "qcom,cpu-clock-osm-msmcobalt-v2"; - reg = <0x179c0000 0x4000>, - <0x17916000 0x1000>, - <0x17816000 0x1000>, - <0x179d1000 0x1000>, - <0x17914800 0x800>, - <0x17814800 0x800>, - <0x00784130 0x8>, - <0x1791101c 0x8>; - reg-names = "osm", "pwrcl_pll", "perfcl_pll", - "apcs_common", "pwrcl_acd", "perfcl_acd", - "perfcl_efuse", "debug"; - - qcom,acdtd-val = <0x00009611 0x00009611>; - qcom,acdcr-val = <0x002b5ffd 0x002b5ffd>; - qcom,acdsscr-val = <0x00000501 0x00000501>; - qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8>; - qcom,acdextint1-val = <0x2cf9afc 0x2cf9afc>; - qcom,acdautoxfer-val = <0x00000015 0x00000015>; - + compatible = "qcom,cpu-clock-osm-msm8998-v2"; /delete-property/ qcom,llm-sw-overr; qcom,pwrcl-speedbin0-v0 = < 300000000 0x0004000f 0x01200020 0x1 1 >, @@ -224,19 +205,19 @@ < 2208000 13763 >; }; &clock_gcc { - compatible = "qcom,gcc-cobalt-v2"; + compatible = "qcom,gcc-8998-v2"; }; &clock_mmss { - compatible = "qcom,mmsscc-cobalt-v2"; + compatible = "qcom,mmsscc-8998-v2"; }; &clock_gpu { - compatible = "qcom,gpucc-cobalt-v2"; + compatible = "qcom,gpucc-8998-v2"; }; &clock_gfx { - compatible = "qcom,gfxcc-cobalt-v2"; + compatible = "qcom,gfxcc-8998-v2"; qcom,gfxfreq-speedbin0 = < 0 0 0 >, < 180000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >, @@ -266,12 +247,12 @@ qcom,max-bandwidth-per-pipe-kbps = <4700000>; }; -&pmcobalt_s10 { +&pm8998_s10 { regulator-min-microvolt = <568000>; regulator-max-microvolt = <1056000>; }; -&pmcobalt_s13 { +&pm8998_s13 { regulator-min-microvolt = <568000>; regulator-max-microvolt = <1056000>; }; @@ -355,7 +336,7 @@ }; &apc0_cpr { - compatible = "qcom,cprh-msmcobalt-v2-kbss-regulator"; + compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; qcom,cpr-corner-switch-delay-time = <1042>; qcom,cpr-aging-ref-voltage = <1056000>; }; @@ -508,7 +489,7 @@ }; &apc1_cpr { - compatible = "qcom,cprh-msmcobalt-v2-kbss-regulator"; + compatible = "qcom,cprh-msm8998-v2-kbss-regulator"; qcom,cpr-corner-switch-delay-time = <1042>; qcom,cpr-aging-ref-voltage = <1056000>; }; @@ -676,7 +657,7 @@ }; &gfx_cpr { - compatible = "qcom,cpr4-msmcobalt-v2-mmss-regulator"; + compatible = "qcom,cpr4-msm8998-v2-mmss-regulator"; qcom,cpr-aging-ref-voltage = <1024000>; }; diff --git a/arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi b/arch/arm/boot/dts/qcom/msm8998-vidc.dtsi index a8655c2e88a0..b8a0b8f3acf2 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-vidc.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-vidc.dtsi @@ -12,7 +12,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/msm/msm-bus-ids.h> -#include <dt-bindings/clock/msm-clocks-cobalt.h> +#include <dt-bindings/clock/msm-clocks-8998.h> &soc { msm_vidc: qcom,vidc@cc00000 { diff --git a/arch/arm/boot/dts/qcom/msmcobalt-wcd.dtsi b/arch/arm/boot/dts/qcom/msm8998-wcd.dtsi index 29f4ccaede9f..29f4ccaede9f 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-wcd.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-wcd.dtsi diff --git a/arch/arm/boot/dts/qcom/msmcobalt-wsa881x.dtsi b/arch/arm/boot/dts/qcom/msm8998-wsa881x.dtsi index baf05c1c241b..746cf23b4c97 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-wsa881x.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-wsa881x.dtsi @@ -9,7 +9,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include "msmcobalt-wcd.dtsi" +#include "msm8998-wcd.dtsi" &slim_aud { tasha_codec { diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msm8998.dtsi index cee85ff63ca8..7f7f2f65deee 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998.dtsi @@ -11,13 +11,13 @@ */ #include "skeleton64.dtsi" -#include <dt-bindings/clock/msm-clocks-cobalt.h> +#include <dt-bindings/clock/msm-clocks-8998.h> #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { - model = "Qualcomm Technologies, Inc. MSM COBALT"; - compatible = "qcom,msmcobalt"; + model = "Qualcomm Technologies, Inc. MSM 8998"; + compatible = "qcom,msm8998"; qcom,msm-id = <292 0x0>; interrupt-parent = <&intc>; @@ -341,8 +341,8 @@ }; }; -#include "msmcobalt-smp2p.dtsi" -#include "msm-gdsc-cobalt.dtsi" +#include "msm8998-smp2p.dtsi" +#include "msm-gdsc-8998.dtsi" &soc { #address-cells = <1>; @@ -731,21 +731,21 @@ }; clock_gcc: qcom,gcc@100000 { - compatible = "qcom,gcc-cobalt"; + compatible = "qcom,gcc-8998"; reg = <0x100000 0xb0000>; reg-names = "cc_base"; - vdd_dig-supply = <&pmcobalt_s1_level>; - vdd_dig_ao-supply = <&pmcobalt_s1_level_ao>; + vdd_dig-supply = <&pm8998_s1_level>; + vdd_dig_ao-supply = <&pm8998_s1_level_ao>; #clock-cells = <1>; #reset-cells = <1>; }; clock_mmss: qcom,mmsscc@c8c0000 { - compatible = "qcom,mmsscc-cobalt"; + compatible = "qcom,mmsscc-8998"; reg = <0xc8c0000 0x40000>; reg-names = "cc_base"; - vdd_dig-supply = <&pmcobalt_s1_level>; - vdd_mmsscc_mx-supply = <&pmcobalt_s9_level>; + vdd_dig-supply = <&pm8998_s1_level>; + vdd_mmsscc_mx-supply = <&pm8998_s9_level>; clock-names = "xo", "gpll0", "gpll0_div", "pclk0_src", "pclk1_src", "byte0_src", "byte1_src", @@ -766,10 +766,10 @@ }; clock_gpu: qcom,gpucc@5065000 { - compatible = "qcom,gpucc-cobalt"; + compatible = "qcom,gpucc-8998"; reg = <0x5065000 0x9000>; reg-names = "cc_base"; - vdd_dig-supply = <&pmcobalt_s1_level>; + vdd_dig-supply = <&pm8998_s1_level>; clock-names = "xo_ao", "gpll0"; clocks = <&clock_gcc clk_cxo_clk_src_ao>, <&clock_gcc clk_gcc_gpu_gpll0_clk>; @@ -777,12 +777,12 @@ }; clock_gfx: qcom,gfxcc@5065000 { - compatible = "qcom,gfxcc-cobalt"; + compatible = "qcom,gfxcc-8998"; reg = <0x5065000 0x9000>; reg-names = "cc_base"; vdd_gpucc-supply = <&gfx_vreg>; - vdd_mx-supply = <&pmcobalt_s9_level>; - vdd_gpu_mx-supply = <&pmcobalt_s9_level>; + vdd_mx-supply = <&pm8998_s9_level>; + vdd_gpu_mx-supply = <&pm8998_s9_level>; qcom,gfx3d_clk_src-opp-handle = <&msm_gpu>; qcom,gfxfreq-speedbin0 = < 0 0 0 >, @@ -803,8 +803,8 @@ #clock-cells = <1>; }; - clock_cpu: qcom,cpu-clock-cobalt@179c0000 { - compatible = "qcom,cpu-clock-osm-msmcobalt-v1"; + clock_cpu: qcom,cpu-clock-8998@179c0000 { + compatible = "qcom,cpu-clock-osm-msm8998-v1"; reg = <0x179c0000 0x4000>, <0x17916000 0x1000>, <0x17816000 0x1000>, @@ -941,7 +941,7 @@ }; clock_debug: qcom,debugcc@162000 { - compatible = "qcom,cc-debug-cobalt"; + compatible = "qcom,cc-debug-8998"; reg = <0x162000 0x4>; reg-names = "cc_base"; clock-names = "debug_gpu_clk", "debug_gfx_clk", @@ -1688,7 +1688,7 @@ <61 512 240000 800000>; qcom,dwc-usb3-msm-tx-fifo-size = <21288>; - extcon = <&pmicobalt_pdphy>; + extcon = <&pmi8998_pdphy>; clocks = <&clock_gcc clk_gcc_usb30_master_clk>, <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>, @@ -1757,9 +1757,9 @@ <0x01fcb24c 0x4>; reg-names = "qusb_phy_base", "tcsr_clamp_dig_n_1p8"; - vdd-supply = <&pmcobalt_l1>; - vdda18-supply = <&pmcobalt_l12>; - vdda33-supply = <&pmcobalt_l24>; + vdd-supply = <&pm8998_l1>; + vdda18-supply = <&pm8998_l12>; + vdda33-supply = <&pm8998_l24>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,qusb-phy-init-seq = /* <value reg_offset> */ @@ -1787,8 +1787,8 @@ reg-names = "qmp_phy_base", "vls_clamp_reg", "tcsr_usb3_dp_phymode"; - vdd-supply = <&pmcobalt_l1>; - core-supply = <&pmcobalt_l2>; + vdd-supply = <&pm8998_l1>; + core-supply = <&pm8998_l2>; qcom,vdd-voltage-level = <0 880000 880000>; qcom,vbus-valid-override; qcom,qmp-phy-init-seq = @@ -1957,7 +1957,7 @@ reg = <0x17300000 0x00100>; interrupts = <0 162 1>; - vdd_cx-supply = <&pmcobalt_s1_level>; + vdd_cx-supply = <&pm8998_s1_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; @@ -2038,9 +2038,9 @@ "mnoc_axi_clk"; interrupts = <0 448 1>; - vdd_cx-supply = <&pmcobalt_s1_level>; + vdd_cx-supply = <&pm8998_s1_level>; vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; - vdd_mx-supply = <&pmcobalt_s9_level>; + vdd_mx-supply = <&pm8998_s9_level>; vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; qcom,firmware-name = "modem"; qcom,pil-self-auth; @@ -2064,7 +2064,7 @@ }; tsens0: tsens@10aa000 { - compatible = "qcom,msmcobalt-tsens"; + compatible = "qcom,msm8998-tsens"; reg = <0x10aa000 0x2000>; reg-names = "tsens_physical"; interrupts = <0 458 0>, <0 445 0>; @@ -2075,7 +2075,7 @@ }; tsens1: tsens@10ad000 { - compatible = "qcom,msmcobalt-tsens"; + compatible = "qcom,msm8998-tsens"; reg = <0x10ad000 0x2000>; reg-names = "tsens_physical"; interrupts = <0 184 0>, <0 430 0>; @@ -2092,7 +2092,7 @@ <&clock_gcc clk_gcc_blsp2_ahb_clk>; clock-frequency = <15000000>; qcom,ipc-gpio = <&tlmm 121 0>; - qcom,finger-detect-gpio = <&pmcobalt_gpios 2 0>; + qcom,finger-detect-gpio = <&pm8998_gpios 2 0>; }; qcom,sensor-information { @@ -2410,7 +2410,7 @@ qcom,vdd-restriction-temp = <5>; qcom,vdd-restriction-temp-hysteresis = <10>; - vdd-dig-supply = <&pmcobalt_s1_floor_level>; + vdd-dig-supply = <&pm8998_s1_floor_level>; vdd-gfx-supply = <&gfx_vreg>; qcom,vdd-dig-rstr{ @@ -2596,9 +2596,9 @@ wake-gpio = <&tlmm 37 0>; gdsc-vdd-supply = <&gdsc_pcie_0>; - vreg-1.8-supply = <&pmcobalt_l2>; - vreg-0.9-supply = <&pmcobalt_l1>; - vreg-cx-supply = <&pmcobalt_s1_level>; + vreg-1.8-supply = <&pm8998_l2>; + vreg-0.9-supply = <&pm8998_l1>; + vreg-cx-supply = <&pm8998_s1_level>; qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; qcom,vreg-0.9-voltage-level = <880000 880000 24000>; @@ -2682,8 +2682,8 @@ reg = <0x5c00000 0x4000>; interrupts = <0 390 1>; - vdd_cx-supply = <&pmcobalt_l27_level>; - vdd_px-supply = <&pmcobalt_lvs2>; + vdd_cx-supply = <&pm8998_l27_level>; + vdd_px-supply = <&pm8998_lvs2>; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 0>; qcom,proxy-reg-names = "vdd_cx", "vdd_px"; qcom,keep-proxy-regs-on; @@ -2766,7 +2766,7 @@ "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; interrupts = <0 352 1>; - vdd_cx-supply = <&pmcobalt_s1_level>; + vdd_cx-supply = <&pm8998_s1_level>; qcom,proxy-reg-names = "vdd_cx"; qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; @@ -2988,14 +2988,19 @@ <0 424 0 /* CE10 */ >, <0 425 0 /* CE11 */ >; qcom,wlan-msa-memory = <0x100000>; - vdd-0.8-cx-mx-supply = <&pmcobalt_l5>; - vdd-1.8-xo-supply = <&pmcobalt_l7_pin_ctrl>; - vdd-1.3-rfa-supply = <&pmcobalt_l17_pin_ctrl>; - vdd-3.3-ch0-supply = <&pmcobalt_l25_pin_ctrl>; + vdd-0.8-cx-mx-supply = <&pm8998_l5>; + vdd-1.8-xo-supply = <&pm8998_l7_pin_ctrl>; + vdd-1.3-rfa-supply = <&pm8998_l17_pin_ctrl>; + vdd-3.3-ch0-supply = <&pm8998_l25_pin_ctrl>; qcom,vdd-0.8-cx-mx-config = <800000 800000>; qcom,vdd-3.3-ch0-config = <3104000 3312000>; - qcom,icnss-vadc = <&pmcobalt_vadc>; - qcom,icnss-adc_tm = <&pmcobalt_adc_tm>; + qcom,msm-bus,name = "msm-icnss"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <81 10065 0 0>, + <81 10065 0 16000>; + qcom,icnss-vadc = <&pm8998_vadc>; + qcom,icnss-adc_tm = <&pm8998_adc_tm>; }; tspp: msm_tspp@0c1e7000 { @@ -3060,8 +3065,8 @@ <45 512 0 0>, <45 512 600000 800000>; /* ~4.6Gbps (MCS12) */ qcom,use-ext-supply; - vdd-supply= <&pmcobalt_s7>; - vddio-supply= <&pmcobalt_s5>; + vdd-supply= <&pm8998_s7>; + vddio-supply= <&pm8998_s5>; qcom,use-ext-clocks; clocks = <&clock_gcc clk_rf_clk3>, <&clock_gcc clk_rf_clk3_pin>; @@ -3174,25 +3179,25 @@ status = "ok"; }; -#include "msm-pmcobalt.dtsi" -#include "msm-pmicobalt.dtsi" +#include "msm-pm8998.dtsi" +#include "msm-pmi8998.dtsi" #include "msm-pm8005.dtsi" -#include "msm-pmcobalt-rpm-regulator.dtsi" -#include "msmcobalt-regulator.dtsi" - -#include "msmcobalt-pm.dtsi" -#include "msm-arm-smmu-cobalt.dtsi" -#include "msm-arm-smmu-impl-defs-cobalt.dtsi" -#include "msmcobalt-ion.dtsi" -#include "msmcobalt-camera.dtsi" -#include "msmcobalt-vidc.dtsi" -#include "msmcobalt-coresight.dtsi" -#include "msmcobalt-bus.dtsi" -#include "msmcobalt-gpu.dtsi" -#include "msmcobalt-pinctrl.dtsi" +#include "msm-pm8998-rpm-regulator.dtsi" +#include "msm8998-regulator.dtsi" + +#include "msm8998-pm.dtsi" +#include "msm-arm-smmu-8998.dtsi" +#include "msm-arm-smmu-impl-defs-8998.dtsi" +#include "msm8998-ion.dtsi" +#include "msm8998-camera.dtsi" +#include "msm8998-vidc.dtsi" +#include "msm8998-coresight.dtsi" +#include "msm8998-bus.dtsi" +#include "msm8998-gpu.dtsi" +#include "msm8998-pinctrl.dtsi" #include "msm-audio-lpass.dtsi" -#include "msmcobalt-mdss.dtsi" -#include "msmcobalt-mdss-pll.dtsi" +#include "msm8998-mdss.dtsi" +#include "msm8998-mdss-pll.dtsi" #include "msm-rdbg.dtsi" -#include "msmcobalt-blsp.dtsi" -#include "msmcobalt-audio.dtsi" +#include "msm8998-blsp.dtsi" +#include "msm8998-audio.dtsi" diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts index 1575cea079ce..00efa39f017d 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts @@ -102,3 +102,8 @@ &pmfalcon_fg { status = "disabled"; }; + +&clock_gfx { + compatible = "qcom,dummycc"; + clock-output-names = "gfx_clocks"; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index e2f5e32cc544..944f662ccc52 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -467,8 +467,21 @@ }; clock_gfx: clock-controller@5065000 { - compatible = "qcom,dummycc"; - clock-output-names = "gfx_clocks"; + compatible = "qcom,gpucc-msmfalcon"; + reg = <0x5065000 0x10000>; + vdd_dig_gfx-supply = <&pm2falcon_s3_level>; + vdd_mx_gfx-supply = <&pm2falcon_s5_level>; + vdd_gfx-supply = <&gfx_vreg_corner>; + qcom,gfxfreq-corner = + < 0 0>, + < 160000000 1>, /* MinSVS */ + < 266000000 2>, /* LowSVS */ + < 370000000 3>, /* SVS */ + < 465000000 4>, /* SVS_L1 */ + < 588000000 5>, /* NOM */ + < 647000000 6>, /* NOM_L1 */ + < 700000000 7>, /* TURBO */ + < 750000000 7>; /* TURBO */ #clock-cells = <1>; #reset-cells = <1>; }; @@ -985,10 +998,8 @@ }; &gdsc_gpu_gx { - clock-names = "bimc_core_clk", "core_clk", "core_root_clk"; - clocks = <&clock_gcc GCC_GPU_BIMC_GFX_CLK>, - <&clock_gfx GPUCC_GFX3D_CLK>, - <&clock_gfx GFX3D_CLK_SRC>; + clock-names = "core_root_clk"; + clocks = <&clock_gfx GFX3D_CLK_SRC>; qcom,force-enable-root-clk; parent-supply = <&gfx_vreg_corner>; status = "ok"; diff --git a/arch/arm/boot/dts/qcom/msmhamster-cdp.dts b/arch/arm/boot/dts/qcom/msmhamster-cdp.dts index dcb4b0830da3..a9a3e6d9f88a 100644 --- a/arch/arm/boot/dts/qcom/msmhamster-cdp.dts +++ b/arch/arm/boot/dts/qcom/msmhamster-cdp.dts @@ -14,7 +14,7 @@ /dts-v1/; #include "msmhamster.dtsi" -#include "msmcobalt-cdp.dtsi" +#include "msm8998-cdp.dtsi" / { model = "Qualcomm Technologies, Inc. MSM HAMSTER"; diff --git a/arch/arm/boot/dts/qcom/msmhamster-mtp.dts b/arch/arm/boot/dts/qcom/msmhamster-mtp.dts index 72106c97db40..5d63fcb88e8a 100644 --- a/arch/arm/boot/dts/qcom/msmhamster-mtp.dts +++ b/arch/arm/boot/dts/qcom/msmhamster-mtp.dts @@ -14,7 +14,7 @@ /dts-v1/; #include "msmhamster.dtsi" -#include "msmcobalt-mtp.dtsi" +#include "msm8998-mtp.dtsi" / { model = "Qualcomm Technologies, Inc. MSM HAMSTER"; diff --git a/arch/arm/boot/dts/qcom/msmhamster-rumi.dts b/arch/arm/boot/dts/qcom/msmhamster-rumi.dts index ac95d1f6618d..250fe060a9af 100644 --- a/arch/arm/boot/dts/qcom/msmhamster-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmhamster-rumi.dts @@ -15,7 +15,7 @@ /memreserve/ 0x90000000 0x00000100; #include "msmhamster.dtsi" -#include "msmcobalt-rumi.dtsi" +#include "msm8998-rumi.dtsi" / { model = "Qualcomm Technologies, Inc. MSM HAMSTER RUMI"; diff --git a/arch/arm/boot/dts/qcom/msmhamster.dtsi b/arch/arm/boot/dts/qcom/msmhamster.dtsi index 952740ae54e8..30308182e199 100644 --- a/arch/arm/boot/dts/qcom/msmhamster.dtsi +++ b/arch/arm/boot/dts/qcom/msmhamster.dtsi @@ -13,10 +13,10 @@ /* * As a general rule, only version-specific property overrides should be placed * inside this file. Common device definitions should be placed inside the - * msmcobalt.dtsi file. + * msm8998.dtsi file. */ -#include "msmcobalt-v2.dtsi" +#include "msm8998-v2.dtsi" / { model = "Qualcomm Technologies, Inc. MSM HAMSTER"; diff --git a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts index 08809fb38cae..491b55aab9a6 100644 --- a/arch/arm/boot/dts/qcom/msmtriton-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmtriton-rumi.dts @@ -63,3 +63,8 @@ compatible = "qcom,dummycc"; clock-output-names = "gcc_clocks"; }; + +&clock_gfx { + compatible = "qcom,dummycc"; + clock-output-names = "gfx_clocks"; +}; diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi index cd751f3181ee..00dad563a020 100644 --- a/arch/arm/boot/dts/qcom/msmtriton.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi @@ -382,8 +382,21 @@ }; clock_gfx: clock-controller@5065000 { - compatible = "qcom,dummycc"; - clock-output-names = "gfx_clocks"; + compatible = "qcom,gpucc-msmfalcon"; + reg = <0x5065000 0x10000>; + vdd_dig_gfx-supply = <&pm2falcon_s3_level>; + vdd_mx_gfx-supply = <&pm2falcon_s5_level>; + vdd_gfx-supply = <&gfx_vreg_corner>; + qcom,gfxfreq-corner = + < 0 0>, + < 160000000 1>, /* MinSVS */ + < 266000000 2>, /* LowSVS */ + < 370000000 3>, /* SVS */ + < 465000000 4>, /* SVS_L1 */ + < 588000000 5>, /* NOM */ + < 647000000 6>, /* NOM_L1 */ + < 700000000 7>, /* TURBO */ + < 750000000 7>; /* TURBO */ #clock-cells = <1>; #reset-cells = <1>; }; @@ -794,10 +807,8 @@ }; &gdsc_gpu_gx { - clock-names = "bimc_core_clk", "core_clk", "core_root_clk"; - clocks = <&clock_gcc GCC_GPU_BIMC_GFX_CLK>, - <&clock_gfx GPUCC_GFX3D_CLK>, - <&clock_gfx GFX3D_CLK_SRC>; + clock-names = "core_root_clk"; + clocks = <&clock_gfx GFX3D_CLK_SRC>; qcom,force-enable-root-clk; parent-supply = <&gfx_vreg_corner>; status = "ok"; diff --git a/arch/arm/configs/msmcortex_defconfig b/arch/arm/configs/msmcortex_defconfig index f8743e760054..b55857fd7cc4 100644 --- a/arch/arm/configs/msmcortex_defconfig +++ b/arch/arm/configs/msmcortex_defconfig @@ -288,7 +288,7 @@ CONFIG_SPI=y CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PINCTRL_MSMCOBALT=y +CONFIG_PINCTRL_MSM8998=y CONFIG_PINCTRL_MSMFALCON=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y diff --git a/arch/arm/configs/msmfalcon_defconfig b/arch/arm/configs/msmfalcon_defconfig index d10fba1dc4b5..abd89c1ca060 100644 --- a/arch/arm/configs/msmfalcon_defconfig +++ b/arch/arm/configs/msmfalcon_defconfig @@ -289,7 +289,7 @@ CONFIG_SPI=y CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PINCTRL_MSMCOBALT=y +CONFIG_PINCTRL_MSM8998=y CONFIG_PINCTRL_MSMFALCON=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_QPNP_PIN=y @@ -422,7 +422,7 @@ CONFIG_RMNET_IPA3=y CONFIG_GPIO_USB_DETECT=y CONFIG_USB_BAM=y CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_MSM_GCC_FALCON=y +CONFIG_MSM_GPUCC_FALCON=y CONFIG_REMOTE_SPINLOCK_MSM=y CONFIG_ARM_SMMU=y CONFIG_IOMMU_DEBUG=y diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 94c0bf30c284..56b7f310ddbc 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -69,12 +69,12 @@ config ARCH_MSM8996 This enables support for the MSM8996 chipset. If you do not wish to build a kernel that runs on this chipset, say 'N' here. -config ARCH_MSMCOBALT - bool "Enable Support for Qualcomm MSMCOBALT" +config ARCH_MSM8998 + bool "Enable Support for Qualcomm MSM8998" depends on ARCH_QCOM select COMMON_CLK_MSM help - This enables support for the MSMCOBALT chipset. If you do not + This enables support for the MSM8998 chipset. If you do not wish to build a kernel that runs on this chipset, say 'N' here. config ARCH_MSMHAMSTER diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig index 3990bece1dd1..23287f8d06ea 100644 --- a/arch/arm64/configs/msmcortex-perf_defconfig +++ b/arch/arm64/configs/msmcortex-perf_defconfig @@ -45,7 +45,7 @@ CONFIG_MODULE_SIG_FORCE=y CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMCOBALT=y +CONFIG_ARCH_MSM8998=y CONFIG_ARCH_MSMHAMSTER=y CONFIG_PCI=y CONFIG_PCI_MSM=y @@ -301,7 +301,7 @@ CONFIG_SPI=y CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PINCTRL_MSMCOBALT=y +CONFIG_PINCTRL_MSM8998=y CONFIG_PINCTRL_MSMFALCON=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y @@ -405,7 +405,7 @@ CONFIG_SND=y CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_AUDIO_QMI=y CONFIG_SND_SOC=y -CONFIG_SND_SOC_MSMCOBALT=y +CONFIG_SND_SOC_MSM8998=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig index 15ca50859eca..9cec02c83936 100644 --- a/arch/arm64/configs/msmcortex_defconfig +++ b/arch/arm64/configs/msmcortex_defconfig @@ -46,7 +46,7 @@ CONFIG_MODULE_SIG_SHA512=y CONFIG_PARTITION_ADVANCED=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_QCOM=y -CONFIG_ARCH_MSMCOBALT=y +CONFIG_ARCH_MSM8998=y CONFIG_ARCH_MSMHAMSTER=y CONFIG_PCI=y CONFIG_PCI_MSM=y @@ -304,7 +304,7 @@ CONFIG_SPI=y CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PINCTRL_MSMCOBALT=y +CONFIG_PINCTRL_MSM8998=y CONFIG_PINCTRL_MSMFALCON=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y @@ -408,7 +408,7 @@ CONFIG_SND=y CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_AUDIO_QMI=y CONFIG_SND_SOC=y -CONFIG_SND_SOC_MSMCOBALT=y +CONFIG_SND_SOC_MSM8998=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y diff --git a/arch/arm64/configs/msmfalcon-perf_defconfig b/arch/arm64/configs/msmfalcon-perf_defconfig index df695f993ed9..1074672d252f 100644 --- a/arch/arm64/configs/msmfalcon-perf_defconfig +++ b/arch/arm64/configs/msmfalcon-perf_defconfig @@ -304,7 +304,7 @@ CONFIG_SPI=y CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PINCTRL_MSMCOBALT=y +CONFIG_PINCTRL_MSM8998=y CONFIG_PINCTRL_MSMFALCON=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y @@ -408,7 +408,7 @@ CONFIG_SND=y CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_AUDIO_QMI=y CONFIG_SND_SOC=y -CONFIG_SND_SOC_MSMCOBALT=y +CONFIG_SND_SOC_MSM8998=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y @@ -489,7 +489,7 @@ CONFIG_GPIO_USB_DETECT=y CONFIG_SEEMP_CORE=y CONFIG_USB_BAM=y CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_MSM_GCC_FALCON=y +CONFIG_MSM_GPUCC_FALCON=y CONFIG_REMOTE_SPINLOCK_MSM=y CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_ARM_SMMU=y diff --git a/arch/arm64/configs/msmfalcon_defconfig b/arch/arm64/configs/msmfalcon_defconfig index 8719eb7cb92e..6d8d9eeab2d5 100644 --- a/arch/arm64/configs/msmfalcon_defconfig +++ b/arch/arm64/configs/msmfalcon_defconfig @@ -307,7 +307,6 @@ CONFIG_SPI=y CONFIG_SPI_QUP=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y -CONFIG_PINCTRL_MSMCOBALT=y CONFIG_PINCTRL_MSMFALCON=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y @@ -411,7 +410,7 @@ CONFIG_SND=y CONFIG_SND_USB_AUDIO=y CONFIG_SND_USB_AUDIO_QMI=y CONFIG_SND_SOC=y -CONFIG_SND_SOC_MSMCOBALT=y +CONFIG_SND_SOC_MSM8998=y CONFIG_UHID=y CONFIG_HID_APPLE=y CONFIG_HID_ELECOM=y @@ -499,7 +498,7 @@ CONFIG_GPIO_USB_DETECT=y CONFIG_SEEMP_CORE=y CONFIG_USB_BAM=y CONFIG_QCOM_CLK_SMD_RPM=y -CONFIG_MSM_GCC_FALCON=y +CONFIG_MSM_GPUCC_FALCON=y CONFIG_REMOTE_SPINLOCK_MSM=y CONFIG_IOMMU_IO_PGTABLE_FAST=y CONFIG_IOMMU_IO_PGTABLE_FAST_SELFTEST=y diff --git a/block/genhd.c b/block/genhd.c index 817c67c9e45e..82bc52cad1c1 100644 --- a/block/genhd.c +++ b/block/genhd.c @@ -831,6 +831,7 @@ static void disk_seqf_stop(struct seq_file *seqf, void *v) if (iter) { class_dev_iter_exit(iter); kfree(iter); + seqf->private = NULL; } } diff --git a/block/ioprio.c b/block/ioprio.c index cc7800e9eb44..01b8116298a1 100644 --- a/block/ioprio.c +++ b/block/ioprio.c @@ -150,8 +150,10 @@ static int get_task_ioprio(struct task_struct *p) if (ret) goto out; ret = IOPRIO_PRIO_VALUE(IOPRIO_CLASS_NONE, IOPRIO_NORM); + task_lock(p); if (p->io_context) ret = p->io_context->ioprio; + task_unlock(p); out: return ret; } diff --git a/drivers/clk/msm/Kconfig b/drivers/clk/msm/Kconfig index 650a23ea1ead..bfb697347ec5 100644 --- a/drivers/clk/msm/Kconfig +++ b/drivers/clk/msm/Kconfig @@ -7,7 +7,7 @@ config COMMON_CLK_MSM This support clock controller used by MSM devices which support global, mmss and gpu clock controller. Say Y if you want to support the clocks exposed by the MSM on - platforms such as msm8996, msmcobalt, msmfalcon etc. + platforms such as msm8996, msm8998, msmfalcon etc. config MSM_CLK_CONTROLLER_V2 bool "QTI clock driver" diff --git a/drivers/clk/msm/Makefile b/drivers/clk/msm/Makefile index baf22bf1df9a..27e07eb12205 100644 --- a/drivers/clk/msm/Makefile +++ b/drivers/clk/msm/Makefile @@ -19,12 +19,12 @@ ifeq ($(CONFIG_COMMON_CLK_MSM), y) obj-$(CONFIG_ARCH_MSM8996) += clock-cpu-8996.o endif -# MSM COBALT +# MSM 8998 ifeq ($(CONFIG_COMMON_CLK_MSM), y) - obj-$(CONFIG_ARCH_MSMCOBALT) += clock-gcc-cobalt.o - obj-$(CONFIG_ARCH_MSMCOBALT) += clock-gpu-cobalt.o - obj-$(CONFIG_ARCH_MSMCOBALT) += clock-mmss-cobalt.o - obj-$(CONFIG_ARCH_MSMCOBALT) += clock-osm.o + obj-$(CONFIG_ARCH_MSM8998) += clock-gcc-8998.o + obj-$(CONFIG_ARCH_MSM8998) += clock-gpu-8998.o + obj-$(CONFIG_ARCH_MSM8998) += clock-mmss-8998.o + obj-$(CONFIG_ARCH_MSM8998) += clock-osm.o endif obj-$(CONFIG_COMMON_CLK_MSM) += gdsc.o diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-8998.c index f2a3f7402f67..b1d767a4cb6f 100644 --- a/drivers/clk/msm/clock-gcc-cobalt.c +++ b/drivers/clk/msm/clock-gcc-8998.c @@ -28,10 +28,10 @@ #include <soc/qcom/rpm-smd.h> #include <soc/qcom/clock-rpm.h> -#include <dt-bindings/clock/msm-clocks-cobalt.h> -#include <dt-bindings/clock/msm-clocks-hwio-cobalt.h> +#include <dt-bindings/clock/msm-clocks-8998.h> +#include <dt-bindings/clock/msm-clocks-hwio-8998.h> -#include "vdd-level-cobalt.h" +#include "vdd-level-8998.h" #include "reset.h" static void __iomem *virt_base; @@ -2444,7 +2444,7 @@ static struct mux_clk gcc_debug_mux = { }, }; -static struct clk_lookup msm_clocks_rpm_cobalt[] = { +static struct clk_lookup msm_clocks_rpm_8998[] = { CLK_LIST(cxo_clk_src), CLK_LIST(bimc_clk), CLK_LIST(bimc_a_clk), @@ -2520,7 +2520,7 @@ static struct clk_lookup msm_clocks_rpm_cobalt[] = { CLK_LIST(gcc_ce1_axi_m_clk), }; -static struct clk_lookup msm_clocks_gcc_cobalt[] = { +static struct clk_lookup msm_clocks_gcc_8998[] = { CLK_LIST(gpll0), CLK_LIST(gpll0_ao), CLK_LIST(gpll0_out_main), @@ -2685,7 +2685,7 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_qspi_ref_clk), }; -static const struct msm_reset_map gcc_cobalt_resets[] = { +static const struct msm_reset_map gcc_8998_resets[] = { [QUSB2PHY_PRIM_BCR] = { 0x12000 }, [QUSB2PHY_SEC_BCR] = { 0x12004 }, [BLSP1_BCR] = { 0x17000 }, @@ -2702,7 +2702,7 @@ static const struct msm_reset_map gcc_cobalt_resets[] = { [PCIE_PHY_COM_BCR] = { 0x6f014 }, }; -static void msm_gcc_cobalt_v1_fixup(void) +static void msm_gcc_8998_v1_fixup(void) { gcc_ufs_rx_symbol_1_clk.c.ops = &clk_ops_dummy; qspi_ref_clk_src.c.ops = &clk_ops_dummy; @@ -2710,14 +2710,14 @@ static void msm_gcc_cobalt_v1_fixup(void) gcc_qspi_ahb_clk.c.ops = &clk_ops_dummy; } -static void msm_gcc_cobalt_v2_fixup(void) +static void msm_gcc_8998_v2_fixup(void) { qspi_ref_clk_src.c.ops = &clk_ops_dummy; gcc_qspi_ref_clk.c.ops = &clk_ops_dummy; gcc_qspi_ahb_clk.c.ops = &clk_ops_dummy; } -static int msm_gcc_cobalt_probe(struct platform_device *pdev) +static int msm_gcc_8998_probe(struct platform_device *pdev) { struct resource *res; u32 regval; @@ -2765,8 +2765,8 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev) } bimc_clk.c.parent = &cxo_clk_src.c; - ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_rpm_cobalt, - ARRAY_SIZE(msm_clocks_rpm_cobalt)); + ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_rpm_8998, + ARRAY_SIZE(msm_clocks_rpm_8998)); if (ret) return ret; @@ -2774,17 +2774,17 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev) if (ret < 0) return ret; - is_v1 = of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-cobalt"); + is_v1 = of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-8998"); if (is_v1) - msm_gcc_cobalt_v1_fixup(); + msm_gcc_8998_v1_fixup(); is_v2 = of_device_is_compatible(pdev->dev.of_node, - "qcom,gcc-cobalt-v2"); + "qcom,gcc-8998-v2"); if (is_v2) - msm_gcc_cobalt_v2_fixup(); + msm_gcc_8998_v2_fixup(); - ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_gcc_cobalt, - ARRAY_SIZE(msm_clocks_gcc_cobalt)); + ret = of_msm_clock_register(pdev->dev.of_node, msm_clocks_gcc_8998, + ARRAY_SIZE(msm_clocks_gcc_8998)); if (ret) return ret; @@ -2808,37 +2808,37 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev) clk_set_flags(&gcc_gpu_bimc_gfx_clk.c, CLKFLAG_RETAIN_MEM); /* Register block resets */ - msm_reset_controller_register(pdev, gcc_cobalt_resets, - ARRAY_SIZE(gcc_cobalt_resets), virt_base); + msm_reset_controller_register(pdev, gcc_8998_resets, + ARRAY_SIZE(gcc_8998_resets), virt_base); dev_info(&pdev->dev, "Registered GCC clocks\n"); return 0; } static struct of_device_id msm_clock_gcc_match_table[] = { - { .compatible = "qcom,gcc-cobalt" }, - { .compatible = "qcom,gcc-cobalt-v2" }, + { .compatible = "qcom,gcc-8998" }, + { .compatible = "qcom,gcc-8998-v2" }, { .compatible = "qcom,gcc-hamster" }, {} }; static struct platform_driver msm_clock_gcc_driver = { - .probe = msm_gcc_cobalt_probe, + .probe = msm_gcc_8998_probe, .driver = { - .name = "qcom,gcc-cobalt", + .name = "qcom,gcc-8998", .of_match_table = msm_clock_gcc_match_table, .owner = THIS_MODULE, }, }; -int __init msm_gcc_cobalt_init(void) +int __init msm_gcc_8998_init(void) { return platform_driver_register(&msm_clock_gcc_driver); } -arch_initcall(msm_gcc_cobalt_init); +arch_initcall(msm_gcc_8998_init); /* ======== Clock Debug Controller ======== */ -static struct clk_lookup msm_clocks_measure_cobalt[] = { +static struct clk_lookup msm_clocks_measure_8998[] = { CLK_LIST(gpu_gcc_debug_clk), CLK_LIST(gfx_gcc_debug_clk), CLK_LIST(debug_mmss_clk), @@ -2847,11 +2847,11 @@ static struct clk_lookup msm_clocks_measure_cobalt[] = { }; static struct of_device_id msm_clock_debug_match_table[] = { - { .compatible = "qcom,cc-debug-cobalt" }, + { .compatible = "qcom,cc-debug-8998" }, {} }; -static int msm_clock_debug_cobalt_probe(struct platform_device *pdev) +static int msm_clock_debug_8998_probe(struct platform_device *pdev) { struct resource *res; int ret; @@ -2883,8 +2883,8 @@ static int msm_clock_debug_cobalt_probe(struct platform_device *pdev) debug_cpu_clk.clk_id = "debug_cpu_clk"; ret = of_msm_clock_register(pdev->dev.of_node, - msm_clocks_measure_cobalt, - ARRAY_SIZE(msm_clocks_measure_cobalt)); + msm_clocks_measure_8998, + ARRAY_SIZE(msm_clocks_measure_8998)); if (ret) return ret; @@ -2893,16 +2893,16 @@ static int msm_clock_debug_cobalt_probe(struct platform_device *pdev) } static struct platform_driver msm_clock_debug_driver = { - .probe = msm_clock_debug_cobalt_probe, + .probe = msm_clock_debug_8998_probe, .driver = { - .name = "qcom,cc-debug-cobalt", + .name = "qcom,cc-debug-8998", .of_match_table = msm_clock_debug_match_table, .owner = THIS_MODULE, }, }; -int __init msm_clock_debug_cobalt_init(void) +int __init msm_clock_debug_8998_init(void) { return platform_driver_register(&msm_clock_debug_driver); } -late_initcall(msm_clock_debug_cobalt_init); +late_initcall(msm_clock_debug_8998_init); diff --git a/drivers/clk/msm/clock-gpu-cobalt.c b/drivers/clk/msm/clock-gpu-8998.c index 7cec9be1f42c..e4789a51b738 100644 --- a/drivers/clk/msm/clock-gpu-cobalt.c +++ b/drivers/clk/msm/clock-gpu-8998.c @@ -27,10 +27,10 @@ #include <soc/qcom/clock-pll.h> #include <soc/qcom/clock-alpha-pll.h> -#include <dt-bindings/clock/msm-clocks-cobalt.h> -#include <dt-bindings/clock/msm-clocks-hwio-cobalt.h> +#include <dt-bindings/clock/msm-clocks-8998.h> +#include <dt-bindings/clock/msm-clocks-hwio-8998.h> -#include "vdd-level-cobalt.h" +#include "vdd-level-8998.h" static void __iomem *virt_base; static void __iomem *virt_base_gfx; @@ -490,7 +490,7 @@ static struct mux_clk gfxcc_dbg_clk = { }, }; -static struct clk_lookup msm_clocks_gpucc_cobalt[] = { +static struct clk_lookup msm_clocks_gpucc_8998[] = { CLK_LIST(gpucc_xo), CLK_LIST(gpucc_gpll0), CLK_LIST(gpucc_cxo_clk), @@ -510,7 +510,7 @@ static void msm_gpucc_hamster_fixup(void) } static struct platform_driver msm_clock_gfxcc_driver; -int msm_gpucc_cobalt_probe(struct platform_device *pdev) +int msm_gpucc_8998_probe(struct platform_device *pdev) { struct resource *res; struct device_node *of_node = pdev->dev.of_node; @@ -563,8 +563,8 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) if (is_vq) msm_gpucc_hamster_fixup(); - rc = of_msm_clock_register(of_node, msm_clocks_gpucc_cobalt, - ARRAY_SIZE(msm_clocks_gpucc_cobalt)); + rc = of_msm_clock_register(of_node, msm_clocks_gpucc_8998, + ARRAY_SIZE(msm_clocks_gpucc_8998)); if (rc) return rc; @@ -579,22 +579,22 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) } static const struct of_device_id msm_clock_gpucc_match_table[] = { - { .compatible = "qcom,gpucc-cobalt" }, - { .compatible = "qcom,gpucc-cobalt-v2" }, + { .compatible = "qcom,gpucc-8998" }, + { .compatible = "qcom,gpucc-8998-v2" }, { .compatible = "qcom,gpucc-hamster" }, {}, }; static struct platform_driver msm_clock_gpucc_driver = { - .probe = msm_gpucc_cobalt_probe, + .probe = msm_gpucc_8998_probe, .driver = { - .name = "qcom,gpucc-cobalt", + .name = "qcom,gpucc-8998", .of_match_table = msm_clock_gpucc_match_table, .owner = THIS_MODULE, }, }; -static struct clk_lookup msm_clocks_gfxcc_cobalt[] = { +static struct clk_lookup msm_clocks_gfxcc_8998[] = { CLK_LIST(gpu_pll0_pll), CLK_LIST(gpu_pll0_pll_out_even), CLK_LIST(gpu_pll0_pll_out_odd), @@ -610,13 +610,13 @@ static void msm_gfxcc_hamster_fixup(void) gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_vq; } -static void msm_gfxcc_cobalt_v2_fixup(void) +static void msm_gfxcc_8998_v2_fixup(void) { gpu_pll0_pll.c.fmax[VDD_DIG_MIN] = 1420000500; gfx3d_clk_src.freq_tbl = ftbl_gfx3d_clk_src_v2; } -int msm_gfxcc_cobalt_probe(struct platform_device *pdev) +int msm_gfxcc_8998_probe(struct platform_device *pdev) { struct resource *res; struct device_node *of_node = pdev->dev.of_node; @@ -675,17 +675,17 @@ int msm_gfxcc_cobalt_probe(struct platform_device *pdev) } is_v2 = of_device_is_compatible(pdev->dev.of_node, - "qcom,gfxcc-cobalt-v2"); + "qcom,gfxcc-8998-v2"); if (is_v2) - msm_gfxcc_cobalt_v2_fixup(); + msm_gfxcc_8998_v2_fixup(); is_vq = of_device_is_compatible(pdev->dev.of_node, "qcom,gfxcc-hamster"); if (is_vq) msm_gfxcc_hamster_fixup(); - rc = of_msm_clock_register(of_node, msm_clocks_gfxcc_cobalt, - ARRAY_SIZE(msm_clocks_gfxcc_cobalt)); + rc = of_msm_clock_register(of_node, msm_clocks_gfxcc_8998, + ARRAY_SIZE(msm_clocks_gfxcc_8998)); if (rc) return rc; @@ -703,23 +703,23 @@ int msm_gfxcc_cobalt_probe(struct platform_device *pdev) } static const struct of_device_id msm_clock_gfxcc_match_table[] = { - { .compatible = "qcom,gfxcc-cobalt" }, - { .compatible = "qcom,gfxcc-cobalt-v2" }, + { .compatible = "qcom,gfxcc-8998" }, + { .compatible = "qcom,gfxcc-8998-v2" }, { .compatible = "qcom,gfxcc-hamster" }, {}, }; static struct platform_driver msm_clock_gfxcc_driver = { - .probe = msm_gfxcc_cobalt_probe, + .probe = msm_gfxcc_8998_probe, .driver = { - .name = "qcom,gfxcc-cobalt", + .name = "qcom,gfxcc-8998", .of_match_table = msm_clock_gfxcc_match_table, .owner = THIS_MODULE, }, }; -int __init msm_gpucc_cobalt_init(void) +int __init msm_gpucc_8998_init(void) { return platform_driver_register(&msm_clock_gpucc_driver); } -arch_initcall(msm_gpucc_cobalt_init); +arch_initcall(msm_gpucc_8998_init); diff --git a/drivers/clk/msm/clock-mmss-cobalt.c b/drivers/clk/msm/clock-mmss-8998.c index 9e2a8fcab2a6..2a112aad1fa3 100644 --- a/drivers/clk/msm/clock-mmss-cobalt.c +++ b/drivers/clk/msm/clock-mmss-8998.c @@ -26,10 +26,10 @@ #include <soc/qcom/clock-pll.h> #include <soc/qcom/clock-alpha-pll.h> -#include <dt-bindings/clock/msm-clocks-cobalt.h> -#include <dt-bindings/clock/msm-clocks-hwio-cobalt.h> +#include <dt-bindings/clock/msm-clocks-8998.h> +#include <dt-bindings/clock/msm-clocks-hwio-8998.h> -#include "vdd-level-cobalt.h" +#include "vdd-level-8998.h" #include "reset.h" static void __iomem *virt_base; @@ -2547,7 +2547,7 @@ static struct mux_clk mmss_debug_mux = { }, }; -static struct clk_lookup msm_clocks_mmss_cobalt[] = { +static struct clk_lookup msm_clocks_mmss_8998[] = { CLK_LIST(mmsscc_xo), CLK_LIST(mmsscc_gpll0), CLK_LIST(mmsscc_gpll0_div), @@ -2718,7 +2718,7 @@ static struct clk_lookup msm_clocks_mmss_cobalt[] = { CLK_LIST(mmss_debug_mux), }; -static const struct msm_reset_map mmss_cobalt_resets[] = { +static const struct msm_reset_map mmss_8998_resets[] = { [CAMSS_MICRO_BCR] = { 0x3490 }, }; @@ -2817,7 +2817,7 @@ static void msm_mmsscc_v2_fixup(void) csi3_clk_src.c.fmax[VDD_DIG_NOMINAL] = 480000000; } -int msm_mmsscc_cobalt_probe(struct platform_device *pdev) +int msm_mmsscc_8998_probe(struct platform_device *pdev) { struct resource *res; int rc; @@ -2909,43 +2909,43 @@ int msm_mmsscc_cobalt_probe(struct platform_device *pdev) msm_mmsscc_hamster_fixup(); is_v2 = of_device_is_compatible(pdev->dev.of_node, - "qcom,mmsscc-cobalt-v2"); + "qcom,mmsscc-8998-v2"); if (is_v2) { msm_mmsscc_hamster_fixup(); msm_mmsscc_v2_fixup(); } - rc = of_msm_clock_register(pdev->dev.of_node, msm_clocks_mmss_cobalt, - ARRAY_SIZE(msm_clocks_mmss_cobalt)); + rc = of_msm_clock_register(pdev->dev.of_node, msm_clocks_mmss_8998, + ARRAY_SIZE(msm_clocks_mmss_8998)); if (rc) return rc; /* Register block resets */ - msm_reset_controller_register(pdev, mmss_cobalt_resets, - ARRAY_SIZE(mmss_cobalt_resets), virt_base); + msm_reset_controller_register(pdev, mmss_8998_resets, + ARRAY_SIZE(mmss_8998_resets), virt_base); dev_info(&pdev->dev, "Registered MMSS clocks.\n"); return 0; } static struct of_device_id msm_clock_mmss_match_table[] = { - { .compatible = "qcom,mmsscc-cobalt" }, - { .compatible = "qcom,mmsscc-cobalt-v2" }, + { .compatible = "qcom,mmsscc-8998" }, + { .compatible = "qcom,mmsscc-8998-v2" }, { .compatible = "qcom,mmsscc-hamster" }, {}, }; static struct platform_driver msm_clock_mmss_driver = { - .probe = msm_mmsscc_cobalt_probe, + .probe = msm_mmsscc_8998_probe, .driver = { - .name = "qcom,mmsscc-cobalt", + .name = "qcom,mmsscc-8998", .of_match_table = msm_clock_mmss_match_table, .owner = THIS_MODULE, }, }; -int __init msm_mmsscc_cobalt_init(void) +int __init msm_mmsscc_8998_init(void) { return platform_driver_register(&msm_clock_mmss_driver); } -arch_initcall(msm_mmsscc_cobalt_init); +arch_initcall(msm_mmsscc_8998_init); diff --git a/drivers/clk/msm/clock-osm.c b/drivers/clk/msm/clock-osm.c index 3e45aee1c0f7..b9e977088126 100644 --- a/drivers/clk/msm/clock-osm.c +++ b/drivers/clk/msm/clock-osm.c @@ -40,8 +40,8 @@ #include <soc/qcom/clock-local2.h> #include <soc/qcom/clock-alpha-pll.h> -#include <dt-bindings/clock/msm-clocks-hwio-cobalt.h> -#include <dt-bindings/clock/msm-clocks-cobalt.h> +#include <dt-bindings/clock/msm-clocks-hwio-8998.h> +#include <dt-bindings/clock/msm-clocks-8998.h> #include "clock.h" @@ -79,7 +79,7 @@ enum clk_osm_trace_packet_id { #define MEM_ACC_SEQ_CONST(n) (n) #define MEM_ACC_INSTR_COMP(n) (0x67 + ((n) * 0x40)) #define MEM_ACC_SEQ_REG_VAL_START(n) (SEQ_REG(60 + (n))) -#define SEQ_REG1_MSMCOBALT_V2 0x1048 +#define SEQ_REG1_MSM8998_V2 0x1048 #define VERSION_REG 0x0 #define VERSION_1P1 0x00010100 @@ -224,10 +224,10 @@ enum clk_osm_trace_packet_id { #define PERFCL_EFUSE_SHIFT 29 #define PERFCL_EFUSE_MASK 0x7 -#define MSMCOBALTV1_PWRCL_BOOT_RATE 1478400000 -#define MSMCOBALTV1_PERFCL_BOOT_RATE 1536000000 -#define MSMCOBALTV2_PWRCL_BOOT_RATE 1555200000 -#define MSMCOBALTV2_PERFCL_BOOT_RATE 1728000000 +#define MSM8998V1_PWRCL_BOOT_RATE 1478400000 +#define MSM8998V1_PERFCL_BOOT_RATE 1536000000 +#define MSM8998V2_PWRCL_BOOT_RATE 1555200000 +#define MSM8998V2_PERFCL_BOOT_RATE 1728000000 /* ACD registers */ #define ACD_HW_VERSION 0x0 @@ -399,8 +399,8 @@ struct clk_osm { bool wdog_trace_en; }; -static bool msmcobalt_v1; -static bool msmcobalt_v2; +static bool msm8998_v1; +static bool msm8998_v2; static inline void clk_osm_masked_write_reg(struct clk_osm *c, u32 val, u32 offset, u32 mask) @@ -1908,7 +1908,7 @@ static void clk_osm_setup_osm_was(struct clk_osm *c) u32 cc_hyst; u32 val; - if (msmcobalt_v2) + if (msm8998_v2) return; val = clk_osm_read_reg(c, PDN_FSM_CTRL_REG); @@ -2191,14 +2191,14 @@ static void clk_osm_apm_vc_setup(struct clk_osm *c) /* Ensure writes complete before returning */ clk_osm_mb(c, OSM_BASE); } else { - if (msmcobalt_v1) { + if (msm8998_v1) { scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(1), c->apm_threshold_vc); scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(73), 0x3b | c->apm_threshold_vc << 6); - } else if (msmcobalt_v2) { + } else if (msm8998_v2) { clk_osm_write_reg(c, c->apm_threshold_vc, - SEQ_REG1_MSMCOBALT_V2); + SEQ_REG1_MSM8998_V2); } scm_io_write(c->pbases[OSM_BASE] + SEQ_REG(72), c->apm_crossover_vc); @@ -2992,11 +2992,11 @@ static int cpu_clock_osm_driver_probe(struct platform_device *pdev) }; if (of_find_compatible_node(NULL, NULL, - "qcom,cpu-clock-osm-msmcobalt-v1")) { - msmcobalt_v1 = true; + "qcom,cpu-clock-osm-msm8998-v1")) { + msm8998_v1 = true; } else if (of_find_compatible_node(NULL, NULL, - "qcom,cpu-clock-osm-msmcobalt-v2")) { - msmcobalt_v2 = true; + "qcom,cpu-clock-osm-msm8998-v2")) { + msm8998_v2 = true; } rc = clk_osm_resources_init(pdev); @@ -3014,8 +3014,8 @@ static int cpu_clock_osm_driver_probe(struct platform_device *pdev) } if ((pwrcl_clk.secure_init || perfcl_clk.secure_init) && - msmcobalt_v2) { - pr_err("unsupported configuration for msmcobalt v2\n"); + msm8998_v2) { + pr_err("unsupported configuration for msm8998 v2\n"); return -EINVAL; } @@ -3230,18 +3230,18 @@ static int cpu_clock_osm_driver_probe(struct platform_device *pdev) } /* Set final boot rate */ - rc = clk_set_rate(&pwrcl_clk.c, msmcobalt_v1 ? - MSMCOBALTV1_PWRCL_BOOT_RATE : - MSMCOBALTV2_PWRCL_BOOT_RATE); + rc = clk_set_rate(&pwrcl_clk.c, msm8998_v1 ? + MSM8998V1_PWRCL_BOOT_RATE : + MSM8998V2_PWRCL_BOOT_RATE); if (rc) { dev_err(&pdev->dev, "Unable to set boot rate on pwr cluster, rc=%d\n", rc); goto exit2; } - rc = clk_set_rate(&perfcl_clk.c, msmcobalt_v1 ? - MSMCOBALTV1_PERFCL_BOOT_RATE : - MSMCOBALTV2_PERFCL_BOOT_RATE); + rc = clk_set_rate(&perfcl_clk.c, msm8998_v1 ? + MSM8998V1_PERFCL_BOOT_RATE : + MSM8998V2_PERFCL_BOOT_RATE); if (rc) { dev_err(&pdev->dev, "Unable to set boot rate on perf cluster, rc=%d\n", rc); @@ -3273,8 +3273,8 @@ exit: } static struct of_device_id match_table[] = { - { .compatible = "qcom,cpu-clock-osm-msmcobalt-v1" }, - { .compatible = "qcom,cpu-clock-osm-msmcobalt-v2" }, + { .compatible = "qcom,cpu-clock-osm-msm8998-v1" }, + { .compatible = "qcom,cpu-clock-osm-msm8998-v2" }, {} }; diff --git a/drivers/clk/msm/mdss/Makefile b/drivers/clk/msm/mdss/Makefile index 89651e6ebc96..64c7609c15eb 100644 --- a/drivers/clk/msm/mdss/Makefile +++ b/drivers/clk/msm/mdss/Makefile @@ -2,8 +2,8 @@ obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll-util.o obj-$(CONFIG_MSM_MDSS_PLL) += mdss-pll.o obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996.o obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8996-util.o -obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-cobalt.o -obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dp-pll-cobalt.o -obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dp-pll-cobalt-util.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-8998.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dp-pll-8998.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dp-pll-8998-util.o obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8996.o -obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-cobalt.o +obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-8998.o diff --git a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c b/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c index 93bbcf5d40f5..af89610f8c65 100644 --- a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt-util.c +++ b/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c @@ -22,7 +22,7 @@ #include "mdss-pll.h" #include "mdss-dp-pll.h" -#include "mdss-dp-pll-cobalt.h" +#include "mdss-dp-pll-8998.h" int link2xclk_divsel_set_div(struct div_clk *clk, int div) { diff --git a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt.c b/drivers/clk/msm/mdss/mdss-dp-pll-8998.c index 598a2e8d25de..d5603179b24d 100644 --- a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt.c +++ b/drivers/clk/msm/mdss/mdss-dp-pll-8998.c @@ -59,11 +59,11 @@ v----------+----------v | divsel_two | | divsel_four | #include <linux/clk/msm-clk-provider.h> #include <linux/clk/msm-clk.h> #include <linux/clk/msm-clock-generic.h> -#include <dt-bindings/clock/msm-clocks-cobalt.h> +#include <dt-bindings/clock/msm-clocks-8998.h> #include "mdss-pll.h" #include "mdss-dp-pll.h" -#include "mdss-dp-pll-cobalt.h" +#include "mdss-dp-pll-8998.h" static struct clk_ops clk_ops_vco_divided_clk_src_c; static struct clk_ops clk_ops_link_2x_clk_div_c; @@ -79,7 +79,7 @@ static struct clk_div_ops vco_divided_clk_ops = { .get_div = vco_divided_clk_get_div, }; -static struct clk_ops dp_cobalt_vco_clk_ops = { +static struct clk_ops dp_8998_vco_clk_ops = { .set_rate = dp_vco_set_rate, .round_rate = dp_vco_round_rate, .prepare = dp_vco_prepare, @@ -97,7 +97,7 @@ static struct dp_pll_vco_clk dp_vco_clk = { .max_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000, .c = { .dbg_name = "dp_vco_clk", - .ops = &dp_cobalt_vco_clk_ops, + .ops = &dp_8998_vco_clk_ops, .flags = CLKFLAG_NO_RATE_CACHE, CLK_INIT(dp_vco_clk.c), }, @@ -167,7 +167,7 @@ static struct mux_clk vco_divided_clk_src_mux = { } }; -static struct clk_lookup dp_pllcc_cobalt[] = { +static struct clk_lookup dp_pllcc_8998[] = { CLK_LIST(dp_vco_clk), CLK_LIST(dp_link_2x_clk_divsel_five), CLK_LIST(vco_divsel_four_clk_src), @@ -175,7 +175,7 @@ static struct clk_lookup dp_pllcc_cobalt[] = { CLK_LIST(vco_divided_clk_src_mux), }; -int dp_pll_clock_register_cobalt(struct platform_device *pdev, +int dp_pll_clock_register_8998(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { int rc = -ENOTSUPP; @@ -209,10 +209,10 @@ int dp_pll_clock_register_cobalt(struct platform_device *pdev, clk_ops_gen_mux_dp.get_rate = parent_get_rate; /* We can select different clock ops for future versions */ - dp_vco_clk.c.ops = &dp_cobalt_vco_clk_ops; + dp_vco_clk.c.ops = &dp_8998_vco_clk_ops; - rc = of_msm_clock_register(pdev->dev.of_node, dp_pllcc_cobalt, - ARRAY_SIZE(dp_pllcc_cobalt)); + rc = of_msm_clock_register(pdev->dev.of_node, dp_pllcc_8998, + ARRAY_SIZE(dp_pllcc_8998)); if (rc) { DEV_ERR("%s: Clock register failed rc=%d\n", __func__, rc); rc = -EPROBE_DEFER; diff --git a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt.h b/drivers/clk/msm/mdss/mdss-dp-pll-8998.h index 28f21ed1fe0d..2dd78ec1944b 100644 --- a/drivers/clk/msm/mdss/mdss-dp-pll-cobalt.h +++ b/drivers/clk/msm/mdss/mdss-dp-pll-8998.h @@ -11,8 +11,8 @@ * */ -#ifndef __MDSS_DP_PLL_COBALT_H -#define __MDSS_DP_PLL_COBALT_H +#ifndef __MDSS_DP_PLL_8998_H +#define __MDSS_DP_PLL_8998_H #define DP_PHY_REVISION_ID0 0x0000 #define DP_PHY_REVISION_ID1 0x0004 @@ -177,4 +177,4 @@ int link2xclk_divsel_get_div(struct div_clk *clk); int vco_divided_clk_set_div(struct div_clk *clk, int div); int vco_divided_clk_get_div(struct div_clk *clk); -#endif /* __MDSS_DP_PLL_COBALT_H */ +#endif /* __MDSS_DP_PLL_8998_H */ diff --git a/drivers/clk/msm/mdss/mdss-dp-pll.h b/drivers/clk/msm/mdss/mdss-dp-pll.h index 3abc4c29c17e..f13c76ad6e32 100644 --- a/drivers/clk/msm/mdss/mdss-dp-pll.h +++ b/drivers/clk/msm/mdss/mdss-dp-pll.h @@ -28,7 +28,7 @@ static inline struct dp_pll_vco_clk *mdss_dp_to_vco_clk(struct clk *clk) return container_of(clk, struct dp_pll_vco_clk, c); } -int dp_pll_clock_register_cobalt(struct platform_device *pdev, +int dp_pll_clock_register_8998(struct platform_device *pdev, struct mdss_pll_resources *pll_res); diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c b/drivers/clk/msm/mdss/mdss-dsi-pll-8998.c index 299934c86d05..a7b4c795591b 100644 --- a/drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c +++ b/drivers/clk/msm/mdss/mdss-dsi-pll-8998.c @@ -20,7 +20,7 @@ #include <linux/clk/msm-clk-provider.h> #include <linux/clk/msm-clk.h> #include <linux/clk/msm-clock-generic.h> -#include <dt-bindings/clock/msm-clocks-cobalt.h> +#include <dt-bindings/clock/msm-clocks-8998.h> #include "mdss-pll.h" #include "mdss-dsi-pll.h" @@ -128,14 +128,14 @@ struct dsi_pll_config { u32 refclk_cycles; }; -struct dsi_pll_cobalt { +struct dsi_pll_8998 { struct mdss_pll_resources *rsc; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup; }; static struct mdss_pll_resources *pll_rsc_db[DSI_PLL_MAX]; -static struct dsi_pll_cobalt plls[DSI_PLL_MAX]; +static struct dsi_pll_8998 plls[DSI_PLL_MAX]; static void dsi_pll_config_slave(struct mdss_pll_resources *rsc) { @@ -166,7 +166,7 @@ static void dsi_pll_config_slave(struct mdss_pll_resources *rsc) pr_debug("Slave PLL %s\n", rsc->slave ? "configured" : "absent"); } -static void dsi_pll_setup_config(struct dsi_pll_cobalt *pll, +static void dsi_pll_setup_config(struct dsi_pll_8998 *pll, struct mdss_pll_resources *rsc) { struct dsi_pll_config *config = &pll->pll_configuration; @@ -198,7 +198,7 @@ static void dsi_pll_setup_config(struct dsi_pll_cobalt *pll, dsi_pll_config_slave(rsc); } -static void dsi_pll_calc_dec_frac(struct dsi_pll_cobalt *pll, +static void dsi_pll_calc_dec_frac(struct dsi_pll_8998 *pll, struct mdss_pll_resources *rsc) { struct dsi_pll_config *config = &pll->pll_configuration; @@ -278,7 +278,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_cobalt *pll, regs->frac_div_start_high = (frac & 0x30000) >> 16; } -static void dsi_pll_calc_ssc(struct dsi_pll_cobalt *pll, +static void dsi_pll_calc_ssc(struct dsi_pll_8998 *pll, struct mdss_pll_resources *rsc) { struct dsi_pll_config *config = &pll->pll_configuration; @@ -323,7 +323,7 @@ static void dsi_pll_calc_ssc(struct dsi_pll_cobalt *pll, ssc_per, (u32)ssc_step_size, config->ssc_adj_per); } -static void dsi_pll_ssc_commit(struct dsi_pll_cobalt *pll, +static void dsi_pll_ssc_commit(struct dsi_pll_8998 *pll, struct mdss_pll_resources *rsc) { void __iomem *pll_base = rsc->pll_base; @@ -349,7 +349,7 @@ static void dsi_pll_ssc_commit(struct dsi_pll_cobalt *pll, } } -static void dsi_pll_config_hzindep_reg(struct dsi_pll_cobalt *pll, +static void dsi_pll_config_hzindep_reg(struct dsi_pll_8998 *pll, struct mdss_pll_resources *rsc) { void __iomem *pll_base = rsc->pll_base; @@ -373,7 +373,7 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_cobalt *pll, MDSS_PLL_REG_W(pll_base, PLL_PLL_LOCK_OVERRIDE, 0x80); } -static void dsi_pll_commit(struct dsi_pll_cobalt *pll, +static void dsi_pll_commit(struct dsi_pll_8998 *pll, struct mdss_pll_resources *rsc) { void __iomem *pll_base = rsc->pll_base; @@ -394,12 +394,12 @@ static void dsi_pll_commit(struct dsi_pll_cobalt *pll, } -static int vco_cobalt_set_rate(struct clk *c, unsigned long rate) +static int vco_8998_set_rate(struct clk *c, unsigned long rate) { int rc; struct dsi_pll_vco_clk *vco = to_vco_clk(c); struct mdss_pll_resources *rsc = vco->priv; - struct dsi_pll_cobalt *pll; + struct dsi_pll_8998 *pll; if (!rsc) { pr_err("pll resource not found\n"); @@ -447,7 +447,7 @@ static int vco_cobalt_set_rate(struct clk *c, unsigned long rate) return 0; } -static int dsi_pll_cobalt_lock_status(struct mdss_pll_resources *pll) +static int dsi_pll_8998_lock_status(struct mdss_pll_resources *pll) { int rc; u32 status; @@ -519,7 +519,7 @@ static int dsi_pll_enable(struct dsi_pll_vco_clk *vco) wmb(); /* Check for PLL lock */ - rc = dsi_pll_cobalt_lock_status(rsc); + rc = dsi_pll_8998_lock_status(rsc); if (rc) { pr_err("PLL(%d) lock failed\n", rsc->index); goto error; @@ -570,7 +570,7 @@ static void dsi_pll_disable(struct dsi_pll_vco_clk *vco) rsc->pll_on = false; } -static void vco_cobalt_unprepare(struct clk *c) +static void vco_8998_unprepare(struct clk *c) { struct dsi_pll_vco_clk *vco = to_vco_clk(c); struct mdss_pll_resources *pll = vco->priv; @@ -585,7 +585,7 @@ static void vco_cobalt_unprepare(struct clk *c) mdss_pll_resource_enable(pll, false); } -static int vco_cobalt_prepare(struct clk *c) +static int vco_8998_prepare(struct clk *c) { int rc = 0; struct dsi_pll_vco_clk *vco = to_vco_clk(c); @@ -680,7 +680,7 @@ static unsigned long dsi_pll_get_vco_rate(struct clk *c) return (unsigned long)vco_rate; } -enum handoff vco_cobalt_handoff(struct clk *c) +enum handoff vco_8998_handoff(struct clk *c) { enum handoff ret = HANDOFF_DISABLED_CLK; int rc; @@ -800,7 +800,7 @@ static int bit_clk_set_div(struct div_clk *clk, int div) { int rc; struct mdss_pll_resources *rsc = clk->priv; - struct dsi_pll_cobalt *pll; + struct dsi_pll_8998 *pll; if (!rsc) { pr_err("pll resource not found\n"); @@ -971,7 +971,7 @@ static int post_bit_clk_set_div(struct div_clk *clk, int div) return rc; } -long vco_cobalt_round_rate(struct clk *c, unsigned long rate) +long vco_8998_round_rate(struct clk *c, unsigned long rate) { unsigned long rrate = rate; struct dsi_pll_vco_clk *vco = to_vco_clk(c); @@ -1011,12 +1011,12 @@ static struct clk_div_ops clk_bitclk_src_ops = { .get_div = bit_clk_get_div, }; -static struct clk_ops clk_ops_vco_cobalt = { - .set_rate = vco_cobalt_set_rate, - .round_rate = vco_cobalt_round_rate, - .handoff = vco_cobalt_handoff, - .prepare = vco_cobalt_prepare, - .unprepare = vco_cobalt_unprepare, +static struct clk_ops clk_ops_vco_8998 = { + .set_rate = vco_8998_set_rate, + .round_rate = vco_8998_round_rate, + .handoff = vco_8998_handoff, + .prepare = vco_8998_prepare, + .unprepare = vco_8998_unprepare, }; static struct clk_mux_ops mdss_mux_ops = { @@ -1079,7 +1079,7 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = { .max_rate = 3500000000UL, .c = { .dbg_name = "dsi0pll_vco_clk", - .ops = &clk_ops_vco_cobalt, + .ops = &clk_ops_vco_8998, .flags = CLKFLAG_NO_RATE_CACHE, CLK_INIT(dsi0pll_vco_clk.c), }, @@ -1248,7 +1248,7 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = { .max_rate = 3500000000UL, .c = { .dbg_name = "dsi1pll_vco_clk", - .ops = &clk_ops_vco_cobalt, + .ops = &clk_ops_vco_8998, .flags = CLKFLAG_NO_RATE_CACHE, CLK_INIT(dsi1pll_vco_clk.c), }, @@ -1411,7 +1411,7 @@ static struct mux_clk dsi1pll_byteclk_mux = { } }; -static struct clk_lookup mdss_dsi_pll0cc_cobalt[] = { +static struct clk_lookup mdss_dsi_pll0cc_8998[] = { CLK_LIST(dsi0pll_byteclk_mux), CLK_LIST(dsi0pll_byteclk_src), CLK_LIST(dsi0pll_pclk_mux), @@ -1424,7 +1424,7 @@ static struct clk_lookup mdss_dsi_pll0cc_cobalt[] = { CLK_LIST(dsi0pll_bitclk_src), CLK_LIST(dsi0pll_vco_clk), }; -static struct clk_lookup mdss_dsi_pll1cc_cobalt[] = { +static struct clk_lookup mdss_dsi_pll1cc_8998[] = { CLK_LIST(dsi1pll_byteclk_mux), CLK_LIST(dsi1pll_byteclk_src), CLK_LIST(dsi1pll_pclk_mux), @@ -1438,7 +1438,7 @@ static struct clk_lookup mdss_dsi_pll1cc_cobalt[] = { CLK_LIST(dsi1pll_vco_clk), }; -int dsi_pll_clock_register_cobalt(struct platform_device *pdev, +int dsi_pll_clock_register_8998(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { int rc = 0, ndx; @@ -1498,8 +1498,8 @@ int dsi_pll_clock_register_cobalt(struct platform_device *pdev, dsi0pll_vco_clk.priv = pll_res; rc = of_msm_clock_register(pdev->dev.of_node, - mdss_dsi_pll0cc_cobalt, - ARRAY_SIZE(mdss_dsi_pll0cc_cobalt)); + mdss_dsi_pll0cc_8998, + ARRAY_SIZE(mdss_dsi_pll0cc_8998)); } else { dsi1pll_byteclk_mux.priv = pll_res; dsi1pll_byteclk_src.priv = pll_res; @@ -1514,8 +1514,8 @@ int dsi_pll_clock_register_cobalt(struct platform_device *pdev, dsi1pll_vco_clk.priv = pll_res; rc = of_msm_clock_register(pdev->dev.of_node, - mdss_dsi_pll1cc_cobalt, - ARRAY_SIZE(mdss_dsi_pll1cc_cobalt)); + mdss_dsi_pll1cc_8998, + ARRAY_SIZE(mdss_dsi_pll1cc_8998)); } if (rc) pr_err("dsi%dpll clock register failed, rc=%d\n", ndx, rc); diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll.h b/drivers/clk/msm/mdss/mdss-dsi-pll.h index f88ae4d0eea1..286c99e339c6 100644 --- a/drivers/clk/msm/mdss/mdss-dsi-pll.h +++ b/drivers/clk/msm/mdss/mdss-dsi-pll.h @@ -58,7 +58,7 @@ int dsi_pll_clock_register_lpm(struct platform_device *pdev, struct mdss_pll_resources *pll_res); int dsi_pll_clock_register_8996(struct platform_device *pdev, struct mdss_pll_resources *pll_res); -int dsi_pll_clock_register_cobalt(struct platform_device *pdev, +int dsi_pll_clock_register_8998(struct platform_device *pdev, struct mdss_pll_resources *pll_res); int set_byte_mux_sel(struct mux_clk *clk, int sel); diff --git a/drivers/clk/msm/mdss/mdss-hdmi-pll-cobalt.c b/drivers/clk/msm/mdss/mdss-hdmi-pll-8998.c index c4f77e01b682..c74162ae8148 100644 --- a/drivers/clk/msm/mdss/mdss-hdmi-pll-cobalt.c +++ b/drivers/clk/msm/mdss/mdss-hdmi-pll-8998.c @@ -20,7 +20,7 @@ #include <linux/clk/msm-clk-provider.h> #include <linux/clk/msm-clk.h> #include <linux/clk/msm-clock-generic.h> -#include <dt-bindings/clock/msm-clocks-cobalt.h> +#include <dt-bindings/clock/msm-clocks-8998.h> #include "mdss-pll.h" #include "mdss-hdmi-pll.h" @@ -85,7 +85,7 @@ #define HDMI_VCO_MIN_RATE_HZ 25000000 #define HDMI_VCO_MAX_RATE_HZ 600000000 -struct cobalt_reg_cfg { +struct hdmi_8998_reg_cfg { u32 tx_band; u32 svs_mode_clk_sel; u32 hsclk_sel; @@ -135,7 +135,7 @@ struct cobalt_reg_cfg { bool debug; }; -static void hdmi_cobalt_get_div(struct cobalt_reg_cfg *cfg, unsigned long pclk) +static void hdmi_8998_get_div(struct hdmi_8998_reg_cfg *cfg, unsigned long pclk) { u32 const ratio_list[] = {1, 2, 3, 4, 5, 6, 9, 10, 12, 15, 25}; @@ -270,8 +270,8 @@ find_optimal_index: cfg->tx_band = found_tx_band_sel; } -static int hdmi_cobalt_config_phy(unsigned long rate, - struct cobalt_reg_cfg *cfg) +static int hdmi_8998_config_phy(unsigned long rate, + struct hdmi_8998_reg_cfg *cfg) { u64 const high_freq_bit_clk_threshold = 3400000000UL; u64 const dig_freq_bit_clk_threshold = 1500000000UL; @@ -300,7 +300,7 @@ static int hdmi_cobalt_config_phy(unsigned long rate, tmds_bclk_ratio = 0; } - hdmi_cobalt_get_div(cfg, rate); + hdmi_8998_get_div(cfg, rate); vco_freq_mhz = cfg->vco_freq * (u64) HDMI_HZ_TO_MHZ; fdata = cfg->vco_freq; @@ -451,15 +451,15 @@ static int hdmi_cobalt_config_phy(unsigned long rate, return rc; } -static int hdmi_cobalt_pll_set_clk_rate(struct clk *c, unsigned long rate) +static int hdmi_8998_pll_set_clk_rate(struct clk *c, unsigned long rate) { int rc = 0; struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); struct mdss_pll_resources *io = vco->priv; - struct cobalt_reg_cfg cfg = {0}; + struct hdmi_8998_reg_cfg cfg = {0}; void __iomem *phy = io->phy_base, *pll = io->pll_base; - rc = hdmi_cobalt_config_phy(rate, &cfg); + rc = hdmi_8998_config_phy(rate, &cfg); if (rc) { pr_err("rate calculation failed\n, rc=%d", rc); return rc; @@ -548,7 +548,7 @@ static int hdmi_cobalt_pll_set_clk_rate(struct clk *c, unsigned long rate) return 0; } -static int hdmi_cobalt_pll_lock_status(struct mdss_pll_resources *io) +static int hdmi_8998_pll_lock_status(struct mdss_pll_resources *io) { u32 const delay_us = 100; u32 const timeout_us = 5000; @@ -578,7 +578,7 @@ static int hdmi_cobalt_pll_lock_status(struct mdss_pll_resources *io) return rc; } -static int hdmi_cobalt_phy_ready_status(struct mdss_pll_resources *io) +static int hdmi_8998_phy_ready_status(struct mdss_pll_resources *io) { u32 const delay_us = 100; u32 const timeout_us = 5000; @@ -609,7 +609,7 @@ static int hdmi_cobalt_phy_ready_status(struct mdss_pll_resources *io) return rc; } -static int hdmi_cobalt_vco_set_rate(struct clk *c, unsigned long rate) +static int hdmi_8998_vco_set_rate(struct clk *c, unsigned long rate) { int rc = 0; struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); @@ -624,7 +624,7 @@ static int hdmi_cobalt_vco_set_rate(struct clk *c, unsigned long rate) if (io->pll_on) goto error; - rc = hdmi_cobalt_pll_set_clk_rate(c, rate); + rc = hdmi_8998_pll_set_clk_rate(c, rate); if (rc) { pr_err("failed to set clk rate, rc=%d\n", rc); goto error; @@ -639,7 +639,7 @@ error: return rc; } -static long hdmi_cobalt_vco_round_rate(struct clk *c, unsigned long rate) +static long hdmi_8998_vco_round_rate(struct clk *c, unsigned long rate) { unsigned long rrate = rate; struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); @@ -652,7 +652,7 @@ static long hdmi_cobalt_vco_round_rate(struct clk *c, unsigned long rate) return rrate; } -static int hdmi_cobalt_pll_enable(struct clk *c) +static int hdmi_8998_pll_enable(struct clk *c) { int rc = 0; struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); @@ -669,7 +669,7 @@ static int hdmi_cobalt_pll_enable(struct clk *c) /* Ensure all registers are flushed to hardware */ wmb(); - rc = hdmi_cobalt_pll_lock_status(io); + rc = hdmi_8998_pll_lock_status(io); if (rc) { pr_err("PLL not locked, rc=%d\n", rc); return rc; @@ -683,7 +683,7 @@ static int hdmi_cobalt_pll_enable(struct clk *c) /* Ensure all registers are flushed to hardware */ wmb(); - rc = hdmi_cobalt_phy_ready_status(io); + rc = hdmi_8998_phy_ready_status(io); if (rc) { pr_err("PHY NOT READY, rc=%d\n", rc); return rc; @@ -700,7 +700,7 @@ static int hdmi_cobalt_pll_enable(struct clk *c) return rc; } -static int hdmi_cobalt_vco_prepare(struct clk *c) +static int hdmi_8998_vco_prepare(struct clk *c) { struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); struct mdss_pll_resources *io = vco->priv; @@ -718,14 +718,14 @@ static int hdmi_cobalt_vco_prepare(struct clk *c) } if (!vco->rate_set && vco->rate) { - rc = hdmi_cobalt_pll_set_clk_rate(c, vco->rate); + rc = hdmi_8998_pll_set_clk_rate(c, vco->rate); if (rc) { pr_err("set rate failed, rc=%d\n", rc); goto error; } } - rc = hdmi_cobalt_pll_enable(c); + rc = hdmi_8998_pll_enable(c); if (rc) pr_err("pll enabled failed, rc=%d\n", rc); @@ -736,7 +736,7 @@ error: return rc; } -static void hdmi_cobalt_pll_disable(struct hdmi_pll_vco_clk *vco) +static void hdmi_8998_pll_disable(struct hdmi_pll_vco_clk *vco) { struct mdss_pll_resources *io = vco->priv; void __iomem *phy = io->phy_base; @@ -754,7 +754,7 @@ static void hdmi_cobalt_pll_disable(struct hdmi_pll_vco_clk *vco) io->pll_on = false; } -static void hdmi_cobalt_vco_unprepare(struct clk *c) +static void hdmi_8998_vco_unprepare(struct clk *c) { struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); struct mdss_pll_resources *io = vco->priv; @@ -764,11 +764,11 @@ static void hdmi_cobalt_vco_unprepare(struct clk *c) return; } - hdmi_cobalt_pll_disable(vco); + hdmi_8998_pll_disable(vco); mdss_pll_resource_enable(io, false); } -static enum handoff hdmi_cobalt_vco_handoff(struct clk *c) +static enum handoff hdmi_8998_vco_handoff(struct clk *c) { enum handoff ret = HANDOFF_DISABLED_CLK; struct hdmi_pll_vco_clk *vco = to_hdmi_vco_clk(c); @@ -796,29 +796,29 @@ static enum handoff hdmi_cobalt_vco_handoff(struct clk *c) return ret; } -static struct clk_ops hdmi_cobalt_vco_clk_ops = { - .set_rate = hdmi_cobalt_vco_set_rate, - .round_rate = hdmi_cobalt_vco_round_rate, - .prepare = hdmi_cobalt_vco_prepare, - .unprepare = hdmi_cobalt_vco_unprepare, - .handoff = hdmi_cobalt_vco_handoff, +static struct clk_ops hdmi_8998_vco_clk_ops = { + .set_rate = hdmi_8998_vco_set_rate, + .round_rate = hdmi_8998_vco_round_rate, + .prepare = hdmi_8998_vco_prepare, + .unprepare = hdmi_8998_vco_unprepare, + .handoff = hdmi_8998_vco_handoff, }; static struct hdmi_pll_vco_clk hdmi_vco_clk = { .min_rate = HDMI_VCO_MIN_RATE_HZ, .max_rate = HDMI_VCO_MAX_RATE_HZ, .c = { - .dbg_name = "hdmi_cobalt_vco_clk", - .ops = &hdmi_cobalt_vco_clk_ops, + .dbg_name = "hdmi_8998_vco_clk", + .ops = &hdmi_8998_vco_clk_ops, CLK_INIT(hdmi_vco_clk.c), }, }; -static struct clk_lookup hdmipllcc_cobalt[] = { +static struct clk_lookup hdmipllcc_8998[] = { CLK_LIST(hdmi_vco_clk), }; -int hdmi_cobalt_pll_clock_register(struct platform_device *pdev, +int hdmi_8998_pll_clock_register(struct platform_device *pdev, struct mdss_pll_resources *pll_res) { int rc = 0; @@ -830,8 +830,8 @@ int hdmi_cobalt_pll_clock_register(struct platform_device *pdev, hdmi_vco_clk.priv = pll_res; - rc = of_msm_clock_register(pdev->dev.of_node, hdmipllcc_cobalt, - ARRAY_SIZE(hdmipllcc_cobalt)); + rc = of_msm_clock_register(pdev->dev.of_node, hdmipllcc_8998, + ARRAY_SIZE(hdmipllcc_8998)); if (rc) { pr_err("clock register failed, rc=%d\n", rc); return rc; diff --git a/drivers/clk/msm/mdss/mdss-hdmi-pll.h b/drivers/clk/msm/mdss/mdss-hdmi-pll.h index d4226bf43e13..19f9b925644a 100644 --- a/drivers/clk/msm/mdss/mdss-hdmi-pll.h +++ b/drivers/clk/msm/mdss/mdss-hdmi-pll.h @@ -56,6 +56,6 @@ int hdmi_8996_v3_pll_clock_register(struct platform_device *pdev, int hdmi_8996_v3_1p8_pll_clock_register(struct platform_device *pdev, struct mdss_pll_resources *pll_res); -int hdmi_cobalt_pll_clock_register(struct platform_device *pdev, +int hdmi_8998_pll_clock_register(struct platform_device *pdev, struct mdss_pll_resources *pll_res); #endif diff --git a/drivers/clk/msm/mdss/mdss-pll.c b/drivers/clk/msm/mdss/mdss-pll.c index 4633c7d0e245..01ce2b1817f2 100644 --- a/drivers/clk/msm/mdss/mdss-pll.c +++ b/drivers/clk/msm/mdss/mdss-pll.c @@ -135,10 +135,10 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, pll_res->pll_interface_type = MDSS_DSI_PLL_8996; pll_res->target_id = MDSS_PLL_TARGET_8996; pll_res->revision = 2; - } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_cobalt")) { - pll_res->pll_interface_type = MDSS_DSI_PLL_COBALT; - } else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_cobalt")) { - pll_res->pll_interface_type = MDSS_DP_PLL_COBALT; + } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) { + pll_res->pll_interface_type = MDSS_DSI_PLL_8998; + } else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_8998")) { + pll_res->pll_interface_type = MDSS_DP_PLL_8998; } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996")) { pll_res->pll_interface_type = MDSS_HDMI_PLL_8996; } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996_v2")) { @@ -148,8 +148,8 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996_v3_1p8")) { pll_res->pll_interface_type = MDSS_HDMI_PLL_8996_V3_1_8; - } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_cobalt")) { - pll_res->pll_interface_type = MDSS_HDMI_PLL_COBALT; + } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8998")) { + pll_res->pll_interface_type = MDSS_HDMI_PLL_8998; } else { goto err; } @@ -176,10 +176,10 @@ static int mdss_pll_clock_register(struct platform_device *pdev, case MDSS_DSI_PLL_8996: rc = dsi_pll_clock_register_8996(pdev, pll_res); break; - case MDSS_DSI_PLL_COBALT: - rc = dsi_pll_clock_register_cobalt(pdev, pll_res); - case MDSS_DP_PLL_COBALT: - rc = dp_pll_clock_register_cobalt(pdev, pll_res); + case MDSS_DSI_PLL_8998: + rc = dsi_pll_clock_register_8998(pdev, pll_res); + case MDSS_DP_PLL_8998: + rc = dp_pll_clock_register_8998(pdev, pll_res); break; case MDSS_HDMI_PLL_8996: rc = hdmi_8996_v1_pll_clock_register(pdev, pll_res); @@ -193,8 +193,8 @@ static int mdss_pll_clock_register(struct platform_device *pdev, case MDSS_HDMI_PLL_8996_V3_1_8: rc = hdmi_8996_v3_1p8_pll_clock_register(pdev, pll_res); break; - case MDSS_HDMI_PLL_COBALT: - rc = hdmi_cobalt_pll_clock_register(pdev, pll_res); + case MDSS_HDMI_PLL_8998: + rc = hdmi_8998_pll_clock_register(pdev, pll_res); break; case MDSS_UNKNOWN_PLL: default: @@ -394,13 +394,13 @@ static int mdss_pll_remove(struct platform_device *pdev) static const struct of_device_id mdss_pll_dt_match[] = { {.compatible = "qcom,mdss_dsi_pll_8996"}, {.compatible = "qcom,mdss_dsi_pll_8996_v2"}, - {.compatible = "qcom,mdss_dsi_pll_cobalt"}, + {.compatible = "qcom,mdss_dsi_pll_8998"}, {.compatible = "qcom,mdss_hdmi_pll_8996"}, {.compatible = "qcom,mdss_hdmi_pll_8996_v2"}, {.compatible = "qcom,mdss_hdmi_pll_8996_v3"}, {.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"}, - {.compatible = "qcom,mdss_dp_pll_cobalt"}, - {.compatible = "qcom,mdss_hdmi_pll_cobalt"}, + {.compatible = "qcom,mdss_dp_pll_8998"}, + {.compatible = "qcom,mdss_hdmi_pll_8998"}, {} }; diff --git a/drivers/clk/msm/mdss/mdss-pll.h b/drivers/clk/msm/mdss/mdss-pll.h index a2eb03e09146..8fffaf30d4ec 100644 --- a/drivers/clk/msm/mdss/mdss-pll.h +++ b/drivers/clk/msm/mdss/mdss-pll.h @@ -31,13 +31,13 @@ enum { MDSS_DSI_PLL_8996, - MDSS_DSI_PLL_COBALT, - MDSS_DP_PLL_COBALT, + MDSS_DSI_PLL_8998, + MDSS_DP_PLL_8998, MDSS_HDMI_PLL_8996, MDSS_HDMI_PLL_8996_V2, MDSS_HDMI_PLL_8996_V3, MDSS_HDMI_PLL_8996_V3_1_8, - MDSS_HDMI_PLL_COBALT, + MDSS_HDMI_PLL_8998, MDSS_UNKNOWN_PLL, }; diff --git a/drivers/clk/msm/vdd-level-cobalt.h b/drivers/clk/msm/vdd-level-8998.h index c1897b7da7f7..c45e003ef7d7 100644 --- a/drivers/clk/msm/vdd-level-cobalt.h +++ b/drivers/clk/msm/vdd-level-8998.h @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ -#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_COBALT_H -#define __DRIVERS_CLK_QCOM_VDD_LEVEL_COBALT_H +#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_8998_H +#define __DRIVERS_CLK_QCOM_VDD_LEVEL_8998_H #include <linux/clk/msm-clock-generic.h> #include <linux/regulator/rpm-smd-regulator.h> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index e39686ca4feb..36ab5cf68740 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -173,6 +173,16 @@ config MSM_GPUCC_FALCON Say Y if you want to support graphics controller devices which will be required to enable those device. +config MSM_MMCC_FALCON + tristate "MSMFALCON Multimedia Clock Controller" + select MSM_GCC_FALCON + depends on COMMON_CLK_QCOM + help + Support for the multimedia clock controller on Qualcomm Technologies, Inc + MSMfalcon devices. + Say Y if you want to support multimedia devices such as display, + video encode/decode, camera, etc. + config QCOM_HFPLL tristate "High-Frequency PLL (HFPLL) Clock Controller" depends on COMMON_CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index adebefd63e71..595254f69db1 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o obj-$(CONFIG_MSM_GPUCC_FALCON) += gpucc-msmfalcon.o +obj-$(CONFIG_MSM_MMCC_FALCON) += mmcc-msmfalcon.o obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) += hfpll.o obj-$(CONFIG_KRAITCC) += krait-cc.o diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index bc982c9bfa71..78be74b1f8ea 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -613,13 +613,13 @@ DEFINE_CLK_SMD_RPM(msmfalcon, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2); DEFINE_CLK_SMD_RPM_QDSS(msmfalcon, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, rf_clk2, rf_clk2_ao, 5); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, rf_clk1, rf_clk1_ao, 4); DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, div_clk1, div_clk1_ao, 0xb); DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk1, ln_bb_clk1_ao, 0x1); DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk2, ln_bb_clk2_ao, 0x2); DEFINE_CLK_SMD_RPM_XO_BUFFER(msmfalcon, ln_bb_clk3, ln_bb_clk3_ao, 0x3); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, rf_clk2_pin, rf_clk2_a_pin, 5); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, rf_clk1_pin, rf_clk1_ao_pin, 4); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk1_pin, ln_bb_clk1_pin_ao, 0x1); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msmfalcon, ln_bb_clk2_pin, @@ -656,8 +656,10 @@ static struct clk_hw *msmfalcon_clks[] = { [RPM_BIMC_A_CLK] = &msmfalcon_bimc_a_clk.hw, [RPM_QDSS_CLK] = &msmfalcon_qdss_clk.hw, [RPM_QDSS_A_CLK] = &msmfalcon_qdss_a_clk.hw, - [RPM_RF_CLK2_PIN] = &msmfalcon_rf_clk2_pin.hw, - [RPM_RF_CLK2_A_PIN] = &msmfalcon_rf_clk2_a_pin.hw, + [RPM_RF_CLK1] = &msmfalcon_rf_clk1.hw, + [RPM_RF_CLK1_A] = &msmfalcon_rf_clk1_ao.hw, + [RPM_RF_CLK1_PIN] = &msmfalcon_rf_clk1_pin.hw, + [RPM_RF_CLK1_A_PIN] = &msmfalcon_rf_clk1_ao_pin.hw, [RPM_AGGR2_NOC_CLK] = &msmfalcon_aggre2_noc_clk.hw, [RPM_AGGR2_NOC_A_CLK] = &msmfalcon_aggre2_noc_a_clk.hw, [RPM_CNOC_CLK] = &msmfalcon_cnoc_clk.hw, diff --git a/drivers/clk/qcom/mdss/mdss-dsi-pll.h b/drivers/clk/qcom/mdss/mdss-dsi-pll.h index f88ae4d0eea1..286c99e339c6 100644 --- a/drivers/clk/qcom/mdss/mdss-dsi-pll.h +++ b/drivers/clk/qcom/mdss/mdss-dsi-pll.h @@ -58,7 +58,7 @@ int dsi_pll_clock_register_lpm(struct platform_device *pdev, struct mdss_pll_resources *pll_res); int dsi_pll_clock_register_8996(struct platform_device *pdev, struct mdss_pll_resources *pll_res); -int dsi_pll_clock_register_cobalt(struct platform_device *pdev, +int dsi_pll_clock_register_8998(struct platform_device *pdev, struct mdss_pll_resources *pll_res); int set_byte_mux_sel(struct mux_clk *clk, int sel); diff --git a/drivers/clk/qcom/mdss/mdss-hdmi-pll.h b/drivers/clk/qcom/mdss/mdss-hdmi-pll.h index d4226bf43e13..19f9b925644a 100644 --- a/drivers/clk/qcom/mdss/mdss-hdmi-pll.h +++ b/drivers/clk/qcom/mdss/mdss-hdmi-pll.h @@ -56,6 +56,6 @@ int hdmi_8996_v3_pll_clock_register(struct platform_device *pdev, int hdmi_8996_v3_1p8_pll_clock_register(struct platform_device *pdev, struct mdss_pll_resources *pll_res); -int hdmi_cobalt_pll_clock_register(struct platform_device *pdev, +int hdmi_8998_pll_clock_register(struct platform_device *pdev, struct mdss_pll_resources *pll_res); #endif diff --git a/drivers/clk/qcom/mdss/mdss-pll.c b/drivers/clk/qcom/mdss/mdss-pll.c index e91e9c9dc768..8264d2e5a3cd 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.c +++ b/drivers/clk/qcom/mdss/mdss-pll.c @@ -136,10 +136,10 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, pll_res->pll_interface_type = MDSS_DSI_PLL_8996; pll_res->target_id = MDSS_PLL_TARGET_8996; pll_res->revision = 2; - } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_cobalt")) { - pll_res->pll_interface_type = MDSS_DSI_PLL_COBALT; - } else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_cobalt")) { - pll_res->pll_interface_type = MDSS_DP_PLL_COBALT; + } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) { + pll_res->pll_interface_type = MDSS_DSI_PLL_8998; + } else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_8998")) { + pll_res->pll_interface_type = MDSS_DP_PLL_8998; } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996")) { pll_res->pll_interface_type = MDSS_HDMI_PLL_8996; } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996_v2")) { @@ -149,8 +149,8 @@ static int mdss_pll_resource_parse(struct platform_device *pdev, } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8996_v3_1p8")) { pll_res->pll_interface_type = MDSS_HDMI_PLL_8996_V3_1_8; - } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_cobalt")) { - pll_res->pll_interface_type = MDSS_HDMI_PLL_COBALT; + } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8998")) { + pll_res->pll_interface_type = MDSS_HDMI_PLL_8998; } else { goto err; } @@ -177,10 +177,10 @@ static int mdss_pll_clock_register(struct platform_device *pdev, case MDSS_DSI_PLL_8996: rc = dsi_pll_clock_register_8996(pdev, pll_res); break; - case MDSS_DSI_PLL_COBALT: - rc = dsi_pll_clock_register_cobalt(pdev, pll_res); - case MDSS_DP_PLL_COBALT: - rc = dp_pll_clock_register_cobalt(pdev, pll_res); + case MDSS_DSI_PLL_8998: + rc = dsi_pll_clock_register_8998(pdev, pll_res); + case MDSS_DP_PLL_8998: + rc = dp_pll_clock_register_8998(pdev, pll_res); break; case MDSS_HDMI_PLL_8996: rc = hdmi_8996_v1_pll_clock_register(pdev, pll_res); @@ -194,8 +194,8 @@ static int mdss_pll_clock_register(struct platform_device *pdev, case MDSS_HDMI_PLL_8996_V3_1_8: rc = hdmi_8996_v3_1p8_pll_clock_register(pdev, pll_res); break; - case MDSS_HDMI_PLL_COBALT: - rc = hdmi_cobalt_pll_clock_register(pdev, pll_res); + case MDSS_HDMI_PLL_8998: + rc = hdmi_8998_pll_clock_register(pdev, pll_res); break; case MDSS_UNKNOWN_PLL: default: @@ -394,13 +394,13 @@ static int mdss_pll_remove(struct platform_device *pdev) static const struct of_device_id mdss_pll_dt_match[] = { {.compatible = "qcom,mdss_dsi_pll_8996"}, {.compatible = "qcom,mdss_dsi_pll_8996_v2"}, - {.compatible = "qcom,mdss_dsi_pll_cobalt"}, + {.compatible = "qcom,mdss_dsi_pll_8998"}, {.compatible = "qcom,mdss_hdmi_pll_8996"}, {.compatible = "qcom,mdss_hdmi_pll_8996_v2"}, {.compatible = "qcom,mdss_hdmi_pll_8996_v3"}, {.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"}, - {.compatible = "qcom,mdss_dp_pll_cobalt"}, - {.compatible = "qcom,mdss_hdmi_pll_cobalt"}, + {.compatible = "qcom,mdss_dp_pll_8998"}, + {.compatible = "qcom,mdss_hdmi_pll_8998"}, {} }; diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h index a2eb03e09146..8fffaf30d4ec 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.h +++ b/drivers/clk/qcom/mdss/mdss-pll.h @@ -31,13 +31,13 @@ enum { MDSS_DSI_PLL_8996, - MDSS_DSI_PLL_COBALT, - MDSS_DP_PLL_COBALT, + MDSS_DSI_PLL_8998, + MDSS_DP_PLL_8998, MDSS_HDMI_PLL_8996, MDSS_HDMI_PLL_8996_V2, MDSS_HDMI_PLL_8996_V3, MDSS_HDMI_PLL_8996_V3_1_8, - MDSS_HDMI_PLL_COBALT, + MDSS_HDMI_PLL_8998, MDSS_UNKNOWN_PLL, }; diff --git a/drivers/clk/qcom/mmcc-msmfalcon.c b/drivers/clk/qcom/mmcc-msmfalcon.c new file mode 100644 index 000000000000..e4a84765430a --- /dev/null +++ b/drivers/clk/qcom/mmcc-msmfalcon.c @@ -0,0 +1,3036 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/kernel.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/clk-provider.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> +#include <dt-bindings/clock/qcom,mmcc-msmfalcon.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "common.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "reset.h" +#include "vdd-level-falcon.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } +#define F_SLEW(f, s, h, m, n, src_freq) { (f), (s), (2 * (h) - 1), (m), (n), \ + (src_freq) } + +enum vdd_a_levels { + VDDA_NONE, + VDDA_LOWER, /* SVS2 */ + VDDA_NUM, +}; + +static int vdda_levels[] = { + 0, + 1800000, +}; + +#define VDDA_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdda, \ + .rate_max = (unsigned long[VDDA_NUM]) { \ + [VDDA_##l1] = (f1), \ + }, \ + .num_rate_max = VDDA_NUM + +static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdd_mx, VDD_DIG_NUM, 1, vdd_corner); +static DEFINE_VDD_REGULATORS(vdda, VDDA_NUM, 1, vdda_levels); + +enum { + P_CORE_BI_PLL_TEST_SE, + P_CORE_PI_SLEEP_CLK, + P_CXO, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV, + P_DSI0_PHY_PLL_OUT_BYTECLK, + P_DSI0_PHY_PLL_OUT_DSICLK, + P_DSI1_PHY_PLL_OUT_BYTECLK, + P_DSI1_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_MMPLL0_PLL_OUT_MAIN, + P_MMPLL10_PLL_OUT_MAIN, + P_MMPLL3_PLL_OUT_MAIN, + P_MMPLL4_PLL_OUT_MAIN, + P_MMPLL5_PLL_OUT_MAIN, + P_MMPLL6_PLL_OUT_MAIN, + P_MMPLL7_PLL_OUT_MAIN, + P_MMPLL8_PLL_OUT_MAIN, +}; + +static const struct parent_map mmcc_parent_map_0[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL8_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_0[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll8_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_1[] = { + { P_CXO, 0 }, + { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, + { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_1[] = { + "xo", + "dsi0_phy_pll_out_byteclk", + "dsi1_phy_pll_out_byteclk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_2[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL10_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_2[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_3[] = { + { P_CXO, 0 }, + { P_MMPLL4_PLL_OUT_MAIN, 1 }, + { P_MMPLL7_PLL_OUT_MAIN, 2 }, + { P_MMPLL10_PLL_OUT_MAIN, 3 }, + { P_CORE_PI_SLEEP_CLK, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_3[] = { + "xo", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "core_pi_sleep_clk", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_4[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL7_PLL_OUT_MAIN, 2 }, + { P_MMPLL10_PLL_OUT_MAIN, 3 }, + { P_CORE_PI_SLEEP_CLK, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_4[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "core_pi_sleep_clk", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_5[] = { + { P_CXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_5[] = { + "xo", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_6[] = { + { P_CXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_6[] = { + "xo", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_7[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL5_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_7[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll5_pll_out_main", + "mmpll7_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_8[] = { + { P_CXO, 0 }, + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, + { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_8[] = { + "xo", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_dsiclk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_9[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL10_PLL_OUT_MAIN, 4 }, + { P_MMPLL6_PLL_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_9[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "mmpll6_pll_out_main", + "gcc_mmss_gpll0_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_10[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_10[] = { + "xo", + "mmpll0_pll_out_main", + "gcc_mmss_gpll0_clk", + "gcc_mmss_gpll0_div_clk", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_11[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL4_PLL_OUT_MAIN, 2 }, + { P_MMPLL7_PLL_OUT_MAIN, 3 }, + { P_MMPLL10_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_MMPLL6_PLL_OUT_MAIN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_11[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll4_pll_out_main", + "mmpll7_pll_out_main", + "mmpll10_pll_out_main", + "gcc_mmss_gpll0_clk", + "mmpll6_pll_out_main", + "core_bi_pll_test_se", +}; + +static const struct parent_map mmcc_parent_map_12[] = { + { P_CXO, 0 }, + { P_MMPLL0_PLL_OUT_MAIN, 1 }, + { P_MMPLL8_PLL_OUT_MAIN, 2 }, + { P_MMPLL3_PLL_OUT_MAIN, 3 }, + { P_MMPLL6_PLL_OUT_MAIN, 4 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_MMPLL7_PLL_OUT_MAIN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const mmcc_parent_names_12[] = { + "xo", + "mmpll0_pll_out_main", + "mmpll8_pll_out_main", + "mmpll3_pll_out_main", + "mmpll6_pll_out_main", + "gcc_mmss_gpll0_clk", + "mmpll7_pll_out_main", + "core_bi_pll_test_se", +}; + +/* Voteable PLL */ +static struct clk_alpha_pll mmpll0_pll_out_main = { + .offset = 0xc000, + .clkr = { + .enable_reg = 0x1f0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmpll0_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 404000000, + LOW, 808000000), + }, + }, +}; + +static struct clk_alpha_pll mmpll6_pll_out_main = { + .offset = 0xf0, + .clkr = { + .enable_reg = 0x1f0, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "mmpll6_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 540000000, + LOW_L1, 1080000000), + }, + }, +}; + +/* APSS controlled PLLs */ +static struct pll_vco vco[] = { + { 1000000000, 2000000000, 0 }, + { 750000000, 1500000000, 1 }, + { 500000000, 1000000000, 2 }, + { 250000000, 500000000, 3 }, +}; + +static const struct pll_config mmpll10_config = { + .l = 0x1e, + .config_ctl_val = 0x00004289, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll10_pll_out_main = { + .offset = 0x190, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll10_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDDA_FMAX_MAP1(LOWER, 576000000), + }, + }, +}; + +static struct pll_vco mmpll3_vco[] = { + { 750000000, 1500000000, 1 }, +}; + +static const struct pll_config mmpll3_config = { + .l = 0x2e, + .config_ctl_val = 0x4001055b, + .vco_val = 0x1 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll3_pll_out_main = { + .offset = 0x0, + .vco_table = mmpll3_vco, + .num_vco = ARRAY_SIZE(mmpll3_vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll3_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_slew_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 441600000, + NOMINAL, 1036800000), + }, + }, +}; + +static const struct pll_config mmpll4_config = { + .l = 0x28, + .config_ctl_val = 0x4001055b, + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll4_pll_out_main = { + .offset = 0x50, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll4_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 384000000, + LOW, 768000000), + }, + }, +}; + +static const struct pll_config mmpll5_config = { + .l = 0x2a, + .config_ctl_val = 0x4001055b, + .alpha_u = 0xf8, + .alpha_en_mask = BIT(24), + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll5_pll_out_main = { + .offset = 0xa0, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll5_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 421500000, + LOW, 825000000), + }, + }, +}; + +static const struct pll_config mmpll7_config = { + .l = 0x32, + .config_ctl_val = 0x4001055b, + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll7_pll_out_main = { + .offset = 0x140, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll7_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 480000000, + LOW, 960000000), + }, + }, +}; + +static const struct pll_config mmpll8_config = { + .l = 0x30, + .alpha_u = 0x70, + .alpha_en_mask = BIT(24), + .config_ctl_val = 0x4001055b, + .vco_val = 0x2 << 20, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, +}; + +static struct clk_alpha_pll mmpll8_pll_out_main = { + .offset = 0x1c0, + .vco_table = vco, + .num_vco = ARRAY_SIZE(vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmpll8_pll_out_main", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + VDD_MMSS_PLL_DIG_FMAX_MAP2(LOWER, 465000000, + LOW, 930000000), + }, + }, +}; + +static const struct freq_tbl ftbl_ahb_clk_src[] = { + F(19200000, P_CXO, 1, 0, 0), + F(40000000, P_GPLL0_OUT_MAIN_DIV, 7.5, 0, 0), + F(80800000, P_MMPLL0_PLL_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 ahb_clk_src = { + .cmd_rcgr = 0x5000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_10, + .freq_tbl = ftbl_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ahb_clk_src", + .parent_names = mmcc_parent_names_10, + .num_parents = 5, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 19200000, + LOW, 40000000, + NOMINAL, 80800000), + }, +}; + +static struct clk_rcg2 byte0_clk_src = { + .cmd_rcgr = 0x2120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "byte0_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_byte2_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 131250000, + LOW, 210000000, + NOMINAL, 262500000), + }, +}; + +static struct clk_rcg2 byte1_clk_src = { + .cmd_rcgr = 0x2140, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "byte1_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_byte2_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 131250000, + LOW, 210000000, + NOMINAL, 262500000), + }, +}; + +static const struct freq_tbl ftbl_camss_gp0_clk_src[] = { + F(10000, P_CXO, 16, 1, 120), + F(24000, P_CXO, 16, 1, 50), + F(6000000, P_GPLL0_OUT_MAIN_DIV, 10, 1, 5), + F(12000000, P_GPLL0_OUT_MAIN_DIV, 10, 2, 5), + F(13043478, P_GPLL0_OUT_MAIN_DIV, 1, 1, 23), + F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25), + F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 camss_gp0_clk_src = { + .cmd_rcgr = 0x3420, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_4, + .freq_tbl = ftbl_camss_gp0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "camss_gp0_clk_src", + .parent_names = mmcc_parent_names_4, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static struct clk_rcg2 camss_gp1_clk_src = { + .cmd_rcgr = 0x3450, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_4, + .freq_tbl = ftbl_camss_gp0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "camss_gp1_clk_src", + .parent_names = mmcc_parent_names_4, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 50000000, + LOW, 100000000, + NOMINAL, 200000000), + }, +}; + +static const struct freq_tbl ftbl_cci_clk_src[] = { + F(37500000, P_GPLL0_OUT_MAIN_DIV, 8, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + { } +}; + +static struct clk_rcg2 cci_clk_src = { + .cmd_rcgr = 0x3300, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_4, + .freq_tbl = ftbl_cci_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cci_clk_src", + .parent_names = mmcc_parent_names_4, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 37500000, + LOW, 50000000, + NOMINAL, 100000000), + }, +}; + +static const struct freq_tbl ftbl_cpp_clk_src[] = { + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + F(256000000, P_MMPLL4_PLL_OUT_MAIN, 3, 0, 0), + F(384000000, P_MMPLL4_PLL_OUT_MAIN, 2, 0, 0), + F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), + F(540000000, P_MMPLL6_PLL_OUT_MAIN, 2, 0, 0), + F(576000000, P_MMPLL10_PLL_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cpp_clk_src = { + .cmd_rcgr = 0x3640, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_11, + .freq_tbl = ftbl_cpp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cpp_clk_src", + .parent_names = mmcc_parent_names_11, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 120000000, + LOW, 256000000, + LOW_L1, 384000000, + NOMINAL, 480000000, + NOMINAL_L1, 540000000, + HIGH, 576000000), + }, +}; + +static const struct freq_tbl ftbl_csi0_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(310000000, P_MMPLL8_PLL_OUT_MAIN, 3, 0, 0), + F(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0), + F(465000000, P_MMPLL8_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 csi0_clk_src = { + .cmd_rcgr = 0x3090, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi0_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 csi0phytimer_clk_src = { + .cmd_rcgr = 0x3000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi0phytimer_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333), + }, +}; + +static struct clk_rcg2 csi1_clk_src = { + .cmd_rcgr = 0x3100, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi1_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static struct clk_rcg2 csi1phytimer_clk_src = { + .cmd_rcgr = 0x3030, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi1phytimer_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333), + }, +}; + +static struct clk_rcg2 csi2_clk_src = { + .cmd_rcgr = 0x3160, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi2_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static struct clk_rcg2 csi2phytimer_clk_src = { + .cmd_rcgr = 0x3060, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_csi0phytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi2phytimer_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333), + }, +}; + +static struct clk_rcg2 csi3_clk_src = { + .cmd_rcgr = 0x31c0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csi0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi3_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 310000000, + NOMINAL, 404000000, + NOMINAL_L1, 465000000), + }, +}; + +static const struct freq_tbl ftbl_csiphy_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0), + F(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 csiphy_clk_src = { + .cmd_rcgr = 0x3800, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_0, + .freq_tbl = ftbl_csiphy_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csiphy_clk_src", + .parent_names = mmcc_parent_names_0, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4( + LOWER, 100000000, + LOW, 200000000, + LOW_L1, 269333333, + NOMINAL, 320000000), + }, +}; + +static const struct freq_tbl ftbl_dp_aux_clk_src[] = { + F(19200000, P_CXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 dp_aux_clk_src = { + .cmd_rcgr = 0x2260, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_5, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_aux_clk_src", + .parent_names = mmcc_parent_names_5, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static const struct freq_tbl ftbl_dp_crypto_clk_src[] = { + F(101250000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), + F(168750000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), + F(337500000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0), + { } +}; + +static struct clk_rcg2 dp_crypto_clk_src = { + .cmd_rcgr = 0x2220, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_6, + .freq_tbl = ftbl_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_crypto_clk_src", + .parent_names = mmcc_parent_names_6, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 101250000, + LOW, 168750000, + NOMINAL, 337500000), + }, +}; + +static const struct freq_tbl ftbl_dp_gtc_clk_src[] = { + F(40000000, P_GPLL0_OUT_MAIN_DIV, 7.5, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN_DIV, 1, 0, 0), + { } +}; + +static struct clk_rcg2 dp_gtc_clk_src = { + .cmd_rcgr = 0x2280, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_5, + .freq_tbl = ftbl_dp_gtc_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_gtc_clk_src", + .parent_names = mmcc_parent_names_5, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 40000000, + LOW, 300000000), + }, +}; + +static const struct freq_tbl ftbl_dp_link_clk_src[] = { + F(162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), + F(270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), + F(540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dp_link_clk_src = { + .cmd_rcgr = 0x2200, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_6, + .freq_tbl = ftbl_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_link_clk_src", + .parent_names = mmcc_parent_names_6, + .num_parents = 4, + .ops = &clk_rcg2_ops, + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, + VDD_DIG_FMAX_MAP3( + LOWER, 162000000, + LOW, 270000000, + NOMINAL, 540000000), + }, +}; + +static struct clk_rcg2 dp_pixel_clk_src = { + .cmd_rcgr = 0x2240, + .mnd_width = 16, + .hid_width = 5, + .parent_map = mmcc_parent_map_6, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_pixel_clk_src", + .parent_names = mmcc_parent_names_6, + .num_parents = 4, + .ops = &clk_dp_ops, + VDD_DIG_FMAX_MAP3( + LOWER, 148380000, + LOW, 296740000, + NOMINAL, 593470000), + }, +}; + +static struct clk_rcg2 esc0_clk_src = { + .cmd_rcgr = 0x2160, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "esc0_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static struct clk_rcg2 esc1_clk_src = { + .cmd_rcgr = 0x2180, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_1, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "esc1_clk_src", + .parent_names = mmcc_parent_names_1, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static const struct freq_tbl ftbl_jpeg0_clk_src[] = { + F(66666667, P_GPLL0_OUT_MAIN_DIV, 4.5, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + F(219428571, P_MMPLL4_PLL_OUT_MAIN, 3.5, 0, 0), + F(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0), + F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 jpeg0_clk_src = { + .cmd_rcgr = 0x3500, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_2, + .freq_tbl = ftbl_jpeg0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "jpeg0_clk_src", + .parent_names = mmcc_parent_names_2, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP5( + LOWER, 66666667, + LOW, 133333333, + LOW_L1, 219428571, + NOMINAL, 320000000, + NOMINAL_L1, 480000000), + }, +}; + +static const struct freq_tbl ftbl_mclk0_clk_src[] = { + F(4800000, P_CXO, 4, 0, 0), + F(6000000, P_GPLL0_OUT_MAIN_DIV, 10, 1, 5), + F(8000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 75), + F(9600000, P_CXO, 2, 0, 0), + F(16666667, P_GPLL0_OUT_MAIN_DIV, 2, 1, 9), + F(19200000, P_CXO, 1, 0, 0), + F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25), + F(33333333, P_GPLL0_OUT_MAIN_DIV, 1, 1, 9), + F(48000000, P_GPLL0_OUT_MAIN, 1, 2, 25), + F(66666667, P_GPLL0_OUT_MAIN, 1, 1, 9), + { } +}; + +static struct clk_rcg2 mclk0_clk_src = { + .cmd_rcgr = 0x3360, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk0_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static struct clk_rcg2 mclk1_clk_src = { + .cmd_rcgr = 0x3390, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk1_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static struct clk_rcg2 mclk2_clk_src = { + .cmd_rcgr = 0x33c0, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk2_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static struct clk_rcg2 mclk3_clk_src = { + .cmd_rcgr = 0x33f0, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_3, + .freq_tbl = ftbl_mclk0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk3_clk_src", + .parent_names = mmcc_parent_names_3, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP2( + LOWER, 33333333, + LOW, 66666667), + }, +}; + +static const struct freq_tbl ftbl_mdp_clk_src[] = { + F(100000000, P_GPLL0_OUT_MAIN_DIV, 3, 0, 0), + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), + F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(275000000, P_MMPLL5_PLL_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(330000000, P_MMPLL5_PLL_OUT_MAIN, 2.5, 0, 0), + F(412500000, P_MMPLL5_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 mdp_clk_src = { + .cmd_rcgr = 0x2040, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_7, + .freq_tbl = ftbl_mdp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mdp_clk_src", + .parent_names = mmcc_parent_names_7, + .num_parents = 7, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4( + LOWER, 171428571, + LOW, 275000000, + NOMINAL, 330000000, + HIGH, 412500000), + }, +}; + +static struct clk_rcg2 pclk0_clk_src = { + .cmd_rcgr = 0x2000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_8, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pclk0_clk_src", + .parent_names = mmcc_parent_names_8, + .num_parents = 4, + .ops = &clk_pixel_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 175000000, + LOW, 280000000, + NOMINAL, 350000000), + }, +}; + +static struct clk_rcg2 pclk1_clk_src = { + .cmd_rcgr = 0x2020, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmcc_parent_map_8, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pclk1_clk_src", + .parent_names = mmcc_parent_names_8, + .num_parents = 4, + .ops = &clk_pixel_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + VDD_DIG_FMAX_MAP3( + LOWER, 175000000, + LOW, 280000000, + NOMINAL, 350000000), + }, +}; + +static const struct freq_tbl ftbl_rot_clk_src[] = { + F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0), + F(275000000, P_MMPLL5_PLL_OUT_MAIN, 3, 0, 0), + F(330000000, P_MMPLL5_PLL_OUT_MAIN, 2.5, 0, 0), + F(412500000, P_MMPLL5_PLL_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 rot_clk_src = { + .cmd_rcgr = 0x21a0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_7, + .freq_tbl = ftbl_rot_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rot_clk_src", + .parent_names = mmcc_parent_names_7, + .num_parents = 7, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP4( + LOWER, 171428571, + LOW, 275000000, + NOMINAL, 330000000, + HIGH, 412500000), + }, +}; + +static const struct freq_tbl ftbl_vfe0_clk_src[] = { + F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + F(256000000, P_MMPLL4_PLL_OUT_MAIN, 3, 0, 0), + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), + F(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0), + F(480000000, P_MMPLL7_PLL_OUT_MAIN, 2, 0, 0), + F(540000000, P_MMPLL6_PLL_OUT_MAIN, 2, 0, 0), + F(576000000, P_MMPLL10_PLL_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 vfe0_clk_src = { + .cmd_rcgr = 0x3600, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_9, + .freq_tbl = ftbl_vfe0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vfe0_clk_src", + .parent_names = mmcc_parent_names_9, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 120000000, + LOW, 256000000, + LOW_L1, 404000000, + NOMINAL, 480000000, + NOMINAL_L1, 540000000, + HIGH, 576000000), + }, +}; + +static struct clk_rcg2 vfe1_clk_src = { + .cmd_rcgr = 0x3620, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_9, + .freq_tbl = ftbl_vfe0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vfe1_clk_src", + .parent_names = mmcc_parent_names_9, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 120000000, + LOW, 256000000, + LOW_L1, 404000000, + NOMINAL, 480000000, + NOMINAL_L1, 540000000, + HIGH, 576000000), + }, +}; + +static const struct freq_tbl ftbl_video_core_clk_src[] = { + F_SLEW(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0, FIXED_FREQ_SRC), + F_SLEW(269333333, P_MMPLL0_PLL_OUT_MAIN, 3, 0, 0, FIXED_FREQ_SRC), + F_SLEW(320000000, P_MMPLL7_PLL_OUT_MAIN, 3, 0, 0, FIXED_FREQ_SRC), + F_SLEW(404000000, P_MMPLL0_PLL_OUT_MAIN, 2, 0, 0, FIXED_FREQ_SRC), + F_SLEW(441600000, P_MMPLL3_PLL_OUT_MAIN, 2, 0, 0, 883200000), + F_SLEW(518400000, P_MMPLL3_PLL_OUT_MAIN, 2, 0, 0, 1036800000), + { } +}; + +static struct clk_rcg2 video_core_clk_src = { + .cmd_rcgr = 0x1000, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_12, + .freq_tbl = ftbl_video_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "video_core_clk_src", + .parent_names = mmcc_parent_names_12, + .num_parents = 8, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP6( + LOWER, 133333333, + LOW, 269333333, + LOW_L1, 320000000, + NOMINAL, 404000000, + NOMINAL_L1, 441600000, + HIGH, 518400000), + }, +}; + +static struct clk_rcg2 vsync_clk_src = { + .cmd_rcgr = 0x2080, + .mnd_width = 0, + .hid_width = 5, + .parent_map = mmcc_parent_map_5, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vsync_clk_src", + .parent_names = mmcc_parent_names_5, + .num_parents = 4, + .ops = &clk_rcg2_ops, + VDD_DIG_FMAX_MAP1( + LOWER, 19200000), + }, +}; + +static struct clk_branch mmss_bimc_smmu_ahb_clk = { + .halt_reg = 0xe004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0xe004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_bimc_smmu_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_bimc_smmu_axi_clk = { + .halt_reg = 0xe008, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0xe008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_bimc_smmu_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_ahb_clk = { + .halt_reg = 0x348c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x348c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cci_ahb_clk = { + .halt_reg = 0x3348, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3348, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cci_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cci_clk = { + .halt_reg = 0x3344, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3344, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cci_clk", + .parent_names = (const char *[]){ + "cci_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid0_clk = { + .halt_reg = 0x3730, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3730, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid0_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid1_clk = { + .halt_reg = 0x3734, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3734, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid1_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid2_clk = { + .halt_reg = 0x3738, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3738, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid2_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cphy_csid3_clk = { + .halt_reg = 0x373c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x373c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cphy_csid3_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_ahb_clk = { + .halt_reg = 0x36b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_axi_clk = { + .halt_reg = 0x36c4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36c4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_clk = { + .halt_reg = 0x36b0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36b0, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_clk", + .parent_names = (const char *[]){ + "cpp_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_cpp_vbif_ahb_clk = { + .halt_reg = 0x36c8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36c8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_cpp_vbif_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0_ahb_clk = { + .halt_reg = 0x30bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30bc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0_clk = { + .halt_reg = 0x30b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0_clk", + .parent_names = (const char *[]){ + "csi0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0phytimer_clk = { + .halt_reg = 0x3024, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0phytimer_clk", + .parent_names = (const char *[]){ + "csi0phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0pix_clk = { + .halt_reg = 0x30e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30e4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0pix_clk", + .parent_names = (const char *[]){ + "csi0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi0rdi_clk = { + .halt_reg = 0x30d4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x30d4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi0rdi_clk", + .parent_names = (const char *[]){ + "csi0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1_ahb_clk = { + .halt_reg = 0x3128, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3128, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1_clk = { + .halt_reg = 0x3124, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3124, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1_clk", + .parent_names = (const char *[]){ + "csi1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1phytimer_clk = { + .halt_reg = 0x3054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1phytimer_clk", + .parent_names = (const char *[]){ + "csi1phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1pix_clk = { + .halt_reg = 0x3154, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3154, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1pix_clk", + .parent_names = (const char *[]){ + "csi1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi1rdi_clk = { + .halt_reg = 0x3144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3144, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi1rdi_clk", + .parent_names = (const char *[]){ + "csi1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2_ahb_clk = { + .halt_reg = 0x3188, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3188, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2_clk = { + .halt_reg = 0x3184, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3184, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2_clk", + .parent_names = (const char *[]){ + "csi2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2phytimer_clk = { + .halt_reg = 0x3084, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3084, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2phytimer_clk", + .parent_names = (const char *[]){ + "csi2phytimer_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2pix_clk = { + .halt_reg = 0x31b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2pix_clk", + .parent_names = (const char *[]){ + "csi2_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi2rdi_clk = { + .halt_reg = 0x31a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31a4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi2rdi_clk", + .parent_names = (const char *[]){ + "csi2_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3_ahb_clk = { + .halt_reg = 0x31e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31e8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3_clk = { + .halt_reg = 0x31e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x31e4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3_clk", + .parent_names = (const char *[]){ + "csi3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3pix_clk = { + .halt_reg = 0x3214, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3214, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3pix_clk", + .parent_names = (const char *[]){ + "csi3_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi3rdi_clk = { + .halt_reg = 0x3204, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3204, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi3rdi_clk", + .parent_names = (const char *[]){ + "csi3_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi_vfe0_clk = { + .halt_reg = 0x3704, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3704, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi_vfe0_clk", + .parent_names = (const char *[]){ + "vfe0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csi_vfe1_clk = { + .halt_reg = 0x3714, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3714, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csi_vfe1_clk", + .parent_names = (const char *[]){ + "vfe1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csiphy0_clk = { + .halt_reg = 0x3740, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3740, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csiphy0_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csiphy1_clk = { + .halt_reg = 0x3744, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3744, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csiphy1_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_csiphy2_clk = { + .halt_reg = 0x3748, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3748, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_csiphy2_clk", + .parent_names = (const char *[]){ + "csiphy_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_gp0_clk = { + .halt_reg = 0x3444, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3444, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_gp0_clk", + .parent_names = (const char *[]){ + "camss_gp0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_gp1_clk = { + .halt_reg = 0x3474, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3474, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_gp1_clk", + .parent_names = (const char *[]){ + "camss_gp1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_ispif_ahb_clk = { + .halt_reg = 0x3224, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3224, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_ispif_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_jpeg0_clk = { + .halt_reg = 0x35a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x35a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_jpeg0_clk", + .parent_names = (const char *[]){ + "jpeg0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_jpeg_ahb_clk = { + .halt_reg = 0x35b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x35b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_jpeg_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_jpeg_axi_clk = { + .halt_reg = 0x35b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x35b8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_jpeg_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk0_clk = { + .halt_reg = 0x3384, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3384, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk0_clk", + .parent_names = (const char *[]){ + "mclk0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk1_clk = { + .halt_reg = 0x33b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x33b4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk1_clk", + .parent_names = (const char *[]){ + "mclk1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk2_clk = { + .halt_reg = 0x33e4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x33e4, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk2_clk", + .parent_names = (const char *[]){ + "mclk2_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_mclk3_clk = { + .halt_reg = 0x3414, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3414, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_mclk3_clk", + .parent_names = (const char *[]){ + "mclk3_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_micro_ahb_clk = { + .halt_reg = 0x3494, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3494, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_micro_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_top_ahb_clk = { + .halt_reg = 0x3484, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3484, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_top_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe0_ahb_clk = { + .halt_reg = 0x3668, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3668, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe0_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe0_clk = { + .halt_reg = 0x36a8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36a8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe0_clk", + .parent_names = (const char *[]){ + "vfe0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe0_stream_clk = { + .halt_reg = 0x3720, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3720, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe0_stream_clk", + .parent_names = (const char *[]){ + "vfe0_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe1_ahb_clk = { + .halt_reg = 0x3678, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3678, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe1_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe1_clk = { + .halt_reg = 0x36ac, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36ac, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe1_clk", + .parent_names = (const char *[]){ + "vfe1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe1_stream_clk = { + .halt_reg = 0x3724, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3724, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe1_stream_clk", + .parent_names = (const char *[]){ + "vfe1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe_vbif_ahb_clk = { + .halt_reg = 0x36b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36b8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe_vbif_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_camss_vfe_vbif_axi_clk = { + .halt_reg = 0x36bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x36bc, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_camss_vfe_vbif_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_csiphy_ahb2crif_clk = { + .halt_reg = 0x374c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x374c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_csiphy_ahb2crif_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_ahb_clk = { + .halt_reg = 0x2308, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2308, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_axi_clk = { + .halt_reg = 0x2310, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2310, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte0_clk = { + .halt_reg = 0x233c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x233c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte0_clk", + .parent_names = (const char *[]){ + "byte0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte0_intf_clk = { + .halt_reg = 0x2374, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2374, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte0_intf_clk", + .parent_names = (const char *[]){ + "mmss_mdss_byte0_intf_div_clk", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_div mmss_mdss_byte0_intf_div_clk = { + .reg = 0x237c, + .shift = 0, + .width = 2, + /* + * NOTE: Op does not work for div-3. Current assumption is that div-3 + * is not a recommended setting for this divider. + */ + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte0_intf_div_clk", + .parent_names = (const char *[]){ + "byte0_clk_src", + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte1_clk = { + .halt_reg = 0x2340, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2340, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte1_clk", + .parent_names = (const char *[]){ + "byte1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_byte1_intf_clk = { + .halt_reg = 0x2378, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2378, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_byte1_intf_clk", + .parent_names = (const char *[]){ + "byte1_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_aux_clk = { + .halt_reg = 0x2364, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2364, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_aux_clk", + .parent_names = (const char *[]){ + "dp_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_crypto_clk = { + .halt_reg = 0x235c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x235c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_crypto_clk", + .parent_names = (const char *[]){ + "dp_crypto_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_gtc_clk = { + .halt_reg = 0x2368, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2368, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_gtc_clk", + .parent_names = (const char *[]){ + "dp_gtc_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_link_clk = { + .halt_reg = 0x2354, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2354, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_link_clk", + .parent_names = (const char *[]){ + "dp_link_clk_src", + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +/* Reset state of MMSS_MDSS_DP_LINK_INTF_DIV is 0x3 (div-4) */ +static struct clk_branch mmss_mdss_dp_link_intf_clk = { + .halt_reg = 0x2358, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2358, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_link_intf_clk", + .parent_names = (const char *[]){ + "dp_link_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_dp_pixel_clk = { + .halt_reg = 0x2360, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2360, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_dp_pixel_clk", + .parent_names = (const char *[]){ + "dp_pixel_clk_src", + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_esc0_clk = { + .halt_reg = 0x2344, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2344, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_esc0_clk", + .parent_names = (const char *[]){ + "esc0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_esc1_clk = { + .halt_reg = 0x2348, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2348, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_esc1_clk", + .parent_names = (const char *[]){ + "esc1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_hdmi_dp_ahb_clk = { + .halt_reg = 0x230c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x230c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_hdmi_dp_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_mdp_clk = { + .halt_reg = 0x231c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x231c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_mdp_clk", + .parent_names = (const char *[]){ + "mdp_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_pclk0_clk = { + .halt_reg = 0x2314, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2314, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_pclk0_clk", + .parent_names = (const char *[]){ + "pclk0_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_pclk1_clk = { + .halt_reg = 0x2318, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2318, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_pclk1_clk", + .parent_names = (const char *[]){ + "pclk1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_rot_clk = { + .halt_reg = 0x2350, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2350, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_rot_clk", + .parent_names = (const char *[]){ + "rot_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mdss_vsync_clk = { + .halt_reg = 0x2328, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2328, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mdss_vsync_clk", + .parent_names = (const char *[]){ + "vsync_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_misc_ahb_clk = { + .halt_reg = 0x328, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x328, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_misc_ahb_clk", + /* + * Dependency to be enabled before the branch is + * enabled. + */ + .parent_names = (const char *[]){ + "mmss_mnoc_ahb_clk", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_misc_cxo_clk = { + .halt_reg = 0x324, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x324, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_misc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_mnoc_ahb_clk = { + .halt_reg = 0x5024, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x5024, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_mnoc_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_snoc_dvm_axi_clk = { + .halt_reg = 0xe040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xe040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_snoc_dvm_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_ahb_clk = { + .halt_reg = 0x1030, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1030, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_ahb_clk", + .parent_names = (const char *[]){ + "ahb_clk_src", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_axi_clk = { + .halt_reg = 0x1034, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1034, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_core_clk = { + .halt_reg = 0x1028, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1028, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_core_clk", + .parent_names = (const char *[]){ + "video_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mmss_video_subcore0_clk = { + .halt_reg = 0x1048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmss_video_subcore0_clk", + .parent_names = (const char *[]){ + "video_core_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *mmcc_falcon_clocks[] = { + [AHB_CLK_SRC] = &ahb_clk_src.clkr, + [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, + [BYTE1_CLK_SRC] = &byte1_clk_src.clkr, + [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, + [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, + [CCI_CLK_SRC] = &cci_clk_src.clkr, + [CPP_CLK_SRC] = &cpp_clk_src.clkr, + [CSI0_CLK_SRC] = &csi0_clk_src.clkr, + [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, + [CSI1_CLK_SRC] = &csi1_clk_src.clkr, + [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr, + [CSI2_CLK_SRC] = &csi2_clk_src.clkr, + [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr, + [CSI3_CLK_SRC] = &csi3_clk_src.clkr, + [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr, + [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr, + [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr, + [DP_GTC_CLK_SRC] = &dp_gtc_clk_src.clkr, + [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr, + [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr, + [ESC0_CLK_SRC] = &esc0_clk_src.clkr, + [ESC1_CLK_SRC] = &esc1_clk_src.clkr, + [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, + [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, + [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, + [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr, + [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr, + [MDP_CLK_SRC] = &mdp_clk_src.clkr, + [MMPLL0_PLL] = &mmpll0_pll_out_main.clkr, + [MMPLL10_PLL] = &mmpll10_pll_out_main.clkr, + [MMPLL3_PLL] = &mmpll3_pll_out_main.clkr, + [MMPLL4_PLL] = &mmpll4_pll_out_main.clkr, + [MMPLL5_PLL] = &mmpll5_pll_out_main.clkr, + [MMPLL6_PLL] = &mmpll6_pll_out_main.clkr, + [MMPLL7_PLL] = &mmpll7_pll_out_main.clkr, + [MMPLL8_PLL] = &mmpll8_pll_out_main.clkr, + [MMSS_BIMC_SMMU_AHB_CLK] = &mmss_bimc_smmu_ahb_clk.clkr, + [MMSS_BIMC_SMMU_AXI_CLK] = &mmss_bimc_smmu_axi_clk.clkr, + [MMSS_CAMSS_AHB_CLK] = &mmss_camss_ahb_clk.clkr, + [MMSS_CAMSS_CCI_AHB_CLK] = &mmss_camss_cci_ahb_clk.clkr, + [MMSS_CAMSS_CCI_CLK] = &mmss_camss_cci_clk.clkr, + [MMSS_CAMSS_CPHY_CSID0_CLK] = &mmss_camss_cphy_csid0_clk.clkr, + [MMSS_CAMSS_CPHY_CSID1_CLK] = &mmss_camss_cphy_csid1_clk.clkr, + [MMSS_CAMSS_CPHY_CSID2_CLK] = &mmss_camss_cphy_csid2_clk.clkr, + [MMSS_CAMSS_CPHY_CSID3_CLK] = &mmss_camss_cphy_csid3_clk.clkr, + [MMSS_CAMSS_CPP_AHB_CLK] = &mmss_camss_cpp_ahb_clk.clkr, + [MMSS_CAMSS_CPP_AXI_CLK] = &mmss_camss_cpp_axi_clk.clkr, + [MMSS_CAMSS_CPP_CLK] = &mmss_camss_cpp_clk.clkr, + [MMSS_CAMSS_CPP_VBIF_AHB_CLK] = &mmss_camss_cpp_vbif_ahb_clk.clkr, + [MMSS_CAMSS_CSI0_AHB_CLK] = &mmss_camss_csi0_ahb_clk.clkr, + [MMSS_CAMSS_CSI0_CLK] = &mmss_camss_csi0_clk.clkr, + [MMSS_CAMSS_CSI0PHYTIMER_CLK] = &mmss_camss_csi0phytimer_clk.clkr, + [MMSS_CAMSS_CSI0PIX_CLK] = &mmss_camss_csi0pix_clk.clkr, + [MMSS_CAMSS_CSI0RDI_CLK] = &mmss_camss_csi0rdi_clk.clkr, + [MMSS_CAMSS_CSI1_AHB_CLK] = &mmss_camss_csi1_ahb_clk.clkr, + [MMSS_CAMSS_CSI1_CLK] = &mmss_camss_csi1_clk.clkr, + [MMSS_CAMSS_CSI1PHYTIMER_CLK] = &mmss_camss_csi1phytimer_clk.clkr, + [MMSS_CAMSS_CSI1PIX_CLK] = &mmss_camss_csi1pix_clk.clkr, + [MMSS_CAMSS_CSI1RDI_CLK] = &mmss_camss_csi1rdi_clk.clkr, + [MMSS_CAMSS_CSI2_AHB_CLK] = &mmss_camss_csi2_ahb_clk.clkr, + [MMSS_CAMSS_CSI2_CLK] = &mmss_camss_csi2_clk.clkr, + [MMSS_CAMSS_CSI2PHYTIMER_CLK] = &mmss_camss_csi2phytimer_clk.clkr, + [MMSS_CAMSS_CSI2PIX_CLK] = &mmss_camss_csi2pix_clk.clkr, + [MMSS_CAMSS_CSI2RDI_CLK] = &mmss_camss_csi2rdi_clk.clkr, + [MMSS_CAMSS_CSI3_AHB_CLK] = &mmss_camss_csi3_ahb_clk.clkr, + [MMSS_CAMSS_CSI3_CLK] = &mmss_camss_csi3_clk.clkr, + [MMSS_CAMSS_CSI3PIX_CLK] = &mmss_camss_csi3pix_clk.clkr, + [MMSS_CAMSS_CSI3RDI_CLK] = &mmss_camss_csi3rdi_clk.clkr, + [MMSS_CAMSS_CSI_VFE0_CLK] = &mmss_camss_csi_vfe0_clk.clkr, + [MMSS_CAMSS_CSI_VFE1_CLK] = &mmss_camss_csi_vfe1_clk.clkr, + [MMSS_CAMSS_CSIPHY0_CLK] = &mmss_camss_csiphy0_clk.clkr, + [MMSS_CAMSS_CSIPHY1_CLK] = &mmss_camss_csiphy1_clk.clkr, + [MMSS_CAMSS_CSIPHY2_CLK] = &mmss_camss_csiphy2_clk.clkr, + [MMSS_CAMSS_GP0_CLK] = &mmss_camss_gp0_clk.clkr, + [MMSS_CAMSS_GP1_CLK] = &mmss_camss_gp1_clk.clkr, + [MMSS_CAMSS_ISPIF_AHB_CLK] = &mmss_camss_ispif_ahb_clk.clkr, + [MMSS_CAMSS_JPEG0_CLK] = &mmss_camss_jpeg0_clk.clkr, + [MMSS_CAMSS_JPEG_AHB_CLK] = &mmss_camss_jpeg_ahb_clk.clkr, + [MMSS_CAMSS_JPEG_AXI_CLK] = &mmss_camss_jpeg_axi_clk.clkr, + [MMSS_CAMSS_MCLK0_CLK] = &mmss_camss_mclk0_clk.clkr, + [MMSS_CAMSS_MCLK1_CLK] = &mmss_camss_mclk1_clk.clkr, + [MMSS_CAMSS_MCLK2_CLK] = &mmss_camss_mclk2_clk.clkr, + [MMSS_CAMSS_MCLK3_CLK] = &mmss_camss_mclk3_clk.clkr, + [MMSS_CAMSS_MICRO_AHB_CLK] = &mmss_camss_micro_ahb_clk.clkr, + [MMSS_CAMSS_TOP_AHB_CLK] = &mmss_camss_top_ahb_clk.clkr, + [MMSS_CAMSS_VFE0_AHB_CLK] = &mmss_camss_vfe0_ahb_clk.clkr, + [MMSS_CAMSS_VFE0_CLK] = &mmss_camss_vfe0_clk.clkr, + [MMSS_CAMSS_VFE0_STREAM_CLK] = &mmss_camss_vfe0_stream_clk.clkr, + [MMSS_CAMSS_VFE1_AHB_CLK] = &mmss_camss_vfe1_ahb_clk.clkr, + [MMSS_CAMSS_VFE1_CLK] = &mmss_camss_vfe1_clk.clkr, + [MMSS_CAMSS_VFE1_STREAM_CLK] = &mmss_camss_vfe1_stream_clk.clkr, + [MMSS_CAMSS_VFE_VBIF_AHB_CLK] = &mmss_camss_vfe_vbif_ahb_clk.clkr, + [MMSS_CAMSS_VFE_VBIF_AXI_CLK] = &mmss_camss_vfe_vbif_axi_clk.clkr, + [MMSS_CSIPHY_AHB2CRIF_CLK] = &mmss_csiphy_ahb2crif_clk.clkr, + [MMSS_MDSS_AHB_CLK] = &mmss_mdss_ahb_clk.clkr, + [MMSS_MDSS_AXI_CLK] = &mmss_mdss_axi_clk.clkr, + [MMSS_MDSS_BYTE0_CLK] = &mmss_mdss_byte0_clk.clkr, + [MMSS_MDSS_BYTE0_INTF_CLK] = &mmss_mdss_byte0_intf_clk.clkr, + [MMSS_MDSS_BYTE0_INTF_DIV_CLK] = &mmss_mdss_byte0_intf_div_clk.clkr, + [MMSS_MDSS_BYTE1_CLK] = &mmss_mdss_byte1_clk.clkr, + [MMSS_MDSS_BYTE1_INTF_CLK] = &mmss_mdss_byte1_intf_clk.clkr, + [MMSS_MDSS_DP_AUX_CLK] = &mmss_mdss_dp_aux_clk.clkr, + [MMSS_MDSS_DP_CRYPTO_CLK] = &mmss_mdss_dp_crypto_clk.clkr, + [MMSS_MDSS_DP_GTC_CLK] = &mmss_mdss_dp_gtc_clk.clkr, + [MMSS_MDSS_DP_LINK_CLK] = &mmss_mdss_dp_link_clk.clkr, + [MMSS_MDSS_DP_LINK_INTF_CLK] = &mmss_mdss_dp_link_intf_clk.clkr, + [MMSS_MDSS_DP_PIXEL_CLK] = &mmss_mdss_dp_pixel_clk.clkr, + [MMSS_MDSS_ESC0_CLK] = &mmss_mdss_esc0_clk.clkr, + [MMSS_MDSS_ESC1_CLK] = &mmss_mdss_esc1_clk.clkr, + [MMSS_MDSS_HDMI_DP_AHB_CLK] = &mmss_mdss_hdmi_dp_ahb_clk.clkr, + [MMSS_MDSS_MDP_CLK] = &mmss_mdss_mdp_clk.clkr, + [MMSS_MDSS_PCLK0_CLK] = &mmss_mdss_pclk0_clk.clkr, + [MMSS_MDSS_PCLK1_CLK] = &mmss_mdss_pclk1_clk.clkr, + [MMSS_MDSS_ROT_CLK] = &mmss_mdss_rot_clk.clkr, + [MMSS_MDSS_VSYNC_CLK] = &mmss_mdss_vsync_clk.clkr, + [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr, + [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr, + [MMSS_MNOC_AHB_CLK] = &mmss_mnoc_ahb_clk.clkr, + [MMSS_SNOC_DVM_AXI_CLK] = &mmss_snoc_dvm_axi_clk.clkr, + [MMSS_VIDEO_AHB_CLK] = &mmss_video_ahb_clk.clkr, + [MMSS_VIDEO_AXI_CLK] = &mmss_video_axi_clk.clkr, + [MMSS_VIDEO_CORE_CLK] = &mmss_video_core_clk.clkr, + [MMSS_VIDEO_SUBCORE0_CLK] = &mmss_video_subcore0_clk.clkr, + [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, + [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr, + [ROT_CLK_SRC] = &rot_clk_src.clkr, + [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, + [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, + [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr, + [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, +}; + +static const struct qcom_reset_map mmcc_falcon_resets[] = { + [CAMSS_MICRO_BCR] = { 0x3490 }, +}; + +static const struct regmap_config mmcc_falcon_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10004, + .fast_io = true, +}; + +static const struct qcom_cc_desc mmcc_falcon_desc = { + .config = &mmcc_falcon_regmap_config, + .clks = mmcc_falcon_clocks, + .num_clks = ARRAY_SIZE(mmcc_falcon_clocks), + .resets = mmcc_falcon_resets, + .num_resets = ARRAY_SIZE(mmcc_falcon_resets), +}; + +static const struct of_device_id mmcc_falcon_match_table[] = { + { .compatible = "qcom,mmcc-msmfalcon" }, + { } +}; +MODULE_DEVICE_TABLE(of, mmcc_falcon_match_table); + +static int mmcc_falcon_probe(struct platform_device *pdev) +{ + int ret = 0; + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &mmcc_falcon_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + /* PLLs connected on Mx rails of MMSS_CC */ + vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx_mmss"); + if (IS_ERR(vdd_mx.regulator[0])) { + if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_mx_mmss regulator\n"); + return PTR_ERR(vdd_mx.regulator[0]); + } + + vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig_mmss"); + if (IS_ERR(vdd_dig.regulator[0])) { + if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdd_dig regulator\n"); + return PTR_ERR(vdd_dig.regulator[0]); + } + + /* MMPLL10 connected to the Analog Rail */ + vdda.regulator[0] = devm_regulator_get(&pdev->dev, "vdda"); + if (IS_ERR(vdda.regulator[0])) { + if (!(PTR_ERR(vdda.regulator[0]) == -EPROBE_DEFER)) + dev_err(&pdev->dev, + "Unable to get vdda regulator\n"); + return PTR_ERR(vdda.regulator[0]); + } + + clk_alpha_pll_configure(&mmpll3_pll_out_main, regmap, &mmpll3_config); + clk_alpha_pll_configure(&mmpll4_pll_out_main, regmap, &mmpll4_config); + clk_alpha_pll_configure(&mmpll5_pll_out_main, regmap, &mmpll5_config); + clk_alpha_pll_configure(&mmpll7_pll_out_main, regmap, &mmpll7_config); + clk_alpha_pll_configure(&mmpll8_pll_out_main, regmap, &mmpll8_config); + clk_alpha_pll_configure(&mmpll10_pll_out_main, regmap, &mmpll10_config); + + ret = qcom_cc_really_probe(pdev, &mmcc_falcon_desc, regmap); + if (ret) { + dev_err(&pdev->dev, "Failed to register MMSS clocks\n"); + return ret; + } + + dev_info(&pdev->dev, "Registered MMSS clocks\n"); + + return ret; +} + +static struct platform_driver mmcc_falcon_driver = { + .probe = mmcc_falcon_probe, + .driver = { + .name = "mmcc-msmfalcon", + .of_match_table = mmcc_falcon_match_table, + }, +}; + +static int __init mmcc_falcon_init(void) +{ + return platform_driver_register(&mmcc_falcon_driver); +} +core_initcall_sync(mmcc_falcon_init); + +static void __exit mmcc_falcon_exit(void) +{ + platform_driver_unregister(&mmcc_falcon_driver); +} +module_exit(mmcc_falcon_exit); diff --git a/drivers/clk/qcom/vdd-level-falcon.h b/drivers/clk/qcom/vdd-level-falcon.h index d54e801ecc67..8f9eefe3a89c 100644 --- a/drivers/clk/qcom/vdd-level-falcon.h +++ b/drivers/clk/qcom/vdd-level-falcon.h @@ -116,6 +116,21 @@ }, \ .num_rate_max = VDD_DIG_NUM +#define VDD_MMSS_PLL_DIG_FMAX_MAP1(l1, f1) \ + .vdd_class = &vdd_mx, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + }, \ + .num_rate_max = VDD_DIG_NUM + +#define VDD_MMSS_PLL_DIG_FMAX_MAP2(l1, f1, l2, f2) \ + .vdd_class = &vdd_mx, \ + .rate_max = (unsigned long[VDD_DIG_NUM]) { \ + [VDD_DIG_##l1] = (f1), \ + [VDD_DIG_##l2] = (f2), \ + }, \ + .num_rate_max = VDD_DIG_NUM + enum vdd_dig_levels { VDD_DIG_NONE, VDD_DIG_MIN, /* MIN SVS */ diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 77aea1f41714..11d88df37d31 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -372,18 +372,18 @@ config CRYPTO_DEV_QCRYPTO config CRYPTO_DEV_QCOM_MSM_QCE tristate "Qualcomm Crypto Engine (QCE) module" - select CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSMCOBALT || ARCH_MSMFALCON || ARCH_MSMTRITON + select CRYPTO_DEV_QCE50 if ARCH_APQ8084 || ARCH_MSM8916 || ARCH_MSM8994 || ARCH_MSM8996 || ARCH_MSM8992 || ARCH_MSMTITANIUM || ARCH_MSM8909 || ARCH_MSM8998 || ARCH_MSMFALCON || ARCH_MSMTRITON default n help This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660 MSM8x55, MSM8960, MSM9615, MSM8916, MSM8994, MSM8996, FSM9900, - MSMTITANINUM, APQ8084, MSMCOBALT, MSMFALCON and MSMTRITON. + MSMTITANINUM, APQ8084, MSM8998, MSMFALCON and MSMTRITON. To compile this driver as a module, choose M here: the For MSM7x30 MSM8660 and MSM8x55 the module is called qce For MSM8960, APQ8064 and MSM9615 the module is called qce40 For MSM8974, MSM8916, MSM8994, MSM8996, MSM8992, MSMTITANIUM, - APQ8084, MSMCOBALT, MSMFALCON and MSMTRITON the module is called qce50. + APQ8084, MSM8998, MSMFALCON and MSMTRITON the module is called qce50. config CRYPTO_DEV_QCEDEV tristate "QCEDEV Interface to CE module" @@ -391,7 +391,7 @@ config CRYPTO_DEV_QCEDEV help This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660, MSM8960, MSM9615, APQ8064, MSM8974, MSM8916, MSM8994, MSM8996, - APQ8084, MSMCOBALT, MSMFALCON, MSMTRITON. This exposes the + APQ8084, MSM8998, MSMFALCON, MSMTRITON. This exposes the interface to the QCE hardware accelerator via IOCTLs. To compile this driver as a module, choose M here: the diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index 9dc9f93f4e36..577183bea07c 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -1251,6 +1251,7 @@ static void hid_input_field(struct hid_device *hid, struct hid_field *field, /* Ignore report if ErrorRollOver */ if (!(field->flags & HID_MAIN_ITEM_VARIABLE) && value[n] >= min && value[n] <= max && + value[n] - min < field->maxusage && field->usage[value[n] - min].hid == HID_UP_KEYBOARD + 1) goto exit; } @@ -1263,11 +1264,13 @@ static void hid_input_field(struct hid_device *hid, struct hid_field *field, } if (field->value[n] >= min && field->value[n] <= max + && field->value[n] - min < field->maxusage && field->usage[field->value[n] - min].hid && search(value, field->value[n], count)) hid_process_event(hid, field, &field->usage[field->value[n] - min], 0, interrupt); if (value[n] >= min && value[n] <= max + && value[n] - min < field->maxusage && field->usage[value[n] - min].hid && search(field->value, value[n], count)) hid_process_event(hid, field, &field->usage[value[n] - min], 1, interrupt); diff --git a/drivers/leds/leds-qpnp-wled.c b/drivers/leds/leds-qpnp-wled.c index 79c54edefdc5..9695c35c56b4 100644 --- a/drivers/leds/leds-qpnp-wled.c +++ b/drivers/leds/leds-qpnp-wled.c @@ -76,7 +76,7 @@ #define QPNP_WLED_VLOOP_COMP_AUTO_GM_THRESH_MASK GENMASK(5, 4) #define QPNP_WLED_VLOOP_COMP_AUTO_GM_THRESH_SHIFT 4 #define QPNP_WLED_LOOP_EA_GM_DFLT_AMOLED_PMI8994 0x03 -#define QPNP_WLED_LOOP_GM_DFLT_AMOLED_PMICOBALT 0x09 +#define QPNP_WLED_LOOP_GM_DFLT_AMOLED_PMI8998 0x09 #define QPNP_WLED_LOOP_GM_DFLT_WLED 0x09 #define QPNP_WLED_LOOP_EA_GM_MIN 0x0 #define QPNP_WLED_LOOP_EA_GM_MAX 0xF @@ -100,9 +100,9 @@ #define PMI8994_WLED_ILIM_MAX_MA 1980 #define PMI8994_WLED_DFLT_ILIM_MA 980 #define PMI8994_AMOLED_DFLT_ILIM_MA 385 -#define PMICOBALT_WLED_ILIM_MAX_MA 1500 -#define PMICOBALT_WLED_DFLT_ILIM_MA 970 -#define PMICOBALT_AMOLED_DFLT_ILIM_MA 620 +#define PMI8998_WLED_ILIM_MAX_MA 1500 +#define PMI8998_WLED_DFLT_ILIM_MA 970 +#define PMI8998_AMOLED_DFLT_ILIM_MA 620 #define QPNP_WLED_BOOST_DUTY_MASK 0xFC #define QPNP_WLED_BOOST_DUTY_STEP_NS 52 #define QPNP_WLED_BOOST_DUTY_MIN_NS 26 @@ -272,7 +272,7 @@ static int qpnp_wled_ovp_thresholds_pmi8994[NUM_SUPPORTED_OVP_THRESHOLDS] = { 31000, 29500, 19400, 17800, }; -static int qpnp_wled_ovp_thresholds_pmicobalt[NUM_SUPPORTED_OVP_THRESHOLDS] = { +static int qpnp_wled_ovp_thresholds_pmi8998[NUM_SUPPORTED_OVP_THRESHOLDS] = { 31100, 29600, 19600, 18100, }; @@ -280,7 +280,7 @@ static int qpnp_wled_ilim_settings_pmi8994[NUM_SUPPORTED_ILIM_THRESHOLDS] = { 105, 385, 660, 980, 1150, 1420, 1700, 1980, }; -static int qpnp_wled_ilim_settings_pmicobalt[NUM_SUPPORTED_ILIM_THRESHOLDS] = { +static int qpnp_wled_ilim_settings_pmi8998[NUM_SUPPORTED_ILIM_THRESHOLDS] = { 105, 280, 450, 620, 970, 1150, 1300, 1500, }; @@ -294,7 +294,7 @@ struct wled_vref_setting { static struct wled_vref_setting vref_setting_pmi8994 = { 300000, 675000, 25000, 350000, }; -static struct wled_vref_setting vref_setting_pmicobalt = { +static struct wled_vref_setting vref_setting_pmi8998 = { 60000, 397500, 22500, 127500, }; @@ -1064,10 +1064,10 @@ static bool is_avdd_trim_adjustment_required(struct qpnp_wled *wled) u8 reg = 0; /* - * AVDD trim adjustment is not required for pmicobalt/pm2falcon and not + * AVDD trim adjustment is not required for pmi8998/pm2falcon and not * supported for pmi8994. */ - if (wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PMI8994_SUBTYPE) return false; @@ -1093,7 +1093,7 @@ static int qpnp_wled_gm_config(struct qpnp_wled *wled) u8 mask = 0, reg = 0; /* Configure the LOOP COMP GM register */ - if (wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { if (wled->loop_auto_gm_en) reg |= QPNP_WLED_VLOOP_COMP_AUTO_GM_EN; @@ -1138,9 +1138,9 @@ static int qpnp_wled_ovp_config(struct qpnp_wled *wled) if (wled->disp_type_amoled) return 0; - if (wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) - ovp_table = qpnp_wled_ovp_thresholds_pmicobalt; + ovp_table = qpnp_wled_ovp_thresholds_pmi8998; else ovp_table = qpnp_wled_ovp_thresholds_pmi8994; @@ -1222,9 +1222,9 @@ static int qpnp_wled_avdd_mode_config(struct qpnp_wled *wled) /* * At present, configuring the mode to SPMI/SWIRE for controlling - * AVDD voltage is available only in pmicobalt/pm2falcon. + * AVDD voltage is available only in pmi8998/pm2falcon. */ - if (wled->pmic_rev_id->pmic_subtype != PMICOBALT_SUBTYPE && + if (wled->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE && wled->pmic_rev_id->pmic_subtype != PM2FALCON_SUBTYPE) return 0; @@ -1268,11 +1268,11 @@ static int qpnp_wled_ilim_config(struct qpnp_wled *wled) if (wled->ilim_ma < PMI8994_WLED_ILIM_MIN_MA) wled->ilim_ma = PMI8994_WLED_ILIM_MIN_MA; - if (wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { - ilim_table = qpnp_wled_ilim_settings_pmicobalt; - if (wled->ilim_ma > PMICOBALT_WLED_ILIM_MAX_MA) - wled->ilim_ma = PMICOBALT_WLED_ILIM_MAX_MA; + ilim_table = qpnp_wled_ilim_settings_pmi8998; + if (wled->ilim_ma > PMI8998_WLED_ILIM_MAX_MA) + wled->ilim_ma = PMI8998_WLED_ILIM_MAX_MA; } else { ilim_table = qpnp_wled_ilim_settings_pmi8994; if (wled->ilim_ma > PMI8994_WLED_ILIM_MAX_MA) @@ -1307,9 +1307,9 @@ static int qpnp_wled_vref_config(struct qpnp_wled *wled) int rc; u8 reg = 0; - if (wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) - vref_setting = vref_setting_pmicobalt; + vref_setting = vref_setting_pmi8998; else vref_setting = vref_setting_pmi8994; @@ -1374,7 +1374,7 @@ static int qpnp_wled_config(struct qpnp_wled *wled) } /* Configure auto PFM mode for LCD mode only */ - if ((wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if ((wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) && !wled->disp_type_amoled) { reg = 0; @@ -1771,10 +1771,10 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } if (wled->disp_type_amoled) { - if (wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) wled->loop_ea_gm = - QPNP_WLED_LOOP_GM_DFLT_AMOLED_PMICOBALT; + QPNP_WLED_LOOP_GM_DFLT_AMOLED_PMI8998; else wled->loop_ea_gm = QPNP_WLED_LOOP_EA_GM_DFLT_AMOLED_PMI8994; @@ -1791,7 +1791,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) return rc; } - if (wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { wled->loop_auto_gm_en = of_property_read_bool(pdev->dev.of_node, @@ -1807,10 +1807,10 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) } } - if (wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { - if (wled->pmic_rev_id->rev4 == PMICOBALT_V2P0_REV4) + if (wled->pmic_rev_id->rev4 == PMI8998_V2P0_REV4) wled->lcd_auto_pfm_en = false; else wled->lcd_auto_pfm_en = true; @@ -1860,9 +1860,9 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) return rc; } - if (wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) - wled->vref_uv = vref_setting_pmicobalt.default_uv; + wled->vref_uv = vref_setting_pmi8998.default_uv; else wled->vref_uv = vref_setting_pmi8994.default_uv; rc = of_property_read_u32(pdev->dev.of_node, @@ -1884,7 +1884,7 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) return rc; } - if (wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) wled->ovp_mv = 29600; else @@ -1898,12 +1898,12 @@ static int qpnp_wled_parse_dt(struct qpnp_wled *wled) return rc; } - if (wled->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE || + if (wled->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE || wled->pmic_rev_id->pmic_subtype == PM2FALCON_SUBTYPE) { if (wled->disp_type_amoled) - wled->ilim_ma = PMICOBALT_AMOLED_DFLT_ILIM_MA; + wled->ilim_ma = PMI8998_AMOLED_DFLT_ILIM_MA; else - wled->ilim_ma = PMICOBALT_WLED_DFLT_ILIM_MA; + wled->ilim_ma = PMI8998_WLED_DFLT_ILIM_MA; } else { if (wled->disp_type_amoled) wled->ilim_ma = PMI8994_AMOLED_DFLT_ILIM_MA; diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c index 4e86a3ff820d..eaf35733b38a 100644 --- a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c +++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c @@ -2013,15 +2013,18 @@ static int sde_hw_rotator_validate_entry(struct sde_rot_mgr *mgr, } } - fmt = sde_get_format_params(item->output.format); - /* Tiled format downscale support not applied to AYUV tiled */ - if (sde_mdp_is_tilea5x_format(fmt) && (entry->dnsc_factor_h > 4)) { - SDEROT_DBG("max downscale for tiled format is 4\n"); + fmt = sde_get_format_params(item->input.format); + /* + * Rotator downscale support max 4 times for UBWC format and + * max 2 times for TP10/TP10_UBWC format + */ + if (sde_mdp_is_ubwc_format(fmt) && (entry->dnsc_factor_h > 4)) { + SDEROT_DBG("max downscale for UBWC format is 4\n"); ret = -EINVAL; goto dnsc_err; } - if (sde_mdp_is_ubwc_format(fmt) && (entry->dnsc_factor_h > 2)) { - SDEROT_DBG("downscale with ubwc cannot be more than 2\n"); + if (sde_mdp_is_tp10_format(fmt) && (entry->dnsc_factor_h > 2)) { + SDEROT_DBG("downscale with TP10 cannot be more than 2\n"); ret = -EINVAL; } goto dnsc_err; @@ -2076,6 +2079,7 @@ static ssize_t sde_hw_rotator_show_caps(struct sde_rot_mgr *mgr, struct device_attribute *attr, char *buf, ssize_t len) { struct sde_hw_rotator *hw_data; + struct sde_rot_data_type *mdata = sde_rot_get_mdata(); int cnt = 0; if (!mgr || !buf) @@ -2087,6 +2091,10 @@ static ssize_t sde_hw_rotator_show_caps(struct sde_rot_mgr *mgr, (cnt += scnprintf(buf + cnt, len - cnt, fmt, ##__VA_ARGS__)) /* insert capabilities here */ + if (test_bit(SDE_CAPS_R3_1P5_DOWNSCALE, mdata->sde_caps_map)) + SPRINT("min_downscale=1.5\n"); + else + SPRINT("min_downscale=2.0\n"); #undef SPRINT return cnt; diff --git a/drivers/media/tuners/tuner-xc2028.c b/drivers/media/tuners/tuner-xc2028.c index 4e941f00b600..082ff5608455 100644 --- a/drivers/media/tuners/tuner-xc2028.c +++ b/drivers/media/tuners/tuner-xc2028.c @@ -1403,11 +1403,12 @@ static int xc2028_set_config(struct dvb_frontend *fe, void *priv_cfg) * in order to avoid troubles during device release. */ kfree(priv->ctrl.fname); + priv->ctrl.fname = NULL; memcpy(&priv->ctrl, p, sizeof(priv->ctrl)); if (p->fname) { priv->ctrl.fname = kstrdup(p->fname, GFP_KERNEL); if (priv->ctrl.fname == NULL) - rc = -ENOMEM; + return -ENOMEM; } /* diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 240bf2903308..9a6f1aed82e8 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -60,7 +60,7 @@ #define PCS_BASE 0x800 #define PCS_MISC_BASE 0x600 -#elif defined(CONFIG_ARCH_MSMCOBALT) +#elif defined(CONFIG_ARCH_MSM8998) #define PCIE_VENDOR_ID_RCP 0x17cb #define PCIE_DEVICE_ID_RCP 0x0105 diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 4805c4feac74..6b83b50d382e 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -96,13 +96,13 @@ config PINCTRL_QCOM_SSBI_PMIC which are using SSBI for communication with SoC. Example PMIC's devices are pm8058 and pm8921. -config PINCTRL_MSMCOBALT - tristate "Qualcomm MSMCOBALT pin controller driver" +config PINCTRL_MSM8998 + tristate "Qualcomm MSM8998 pin controller driver" depends on GPIOLIB && OF select PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the - Qualcomm TLMM block found in the Qualcomm MSMCOBALT platform. + Qualcomm TLMM block found in the Qualcomm MSM8998 platform. config PINCTRL_MSM8996 tristate "Qualcomm MSM8996 pin controller driver" diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index bddc21431eeb..7d9cc7a9eb43 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -13,6 +13,6 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o -obj-$(CONFIG_PINCTRL_MSMCOBALT) += pinctrl-msmcobalt.o +obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o obj-$(CONFIG_PINCTRL_MSMFALCON) += pinctrl-msmfalcon.o obj-$(CONFIG_PINCTRL_WCD) += pinctrl-wcd.o diff --git a/drivers/pinctrl/qcom/pinctrl-msmcobalt.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c index 039da7b0997b..e983bcc8e47d 100644 --- a/drivers/pinctrl/qcom/pinctrl-msmcobalt.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c @@ -92,7 +92,7 @@ .intr_detection_bit = -1, \ .intr_detection_width = -1, \ } -static const struct pinctrl_pin_desc msmcobalt_pins[] = { +static const struct pinctrl_pin_desc msm8998_pins[] = { PINCTRL_PIN(0, "GPIO_0"), PINCTRL_PIN(1, "GPIO_1"), PINCTRL_PIN(2, "GPIO_2"), @@ -405,7 +405,7 @@ static const unsigned int sdc2_clk_pins[] = { 150 }; static const unsigned int sdc2_cmd_pins[] = { 151 }; static const unsigned int sdc2_data_pins[] = { 152 }; -enum msmcobalt_functions { +enum msm8998_functions { msm_mux_blsp_spi1, msm_mux_blsp_uim1_a, msm_mux_blsp_uart1_a, @@ -1374,7 +1374,7 @@ static const char * const mss_lte_groups[] = { "gpio144", "gpio145", }; -static const struct msm_function msmcobalt_functions[] = { +static const struct msm_function msm8998_functions[] = { FUNCTION(blsp_spi1), FUNCTION(gpio), FUNCTION(blsp_uim1_a), @@ -1612,7 +1612,7 @@ static const struct msm_function msmcobalt_functions[] = { FUNCTION(mss_lte), }; -static const struct msm_pingroup msmcobalt_groups[] = { +static const struct msm_pingroup msm8998_groups[] = { PINGROUP(0, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, NA, NA, NA, NA, NA, NA), PINGROUP(1, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, NA, NA, NA, NA, @@ -1858,48 +1858,48 @@ static const struct msm_pingroup msmcobalt_groups[] = { SDC_QDSD_PINGROUP(sdc2_data, 0x999000, 9, 0), }; -static const struct msm_pinctrl_soc_data msmcobalt_pinctrl = { - .pins = msmcobalt_pins, - .npins = ARRAY_SIZE(msmcobalt_pins), - .functions = msmcobalt_functions, - .nfunctions = ARRAY_SIZE(msmcobalt_functions), - .groups = msmcobalt_groups, - .ngroups = ARRAY_SIZE(msmcobalt_groups), +static const struct msm_pinctrl_soc_data msm8998_pinctrl = { + .pins = msm8998_pins, + .npins = ARRAY_SIZE(msm8998_pins), + .functions = msm8998_functions, + .nfunctions = ARRAY_SIZE(msm8998_functions), + .groups = msm8998_groups, + .ngroups = ARRAY_SIZE(msm8998_groups), .ngpios = 153, }; -static int msmcobalt_pinctrl_probe(struct platform_device *pdev) +static int msm8998_pinctrl_probe(struct platform_device *pdev) { - return msm_pinctrl_probe(pdev, &msmcobalt_pinctrl); + return msm_pinctrl_probe(pdev, &msm8998_pinctrl); } -static const struct of_device_id msmcobalt_pinctrl_of_match[] = { - { .compatible = "qcom,msmcobalt-pinctrl", }, +static const struct of_device_id msm8998_pinctrl_of_match[] = { + { .compatible = "qcom,msm8998-pinctrl", }, { }, }; -static struct platform_driver msmcobalt_pinctrl_driver = { +static struct platform_driver msm8998_pinctrl_driver = { .driver = { - .name = "msmcobalt-pinctrl", + .name = "msm8998-pinctrl", .owner = THIS_MODULE, - .of_match_table = msmcobalt_pinctrl_of_match, + .of_match_table = msm8998_pinctrl_of_match, }, - .probe = msmcobalt_pinctrl_probe, + .probe = msm8998_pinctrl_probe, .remove = msm_pinctrl_remove, }; -static int __init msmcobalt_pinctrl_init(void) +static int __init msm8998_pinctrl_init(void) { - return platform_driver_register(&msmcobalt_pinctrl_driver); + return platform_driver_register(&msm8998_pinctrl_driver); } -arch_initcall(msmcobalt_pinctrl_init); +arch_initcall(msm8998_pinctrl_init); -static void __exit msmcobalt_pinctrl_exit(void) +static void __exit msm8998_pinctrl_exit(void) { - platform_driver_unregister(&msmcobalt_pinctrl_driver); + platform_driver_unregister(&msm8998_pinctrl_driver); } -module_exit(msmcobalt_pinctrl_exit); +module_exit(msm8998_pinctrl_exit); -MODULE_DESCRIPTION("QTI msmcobalt pinctrl driver"); +MODULE_DESCRIPTION("QTI msm8998 pinctrl driver"); MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, msmcobalt_pinctrl_of_match); +MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match); diff --git a/drivers/platform/msm/qpnp-revid.c b/drivers/platform/msm/qpnp-revid.c index 1ef8ebe3ed7d..cfc8093fa3dd 100644 --- a/drivers/platform/msm/qpnp-revid.c +++ b/drivers/platform/msm/qpnp-revid.c @@ -52,8 +52,8 @@ static const char *const pmic_names[] = { [PMI8950_SUBTYPE] = "PMI8950", [PMK8001_SUBTYPE] = "PMK8001", [PMI8996_SUBTYPE] = "PMI8996", - [PMCOBALT_SUBTYPE] = "PMCOBALT", - [PMICOBALT_SUBTYPE] = "PMICOBALT", + [PM8998_SUBTYPE] = "PM8998", + [PMI8998_SUBTYPE] = "PMI8998", [PM8005_SUBTYPE] = "PM8005", [PM8937_SUBTYPE] = "PM8937", [PM2FALCON_SUBTYPE] = "PM2FALCON", diff --git a/drivers/power/qcom-charger/bcl_peripheral.c b/drivers/power/qcom-charger/bcl_peripheral.c index 8a7012ac2bef..cae4967f1ef4 100644 --- a/drivers/power/qcom-charger/bcl_peripheral.c +++ b/drivers/power/qcom-charger/bcl_peripheral.c @@ -56,25 +56,25 @@ #define BCL_VBAT_TRIP 0x68 #define BCL_IBAT_TRIP 0x69 -#define BCL_COBALT_VBAT_VALUE 0x58 -#define BCL_COBALT_IBAT_VALUE 0x59 -#define BCL_COBALT_VBAT_MIN 0x5C -#define BCL_COBALT_IBAT_MAX 0x5D -#define BCL_COBALT_MAX_MIN_CLR 0x48 -#define BCL_COBALT_IBAT_MAX_CLR 3 -#define BCL_COBALT_VBAT_MIN_CLR 2 -#define BCL_COBALT_VBAT_ADC_LOW 0x72 -#define BCL_COBALT_VBAT_COMP_LOW 0x75 -#define BCL_COBALT_VBAT_COMP_TLOW 0x76 -#define BCL_COBALT_IBAT_HIGH 0x78 -#define BCL_COBALT_IBAT_TOO_HIGH 0x79 -#define BCL_COBALT_LMH_CFG 0xA3 -#define BCL_COBALT_BCL_CFG 0x6A -#define LMH_COBALT_INT_POL_HIGH 0x12 -#define LMH_COBALT_INT_EN 0x15 - -#define BCL_COBALT_VBAT_SCALING 39000 -#define BCL_COBALT_IBAT_SCALING 80000 +#define BCL_8998_VBAT_VALUE 0x58 +#define BCL_8998_IBAT_VALUE 0x59 +#define BCL_8998_VBAT_MIN 0x5C +#define BCL_8998_IBAT_MAX 0x5D +#define BCL_8998_MAX_MIN_CLR 0x48 +#define BCL_8998_IBAT_MAX_CLR 3 +#define BCL_8998_VBAT_MIN_CLR 2 +#define BCL_8998_VBAT_ADC_LOW 0x72 +#define BCL_8998_VBAT_COMP_LOW 0x75 +#define BCL_8998_VBAT_COMP_TLOW 0x76 +#define BCL_8998_IBAT_HIGH 0x78 +#define BCL_8998_IBAT_TOO_HIGH 0x79 +#define BCL_8998_LMH_CFG 0xA3 +#define BCL_8998_BCL_CFG 0x6A +#define LMH_8998_INT_POL_HIGH 0x12 +#define LMH_8998_INT_EN 0x15 + +#define BCL_8998_VBAT_SCALING 39000 +#define BCL_8998_IBAT_SCALING 80000 #define BCL_VBAT_LOW_THRESHOLD 0x7 /* 3.1V */ #define BCL_VBAT_TLOW_THRESHOLD 0x5 /* 2.9v */ #define BCL_IBAT_HIGH_THRESH_UA 4300000 @@ -124,7 +124,7 @@ enum bcl_monitor_state { enum bcl_hw_type { BCL_PMI8994, - BCL_PMICOBALT, + BCL_PMI8998, BCL_VERSION_MAX, }; @@ -243,8 +243,8 @@ static void convert_vbat_to_adc_val(int *val) / perph_data->gain_factor_den)) / perph_data->scaling_factor; break; - case BCL_PMICOBALT: - *val = *val / BCL_COBALT_VBAT_SCALING; + case BCL_PMI8998: + *val = *val / BCL_8998_VBAT_SCALING; break; default: break; @@ -268,8 +268,8 @@ static void convert_adc_to_vbat_val(int *val) * BCL_CONSTANT_NUM / perph_data->gain_factor_den) / 100; break; - case BCL_PMICOBALT: - *val = *val * BCL_COBALT_VBAT_SCALING; + case BCL_PMI8998: + *val = *val * BCL_8998_VBAT_SCALING; break; default: break; @@ -295,8 +295,8 @@ static void convert_ibat_to_adc_val(int *val) / perph_data->offset_factor_den) / perph_data->scaling_factor; break; - case BCL_PMICOBALT: - *val = *val / BCL_COBALT_IBAT_SCALING; + case BCL_PMI8998: + *val = *val / BCL_8998_IBAT_SCALING; break; default: break; @@ -321,8 +321,8 @@ static void convert_adc_to_ibat_val(int *val) * perph_data->gain) * BCL_CONSTANT_NUM / perph_data->gain_factor_den) / 100; break; - case BCL_PMICOBALT: - *val = *val * BCL_COBALT_IBAT_SCALING; + case BCL_PMI8998: + *val = *val * BCL_8998_IBAT_SCALING; break; default: break; @@ -355,18 +355,18 @@ static int bcl_set_high_ibat(int thresh_value) thresh_value); val = (int8_t)thresh_value; ret = bcl_write_register((bcl_perph_version == BCL_PMI8994) ? - BCL_IBAT_TRIP : BCL_COBALT_IBAT_HIGH, val); + BCL_IBAT_TRIP : BCL_8998_IBAT_HIGH, val); if (ret) { pr_err("Error accessing BCL peripheral. err:%d\n", ret); return ret; } bcl_perph->param[BCL_PARAM_CURRENT].high_trip = thresh_value; - if (bcl_perph_version == BCL_PMICOBALT) { + if (bcl_perph_version == BCL_PMI8998) { convert_ibat_to_adc_val(&too_high_thresh); pr_debug("Setting Ibat too high trip:%d. ADC_val:%d\n", BCL_IBAT_HIGH_THRESH_UA, too_high_thresh); val = (int8_t)too_high_thresh; - ret = bcl_write_register(BCL_COBALT_IBAT_TOO_HIGH, val); + ret = bcl_write_register(BCL_8998_IBAT_TOO_HIGH, val); if (ret) { pr_err("Error accessing BCL peripheral. err:%d\n", ret); return ret; @@ -408,13 +408,13 @@ static int bcl_set_low_vbat(int thresh_value) thresh_value); val = (int8_t)thresh_value; ret = bcl_write_register((bcl_perph_version == BCL_PMI8994) - ? BCL_VBAT_TRIP : BCL_COBALT_VBAT_ADC_LOW, val); + ? BCL_VBAT_TRIP : BCL_8998_VBAT_ADC_LOW, val); if (ret) { pr_err("Error accessing BCL peripheral. err:%d\n", ret); return ret; } - if (bcl_perph_version == BCL_PMICOBALT) { - ret = bcl_write_register(BCL_COBALT_VBAT_COMP_LOW, + if (bcl_perph_version == BCL_PMI8998) { + ret = bcl_write_register(BCL_8998_VBAT_COMP_LOW, BCL_VBAT_LOW_THRESHOLD); if (ret) { pr_err("Error accessing BCL peripheral. err:%d\n", ret); @@ -422,7 +422,7 @@ static int bcl_set_low_vbat(int thresh_value) } pr_debug("Setting Vbat low comparator threshold:0x%x.\n", BCL_VBAT_LOW_THRESHOLD); - ret = bcl_write_register(BCL_COBALT_VBAT_COMP_TLOW, + ret = bcl_write_register(BCL_8998_VBAT_COMP_TLOW, BCL_VBAT_TLOW_THRESHOLD); if (ret) { pr_err("Error accessing BCL peripheral. err:%d\n", ret); @@ -482,7 +482,7 @@ static int bcl_access_monitor_enable(bool enable) if (enable == bcl_perph->enabled) goto access_exit; - if ((bcl_perph_version == BCL_PMICOBALT) && !hw_enabled && enable) + if ((bcl_perph_version == BCL_PMI8998) && !hw_enabled && enable) bcl_lmh_dcvs_enable(); for (; i < BCL_PARAM_MAX; i++) { @@ -552,7 +552,7 @@ static int bcl_read_ibat_high_trip(int *thresh_value) *thresh_value = (int)val; ret = bcl_read_register((bcl_perph_version == BCL_PMI8994) ? - BCL_IBAT_TRIP : BCL_COBALT_IBAT_HIGH, &val); + BCL_IBAT_TRIP : BCL_8998_IBAT_HIGH, &val); if (ret) { pr_err("BCL register read error. err:%d\n", ret); ret = 0; @@ -581,7 +581,7 @@ static int bcl_read_vbat_low_trip(int *thresh_value) *thresh_value = (int)val; ret = bcl_read_register((bcl_perph_version == BCL_PMI8994) - ? BCL_VBAT_TRIP : BCL_COBALT_VBAT_ADC_LOW, + ? BCL_VBAT_TRIP : BCL_8998_VBAT_ADC_LOW, &val); if (ret) { pr_err("BCL register read error. err:%d\n", ret); @@ -610,8 +610,8 @@ static int bcl_clear_vbat_min(void) if (bcl_perph_version == BCL_PMI8994) ret = bcl_write_register(BCL_VBAT_MIN_CLR, BIT(7)); else - ret = bcl_write_register(BCL_COBALT_MAX_MIN_CLR, - BIT(BCL_COBALT_VBAT_MIN_CLR)); + ret = bcl_write_register(BCL_8998_MAX_MIN_CLR, + BIT(BCL_8998_VBAT_MIN_CLR)); if (ret) pr_err("Error in clearing vbat min reg. err:%d", ret); @@ -625,8 +625,8 @@ static int bcl_clear_ibat_max(void) if (bcl_perph_version == BCL_PMI8994) ret = bcl_write_register(BCL_IBAT_MAX_CLR, BIT(7)); else - ret = bcl_write_register(BCL_COBALT_MAX_MIN_CLR, - BIT(BCL_COBALT_IBAT_MAX_CLR)); + ret = bcl_write_register(BCL_8998_MAX_MIN_CLR, + BIT(BCL_8998_IBAT_MAX_CLR)); if (ret) pr_err("Error in clearing ibat max reg. err:%d", ret); @@ -642,7 +642,7 @@ static int bcl_read_ibat_max(int *adc_value) do { ret = bcl_read_multi_register( (bcl_perph_version == BCL_PMI8994) ? BCL_IBAT_MAX - : BCL_COBALT_IBAT_MAX, val, + : BCL_8998_IBAT_MAX, val, VAL_CP_REG_BUF_LEN); if (ret) { pr_err("BCL register read error. err:%d\n", ret); @@ -673,7 +673,7 @@ static int bcl_read_vbat_min(int *adc_value) do { ret = bcl_read_multi_register( (bcl_perph_version == BCL_PMI8994) ? BCL_VBAT_MIN - : BCL_COBALT_VBAT_MIN, val, + : BCL_8998_VBAT_MIN, val, VAL_CP_REG_BUF_LEN); if (ret) { pr_err("BCL register read error. err:%d\n", ret); @@ -704,7 +704,7 @@ static int bcl_read_ibat(int *adc_value) do { ret = bcl_read_multi_register( (bcl_perph_version == BCL_PMI8994) ? BCL_IBAT_VALUE - : BCL_COBALT_IBAT_VALUE, val, + : BCL_8998_IBAT_VALUE, val, VAL_CP_REG_BUF_LEN); if (ret) { pr_err("BCL register read error. err:%d\n", ret); @@ -735,7 +735,7 @@ static int bcl_read_vbat(int *adc_value) do { ret = bcl_read_multi_register( (bcl_perph_version == BCL_PMI8994) ? BCL_VBAT_VALUE : - BCL_COBALT_VBAT_VALUE, val, + BCL_8998_VBAT_VALUE, val, VAL_CP_REG_BUF_LEN); if (ret) { pr_err("BCL register read error. err:%d\n", ret); @@ -1231,11 +1231,11 @@ static int bcl_probe(struct platform_device *pdev) return ret; } } else { - bcl_write_register(BCL_COBALT_LMH_CFG, BCL_LMH_CFG_VAL); - bcl_write_register(BCL_COBALT_BCL_CFG, BCL_CFG_VAL); - bcl_write_general_register(LMH_COBALT_INT_POL_HIGH, + bcl_write_register(BCL_8998_LMH_CFG, BCL_LMH_CFG_VAL); + bcl_write_register(BCL_8998_BCL_CFG, BCL_CFG_VAL); + bcl_write_general_register(LMH_8998_INT_POL_HIGH, bcl_perph->fg_lmh_addr, LMH_INT_VAL); - bcl_write_general_register(LMH_COBALT_INT_EN, + bcl_write_general_register(LMH_8998_INT_EN, bcl_perph->fg_lmh_addr, LMH_INT_VAL); } @@ -1320,7 +1320,7 @@ static struct of_device_id bcl_match[] = { .data = (void *) BCL_PMI8994, }, { .compatible = "qcom,msm-bcl-lmh", - .data = (void *) BCL_PMICOBALT, + .data = (void *) BCL_PMI8998, }, {}, }; diff --git a/drivers/power/qcom-charger/qpnp-fg-gen3.c b/drivers/power/qcom-charger/qpnp-fg-gen3.c index 100153280d9e..6ff0e9e45b00 100644 --- a/drivers/power/qcom-charger/qpnp-fg-gen3.c +++ b/drivers/power/qcom-charger/qpnp-fg-gen3.c @@ -25,9 +25,9 @@ #define FG_GEN3_DEV_NAME "qcom,fg-gen3" #define PERPH_SUBTYPE_REG 0x05 -#define FG_BATT_SOC_PMICOBALT 0x10 -#define FG_BATT_INFO_PMICOBALT 0x11 -#define FG_MEM_INFO_PMICOBALT 0x0D +#define FG_BATT_SOC_PMI8998 0x10 +#define FG_BATT_INFO_PMI8998 0x11 +#define FG_MEM_INFO_PMI8998 0x0D /* SRAM address and offset in ascending order */ #define CUTOFF_VOLT_WORD 5 @@ -143,7 +143,7 @@ static void fg_encode_default(struct fg_sram_param *sp, .decode = _dec, \ } \ -static struct fg_sram_param pmicobalt_v1_sram_params[] = { +static struct fg_sram_param pmi8998_v1_sram_params[] = { PARAM(BATT_SOC, BATT_SOC_WORD, BATT_SOC_OFFSET, 4, 1, 1, 0, NULL, fg_decode_default), PARAM(FULL_SOC, FULL_SOC_WORD, FULL_SOC_OFFSET, 2, 1, 1, 0, NULL, @@ -197,7 +197,7 @@ static struct fg_sram_param pmicobalt_v1_sram_params[] = { fg_encode_default, NULL), }; -static struct fg_sram_param pmicobalt_v2_sram_params[] = { +static struct fg_sram_param pmi8998_v2_sram_params[] = { PARAM(BATT_SOC, BATT_SOC_WORD, BATT_SOC_OFFSET, 4, 1, 1, 0, NULL, fg_decode_default), PARAM(FULL_SOC, FULL_SOC_WORD, FULL_SOC_OFFSET, 2, 1, 1, 0, NULL, @@ -254,7 +254,7 @@ static struct fg_sram_param pmicobalt_v2_sram_params[] = { fg_encode_default, NULL), }; -static struct fg_alg_flag pmicobalt_v1_alg_flags[] = { +static struct fg_alg_flag pmi8998_v1_alg_flags[] = { [ALG_FLAG_SOC_LT_OTG_MIN] = { .name = "SOC_LT_OTG_MIN", .bit = BIT(0), @@ -284,7 +284,7 @@ static struct fg_alg_flag pmicobalt_v1_alg_flags[] = { }, }; -static struct fg_alg_flag pmicobalt_v2_alg_flags[] = { +static struct fg_alg_flag pmi8998_v2_alg_flags[] = { [ALG_FLAG_SOC_LT_OTG_MIN] = { .name = "SOC_LT_OTG_MIN", .bit = BIT(0), @@ -545,7 +545,7 @@ static int fg_get_battery_esr(struct fg_chip *chip, int *val) return rc; } - if (chip->pmic_rev_id->rev4 < PMICOBALT_V2P0_REV4) + if (chip->pmic_rev_id->rev4 < PMI8998_V2P0_REV4) temp = ((buf[0] & ESR_MSB_MASK) << 8) | (buf[1] & ESR_LSB_MASK); else @@ -592,7 +592,7 @@ static int fg_get_battery_current(struct fg_chip *chip, int *val) return rc; } - if (chip->pmic_rev_id->rev4 < PMICOBALT_V2P0_REV4) + if (chip->pmic_rev_id->rev4 < PMI8998_V2P0_REV4) temp = buf[0] << 8 | buf[1]; else temp = buf[1] << 8 | buf[0]; @@ -619,7 +619,7 @@ static int fg_get_battery_voltage(struct fg_chip *chip, int *val) return rc; } - if (chip->pmic_rev_id->rev4 < PMICOBALT_V2P0_REV4) + if (chip->pmic_rev_id->rev4 < PMI8998_V2P0_REV4) temp = buf[0] << 8 | buf[1]; else temp = buf[1] << 8 | buf[0]; @@ -2396,7 +2396,7 @@ static int fg_hw_init(struct fg_chip *chip) } /* This SRAM register is only present in v2.0 */ - if (chip->pmic_rev_id->rev4 == PMICOBALT_V2P0_REV4 && + if (chip->pmic_rev_id->rev4 == PMI8998_V2P0_REV4 && chip->bp.float_volt_uv > 0) { fg_encode(chip->sp, FG_SRAM_FLOAT_VOLT, chip->bp.float_volt_uv / 1000, buf); @@ -2986,13 +2986,13 @@ static int fg_parse_dt(struct fg_chip *chip) chip->pmic_rev_id->pmic_subtype, chip->pmic_rev_id->rev4); switch (chip->pmic_rev_id->pmic_subtype) { - case PMICOBALT_SUBTYPE: - if (chip->pmic_rev_id->rev4 < PMICOBALT_V2P0_REV4) { - chip->sp = pmicobalt_v1_sram_params; - chip->alg_flags = pmicobalt_v1_alg_flags; - } else if (chip->pmic_rev_id->rev4 == PMICOBALT_V2P0_REV4) { - chip->sp = pmicobalt_v2_sram_params; - chip->alg_flags = pmicobalt_v2_alg_flags; + case PMI8998_SUBTYPE: + if (chip->pmic_rev_id->rev4 < PMI8998_V2P0_REV4) { + chip->sp = pmi8998_v1_sram_params; + chip->alg_flags = pmi8998_v1_alg_flags; + } else if (chip->pmic_rev_id->rev4 == PMI8998_V2P0_REV4) { + chip->sp = pmi8998_v2_sram_params; + chip->alg_flags = pmi8998_v2_alg_flags; } else { return -EINVAL; } @@ -3032,13 +3032,13 @@ static int fg_parse_dt(struct fg_chip *chip) } switch (subtype) { - case FG_BATT_SOC_PMICOBALT: + case FG_BATT_SOC_PMI8998: chip->batt_soc_base = base; break; - case FG_BATT_INFO_PMICOBALT: + case FG_BATT_INFO_PMI8998: chip->batt_info_base = base; break; - case FG_MEM_INFO_PMICOBALT: + case FG_MEM_INFO_PMI8998: chip->mem_if_base = base; break; default: diff --git a/drivers/power/qcom-charger/qpnp-qnovo.c b/drivers/power/qcom-charger/qpnp-qnovo.c index 2418b112d670..ac1c900f4771 100644 --- a/drivers/power/qcom-charger/qpnp-qnovo.c +++ b/drivers/power/qcom-charger/qpnp-qnovo.c @@ -317,8 +317,8 @@ static int qnovo_check_chg_version(struct qnovo *chip) return rc; } - if ((chip->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE) - && (chip->pmic_rev_id->rev4 < PMICOBALT_V2P0_REV4)) { + if ((chip->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) + && (chip->pmic_rev_id->rev4 < PMI8998_V2P0_REV4)) { chip->wa_flags |= QNOVO_ERASE_OFFSET_WA_BIT; chip->wa_flags |= QNOVO_NO_ERR_STS_BIT; } diff --git a/drivers/power/qcom-charger/qpnp-smb2.c b/drivers/power/qcom-charger/qpnp-smb2.c index 8248fcee341d..7accaa3a1673 100644 --- a/drivers/power/qcom-charger/qpnp-smb2.c +++ b/drivers/power/qcom-charger/qpnp-smb2.c @@ -1322,11 +1322,11 @@ static int smb2_setup_wa_flags(struct smb2 *chip) } switch (pmic_rev_id->pmic_subtype) { - case PMICOBALT_SUBTYPE: + case PMI8998_SUBTYPE: chip->chg.wa_flags |= BOOST_BACK_WA; - if (pmic_rev_id->rev4 == PMICOBALT_V1P1_REV4) /* PMI rev 1.1 */ + if (pmic_rev_id->rev4 == PMI8998_V1P1_REV4) /* PMI rev 1.1 */ chg->wa_flags |= QC_CHARGER_DETECTION_WA_BIT; - if (pmic_rev_id->rev4 == PMICOBALT_V2P0_REV4) /* PMI rev 2.0 */ + if (pmic_rev_id->rev4 == PMI8998_V2P0_REV4) /* PMI rev 2.0 */ chg->wa_flags |= TYPEC_CC2_REMOVAL_WA_BIT; break; default: diff --git a/drivers/regulator/cpr3-mmss-regulator.c b/drivers/regulator/cpr3-mmss-regulator.c index 59cbe7460750..1ac9791b467b 100644 --- a/drivers/regulator/cpr3-mmss-regulator.c +++ b/drivers/regulator/cpr3-mmss-regulator.c @@ -52,7 +52,7 @@ * min and max sensors measured at time of manufacturing * @force_highest_corner: Flag indicating that all corners must operate * at the voltage of the highest corner. This is - * applicable to MSMCOBALT only. + * applicable to MSM8998 only. * * This struct holds the values for all of the fuses read from memory. */ @@ -76,7 +76,7 @@ struct cpr3_msm8996_mmss_fuses { #define CPR3_MSM8996PRO_MMSS_FUSE_COMBO_COUNT 16 /* Fuse combos 0 - 7 map to CPR fusing revision 0 - 7 */ -#define CPR3_MSMCOBALT_MMSS_FUSE_COMBO_COUNT 8 +#define CPR3_MSM8998_MMSS_FUSE_COMBO_COUNT 8 /* * MSM8996 MMSS fuse parameter locations: @@ -128,34 +128,34 @@ static const struct cpr3_fuse_param msm8996pro_mmss_speed_bin_param[] = { {}, }; -/* MSMCOBALT MMSS fuse parameter locations: */ +/* MSM8998 MMSS fuse parameter locations: */ static const struct cpr3_fuse_param -msmcobalt_mmss_init_voltage_param[MSM8996_MMSS_FUSE_CORNERS][2] = { +msm8998_mmss_init_voltage_param[MSM8996_MMSS_FUSE_CORNERS][2] = { {{65, 39, 43}, {} }, {{65, 34, 38}, {} }, {{65, 29, 33}, {} }, {{65, 24, 28}, {} }, }; -static const struct cpr3_fuse_param msmcobalt_cpr_fusing_rev_param[] = { +static const struct cpr3_fuse_param msm8998_cpr_fusing_rev_param[] = { {39, 48, 50}, {}, }; -static const struct cpr3_fuse_param msmcobalt_cpr_limitation_param[] = { +static const struct cpr3_fuse_param msm8998_cpr_limitation_param[] = { {41, 46, 47}, {}, }; static const struct cpr3_fuse_param -msmcobalt_mmss_aging_init_quot_diff_param[] = { +msm8998_mmss_aging_init_quot_diff_param[] = { {65, 60, 63}, {66, 0, 3}, {}, }; static const struct cpr3_fuse_param -msmcobalt_mmss_offset_voltage_param[MSM8996_MMSS_FUSE_CORNERS][2] = { +msm8998_mmss_offset_voltage_param[MSM8996_MMSS_FUSE_CORNERS][2] = { {{65, 56, 59}, {} }, {{65, 52, 55}, {} }, {{65, 48, 51}, {} }, @@ -163,14 +163,14 @@ msmcobalt_mmss_offset_voltage_param[MSM8996_MMSS_FUSE_CORNERS][2] = { }; static const struct cpr3_fuse_param -msmcobalt_cpr_force_highest_corner_param[] = { +msm8998_cpr_force_highest_corner_param[] = { {100, 45, 45}, {}, }; #define MSM8996PRO_SOC_ID 4 -#define MSMCOBALT_V1_SOC_ID 5 -#define MSMCOBALT_V2_SOC_ID 6 +#define MSM8998_V1_SOC_ID 5 +#define MSM8998_V2_SOC_ID 6 /* * Some initial msm8996 parts cannot be used in a meaningful way by software. @@ -201,7 +201,7 @@ static const int msm8996pro_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { 1065000, }; -static const int msmcobalt_v1_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { +static const int msm8998_v1_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { 528000, 656000, 812000, @@ -209,14 +209,14 @@ static const int msmcobalt_v1_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { }; static const int -msmcobalt_v1_rev0_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { +msm8998_v1_rev0_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { 632000, 768000, 896000, 1032000, }; -static const int msmcobalt_v2_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { +static const int msm8998_v2_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { 516000, 628000, 752000, @@ -224,7 +224,7 @@ static const int msmcobalt_v2_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { }; static const int -msmcobalt_v2_rev0_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { +msm8998_v2_rev0_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { 616000, 740000, 828000, @@ -245,40 +245,40 @@ msmcobalt_v2_rev0_mmss_fuse_ref_volt[MSM8996_MMSS_FUSE_CORNERS] = { #define MSM8996_MMSS_AGING_SENSOR_ID 29 #define MSM8996_MMSS_AGING_BYPASS_MASK0 (GENMASK(23, 0)) -#define MSMCOBALT_MMSS_AGING_INIT_QUOT_DIFF_SCALE 1 -#define MSMCOBALT_MMSS_AGING_INIT_QUOT_DIFF_SIZE 8 +#define MSM8998_MMSS_AGING_INIT_QUOT_DIFF_SCALE 1 +#define MSM8998_MMSS_AGING_INIT_QUOT_DIFF_SIZE 8 -#define MSMCOBALT_MMSS_CPR_SENSOR_COUNT 35 +#define MSM8998_MMSS_CPR_SENSOR_COUNT 35 -#define MSMCOBALT_MMSS_AGING_SENSOR_ID 29 -#define MSMCOBALT_MMSS_AGING_BYPASS_MASK0 (GENMASK(23, 0)) +#define MSM8998_MMSS_AGING_SENSOR_ID 29 +#define MSM8998_MMSS_AGING_BYPASS_MASK0 (GENMASK(23, 0)) -#define MSMCOBALT_MMSS_MAX_TEMP_POINTS 3 -#define MSMCOBALT_MMSS_TEMP_SENSOR_ID_START 12 -#define MSMCOBALT_MMSS_TEMP_SENSOR_ID_END 13 +#define MSM8998_MMSS_MAX_TEMP_POINTS 3 +#define MSM8998_MMSS_TEMP_SENSOR_ID_START 12 +#define MSM8998_MMSS_TEMP_SENSOR_ID_END 13 /* - * Some initial msmcobalt parts cannot be operated at low voltages. The + * Some initial msm8998 parts cannot be operated at low voltages. The * open-loop voltage fuses are reused to identify these parts so that software * can properly handle the limitation. 0xF means that the next higher fuse * corner should be used. 0xE means that the next higher fuse corner which * does not have a voltage limitation should be used. */ -enum msmcobalt_cpr_partial_binning { - MSMCOBALT_CPR_PARTIAL_BINNING_NEXT_CORNER = 0xF, - MSMCOBALT_CPR_PARTIAL_BINNING_SAFE_CORNER = 0xE, +enum msm8998_cpr_partial_binning { + MSM8998_CPR_PARTIAL_BINNING_NEXT_CORNER = 0xF, + MSM8998_CPR_PARTIAL_BINNING_SAFE_CORNER = 0xE, }; /* * The partial binning open-loop voltage fuse values only apply to the lowest * two fuse corners (0 and 1, i.e. MinSVS and SVS). */ -#define MSMCOBALT_CPR_PARTIAL_BINNING_MAX_FUSE_CORNER 1 +#define MSM8998_CPR_PARTIAL_BINNING_MAX_FUSE_CORNER 1 -static inline bool cpr3_ctrl_is_msmcobalt(const struct cpr3_controller *ctrl) +static inline bool cpr3_ctrl_is_msm8998(const struct cpr3_controller *ctrl) { - return ctrl->soc_revision == MSMCOBALT_V1_SOC_ID || - ctrl->soc_revision == MSMCOBALT_V2_SOC_ID; + return ctrl->soc_revision == MSM8998_V1_SOC_ID || + ctrl->soc_revision == MSM8998_V2_SOC_ID; } /** @@ -313,8 +313,8 @@ static int cpr3_msm8996_mmss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - cpr3_ctrl_is_msmcobalt(vreg->thread->ctrl) - ? msmcobalt_cpr_fusing_rev_param + cpr3_ctrl_is_msm8998(vreg->thread->ctrl) + ? msm8998_cpr_fusing_rev_param : msm8996_cpr_fusing_rev_param, &fuse->cpr_fusing_rev); if (rc) { @@ -325,8 +325,8 @@ static int cpr3_msm8996_mmss_read_fuse_data(struct cpr3_regulator *vreg) cpr3_info(vreg, "CPR fusing revision = %llu\n", fuse->cpr_fusing_rev); rc = cpr3_read_fuse_param(base, - cpr3_ctrl_is_msmcobalt(vreg->thread->ctrl) - ? msmcobalt_cpr_limitation_param + cpr3_ctrl_is_msm8998(vreg->thread->ctrl) + ? msm8998_cpr_limitation_param : msm8996_cpr_limitation_param, &fuse->limitation); if (rc) { @@ -341,8 +341,8 @@ static int cpr3_msm8996_mmss_read_fuse_data(struct cpr3_regulator *vreg) ? "CPR disabled and no interpolation" : "none"); rc = cpr3_read_fuse_param(base, - cpr3_ctrl_is_msmcobalt(vreg->thread->ctrl) - ? msmcobalt_mmss_aging_init_quot_diff_param + cpr3_ctrl_is_msm8998(vreg->thread->ctrl) + ? msm8998_mmss_aging_init_quot_diff_param : msm8996_mmss_aging_init_quot_diff_param, &fuse->aging_init_quot_diff); if (rc) { @@ -353,8 +353,8 @@ static int cpr3_msm8996_mmss_read_fuse_data(struct cpr3_regulator *vreg) for (i = 0; i < MSM8996_MMSS_FUSE_CORNERS; i++) { rc = cpr3_read_fuse_param(base, - cpr3_ctrl_is_msmcobalt(vreg->thread->ctrl) - ? msmcobalt_mmss_init_voltage_param[i] + cpr3_ctrl_is_msm8998(vreg->thread->ctrl) + ? msm8998_mmss_init_voltage_param[i] : msm8996_mmss_init_voltage_param[i], &fuse->init_voltage[i]); if (rc) { @@ -364,8 +364,8 @@ static int cpr3_msm8996_mmss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - cpr3_ctrl_is_msmcobalt(vreg->thread->ctrl) - ? msmcobalt_mmss_offset_voltage_param[i] + cpr3_ctrl_is_msm8998(vreg->thread->ctrl) + ? msm8998_mmss_offset_voltage_param[i] : msm8996_mmss_offset_voltage_param[i], &fuse->offset_voltage[i]); if (rc) { @@ -375,9 +375,9 @@ static int cpr3_msm8996_mmss_read_fuse_data(struct cpr3_regulator *vreg) } } - if (cpr3_ctrl_is_msmcobalt(vreg->thread->ctrl)) { + if (cpr3_ctrl_is_msm8998(vreg->thread->ctrl)) { rc = cpr3_read_fuse_param(base, - msmcobalt_cpr_force_highest_corner_param, + msm8998_cpr_force_highest_corner_param, &fuse->force_highest_corner); if (rc) { cpr3_err(vreg, "Unable to read CPR force highest corner fuse, rc=%d\n", @@ -388,8 +388,8 @@ static int cpr3_msm8996_mmss_read_fuse_data(struct cpr3_regulator *vreg) cpr3_info(vreg, "Fusing requires all operation at the highest corner\n"); } - if (cpr3_ctrl_is_msmcobalt(vreg->thread->ctrl)) { - combo_max = CPR3_MSMCOBALT_MMSS_FUSE_COMBO_COUNT; + if (cpr3_ctrl_is_msm8998(vreg->thread->ctrl)) { + combo_max = CPR3_MSM8998_MMSS_FUSE_COMBO_COUNT; vreg->fuse_combo = fuse->cpr_fusing_rev; } else if (vreg->thread->ctrl->soc_revision == MSM8996PRO_SOC_ID) { combo_max = CPR3_MSM8996PRO_MMSS_FUSE_COMBO_COUNT; @@ -493,8 +493,8 @@ static int cpr3_msm8996_mmss_apply_closed_loop_offset_voltages( if (rc) goto done; - offset_param = cpr3_ctrl_is_msmcobalt(vreg->thread->ctrl) - ? msmcobalt_mmss_offset_voltage_param + offset_param = cpr3_ctrl_is_msm8998(vreg->thread->ctrl) + ? msm8998_mmss_offset_voltage_param : msm8996_mmss_offset_voltage_param; for (i = 0; i < vreg->fuse_corner_count; i++) { fuse_len = offset_param[i][0].bit_end + 1 @@ -749,7 +749,7 @@ static int cpr3_msm8996_mmss_calculate_open_loop_voltages( { struct device_node *node = vreg->of_node; struct cpr3_msm8996_mmss_fuses *fuse = vreg->platform_fuses; - bool is_msmcobalt = cpr3_ctrl_is_msmcobalt(vreg->thread->ctrl); + bool is_msm8998 = cpr3_ctrl_is_msm8998(vreg->thread->ctrl); int rc = 0; bool allow_interpolation; u64 freq_low, volt_low, freq_high, volt_high, volt_init; @@ -767,16 +767,16 @@ static int cpr3_msm8996_mmss_calculate_open_loop_voltages( goto done; } - if (vreg->thread->ctrl->soc_revision == MSMCOBALT_V2_SOC_ID + if (vreg->thread->ctrl->soc_revision == MSM8998_V2_SOC_ID && fuse->cpr_fusing_rev == 0) - ref_volt = msmcobalt_v2_rev0_mmss_fuse_ref_volt; - else if (vreg->thread->ctrl->soc_revision == MSMCOBALT_V2_SOC_ID) - ref_volt = msmcobalt_v2_mmss_fuse_ref_volt; - else if (vreg->thread->ctrl->soc_revision == MSMCOBALT_V1_SOC_ID + ref_volt = msm8998_v2_rev0_mmss_fuse_ref_volt; + else if (vreg->thread->ctrl->soc_revision == MSM8998_V2_SOC_ID) + ref_volt = msm8998_v2_mmss_fuse_ref_volt; + else if (vreg->thread->ctrl->soc_revision == MSM8998_V1_SOC_ID && fuse->cpr_fusing_rev == 0) - ref_volt = msmcobalt_v1_rev0_mmss_fuse_ref_volt; - else if (vreg->thread->ctrl->soc_revision == MSMCOBALT_V1_SOC_ID) - ref_volt = msmcobalt_v1_mmss_fuse_ref_volt; + ref_volt = msm8998_v1_rev0_mmss_fuse_ref_volt; + else if (vreg->thread->ctrl->soc_revision == MSM8998_V1_SOC_ID) + ref_volt = msm8998_v1_mmss_fuse_ref_volt; else if (vreg->thread->ctrl->soc_revision == MSM8996PRO_SOC_ID) ref_volt = msm8996pro_mmss_fuse_ref_volt; else @@ -785,16 +785,16 @@ static int cpr3_msm8996_mmss_calculate_open_loop_voltages( for (i = 0; i < vreg->fuse_corner_count; i++) { volt_init = fuse->init_voltage[i]; /* - * Handle partial binning on MSMCOBALT where the initial voltage + * Handle partial binning on MSM8998 where the initial voltage * fuse is reused as a flag for partial binning needs. Set the * open-loop voltage to the minimum possible value so that it * does not result in higher fuse corners getting forced to * higher open-loop voltages after monotonicity enforcement. */ - if (is_msmcobalt && - (volt_init == MSMCOBALT_CPR_PARTIAL_BINNING_NEXT_CORNER || - volt_init == MSMCOBALT_CPR_PARTIAL_BINNING_SAFE_CORNER) && - i <= MSMCOBALT_CPR_PARTIAL_BINNING_MAX_FUSE_CORNER) + if (is_msm8998 && + (volt_init == MSM8998_CPR_PARTIAL_BINNING_NEXT_CORNER || + volt_init == MSM8998_CPR_PARTIAL_BINNING_SAFE_CORNER) && + i <= MSM8998_CPR_PARTIAL_BINNING_MAX_FUSE_CORNER) volt_init = MSM8996_MMSS_MIN_VOLTAGE_FUSE_VAL; fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse(ref_volt[i], @@ -887,7 +887,7 @@ done: } /** - * cpr3_msmcobalt_partial_binning_override() - override the voltage and quotient + * cpr3_msm8998_partial_binning_override() - override the voltage and quotient * settings for low corners based upon the special partial binning * open-loop voltage fuse values * @vreg: Pointer to the CPR3 regulator @@ -897,17 +897,17 @@ done: * * Return: 0 on success, errno on failure */ -static int cpr3_msmcobalt_partial_binning_override(struct cpr3_regulator *vreg) +static int cpr3_msm8998_partial_binning_override(struct cpr3_regulator *vreg) { struct cpr3_msm8996_mmss_fuses *fuse = vreg->platform_fuses; - u64 next = MSMCOBALT_CPR_PARTIAL_BINNING_NEXT_CORNER; - u64 safe = MSMCOBALT_CPR_PARTIAL_BINNING_SAFE_CORNER; + u64 next = MSM8998_CPR_PARTIAL_BINNING_NEXT_CORNER; + u64 safe = MSM8998_CPR_PARTIAL_BINNING_SAFE_CORNER; u32 proc_freq; struct cpr3_corner *corner; struct cpr3_corner *safe_corner; int i, j, low, high, safe_fuse_corner, max_fuse_corner; - if (!cpr3_ctrl_is_msmcobalt(vreg->thread->ctrl)) + if (!cpr3_ctrl_is_msm8998(vreg->thread->ctrl)) return 0; /* Handle the force highest corner fuse. */ @@ -932,7 +932,7 @@ static int cpr3_msmcobalt_partial_binning_override(struct cpr3_regulator *vreg) * Allow up to the max corner which can be fused with partial * binning values. */ - max_fuse_corner = min(MSMCOBALT_CPR_PARTIAL_BINNING_MAX_FUSE_CORNER, + max_fuse_corner = min(MSM8998_CPR_PARTIAL_BINNING_MAX_FUSE_CORNER, vreg->fuse_corner_count - 2); for (i = 0; i <= max_fuse_corner; i++) { @@ -1042,15 +1042,15 @@ static int cpr3_mmss_init_aging(struct cpr3_controller *ctrl) ctrl->aging_sensor->ro_scale = aging_ro_scale; - if (cpr3_ctrl_is_msmcobalt(ctrl)) { - ctrl->aging_sensor->sensor_id = MSMCOBALT_MMSS_AGING_SENSOR_ID; + if (cpr3_ctrl_is_msm8998(ctrl)) { + ctrl->aging_sensor->sensor_id = MSM8998_MMSS_AGING_SENSOR_ID; ctrl->aging_sensor->bypass_mask[0] - = MSMCOBALT_MMSS_AGING_BYPASS_MASK0; + = MSM8998_MMSS_AGING_BYPASS_MASK0; ctrl->aging_sensor->init_quot_diff = cpr3_convert_open_loop_voltage_fuse(0, - MSMCOBALT_MMSS_AGING_INIT_QUOT_DIFF_SCALE, + MSM8998_MMSS_AGING_INIT_QUOT_DIFF_SCALE, fuse->aging_init_quot_diff, - MSMCOBALT_MMSS_AGING_INIT_QUOT_DIFF_SIZE); + MSM8998_MMSS_AGING_INIT_QUOT_DIFF_SIZE); } else { ctrl->aging_sensor->sensor_id = MSM8996_MMSS_AGING_SENSOR_ID; ctrl->aging_sensor->bypass_mask[0] @@ -1141,7 +1141,7 @@ static int cpr3_mmss_init_thread(struct cpr3_thread *thread) return rc; } - if (cpr3_ctrl_is_msmcobalt(thread->ctrl)) { + if (cpr3_ctrl_is_msm8998(thread->ctrl)) { rc = cpr4_parse_core_count_temp_voltage_adj(vreg, false); if (rc) { cpr3_err(vreg, "unable to parse temperature based voltage adjustments, rc=%d\n", @@ -1150,7 +1150,7 @@ static int cpr3_mmss_init_thread(struct cpr3_thread *thread) } } - rc = cpr3_msmcobalt_partial_binning_override(vreg); + rc = cpr3_msm8998_partial_binning_override(vreg); if (rc) { cpr3_err(vreg, "unable to override CPR parameters based on partial binning fuse values, rc=%d\n", rc); @@ -1179,9 +1179,9 @@ static int cpr4_mmss_parse_temp_adj_properties(struct cpr3_controller *ctrl) temp_point_count = len / sizeof(u32); if (temp_point_count <= 0 - || temp_point_count > MSMCOBALT_MMSS_MAX_TEMP_POINTS) { + || temp_point_count > MSM8998_MMSS_MAX_TEMP_POINTS) { cpr3_err(ctrl, "invalid number of temperature points %d > %d (max)\n", - temp_point_count, MSMCOBALT_MMSS_MAX_TEMP_POINTS); + temp_point_count, MSM8998_MMSS_MAX_TEMP_POINTS); return -EINVAL; } @@ -1218,8 +1218,8 @@ static int cpr4_mmss_parse_temp_adj_properties(struct cpr3_controller *ctrl) return -EINVAL; } - ctrl->temp_sensor_id_start = MSMCOBALT_MMSS_TEMP_SENSOR_ID_START; - ctrl->temp_sensor_id_end = MSMCOBALT_MMSS_TEMP_SENSOR_ID_END; + ctrl->temp_sensor_id_start = MSM8998_MMSS_TEMP_SENSOR_ID_START; + ctrl->temp_sensor_id_end = MSM8998_MMSS_TEMP_SENSOR_ID_END; ctrl->allow_temp_adj = true; return rc; @@ -1244,14 +1244,14 @@ static int cpr3_mmss_init_controller(struct cpr3_controller *ctrl) return rc; } - if (cpr3_ctrl_is_msmcobalt(ctrl)) { + if (cpr3_ctrl_is_msm8998(ctrl)) { rc = cpr4_mmss_parse_temp_adj_properties(ctrl); if (rc) return rc; } - ctrl->sensor_count = cpr3_ctrl_is_msmcobalt(ctrl) - ? MSMCOBALT_MMSS_CPR_SENSOR_COUNT + ctrl->sensor_count = cpr3_ctrl_is_msm8998(ctrl) + ? MSM8998_MMSS_CPR_SENSOR_COUNT : MSM8996_MMSS_CPR_SENSOR_COUNT; /* @@ -1264,7 +1264,7 @@ static int cpr3_mmss_init_controller(struct cpr3_controller *ctrl) return -ENOMEM; ctrl->cpr_clock_rate = MSM8996_MMSS_CPR_CLOCK_RATE; - ctrl->ctrl_type = cpr3_ctrl_is_msmcobalt(ctrl) + ctrl->ctrl_type = cpr3_ctrl_is_msm8998(ctrl) ? CPR_CTRL_TYPE_CPR4 : CPR_CTRL_TYPE_CPR3; if (ctrl->ctrl_type == CPR_CTRL_TYPE_CPR4) { @@ -1281,8 +1281,8 @@ static int cpr3_mmss_init_controller(struct cpr3_controller *ctrl) ctrl->iface_clk = devm_clk_get(ctrl->dev, "iface_clk"); if (IS_ERR(ctrl->iface_clk)) { rc = PTR_ERR(ctrl->iface_clk); - if (cpr3_ctrl_is_msmcobalt(ctrl)) { - /* iface_clk is optional for msmcobalt */ + if (cpr3_ctrl_is_msm8998(ctrl)) { + /* iface_clk is optional for msm8998 */ ctrl->iface_clk = NULL; } else if (rc == -EPROBE_DEFER) { return rc; @@ -1343,16 +1343,16 @@ static struct of_device_id cpr_regulator_match_table[] = { .data = (void *)(uintptr_t)MSM8996PRO_SOC_ID, }, { - .compatible = "qcom,cpr4-msmcobalt-v1-mmss-regulator", - .data = (void *)(uintptr_t)MSMCOBALT_V1_SOC_ID, + .compatible = "qcom,cpr4-msm8998-v1-mmss-regulator", + .data = (void *)(uintptr_t)MSM8998_V1_SOC_ID, }, { - .compatible = "qcom,cpr4-msmcobalt-v2-mmss-regulator", - .data = (void *)(uintptr_t)MSMCOBALT_V2_SOC_ID, + .compatible = "qcom,cpr4-msm8998-v2-mmss-regulator", + .data = (void *)(uintptr_t)MSM8998_V2_SOC_ID, }, { - .compatible = "qcom,cpr4-msmcobalt-mmss-regulator", - .data = (void *)(uintptr_t)MSMCOBALT_V2_SOC_ID, + .compatible = "qcom,cpr4-msm8998-mmss-regulator", + .data = (void *)(uintptr_t)MSM8998_V2_SOC_ID, }, {} }; diff --git a/drivers/regulator/cprh-kbss-regulator.c b/drivers/regulator/cprh-kbss-regulator.c index 5661ae75843c..2608cc4a430a 100644 --- a/drivers/regulator/cprh-kbss-regulator.c +++ b/drivers/regulator/cprh-kbss-regulator.c @@ -35,10 +35,10 @@ #include "cpr3-regulator.h" -#define MSMCOBALT_KBSS_FUSE_CORNERS 4 +#define MSM8998_KBSS_FUSE_CORNERS 4 /** - * struct cprh_msmcobalt_kbss_fuses - KBSS specific fuse data for MSMCOBALT + * struct cprh_msm8998_kbss_fuses - KBSS specific fuse data for MSM8998 * @ro_sel: Ring oscillator select fuse parameter value for each * fuse corner * @init_voltage: Initial (i.e. open-loop) voltage fuse parameter value @@ -53,17 +53,17 @@ * @cpr_fusing_rev: CPR fusing revision fuse parameter value * @force_highest_corner: Flag indicating that all corners must operate * at the voltage of the highest corner. This is - * applicable to MSMCOBALT only. + * applicable to MSM8998 only. * @aging_init_quot_diff: Initial quotient difference between CPR aging * min and max sensors measured at time of manufacturing * * This struct holds the values for all of the fuses read from memory. */ -struct cprh_msmcobalt_kbss_fuses { - u64 ro_sel[MSMCOBALT_KBSS_FUSE_CORNERS]; - u64 init_voltage[MSMCOBALT_KBSS_FUSE_CORNERS]; - u64 target_quot[MSMCOBALT_KBSS_FUSE_CORNERS]; - u64 quot_offset[MSMCOBALT_KBSS_FUSE_CORNERS]; +struct cprh_msm8998_kbss_fuses { + u64 ro_sel[MSM8998_KBSS_FUSE_CORNERS]; + u64 init_voltage[MSM8998_KBSS_FUSE_CORNERS]; + u64 target_quot[MSM8998_KBSS_FUSE_CORNERS]; + u64 quot_offset[MSM8998_KBSS_FUSE_CORNERS]; u64 speed_bin; u64 cpr_fusing_rev; u64 force_highest_corner; @@ -74,35 +74,35 @@ struct cprh_msmcobalt_kbss_fuses { * Fuse combos 0 - 7 map to CPR fusing revision 0 - 7 with speed bin fuse = 0. * Fuse combos 8 - 15 map to CPR fusing revision 0 - 7 with speed bin fuse = 1. */ -#define CPRH_MSMCOBALT_KBSS_FUSE_COMBO_COUNT 16 +#define CPRH_MSM8998_KBSS_FUSE_COMBO_COUNT 16 /* * Constants which define the name of each fuse corner. */ -enum cprh_msmcobalt_kbss_fuse_corner { - CPRH_MSMCOBALT_KBSS_FUSE_CORNER_LOWSVS = 0, - CPRH_MSMCOBALT_KBSS_FUSE_CORNER_SVS = 1, - CPRH_MSMCOBALT_KBSS_FUSE_CORNER_NOM = 2, - CPRH_MSMCOBALT_KBSS_FUSE_CORNER_TURBO_L1 = 3, +enum cprh_msm8998_kbss_fuse_corner { + CPRH_MSM8998_KBSS_FUSE_CORNER_LOWSVS = 0, + CPRH_MSM8998_KBSS_FUSE_CORNER_SVS = 1, + CPRH_MSM8998_KBSS_FUSE_CORNER_NOM = 2, + CPRH_MSM8998_KBSS_FUSE_CORNER_TURBO_L1 = 3, }; -static const char * const cprh_msmcobalt_kbss_fuse_corner_name[] = { - [CPRH_MSMCOBALT_KBSS_FUSE_CORNER_LOWSVS] = "LowSVS", - [CPRH_MSMCOBALT_KBSS_FUSE_CORNER_SVS] = "SVS", - [CPRH_MSMCOBALT_KBSS_FUSE_CORNER_NOM] = "NOM", - [CPRH_MSMCOBALT_KBSS_FUSE_CORNER_TURBO_L1] = "TURBO_L1", +static const char * const cprh_msm8998_kbss_fuse_corner_name[] = { + [CPRH_MSM8998_KBSS_FUSE_CORNER_LOWSVS] = "LowSVS", + [CPRH_MSM8998_KBSS_FUSE_CORNER_SVS] = "SVS", + [CPRH_MSM8998_KBSS_FUSE_CORNER_NOM] = "NOM", + [CPRH_MSM8998_KBSS_FUSE_CORNER_TURBO_L1] = "TURBO_L1", }; /* KBSS cluster IDs */ -#define MSMCOBALT_KBSS_POWER_CLUSTER_ID 0 -#define MSMCOBALT_KBSS_PERFORMANCE_CLUSTER_ID 1 +#define MSM8998_KBSS_POWER_CLUSTER_ID 0 +#define MSM8998_KBSS_PERFORMANCE_CLUSTER_ID 1 /* KBSS controller IDs */ -#define MSMCOBALT_KBSS_MIN_CONTROLLER_ID 0 -#define MSMCOBALT_KBSS_MAX_CONTROLLER_ID 1 +#define MSM8998_KBSS_MIN_CONTROLLER_ID 0 +#define MSM8998_KBSS_MAX_CONTROLLER_ID 1 /* - * MSMCOBALT KBSS fuse parameter locations: + * MSM8998 KBSS fuse parameter locations: * * Structs are organized with the following dimensions: * Outer: 0 or 1 for power or performance cluster @@ -116,14 +116,14 @@ static const char * const cprh_msmcobalt_kbss_fuse_corner_name[] = { * */ static const struct cpr3_fuse_param -msmcobalt_kbss_ro_sel_param[2][MSMCOBALT_KBSS_FUSE_CORNERS][2] = { - [MSMCOBALT_KBSS_POWER_CLUSTER_ID] = { +msm8998_kbss_ro_sel_param[2][MSM8998_KBSS_FUSE_CORNERS][2] = { + [MSM8998_KBSS_POWER_CLUSTER_ID] = { {{67, 12, 15}, {} }, {{67, 8, 11}, {} }, {{67, 4, 7}, {} }, {{67, 0, 3}, {} }, }, - [MSMCOBALT_KBSS_PERFORMANCE_CLUSTER_ID] = { + [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { {{69, 26, 29}, {} }, {{69, 22, 25}, {} }, {{69, 18, 21}, {} }, @@ -132,14 +132,14 @@ msmcobalt_kbss_ro_sel_param[2][MSMCOBALT_KBSS_FUSE_CORNERS][2] = { }; static const struct cpr3_fuse_param -msmcobalt_kbss_init_voltage_param[2][MSMCOBALT_KBSS_FUSE_CORNERS][2] = { - [MSMCOBALT_KBSS_POWER_CLUSTER_ID] = { +msm8998_kbss_init_voltage_param[2][MSM8998_KBSS_FUSE_CORNERS][2] = { + [MSM8998_KBSS_POWER_CLUSTER_ID] = { {{67, 34, 39}, {} }, {{67, 28, 33}, {} }, {{67, 22, 27}, {} }, {{67, 16, 21}, {} }, }, - [MSMCOBALT_KBSS_PERFORMANCE_CLUSTER_ID] = { + [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { {{69, 48, 53}, {} }, {{69, 42, 47}, {} }, {{69, 36, 41}, {} }, @@ -148,14 +148,14 @@ msmcobalt_kbss_init_voltage_param[2][MSMCOBALT_KBSS_FUSE_CORNERS][2] = { }; static const struct cpr3_fuse_param -msmcobalt_kbss_target_quot_param[2][MSMCOBALT_KBSS_FUSE_CORNERS][3] = { - [MSMCOBALT_KBSS_POWER_CLUSTER_ID] = { +msm8998_kbss_target_quot_param[2][MSM8998_KBSS_FUSE_CORNERS][3] = { + [MSM8998_KBSS_POWER_CLUSTER_ID] = { {{68, 18, 29}, {} }, {{68, 6, 17}, {} }, {{67, 58, 63}, {68, 0, 5} }, {{67, 46, 57}, {} }, }, - [MSMCOBALT_KBSS_PERFORMANCE_CLUSTER_ID] = { + [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { {{70, 32, 43}, {} }, {{70, 20, 31}, {} }, {{70, 8, 19}, {} }, @@ -164,14 +164,14 @@ msmcobalt_kbss_target_quot_param[2][MSMCOBALT_KBSS_FUSE_CORNERS][3] = { }; static const struct cpr3_fuse_param -msmcobalt_kbss_quot_offset_param[2][MSMCOBALT_KBSS_FUSE_CORNERS][3] = { - [MSMCOBALT_KBSS_POWER_CLUSTER_ID] = { +msm8998_kbss_quot_offset_param[2][MSM8998_KBSS_FUSE_CORNERS][3] = { + [MSM8998_KBSS_POWER_CLUSTER_ID] = { {{} }, {{68, 63, 63}, {69, 0, 5}, {} }, {{68, 56, 62}, {} }, {{68, 49, 55}, {} }, }, - [MSMCOBALT_KBSS_PERFORMANCE_CLUSTER_ID] = { + [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { {{} }, {{71, 13, 15}, {71, 21, 24}, {} }, {{71, 6, 12}, {} }, @@ -179,39 +179,39 @@ msmcobalt_kbss_quot_offset_param[2][MSMCOBALT_KBSS_FUSE_CORNERS][3] = { }, }; -static const struct cpr3_fuse_param msmcobalt_cpr_fusing_rev_param[] = { +static const struct cpr3_fuse_param msm8998_cpr_fusing_rev_param[] = { {39, 51, 53}, {}, }; -static const struct cpr3_fuse_param msmcobalt_kbss_speed_bin_param[] = { +static const struct cpr3_fuse_param msm8998_kbss_speed_bin_param[] = { {38, 29, 31}, {}, }; static const struct cpr3_fuse_param -msmcobalt_cpr_force_highest_corner_param[] = { +msm8998_cpr_force_highest_corner_param[] = { {100, 45, 45}, {}, }; static const struct cpr3_fuse_param -msmcobalt_kbss_aging_init_quot_diff_param[2][2] = { - [MSMCOBALT_KBSS_POWER_CLUSTER_ID] = { +msm8998_kbss_aging_init_quot_diff_param[2][2] = { + [MSM8998_KBSS_POWER_CLUSTER_ID] = { {69, 6, 13}, {}, }, - [MSMCOBALT_KBSS_PERFORMANCE_CLUSTER_ID] = { + [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { {71, 25, 32}, {}, }, }; /* - * Open loop voltage fuse reference voltages in microvolts for MSMCOBALT v1 + * Open loop voltage fuse reference voltages in microvolts for MSM8998 v1 */ static const int -msmcobalt_v1_kbss_fuse_ref_volt[MSMCOBALT_KBSS_FUSE_CORNERS] = { +msm8998_v1_kbss_fuse_ref_volt[MSM8998_KBSS_FUSE_CORNERS] = { 696000, 768000, 896000, @@ -219,17 +219,17 @@ msmcobalt_v1_kbss_fuse_ref_volt[MSMCOBALT_KBSS_FUSE_CORNERS] = { }; /* - * Open loop voltage fuse reference voltages in microvolts for MSMCOBALT v2 + * Open loop voltage fuse reference voltages in microvolts for MSM8998 v2 */ static const int -msmcobalt_v2_kbss_fuse_ref_volt[2][MSMCOBALT_KBSS_FUSE_CORNERS] = { - [MSMCOBALT_KBSS_POWER_CLUSTER_ID] = { +msm8998_v2_kbss_fuse_ref_volt[2][MSM8998_KBSS_FUSE_CORNERS] = { + [MSM8998_KBSS_POWER_CLUSTER_ID] = { 688000, 756000, 828000, 1056000, }, - [MSMCOBALT_KBSS_PERFORMANCE_CLUSTER_ID] = { + [MSM8998_KBSS_PERFORMANCE_CLUSTER_ID] = { 756000, 756000, 828000, @@ -237,55 +237,55 @@ msmcobalt_v2_kbss_fuse_ref_volt[2][MSMCOBALT_KBSS_FUSE_CORNERS] = { }, }; -#define MSMCOBALT_KBSS_FUSE_STEP_VOLT 10000 -#define MSMCOBALT_KBSS_VOLTAGE_FUSE_SIZE 6 -#define MSMCOBALT_KBSS_QUOT_OFFSET_SCALE 5 -#define MSMCOBALT_KBSS_AGING_INIT_QUOT_DIFF_SIZE 8 -#define MSMCOBALT_KBSS_AGING_INIT_QUOT_DIFF_SCALE 1 +#define MSM8998_KBSS_FUSE_STEP_VOLT 10000 +#define MSM8998_KBSS_VOLTAGE_FUSE_SIZE 6 +#define MSM8998_KBSS_QUOT_OFFSET_SCALE 5 +#define MSM8998_KBSS_AGING_INIT_QUOT_DIFF_SIZE 8 +#define MSM8998_KBSS_AGING_INIT_QUOT_DIFF_SCALE 1 -#define MSMCOBALT_KBSS_POWER_CPR_SENSOR_COUNT 6 -#define MSMCOBALT_KBSS_PERFORMANCE_CPR_SENSOR_COUNT 9 +#define MSM8998_KBSS_POWER_CPR_SENSOR_COUNT 6 +#define MSM8998_KBSS_PERFORMANCE_CPR_SENSOR_COUNT 9 -#define MSMCOBALT_KBSS_CPR_CLOCK_RATE 19200000 +#define MSM8998_KBSS_CPR_CLOCK_RATE 19200000 -#define MSMCOBALT_KBSS_MAX_CORNER_BAND_COUNT 4 -#define MSMCOBALT_KBSS_MAX_CORNER_COUNT 40 +#define MSM8998_KBSS_MAX_CORNER_BAND_COUNT 4 +#define MSM8998_KBSS_MAX_CORNER_COUNT 40 -#define MSMCOBALT_KBSS_CPR_SDELTA_CORE_COUNT 4 +#define MSM8998_KBSS_CPR_SDELTA_CORE_COUNT 4 -#define MSMCOBALT_KBSS_MAX_TEMP_POINTS 3 -#define MSMCOBALT_KBSS_POWER_TEMP_SENSOR_ID_START 1 -#define MSMCOBALT_KBSS_POWER_TEMP_SENSOR_ID_END 5 -#define MSMCOBALT_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START 6 -#define MSMCOBALT_KBSS_PERFORMANCE_TEMP_SENSOR_ID_END 10 +#define MSM8998_KBSS_MAX_TEMP_POINTS 3 +#define MSM8998_KBSS_POWER_TEMP_SENSOR_ID_START 1 +#define MSM8998_KBSS_POWER_TEMP_SENSOR_ID_END 5 +#define MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START 6 +#define MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_END 10 -#define MSMCOBALT_KBSS_POWER_AGING_SENSOR_ID 0 -#define MSMCOBALT_KBSS_POWER_AGING_BYPASS_MASK0 0 +#define MSM8998_KBSS_POWER_AGING_SENSOR_ID 0 +#define MSM8998_KBSS_POWER_AGING_BYPASS_MASK0 0 -#define MSMCOBALT_KBSS_PERFORMANCE_AGING_SENSOR_ID 0 -#define MSMCOBALT_KBSS_PERFORMANCE_AGING_BYPASS_MASK0 0 +#define MSM8998_KBSS_PERFORMANCE_AGING_SENSOR_ID 0 +#define MSM8998_KBSS_PERFORMANCE_AGING_BYPASS_MASK0 0 /** - * cprh_msmcobalt_kbss_read_fuse_data() - load KBSS specific fuse parameter values + * cprh_msm8998_kbss_read_fuse_data() - load KBSS specific fuse parameter values * @vreg: Pointer to the CPR3 regulator * - * This function allocates a cprh_msmcobalt_kbss_fuses struct, fills it with + * This function allocates a cprh_msm8998_kbss_fuses struct, fills it with * values read out of hardware fuses, and finally copies common fuse values * into the CPR3 regulator struct. * * Return: 0 on success, errno on failure */ -static int cprh_msmcobalt_kbss_read_fuse_data(struct cpr3_regulator *vreg) +static int cprh_msm8998_kbss_read_fuse_data(struct cpr3_regulator *vreg) { void __iomem *base = vreg->thread->ctrl->fuse_base; - struct cprh_msmcobalt_kbss_fuses *fuse; + struct cprh_msm8998_kbss_fuses *fuse; int i, id, rc; fuse = devm_kzalloc(vreg->thread->ctrl->dev, sizeof(*fuse), GFP_KERNEL); if (!fuse) return -ENOMEM; - rc = cpr3_read_fuse_param(base, msmcobalt_kbss_speed_bin_param, + rc = cpr3_read_fuse_param(base, msm8998_kbss_speed_bin_param, &fuse->speed_bin); if (rc) { cpr3_err(vreg, "Unable to read speed bin fuse, rc=%d\n", rc); @@ -293,7 +293,7 @@ static int cprh_msmcobalt_kbss_read_fuse_data(struct cpr3_regulator *vreg) } cpr3_info(vreg, "speed bin = %llu\n", fuse->speed_bin); - rc = cpr3_read_fuse_param(base, msmcobalt_cpr_fusing_rev_param, + rc = cpr3_read_fuse_param(base, msm8998_cpr_fusing_rev_param, &fuse->cpr_fusing_rev); if (rc) { cpr3_err(vreg, "Unable to read CPR fusing revision fuse, rc=%d\n", @@ -304,9 +304,9 @@ static int cprh_msmcobalt_kbss_read_fuse_data(struct cpr3_regulator *vreg) id = vreg->thread->ctrl->ctrl_id; - for (i = 0; i < MSMCOBALT_KBSS_FUSE_CORNERS; i++) { + for (i = 0; i < MSM8998_KBSS_FUSE_CORNERS; i++) { rc = cpr3_read_fuse_param(base, - msmcobalt_kbss_init_voltage_param[id][i], + msm8998_kbss_init_voltage_param[id][i], &fuse->init_voltage[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d initial voltage fuse, rc=%d\n", @@ -315,7 +315,7 @@ static int cprh_msmcobalt_kbss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msmcobalt_kbss_target_quot_param[id][i], + msm8998_kbss_target_quot_param[id][i], &fuse->target_quot[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d target quotient fuse, rc=%d\n", @@ -324,7 +324,7 @@ static int cprh_msmcobalt_kbss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msmcobalt_kbss_ro_sel_param[id][i], + msm8998_kbss_ro_sel_param[id][i], &fuse->ro_sel[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d RO select fuse, rc=%d\n", @@ -333,7 +333,7 @@ static int cprh_msmcobalt_kbss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msmcobalt_kbss_quot_offset_param[id][i], + msm8998_kbss_quot_offset_param[id][i], &fuse->quot_offset[i]); if (rc) { cpr3_err(vreg, "Unable to read fuse-corner %d quotient offset fuse, rc=%d\n", @@ -344,7 +344,7 @@ static int cprh_msmcobalt_kbss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msmcobalt_kbss_aging_init_quot_diff_param[id], + msm8998_kbss_aging_init_quot_diff_param[id], &fuse->aging_init_quot_diff); if (rc) { cpr3_err(vreg, "Unable to read aging initial quotient difference fuse, rc=%d\n", @@ -353,7 +353,7 @@ static int cprh_msmcobalt_kbss_read_fuse_data(struct cpr3_regulator *vreg) } rc = cpr3_read_fuse_param(base, - msmcobalt_cpr_force_highest_corner_param, + msm8998_cpr_force_highest_corner_param, &fuse->force_highest_corner); if (rc) { cpr3_err(vreg, "Unable to read CPR force highest corner fuse, rc=%d\n", @@ -365,7 +365,7 @@ static int cprh_msmcobalt_kbss_read_fuse_data(struct cpr3_regulator *vreg) cpr3_info(vreg, "Fusing requires all operation at the highest corner\n"); vreg->fuse_combo = fuse->cpr_fusing_rev + 8 * fuse->speed_bin; - if (vreg->fuse_combo >= CPRH_MSMCOBALT_KBSS_FUSE_COMBO_COUNT) { + if (vreg->fuse_combo >= CPRH_MSM8998_KBSS_FUSE_COMBO_COUNT) { cpr3_err(vreg, "invalid CPR fuse combo = %d found\n", vreg->fuse_combo); return -EINVAL; @@ -373,7 +373,7 @@ static int cprh_msmcobalt_kbss_read_fuse_data(struct cpr3_regulator *vreg) vreg->speed_bin_fuse = fuse->speed_bin; vreg->cpr_rev_fuse = fuse->cpr_fusing_rev; - vreg->fuse_corner_count = MSMCOBALT_KBSS_FUSE_CORNERS; + vreg->fuse_corner_count = MSM8998_KBSS_FUSE_CORNERS; vreg->platform_fuses = fuse; return 0; @@ -397,13 +397,13 @@ static int cprh_kbss_parse_corner_data(struct cpr3_regulator *vreg) } /* - * A total of MSMCOBALT_KBSS_MAX_CORNER_COUNT - 1 corners + * A total of MSM8998_KBSS_MAX_CORNER_COUNT - 1 corners * may be specified in device tree as an additional corner * must be allocated to correspond to the APM crossover voltage. */ - if (vreg->corner_count > MSMCOBALT_KBSS_MAX_CORNER_COUNT - 1) { + if (vreg->corner_count > MSM8998_KBSS_MAX_CORNER_COUNT - 1) { cpr3_err(vreg, "corner count %d exceeds supported maximum %d\n", - vreg->corner_count, MSMCOBALT_KBSS_MAX_CORNER_COUNT - 1); + vreg->corner_count, MSM8998_KBSS_MAX_CORNER_COUNT - 1); return -EINVAL; } @@ -411,7 +411,7 @@ static int cprh_kbss_parse_corner_data(struct cpr3_regulator *vreg) } /** - * cprh_msmcobalt_kbss_calculate_open_loop_voltages() - calculate the open-loop + * cprh_msm8998_kbss_calculate_open_loop_voltages() - calculate the open-loop * voltage for each corner of a CPR3 regulator * @vreg: Pointer to the CPR3 regulator * @@ -427,11 +427,11 @@ static int cprh_kbss_parse_corner_data(struct cpr3_regulator *vreg) * * Return: 0 on success, errno on failure */ -static int cprh_msmcobalt_kbss_calculate_open_loop_voltages( +static int cprh_msm8998_kbss_calculate_open_loop_voltages( struct cpr3_regulator *vreg) { struct device_node *node = vreg->of_node; - struct cprh_msmcobalt_kbss_fuses *fuse = vreg->platform_fuses; + struct cprh_msm8998_kbss_fuses *fuse = vreg->platform_fuses; int i, j, soc_revision, id, rc = 0; bool allow_interpolation; u64 freq_low, volt_low, freq_high, volt_high; @@ -451,19 +451,19 @@ static int cprh_msmcobalt_kbss_calculate_open_loop_voltages( id = vreg->thread->ctrl->ctrl_id; soc_revision = vreg->thread->ctrl->soc_revision; if (soc_revision == 1) - ref_volt = msmcobalt_v1_kbss_fuse_ref_volt; + ref_volt = msm8998_v1_kbss_fuse_ref_volt; else - ref_volt = msmcobalt_v2_kbss_fuse_ref_volt[id]; + ref_volt = msm8998_v2_kbss_fuse_ref_volt[id]; for (i = 0; i < vreg->fuse_corner_count; i++) { fuse_volt[i] = cpr3_convert_open_loop_voltage_fuse( ref_volt[i], - MSMCOBALT_KBSS_FUSE_STEP_VOLT, fuse->init_voltage[i], - MSMCOBALT_KBSS_VOLTAGE_FUSE_SIZE); + MSM8998_KBSS_FUSE_STEP_VOLT, fuse->init_voltage[i], + MSM8998_KBSS_VOLTAGE_FUSE_SIZE); /* Log fused open-loop voltage values for debugging purposes. */ cpr3_info(vreg, "fused %8s: open-loop=%7d uV\n", - cprh_msmcobalt_kbss_fuse_corner_name[i], + cprh_msm8998_kbss_fuse_corner_name[i], fuse_volt[i]); } @@ -547,7 +547,7 @@ done: } /** - * cprh_msmcobalt_partial_binning_override() - override the voltage and quotient + * cprh_msm8998_partial_binning_override() - override the voltage and quotient * settings for low corners based upon special partial binning * fuse values * @@ -559,9 +559,9 @@ done: * * Return: 0 on success, errno on failure */ -static int cprh_msmcobalt_partial_binning_override(struct cpr3_regulator *vreg) +static int cprh_msm8998_partial_binning_override(struct cpr3_regulator *vreg) { - struct cprh_msmcobalt_kbss_fuses *fuse = vreg->platform_fuses; + struct cprh_msm8998_kbss_fuses *fuse = vreg->platform_fuses; struct cpr3_corner *corner; struct cpr4_sdelta *sdelta; int i; @@ -657,11 +657,11 @@ static int cprh_kbss_parse_core_count_temp_adj_properties( kfree(combo_corner_bands); if (vreg->corner_band_count <= 0 || - vreg->corner_band_count > MSMCOBALT_KBSS_MAX_CORNER_BAND_COUNT || + vreg->corner_band_count > MSM8998_KBSS_MAX_CORNER_BAND_COUNT || vreg->corner_band_count > vreg->corner_count) { cpr3_err(vreg, "invalid corner band count %d > %d (max) for %d corners\n", vreg->corner_band_count, - MSMCOBALT_KBSS_MAX_CORNER_BAND_COUNT, + MSM8998_KBSS_MAX_CORNER_BAND_COUNT, vreg->corner_count); return -EINVAL; } @@ -759,9 +759,9 @@ static int cprh_kbss_parse_core_count_temp_adj_properties( temp_point_count = len / sizeof(u32); if (temp_point_count <= 0 || temp_point_count > - MSMCOBALT_KBSS_MAX_TEMP_POINTS) { + MSM8998_KBSS_MAX_TEMP_POINTS) { cpr3_err(ctrl, "invalid number of temperature points %d > %d (max)\n", - temp_point_count, MSMCOBALT_KBSS_MAX_TEMP_POINTS); + temp_point_count, MSM8998_KBSS_MAX_TEMP_POINTS); rc = -EINVAL; goto free_temp; } @@ -810,13 +810,13 @@ static int cprh_kbss_parse_core_count_temp_adj_properties( } ctrl->temp_sensor_id_start = ctrl->ctrl_id == - MSMCOBALT_KBSS_POWER_CLUSTER_ID - ? MSMCOBALT_KBSS_POWER_TEMP_SENSOR_ID_START : - MSMCOBALT_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START; + MSM8998_KBSS_POWER_CLUSTER_ID + ? MSM8998_KBSS_POWER_TEMP_SENSOR_ID_START : + MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START; ctrl->temp_sensor_id_end = ctrl->ctrl_id == - MSMCOBALT_KBSS_POWER_CLUSTER_ID - ? MSMCOBALT_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START : - MSMCOBALT_KBSS_PERFORMANCE_TEMP_SENSOR_ID_END; + MSM8998_KBSS_POWER_CLUSTER_ID + ? MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_START : + MSM8998_KBSS_PERFORMANCE_TEMP_SENSOR_ID_END; ctrl->allow_temp_adj = true; return 0; @@ -866,7 +866,7 @@ static int cprh_kbss_apm_crossover_as_corner(struct cpr3_regulator *vreg) } /** - * cprh_msmcobalt_kbss_set_no_interpolation_quotients() - use the fused target + * cprh_msm8998_kbss_set_no_interpolation_quotients() - use the fused target * quotient values for lower frequencies. * @vreg: Pointer to the CPR3 regulator * @volt_adjust: Pointer to array of per-corner closed-loop adjustment @@ -878,11 +878,11 @@ static int cprh_kbss_apm_crossover_as_corner(struct cpr3_regulator *vreg) * * Return: 0 on success, errno on failure */ -static int cprh_msmcobalt_kbss_set_no_interpolation_quotients( +static int cprh_msm8998_kbss_set_no_interpolation_quotients( struct cpr3_regulator *vreg, int *volt_adjust, int *volt_adjust_fuse, int *ro_scale) { - struct cprh_msmcobalt_kbss_fuses *fuse = vreg->platform_fuses; + struct cprh_msm8998_kbss_fuses *fuse = vreg->platform_fuses; u32 quot, ro; int quot_adjust; int i, fuse_corner; @@ -909,7 +909,7 @@ static int cprh_msmcobalt_kbss_set_no_interpolation_quotients( } /** - * cprh_msmcobalt_kbss_calculate_target_quotients() - calculate the CPR target + * cprh_msm8998_kbss_calculate_target_quotients() - calculate the CPR target * quotient for each corner of a CPR3 regulator * @vreg: Pointer to the CPR3 regulator * @@ -925,10 +925,10 @@ static int cprh_msmcobalt_kbss_set_no_interpolation_quotients( * * Return: 0 on success, errno on failure */ -static int cprh_msmcobalt_kbss_calculate_target_quotients( +static int cprh_msm8998_kbss_calculate_target_quotients( struct cpr3_regulator *vreg) { - struct cprh_msmcobalt_kbss_fuses *fuse = vreg->platform_fuses; + struct cprh_msm8998_kbss_fuses *fuse = vreg->platform_fuses; int rc; bool allow_interpolation; u64 freq_low, freq_high, prev_quot; @@ -941,15 +941,15 @@ static int cprh_msmcobalt_kbss_calculate_target_quotients( /* Log fused quotient values for debugging purposes. */ cpr3_info(vreg, "fused LowSVS: quot[%2llu]=%4llu\n", - fuse->ro_sel[CPRH_MSMCOBALT_KBSS_FUSE_CORNER_LOWSVS], - fuse->target_quot[CPRH_MSMCOBALT_KBSS_FUSE_CORNER_LOWSVS]); - for (i = CPRH_MSMCOBALT_KBSS_FUSE_CORNER_SVS; - i <= CPRH_MSMCOBALT_KBSS_FUSE_CORNER_TURBO_L1; i++) + fuse->ro_sel[CPRH_MSM8998_KBSS_FUSE_CORNER_LOWSVS], + fuse->target_quot[CPRH_MSM8998_KBSS_FUSE_CORNER_LOWSVS]); + for (i = CPRH_MSM8998_KBSS_FUSE_CORNER_SVS; + i <= CPRH_MSM8998_KBSS_FUSE_CORNER_TURBO_L1; i++) cpr3_info(vreg, "fused %8s: quot[%2llu]=%4llu, quot_offset[%2llu]=%4llu\n", - cprh_msmcobalt_kbss_fuse_corner_name[i], + cprh_msm8998_kbss_fuse_corner_name[i], fuse->ro_sel[i], fuse->target_quot[i], fuse->ro_sel[i], fuse->quot_offset[i] * - MSMCOBALT_KBSS_QUOT_OFFSET_SCALE); + MSM8998_KBSS_QUOT_OFFSET_SCALE); allow_interpolation = of_property_read_bool(vreg->of_node, "qcom,allow-quotient-interpolation"); @@ -982,7 +982,7 @@ static int cprh_msmcobalt_kbss_calculate_target_quotients( if (!allow_interpolation) { /* Use fused target quotients for lower frequencies. */ - return cprh_msmcobalt_kbss_set_no_interpolation_quotients( + return cprh_msm8998_kbss_set_no_interpolation_quotients( vreg, volt_adjust, volt_adjust_fuse, ro_scale); } @@ -1004,7 +1004,7 @@ static int cprh_msmcobalt_kbss_calculate_target_quotients( * Interpolation is not possible for corners mapped to the lowest fuse * corner so use the fuse corner value directly. */ - i = CPRH_MSMCOBALT_KBSS_FUSE_CORNER_LOWSVS; + i = CPRH_MSM8998_KBSS_FUSE_CORNER_LOWSVS; quot_adjust = cpr3_quot_adjustment(ro_scale[i], volt_adjust_fuse[i]); quot = fuse->target_quot[i] + quot_adjust; quot_high[i] = quot_low[i] = quot; @@ -1013,11 +1013,11 @@ static int cprh_msmcobalt_kbss_calculate_target_quotients( cpr3_debug(vreg, "adjusted fuse corner %d RO%u target quot: %llu --> %u (%d uV)\n", i, ro, fuse->target_quot[i], quot, volt_adjust_fuse[i]); - for (i = 0; i <= fmax_corner[CPRH_MSMCOBALT_KBSS_FUSE_CORNER_LOWSVS]; + for (i = 0; i <= fmax_corner[CPRH_MSM8998_KBSS_FUSE_CORNER_LOWSVS]; i++) vreg->corner[i].target_quot[ro] = quot; - for (i = CPRH_MSMCOBALT_KBSS_FUSE_CORNER_SVS; + for (i = CPRH_MSM8998_KBSS_FUSE_CORNER_SVS; i < vreg->fuse_corner_count; i++) { quot_high[i] = fuse->target_quot[i]; if (fuse->ro_sel[i] == fuse->ro_sel[i - 1]) @@ -1025,7 +1025,7 @@ static int cprh_msmcobalt_kbss_calculate_target_quotients( else quot_low[i] = quot_high[i] - fuse->quot_offset[i] - * MSMCOBALT_KBSS_QUOT_OFFSET_SCALE; + * MSM8998_KBSS_QUOT_OFFSET_SCALE; if (quot_high[i] < quot_low[i]) { cpr3_debug(vreg, "quot_high[%d]=%llu < quot_low[%d]=%llu; overriding: quot_high[%d]=%llu\n", i, quot_high[i], i, quot_low[i], @@ -1163,10 +1163,10 @@ static int cprh_kbss_init_thread(struct cpr3_thread *thread) */ static int cprh_kbss_init_regulator(struct cpr3_regulator *vreg) { - struct cprh_msmcobalt_kbss_fuses *fuse; + struct cprh_msm8998_kbss_fuses *fuse; int rc; - rc = cprh_msmcobalt_kbss_read_fuse_data(vreg); + rc = cprh_msm8998_kbss_read_fuse_data(vreg); if (rc) { cpr3_err(vreg, "unable to read CPR fuse data, rc=%d\n", rc); return rc; @@ -1181,7 +1181,7 @@ static int cprh_kbss_init_regulator(struct cpr3_regulator *vreg) return rc; } - rc = cprh_msmcobalt_kbss_calculate_open_loop_voltages(vreg); + rc = cprh_msm8998_kbss_calculate_open_loop_voltages(vreg); if (rc) { cpr3_err(vreg, "unable to calculate open-loop voltages, rc=%d\n", rc); @@ -1205,7 +1205,7 @@ static int cprh_kbss_init_regulator(struct cpr3_regulator *vreg) return rc; } - rc = cprh_msmcobalt_kbss_calculate_target_quotients(vreg); + rc = cprh_msm8998_kbss_calculate_target_quotients(vreg); if (rc) { cpr3_err(vreg, "unable to calculate target quotients, rc=%d\n", rc); @@ -1228,13 +1228,13 @@ static int cprh_kbss_init_regulator(struct cpr3_regulator *vreg) if (vreg->allow_core_count_adj && (vreg->max_core_count <= 0 || vreg->max_core_count > - MSMCOBALT_KBSS_CPR_SDELTA_CORE_COUNT)) { + MSM8998_KBSS_CPR_SDELTA_CORE_COUNT)) { cpr3_err(vreg, "qcom,max-core-count has invalid value = %d\n", vreg->max_core_count); return -EINVAL; } - rc = cprh_msmcobalt_partial_binning_override(vreg); + rc = cprh_msm8998_partial_binning_override(vreg); if (rc) { cpr3_err(vreg, "unable to override CPR parameters based on partial binning fuse values, rc=%d\n", rc); @@ -1262,7 +1262,7 @@ static int cprh_kbss_init_regulator(struct cpr3_regulator *vreg) */ static int cprh_kbss_init_aging(struct cpr3_controller *ctrl) { - struct cprh_msmcobalt_kbss_fuses *fuse = NULL; + struct cprh_msm8998_kbss_fuses *fuse = NULL; struct cpr3_regulator *vreg; u32 aging_ro_scale; int i, j, rc; @@ -1300,24 +1300,24 @@ static int cprh_kbss_init_aging(struct cpr3_controller *ctrl) if (!ctrl->aging_sensor) return -ENOMEM; - if (ctrl->ctrl_id == MSMCOBALT_KBSS_POWER_CLUSTER_ID) { + if (ctrl->ctrl_id == MSM8998_KBSS_POWER_CLUSTER_ID) { ctrl->aging_sensor->sensor_id - = MSMCOBALT_KBSS_POWER_AGING_SENSOR_ID; + = MSM8998_KBSS_POWER_AGING_SENSOR_ID; ctrl->aging_sensor->bypass_mask[0] - = MSMCOBALT_KBSS_POWER_AGING_BYPASS_MASK0; + = MSM8998_KBSS_POWER_AGING_BYPASS_MASK0; } else { ctrl->aging_sensor->sensor_id - = MSMCOBALT_KBSS_PERFORMANCE_AGING_SENSOR_ID; + = MSM8998_KBSS_PERFORMANCE_AGING_SENSOR_ID; ctrl->aging_sensor->bypass_mask[0] - = MSMCOBALT_KBSS_PERFORMANCE_AGING_BYPASS_MASK0; + = MSM8998_KBSS_PERFORMANCE_AGING_BYPASS_MASK0; } ctrl->aging_sensor->ro_scale = aging_ro_scale; ctrl->aging_sensor->init_quot_diff = cpr3_convert_open_loop_voltage_fuse(0, - MSMCOBALT_KBSS_AGING_INIT_QUOT_DIFF_SCALE, + MSM8998_KBSS_AGING_INIT_QUOT_DIFF_SCALE, fuse->aging_init_quot_diff, - MSMCOBALT_KBSS_AGING_INIT_QUOT_DIFF_SIZE); + MSM8998_KBSS_AGING_INIT_QUOT_DIFF_SIZE); cpr3_debug(ctrl, "sensor %u aging init quotient diff = %d, aging RO scale = %u QUOT/V\n", ctrl->aging_sensor->sensor_id, @@ -1355,8 +1355,8 @@ static int cprh_kbss_init_controller(struct cpr3_controller *ctrl) return rc; } - if (ctrl->ctrl_id < MSMCOBALT_KBSS_MIN_CONTROLLER_ID || - ctrl->ctrl_id > MSMCOBALT_KBSS_MAX_CONTROLLER_ID) { + if (ctrl->ctrl_id < MSM8998_KBSS_MIN_CONTROLLER_ID || + ctrl->ctrl_id > MSM8998_KBSS_MAX_CONTROLLER_ID) { cpr3_err(ctrl, "invalid qcom,cpr-controller-id specified\n"); return -EINVAL; } @@ -1436,9 +1436,9 @@ static int cprh_kbss_init_controller(struct cpr3_controller *ctrl) "qcom,cpr-corner-switch-delay-time", &ctrl->corner_switch_delay_time); - ctrl->sensor_count = ctrl->ctrl_id == MSMCOBALT_KBSS_POWER_CLUSTER_ID ? - MSMCOBALT_KBSS_POWER_CPR_SENSOR_COUNT : - MSMCOBALT_KBSS_PERFORMANCE_CPR_SENSOR_COUNT; + ctrl->sensor_count = ctrl->ctrl_id == MSM8998_KBSS_POWER_CLUSTER_ID ? + MSM8998_KBSS_POWER_CPR_SENSOR_COUNT : + MSM8998_KBSS_PERFORMANCE_CPR_SENSOR_COUNT; /* * KBSS only has one thread (0) per controller so the zeroed @@ -1449,7 +1449,7 @@ static int cprh_kbss_init_controller(struct cpr3_controller *ctrl) if (!ctrl->sensor_owner) return -ENOMEM; - ctrl->cpr_clock_rate = MSMCOBALT_KBSS_CPR_CLOCK_RATE; + ctrl->cpr_clock_rate = MSM8998_KBSS_CPR_CLOCK_RATE; ctrl->supports_hw_closed_loop = true; ctrl->use_hw_closed_loop = of_property_read_bool(ctrl->dev->of_node, "qcom,cpr-hw-closed-loop"); @@ -1504,15 +1504,15 @@ static int cprh_kbss_regulator_resume(struct platform_device *pdev) /* Data corresponds to the SoC revision */ static struct of_device_id cprh_regulator_match_table[] = { { - .compatible = "qcom,cprh-msmcobalt-v1-kbss-regulator", + .compatible = "qcom,cprh-msm8998-v1-kbss-regulator", .data = (void *)(uintptr_t)1 }, { - .compatible = "qcom,cprh-msmcobalt-v2-kbss-regulator", + .compatible = "qcom,cprh-msm8998-v2-kbss-regulator", .data = (void *)(uintptr_t)2 }, { - .compatible = "qcom,cprh-msmcobalt-kbss-regulator", + .compatible = "qcom,cprh-msm8998-kbss-regulator", .data = (void *)(uintptr_t)2 }, {} diff --git a/drivers/regulator/qpnp-labibb-regulator.c b/drivers/regulator/qpnp-labibb-regulator.c index 3d0be1f8a5b5..15ade85f446b 100644 --- a/drivers/regulator/qpnp-labibb-regulator.c +++ b/drivers/regulator/qpnp-labibb-regulator.c @@ -714,10 +714,10 @@ static int qpnp_lab_dt_init(struct qpnp_labibb *labibb, u32 tmp; /* - * Do not configure LCD_AMOLED_SEL for pmicobalt as it will be done by + * Do not configure LCD_AMOLED_SEL for pmi8998 as it will be done by * GPIO selector. */ - if (labibb->pmic_rev_id->pmic_subtype != PMICOBALT_SUBTYPE) { + if (labibb->pmic_rev_id->pmic_subtype != PMI8998_SUBTYPE) { if (labibb->mode == QPNP_LABIBB_LCD_MODE) val = REG_LAB_IBB_LCD_MODE; else @@ -1529,7 +1529,7 @@ static int qpnp_labibb_regulator_disable(struct qpnp_labibb *labibb) return -EINVAL; } - if (labibb->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE && + if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE && labibb->mode == QPNP_LABIBB_LCD_MODE) { rc = qpnp_lab_pfm_disable(labibb); if (rc < 0) { @@ -1752,7 +1752,7 @@ static irqreturn_t lab_vreg_ok_handler(int irq, void *_labibb) if (rc < 0) pr_err("Failed in 'qpnp_skip_swire_command' rc=%d\n", rc); - } else if (labibb->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE && + } else if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE && labibb->mode == QPNP_LABIBB_LCD_MODE) { rc = qpnp_lab_pfm_enable(labibb); if (rc < 0) @@ -1776,13 +1776,13 @@ static bool is_lab_vreg_ok_irq_available(struct qpnp_labibb *labibb) { /* * LAB VREG_OK interrupt is used only to skip 2nd SWIRE command in - * dig_major < 2 targets. For pmicobalt, it is used to enable PFM in + * dig_major < 2 targets. For pmi8998, it is used to enable PFM in * LCD mode. */ if (labibb->skip_2nd_swire_cmd && labibb->lab_dig_major < 2) return true; - if (labibb->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE && + if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE && labibb->mode == QPNP_LABIBB_LCD_MODE) return true; @@ -2092,11 +2092,11 @@ static int qpnp_ibb_dt_init(struct qpnp_labibb *labibb, u8 val; /* - * Do not configure LCD_AMOLED_SEL for pmicobalt as it will be done by + * Do not configure LCD_AMOLED_SEL for pmi8998 as it will be done by * GPIO selector. Override the labibb->mode with what was configured * by the bootloader. */ - if (labibb->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE) { + if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) { rc = qpnp_labibb_read(labibb, &val, labibb->ibb_base + REG_IBB_LCD_AMOLED_SEL, 1); if (rc) { @@ -2627,10 +2627,10 @@ static int register_qpnp_ibb_regulator(struct qpnp_labibb *labibb, } /* - * For pmicobalt, override swire_control with what was configured + * For pmi8998, override swire_control with what was configured * before by the bootloader. */ - if (labibb->pmic_rev_id->pmic_subtype == PMICOBALT_SUBTYPE) + if (labibb->pmic_rev_id->pmic_subtype == PMI8998_SUBTYPE) labibb->swire_control = val & IBB_ENABLE_CTL_SWIRE_RDY; if (ibb_enable_ctl & diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index ea4f557fcd70..826a22355429 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -529,8 +529,8 @@ static struct msm_soc_info cpu_of_id[] = { [271] = {MSM_CPU_8929, "APQ8029"}, /* Cobalt IDs */ - [292] = {MSM_CPU_COBALT, "MSMCOBALT"}, - [319] = {MSM_CPU_COBALT, "APQCOBALT"}, + [292] = {MSM_CPU_8998, "MSM8998"}, + [319] = {MSM_CPU_8998, "APQ8998"}, /* Hamster ID */ [306] = {MSM_CPU_HAMSTER, "MSMHAMSTER"}, @@ -1198,9 +1198,9 @@ static void * __init setup_dummy_socinfo(void) dummy_socinfo.id = 268; strlcpy(dummy_socinfo.build_id, "msm8929 - ", sizeof(dummy_socinfo.build_id)); - } else if (early_machine_is_msmcobalt()) { + } else if (early_machine_is_msm8998()) { dummy_socinfo.id = 292; - strlcpy(dummy_socinfo.build_id, "msmcobalt - ", + strlcpy(dummy_socinfo.build_id, "msm8998 - ", sizeof(dummy_socinfo.build_id)); } else if (early_machine_is_msmhamster()) { dummy_socinfo.id = 306; @@ -1214,9 +1214,9 @@ static void * __init setup_dummy_socinfo(void) dummy_socinfo.id = 318; strlcpy(dummy_socinfo.build_id, "msmtriton - ", sizeof(dummy_socinfo.build_id)); - } else if (early_machine_is_apqcobalt()) { + } else if (early_machine_is_apq8998()) { dummy_socinfo.id = 319; - strlcpy(dummy_socinfo.build_id, "apqcobalt - ", + strlcpy(dummy_socinfo.build_id, "apq8998 - ", sizeof(dummy_socinfo.build_id)); } diff --git a/drivers/thermal/msm-tsens.c b/drivers/thermal/msm-tsens.c index df3a638510c2..7592bcb984ff 100644 --- a/drivers/thermal/msm-tsens.c +++ b/drivers/thermal/msm-tsens.c @@ -924,7 +924,7 @@ static struct of_device_id tsens_match[] = { { .compatible = "qcom,msmgold-tsens", .data = (void *)TSENS_CALIB_FUSE_MAP_MSMGOLD, }, - { .compatible = "qcom,msmcobalt-tsens", + { .compatible = "qcom,msm8998-tsens", .data = (void *)TSENS_CALIB_FUSE_MAP_NONE, }, { .compatible = "qcom,msmhamster-tsens", @@ -980,7 +980,7 @@ static int32_t get_tsens_sensor_for_client_id(struct tsens_tm_device *tmdev, } if (!strcmp(id->compatible, "qcom,msm8996-tsens") || - (!strcmp(id->compatible, "qcom,msmcobalt-tsens")) || + (!strcmp(id->compatible, "qcom,msm8998-tsens")) || (!strcmp(id->compatible, "qcom,msmhamster-tsens"))) { while (i < tmdev->tsens_num_sensor && !id_found) { if (tmdev->sensor[i].sensor_client_id == @@ -1109,7 +1109,7 @@ int tsens_get_hw_id_mapping(int thermal_sensor_num, int *sensor_client_id) } if (!strcmp(id->compatible, "qcom,msm8996-tsens") || - (!strcmp(id->compatible, "qcom,msmcobalt-tsens")) || + (!strcmp(id->compatible, "qcom,msm8998-tsens")) || (!strcmp(id->compatible, "qcom,msmhamster-tsens"))) { /* Assign client id's that is used to get the * controller and hw_sensor details @@ -5434,7 +5434,7 @@ static int get_device_tree_data(struct platform_device *pdev, (!strcmp(id->compatible, "qcom,msm8992-tsens"))) tmdev->tsens_type = TSENS_TYPE2; else if (!strcmp(id->compatible, "qcom,msm8996-tsens") || - (!strcmp(id->compatible, "qcom,msmcobalt-tsens"))) + (!strcmp(id->compatible, "qcom,msm8998-tsens"))) tmdev->tsens_type = TSENS_TYPE3; else if (!strcmp(id->compatible, "qcom,msmtitanium-tsens") || (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || @@ -5459,7 +5459,7 @@ static int get_device_tree_data(struct platform_device *pdev, (!strcmp(id->compatible, "qcom,msm8952-tsens")) || (!strcmp(id->compatible, "qcom,msm8937-tsens")) || (!strcmp(id->compatible, "qcom,msmtitanium-tsens")) || - (!strcmp(id->compatible, "qcom,msmcobalt-tsens")) || + (!strcmp(id->compatible, "qcom,msm8998-tsens")) || (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || (!strcmp(id->compatible, "qcom,msmtriton-tsens") || (!strcmp(id->compatible, "qcom,msmhamster-tsens"))))) @@ -5475,7 +5475,7 @@ static int get_device_tree_data(struct platform_device *pdev, } if (!strcmp(id->compatible, "qcom,msm8996-tsens") || - (!strcmp(id->compatible, "qcom,msmcobalt-tsens")) || + (!strcmp(id->compatible, "qcom,msm8998-tsens")) || (!strcmp(id->compatible, "qcom,msmhamster-tsens")) || (!strcmp(id->compatible, "qcom,msmfalcon-tsens") || (!strcmp(id->compatible, "qcom,msmtriton-tsens") || diff --git a/drivers/tty/tty_ldisc.c b/drivers/tty/tty_ldisc.c index 629e3c865072..9bee25cfa0be 100644 --- a/drivers/tty/tty_ldisc.c +++ b/drivers/tty/tty_ldisc.c @@ -417,6 +417,10 @@ EXPORT_SYMBOL_GPL(tty_ldisc_flush); * they are not on hot paths so a little discipline won't do * any harm. * + * The line discipline-related tty_struct fields are reset to + * prevent the ldisc driver from re-using stale information for + * the new ldisc instance. + * * Locking: takes termios_rwsem */ @@ -425,6 +429,9 @@ static void tty_set_termios_ldisc(struct tty_struct *tty, int num) down_write(&tty->termios_rwsem); tty->termios.c_line = num; up_write(&tty->termios_rwsem); + + tty->disc_data = NULL; + tty->receive_room = 0; } /** diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index eb2409dda50d..19d6a997ee6c 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -760,8 +760,8 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data) ssize_t ret, data_len = -EINVAL; int halt; - ffs_log("enter: epfile name %s epfile err %d", epfile->name, - atomic_read(&epfile->error)); + ffs_log("enter: epfile name %s epfile err %d (%s)", epfile->name, + atomic_read(&epfile->error), io_data->read ? "READ" : "WRITE"); smp_mb__before_atomic(); if (atomic_read(&epfile->error)) @@ -781,6 +781,12 @@ static ssize_t ffs_epfile_io(struct file *file, struct ffs_io_data *io_data) goto error; } + /* Don't wait on write if device is offline */ + if (!io_data->read) { + ret = -EINTR; + goto error; + } + /* * If ep is disabled, this fails all current IOs * and wait for next epfile open to happen. diff --git a/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c b/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c index d4ff82a11a09..992fd51606ca 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c +++ b/drivers/video/fbdev/msm/mdss_dsi_phy_v3.c @@ -220,13 +220,13 @@ static void mdss_dsi_phy_v3_config_lane_settings( int mdss_dsi_phy_v3_regulator_enable(struct mdss_dsi_ctrl_pdata *ctrl) { - /* Nothing to be done for cobalt */ + /* Nothing to be done for 8998 */ return 0; } int mdss_dsi_phy_v3_regulator_disable(struct mdss_dsi_ctrl_pdata *ctrl) { - /* Nothing to be done for cobalt */ + /* Nothing to be done for 8998 */ return 0; } diff --git a/drivers/video/fbdev/msm/mdss_hdmi_tx.c b/drivers/video/fbdev/msm/mdss_hdmi_tx.c index 9c90a72bce99..d01d163af5fa 100644 --- a/drivers/video/fbdev/msm/mdss_hdmi_tx.c +++ b/drivers/video/fbdev/msm/mdss_hdmi_tx.c @@ -78,7 +78,7 @@ #define HDMI_TX_MIN_FPS 20000 #define HDMI_TX_MAX_FPS 120000 -#define HDMI_TX_VERSION_403 0x40000003 /* msmcobalt */ +#define HDMI_TX_VERSION_403 0x40000003 /* msm8998 */ #define HDMI_GET_MSB(x) (x >> 8) #define HDMI_GET_LSB(x) (x & 0xff) diff --git a/drivers/video/fbdev/msm/mdss_mdp_debug.c b/drivers/video/fbdev/msm/mdss_mdp_debug.c index 711d2d222c7d..1ad6810a6bb6 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_debug.c +++ b/drivers/video/fbdev/msm/mdss_mdp_debug.c @@ -938,7 +938,7 @@ static struct debug_bus dbg_bus_8996[] = { }; -static struct debug_bus dbg_bus_msmcobalt[] = { +static struct debug_bus dbg_bus_msm8998[] = { /* * sspp0 - 0x188 @@ -1727,7 +1727,7 @@ static struct vbif_debug_bus nrt_vbif_dbg_bus_8996[] = { {0x21c, 0x214, 0, 12, 0, 0xc}, /* xin blocks - clock side */ }; -static struct vbif_debug_bus vbif_dbg_bus_msmcobalt[] = { +static struct vbif_debug_bus vbif_dbg_bus_msm8998[] = { {0x214, 0x21c, 16, 2, 0x0, 0xd}, /* arb clients */ {0x214, 0x21c, 16, 2, 0x80, 0xc0}, /* arb clients */ {0x214, 0x21c, 16, 2, 0x100, 0x140}, /* arb clients */ @@ -1757,10 +1757,10 @@ void mdss_mdp_hw_rev_debug_caps_init(struct mdss_data_type *mdata) break; case MDSS_MDP_HW_REV_300: case MDSS_MDP_HW_REV_301: - mdata->dbg_bus = dbg_bus_msmcobalt; - mdata->dbg_bus_size = ARRAY_SIZE(dbg_bus_msmcobalt); - mdata->vbif_dbg_bus = vbif_dbg_bus_msmcobalt; - mdata->vbif_dbg_bus_size = ARRAY_SIZE(vbif_dbg_bus_msmcobalt); + mdata->dbg_bus = dbg_bus_msm8998; + mdata->dbg_bus_size = ARRAY_SIZE(dbg_bus_msm8998); + mdata->vbif_dbg_bus = vbif_dbg_bus_msm8998; + mdata->vbif_dbg_bus_size = ARRAY_SIZE(vbif_dbg_bus_msm8998); mdata->nrt_vbif_dbg_bus = nrt_vbif_dbg_bus_8996; mdata->nrt_vbif_dbg_bus_size = ARRAY_SIZE(nrt_vbif_dbg_bus_8996); diff --git a/drivers/video/fbdev/msm/mdss_mdp_pp.c b/drivers/video/fbdev/msm/mdss_mdp_pp.c index c6bef7c22193..248492b28ce2 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_pp.c +++ b/drivers/video/fbdev/msm/mdss_mdp_pp.c @@ -2190,7 +2190,7 @@ static int pp_hist_setup(u32 *op, u32 block, struct mdss_mdp_mixer *mix, if (hist_info->col_en) mdss_mdp_hist_irq_set_mask(intr_mask << hist_info->intr_shift); /* - * Starting from msmcobalt, the histogram enable bit has been moved + * Starting from msm8998, the histogram enable bit has been moved * from DSPP opmode register to PA_HIST opmode register, hence we need * to update the histogram enable bit differently based on mdss version. * If HIST pp_set_config is defined, we will enable or disable the diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-8998.h index 4bacef303967..42617016188d 100644 --- a/include/dt-bindings/clock/msm-clocks-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-8998.h @@ -10,8 +10,8 @@ * GNU General Public License for more details. */ -#ifndef __MSM_CLOCKS_COBALT_H -#define __MSM_CLOCKS_COBALT_H +#ifndef __MSM_CLOCKS_8998_H +#define __MSM_CLOCKS_8998_H #include "audio-ext-clk.h" diff --git a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h b/include/dt-bindings/clock/msm-clocks-hwio-8998.h index f10afffc74b2..f10afffc74b2 100644 --- a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h +++ b/include/dt-bindings/clock/msm-clocks-hwio-8998.h diff --git a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h b/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h index ffb80a128dd6..7a6ec2bf2418 100644 --- a/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h +++ b/include/dt-bindings/clock/qcom,mmcc-msmfalcon.h @@ -159,46 +159,47 @@ #define MMSS_MDSS_AXI_CLK 142 #define MMSS_MDSS_BYTE0_CLK 143 #define MMSS_MDSS_BYTE0_INTF_CLK 144 -#define MMSS_MDSS_BYTE1_CLK 145 -#define MMSS_MDSS_BYTE1_INTF_CLK 146 -#define MMSS_MDSS_DP_AUX_CLK 147 -#define MMSS_MDSS_DP_CRYPTO_CLK 148 -#define MMSS_MDSS_DP_GTC_CLK 149 -#define MMSS_MDSS_DP_LINK_CLK 150 -#define MMSS_MDSS_DP_LINK_INTF_CLK 151 -#define MMSS_MDSS_DP_PIXEL_CLK 152 -#define MMSS_MDSS_ESC0_CLK 153 -#define MMSS_MDSS_ESC1_CLK 154 -#define MMSS_MDSS_HDMI_DP_AHB_CLK 155 -#define MMSS_MDSS_MDP_CLK 156 -#define MMSS_MDSS_PCLK0_CLK 157 -#define MMSS_MDSS_PCLK1_CLK 158 -#define MMSS_MDSS_ROT_CLK 159 -#define MMSS_MDSS_VSYNC_CLK 160 -#define MMSS_MISC_AHB_CLK 161 -#define MMSS_MISC_CXO_CLK 162 -#define MMSS_MNOC_AHB_CLK 163 -#define MMSS_SNOC_DVM_AXI_CLK 164 -#define MMSS_THROTTLE_CAMSS_AHB_CLK 165 -#define MMSS_THROTTLE_CAMSS_AXI_CLK 166 -#define MMSS_THROTTLE_CAMSS_CXO_CLK 167 -#define MMSS_THROTTLE_MDSS_AHB_CLK 168 -#define MMSS_THROTTLE_MDSS_AXI_CLK 169 -#define MMSS_THROTTLE_MDSS_CXO_CLK 170 -#define MMSS_THROTTLE_VIDEO_AHB_CLK 171 -#define MMSS_THROTTLE_VIDEO_AXI_CLK 172 -#define MMSS_THROTTLE_VIDEO_CXO_CLK 173 -#define MMSS_VIDEO_AHB_CLK 174 -#define MMSS_VIDEO_AXI_CLK 175 -#define MMSS_VIDEO_CORE_CLK 176 -#define MMSS_VIDEO_SUBCORE0_CLK 177 -#define PCLK0_CLK_SRC 178 -#define PCLK1_CLK_SRC 179 -#define ROT_CLK_SRC 180 -#define VFE0_CLK_SRC 181 -#define VFE1_CLK_SRC 182 -#define VIDEO_CORE_CLK_SRC 183 -#define VSYNC_CLK_SRC 184 +#define MMSS_MDSS_BYTE0_INTF_DIV_CLK 145 +#define MMSS_MDSS_BYTE1_CLK 146 +#define MMSS_MDSS_BYTE1_INTF_CLK 147 +#define MMSS_MDSS_DP_AUX_CLK 148 +#define MMSS_MDSS_DP_CRYPTO_CLK 149 +#define MMSS_MDSS_DP_GTC_CLK 150 +#define MMSS_MDSS_DP_LINK_CLK 151 +#define MMSS_MDSS_DP_LINK_INTF_CLK 152 +#define MMSS_MDSS_DP_PIXEL_CLK 153 +#define MMSS_MDSS_ESC0_CLK 154 +#define MMSS_MDSS_ESC1_CLK 155 +#define MMSS_MDSS_HDMI_DP_AHB_CLK 156 +#define MMSS_MDSS_MDP_CLK 157 +#define MMSS_MDSS_PCLK0_CLK 158 +#define MMSS_MDSS_PCLK1_CLK 159 +#define MMSS_MDSS_ROT_CLK 160 +#define MMSS_MDSS_VSYNC_CLK 161 +#define MMSS_MISC_AHB_CLK 162 +#define MMSS_MISC_CXO_CLK 163 +#define MMSS_MNOC_AHB_CLK 164 +#define MMSS_SNOC_DVM_AXI_CLK 165 +#define MMSS_THROTTLE_CAMSS_AHB_CLK 166 +#define MMSS_THROTTLE_CAMSS_AXI_CLK 167 +#define MMSS_THROTTLE_CAMSS_CXO_CLK 168 +#define MMSS_THROTTLE_MDSS_AHB_CLK 169 +#define MMSS_THROTTLE_MDSS_AXI_CLK 170 +#define MMSS_THROTTLE_MDSS_CXO_CLK 171 +#define MMSS_THROTTLE_VIDEO_AHB_CLK 172 +#define MMSS_THROTTLE_VIDEO_AXI_CLK 173 +#define MMSS_THROTTLE_VIDEO_CXO_CLK 174 +#define MMSS_VIDEO_AHB_CLK 175 +#define MMSS_VIDEO_AXI_CLK 176 +#define MMSS_VIDEO_CORE_CLK 177 +#define MMSS_VIDEO_SUBCORE0_CLK 178 +#define PCLK0_CLK_SRC 179 +#define PCLK1_CLK_SRC 180 +#define ROT_CLK_SRC 181 +#define VFE0_CLK_SRC 182 +#define VFE1_CLK_SRC 183 +#define VIDEO_CORE_CLK_SRC 184 +#define VSYNC_CLK_SRC 185 #define BIMC_SMMU_GDSC 0 #define CAMSS_CPP_GDSC 1 @@ -209,5 +210,6 @@ #define VIDEO_SUBCORE0_GDSC 6 #define VIDEO_TOP_GDSC 7 +#define CAMSS_MICRO_BCR 0 #endif diff --git a/include/linux/qpnp/qpnp-revid.h b/include/linux/qpnp/qpnp-revid.h index 652d68ac63bf..8d9bbfd67992 100644 --- a/include/linux/qpnp/qpnp-revid.h +++ b/include/linux/qpnp/qpnp-revid.h @@ -171,30 +171,30 @@ /* PMI8996 */ #define PMI8996_SUBTYPE 0x13 -/* PMCOBALT */ -#define PMCOBALT_SUBTYPE 0x14 +/* PM8998 */ +#define PM8998_SUBTYPE 0x14 -/* PMICOBALT */ -#define PMICOBALT_SUBTYPE 0x15 +/* PMI8998 */ +#define PMI8998_SUBTYPE 0x15 /* PMFALCON */ #define PM2FALCON_SUBTYPE 0x1A #define PMFALCON_SUBTYPE 0x1B -#define PMICOBALT_V1P0_REV1 0x00 -#define PMICOBALT_V1P0_REV2 0x00 -#define PMICOBALT_V1P0_REV3 0x00 -#define PMICOBALT_V1P0_REV4 0x01 +#define PMI8998_V1P0_REV1 0x00 +#define PMI8998_V1P0_REV2 0x00 +#define PMI8998_V1P0_REV3 0x00 +#define PMI8998_V1P0_REV4 0x01 -#define PMICOBALT_V1P1_REV1 0x00 -#define PMICOBALT_V1P1_REV2 0x00 -#define PMICOBALT_V1P1_REV3 0x01 -#define PMICOBALT_V1P1_REV4 0x01 +#define PMI8998_V1P1_REV1 0x00 +#define PMI8998_V1P1_REV2 0x00 +#define PMI8998_V1P1_REV3 0x01 +#define PMI8998_V1P1_REV4 0x01 -#define PMICOBALT_V2P0_REV1 0x00 -#define PMICOBALT_V2P0_REV2 0x00 -#define PMICOBALT_V2P0_REV3 0x00 -#define PMICOBALT_V2P0_REV4 0x02 +#define PMI8998_V2P0_REV1 0x00 +#define PMI8998_V2P0_REV2 0x00 +#define PMI8998_V2P0_REV3 0x00 +#define PMI8998_V2P0_REV4 0x02 /* PM8005 */ #define PM8005_SUBTYPE 0x18 diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index b89c9c2f7f6e..cc1e8d6b3454 100644 --- a/include/net/cfg80211.h +++ b/include/net/cfg80211.h @@ -796,19 +796,15 @@ struct cfg80211_csa_settings { * @iftype_num: array with the number of interfaces of each interface * type. The index is the interface type as specified in &enum * nl80211_iftype. - * @beacon_int_gcd: a value specifying GCD of all beaconing interfaces, - * the GCD of a single value is considered the value itself, so for - * a single interface this should be set to that interface's beacon - * interval - * @beacon_int_different: a flag indicating whether or not all beacon - * intervals (of beaconing interfaces) are different or not. + * @new_beacon_int: set this to the beacon interval of a new interface + * that's not operating yet, if such is to be checked as part of + * the verification */ struct iface_combination_params { int num_different_channels; u8 radar_detect; int iftype_num[NUM_NL80211_IFTYPES]; - u32 beacon_int_gcd; - bool beacon_int_different; + u32 new_beacon_int; }; /** @@ -3219,6 +3215,9 @@ struct wiphy_iftype_ext_capab { * @vht_capa_mod_mask: Specify what VHT capabilities can be over-ridden. * If null, then none can be over-ridden. * + * @wdev_list: the list of associated (virtual) interfaces; this list must + * not be modified by the driver, but can be read with RTNL/RCU protection. + * * @max_acl_mac_addrs: Maximum number of MAC addresses that the device * supports for ACL. * @@ -3363,6 +3362,8 @@ struct wiphy { const struct ieee80211_ht_cap *ht_capa_mod_mask; const struct ieee80211_vht_cap *vht_capa_mod_mask; + struct list_head wdev_list; + /* the network namespace this phy lives in currently */ possible_net_t _net; diff --git a/include/net/tcp.h b/include/net/tcp.h index 213601d620e0..52402ab90c57 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -1528,6 +1528,8 @@ static inline void tcp_check_send_head(struct sock *sk, struct sk_buff *skb_unli { if (sk->sk_send_head == skb_unlinked) sk->sk_send_head = NULL; + if (tcp_sk(sk)->highest_sack == skb_unlinked) + tcp_sk(sk)->highest_sack = NULL; } static inline void tcp_init_send_head(struct sock *sk) diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h index 76555ce53d97..5f1912a62267 100644 --- a/include/soc/qcom/socinfo.h +++ b/include/soc/qcom/socinfo.h @@ -88,10 +88,10 @@ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msm8996-cdp") #define early_machine_is_msm8929() \ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msm8929") -#define early_machine_is_msmcobalt() \ - of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmcobalt") -#define early_machine_is_apqcobalt() \ - of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,apqcobalt") +#define early_machine_is_msm8998() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msm8998") +#define early_machine_is_apq8998() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,apq8998") #define early_machine_is_msmhamster() \ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msmhamster") #define early_machine_is_msmfalcon() \ @@ -131,8 +131,8 @@ #define early_machine_is_msm8996() 0 #define early_machine_is_msm8976() 0 #define early_machine_is_msm8929() 0 -#define early_machine_is_msmcobalt() 0 -#define early_machine_is_apqcobalt() 0 +#define early_machine_is_msm8998() 0 +#define early_machine_is_apq8998() 0 #define early_machine_is_msmhamster() 0 #define early_machine_is_msmfalcon() 0 #define early_machine_is_msmtriton() 0 @@ -192,7 +192,7 @@ enum msm_cpu { MSM_CPU_8996, MSM_CPU_8976, MSM_CPU_8929, - MSM_CPU_COBALT, + MSM_CPU_8998, MSM_CPU_HAMSTER, MSM_CPU_FALCON, MSM_CPU_TRITON, diff --git a/include/uapi/linux/msm_mdp.h b/include/uapi/linux/msm_mdp.h index f0ac02e9c7a8..20b879c2e5fc 100644 --- a/include/uapi/linux/msm_mdp.h +++ b/include/uapi/linux/msm_mdp.h @@ -116,8 +116,8 @@ #define MDSS_MDP_HW_REV_114 MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */ #define MDSS_MDP_HW_REV_115 MDSS_MDP_REV(1, 15, 0) /* msmgold */ #define MDSS_MDP_HW_REV_116 MDSS_MDP_REV(1, 16, 0) /* msmtitanium */ -#define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msmcobalt */ -#define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msmcobalt v1.0 */ +#define MDSS_MDP_HW_REV_300 MDSS_MDP_REV(3, 0, 0) /* msm8998 */ +#define MDSS_MDP_HW_REV_301 MDSS_MDP_REV(3, 0, 1) /* msm8998 v1.0 */ enum { NOTIFY_UPDATE_INIT, diff --git a/kernel/cgroup.c b/kernel/cgroup.c index ae83d9602aa0..8c9823947c7a 100644 --- a/kernel/cgroup.c +++ b/kernel/cgroup.c @@ -6002,7 +6002,7 @@ static int cgroup_css_links_read(struct seq_file *seq, void *v) struct task_struct *task; int count = 0; - seq_printf(seq, "css_set %p\n", cset); + seq_printf(seq, "css_set %pK\n", cset); list_for_each_entry(task, &cset->tasks, cg_list) { if (count++ > MAX_TASKS_SHOWN_PER_CSS) diff --git a/net/netfilter/nfnetlink.c b/net/netfilter/nfnetlink.c index 77afe913d03d..9adedba78eea 100644 --- a/net/netfilter/nfnetlink.c +++ b/net/netfilter/nfnetlink.c @@ -326,10 +326,12 @@ replay: nlh = nlmsg_hdr(skb); err = 0; - if (nlmsg_len(nlh) < sizeof(struct nfgenmsg) || - skb->len < nlh->nlmsg_len) { - err = -EINVAL; - goto ack; + if (nlh->nlmsg_len < NLMSG_HDRLEN || + skb->len < nlh->nlmsg_len || + nlmsg_len(nlh) < sizeof(struct nfgenmsg)) { + nfnl_err_reset(&err_list); + status |= NFNL_BATCH_FAILURE; + goto done; } /* Only requests are handled by the kernel */ diff --git a/net/wireless/chan.c b/net/wireless/chan.c index cf14c7e22fb3..d5ccaeaa76e0 100644 --- a/net/wireless/chan.c +++ b/net/wireless/chan.c @@ -749,7 +749,7 @@ static bool cfg80211_ir_permissive_chan(struct wiphy *wiphy, * and thus fail the GO instantiation, consider only the interfaces of * the current registered device. */ - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { struct ieee80211_channel *other_chan = NULL; int r1, r2; diff --git a/net/wireless/core.c b/net/wireless/core.c index 6d3402434a63..16043faba52c 100644 --- a/net/wireless/core.c +++ b/net/wireless/core.c @@ -3,6 +3,7 @@ * * Copyright 2006-2010 Johannes Berg <johannes@sipsolutions.net> * Copyright 2013-2014 Intel Mobile Communications GmbH + * Copyright 2015 Intel Deutschland GmbH */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt @@ -157,7 +158,7 @@ int cfg80211_switch_netns(struct cfg80211_registered_device *rdev, if (!(rdev->wiphy.flags & WIPHY_FLAG_NETNS_OK)) return -EOPNOTSUPP; - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (!wdev->netdev) continue; wdev->netdev->features &= ~NETIF_F_NETNS_LOCAL; @@ -171,7 +172,8 @@ int cfg80211_switch_netns(struct cfg80211_registered_device *rdev, /* failed -- clean up to old netns */ net = wiphy_net(&rdev->wiphy); - list_for_each_entry_continue_reverse(wdev, &rdev->wdev_list, + list_for_each_entry_continue_reverse(wdev, + &rdev->wiphy.wdev_list, list) { if (!wdev->netdev) continue; @@ -230,7 +232,7 @@ void cfg80211_shutdown_all_interfaces(struct wiphy *wiphy) ASSERT_RTNL(); - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (wdev->netdev) { dev_close(wdev->netdev); continue; @@ -298,7 +300,8 @@ void cfg80211_destroy_ifaces(struct cfg80211_registered_device *rdev) kfree(item); spin_unlock_irq(&rdev->destroy_list_lock); - list_for_each_entry_safe(wdev, tmp, &rdev->wdev_list, list) { + list_for_each_entry_safe(wdev, tmp, + &rdev->wiphy.wdev_list, list) { if (nlportid == wdev->owner_nlportid) rdev_del_virtual_intf(rdev, wdev); } @@ -400,7 +403,7 @@ use_default_name: dev_set_name(&rdev->wiphy.dev, PHY_NAME "%d", rdev->wiphy_idx); } - INIT_LIST_HEAD(&rdev->wdev_list); + INIT_LIST_HEAD(&rdev->wiphy.wdev_list); INIT_LIST_HEAD(&rdev->beacon_registrations); spin_lock_init(&rdev->beacon_registrations_lock); spin_lock_init(&rdev->bss_lock); @@ -812,7 +815,7 @@ void wiphy_unregister(struct wiphy *wiphy) nl80211_notify_wiphy(rdev, NL80211_CMD_DEL_WIPHY); rdev->wiphy.registered = false; - WARN_ON(!list_empty(&rdev->wdev_list)); + WARN_ON(!list_empty(&rdev->wiphy.wdev_list)); /* * First remove the hardware from everywhere, this makes @@ -949,7 +952,7 @@ static int cfg80211_netdev_notifier_call(struct notifier_block *nb, spin_lock_init(&wdev->mgmt_registrations_lock); wdev->identifier = ++rdev->wdev_id; - list_add_rcu(&wdev->list, &rdev->wdev_list); + list_add_rcu(&wdev->list, &rdev->wiphy.wdev_list); rdev->devlist_generation++; /* can only change netns with wiphy */ dev->features |= NETIF_F_NETNS_LOCAL; diff --git a/net/wireless/core.h b/net/wireless/core.h index fcd59e76a8e5..a06a1056f726 100644 --- a/net/wireless/core.h +++ b/net/wireless/core.h @@ -50,8 +50,7 @@ struct cfg80211_registered_device { /* wiphy index, internal only */ int wiphy_idx; - /* associated wireless interfaces, protected by rtnl or RCU */ - struct list_head wdev_list; + /* protected by RTNL */ int devlist_generation, wdev_id; int opencount; /* also protected by devlist_mtx */ wait_queue_head_t dev_wait; diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c index 40299f19c09b..375d6c1732fa 100644 --- a/net/wireless/nl80211.c +++ b/net/wireless/nl80211.c @@ -103,7 +103,7 @@ __cfg80211_wdev_from_attrs(struct net *netns, struct nlattr **attrs) if (have_wdev_id && rdev->wiphy_idx != wiphy_idx) continue; - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (have_ifidx && wdev->netdev && wdev->netdev->ifindex == ifidx) { result = wdev; @@ -149,7 +149,7 @@ __cfg80211_rdev_from_attrs(struct net *netns, struct nlattr **attrs) tmp = cfg80211_rdev_by_wiphy_idx(wdev_id >> 32); if (tmp) { /* make sure wdev exists */ - list_for_each_entry(wdev, &tmp->wdev_list, list) { + list_for_each_entry(wdev, &tmp->wiphy.wdev_list, list) { if (wdev->identifier != (u32)wdev_id) continue; found = true; @@ -524,7 +524,7 @@ static int nl80211_prepare_wdev_dump(struct sk_buff *skb, *rdev = wiphy_to_rdev(wiphy); *wdev = NULL; - list_for_each_entry(tmp, &(*rdev)->wdev_list, list) { + list_for_each_entry(tmp, &(*rdev)->wiphy.wdev_list, list) { if (tmp->identifier == cb->args[1]) { *wdev = tmp; break; @@ -2504,7 +2504,7 @@ static int nl80211_dump_interface(struct sk_buff *skb, struct netlink_callback * } if_idx = 0; - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (if_idx < if_start) { if_idx++; continue; @@ -2776,7 +2776,7 @@ static int nl80211_new_interface(struct sk_buff *skb, struct genl_info *info) spin_lock_init(&wdev->mgmt_registrations_lock); wdev->identifier = ++rdev->wdev_id; - list_add_rcu(&wdev->list, &rdev->wdev_list); + list_add_rcu(&wdev->list, &rdev->wiphy.wdev_list); rdev->devlist_generation++; break; default: @@ -3585,7 +3585,7 @@ static bool nl80211_get_ap_channel(struct cfg80211_registered_device *rdev, struct wireless_dev *wdev; bool ret = false; - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (wdev->iftype != NL80211_IFTYPE_AP && wdev->iftype != NL80211_IFTYPE_P2P_GO) continue; @@ -7770,12 +7770,14 @@ static int nl80211_join_ibss(struct sk_buff *skb, struct genl_info *info) ibss.beacon_interval = 100; - if (info->attrs[NL80211_ATTR_BEACON_INTERVAL]) { + if (info->attrs[NL80211_ATTR_BEACON_INTERVAL]) ibss.beacon_interval = nla_get_u32(info->attrs[NL80211_ATTR_BEACON_INTERVAL]); - if (ibss.beacon_interval < 1 || ibss.beacon_interval > 10000) - return -EINVAL; - } + + err = cfg80211_validate_beacon_int(rdev, NL80211_IFTYPE_ADHOC, + ibss.beacon_interval); + if (err) + return err; if (!rdev->ops->join_ibss) return -EOPNOTSUPP; @@ -9013,9 +9015,12 @@ static int nl80211_join_mesh(struct sk_buff *skb, struct genl_info *info) if (info->attrs[NL80211_ATTR_BEACON_INTERVAL]) { setup.beacon_interval = nla_get_u32(info->attrs[NL80211_ATTR_BEACON_INTERVAL]); - if (setup.beacon_interval < 10 || - setup.beacon_interval > 10000) - return -EINVAL; + + err = cfg80211_validate_beacon_int(rdev, + NL80211_IFTYPE_MESH_POINT, + setup.beacon_interval); + if (err) + return err; } if (info->attrs[NL80211_ATTR_DTIM_PERIOD]) { @@ -10328,7 +10333,7 @@ static int nl80211_prepare_vendor_dump(struct sk_buff *skb, *wdev = NULL; if (cb->args[1]) { - list_for_each_entry(tmp, &(*rdev)->wdev_list, list) { + list_for_each_entry(tmp, &wiphy->wdev_list, list) { if (tmp->identifier == cb->args[1] - 1) { *wdev = tmp; break; @@ -13339,7 +13344,7 @@ static int nl80211_netlink_notify(struct notifier_block * nb, sched_scan_req->owner_nlportid == notify->portid) schedule_scan_stop = true; - list_for_each_entry_rcu(wdev, &rdev->wdev_list, list) { + list_for_each_entry_rcu(wdev, &rdev->wiphy.wdev_list, list) { cfg80211_mlme_unregister_socket(wdev, notify->portid); if (wdev->owner_nlportid == notify->portid) diff --git a/net/wireless/reg.c b/net/wireless/reg.c index 2fed05f2edf8..050d7948dd68 100644 --- a/net/wireless/reg.c +++ b/net/wireless/reg.c @@ -1685,7 +1685,7 @@ static void reg_leave_invalid_chans(struct wiphy *wiphy) struct cfg80211_sched_scan_request *sched_scan_req; ASSERT_RTNL(); - list_for_each_entry(wdev, &rdev->wdev_list, list) + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) if (!reg_wdev_chan_valid(wiphy, wdev)) { dev = wdev->netdev; switch (wdev->iftype) { diff --git a/net/wireless/sme.c b/net/wireless/sme.c index 37d8ab3a71be..e5b962d2ffe7 100644 --- a/net/wireless/sme.c +++ b/net/wireless/sme.c @@ -54,7 +54,7 @@ static bool cfg80211_is_all_countryie_ignore(void) bool is_all_countryie_ignore = true; list_for_each_entry(rdev, &cfg80211_rdev_list, list) { - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { wdev_lock(wdev); if (!(wdev->wiphy->regulatory_flags & REGULATORY_COUNTRY_IE_IGNORE)) { @@ -246,7 +246,7 @@ void cfg80211_conn_work(struct work_struct *work) rtnl_lock(); - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (!wdev->netdev) continue; @@ -630,7 +630,7 @@ static bool cfg80211_is_all_idle(void) * count as new regulatory hints. */ list_for_each_entry(rdev, &cfg80211_rdev_list, list) { - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { wdev_lock(wdev); if (wdev->conn || wdev->current_bss) is_all_idle = false; diff --git a/net/wireless/util.c b/net/wireless/util.c index acff02fcc281..ef394e8a42bc 100644 --- a/net/wireless/util.c +++ b/net/wireless/util.c @@ -13,6 +13,7 @@ #include <net/dsfield.h> #include <linux/if_vlan.h> #include <linux/mpls.h> +#include <linux/gcd.h> #include "core.h" #include "rdev-ops.h" @@ -910,7 +911,7 @@ void cfg80211_process_rdev_events(struct cfg80211_registered_device *rdev) ASSERT_RTNL(); - list_for_each_entry(wdev, &rdev->wdev_list, list) + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) cfg80211_process_wdev_events(wdev); } @@ -1482,47 +1483,53 @@ bool ieee80211_chandef_to_operating_class(struct cfg80211_chan_def *chandef, } EXPORT_SYMBOL(ieee80211_chandef_to_operating_class); -int cfg80211_validate_beacon_int(struct cfg80211_registered_device *rdev, - enum nl80211_iftype iftype, u32 beacon_int) +static void cfg80211_calculate_bi_data(struct wiphy *wiphy, u32 new_beacon_int, + u32 *beacon_int_gcd, + bool *beacon_int_different) { struct wireless_dev *wdev; - struct iface_combination_params params = { - .beacon_int_gcd = beacon_int, /* GCD(n) = n */ - }; - if (!beacon_int) - return -EINVAL; + *beacon_int_gcd = 0; + *beacon_int_different = false; - params.iftype_num[iftype] = 1; - list_for_each_entry(wdev, &rdev->wdev_list, list) { + list_for_each_entry(wdev, &wiphy->wdev_list, list) { if (!wdev->beacon_interval) continue; - params.iftype_num[wdev->iftype]++; - } - - list_for_each_entry(wdev, &rdev->wdev_list, list) { - u32 bi_prev = wdev->beacon_interval; - - if (!wdev->beacon_interval) + if (!*beacon_int_gcd) { + *beacon_int_gcd = wdev->beacon_interval; continue; + } - /* slight optimisation - skip identical BIs */ - if (wdev->beacon_interval == beacon_int) + if (wdev->beacon_interval == *beacon_int_gcd) continue; - params.beacon_int_different = true; - - /* Get the GCD */ - while (bi_prev != 0) { - u32 tmp_bi = bi_prev; + *beacon_int_different = true; + *beacon_int_gcd = gcd(*beacon_int_gcd, wdev->beacon_interval); + } - bi_prev = params.beacon_int_gcd % bi_prev; - params.beacon_int_gcd = tmp_bi; - } + if (new_beacon_int && *beacon_int_gcd != new_beacon_int) { + if (*beacon_int_gcd) + *beacon_int_different = true; + *beacon_int_gcd = gcd(*beacon_int_gcd, new_beacon_int); } +} - return cfg80211_check_combinations(&rdev->wiphy, ¶ms); +int cfg80211_validate_beacon_int(struct cfg80211_registered_device *rdev, + enum nl80211_iftype iftype, u32 beacon_int) +{ + /* + * This is just a basic pre-condition check; if interface combinations + * are possible the driver must already be checking those with a call + * to cfg80211_check_combinations(), in which case we'll validate more + * through the cfg80211_calculate_bi_data() call and code in + * cfg80211_iter_combinations(). + */ + + if (beacon_int < 10 || beacon_int > 10000) + return -EINVAL; + + return 0; } int cfg80211_iter_combinations(struct wiphy *wiphy, @@ -1536,6 +1543,21 @@ int cfg80211_iter_combinations(struct wiphy *wiphy, int i, j, iftype; int num_interfaces = 0; u32 used_iftypes = 0; + u32 beacon_int_gcd; + bool beacon_int_different; + + /* + * This is a bit strange, since the iteration used to rely only on + * the data given by the driver, but here it now relies on context, + * in form of the currently operating interfaces. + * This is OK for all current users, and saves us from having to + * push the GCD calculations into all the drivers. + * In the future, this should probably rely more on data that's in + * cfg80211 already - the only thing not would appear to be any new + * interfaces (while being brought up) and channel/radar data. + */ + cfg80211_calculate_bi_data(wiphy, params->new_beacon_int, + &beacon_int_gcd, &beacon_int_different); if (params->radar_detect) { rcu_read_lock(); @@ -1598,14 +1620,11 @@ int cfg80211_iter_combinations(struct wiphy *wiphy, if ((all_iftypes & used_iftypes) != used_iftypes) goto cont; - if (params->beacon_int_gcd) { + if (beacon_int_gcd) { if (c->beacon_int_min_gcd && - params->beacon_int_gcd < c->beacon_int_min_gcd) { - kfree(limits); - return -EINVAL; - } - if (!c->beacon_int_min_gcd && - params->beacon_int_different) + beacon_int_gcd < c->beacon_int_min_gcd) + goto cont; + if (!c->beacon_int_min_gcd && beacon_int_different) goto cont; } @@ -1701,7 +1720,7 @@ int cfg80211_can_use_iftype_chan(struct cfg80211_registered_device *rdev, break; } - list_for_each_entry(wdev_iter, &rdev->wdev_list, list) { + list_for_each_entry(wdev_iter, &rdev->wiphy.wdev_list, list) { if (wdev_iter == wdev) continue; if (wdev_iter->iftype == NL80211_IFTYPE_P2P_DEVICE) { diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 38b8a806584f..553b35a2d717 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -989,7 +989,7 @@ config SND_SOC_MSM_STUB config SND_SOC_MSM_HDMI_CODEC_RX bool "HDMI Audio Playback" - depends on FB_MSM_MDSS_HDMI_PANEL && (SND_SOC_APQ8084 || SND_SOC_MSM8994 || SND_SOC_MSM8996 || SND_SOC_MSMCOBALT) + depends on FB_MSM_MDSS_HDMI_PANEL && (SND_SOC_APQ8084 || SND_SOC_MSM8994 || SND_SOC_MSM8996 || SND_SOC_MSM8998) help HDMI audio drivers should be built only if the platform supports hdmi panel. diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig index 9cf69eca0028..a5cd94f91cfc 100644 --- a/sound/soc/msm/Kconfig +++ b/sound/soc/msm/Kconfig @@ -190,8 +190,8 @@ config SND_SOC_MSM8996 the machine driver and the corresponding DAI-links -config SND_SOC_MSMCOBALT - tristate "SoC Machine driver for MSMCOBALT boards" +config SND_SOC_MSM8998 + tristate "SoC Machine driver for MSM8998 boards" depends on ARCH_QCOM select SND_SOC_COMPRESS select SND_SOC_QDSP6V2 @@ -215,7 +215,7 @@ config SND_SOC_MSMCOBALT select SND_HWDEP select DTS_EAGLE help - To add support for SoC audio on MSMCOBALT. + To add support for SoC audio on MSM8998. This will enable sound soc drivers which interfaces with DSP, also it will enable the machine driver and the corresponding diff --git a/sound/soc/msm/Makefile b/sound/soc/msm/Makefile index 799c9ee63d43..8df7fad3893d 100644 --- a/sound/soc/msm/Makefile +++ b/sound/soc/msm/Makefile @@ -16,9 +16,9 @@ obj-$(CONFIG_SND_SOC_CPE) += snd-soc-cpe.o snd-soc-msm8996-objs := msm8996.o obj-$(CONFIG_SND_SOC_MSM8996) += snd-soc-msm8996.o -# for MSMCOBALT sound card driver -snd-soc-msmcobalt-objs := msmcobalt.o -obj-$(CONFIG_SND_SOC_MSMCOBALT) += snd-soc-msmcobalt.o +# for MSM8998 sound card driver +snd-soc-msm8998-objs := msm8998.o +obj-$(CONFIG_SND_SOC_MSM8998) += snd-soc-msm8998.o # for MSMFALCON sound card driver snd-soc-msmfalcon-common-objs := msm-audio-pinctrl.o msmfalcon-common.o @@ -33,4 +33,3 @@ obj-$(CONFIG_SND_SOC_INT_CODEC) += snd-soc-int-codec.o snd-soc-ext-codec-objs := msmfalcon-external.o msmfalcon-ext-dai-links.o obj-$(CONFIG_SND_SOC_EXT_CODEC) += snd-soc-msmfalcon-common.o obj-$(CONFIG_SND_SOC_EXT_CODEC) += snd-soc-ext-codec.o - diff --git a/sound/soc/msm/msmcobalt.c b/sound/soc/msm/msm8998.c index 9c392f3d4ddc..94a529acaff7 100644 --- a/sound/soc/msm/msmcobalt.c +++ b/sound/soc/msm/msm8998.c @@ -40,9 +40,9 @@ #include "../codecs/wcd934x/wcd934x-mbhc.h" #include "../codecs/wsa881x.h" -#define DRV_NAME "msmcobalt-asoc-snd" +#define DRV_NAME "msm8998-asoc-snd" -#define __CHIPSET__ "MSMCOBALT " +#define __CHIPSET__ "MSM8998 " #define MSM_DAILINK_NAME(name) (__CHIPSET__#name) #define SAMPLING_RATE_8KHZ 8000 @@ -3108,7 +3108,7 @@ err_fail: return ret; } -static int msmcobalt_notifier_service_cb(struct notifier_block *this, +static int msm8998_notifier_service_cb(struct notifier_block *this, unsigned long opcode, void *ptr) { int ret; @@ -3166,7 +3166,7 @@ done: } static struct notifier_block service_nb = { - .notifier_call = msmcobalt_notifier_service_cb, + .notifier_call = msm8998_notifier_service_cb, .priority = -INT_MAX, }; @@ -5824,12 +5824,12 @@ err_pcm_runtime: } struct snd_soc_card snd_soc_card_tasha_msm = { - .name = "msmcobalt-tasha-snd-card", + .name = "msm8998-tasha-snd-card", .late_probe = msm_snd_card_late_probe, }; struct snd_soc_card snd_soc_card_tavil_msm = { - .name = "msmcobalt-tavil-snd-card", + .name = "msm8998-tavil-snd-card", .late_probe = msm_snd_card_tavil_late_probe, }; @@ -6089,15 +6089,15 @@ static struct snd_soc_dai_link msm_stub_dai_links[ ARRAY_SIZE(msm_stub_be_dai_links)]; struct snd_soc_card snd_soc_card_stub_msm = { - .name = "msmcobalt-stub-snd-card", + .name = "msm8998-stub-snd-card", }; -static const struct of_device_id msmcobalt_asoc_machine_of_match[] = { - { .compatible = "qcom,msmcobalt-asoc-snd-tasha", +static const struct of_device_id msm8998_asoc_machine_of_match[] = { + { .compatible = "qcom,msm8998-asoc-snd-tasha", .data = "tasha_codec"}, - { .compatible = "qcom,msmcobalt-asoc-snd-tavil", + { .compatible = "qcom,msm8998-asoc-snd-tavil", .data = "tavil_codec"}, - { .compatible = "qcom,msmcobalt-asoc-snd-stub", + { .compatible = "qcom,msm8998-asoc-snd-stub", .data = "stub_codec"}, {}, }; @@ -6110,7 +6110,7 @@ static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev) int total_links; const struct of_device_id *match; - match = of_match_node(msmcobalt_asoc_machine_of_match, dev->of_node); + match = of_match_node(msm8998_asoc_machine_of_match, dev->of_node); if (!match) { dev_err(dev, "%s: No DT match found for sound card\n", __func__); @@ -6590,7 +6590,7 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) goto err; } - match = of_match_node(msmcobalt_asoc_machine_of_match, + match = of_match_node(msm8998_asoc_machine_of_match, pdev->dev.of_node); if (!match) { dev_err(&pdev->dev, "%s: no matched codec is found.\n", @@ -6710,7 +6710,7 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) i2s_auxpcm_init(pdev); is_initial_boot = true; - ret = audio_notifier_register("msmcobalt", AUDIO_NOTIFIER_ADSP_DOMAIN, + ret = audio_notifier_register("msm8998", AUDIO_NOTIFIER_ADSP_DOMAIN, &service_nb); if (ret < 0) pr_err("%s: Audio notifier register failed ret = %d\n", @@ -6755,19 +6755,19 @@ static int msm_asoc_machine_remove(struct platform_device *pdev) return 0; } -static struct platform_driver msmcobalt_asoc_machine_driver = { +static struct platform_driver msm8998_asoc_machine_driver = { .driver = { .name = DRV_NAME, .owner = THIS_MODULE, .pm = &snd_soc_pm_ops, - .of_match_table = msmcobalt_asoc_machine_of_match, + .of_match_table = msm8998_asoc_machine_of_match, }, .probe = msm_asoc_machine_probe, .remove = msm_asoc_machine_remove, }; -module_platform_driver(msmcobalt_asoc_machine_driver); +module_platform_driver(msm8998_asoc_machine_driver); MODULE_DESCRIPTION("ALSA SoC msm"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:" DRV_NAME); -MODULE_DEVICE_TABLE(of, msmcobalt_asoc_machine_of_match); +MODULE_DEVICE_TABLE(of, msm8998_asoc_machine_of_match); diff --git a/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c b/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c index 718f7017342b..f1f2fd908eca 100644 --- a/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c +++ b/sound/soc/msm/qdsp6v2/msm-dai-q6-v2.c @@ -2645,8 +2645,10 @@ static struct snd_soc_dai_driver msm_dai_q6_usb_rx_dai = { .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | - SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_384000, + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | + SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_352800 | + SNDRV_PCM_RATE_384000, .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, @@ -2667,8 +2669,10 @@ static struct snd_soc_dai_driver msm_dai_q6_usb_tx_dai = { .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | - SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_384000, + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | + SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | + SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_352800 | + SNDRV_PCM_RATE_384000, .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, |